From nobody Mon Feb 9 02:28:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85904+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85904+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1642758628; cv=none; d=zohomail.com; s=zohoarc; b=ceEakJONCmlapMuQBTCKSKa3IIM7TRajWjUh6phYqB9yu92IEUGKOaunWpeT3MzEnjlnrH2piLbUSPkO/V5Ai6yz75pNJE1xOzM07kHqRHxA7TH7tnDOCC2pEZwpul5nPYZQDNi8PJ7Hq10tODYfFBv4RTFTgrmM8VgULvSLkck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642758628; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qwZfto/kW5SoCTRstxTqb3hgBjU1t2akHICLTuDC3vw=; b=FdtG+gxSQgPjvxNRL8jqXativIkFE5K7a6ZhO/Z9IyfZuSvBKobj2jw1OvXevyum7wFzwOb2CDipB8wKYrSg4G1g/YtVt5nModUcTwZGXTJwzE8MRc+/nOdR+q3DWeedARGsxzdZ62iJf4QMvduBQ316lrzdw19QKUCF8QMJJE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85904+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642758628251438.02119968916986; Fri, 21 Jan 2022 01:50:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6t2VYY1788612xp87qwJs9lb; Fri, 21 Jan 2022 01:50:27 -0800 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.9807.1642758626327755440 for ; Fri, 21 Jan 2022 01:50:26 -0800 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20L7vsH9027461; Fri, 21 Jan 2022 09:50:26 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3dqrw50wpt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 09:50:25 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 156F54F; Fri, 21 Jan 2022 09:50:25 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id ECDCD48; Fri, 21 Jan 2022 09:50:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 04/14] RISC-V/PlatformPkg: Address Spelling check errors. Date: Fri, 21 Jan 2022 16:48:38 +0800 Message-Id: <20220121084848.7695-5-abner.chang@hpe.com> In-Reply-To: <20220121084848.7695-1-abner.chang@hpe.com> References: <20220121084848.7695-1-abner.chang@hpe.com> X-Proofpoint-GUID: zqvUQmwyQL1wnAU6VnTL5yrUCf17paJm X-Proofpoint-ORIG-GUID: zqvUQmwyQL1wnAU6VnTL5yrUCf17paJm X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: FEmBuY6uXDeUceUWMznzJXSmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642758627; bh=WAKIcB5/UV/Ux17ZxDlOpFH4rbUNanNpRj/y3Wv9rrA=; h=Cc:Date:From:Reply-To:Subject:To; b=ZGnp57Nv2qLZiOQ8FLBQycrvFLZe+PkL3MNdB7GABJw6Mb/Qn3IBnedcwM3PrUVHRxl 2rFe9lYPtV11hms9yuIJOYDT5ZnrrXZb9sPbisJ9gPxNyV9upbQ7ZkRpmE8Iuj7ft3zFX x2MDNYCXGjhfs2tpBVF8fZ0oDmUAhmaktLs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642758629597100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++-- .../FirmwareContextProcessorSpecificLib.inf | 2 +- .../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +- .../Library/FirmwareContextProcessorSpecificLib.h | 4 ++-- .../RISC-V/PlatformPkg/Universal/Sec/SecMain.h | 4 ++-- .../Edk2OpensbiPlatformWrapperLib.c | 10 +++++----- .../FirmwareContextProcessorSpecificLib.c | 8 ++++---- .../PlatformBootManagerLib/PlatformBootManager.c | 4 ++-- .../Universal/Pei/PlatformPei/Platform.c | 4 ++-- .../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 10 +++++----- Platform/RISC-V/PlatformPkg/Readme.md | 14 +++++++------- .../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 8 ++++---- 12 files changed, 37 insertions(+), 37 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 53d424c901..f3217e4a05 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -1,7 +1,7 @@ ## @file RiscVPlatformPkg.dec # This Package provides UEFI RISC-V platform modules and libraries. # -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +20,7 @@ [LibraryClasses] FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProce= ssorSpecificLib.h RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryIn= itLib.h - Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h + Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapper= Lib.h =20 [Guids] gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/Platfor= mPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSp= ecificLib.inf index ea2550ce2c..8b645e2c5c 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.inf @@ -1,6 +1,6 @@ ## @file # This is the library module of RISC-V EDK2 OpenSBI Firmware Context -# Processor Specific hwardware information. +# Processor Specific hardware information. # # Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All= rights reserved.
# diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf b/Pl= atform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf index dc3a685d58..2579dafe86 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf @@ -1,7 +1,7 @@ ## @file # The FDT Peim driver is used to pass the device tree to DXE phase. # -# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All righ= ts reserved.
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextPro= cessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareC= ontextProcessorSpecificLib.h index 3920c61155..0eec62033b 100644 --- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h +++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h @@ -1,7 +1,7 @@ /** @file Firmware Context Processor-specific common library =20 - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -18,7 +18,7 @@ =20 @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core - @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core. + @param ParentProcessorUid Unique ID of physical processor whi= ch owns this core. @param CoreGuid Pointer to GUID of core @param HartId Hart ID of this core. @param IsBootHart This is boot hart or not diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.h index 63a610fbd0..4098bd7d92 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module definitions.. =20 - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -35,7 +35,7 @@ =20 **/ INT32 -SecPostOpenSbiPlatformEarlylInit( +SecPostOpenSbiPlatformEarlyInit( IN BOOLEAN ColdBoot ); =20 diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapper= Lib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/E= dk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c index 2137c6c619..0bd1b44241 100644 --- a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.c @@ -1,7 +1,7 @@ /** @file EDK2 OpenSBI generic platform wrapper library =20 - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -43,7 +43,7 @@ SecSetEdk2FwMemoryRegions ( fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE; Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs); if (Ret !=3D 0) { - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__)); + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n", _= _FUNCTION__)); } =20 // @@ -54,7 +54,7 @@ SecSetEdk2FwMemoryRegions ( fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE; Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs); if (Ret !=3D 0) { - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__)); + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain f= ail\n", __FUNCTION__)); } return Ret; } @@ -66,7 +66,7 @@ SecSetEdk2FwMemoryRegions ( =20 **/ INT32 -SecPostOpenSbiPlatformEarlylInit( +SecPostOpenSbiPlatformEarlyInit( IN BOOLEAN ColdBoot ) { @@ -190,7 +190,7 @@ Edk2OpensbiPlatformEarlyInit ( } } if (ColdBoot) { - return SecPostOpenSbiPlatformEarlylInit(ColdBoot); + return SecPostOpenSbiPlatformEarlyInit(ColdBoot); } return 0; } diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformP= kg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpec= ificLib.c index 143c18d62c..c94f7881c2 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c @@ -1,7 +1,7 @@ /** @file - Common library to build upfirmware context processor-specific information + Common library to build up firmware context processor-specific informati= on =20 - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -28,7 +28,7 @@ =20 @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core - @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core. + @param ParentProcessorUid Unique ID of physical processor whi= ch owns this core. @param CoreGuid Pointer to GUID of core @param HartId Hart ID of this core. @param IsBootHart This is boot hart or not @@ -52,7 +52,7 @@ CommonFirmwareContextHartSpecificInfo ( // // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. // - CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessor= Guid); + CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid, ParentProcesso= rGuid); ProcessorSpecificDataHob->ParentProcessorUid =3D ParentProcessorUid; CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid); ProcessorSpecificDataHob->Context =3D NULL; diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Pla= tformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManage= rLib/PlatformBootManager.c index deaad7d5a1..9ad4ef17db 100644 --- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBo= otManager.c +++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBo= otManager.c @@ -1,7 +1,7 @@ /** @file This file include all platform actions =20 -Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All ri= ghts reserved.
Copyright (c) 2015, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -215,7 +215,7 @@ PlatformBootManagerBeforeConsole ( Signal console ready platform customized event; Run diagnostics like memory testing; Connect certain devices; - Dispatch aditional option roms. + Dispatch additional option roms. **/ VOID EFIAPI diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform= .c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c index 972a429fb9..c28b2ed373 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c @@ -296,7 +296,7 @@ BootModeInitialization ( { EFI_STATUS Status; =20 - if (CheckResumeFromS3 ()) { + if (CheckResumeFromS3) { DEBUG ((DEBUG_INFO, "This is wake from S3\n")); } else { DEBUG ((DEBUG_INFO, "This is normal boot\n")); @@ -357,7 +357,7 @@ InitializePlatform ( MiscInitialization (); Status =3D BuildCoreInformationHob (); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n")); + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n")); ASSERT(FALSE); } return EFI_SUCCESS; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 1fafed2799..7a79eeec2d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -291,7 +291,7 @@ FindPeiCoreImageBase ( /** Find and return Pei Core entry point. =20 - It also find SEC and PEI Core file debug inforamtion. It will report the= m if + It also find SEC and PEI Core file debug information. It will report the= m if remote debug is enabled. =20 @param[in] BootFirmwareVolumePtr The firmware volume pointer to search @@ -516,7 +516,7 @@ LaunchPeiCore ( @param[in] FuncArg1 Arg1 to pass to next phase entry point addres= s. @param[in] NextAddr Entry point of next phase. @param[in] NextMode Privilege mode of next phase. - @param[in] NextVirt Next phase is in virtualiztion. + @param[in] NextVirt Next phase is in virtualization. =20 **/ VOID @@ -600,7 +600,7 @@ Edk2PlatformHartIndex2Id ( } =20 /** - This function initilizes hart specific information and SBI. + This function initializes hart specific information and SBI. For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL. For others, it goes to initial SBI and halt. =20 @@ -658,9 +658,9 @@ SecCoreStartUpWithStack( HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode; =20 // - // Hook platorm_ops with EDK2 one. Thus we can have interface + // Hook platform_ops with EDK2 one. Thus we can have interface // call out to OEM EDK2 platform code in M-mode before switching - // to S-mode in opensbo init. + // to S-mode in opensbi init. // ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 66fba15544..5a344a864a 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -26,16 +26,16 @@ differently from the default settings according to the = OEM platform design. to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib***= provides the RISC-V SBI implementation and initialize the OpenSBI boot flow. SEC module is also li= nked with below libraries, - edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that prov= ides the generic RISC-V platform initialization code. -- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) lib= rary which is provided by the RISC-V +- edk2 [RiscVSpecialPlatformLib](#RiscVSpecialPlatformLib-library) library= which is provided by the RISC-V platform vendor for the platform-specific initialization. The underlying i= mplementation of above two edk2 libraries are from OpenSBI project. edk2 libraries are introduced as the wrapper lib= raries that separates and organizes OpenSBI core and platform code based on= edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***R= iscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://gi= thub.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) = while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V = PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platfo= rm/RISC-V/PlatformPkg). -- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is = provided by the platform vendor and located under edk2 RISC-V platform-spec= ific folder. +- edk2 [RiscVSpecialPlatformLib](#riscvspecialplatformlib) library is prov= ided by the platform vendor and located under edk2 RISC-V platform-specific= folder. =20 ##### OpenSbiPlatformLib Library [Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams) > ***OpenSbiPlatformLib*** provides the generic RISC-V platform initializa= tion code. Platform vendor can just utilize this library if they don't have= additional requirements on the platform initialization. =20 -##### RiscVSpecifialPlatformLib Library +##### RiscVSpecialPlatformLib Library [Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams) > The major use case of this library is to facilitate the interfaces for p= latform vendors to provide the special platform initialization based on the generic platform initialization libra= ry. @@ -57,7 +57,7 @@ privilege according to the PCD. =20 #### PEI Phase SEC module hands off the boot process to PEI core in the privilege configu= red by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is= forced to S-mode)*. PEI and later phases are allowed to executed in M-mode -if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mo= de) for the virtualization. RISC-V edk2 port provides its own instance ***P= eiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-= port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppili= b-library) in order to support the S-mode PEI phase. PEI core requires [Ris= cVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve= the information of RISC-V HARTs and platform (e.g. FDT) configurations tha= t built up in SEC phase. ***PeiServicePointer*** is also maintained in the = ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved= by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library)= library. +if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mo= de) for the virtualization. RISC-V edk2 port provides its own instance ***P= eiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-= port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppili= b-library) in order to support the S-mode PEI phase. PEI core requires [Ris= cVFirmwareContextLib](#riscvfirmwarecontextlib-library) library to retrieve= the information of RISC-V HARTs and platform (e.g. FDT) configurations tha= t built up in SEC phase. ***PeiServicePointer*** is also maintained in the = ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved= by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library)= library. =20 ##### PlatformSecPpiLib Library [Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams) @@ -178,7 +178,7 @@ The PCD settings regard to EFI Variable |PcdVariableFdSize| The EFI variable firmware device size| |PcdVariableFdBlockSize| The block size of EFI variable firmware device| |PcdPlatformFlashNvStorageVariableBase| EFI variable base address within f= irmware device| -|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance worksapce (FTW) within firmware device| +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance workspace (FTW) within firmware device| |PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable s= pare FTW within firmware device| =20 ### RISC-V Physical Memory Protection (PMP) Region Settings @@ -190,7 +190,7 @@ Below PCDs could be set in platform FDF file. |PcdRootFirmwareDomainSize| The size of root firmware domain|-|-| |PcdFirmwareDomainBaseAddress| The starting address of firmware domain tha= t can be accessed and executed in S-mode|Full access|Readable and Executabl= e| |PcdFirmwareDomainSize| The size of firmware domain|-|-| -|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variabl= e region that can be accessed in S-mode|Full access|Readale and Writable| +|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variabl= e region that can be accessed in S-mode|Full access|Readable and Writable| |PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-= |-| =20 ### RISC-V Processor HART Settings @@ -198,7 +198,7 @@ Below PCDs could be set in platform FDF file. | **PCD name** |**Usage**| |--------------|---------| |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| -|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| +|PcdBootHartId| The ID of RISC-V HART to execute main firmware code and bo= ot system to OS| |PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value| |PcdBootableHartIndexToId| if PcdBootableHartNumber =3D=3D 0, hart_index2i= d is built from Device Tree, otherwise this is an array of HART index to HA= RT ID| =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 0fc7817665..a96dd9474b 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -67,7 +67,7 @@ skip_fw_init: * DTB for this processor. We allocate the * scratch buffer according to this number. */ - la a4, _pysical_hart_count + la a4, _physical_hart_count sd s7, (a4) =20 li s8, FixedPcdGet32 (PcdOpenSbiStackSize) @@ -227,7 +227,7 @@ _start_warm: csrr a0, CSR_MHARTID j _uninitialized_hart_wait 4: - la a5, _pysical_hart_count + la a5, _physical_hart_count ld s7, (a5) /* Find the scratch space for this hart * @@ -294,7 +294,7 @@ _start_warm: .section .data, "aw" _boot_hart_done: RISCV_PTR 0 -_pysical_hart_count: +_physical_hart_count: RISCV_PTR 0 =20 .align 3 @@ -323,7 +323,7 @@ _hartid_to_scratch: lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) #endif =20 - la s1, _pysical_hart_count /* total HART count */ + la s1, _physical_hart_count /* total HART count */ ld s2, (s1) mul s2, s2, s0 li s1, FixedPcdGet32 (PcdScratchRamBase) --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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