From nobody Thu Apr 25 17:24:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85283+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85283+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1641378926; cv=none; d=zohomail.com; s=zohoarc; b=NEKbfNZbcpE9ArByzxIWxCAlVf1/a1Xp+202Vy8uzySVtSsefjM/QOYfVsWzBHSgoE3ISkL0xIqC6/GQgOKq43frBmuIAnIff2ivUNv2MBeouRKYFUI28YwTarst6Y9V0lxCnQGlW77a98H21ct8el6wi+bn/MuHQz3B5VOKP5s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1641378926; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=xzt0j+JW6DncUetVvz/G7cLeKgO/2068nP2Zl8gdQWA=; b=NnYAt++NdQStK4a/coMd+rkDg6uwWmZVHQXi8BXn79JdaHub4KkVlgV+NeJtct1FPyfBcWvterZJaT01iaElYFN0gcLOmuGhQmsOXZZvTWytVJh2m4IZ0LvUyC4I8OFC5Doy+NUxgcAXaBAn4n5XuGgC6ZnBgWRfioM+Fl4N9lM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85283+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164137892598590.70225656219247; Wed, 5 Jan 2022 02:35:25 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id nC9pYY1788612xXwIp1STje7; Wed, 05 Jan 2022 02:35:25 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.5478.1641378924460110104 for ; Wed, 05 Jan 2022 02:35:24 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10217"; a="328759491" X-IronPort-AV: E=Sophos;i="5.88,263,1635231600"; d="scan'208";a="328759491" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2022 02:35:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,263,1635231600"; d="scan'208";a="668052689" X-Received: from chumaggi-desk.gar.corp.intel.com ([10.5.215.19]) by fmsmga001.fm.intel.com with ESMTP; 05 Jan 2022 02:35:22 -0800 From: "Maggie Chu" To: devel@edk2.groups.io Cc: Liming Gao , Michael D Kinney , Zhiguang Liu Subject: [edk2-devel] [PATCH v3] MdePkg: Add registers of boot partition feature Date: Wed, 5 Jan 2022 18:35:06 +0800 Message-Id: <20220105103506.2056-1-maggie.chu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,maggie.chu@intel.com X-Gm-Message-State: UCaEwoAu45i4CTHjDxr1mpUlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1641378925; bh=B2Bf/2EgLDAPoZ4vu7WZx1uyzaYF2L/R8W3/G9hyRrQ=; h=Cc:Date:From:Reply-To:Subject:To; b=dXQELEYDKKh538xtLceNxY0jqCUium+HfU1w5D3jfjXXnvf8skcwaaTyiqScMworuqx XT5azCEqceHSKR98NluHiva0NVm9984A548I4SaLvdLzLSs3I/M6CPCAgHFkHuz6e/I5W gcATc4YCiXGRJWwHsDj1aVb0KJz1Dfy8FOY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1641378928262100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3757 Add registers of boot partition feature which defined in NVM Express 1.4 Sp= ec Cc: Liming Gao Cc: Michael D Kinney Cc: Zhiguang Liu Signed-off-by: Maggie Chu --- MdePkg/Include/IndustryStandard/Nvme.h | 108 ++++++++++++++++++++----- 1 file changed, 89 insertions(+), 19 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/Indust= ryStandard/Nvme.h index 7d4aee9dc8..4a1d92c45d 100644 --- a/MdePkg/Include/IndustryStandard/Nvme.h +++ b/MdePkg/Include/IndustryStandard/Nvme.h @@ -2,11 +2,12 @@ Definitions based on NVMe spec. version 1.1. =20 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: NVMe Specification 1.1 + NVMe Specification 1.4 =20 **/ =20 @@ -18,18 +19,21 @@ // // controller register offsets // -#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities -#define NVME_VER_OFFSET 0x0008 // Version -#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set -#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear -#define NVME_CC_OFFSET 0x0014 // Controller Configuration -#define NVME_CSTS_OFFSET 0x001c // Controller Status -#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset -#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes -#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Ad= dress -#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Ad= dress -#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tai= l Doorbell -#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Hea= d Doorbell +#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities +#define NVME_VER_OFFSET 0x0008 // Version +#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set +#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear +#define NVME_CC_OFFSET 0x0014 // Controller Configuration +#define NVME_CSTS_OFFSET 0x001c // Controller Status +#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset +#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes +#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base A= ddress +#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base A= ddress +#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information +#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select +#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer = Location +#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Ta= il Doorbell +#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) He= ad Doorbell =20 // // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD)) @@ -51,11 +55,14 @@ typedef struct { UINT8 To; // Timeout UINT16 Dstrd : 4; UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS - UINT16 Css : 4; // Command Sets Supported - Bit 37 - UINT16 Rsvd3 : 7; + UINT16 Css : 8; // Command Sets Supported - Bit 37 + UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4 + UINT16 Rsvd3 : 2; UINT8 Mpsmin : 4; UINT8 Mpsmax : 4; - UINT8 Rsvd4; + UINT8 Pmrs : 1; + UINT8 Cmbs : 1; + UINT8 Rsvd4 : 6; } NVME_CAP; =20 // @@ -115,7 +122,36 @@ typedef struct { #define NVME_ACQ UINT64 =20 // -// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission= Queue y Tail Doorbell +// 3.1.13 Offset 40h: BPINFO - Boot Partition Information +// +typedef struct { + UINT32 Bpsz : 15; // Boot Partition Size + UINT32 Rsvd1 : 9; + UINT32 Brs : 2; // Boot Read Status + UINT32 Rsvd2 : 5; + UINT32 Abpid : 1; // Active Boot Partition ID +} NVME_BPINFO; + +// +// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select +// +typedef struct { + UINT32 Bprsz : 10; // Boot Partition Read Size + UINT32 Bprof : 20; // Boot Partition Read Offset + UINT32 Rsvd1 : 1; + UINT32 Bpid : 1; // Boot Partition Identifier +} NVME_BPRSEL; + +// +// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optio= nal) +// +typedef struct { + UINT64 Rsvd1 : 12; + UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address +} NVME_BPMBL; + +// +// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission= Queue y Tail Doorbell // typedef struct { UINT16 Sqt; @@ -353,7 +389,7 @@ typedef struct { UINT8 Avscc; /* Admin Vendor Specific Command Configurati= on */ UINT8 Apsta; /* Autonomous Power State Transition Attribu= tes */ // - // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec + // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec // UINT16 Wctemp; /* Warning Composite Temperature Thres= hold */ UINT16 Cctemp; /* Critical Composite Temperature Thre= shold */ @@ -361,7 +397,12 @@ typedef struct { UINT32 Hmpre; /* Host Memory Buffer Preferred Size */ UINT32 Hmmin; /* Host Memory Buffer Minimum Size */ UINT8 Tnvmcap[16]; /* Total NVM Capacity */ - UINT8 Rsvd2[216]; /* Reserved as of NVM Express */ + UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */ + UINT32 Rpmbs; /* Replay Protected Memory Block Suppo= rt */ + UINT16 Edstt; /* Extended Device Self-test Time */ + UINT8 Dsto; /* Device Self-test Options */ + UINT8 Fwug; /* Firmware Update Granularity */ + UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec= */ // // NVM Command Set Attributes // @@ -433,6 +474,34 @@ typedef struct { UINT8 VendorData[3712]; /* Vendor specific data */ } NVME_ADMIN_NAMESPACE_DATA; =20 +// +// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Sp= ec +// +typedef struct { + UINT8 Bppe; /* Boot Partition Protection Enable */ + UINT8 Bpl; /* Boot Partition Lock */ + UINT8 Nwpac; /* Namespace Write Protection Authentication Contro= l */ + UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */ +} NVME_RPMB_CONFIGURATION_DATA; + +#define RPMB_FRAME_STUFF_BYTES 223 + +// +// RPMB Data Frame as of Nvm Express 1.4 Spec +// +typedef struct { + UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */ + /* [222:222-(N-1)] Authentica= tion Key or Message Authentication Code (MAC) */ + UINT8 Rpmbt; /* RPMB Target */ + UINT64 Nonce[2]; + UINT32 Wcounter; /* Write Counter */ + UINT32 Address; /* Starting address of data t= o be programmed to or read from the RPMB. */ + UINT32 Scount; /* Sector Count */ + UINT16 Result; + UINT16 Rpmessage; /* Request/Response Message */ + // UINT8 *Data; /* Data to be written or read= by signed access where M =3D 512 * Sector Count. */ +} NVME_RPMB_DATA_FRAME; + // // NvmExpress Admin Identify Cmd // @@ -564,6 +633,7 @@ typedef struct { #define LID_ERROR_INFO 0x1 #define LID_SMART_INFO 0x2 #define LID_FW_SLOT_INFO 0x3 + #define LID_BP_INFO 0x15 UINT32 Rsvd1 : 8; UINT32 Numd : 12; /* Number of Dwords */ UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */ --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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