From nobody Sun Sep 7 23:51:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85024+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85024+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1639692515; cv=none; d=zohomail.com; s=zohoarc; b=bFSfAgv0ieCWkcn5zcCtB67hGOHXHf/mWOddMLmn8BKKZHDw4tZcKFW63WHgD4C4RBinOi/h402Z4ueIFsI3wxmWGlJV52m705aYujxmOBY4nKH3tGbtoQo/2EpK/yMaiD+Tsqp/PZljA+xWrRyLnSRJ7OjpRs/uYVFt+9BW/1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639692515; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=JSkqQh1KTSVcGnS7BSr5cNqxMO7mZ1d3nMOxomn9teY=; b=Kz37ncNbyIxeN2L8LpA/BgeT+2VEoyNzrLIlgLZ3BrTfClfBMkz4/IYlzTSjVUnmQRnxmEDKJ5diHr5kxlLcfBcErUUjk+lWYqnT2xQdVUUXLAa5fstud8WBvfzWS+LeK9m8QY5Cj5QYQQRYoXJQJexLyNeIRBnKhmub0xKYdCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85024+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1639692515133652.87037620565; Thu, 16 Dec 2021 14:08:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id MUxzYY1788612x2ON8kDy6LD; Thu, 16 Dec 2021 14:08:34 -0800 X-Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web10.993.1639692514211318164 for ; Thu, 16 Dec 2021 14:08:34 -0800 X-Received: by mail-pf1-f170.google.com with SMTP id z6so519790pfe.7 for ; Thu, 16 Dec 2021 14:08:34 -0800 (PST) X-Gm-Message-State: h4I4NwGHLxtZ5lSXNJVoKNdex1787277AA= X-Google-Smtp-Source: ABdhPJzBu+v9FWHTvL/gYqZfgrqLxzMu0YqIIGId50vReDxI70O8Wgdb9rvEOcbbQjbOcL8OHwT6/Q== X-Received: by 2002:a05:6a00:188e:b0:4a4:f2fd:d7b9 with SMTP id x14-20020a056a00188e00b004a4f2fdd7b9mr15725392pfh.20.1639692513482; Thu, 16 Dec 2021 14:08:33 -0800 (PST) X-Received: from linbox.ba.nuviainc.com ([2601:681:4300:69e:9e7b:efff:fe2b:884c]) by smtp.gmail.com with ESMTPSA id 32sm5982619pgs.48.2021.12.16.14.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 14:08:33 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io, Ard Biesheuvel , Samer El-Haj-Mahmoud , Leif Lindholm , Sami Mujawar , Wenyi Xie , Peng Xie , Ling Jia , Yiqi Shu , Nhi Pham , Vu Nguyen , Thang Nguyen , Chuong Tran , Pete Batard , Masami Hiramatsu , Graeme Gregory , Radoslaw Biernacki , Marcin Wojtas Cc: Rebecca Cran Subject: [edk2-devel] [PATCH v2 12/17] Silicon/AMD: Update Styx code to work with changes ARM_CORE_INFO struct Date: Thu, 16 Dec 2021 15:07:55 -0700 Message-Id: <20211216220800.9628-13-rebecca@nuviainc.com> In-Reply-To: <20211216220800.9628-1-rebecca@nuviainc.com> References: <20211216220800.9628-1-rebecca@nuviainc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@nuviainc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1639692514; bh=2fVZkcwj69T2ccNoDxsnlbLKvmOR3x40EtLPuRXgWT8=; h=Cc:Date:From:Reply-To:Subject:To; b=b6X/lftr3DWptK0XH7Fjh0LBVZtntE88LbpsIrZyKapvhi/hmJsUCYZ+NIo57k7MRNC eSrYpKZSb0Lp0LRyHUs2kAePwcHM5TZEPY88a3RJLC47miyWwPt/1GYqA90gzEgkXYgKo 3mCNjaHJV3w0WMRiowW/UmcOReG1Fs8U/BQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1639692515852100002 Content-Type: text/plain; charset="utf-8" The ARM_CORE_INFO struct has been updated so the MPIDR is now a single field instead of separate cluster/core fields. Update the Styx code in AcpiPlatformDxe, PlatInitPei and StyxDtbLoaderLib. Signed-off-by: Rebecca Cran --- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +-- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 8 +++---- Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 22 ++++++++= +----------- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Sili= con/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 7c267542db19..5f059110ff0c 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -100,8 +100,7 @@ EnableAvailableCores ( =20 while (CoreCount--) { for (Index =3D 0; Index < MAX_CORES; Index++) { - if (GicC[Index].MPIDR =3D=3D GET_MPID (ArmCoreInfoTable->ClusterId, - ArmCoreInfoTable->CoreId)) { + if (GicC[Index].MPIDR =3D=3D ArmCoreInfoTable->Mpidr) { GicC[Index].Flags |=3D EFI_ACPI_5_1_GIC_ENABLED; break; } diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/A= MD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 3f359ffbd2d8..45490aa33c5a 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -166,12 +166,12 @@ PlatInitPeiEntryPoint ( ASSERT (CpuResetInfo.CoreStatus.Status !=3D CPU_CORE_DISABLED); ASSERT (CpuResetInfo.CoreStatus.Status !=3D CPU_CORE_UNDEFINED); =20 - mAmdMpCoreInfoTable[Index].ClusterId =3D CpuResetInfo.CoreStatus.Clu= sterId; - mAmdMpCoreInfoTable[Index].CoreId =3D CpuResetInfo.CoreStatus.CoreId; + mAmdMpCoreInfoTable[Index].Mpidr =3D GET_MPID (CpuResetInfo.CoreStat= us.ClusterId, + CpuResetInfo.CoreStatus.CoreId); =20 DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId =3D %d CoreId =3D %d\n", - Index, mAmdMpCoreInfoTable[Index].ClusterId, - mAmdMpCoreInfoTable[Index].CoreId)); + Index, GET_MPIDR_AFF1 (mAmdMpCoreInfoTable[Index].Mpidr), + GET_MPIDR_AFF0 (mAmdMpCoreInfoTable[Index].Mpidr))); =20 // Next core in Table ++Index; diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b= /Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 75e529021d09..178fb5698504 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -50,7 +50,7 @@ ClusterInRange ( ) { do { - if (ClusterId =3D=3D ArmCoreInfoTable[LowIndex].ClusterId) + if (ClusterId =3D=3D GET_MPIDR_AFF1 (ArmCoreInfoTable[LowIndex].Mpidr)) return TRUE; } while (++LowIndex <=3D HighIndex); =20 @@ -70,7 +70,7 @@ NumberOfCoresInCluster ( =20 Cores =3D 0; for (Index =3D 0; Index < NumberOfEntries; ++Index) { - if (ClusterId =3D=3D ArmCoreInfoTable[Index].ClusterId) + if (ClusterId =3D=3D GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr)) ++Cores; } =20 @@ -92,7 +92,7 @@ NumberOfClustersInTable ( Cores =3D NumberOfEntries; while (Cores) { ++Clusters; - ClusterId =3D ArmCoreInfoTable[Index].ClusterId; + ClusterId =3D GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr); Cores -=3D NumberOfCoresInCluster (ArmCoreInfoTable, NumberOfEntries, ClusterId); @@ -100,7 +100,7 @@ NumberOfClustersInTable ( do { ++Index; } while (ClusterInRange (ArmCoreInfoTable, - ArmCoreInfoTable[Index].ClusterId, + GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mp= idr), 0, Index-1)); } } @@ -402,8 +402,7 @@ PrepareFdt ( =20 fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci"); =20 - MpId =3D (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, - ArmCoreInfoTable[Index].CoreId); + MpId =3D ArmCoreInfoTable[Index].Mpidr; MpId =3D cpu_to_fdt64 (MpId); fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId)); fdt_setprop (Fdt, CpuNode, "compatible", mCpuCompatible, @@ -417,7 +416,7 @@ PrepareFdt ( fdt_setprop_cell (Fdt, CpuNode, "d-cache-line-size", 64); fdt_setprop_cell (Fdt, CpuNode, "d-cache-sets", 256); fdt_setprop_cell (Fdt, CpuNode, "l2-cache", - L2Phandle[ArmCoreInfoTable[Index].ClusterId]); + L2Phandle[GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr)]); } =20 // Create /cpu-map node @@ -435,7 +434,7 @@ PrepareFdt ( return EFI_INVALID_PARAMETER; } =20 - ClusterId =3D ArmCoreInfoTable[ClusterIndex].ClusterId; + ClusterId =3D GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterIndex].Mpidr); CoreIndex =3D ClusterIndex; CoresInCluster =3D NumberOfCoresInCluster (ArmCoreInfoTable, ArmCoreCount, @@ -454,7 +453,7 @@ PrepareFdt ( if (CoresInCluster) { do { --CoreIndex; - } while (ClusterId !=3D ArmCoreInfoTable[CoreIndex].ClusterId); + } while (ClusterId !=3D GET_MPIDR_AFF1 (ArmCoreInfoTable[CoreInd= ex].Mpidr)); } } =20 @@ -463,7 +462,7 @@ PrepareFdt ( do { --ClusterIndex; } while (ClusterInRange (ArmCoreInfoTable, - ArmCoreInfoTable[ClusterIndex].ClusterId, + GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterI= ndex].Mpidr), ClusterIndex + 1, ArmCoreCount - 1)); } @@ -481,8 +480,7 @@ PrepareFdt ( =20 // append PMU interrupts for (Index =3D 0; Index < ArmCoreCount; Index++) { - MpId =3D (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, - ArmCoreInfoTable[Index].CoreId); + MpId =3D (UINTN)ArmCoreInfoTable[Index].Mpidr; =20 Status =3D AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.I= ntId); if (EFI_ERROR (Status)) { --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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