From nobody Tue Feb 10 02:49:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+84809+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84809+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1639489323; cv=none; d=zohomail.com; s=zohoarc; b=fgsG4J87KvjnpO2Ez2TH/aV0v69/NR/rJUHPf4xwKcGHH0K9GDJ4+KyflL5h9t5TRow+L043K8/obc7ZgM0T93ZnS7Q+cqjd+g+ChWnwK/MmlYmOxoWwbExoCjXS4B9UIrIPCjSbzo8XheTsKyNqVws0MOwvkDn0BeujS1tgses= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639489323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=aJ2PEP6vA978zk/AgpfJlLE6M3VRj6d/18JiHNfgHHE=; b=RSuK6yzhZH82jeXnSpsUxVFPA6QpzDgnHSa1weH8nN/N/kkdi/jxhAJI6jnRbD06q7ax0FScD5wL0nEvLgQ34vtMp0F8gjTRFNuhIGw+P9lBXNoQTroV38KaaoyPx3MRbm1vTvtvHg29sASYHj1g/m61M8yBJ2hOsz7f74j+4M4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84809+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1639489323172373.11524171643555; Tue, 14 Dec 2021 05:42:03 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3VlTYY1788612xMyjOOZHKjK; Tue, 14 Dec 2021 05:42:02 -0800 X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web08.25742.1639489321528370744 for ; Tue, 14 Dec 2021 05:42:01 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10197"; a="218993611" X-IronPort-AV: E=Sophos;i="5.88,205,1635231600"; d="scan'208";a="218993611" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2021 05:42:00 -0800 X-IronPort-AV: E=Sophos;i="5.88,205,1635231600"; d="scan'208";a="465094146" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.115]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2021 05:41:57 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH 05/10] OvmfPkg: Add SecPlatformLibQemuTdx Date: Tue, 14 Dec 2021 21:41:21 +0800 Message-Id: <20211214134126.869-6-min.m.xu@intel.com> In-Reply-To: <20211214134126.869-1-min.m.xu@intel.com> References: <20211214134126.869-1-min.m.xu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: lohzHDNuIqlCq1TlVSTUjaB7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1639489322; bh=OPoXLf93xbCyrIY6DEp5KcViYwd1SONlE0AZb1XH3TI=; h=Cc:Date:From:Reply-To:Subject:To; b=X3MA31/fMwyTZr6StkGV2WT9pur09j/fiAO2hMkxiyKF4aSoGNPBQvILH9dtQt1m01/ +d1qHscN8LTkIwiN6gq5XEizbKoyuCCQQrZKzMexmhWWFzWjt9RaZ4XKaRs1y6qLYDYoF xBPexm71RRaPFDNUSUZ0XEv/+V3kKRquvu4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1639489324002100021 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 SecPlatformLibQemuTdx initialize the platform in Tdx guest. It sets the HostBridgePciDevId in PlatformInfoHob which will be transferred to DXE phase. Another task is to download QEMU configurations via fw_cfg interface. Cc: Michael D Kinney Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/TdxPlatformLib.h | 38 +++ .../IntelTdx/SecPlatformLibQemuTdx/Platform.c | 286 ++++++++++++++++++ .../SecPlatformLibQemuTdx/TdxPlatformLib.inf | 49 +++ OvmfPkg/OvmfPkg.dec | 4 + 4 files changed, 377 insertions(+) create mode 100644 OvmfPkg/Include/Library/TdxPlatformLib.h create mode 100644 OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/Platform.c create mode 100644 OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/TdxPlatformLib.i= nf diff --git a/OvmfPkg/Include/Library/TdxPlatformLib.h b/OvmfPkg/Include/Lib= rary/TdxPlatformLib.h new file mode 100644 index 000000000000..a6118a0edd98 --- /dev/null +++ b/OvmfPkg/Include/Library/TdxPlatformLib.h @@ -0,0 +1,38 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_PLATFORM_LIB_H_ +#define TDX_PLATFORM_LIB_H_ + +#include +#include +#include +#include +#include +#include + +#define FW_CFG_NX_STACK_ITEM "opt/ovmf/PcdSetNxForStack" +#define FW_CFG_SYSTEM_STATE_ITEM "etc/system-states" + +/** + * Perform Platform initialization. + * + * @param PlatformInfoHob Pointer to the PlatformInfo Hob + * @param CfgSysStateDefault Indicate if using the default SysState + * @param CfgNxForStackDefault Indicate if using the default NxForStack + * @return VOID + */ +VOID +EFIAPI +TdxPlatformInitialize ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob, + OUT BOOLEAN *CfgSysStateDefault, + OUT BOOLEAN *CfgNxForStackDefault + ); + +#endif diff --git a/OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/Platform.c b/OvmfPkg/In= telTdx/SecPlatformLibQemuTdx/Platform.c new file mode 100644 index 000000000000..e205db18cd88 --- /dev/null +++ b/OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/Platform.c @@ -0,0 +1,286 @@ +/**@file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Host Bridge DID Address +// +#define HOSTBRIDGE_DID \ + PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET) + +// +// Values we program into the PM base address registers +// +#define PIIX4_PMBA_VALUE 0xB000 +#define ICH9_PMBASE_VALUE 0x0600 + +EFI_STATUS +GetNamedFwCfgBoolean ( + IN CHAR8 *FwCfgFileName, + OUT BOOLEAN *Setting + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + UINT8 Value[3]; + + Status =3D QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FwCfgSize > sizeof Value) { + return EFI_BAD_BUFFER_SIZE; + } + + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (FwCfgSize, Value); + + if ((FwCfgSize =3D=3D 1) || + ((FwCfgSize =3D=3D 2) && (Value[1] =3D=3D '\n')) || + ((FwCfgSize =3D=3D 3) && (Value[1] =3D=3D '\r') && (Value[2] =3D=3D = '\n'))) + { + switch (Value[0]) { + case '0': + case 'n': + case 'N': + *Setting =3D FALSE; + return EFI_SUCCESS; + + case '1': + case 'y': + case 'Y': + *Setting =3D TRUE; + return EFI_SUCCESS; + + default: + break; + } + } + + return EFI_PROTOCOL_ERROR; +} + +VOID +PciExBarInitialization ( + VOID + ) +{ + union { + UINT64 Uint64; + UINT32 Uint32[2]; + } PciExBarBase; + + // + // We only support the 256MB size for the MMCONFIG area: + // 256 buses * 32 devices * 8 functions * 4096 bytes config space. + // + // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea + // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. + // + // Note that (b) also ensures that the minimum address width we have + // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce + // for DXE's page tables to cover the MMCONFIG area. + // + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); + ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); + + // + // Clear the PCIEXBAREN bit first, before programming the high register. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); + + // + // Program the high register. Then program the low register, setting the + // MMCONFIG area size and enabling decoding at once. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); + PciWrite32 ( + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN + ); +} + +VOID +MiscInitialization ( + EFI_HOB_PLATFORM_INFO *PlatformInfoHob, + BOOLEAN *CfgSysStateDefault + ) +{ + RETURN_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + UINTN PmCmd; + UINTN Pmba; + UINT32 PmbaAndVal; + UINT32 PmbaOrVal; + UINTN AcpiCtlReg; + UINT8 AcpiEnBit; + + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Determine platform type and save Host Bridge DID to PCD + // + switch (PlatformInfoHob->HostBridgePciDevId) { + case INTEL_82441_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); + PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; + PmbaOrVal =3D PIIX4_PMBA_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); + AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; + break; + case INTEL_Q35_MCH_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); + PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; + PmbaOrVal =3D ICH9_PMBASE_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); + AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; + break; + default: + DEBUG (( + DEBUG_ERROR, + "%a: Unknown Host Bridge Device ID: 0x%04x\n", + __FUNCTION__, + PlatformInfoHob->HostBridgePciDevId + )); + ASSERT (FALSE); + return; + } + + // + // If the appropriate IOspace enable bit is set, assume the ACPI PMBA + // has been configured and skip the setup here. + // This matches the logic in AcpiTimerLibConstructor (). + // + if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { + // + // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: + // 1. set PMBA + // + PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); + + // + // 2. set PCICMD/IOSE + // + PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); + + // + // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) + // + PciOr8 (AcpiCtlReg, AcpiEnBit); + } + + if (PlatformInfoHob->HostBridgePciDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // Set Root Complex Register Block BAR + // + PciWrite32 ( + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN + ); + + // + // Set PCI Express Register Range Base Address + // + PciExBarInitialization (); + } + + // + // check for overrides + // + Status =3D QemuFwCfgFindFile ("etc/system-states", &FwCfgItem, &FwCfgSiz= e); + if ((Status !=3D RETURN_SUCCESS) || (FwCfgSize !=3D sizeof PlatformInfoH= ob->SystemStates)) { + DEBUG ((DEBUG_INFO, "ACPI using S3/S4 defaults\n")); + *CfgSysStateDefault =3D TRUE; + return; + } + + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (sizeof PlatformInfoHob->SystemStates, PlatformInfoHo= b->SystemStates); +} + +/** + * Perform Platform initialization. + * + * @param PlatformInfoHob Pointer to the PlatformInfo Hob + * @param CfgSysStateDefault Indicate if using the default SysState + * @param CfgNxForStackDefault Indicate if using the default NxForStack + * @return VOID + */ +VOID +EFIAPI +TdxPlatformInitialize ( + EFI_HOB_PLATFORM_INFO *PlatformInfoHob, + BOOLEAN *CfgSysStateDefault, + BOOLEAN *CfgNxForStackDefault + ) +{ + RETURN_STATUS Status; + + PlatformInfoHob->HostBridgePciDevId =3D PciRead16 (HOSTBRIDGE_DID); + + if (PlatformInfoHob->HostBridgePciDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + 0x6000, + 0xa000 + ); + } else { + BuildResourceDescriptorHob ( + EFI_RESOURCE_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + 0xc000, + 0x4000 + ); + } + + MiscInitialization (PlatformInfoHob, CfgSysStateDefault); + + Status =3D GetNamedFwCfgBoolean ("opt/ovmf/PcdSetNxForStack", &PlatformI= nfoHob->SetNxForStack); + if (Status !=3D RETURN_SUCCESS) { + DEBUG ((DEBUG_INFO, "NxForStack using defaults\n")); + *CfgNxForStackDefault =3D TRUE; + } +} diff --git a/OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/TdxPlatformLib.inf b/Ov= mfPkg/IntelTdx/SecPlatformLibQemuTdx/TdxPlatformLib.inf new file mode 100644 index 000000000000..23af0475f035 --- /dev/null +++ b/OvmfPkg/IntelTdx/SecPlatformLibQemuTdx/TdxPlatformLib.inf @@ -0,0 +1,49 @@ +## @file +# +# Tdvf Platform Lib for the QEMU VMM +# +# Copyright (C) 2013, Red Hat, Inc. +# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecPlatformLibQemuTdx + FILE_GUID =3D 44cabe70-fcfb-11ea-8b6e-0800200c9a66 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxPlatformLib|SEC + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + Platform.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec + +[Guids] + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + HobLib + PciLib + QemuFwCfgLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 86138594b83b..3194b02d9d6b 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -117,6 +117,10 @@ # TdxMailboxLib|Include/Library/TdxMailboxLib.h =20 + ## @libraryclass TdxPlatformLib + # + TdxPlatformLib|Include/Library/TdxPlatformLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {= 0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid =3D {0xd3b46f3b, 0xd441, 0x1244, {= 0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#84809): https://edk2.groups.io/g/devel/message/84809 Mute This Topic: https://groups.io/mt/87720798/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-