From nobody Mon Feb 9 10:48:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+84433+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84433+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1638842206; cv=none; d=zohomail.com; s=zohoarc; b=kWuMpKIxsjsPIYSRRZaYMXtpn6LKbtYLwEbYYOaIJU5MKv2soU7VQWY2oB1yuiKgERZAXMlfIJCAFMNs5vENKP1vA1CEpdZRddCZLfPOSsC7DVlYWccW0UFlaF01VombOOdFXzzRaivw7YHaW6M5bMSV0U4lnxI2p8t+ydH1Qik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1638842206; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=5RrVlmlbEl9kTFrkdizzK9xCDrN2Drok47Rm0y4v3kU=; b=WOWzIr53fojjsr5EVjoldJ5yD5/UpXKfsTbopjSpaGRDamNj4zZLCfqE3cjB1T8WesWSmBTGA/L6T5rzbadEIJLk4nQND8PuCC/vdi5BLoA2rAamAaxRFj22DzqHS34aNxQHhj87RD8Ptc4C3ne2Ex4i3m8o9zI4jb6hNw2ExoA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84433+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1638842206616486.0411802806043; Mon, 6 Dec 2021 17:56:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bcKAYY1788612xdCem8Fn9KP; Mon, 06 Dec 2021 17:56:46 -0800 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web09.61336.1638842205325787944 for ; Mon, 06 Dec 2021 17:56:45 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10190"; a="224329354" X-IronPort-AV: E=Sophos;i="5.87,293,1631602800"; d="scan'208";a="224329354" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2021 17:56:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,293,1631602800"; d="scan'208";a="462109540" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga006.jf.intel.com with ESMTP; 06 Dec 2021 17:56:07 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang , Robert Kowalewski Subject: [edk2-devel] [PATCH 2/4] IntelSiliconPkg/VTd: Update VTd register structs Date: Tue, 7 Dec 2021 09:55:34 +0800 Message-Id: <20211207015536.18228-3-w.sheng@intel.com> In-Reply-To: <20211207015536.18228-1-w.sheng@intel.com> References: <20211207015536.18228-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: xwXqajUW1PvDUog5UKEuylfFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1638842206; bh=8AlzxmVVdDCmu98WJ4Sw0HPEECv6GfJAMlfsas5hNmc=; h=Cc:Date:From:Reply-To:Subject:To; b=jJrSZv1pdHeqUA8ZyISY3pGyMGl698yJIBf6kiAEjZb32dbc933KUT5pWOn+KldpXH1 LmwsxbpNb1Wba77NDuQNxNtX4XY7pyjDjgqAxPmtuLUpEp4hvW4ztgz9MBXenkPrn84aH OFa/XD0dJoGhFsMEh38tz45HKliKzD37wJ8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1638842207602100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update VTd register structs accroding to VTd spec ver 3.3 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3765 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski Signed-off-by: Sheng Wei --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +- .../Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 23 +++++++++++---- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 22 ++++++++++++-- .../Feature/VTd/IntelVTdDxe/VtdReg.c | 15 ++++++++-- .../IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 34 +++++++++++++++++-= ---- 5 files changed, 76 insertions(+), 21 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index c3a939c9..87ce9716 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -631,10 +631,8 @@ DumpVtdECapRegs ( DEBUG ((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC)); DEBUG ((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO)); DEBUG ((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV)); - DEBUG ((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS)); DEBUG ((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS)); DEBUG ((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST)); - DEBUG ((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS)); DEBUG ((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID)); DEBUG ((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS)); DEBUG ((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS)); @@ -642,6 +640,7 @@ DumpVtdECapRegs ( DEBUG ((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS)); DEBUG ((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS)); DEBUG ((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS)); + DEBUG ((DEBUG_INFO, " ADMS - 0x%x\n", ECapReg->Bits.ADMS)); } =20 =20 diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Tran= slationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/= TranslationTable.c index 6676b2a9..a309d566 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translation= Table.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translation= Table.c @@ -884,13 +884,26 @@ SetupTranslationTable ( return Status; } =20 - if (VtdUnitInfo->ECapReg.Bits.ECS) { - DEBUG ((DEBUG_INFO, "CreateExtContextEntry - %d\n", Index)); - Status =3D CreateExtContextEntry (VtdUnitInfo); + if (VtdUnitInfo->ECapReg.Bits.SMTS) { + if (VtdUnitInfo->ECapReg.Bits.DEP_24) { + DEBUG ((DEBUG_ERROR,"ECapReg.bit24 is not zero\n")); + ASSERT(FALSE); + Status =3D EFI_UNSUPPORTED; + } else { + Status =3D CreateExtContextEntry (VtdUnitInfo); + } } else { - DEBUG ((DEBUG_INFO, "CreateContextEntry - %d\n", Index)); - Status =3D CreateContextEntry (VtdUnitInfo); + if (VtdUnitInfo->ECapReg.Bits.DEP_24) { + // + // To compatible with pervious VTd engine + // It was ECS(Extended Context Support) bit. + // + Status =3D CreateExtContextEntry (VtdUnitInfo); + } else { + Status =3D CreateContextEntry (VtdUnitInfo); + } } + if (EFI_ERROR (Status)) { return Status; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c index ca5f65a8..48e38d56 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c @@ -382,11 +382,27 @@ SetupTranslationTable ( =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, "CreateContextEntry - %d\n", Index)); - if (mVtdUnitInformation[Index].ECapReg.Bits.ECS) { - Status =3D CreateExtContextEntry (Index); + + if (mVtdUnitInformation[Index].ECapReg.Bits.SMTS) { + if (mVtdUnitInformation[Index].ECapReg.Bits.DEP_24) { + DEBUG ((DEBUG_ERROR,"ECapReg.bit24 is not zero\n")); + ASSERT(FALSE); + Status =3D EFI_UNSUPPORTED; + } else { + Status =3D CreateExtContextEntry (Index); + } } else { - Status =3D CreateContextEntry (Index); + if (mVtdUnitInformation[Index].ECapReg.Bits.DEP_24) { + // + // To compatible with pervious VTd engine + // It was ECS(Extended Context Support) bit. + // + Status =3D CreateExtContextEntry (Index); + } else { + Status =3D CreateContextEntry (Index); + } } + if (EFI_ERROR (Status)) { return Status; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 1ce9c1c0..7a9af56f 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -698,10 +698,8 @@ DumpVtdECapRegs ( DEBUG((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC)); DEBUG((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO)); DEBUG((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV)); - DEBUG((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS)); DEBUG((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS)); DEBUG((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST)); - DEBUG((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS)); DEBUG((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID)); DEBUG((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS)); DEBUG((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS)); @@ -709,6 +707,8 @@ DumpVtdECapRegs ( DEBUG((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS)); DEBUG((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS)); DEBUG((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS)); + DEBUG((DEBUG_INFO, " SMTS - 0x%x\n", ECapReg->Bits.SMTS)); + DEBUG((DEBUG_INFO, " ADMS - 0x%x\n", ECapReg->Bits.ADMS)); } =20 /** @@ -721,12 +721,20 @@ DumpVtdRegs ( IN UINTN VtdIndex ) { + const CHAR8 *TypeName[4] =3D { + "Write", + "Page", + "Read", + "AtomicOp", + }; + UINTN Index; UINT64 Reg64; VTD_FRCD_REG FrcdReg; VTD_CAP_REG CapReg; UINT32 Reg32; VTD_SOURCE_ID SourceId; + UINT32 TypeId; =20 DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex)); =20 @@ -771,7 +779,8 @@ DumpVtdRegs ( DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS= (FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi))); SourceId.Uint16 =3D (UINT16)FrcdReg.Bits.SID; DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits= .Bus, SourceId.Bits.Device, SourceId.Bits.Function)); - DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.B= its.T ? "read" : "write")); + TypeId =3D (FrcdReg.Bits.T1 << 1) | FrcdReg.Bits.T2; + DEBUG((DEBUG_INFO, " Type - %x (%a)\n", TypeId, TypeName[TypeId])= ); DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\= n", FrcdReg.Bits.FR)); } } diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h b= /Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h index a759ca10..32fbdd02 100644 --- a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h @@ -216,6 +216,7 @@ typedef union { #define B_GSTS_REG_RTPS BIT30 #define B_GSTS_REG_TE BIT31 #define R_RTADDR_REG 0x20 +#define V_RTADDR_REG_TTM_ADM (BIT11|BIT10) #define R_CCMD_REG 0x28 #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61) #define V_CCMD_REG_CIRG_GLOBAL BIT61 @@ -334,7 +335,10 @@ typedef union { UINT8 FL1GP:1; // First Level 1-GByte Page Support UINT8 Rsvd_57:2; UINT8 PI:1; // Posted Interrupts Support - UINT8 Rsvd_60:4; + UINT8 FL5LP:1; // First Level 5-level Paging Support + UINT8 Rsvd_61:1; + UINT8 ESIRTPS:1; // Enhanced Set Interrupt Remap Table Pointer= Support + UINT8 ESRTPS:1; // Enhanced Set Root Table Pointer Support } Bits; UINT64 Uint64; } VTD_CAP_REG; @@ -346,7 +350,7 @@ typedef union { UINT8 DT:1; // Device-TLB support UINT8 IR:1; // Interrupt Remapping support UINT8 EIM:1; // Extended Interrupt Mode - UINT8 Rsvd_5:1; + UINT8 DEP_5:1; UINT8 PT:1; // Pass Through UINT8 SC:1; // Snoop Control =20 @@ -354,11 +358,11 @@ typedef union { UINT16 Rsvd_18:2; UINT16 MHMV:4; // Maximum Handle Mask Value =20 - UINT8 ECS:1; // Extended Context Support + UINT8 DEP_24:1; UINT8 MTS:1; // Memory Type Support UINT8 NEST:1; // Nested Translation Support - UINT8 DIS:1; // Deferred Invalidate Support - UINT8 PASID:1; // Process Address Space ID Support + UINT8 Rsvd_27:1; + UINT8 DEP_28:1; UINT8 PRS:1; // Page Request Support UINT8 ERS:1; // Execute Request Support UINT8 SRS:1; // Supervisor Request Support @@ -367,7 +371,20 @@ typedef union { UINT32 NWFS:1; // No Write Flag Support UINT32 EAFS:1; // Extended Accessed Flag Support UINT32 PSS:5; // PASID Size Supported - UINT32 Rsvd_40:24; + UINT32 PASID:1; // Process Address Space ID Support + UINT32 DIT:1; // Device-TLB Invalidation Throttle + UINT32 PDS:1; // Page-request Drain Support + UINT32 SMTS:1; // Scalable Mode Translation Support + UINT32 VCS:1; // Virtual Command Support + UINT32 SLADS:1; // Second-Level Accessed Dirty Support + UINT32 SLTS:1; // Second-level Translation Support + UINT32 FLTS:1; // First-level Translation Support + UINT32 SMPWCS:1; // Scalable-Mode Page-walk Coherency Support + UINT32 RPS:1; // RID-PASID Support + UINT32 Rsvd_50:2; + UINT32 ADMS:1; // Abort DMA Mode Support + UINT32 RPRIVS:1; // RID_PRIV Support + UINT32 Rsvd_54:10; } Bits; UINT64 Uint64; } VTD_ECAP_REG; @@ -379,7 +396,8 @@ typedef union { UINT32 FIHi:32; // FaultInfo =20 UINT32 SID:16; // Source Identifier - UINT32 Rsvd_80:13; + UINT32 Rsvd_80:12; + UINT32 T2:1; // Type bit2 (0: Write/Read, 1: Page/AtomicOp) UINT32 PRIV:1; // Privilege Mode Requested UINT32 EXE:1; // Execute Permission Requested UINT32 PP:1; // PASID Present @@ -387,7 +405,7 @@ typedef union { UINT32 FR:8; // Fault Reason UINT32 PV:20; // PASID Value UINT32 AT:2; // Address Type - UINT32 T:1; // Type (0: Write, 1: Read) + UINT32 T1:1; // Type bit1 (0: Write/Page, 1: Read/AtomicOp) UINT32 F:1; // Fault } Bits; UINT64 Uint64[2]; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#84433): https://edk2.groups.io/g/devel/message/84433 Mute This Topic: https://groups.io/mt/87556764/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-