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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6800 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: fed18503-6d4d-4621-7108-08d9a8d7a90d X-Microsoft-Antispam-Message-Info: wj2lT7OI0nOhHuRT7vWSgbDCt4FDHuVZ3k4qZK2d6JtdkxE40V+X2Zy5w4IPpMgQmEDe1xdwoVBMM1J2RvohA7gzzz+RDaAON+pzDVgrDgkMuyXpuRpDbuZ7WsSR5Mp5OpCO0agwD2OfmEhDrV3wM0GKXiAvrYt/9iiL2Iqx8Mj2jvCnGsGVt4rj3eO3Qc5QVMAxNo+lsqh0LmSrZkhS3Orf7YvE2nfEPtJRqnBU9wKzbNGEPtfssFiLOGZMuQ4c7RuH6CFeNsDcsWsABk9Ta8VXAGeLiA4r+8DUrQWqEZ1ec1Ly19NyEEsxiit+ljd5xqWc9TrRhy06DBULwuFqAWTckY0PkVOU2ZL9OTna9BB5mN7dNdalxjMO7r7Kv+aftgcRZaBdtDWa1GL3AA8X7S+/Q+e8cR3+eCRyWJrRd7v+twg7x6pVGQrO2c6RNPqhd34X6m2NoVrb66rsF7RT3N73uNTrouuUfsMRLPVeOYyvKM6SE5qlOr4JzRRcUMXOtL/ULDarxJROeMB7yq/sD1ZZr4eFiWbA7tgtSCj6CJlMOt744seKkxt9SCWleligxARf9m/3nxfHqN7xjaDQJI1NSsyenIsIhd5WuUNst1eEUM6ENpmR4gtZ/+HIVjBUZGQi1IbdMart058/dI7hjOqomGl6qvHlmolI/MCHOtZs/qI530RsVGufXKgOsf1k2TyjbCYdfHbB1UhYC4jQAg== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2021 08:04:20.2430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9eb6ed6-28bb-429c-ae48-08d9a8d7b1bf X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3198 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: GGSBVNP2DtzFewvvIa12iqJcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1637049865; bh=ps3Nz0PFmz6NfOCt9X2Zfa7rjasiUAvSWRI+Ws1Omx8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=wW1y3u4QBUHWRxUJkqlNwQgWAwQmweXBybYOMj8m7AjGqdGtg1G+INp1mujnOGBTSCm BM97JzoRAOMvVAR1Igl7s6zd9NFubfc94ILtaAWVXlh6hD+n1Xay5Iqcs5EIBv9oXS6NI XlVe2hZOi1Q38zJbfkojDYX0n6od26EQJS0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1637049986672100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the PciExpressLib to enable CCIX port as PCIe root host by validating the PCIe addresses and introducing corresponding PCD entries. Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e Signed-off-by: Deepak Pandey Signed-off-by: Khasim Syed Mohammed --- .../PciExpressLib.c | 127 ++++++++++++------ .../PciExpressLib.inf | 7 +- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +- 3 files changed, 94 insertions(+), 45 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/P= ciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressL= ib/PciExpressLib.c index bb0246b4a9..3abe0a2d6b 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.c @@ -20,7 +20,7 @@ The description of the workarounds included for these limitations can be found in the comments below. =20 - Copyright (c) 2020, ARM Limited. All rights reserved. + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -36,15 +36,29 @@ #include #include =20 +#define BUS_OFFSET 20 +#define DEV_OFFSET 15 +#define FUNC_OFFSET 12 +#define REG_OFFSET 4096 + /** - Assert the validity of a PCI address. A valid PCI address should contain= 1's - only in the low 28 bits. + Assert the validity of a PCI address. A valid PCI address should contain= 1's. =20 @param A The address to validate. =20 **/ #define ASSERT_INVALID_PCI_ADDRESS(A) \ - ASSERT (((A) & ~0xfffffff) =3D=3D 0) + ASSERT (((A) & ~0xffffffff) =3D=3D 0) + +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ + (UINT64) ( \ + (((UINTN) bus) << BUS_OFFSET) | \ + (((UINTN) dev) << DEV_OFFSET) | \ + (((UINTN) func) << FUNC_OFFSET) | \ + (((UINTN) (reg)) < REG_OFFSET ? \ + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) =20 /* Root port Entry, BDF Entries Count */ #define BDF_TABLE_ENTRY_SIZE 4 @@ -53,6 +67,7 @@ =20 /* BDF table offsets for PCIe */ #define PCIE_BDF_TABLE_OFFSET 0 +#define CCIX_BDF_TABLE_OFFSET (16 * 1024) =20 #define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) #define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) @@ -113,49 +128,64 @@ PciExpressRegisterForRuntimeAccess ( } =20 /** - Check if the requested PCI address can be safely accessed. + Check if the requested PCI address is a valid BDF address. =20 - SCP performs the initial bus scan, prepares a table of valid BDF address= es - and shares them through non-trusted SRAM. This function validates if the - requested PCI address belongs to a valid BDF by checking the table of va= lid - entries. If not, this function will return false. This is a workaround to - avoid bus fault that occurs when accessing unavailable PCI device due to - hardware bug. + SCP performs the initial bus scan and prepares a table of valid BDF addr= esses + and shares them through non-trusted SRAM. This function validates if the= PCI + address from any PCI request falls within the table of valid entries. If= not, + this function will return 0xFFFFFFFF. This is a workaround to avoid bus = fault + that happens when accessing unavailable PCI device due to RTL bug. =20 @param Address The address that encodes the PCI Bus, Device, Function a= nd Register. =20 - @return TRUE BDF can be accessed, valid. - @return FALSE BDF should not be accessed, invalid. + @return The base address of PCI Express. =20 **/ STATIC -BOOLEAN +UINTN IsBdfValid ( - IN UINTN Address + IN UINTN Address ) { + UINT8 Bus; + UINT8 Device; + UINT8 Function; UINTN BdfCount; UINTN BdfValue; - UINTN BdfEntry; UINTN Count; UINTN TableBase; - UINTN ConfigBase; + UINTN PciAddress; + + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); + Function =3D GET_FUNC_NUM (Address); + + PciAddress =3D EFI_PCIE_ADDRESS (Bus, Device, Function, 0); + + if (GET_PCIE_BASE_ADDRESS (Address) =3D=3D + FixedPcdGet64 (PcdPcieExpressBaseAddress)) { + TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFS= ET; + } else { + TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFS= ET; + } =20 - ConfigBase =3D Address & ~0xFFF; - TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; BdfCount =3D MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); - BdfEntry =3D TableBase + BDF_TABLE_HEADER_SIZE; - - /* Skip the header & check remaining entry */ - for (Count =3D 0; Count < BdfCount; Count++, BdfEntry +=3D BDF_TABLE_ENT= RY_SIZE) { - BdfValue =3D MmioRead32 (BdfEntry); - if (BdfValue =3D=3D ConfigBase) { - return TRUE; - } + + /* Start from the second entry */ + for (Count =3D BDF_TABLE_HEADER_COUNT; + Count < (BdfCount + BDF_TABLE_HEADER_COUNT); + Count++) { + BdfValue =3D MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE)); + if (BdfValue =3D=3D PciAddress) + break; } =20 - return FALSE; + if (Count =3D=3D (BdfCount + BDF_TABLE_HEADER_COUNT)) { + return mDummyConfigData; + } else { + return PciAddress; + } } =20 /** @@ -186,20 +216,35 @@ GetPciExpressAddress ( IN UINTN Address ) { - UINT8 Bus, Device, Function; - UINTN ConfigAddress; - - Bus =3D GET_BUS_NUM (Address); - Device =3D GET_DEV_NUM (Address); + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT16 Register; + UINTN ConfigAddress; + + // Get the EFI notation + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); Function =3D GET_FUNC_NUM (Address); - - if ((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0)) { - ConfigAddress =3D PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Addres= s; - } else { - ConfigAddress =3D PcdGet64 (PcdPciExpressBaseAddress) + Address; - if (!IsBdfValid(Address)) { - ConfigAddress =3D (UINTN)&mDummyConfigData; - } + Register =3D GET_REG_NUM (Address); + + ConfigAddress =3D (UINTN) + ((GET_PCIE_BASE_ADDRESS (Address) =3D=3D + FixedPcdGet64 (PcdPcieExpressBaseAddress)) ? + (((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function = =3D=3D 0)) ? + PcdGet32 (PcdPcieRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)): + PcdGet64 (PcdPcieExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r))) : + (((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function = =3D=3D 0)) ? + PcdGet32 (PcdCcixRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)): + PcdGet32 (PcdCcixExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)))); + + if (!((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0))) { + if (IsBdfValid (Address) =3D=3D mDummyConfigData) + ConfigAddress =3D (UINTN) &mDummyConfigData; } =20 return (VOID *)ConfigAddress; diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/P= ciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpres= sLib/PciExpressLib.inf index acb6fb6219..eac981e460 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.inf @@ -21,7 +21,7 @@ # 2. Root port ECAM space is not capable of 8bit/16bit writes. # This library includes workaround for these limitations as well. # -# Copyright (c) 2020, ARM Limited. All rights reserved. +# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,8 @@ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec =20 [FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize =20 @@ -53,4 +55,5 @@ PcdLib =20 [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index eea2d58402..5ec3c32539 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -46,6 +46,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64= |0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x= 00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00= 000012 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UIN= T64|0x00000013 =20 # CCIX gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 @@ -53,8 +54,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UIN= T32|0x00000019 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x00000= 01B - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x000= 0001B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x000000= 1C gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0= x00000001D gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x00= 00001E gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0= x00000001F --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#83772): https://edk2.groups.io/g/devel/message/83772 Mute This Topic: https://groups.io/mt/87090571/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-