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Tue, 16 Nov 2021 08:04:06 +0000 X-Received: from PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::d02e:f1e5:1354:622e]) by PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::d02e:f1e5:1354:622e%9]) with mapi id 15.20.4669.022; Tue, 16 Nov 2021 08:04:06 +0000 From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: nd@arm.com, Khasim Syed Mohammed , Deepak Pandey Subject: [edk2-devel] [PATCH 1/3] Silicon/ARM/NeoverseN1Soc: Update PciExpressLib to enable CCIX port Date: Tue, 16 Nov 2021 13:33:17 +0530 Message-Id: <20211116080319.18533-2-khasim.mohammed@arm.com> In-Reply-To: <20211116080319.18533-1-khasim.mohammed@arm.com> References: <20211116080319.18533-1-khasim.mohammed@arm.com> X-ClientProxiedBy: PN3PR01CA0124.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:96::12) To PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) MIME-Version: 1.0 X-Received: from e116623.arm.com (217.140.105.56) by PN3PR01CA0124.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:96::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.19 via Frontend Transport; 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6800 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: fed18503-6d4d-4621-7108-08d9a8d7a90d X-Microsoft-Antispam-Message-Info: wj2lT7OI0nOhHuRT7vWSgbDCt4FDHuVZ3k4qZK2d6JtdkxE40V+X2Zy5w4IPpMgQmEDe1xdwoVBMM1J2RvohA7gzzz+RDaAON+pzDVgrDgkMuyXpuRpDbuZ7WsSR5Mp5OpCO0agwD2OfmEhDrV3wM0GKXiAvrYt/9iiL2Iqx8Mj2jvCnGsGVt4rj3eO3Qc5QVMAxNo+lsqh0LmSrZkhS3Orf7YvE2nfEPtJRqnBU9wKzbNGEPtfssFiLOGZMuQ4c7RuH6CFeNsDcsWsABk9Ta8VXAGeLiA4r+8DUrQWqEZ1ec1Ly19NyEEsxiit+ljd5xqWc9TrRhy06DBULwuFqAWTckY0PkVOU2ZL9OTna9BB5mN7dNdalxjMO7r7Kv+aftgcRZaBdtDWa1GL3AA8X7S+/Q+e8cR3+eCRyWJrRd7v+twg7x6pVGQrO2c6RNPqhd34X6m2NoVrb66rsF7RT3N73uNTrouuUfsMRLPVeOYyvKM6SE5qlOr4JzRRcUMXOtL/ULDarxJROeMB7yq/sD1ZZr4eFiWbA7tgtSCj6CJlMOt744seKkxt9SCWleligxARf9m/3nxfHqN7xjaDQJI1NSsyenIsIhd5WuUNst1eEUM6ENpmR4gtZ/+HIVjBUZGQi1IbdMart058/dI7hjOqomGl6qvHlmolI/MCHOtZs/qI530RsVGufXKgOsf1k2TyjbCYdfHbB1UhYC4jQAg== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2021 08:04:20.2430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9eb6ed6-28bb-429c-ae48-08d9a8d7b1bf X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3198 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: GGSBVNP2DtzFewvvIa12iqJcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1637049865; bh=ps3Nz0PFmz6NfOCt9X2Zfa7rjasiUAvSWRI+Ws1Omx8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=wW1y3u4QBUHWRxUJkqlNwQgWAwQmweXBybYOMj8m7AjGqdGtg1G+INp1mujnOGBTSCm BM97JzoRAOMvVAR1Igl7s6zd9NFubfc94ILtaAWVXlh6hD+n1Xay5Iqcs5EIBv9oXS6NI XlVe2hZOi1Q38zJbfkojDYX0n6od26EQJS0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1637049986672100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the PciExpressLib to enable CCIX port as PCIe root host by validating the PCIe addresses and introducing corresponding PCD entries. Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e Signed-off-by: Deepak Pandey Signed-off-by: Khasim Syed Mohammed --- .../PciExpressLib.c | 127 ++++++++++++------ .../PciExpressLib.inf | 7 +- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +- 3 files changed, 94 insertions(+), 45 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/P= ciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressL= ib/PciExpressLib.c index bb0246b4a9..3abe0a2d6b 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.c @@ -20,7 +20,7 @@ The description of the workarounds included for these limitations can be found in the comments below. =20 - Copyright (c) 2020, ARM Limited. All rights reserved. + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -36,15 +36,29 @@ #include #include =20 +#define BUS_OFFSET 20 +#define DEV_OFFSET 15 +#define FUNC_OFFSET 12 +#define REG_OFFSET 4096 + /** - Assert the validity of a PCI address. A valid PCI address should contain= 1's - only in the low 28 bits. + Assert the validity of a PCI address. A valid PCI address should contain= 1's. =20 @param A The address to validate. =20 **/ #define ASSERT_INVALID_PCI_ADDRESS(A) \ - ASSERT (((A) & ~0xfffffff) =3D=3D 0) + ASSERT (((A) & ~0xffffffff) =3D=3D 0) + +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ + (UINT64) ( \ + (((UINTN) bus) << BUS_OFFSET) | \ + (((UINTN) dev) << DEV_OFFSET) | \ + (((UINTN) func) << FUNC_OFFSET) | \ + (((UINTN) (reg)) < REG_OFFSET ? \ + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) =20 /* Root port Entry, BDF Entries Count */ #define BDF_TABLE_ENTRY_SIZE 4 @@ -53,6 +67,7 @@ =20 /* BDF table offsets for PCIe */ #define PCIE_BDF_TABLE_OFFSET 0 +#define CCIX_BDF_TABLE_OFFSET (16 * 1024) =20 #define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) #define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) @@ -113,49 +128,64 @@ PciExpressRegisterForRuntimeAccess ( } =20 /** - Check if the requested PCI address can be safely accessed. + Check if the requested PCI address is a valid BDF address. =20 - SCP performs the initial bus scan, prepares a table of valid BDF address= es - and shares them through non-trusted SRAM. This function validates if the - requested PCI address belongs to a valid BDF by checking the table of va= lid - entries. If not, this function will return false. This is a workaround to - avoid bus fault that occurs when accessing unavailable PCI device due to - hardware bug. + SCP performs the initial bus scan and prepares a table of valid BDF addr= esses + and shares them through non-trusted SRAM. This function validates if the= PCI + address from any PCI request falls within the table of valid entries. If= not, + this function will return 0xFFFFFFFF. This is a workaround to avoid bus = fault + that happens when accessing unavailable PCI device due to RTL bug. =20 @param Address The address that encodes the PCI Bus, Device, Function a= nd Register. =20 - @return TRUE BDF can be accessed, valid. - @return FALSE BDF should not be accessed, invalid. + @return The base address of PCI Express. =20 **/ STATIC -BOOLEAN +UINTN IsBdfValid ( - IN UINTN Address + IN UINTN Address ) { + UINT8 Bus; + UINT8 Device; + UINT8 Function; UINTN BdfCount; UINTN BdfValue; - UINTN BdfEntry; UINTN Count; UINTN TableBase; - UINTN ConfigBase; + UINTN PciAddress; + + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); + Function =3D GET_FUNC_NUM (Address); + + PciAddress =3D EFI_PCIE_ADDRESS (Bus, Device, Function, 0); + + if (GET_PCIE_BASE_ADDRESS (Address) =3D=3D + FixedPcdGet64 (PcdPcieExpressBaseAddress)) { + TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFS= ET; + } else { + TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFS= ET; + } =20 - ConfigBase =3D Address & ~0xFFF; - TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; BdfCount =3D MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); - BdfEntry =3D TableBase + BDF_TABLE_HEADER_SIZE; - - /* Skip the header & check remaining entry */ - for (Count =3D 0; Count < BdfCount; Count++, BdfEntry +=3D BDF_TABLE_ENT= RY_SIZE) { - BdfValue =3D MmioRead32 (BdfEntry); - if (BdfValue =3D=3D ConfigBase) { - return TRUE; - } + + /* Start from the second entry */ + for (Count =3D BDF_TABLE_HEADER_COUNT; + Count < (BdfCount + BDF_TABLE_HEADER_COUNT); + Count++) { + BdfValue =3D MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE)); + if (BdfValue =3D=3D PciAddress) + break; } =20 - return FALSE; + if (Count =3D=3D (BdfCount + BDF_TABLE_HEADER_COUNT)) { + return mDummyConfigData; + } else { + return PciAddress; + } } =20 /** @@ -186,20 +216,35 @@ GetPciExpressAddress ( IN UINTN Address ) { - UINT8 Bus, Device, Function; - UINTN ConfigAddress; - - Bus =3D GET_BUS_NUM (Address); - Device =3D GET_DEV_NUM (Address); + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT16 Register; + UINTN ConfigAddress; + + // Get the EFI notation + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); Function =3D GET_FUNC_NUM (Address); - - if ((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0)) { - ConfigAddress =3D PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Addres= s; - } else { - ConfigAddress =3D PcdGet64 (PcdPciExpressBaseAddress) + Address; - if (!IsBdfValid(Address)) { - ConfigAddress =3D (UINTN)&mDummyConfigData; - } + Register =3D GET_REG_NUM (Address); + + ConfigAddress =3D (UINTN) + ((GET_PCIE_BASE_ADDRESS (Address) =3D=3D + FixedPcdGet64 (PcdPcieExpressBaseAddress)) ? + (((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function = =3D=3D 0)) ? + PcdGet32 (PcdPcieRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)): + PcdGet64 (PcdPcieExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r))) : + (((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function = =3D=3D 0)) ? + PcdGet32 (PcdCcixRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)): + PcdGet32 (PcdCcixExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Registe= r)))); + + if (!((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0))) { + if (IsBdfValid (Address) =3D=3D mDummyConfigData) + ConfigAddress =3D (UINTN) &mDummyConfigData; } =20 return (VOID *)ConfigAddress; diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/P= ciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpres= sLib/PciExpressLib.inf index acb6fb6219..eac981e460 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpre= ssLib.inf @@ -21,7 +21,7 @@ # 2. Root port ECAM space is not capable of 8bit/16bit writes. # This library includes workaround for these limitations as well. # -# Copyright (c) 2020, ARM Limited. All rights reserved. +# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,8 @@ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec =20 [FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize =20 @@ -53,4 +55,5 @@ PcdLib =20 [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index eea2d58402..5ec3c32539 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -46,6 +46,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64= |0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x= 00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00= 000012 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UIN= T64|0x00000013 =20 # CCIX gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 @@ -53,8 +54,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UIN= T32|0x00000019 gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x00000= 01B - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x000= 0001B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x000000= 1C gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0= x00000001D gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x00= 00001E gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0= x00000001F --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6800 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT059.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 7e556181-5441-4a1c-9ad9-08d9a8d7aac1 X-Microsoft-Antispam-Message-Info: +QucUTzcmAIzucW5YesdgJiMQQmactPKu7sXolw9MiWUB5plskqW7QQrQVT5iQcw2szRl9IsT58XW4P3uJG6LbqDzZAaHG7AUvUswEpSghmTsphDDWFOLPr0/fSg0yrS3VwJzSfBadkYLpmB8MysxWeWCsQDmfTZf/2Ab/SjFQySjvOe/fqBHOSQC8O0JcbX3S8fcoGxa1h1HU8S5i/av6Fxnt0Dnf0NK87g5jSFfxSsGr/7VULQTGm6kZzRIBZDh8XP8kiwYEvPeicFc3QVHlSdA1k6v47R5rfSCrnODp8h62bIfk81Ok0vYnEyLVu1tz1BwQOnWAga3xQ793P4HQ+TEhG3ZEqIueZFhZ7fgGHWfgN3hpy9fy8tRi7DZYyiYX40dbA1CEYXC//kyECUzf1HQUbuNAlkuyZVyH6bKTR59ZsXCWsdGCU1nB/QW1tfgL36E5ccezNvqpkiWluzu2yDlT9ZC/OuhXjXBIZqZkiQw3Vg0D94gFIJKVkI5qGtxr+bJdZSWEIGTCJnDv5m2/4bRhdn4jyH/8R2Nep9A4iHXBlc0AB5dNdRTC8YOP0PTRienduaItUUZX5zRLZKckEP+xeAu23xJATcnNOGlHPhppuRO5/8rBuBeO+KGu+kA8gXLjaNqxJ+XQxpIAFr0WFB5T0WKTikJqPSBQyyYUoTR40udqbUkOpHiO21Dd8/svc/WslG0xZZ/w5r48B5TA== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2021 08:04:25.3004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 139a0a8a-74fa-4d79-4d4b-08d9a8d7b4c4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT059.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB5063 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: iMCGIWBvRDw06cPVv1iBxFgVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1637049873; bh=gaKKJsTPJU8loRnmOXpzDNtdYq8alOuVU0+BqcGh4hM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=mha18GNglcsIXzI7hAHhRU7tBlMVueoG0xoWRWnTMfeJLwDOLOjOY6Ay2jgRXdQEmww AGiOCqcScB7Xpvur9mmuKPYzYRDdnwvxUkBTZHl/0eS4XquK8XJmdTVHbwOKcR+cFHYv2 9R52qlN9UUoO+0s1rtYBiCKLlde1toT38GQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1637049997203100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BasePCISegment Library in MdePkg doesn't allow configuring multiple segments required for PCIe and CCIX root port enumeration. Therefore, a custom PCI Segment library is adapted from SynQuacerPciSegmentLib and ported for N1Sdp. Change-Id: I0a124b0ea2fb7a8ee652de2d66b977d848c509b4 Signed-off-by: Khasim Syed Mohammed --- .../Library/PciSegmentLib/PciSegmentLib.c | 1425 +++++++++++++++++ .../Library/PciSegmentLib/PciSegmentLib.inf | 41 + 2 files changed, 1466 insertions(+) create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegm= entLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegm= entLib.inf diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.= c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c new file mode 100644 index 0000000000..dbf00e1f14 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1425 @@ +/** @file + PCI Segment Library for N1SDP SoC with multiple RCs + + Having two distinct root complexes is not supported by the standard + set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib + reimplements the functionality to support multiple root ports on + different segment numbers. + + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
+ Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + PciCfgWidthUint8 =3D 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48.= .63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) + +/** + Function to return PCIe Physical Address for different RCs. + If address is invalid, then ASSERT(). + + @param Address Address passed from bus layer. + + @return Return PCIe base address. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address + ) +{ + switch ((UINT16)(Address >> 32)) { + case 0: + return FixedPcdGet32 (PcdPcieExpressBaseAddress); + case 1: + return FixedPcdGet32 (PcdCcixExpressBaseAddress); + default: + ASSERT (FALSE); + } + return 0; +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function + and Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + + Base =3D PciSegmentLibGetConfigBase (Address); + + switch (Width) { + case PciCfgWidthUint8: + return PciRead8 (Base + (UINT32)Address); + case PciCfgWidthUint16: + return PciRead16 (Base + (UINT32)Address); + case PciCfgWidthUint32: + return PciRead32 (Base + (UINT32)Address); + default: + ASSERT (FALSE); + } + return 0; +} + +/** + Internal worker function to write to a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function + and Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + + Base =3D PciSegmentLibGetConfigBase (Address); + + switch (Width) { + case PciCfgWidthUint8: + PciWrite8 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint16: + PciWrite16 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint32: + PciWrite32 (Base + (UINT32)Address, Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are + serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + + @return The 8-bit PCI configuration register specified by the Address. +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit Value in the PCI configuration register specified by the + Address. This function must guarantee that all PCI read and write operat= ions + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Valu= e); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) (PciSegmentRead8 (Address) | OrData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by + AndData, and writes the result to the 8-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) (PciSegmentRead8 (Address) & AndData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with + an 8-bit value, followed by a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, performs a bitwise OR between the result of the AND operation + and the value specified by OrData, and writes the result to the 8-bit + PCI configuration register specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + (UINT8) ((PciSegmentRead8 (Address) & AndData) + | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciSegmentWrite8 (Address, + BitFieldWrite8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldOr8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldAnd8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, + BitFieldAndThenOr8 (PciSegmentRead8 (Address), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, + Function, and Register. + @param Value The value to write. + + @return The Value written is returned. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Va= lue); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) (PciSegmentRead16 (Address) | OrData)= ); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 16-bit PCI configuration regist= er + specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) (PciSegmentRead16 (Address) & AndData= )); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by + AndData, performs a bitwise OR between the result of the AND operation a= nd + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + (UINT16) ((PciSegmentRead16 (Address) & AndDat= a) + | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciSegmentWrite16 (Address, + BitFieldWrite16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified + by OrData, and writes the result to the 16-bit PCI configuration register + specified by the Address. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldOr16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by the Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and + EndBit, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + The ordinal of the least significant bit in a byte is + bit 0. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + The ordinal of the most significant bit in a byte is b= it 7. + @param AndData The value to AND with the read value from the PCI + configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldAnd16 (PciSegmentRead16 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and + EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, + BitFieldAndThenOr16 (PciSegmentRead16 (Address= ), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he + value specified by Value. Value is returned. This function must guarant= ee + that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a + 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified + by OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 32-bit PCI configuration regist= er + specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with + a 32-bit value, followed by a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, performs a bitwise OR between the result of the AND operation + and the value specified by OrData, and writes the result to the 32-bit + PCI configuration register specified by Address. + + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, + (PciSegmentRead32 (Address) & AndData) | OrDat= a); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciSegmentWrite32 (Address, + BitFieldWrite32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + Value)); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, + BitFieldOr32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + OrData)); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified + by AndData, and writes the result to the 32-bit PCI configuration regist= er + specified by Address. The value written to the PCI configuration register + is returned. This function must guarantee that all PCI read and write + operations are serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and + EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, + BitFieldAnd32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + AndData)); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit + and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAndThenOr32 (PciSegmentRead32 (Address), + StartBit, + EndBit, + AndData, + OrData)); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to= read + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning an= d the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // Save Size for return + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // Read a byte if StartAddress is byte aligned + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // Read a word if StartAddress is word aligned + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // Read as many double words as possible + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // Read the last remaining word if exist + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // Read the last remaining byte if exist + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions, + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + + // Save Size for return + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // Write a byte if StartAddress is byte aligned + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // Write a word if StartAddress is word aligned + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // Write as many double words as possible + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // Write the last remaining word if exist + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // Write the last remaining byte if exist + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.= inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100644 index 0000000000..dad123b4f2 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,41 @@ +## @file +# PCI Segment Library for N1Sdp SoC with multiple RCs +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PciSegmentLib + FILE_GUID =3D b5ecc9c3-6b30-4f72-8a06-889b4ea8427e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/ARM/N1Sdp/N1SdpPlatform.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PciLib + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-Received: from PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) by PAXPR08MB6800.eurprd08.prod.outlook.com (2603:10a6:102:137::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.27; Tue, 16 Nov 2021 08:04:12 +0000 X-Received: from PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::d02e:f1e5:1354:622e]) by PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::d02e:f1e5:1354:622e%9]) with mapi id 15.20.4669.022; Tue, 16 Nov 2021 08:04:12 +0000 From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: nd@arm.com, Khasim Syed Mohammed Subject: [edk2-devel] [PATCH 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Date: Tue, 16 Nov 2021 13:33:19 +0530 Message-Id: <20211116080319.18533-4-khasim.mohammed@arm.com> In-Reply-To: <20211116080319.18533-1-khasim.mohammed@arm.com> References: <20211116080319.18533-1-khasim.mohammed@arm.com> X-ClientProxiedBy: PN3PR01CA0124.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:96::12) To PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) MIME-Version: 1.0 X-Received: from e116623.arm.com (217.140.105.56) by PN3PR01CA0124.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:96::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.19 via Frontend Transport; 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6800 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT040.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 63814bd6-de3a-45ae-fd98-08d9a8d7aca6 X-Microsoft-Antispam-Message-Info: bFDkrIVnSHo6QG8G4M2Rhx5riHs+brad5qa7dQnzjtg4ZUHRLAJ6QKLpVktliofA7TtzEmcYA2ktoIIoDJXnuIEXPfs5q3Qj/9AnKcokxU64QGjYIYBkUKeV7GyMFMWR0UGqI1wUQAldijRFj+oCYV7PzgMJZOSgLTtRvOCFS1Kpgy6q32mLlPUDTbc/ewqyuttXuoY2PlQX0DjwSdnu1ffQWfDK4Rg9R2c1uxgs3W4oxhrE2jJjEl1rC00UFryxJdTyviTXbpPlYWBx/SCK5qzss5zQAix8cGQDwvZnZ2u+n7UJKE5SPE3yEuVg2Sz56Wa2lWDeCEt7NUH9XZ0zTcmbQQHNcXl9/0TS392HH7/V1Be41oww0YoFoLVw7DGBIObUSWfOxeA9zqSuuexjxfpjO4usbqgg6Q6vEGKEu6PS3PRyI31ePRCB91n4/QpdDuu7wUU7syk3tfYvtelMolPhY15pZWMpUtzyITLilfGDTo0HF9AdlKxY2Odjj4UPT1YNqVGJauUnQ8PNiH/eYdAY8DuUK7vz2oZ831EDuP8QCmhUegs+l5diYB8DdDVFgAAjAgNE2erJn25aJKs/WgmBks2pbl9kr2R4Kqbh/pEDeiTe8QsqmO+LlHescvI9vX4ypk9jdM7JfTV1SklrV4755FO6fZk9+V0z6f197XA7ZqgVpTOKOoK1Nkr3R9jefQB8ujBeI+efW2AUZiY1/A== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2021 08:04:25.8031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1847f0ad-00bd-4457-167c-08d9a8d7b510 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT040.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3860 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: E9UTV9jdAbJcI2vpWxhggcRMx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1637049873; bh=gh6PCywFVf0mI6vhlKe7JYWyyHroYu54++kZM+DANT0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=l2thBnQKCIPrftDDNJ0+mrkZE5NU1tVdAIXZBg3XzXDeHj9L3eIYScqiejDuY0UHC52 MJpN8bqfP8A2wmyVPj1vSRr92FW/0OQ/TQdwzzanqFd5KS1co5z6E8wETPNgwqmwN1+P+ k7ayUgvSdeS9ER6W0SzW3Rjm+c/gIeyI1jA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1637049994740100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch enables CCIX root complex support by updating the root complex node info in PciHostBridge library and enabling PciSegment library for N1Sdp. Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 Signed-off-by: Khasim Syed Mohammed --- .../ConfigurationManagerDxe.inf | 3 +- Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 - Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +- .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- .../Library/PlatformLib/PlatformLib.inf | 1 + .../Library/PlatformLib/PlatformLibMem.c | 4 +- 7 files changed, 81 insertions(+), 15 deletions(-) diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDx= e/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/Con= figurationManagerDxe/ConfigurationManagerDxe.inf index 027a4202ff..67b0c3a0ea 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManagerDxe.inf +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManagerDxe.inf @@ -76,8 +76,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate =20 - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress - gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base =20 @@ -91,6 +89,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1Sd= pPlatform.dec index 2ab6c20dcc..98d2d5ba81 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec @@ -34,9 +34,6 @@ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 =20 - # PCIe - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00= 000007 - # External memory gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 =20 diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1Sd= pPlatform.dsc index 7488bdc036..75d7871452 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -75,7 +75,7 @@ [LibraryClasses.common.DXE_DRIVER] FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciH= ostBridgeLib.inf - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegment= Lib.inf PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressL= ib/PciExpressLib.inf =20 @@ -127,7 +127,6 @@ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 =20 # PCIe - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE =20 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBrid= geLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.c index 9332939f63..c3a14a6c17 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -1,7 +1,7 @@ /** @file * PCI Host Bridge Library instance for ARM Neoverse N1 platform * -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
* * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -16,6 +16,8 @@ #include #include =20 +#define ROOT_COMPLEX_NUM 2 + GLOBAL_REMOVE_IF_UNREFERENCED STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { L"Mem", L"I/O", L"Bus" @@ -28,7 +30,7 @@ typedef struct { } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; #pragma pack () =20 -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D { +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_CO= MPLEX_NUM] =3D { // PCIe { { @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridg= eDevicePath[] =3D { 0 } } - } + }, + //CCIX + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID(0x0A09), // CCIX + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, }; =20 -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] =3D { { 0, // Segment 0, // Supports @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { 0 }, (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] - } + }, + { + 1, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpa= ce + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdCcixBusMin), + FixedPcdGet32 (PcdCcixBusMax) + }, { + // Io + FixedPcdGet64 (PcdCcixIoBase), + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdCcixMmio32Base), + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size= ) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdCcixMmio64Base), + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size= ) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] + }, }; =20 /** diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBrid= geLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridg= eLib.inf index 3ff1c592f2..3356c3ad35 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf @@ -1,7 +1,7 @@ ## @file # PCI Host Bridge Library instance for ARM Neoverse N1 platform. # -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -42,6 +42,15 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size =20 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size + [Protocols] gEfiCpuIo2ProtocolGuid =20 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 8e2154aadf..96e590cdd8 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -43,6 +43,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 1c4a445c5e..339fa07b32 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 // PCIe ECAM Configuration Space - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieExpressBa= seAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPcieExpressBa= seAddress); VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPcieBus= Max) - FixedPcdGet32 (PcdPcieBusMi= n) + 1) * SIZE_1MB; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#83774): https://edk2.groups.io/g/devel/message/83774 Mute This Topic: https://groups.io/mt/87090574/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-