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Mon, 15 Nov 2021 03:55:59 GMT X-Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3ca4bsushc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Nov 2021 03:55:59 +0000 X-Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 9A9446D; Mon, 15 Nov 2021 03:55:58 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 8C31636; Mon, 15 Nov 2021 03:55:57 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 11/14] RiscVPlatformPkg/U500: Add device tree for U500 platform Date: Mon, 15 Nov 2021 10:56:37 +0800 Message-Id: <20211115025640.12897-12-abner.chang@hpe.com> In-Reply-To: <20211115025640.12897-1-abner.chang@hpe.com> References: <20211115025640.12897-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: EGN1Hu0sfH2QFtgt-iFE87c_AAqv_KLM X-Proofpoint-ORIG-GUID: EGN1Hu0sfH2QFtgt-iFE87c_AAqv_KLM X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: MvCvUbcFIikPGqM33VGmTrk1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1636948566; bh=sk3uCQ26bcFalcQZEJ3niqfQHKY9JZVpgcVQ+2HTwvc=; h=Cc:Date:From:Reply-To:Subject:To; b=jkA3pXj6k5+Li2aF/X65NhjhAkqi4y3ZeNQhHylfxgPx4ZqLYVoKNzjjtRadS+8tr63 VMkj64zJxZXzCbEKYOYxwR2C4GkK6Dlg6UnjavMpqUmJf4bdsTatBW/hueWbetZmnGKKi 28Fx5Vbu57IEH5MYrB6T+FNBPqwnUPcrmYo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1636948567981100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../DeviceTree/U500DeviceTree.inf | 25 ++ .../FreedomU500VC707Board/DeviceTree/gpio.h | 45 +++ .../DeviceTree/sifive-fu500-prci.h | 19 ++ .../DeviceTree/fu500-c000.dtsi | 276 ++++++++++++++++++ .../DeviceTree/hifive-unleashed-a00.dts | 108 +++++++ 5 files changed, 473 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/U500DeviceTree.inf create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/gpio.h create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/sifive-fu500-prci.h create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/fu500-c000.dtsi create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/hifive-unleashed-a00.dts diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U= 500DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/U500DeviceTree.inf new file mode 100644 index 0000000000..3eeb8c51f4 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500Devi= ceTree.inf @@ -0,0 +1,25 @@ +## @file +# +# Device tree description of SiFive U500 VC707 platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D U500DeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + gpio.h + hifive-unleashed-a00.dts + fu500-c000.dtsi + sifive-fu500-prci.h + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/g= pio.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h new file mode 100644 index 0000000000..bc7e2fe7a1 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h @@ -0,0 +1,45 @@ +/** @file + This header provides constants for most GPIO bindings. + + Most GPIO bindings include a flags cell as part of the GPIO specifier. + In most cases, the format of the flags cell uses the standard values + defined in this header. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef DT_BINDINGS_GPIO_GPIO_H_ +#define DT_BINDINGS_GPIO_GPIO_H_ + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +// +// Open Drain/Collector is the combination of single-ended open drain inte= rface. +// Open Source/Emitter is the combination of single-ended open source inte= rface. +// +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/s= ifive-fu500-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devi= ceTree/sifive-fu500-prci.h new file mode 100644 index 0000000000..7efa0006a0 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-f= u500-prci.h @@ -0,0 +1,19 @@ +/**@file + + SPDX-License-Identifier: (GPL-2.0 OR MIT) + Copyright (c) 2018-2019 SiFive, Inc + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/f= u500-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTr= ee/fu500-c000.dtsi new file mode 100644 index 0000000000..82f10e71e0 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c0= 00.dtsi @@ -0,0 +1,276 @@ +/**@file + U500 VC707 Device Tree, compatible with fu540-c000 platform. + + SPDX-License-Identifier: (GPL-2.0 OR MIT) + Copyright (c) 2018-2019 SiFive, Inc + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/dts-v1/; + +#include "sifive-fu500-prci.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + ethernet0 =3D ð0; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu@0 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <0>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl= e-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff &cpu0_intc 9 + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9>; + }; + prci: clock-controller@10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial@54000000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0"; + reg =3D <0x0 0x54000000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + dma: dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <23 24 25 26 27 28 29 30>; + #dma-cells =3D <1>; + }; + i2c0: i2c@10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2= c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi@10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi@10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi@10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet@10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm0: pwm@10020000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10020000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <42 43 44 45>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + pwm1: pwm@10021000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10021000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <46 47 48 49>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible =3D "sifive,fu540-c000-ccache", "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic0>; + interrupts =3D <1 2 3>; + reg =3D <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible =3D "sifive,fu540-c000-gpio", "sifive,g= pio0"; + interrupt-parent =3D <&plic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1= 3>, + <14>, <15>, <16>, <17>, <18>, <19>, <= 20>, + <21>, <22>; + reg =3D <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + clint: clint@2000000 { + compatible =3D "riscv,clint0"; + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7>; + reg =3D <0x0 0x2000000 0x0 0xc0000>; + }; + }; +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/h= ifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board= /DeviceTree/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..2074b18fa8 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-u= nleashed-a00.dts @@ -0,0 +1,108 @@ +/**@file + U500 VC707 Device Tree + + SPDX-License-Identifier: (GPL-2.0 OR MIT) + Copyright (c) 2018-2019 SiFive, Inc + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "fu500-c000.dtsi" +#include "gpio.h" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SiFive HiFive Unleashed A00"; + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path =3D "serial0"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <33333333>; + clock-output-names =3D "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D ; + clock-output-names =3D "rtcclk"; + }; + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 10 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&qspi0 { + status =3D "okay"; + flash@0 { + compatible =3D "issi,is25wp256", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qspi2 { + status =3D "okay"; + mmc@0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&gpio { + status =3D "okay"; +}; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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