From nobody Tue Apr 23 09:36:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+83669+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+83669+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1636681234; cv=none; d=zohomail.com; s=zohoarc; b=fCNcXmHpiuYApsM/wnYf/lJpu+jYyxbzjrfrQn5/u38YN5+mAsFY4iJYyVk3Z+QY0CO9QPjCWYfP6fMaCh2c6Wtyw7b+XABTtrC8dtz0og5U0k/bbR8olZHlt2qjXrjAFRv1nLnSP4dugs4bLorSdQiNvy0E5uZ6hYFfceuN6+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1636681234; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=ROZ6BQ/yoTMwOWzBjX2CHN29VG0IrCp8i5assDG5aJ8=; b=P6H4xVmfbKMFdgwC/beW9sBUXXrBi4hLZc8dPyQK8zfhK4ZAZTF4ktEw3+aM7TepuM8YPF2GKveHuW+8DnlwQwmINIyQAdOgQoqdo75KFsa0kCn3LGTuQz9Rz6WxcK3jMo+e0PyJJP580WwPTO/HI9uI+YShOczJg78g+Uy4dZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+83669+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1636681234121151.37853649199008; Thu, 11 Nov 2021 17:40:34 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id QX58YY1788612xdYljsAQYoM; Thu, 11 Nov 2021 17:40:33 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.9353.1636681232964293016 for ; Thu, 11 Nov 2021 17:40:33 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10165"; a="232999005" X-IronPort-AV: E=Sophos;i="5.87,227,1631602800"; d="scan'208";a="232999005" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2021 17:40:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,227,1631602800"; d="scan'208";a="452966923" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga006.jf.intel.com with ESMTP; 11 Nov 2021 17:40:30 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH v4] UefiCpuPkg/PiSmmCpuDxeSmm: Use SMM Interrupt Shadow Stack Date: Fri, 12 Nov 2021 09:40:28 +0800 Message-Id: <20211112014028.9520-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: jCC8anPPr2UdREcWwMS8hysNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1636681233; bh=jBjsl082SgOtILELAQ0O+8wW2TbHb2ct/bKfXnJuJtI=; h=Cc:Date:From:Reply-To:Subject:To; b=XlP0rHRMRTgBFlNqnY+tz/l2RKgn/U7u8b3JfItyYMVhG/4EzVO6j58o0/H5Kc2X+ae v23UBtLRZLdBzcI83Wh9p0YIPJ3N/EeW7fWUhqS4epN3PSt5BQ2AP9IbZptZSLzEYHd8n OIT6Ae5ODh3xLW6hK90eW5sHC56Ji4Ei72o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1636681234619100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When CET shadow stack feature is enabled, it needs to use IST for the exceptions, and uses interrupt shadow stack for the stack switch. Shadow stack should be 32 bytes aligned. Check IST field, when clear shadow stack token busy bit when using retf. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3728 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Reviewed-by: Ray Ni --- .../X64/Xcode5ExceptionHandlerAsm.nasm | 66 ++++++++++++------ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 61 +++++++++++----- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 14 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 12 +++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 81 ++++++++++++------= ---- 5 files changed, 157 insertions(+), 77 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5Except= ionHandlerAsm.nasm index 4881a02848..84a12ddb88 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm @@ -15,17 +15,36 @@ ;-------------------------------------------------------------------------= ----- %include "Nasm.inc" =20 +; +; Equivalent NASM structure of IA32_DESCRIPTOR +; +struc IA32_DESCRIPTOR + .Limit CTYPE_UINT16 1 + .Base CTYPE_UINTN 1 +endstruc + +; +; Equivalent NASM structure of IA32_IDT_GATE_DESCRIPTOR +; +struc IA32_IDT_GATE_DESCRIPTOR + .OffsetLow CTYPE_UINT16 1 + .Selector CTYPE_UINT16 1 + .Reserved_0 CTYPE_UINT8 1 + .GateType CTYPE_UINT8 1 + .OffsetHigh CTYPE_UINT16 1 + .OffsetUpper CTYPE_UINT32 1 + .Reserved_1 CTYPE_UINT32 1 +endstruc + ; ; CommonExceptionHandler() ; =20 %define VC_EXCEPTION 29 -%define PF_EXCEPTION 14 =20 extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) -extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) =20 SECTION .data =20 @@ -282,42 +301,49 @@ DrFinish: =20 ; The follow algorithm is used for clear shadow stack token busy bit. ; The comment is based on the sample shadow stack. + ; Shadow stack is 32 bytes aligned. ; The sample shadow stack layout : ; Address | Context ; +-------------------------+ - ; 0xFD0 | FREE | it is 0xFD8|0x02|(LMA & CS.L), a= fter SAVEPREVSSP. + ; 0xFB8 | FREE | It is 0xFC0|0x02|(LMA & CS.L), a= fter SAVEPREVSSP. ; +-------------------------+ - ; 0xFD8 | Prev SSP | + ; 0xFC0 | Prev SSP | ; +-------------------------+ - ; 0xFE0 | RIP | + ; 0xFC8 | RIP | ; +-------------------------+ - ; 0xFE8 | CS | + ; 0xFD0 | CS | ; +-------------------------+ - ; 0xFF0 | 0xFF0 | BUSY | BUSY flag cleared after CLRSSBSY + ; 0xFD8 | 0xFD8 | BUSY | BUSY flag cleared after CLRSSBSY ; +-------------------------+ - ; 0xFF8 | 0xFD8|0x02|(LMA & CS.L) | + ; 0xFE0 | 0xFC0|0x02|(LMA & CS.L) | ; +-------------------------+ ; Instructions for Intel Control Flow Enforcement Technology (CET) are= supported since NASM version 2.15.01. cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 jz CetDone - cmp qword [rbp + 8], PF_EXCEPTION ; check if it is a Page Fault - jnz CetDone - cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0 - jz CetDone mov rax, cr4 - and rax, 0x800000 ; check if CET is enabled + and rax, 0x800000 ; Check if CET is enabled + jz CetDone + sub rsp, 0x10 + sidt [rsp] + mov rcx, qword [rsp + IA32_DESCRIPTOR.Base]; Get IDT base address + add rsp, 0x10 + mov rax, qword [rbp + 8]; Get exception number + sal rax, 0x04 ; Get IDT offset + add rax, rcx ; Get IDT gate descriptor address + mov al, byte [rax + IA32_IDT_GATE_DESCRIPTOR.Reserved_0] + and rax, 0x01 ; Check IST field jz CetDone - ; SSP should be 0xFD8 at this point + ; SSP should be 0xFC0 at this point mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor s= hadow stack token - INCSSP_RAX ; After this SSP should be 0xFF8 - SAVEPREVSSP ; now the shadow stack restore token will = be created at 0xFD0 - READSSP_RAX ; Read new SSP, SSP should be 0x1000 + INCSSP_RAX ; After this SSP should be 0xFE0 + SAVEPREVSSP ; now the shadow stack restore token will = be created at 0xFB8 + READSSP_RAX ; Read new SSP, SSP should be 0xFE8 sub rax, 0x10 - CLRSSBSY_RAX ; Clear token at 0xFF0, SSP should be 0 af= ter this + CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 af= ter this sub rax, 0x20 - RSTORSSP_RAX ; Restore to token at 0xFD0, new SSP will = be 0xFD0 + RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will = be 0xFB8 mov rax, 0x01 ; Pop off the new save token created - INCSSP_RAX ; SSP should be 0xFD8 now + INCSSP_RAX ; SSP should be 0xFC0 now CetDone: =20 cli diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 67ad9a4c07..2b2e1a5390 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -861,35 +861,58 @@ PiCpuSmmEntry ( mSmmStackSize =3D EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpu= SmmStackSize))); if (FeaturePcdGet (PcdCpuSmmStackGuard)) { // - // 2 more pages is allocated for each processor. - // one is guard page and the other is known good stack. + // SMM Stack Guard Enabled + // 2 more pages is allocated for each processor, one is guard page a= nd the other is known good stack. // - // +-------------------------------------------+-----+----------------= ---------------------------+ - // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stac= k | Guard Page | SMM Stack | - // +-------------------------------------------+-----+----------------= ---------------------------+ - // | | | = | - // |<-------------- Processor 0 -------------->| |<-------------- = Processor n -------------->| + // +--------------------------------------------------+-----+---------= -----------------------------------------+ + // | Known Good Stack | Guard Page | SMM Stack | ... | Known Go= od Stack | Guard Page | SMM Stack | + // +--------------------------------------------------+-----+---------= -----------------------------------------+ + // | 4K | 4K PcdCpuSmmStackSize| | 4= K | 4K PcdCpuSmmStackSize| + // |<---------------- mSmmStackSize ----------------->| |<--------= -------- mSmmStackSize ----------------->| + // | | | = | + // |<------------------ Processor 0 ----------------->| |<--------= ---------- Processor n ----------------->| // mSmmStackSize +=3D EFI_PAGES_TO_SIZE (2); } =20 mSmmShadowStackSize =3D 0; if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) && mCetSup= ported) { - // - // Append Shadow Stack after normal stack - // - // |=3D Stacks - // +--------------------------------------------------+---------------= ------------------------------------------------+ - // | Known Good Stack | Guard Page | SMM Stack | Known Good Sha= dow Stack | Guard Page | SMM Shadow Stack | - // +--------------------------------------------------+---------------= ------------------------------------------------+ - // | |PcdCpuSmmStackSize| = |PcdCpuSmmShadowStackSize| - // |<---------------- mSmmStackSize ----------------->|<--------------= ------- mSmmShadowStackSize ------------------->| - // | = | - // |<-------------------------------------------- Processor N --------= ----------------------------------------------->| - // mSmmShadowStackSize =3D EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32= (PcdCpuSmmShadowStackSize))); + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + // + // SMM Stack Guard Enabled + // Append Shadow Stack after normal stack + // 2 more pages is allocated for each processor, one is guard page= and the other is known good shadow stack. + // + // |=3D Stacks + // +--------------------------------------------------+-------------= --------------------------------------------------+ + // | Known Good Stack | Guard Page | SMM Stack | Known Good S= hadow Stack | Guard Page | SMM Shadow Stack | + // +--------------------------------------------------+-------------= --------------------------------------------------+ + // | 4K | 4K |PcdCpuSmmStackSize| 4= K | 4K |PcdCpuSmmShadowStackSize| + // |<---------------- mSmmStackSize ----------------->|<------------= --------- mSmmShadowStackSize ------------------->| + // | = | + // |<-------------------------------------------- Processor N ------= ------------------------------------------------->| + // mSmmShadowStackSize +=3D EFI_PAGES_TO_SIZE (2); + } else { + // + // SMM Stack Guard Disabled (Known Good Stack is still required for = potential stack switch.) + // Append Shadow Stack after normal stack with 1 more page as know= n good shadow stack. + // 1 more pages is allocated for each processor, it is known good = stack. + // + // + // |=3D Stacks + // +-------------------------------------+--------------------------= ------------------------+ + // | Known Good Stack | SMM Stack | Known Good Shadow Stack |= SMM Shadow Stack | + // +-------------------------------------+--------------------------= ------------------------+ + // | 4K |PcdCpuSmmStackSize| 4K |= PcdCpuSmmShadowStackSize| + // |<---------- mSmmStackSize ---------->|<--------------- mSmmShado= wStackSize ------------>| + // | = | + // |<-------------------------------- Processor N ------------------= ----------------------->| + // + mSmmShadowStackSize +=3D EFI_PAGES_TO_SIZE (1); + mSmmStackSize +=3D EFI_PAGES_TO_SIZE (1); } } =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 2248a8c5ee..fc9b748948 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -557,6 +557,20 @@ InitializeIDTSmmStackGuard ( VOID ); =20 +/** + Initialize IDT IST Field. + + @param[in] ExceptionType Exception type. + @param[in] Ist IST value. + +**/ +VOID +EFIAPI +InitializeIdtIst ( + IN EFI_EXCEPTION_TYPE ExceptionType, + IN UINT8 Ist + ); + /** Initialize Gdt for all processors. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index d6f8dd94d3..211a78b1c4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -481,7 +481,17 @@ SmmInitPageTable ( // Additional SMM IDT initialization for SMM stack guard // if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - InitializeIDTSmmStackGuard (); + DEBUG ((DEBUG_INFO, "Initialize IDT IST field for SMM Stack Guard\n")); + InitializeIdtIst (EXCEPT_IA32_PAGE_FAULT, 1); + } + + // + // Additional SMM IDT initialization for SMM CET shadow stack + // + if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) && mCetSup= ported) { + DEBUG ((DEBUG_INFO, "Initialize IDT IST field for SMM Shadow Stack\n")= ); + InitializeIdtIst (EXCEPT_IA32_PAGE_FAULT, 1); + InitializeIdtIst (EXCEPT_IA32_MACHINE_CHECK, 1); } =20 // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSm= mCpuDxeSmm/X64/SmmFuncsArch.c index ca3f5ff91a..ce7afce6d4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -24,24 +24,24 @@ UINT32 mCetInterruptSspTable; UINTN mSmmInterruptSspTables; =20 /** - Initialize IDT for SMM Stack Guard. + Initialize IDT IST Field. + + @param[in] ExceptionType Exception type. + @param[in] Ist IST value. =20 **/ VOID EFIAPI -InitializeIDTSmmStackGuard ( - VOID +InitializeIdtIst ( + IN EFI_EXCEPTION_TYPE ExceptionType, + IN UINT8 Ist ) { IA32_IDT_GATE_DESCRIPTOR *IdtGate; =20 - // - // If SMM Stack Guard feature is enabled, set the IST field of - // the interrupt gate for Page Fault Exception to be 1 - // IdtGate =3D (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base; - IdtGate +=3D EXCEPT_IA32_PAGE_FAULT; - IdtGate->Bits.Reserved_0 =3D 1; + IdtGate +=3D ExceptionType; + IdtGate->Bits.Reserved_0 =3D Ist; } =20 /** @@ -89,7 +89,7 @@ InitGdt ( GdtDescriptor->Bits.BaseMid =3D (UINT8)((UINTN)TssBase >> 16); GdtDescriptor->Bits.BaseHigh =3D (UINT8)((UINTN)TssBase >> 24); =20 - if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + if ((FeaturePcdGet (PcdCpuSmmStackGuard)) || ((PcdGet32 (PcdControlFlo= wEnforcementPropertyMask) !=3D 0) && mCetSupported)) { // // Setup top of known good stack as IST1 for each processor. // @@ -177,8 +177,16 @@ InitShadowStack ( =20 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) && mCetSup= ported) { SmmShadowStackSize =3D EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 = (PcdCpuSmmShadowStackSize))); + // + // Add 1 page as known good shadow stack + // + SmmShadowStackSize +=3D EFI_PAGES_TO_SIZE (1); + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - SmmShadowStackSize +=3D EFI_PAGES_TO_SIZE (2); + // + // Add one guard page between Known Good Shadow Stack and SMM Shadow= Stack. + // + SmmShadowStackSize +=3D EFI_PAGES_TO_SIZE (1); } mCetPl0Ssp =3D (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - size= of(UINT64)); PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4); @@ -186,33 +194,32 @@ InitShadowStack ( DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack)); DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSiz= e)); =20 - if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - if (mSmmInterruptSspTables =3D=3D 0) { - mSmmInterruptSspTables =3D (UINTN)AllocateZeroPool(sizeof(UINT64) = * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); - ASSERT (mSmmInterruptSspTables !=3D 0); - DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterru= ptSspTables)); - } - - // - // The highest address on the stack (0xFF8) is a save-previous-ssp t= oken pointing to a location that is 40 bytes away - 0xFD0. - // The supervisor shadow stack token is just above it at address 0xF= F0. This is where the interrupt SSP table points. - // So when an interrupt of exception occurs, we can use SAVESSP/REST= ORESSP/CLEARSSBUSY for the supervisor shadow stack, - // due to the reason the RETF in SMM exception handler cannot clear = the BUSY flag with same CPL. - // (only IRET or RETF with different CPL can clear BUSY flag) - // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for= the full stack frame at runtime. - // - InterruptSsp =3D (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) = - sizeof(UINT64)); - *(UINT64 *)(UINTN)InterruptSsp =3D (InterruptSsp - sizeof(UINT64) * = 4) | 0x2; - mCetInterruptSsp =3D InterruptSsp - sizeof(UINT64); - - mCetInterruptSspTable =3D (UINT32)(UINTN)(mSmmInterruptSspTables + s= izeof(UINT64) * 8 * CpuIndex); - InterruptSspTable =3D (UINT64 *)(UINTN)mCetInterruptSspTable; - InterruptSspTable[1] =3D mCetInterruptSsp; - PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); - PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTab= le, 4); - DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp)); - DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptS= spTable)); + if (mSmmInterruptSspTables =3D=3D 0) { + mSmmInterruptSspTables =3D (UINTN)AllocateZeroPool(sizeof(UINT64) * = 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); + ASSERT (mSmmInterruptSspTables !=3D 0); + DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterrupt= SspTables)); } + + // + // The highest address on the stack (0xFE0) is a save-previous-ssp tok= en pointing to a location that is 40 bytes away - 0xFB8. + // The supervisor shadow stack token is just above it at address 0xFD8= . This is where the interrupt SSP table points. + // So when an interrupt of exception occurs, we can use SAVESSP/RESTOR= ESSP/CLEARSSBUSY for the supervisor shadow stack, + // due to the reason the RETF in SMM exception handler cannot clear th= e BUSY flag with same CPL. + // (only IRET or RETF with different CPL can clear BUSY flag) + // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for t= he full stack frame at runtime. + // According to SDM (ver. 075 June 2021), shadow stack should be 32 by= tes aligned. + // + InterruptSsp =3D (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) -= (sizeof(UINT64) * 4)) & ~0x1f); + *(UINT64 *)(UINTN)InterruptSsp =3D (InterruptSsp - sizeof(UINT64) * 4)= | 0x2; + mCetInterruptSsp =3D InterruptSsp - sizeof(UINT64); + + mCetInterruptSspTable =3D (UINT32)(UINTN)(mSmmInterruptSspTables + siz= eof(UINT64) * 8 * CpuIndex); + InterruptSspTable =3D (UINT64 *)(UINTN)mCetInterruptSspTable; + InterruptSspTable[1] =3D mCetInterruptSsp; + PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); + PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable= , 4); + DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp)); + DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSsp= Table)); } } =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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