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Wed, 10 Nov 2021 22:15:30 +0000 X-Received: from sbrijesh-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 10 Nov 2021 16:15:29 -0600 From: "Brijesh Singh via groups.io" To: CC: James Bottomley , Min Xu , "Jiewen Yao" , Tom Lendacky , "Jordan Justen" , Ard Biesheuvel , Erdem Aktas , "Michael Roth" , Gerd Hoffmann , "Michael D Kinney" , Liming Gao , Zhiguang Liu , Ray Ni , Rahul Kumar , Eric Dong , Michael Roth , Brijesh Singh Subject: [edk2-devel] [PATCH v12 27/32] UefiCpuPkg/MpInitLib: use BSP to do extended topology check Date: Wed, 10 Nov 2021 16:14:52 -0600 Message-ID: <20211110221457.2397234-28-brijesh.singh@amd.com> In-Reply-To: <20211110221457.2397234-1-brijesh.singh@amd.com> References: <20211110221457.2397234-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b079b89d-98f1-4a6d-8db4-08d9a4979bc2 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0238: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,brijesh.singh@amd.com X-Gm-Message-State: bOR2uGbEcbCGbHX5PELb6rfqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1636582537; bh=r9ss54S1Acgau1iy9oMT39Idu79gCqKvdjz3Zyx1360=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=a2n7TyfkXD488wIHMK7a2mCRdHGBGZmvAFVdIlXqIihId1oFT/ETObS33shZv3Y/Lgq BT6XzHT2cWoWZr09dfESB1sL0Lj2JRaPcAlq0J1eO5QHBJk9PDKFfe3RkUf2UqBaNUyCH X76RUU4nhttD5MgQDSOLcMpX11zHKeJfFrk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1636582538568100053 Content-Type: text/plain; charset="utf-8" From: Michael Roth During AP bringup, just after switching to long mode, APs will do some cpuid calls to verify that the extended topology leaf (0xB) is available so they can fetch their x2 APIC IDs from it. In the case of SEV-ES, these cpuid instructions must be handled by direct use of the GHCB MSR protocol to fetch the values from the hypervisor, since a #VC handler is not yet available due to the AP's stack not being set up yet. For SEV-SNP, rather than relying on the GHCB MSR protocol, it is expected that these values would be obtained from the SEV-SNP CPUID table instead. The actual x2 APIC ID (and 8-bit APIC IDs) would still be fetched from hypervisor using the GHCB MSR protocol however, so introducing support for the SEV-SNP CPUID table in that part of the AP bring-up code would only be to handle the checks/validation of the extended topology leaf. Rather than introducing all the added complexity needed to handle these checks via the CPUID table, instead let the BSP do the check in advance, since it can make use of the #VC handler to avoid the need to scan the SNP CPUID table directly, and add a flag in ExchangeInfo to communicate the result of this check to APs. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Suggested-by: Brijesh Singh Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.c | 11 ++++++++ UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 1 + UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 27 ++++++++++++++++++++ 4 files changed, 40 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 45bc1de23e3c..c52b6157429b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -224,6 +224,7 @@ typedef struct { BOOLEAN SevEsIsEnabled; BOOLEAN SevSnpIsEnabled; UINTN GhcbBase; + BOOLEAN ExtTopoAvail; } MP_CPU_EXCHANGE_INFO; =20 #pragma pack() diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index ab838cbc0ff6..d8372ffa9d5a 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -853,6 +853,7 @@ FillExchangeInfoData ( UINTN Size; IA32_SEGMENT_DESCRIPTOR *Selector; IA32_CR4 Cr4; + UINT32 StdRangeMax; =20 ExchangeInfo =3D CpuMpData->MpCpuExchangeInfo; ExchangeInfo->StackStart =3D CpuMpData->Buffer; @@ -892,6 +893,16 @@ FillExchangeInfoData ( ExchangeInfo->SevSnpIsEnabled =3D CpuMpData->SevSnpIsEnabled; ExchangeInfo->GhcbBase =3D (UINTN) CpuMpData->GhcbBase; =20 + if (ExchangeInfo->SevSnpIsEnabled) { + AsmCpuid (CPUID_SIGNATURE, &StdRangeMax, NULL, NULL, NULL); + if (StdRangeMax >=3D CPUID_EXTENDED_TOPOLOGY) { + CPUID_EXTENDED_TOPOLOGY_EBX ExtTopoEbx; + + AsmCpuid (CPUID_EXTENDED_TOPOLOGY, NULL, &ExtTopoEbx.Uint32, NULL, N= ULL); + ExchangeInfo->ExtTopoAvail =3D !!ExtTopoEbx.Bits.LogicalProcessors; + } + } + // // Get the BSP's data of GDT and IDT // diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc index 01668638f245..aba53f57201c 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -94,6 +94,7 @@ struc MP_CPU_EXCHANGE_INFO .SevEsIsEnabled: CTYPE_BOOLEAN 1 .SevSnpIsEnabled CTYPE_BOOLEAN 1 .GhcbBase: CTYPE_UINTN 1 + .ExtTopoAvail: CTYPE_BOOLEAN 1 endstruc =20 MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelPro= cStart) diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index 0034920b2f6b..8bb1161fa0f7 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -118,6 +118,32 @@ SevEsGetApicId: or rax, rdx mov rdi, rax ; RDI now holds the original GHCB GPA =20 + ; + ; For SEV-SNP, the recommended handling for getting the x2APIC ID + ; would be to use the SNP CPUID table to fetch CPUID.00H:EAX and + ; CPUID:0BH:EBX[15:0] instead of the GHCB MSR protocol vmgexits + ; below. + ; + ; To avoid the unecessary ugliness to accomplish that here, the BSP + ; has performed these checks in advance (where #VC handler handles + ; the CPUID table lookups automatically) and cached them in a flag + ; so those checks can be skipped here. + ; + mov eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpIsEnabled)] + cmp al, 1 + jne CheckExtTopoAvail + + ; + ; Even with SEV-SNP, the actual x2APIC ID in CPUID.0BH:EDX + ; fetched from the hypervisor the same way SEV-ES does it. + ; + mov eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (ExtTopoAvail)] + cmp al, 1 + je GetApicIdSevEs + ; The 8-bit APIC ID fallback is also the same as with SEV-ES + jmp NoX2ApicSevEs + +CheckExtTopoAvail: mov rdx, 0 ; CPUID function 0 mov rax, 0 ; RAX register requested or rax, 4 @@ -136,6 +162,7 @@ SevEsGetApicId: test edx, 0ffffh jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero =20 +GetApicIdSevEs: mov rdx, 0bh ; CPUID function 0x0b mov rax, 0c0000000h ; RDX register requested or rax, 4 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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