From nobody Thu May 2 00:10:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+83381+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+83381+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1636105579; cv=none; d=zohomail.com; s=zohoarc; b=XMjkh7WIui0skBIYiWq2y+Cg/kb4V18jKcYgWVCOKyjX+rV+h1MjPPzNrIcSZ5YmFuR/7nwoIc3dNcbQ30hOqQnel48oCZzJ5jU7ryNBDZMcu8aJfq9sdV9WZ/x2HhZNYHPQsCWzJW50eONatj2ookC/Wh25dO9/La78HJgiugo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1636105579; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=QMPbkwNfhhMOrWL1+wT0NTWtCs1F1RYrakV74cosJkQ=; b=fGYhLM4ZKgMVD+W5AH968GLZZnwgLasbdQgySFnoYjGIW8pMS86/R6XnebN8g4WfjY+UFi1gvTdbCRZw5kJwbdTkzAeQogzIChqmGZI4i8FqwXzcT7nPC2ompkwzQ84vZ4zqBLrWhZ8qYw+ynpmYj2rEC0Jeo/FiPblj/+0Rca4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+83381+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1636105579501599.5251244115974; Fri, 5 Nov 2021 02:46:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Q2mrYY1788612xoZ8ch7ujvZ; Fri, 05 Nov 2021 02:46:19 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.3291.1636105577524348002 for ; Fri, 05 Nov 2021 02:46:18 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10158"; a="219068142" X-IronPort-AV: E=Sophos;i="5.87,211,1631602800"; d="scan'208";a="219068142" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2021 02:46:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,211,1631602800"; d="scan'208";a="450749963" X-Received: from ikuox-desk1.gar.corp.intel.com ([10.227.107.18]) by orsmga003.jf.intel.com with ESMTP; 05 Nov 2021 02:46:14 -0700 From: ian.chiu@intel.com To: devel@edk2.groups.io Cc: Ian Chiu , Ian Chiu , Maggie Chu , Ray Ni , Hao A Wu Subject: [edk2-devel] [PATCH v2] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bits Date: Fri, 5 Nov 2021 17:46:09 +0800 Message-Id: <20211105094609.717-1-ian.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ian.chiu@intel.com X-Gm-Message-State: UkJt0Ok9hTvoBUo8MpBQ0w7Xx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1636105579; bh=TwPLfqrNUKW8FJtq/xYQUFviJYXL8Bzuox8K7Rzr71E=; h=Cc:Date:From:Reply-To:Subject:To; b=MCGxLyoD0uI/k0C/EPhjQk2K6nP7IgAbkfjJAplsdoiW5aQnbKGOft0LowKlFZR05Bz Drt7SmyYEj1B6CrJ/Ur5G1iQ/Oe3JUWu5ANuprEyvloLeFXwErCrsY5y29EQGFLbtKrBV IiretAw6IGHd83c83ZZrjPtIFmBTE7r4Td0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1636105581200100002 Content-Type: text/plain; charset="utf-8" From: Ian Chiu REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3703 MMIO base address size will overflow while finding two or more Host controller in the system. Correct it and support 32 and 64 bits address space. Signed-off-by: Ian Chiu Cc: Maggie Chu Cc: Ray Ni Cc: Hao A Wu Reviewed-by: Hao A Wu --- MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 47 +++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/= Bus/Pci/UfsPciHcPei/UfsPciHcPei.c index 447a05b5b2..86f1529eec 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c @@ -76,6 +76,8 @@ InitializeUfsHcPeim ( UINT16 Device; UINT16 Function; UINT32 Size; + UINT64 MmioSize; + UINT32 BarAddr; UINT8 SubClass; UINT8 BaseClass; UFS_HC_PEI_PRIVATE_DATA *Private; @@ -106,6 +108,7 @@ InitializeUfsHcPeim ( Private->PpiList =3D mPpiList; Private->PpiList.Ppi =3D &Private->UfsHostControllerPpi; =20 + BarAddr =3D PcdGet32 (PcdUfsPciHostControllerMmioBase); for (Bus =3D 0; Bus < 256; Bus++) { for (Device =3D 0; Device < 32; Device++) { for (Function =3D 0; Function < 8; Function++) { @@ -119,17 +122,57 @@ InitializeUfsHcPeim ( PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OF= FSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE)= ); PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), 0xFFFFFFFF); Size =3D PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_= BASE_ADDRESSREG_OFFSET)); + + switch (Size & 0x07) { + case 0x0: + // + // Memory space: anywhere in 32 bit address space + // + MmioSize =3D (~(Size & 0xFFFFFFF0)) + 1; + break; + case 0x4: + // + // Memory space: anywhere in 64 bit address space + // + MmioSize =3D Size & 0xFFFFFFF0; + PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_= ADDRESSREG_OFFSET + 4), 0xFFFFFFFF); + Size =3D PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, P= CI_BASE_ADDRESSREG_OFFSET + 4)); + + // + // Fix the length to support some specific 64 bit BAR + // + Size |=3D ((UINT32)(-1) << HighBitSet32 (Size)); + + // + // Calculate the size of 64bit bar + // + MmioSize |=3D LShiftU64 ((UINT64) Size, 32); + MmioSize =3D (~(MmioSize)) + 1; + + // + // Clean the high 32bits of this 64bit BAR to 0 as we only a= llow a 32bit BAR. + // + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE= _ADDRESSREG_OFFSET + 4), 0); + break; + default: + // + // Unknown BAR type + // + ASSERT (FALSE); + continue; + }; // // Assign resource to the Ufs Pci host controller's MMIO BAR. // Enable the Ufs Pci host controller by setting BME and MSE bit= s of PCI_CMD register. // - PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size= * Private->TotalUfsHcs)); + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), BarAddr); PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFF= SET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE)); // // Record the allocated Mmio base address. // - Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D PcdGet32 (PcdUfs= PciHostControllerMmioBase) + Size * Private->TotalUfsHcs; + Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D BarAddr; Private->TotalUfsHcs++; + BarAddr +=3D (UINT32)MmioSize; ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS); } } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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