From nobody Sun Feb 8 10:49:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82825+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82825+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1635453859; cv=none; d=zohomail.com; s=zohoarc; b=ay6fiKTvEpfoJ1Q1e5gDgu2se7669tjuUc3zqLhKp7PXazyacYCQd3wQZNwhuSMOtsxfYZRLxiua/VrzsutWS6aocEWgpNQJnFtPwwvsAnc4n5zOVadxXyIWRIFbsVEgiu/2ClQLM0Ah0BxvpPW7+V4oDUHcEMIdMWA7hr6I21I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635453859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GtvYozGXij5cLHJzaqILyLOwcWBPDrVPKTO6WPqaD+Q=; b=Sah58gzgAmRu3aakCdEmOlrXyecUypPOWyejUKs8NPzq+0SqXsxzeymWqLq07aD5AQacHGyCsQPFd8sSkNW4ypGieulZ5G3ekrESrIKTW5x/b61EXndEVkN5u/exMDFufi52UrmEFh+22/vkR1MyTJyATGNNdoyVFwvmARRmcIc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82825+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1635453859704981.4723432995738; Thu, 28 Oct 2021 13:44:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id M64fYY1788612x6eTpAQ7DYV; Thu, 28 Oct 2021 13:44:19 -0700 X-Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web12.633.1635453858814096427 for ; Thu, 28 Oct 2021 13:44:18 -0700 X-Received: from localhost.localdomain (c-73-27-179-174.hsd1.fl.comcast.net [73.27.179.174]) by linux.microsoft.com (Postfix) with ESMTPSA id D5093208F4E9; Thu, 28 Oct 2021 13:44:17 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D5093208F4E9 From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Nate DeSimone Subject: [edk2-devel] [PATCH v6 06/52] IntelSiliconPkg: Add PCH SPI PPI Date: Thu, 28 Oct 2021 16:42:40 -0400 Message-Id: <20211028204326.645-7-mikuback@linux.microsoft.com> In-Reply-To: <20211028204326.645-1-mikuback@linux.microsoft.com> References: <20211028204326.645-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mikuback@linux.microsoft.com X-Gm-Message-State: DPVqUHtl7U1BRbeS7FqW6ad7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1635453859; bh=vorgRWbyuPf3JP+WG/93LwTYR2XZ4lH6gXZjXy0BqjM=; h=Cc:Date:From:Reply-To:Subject:To; b=CuRy8iQXlj/czaWcwqrWblchQ59e1bQhADFnj2zXW4AaPQ04hGrkb1sNNVTfWLY7Pay JFvDhmoBxqGDijaJt65V8o0kDIsHJe33uFvqE1CF6ykASXa5a0bN/q+fDIXPBPkW4X1Yw H3DVmBWCutpEea5FXhI3jNBDlMWRXzi9WdI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1635453860993100001 Content-Type: text/plain; charset="utf-8" From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 This SPI PPI definition is intended to serve as the single definition for Intel platform and silicon packages. Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Michael Kubacki Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty --- Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h | 25 ++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 3 +++ 2 files changed, 28 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h b/Silicon/Inte= l/IntelSiliconPkg/Include/Ppi/Spi.h new file mode 100644 index 000000000000..b2410bd17300 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/Spi.h @@ -0,0 +1,25 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiSe= rvice pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index fb8391000347..1fa447f37722 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -71,6 +71,9 @@ [Guids] gEdkiiMicrocodeStorageTypeFlashGuid =3D { 0x2cba01b3, 0xd391, 0x4598, { = 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } } =20 [Ppis] + ## Include/Ppi/Spi.h + gPchSpiPpiGuid =3D { 0x104c7177, 0xc2e6, 0x44f0, { 0xae, 0xe3, 0x9d, 0x0= d, 0x9a, 0x52, 0xca, 0xdf } } + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1= , 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } =20 --=20 2.28.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82825): https://edk2.groups.io/g/devel/message/82825 Mute This Topic: https://groups.io/mt/86662277/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-