From nobody Sun Feb 8 14:11:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82831+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82831+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1635453886; cv=none; d=zohomail.com; s=zohoarc; b=mdcN6M41RpKPGap94wl84gU4/artSH4yjERFsNjQS/VFwF7U+/poCbhnMl/yp9rSROV+KyUcZqRQKZiglZCFgRKkEfG/A59PumdRIpKho1yUwYRGosZVhoxjZdgwOkrf29tbScNybn6dqLI42KSa1OyZJfnDh5eJuIiUQR5CDbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635453886; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=446qprQG4WHsbXtjMpe0fwp7IABmHJ8DYRNllQ/i6is=; b=l+LIBH+RBCzzHvMSQ8N6hl+4OWjde4UaX6vFjbP/QmqhHDE0BsadXsHo5EpybPH//aaRFHcFTrBRztc0+tZHNw09ipxfSyTdNTn0WyLS1t7Gv7ZJkyQFm7WxM1U/td4/zU+XOnePjIyfI0J60VsOM2oQTi5rkRamtAnqqwHY054= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82831+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1635453886812510.2931312244906; Thu, 28 Oct 2021 13:44:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id K1DPYY1788612xTeerpsPFNo; Thu, 28 Oct 2021 13:44:46 -0700 X-Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web12.639.1635453886031473821 for ; Thu, 28 Oct 2021 13:44:46 -0700 X-Received: from localhost.localdomain (c-73-27-179-174.hsd1.fl.comcast.net [73.27.179.174]) by linux.microsoft.com (Postfix) with ESMTPSA id 18240208F4E9; Thu, 28 Oct 2021 13:44:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 18240208F4E9 From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller , Benjamin Doron Subject: [edk2-devel] [PATCH v6 12/52] KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Date: Thu, 28 Oct 2021 16:42:46 -0400 Message-Id: <20211028204326.645-13-mikuback@linux.microsoft.com> In-Reply-To: <20211028204326.645-1-mikuback@linux.microsoft.com> References: <20211028204326.645-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mikuback@linux.microsoft.com X-Gm-Message-State: kn1jr8dSi2qqWindJcMwneoax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1635453886; bh=5aIms8/acmlTs5/stU8W3cJzN2jxluobLEwzda2+pZQ=; h=Cc:Date:From:Reply-To:Subject:To; b=QCVP1jNvdJhJPi+yVm0ISWjRgrhrCOEqPoQi2mieN8PmLzD1A6zrKPQLi1YGHdORH2G d2pB5qSsH3HppAer6tZ8lSVreKYkOBFh35l090tQ/KZ9Og1oBUjS5y3F3E4L0dsa3uFOh 6YZVSl8Um50VIflA8oIYXaR2Apk8Pvsg8/M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1635453887647100002 Content-Type: text/plain; charset="utf-8" From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Cc: Benjamin Doron Signed-off-by: Michael Kubacki Reviewed-by: Nate DeSimone Reviewed-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMap= Include.fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf = | 38 ++++++++++---------- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclude= .fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf = | 38 ++++++++++---------- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInclu= de.fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf = | 38 ++++++++++---------- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +-- 9 files changed, 69 insertions(+), 69 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash= 572G/Include/Fdf/FlashMapInclude.fdf index aac4d83f6480..8f6696b7d1fe 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla= shMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla= shMapInclude.fdf @@ -36,8 +36,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00180000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 003C0000 # Flash addr (0xFFDC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00020000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 003E0000 # Flash addr (0xFFDE0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 00080000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 003E0000 # Flash addr (0xFFDE0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 00080000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00460000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 0004C000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 004AC000 # Flash addr (0xFFEAC000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.fdf index 7a926454eaad..36fd0bb733da 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.AspireVn7Dash572G] # assigned with PCD values. Instead, it uses the definitions for its varie= ty, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAdd= ress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAr= eaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSi= ze #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.AspireVn7Dash572G] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to = get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffs= et) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpac= eGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSili= conPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize ##########################################################################= ###### # # Following are lists of FD Region layout which correspond to the location= s of different @@ -155,8 +155,8 @@ [FD.AspireVn7Dash572G] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 4dcc000186ac..1ce26fc3dcec 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -68,11 +68,11 @@ [Guids] =20 [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Pl= atform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf index e5e40144a68a..6607ea6edfc3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -36,8 +36,8 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSU= MES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSU= MES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES =20 [Sources] BiosInfo.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/Fla= shMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/F= df/FlashMapInclude.fdf index 6cb6d54f558f..ce809a277b6e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIn= clude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIn= clude.fdf @@ -36,8 +36,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00140000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 002E0000 # Flash addr (0xFFD00000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 000B0000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 00390000 # Flash addr (0xFFDB0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 00390000 # Flash addr (0xFFDB0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00430000 # Flash addr (0xFFE50000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 00490000 # Flash addr (0xFFEB0000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fd= f b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf index bcd1ade72ba5..39432d21b8b5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.GalagoPro3] # assigned with PCD values. Instead, it uses the definitions for its varie= ty, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAdd= ress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAr= eaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSi= ze #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.GalagoPro3] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to = get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffs= et) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpac= eGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSili= conPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize ##########################################################################= ###### # # Following are lists of FD Region layout which correspond to the location= s of different @@ -155,8 +155,8 @@ [FD.GalagoPro3] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/F= lashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Inclu= de/Fdf/FlashMapInclude.fdf index b5e3f66ceafc..67649e867616 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMap= Include.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMap= Include.fdf @@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 001E0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00370000 # Flash addr (0xFFB70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 004F0000 # Flash addr (0xFFCF0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 004F0000 # Flash addr (0xFFCF0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00590000 # Flash addr (0xFFD90000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 005F0000 # Flash addr (0xFFDF0000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 6cdf4e2f9f1f..f003dda0ddfc 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.KabylakeRvp3] # assigned with PCD values. Instead, it uses the definitions for its varie= ty, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAdd= ress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAr= eaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSi= ze #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.KabylakeRvp3] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to = get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffs= et) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpac= eGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSili= conPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelSil= iconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelSil= iconPkgTokenSpaceGuid.PcdBiosSize ##########################################################################= ###### # # Following are lists of FD Region layout which correspond to the location= s of different @@ -151,8 +151,8 @@ [FD.KabylakeRvp3] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index 4b30ba02ead6..25eae88f5989 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -54,11 +54,11 @@ [Guids] =20 [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES --=20 2.28.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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