From nobody Mon Feb 9 12:25:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82315+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82315+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634503; cv=none; d=zohomail.com; s=zohoarc; b=dv81AFrExCgrXtB3uTtbdXQJfb7EzqUFQZhiCBoZY0oB7qh8QEaVJOa55dB6TtXgW2E1Vr6Cop/GYF3/xjPn/dHeSiImXPoMPmZPJiZ23iLeWhXCgALYTJAjVVsszqB2Z4ul3xav3qyL9suQD0uunNuZIV6S01WpHSO2WX8h+XQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634503; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zZFVyqb5bGmJAegM8dmoHAQLAe/U0muE0IF/J8Yq/yw=; b=GXMQLOxWY6L+d6X3sMWRws6v0rN5wCoFmQN/PmoDpUX5NcxoLWwpdcNWZr8/DwgT52U8lJt2obmZkamRX2+6EYO1PrHgrmubzGkmfQW3Ky/qR6gnToMV3L+Rqf+ehlXNNu4ikgBs4ja5ADJLmH6DDdrlxtYV8fC1XhMlw//WJlQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82315+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634503167943.039081213172; Tue, 19 Oct 2021 02:08:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id iWEbYY1788612xkFOBwe6K61; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.7152.1634634498110023633 for ; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19ILhMZa008004; Tue, 19 Oct 2021 09:08:17 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qrv9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:16 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 6A30C62; Tue, 19 Oct 2021 09:08:16 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 5C13E4B; Tue, 19 Oct 2021 09:08:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Date: Tue, 19 Oct 2021 16:09:40 +0800 Message-Id: <20211019081007.31165-4-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: x2IGIjS1iQCcMGLIipob44dcdj-r4zlO X-Proofpoint-ORIG-GUID: x2IGIjS1iQCcMGLIipob44dcdj-r4zlO X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: kGGylzMkyqC5UcvXJrJM4CeSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634502; bh=xqJXYP8VmnEw4wO//aw7WuQtjX0nUSouZt4mu9tKCa4=; h=Cc:Date:From:Reply-To:Subject:To; b=G2SR0dSO/ZZ7X9ThgCUiJPkjpxTEkx73Nm02CZZXkWdW9HhIaTci8FkCXOMrNPNmuoM 8ik3oK1rqf/ve+0qUUgW7eXIiQ9t9+/dOnSCVqgdiqU6i1s4OV1kBEB2Hm/mzeex066XL MuI2wqxeWsmn5GmaBdtp3cL0+5v79z506ro= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634504760100001 Content-Type: text/plain; charset="utf-8" Incorporate with opensbi to create three firmware domains, - Boot firmware domain, which built with opensbi library as M-mode access only region. - Firmware domain which includes PEI and DXE regions, the PMP attribute is readable, wriable and executable. - EFI Variable region which is readable and writable. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 40 ++++----- .../U540.fdf.inc | 80 +++++++++++++----- .../VarStore.fdf.inc | 8 +- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 9 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 6 +- .../Library/OpensbiPlatformLib/Platform.c | 84 ++++++++++++++++--- .../PlatformPkg/Universal/Sec/SecMain.c | 53 +++++------- .../Universal/Sec/Riscv64/SecEntry.S | 7 +- 8 files changed, 188 insertions(+), 99 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index ad15a155fe..7e41e7bdb2 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -1,7 +1,7 @@ ## @file RiscVPlatformPkg.dec # This Package provides UEFI RISC-V platform modules and libraries. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,33 +31,33 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 016 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 017 - + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 006 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 007 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0= |UINT32|0x00001008 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32= |0x00001009 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UIN= T32|0x0000100a + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0= 000100b + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= |0x0|UINT32|0x0000100c + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UI= NT32|0x0000100d # # Definition of EFI Variable region # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015 -# -# Firmware region which is protected by PMP. -# - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001040 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001041 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001042 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001043 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001044 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001045 + # # Definition of RISC-V Hart # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084 # # The bootable hart core number, which is incorporate with OpenSBI platfor= m hart_index2id value. # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01085 # # Definitions for OpenSbi # @@ -73,7 +73,7 @@ [PcdsPatchableInModule] =20 [PcdsFeatureFlag] - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001200 =20 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] =20 diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 8e7afc2d82..f708f4d8be 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -1,7 +1,7 @@ ## @file # Definitions of Flash definition file on SiFive Freedom U540 HiFive Unle= ashed RISC-V platform # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -10,37 +10,77 @@ DEFINE BLOCK_SIZE =3D 0x1000 =20 DEFINE FW_BASE_ADDRESS =3D 0x80000000 -DEFINE FW_SIZE =3D 0x00820000 -DEFINE FW_BLOCKS =3D 0x820 +DEFINE FW_SIZE =3D 0x00900000 +DEFINE FW_BLOCKS =3D 0x900 =20 # # 0x000000-0x7DFFFF code # 0x7E0000-0x800000 variables # DEFINE CODE_BASE_ADDRESS =3D 0x80000000 -DEFINE CODE_SIZE =3D 0x007E0000 -DEFINE CODE_BLOCKS =3D 0x7E0 +DEFINE CODE_SIZE =3D 0x00800000 +DEFINE CODE_BLOCKS =3D 0x800 DEFINE VARS_BLOCKS =3D 0x20 =20 -DEFINE SECFV_OFFSET =3D 0x00000000 -DEFINE SECFV_SIZE =3D 0x00030000 -DEFINE PEIFV_OFFSET =3D 0x00030000 -DEFINE PEIFV_SIZE =3D 0x00080000 -DEFINE SCRATCH_OFFSET =3D 0x000b0000 -DEFINE SCRATCH_SIZE =3D 0x00010000 -DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng -DEFINE FVMAIN_SIZE =3D 0x0018C000 -DEFINE VARS_OFFSET =3D 0x007E0000 -DEFINE VARS_SIZE =3D 0x00020000 -DEFINE DTB_OFFSET =3D 0x00800000 -DEFINE DTB_SIZE =3D 0x00002000 +# +# SEC + opensbi library is the root FW domain. +# The base address must be round up to log2. +# +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00040000 +DEFINE ROOT_FW_DOMAIN_SIZE =3D $(SECFV_SIZE) + +# +# Other FV regions are in the second FW domain. +# The size of memory region must be power of 2. +# The base address must be aligned with the size. +# +# FW memory region +# +DEFINE PEIFV_OFFSET =3D 0x00400000 +DEFINE PEIFV_SIZE =3D 0x00180000 +DEFINE FVMAIN_OFFSET =3D 0x00580000 +DEFINE FVMAIN_SIZE =3D 0x00280000 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D 0x00800000 +DEFINE VARS_SIZE =3D 0x00007000 +DEFINE VARS_FTW_WORKING_OFFSET =3D 0x00807000 +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00001000 +DEFINE VARS_FTW_SPARE_OFFSET =3D 0x00808000 +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00018000 + +# +# Device Tree memory region +# +DEFINE DTB_OFFSET =3D 0x00840000 +DEFINE DTB_SIZE =3D 0x00002000 + +# +# Scratch area memory region +# +DEFINE SCRATCH_OFFSET =3D 0x00880000 +DEFINE SCRATCH_SIZE =3D 0x00010000 + + +DEFINE FW_DOMAIN_SIZE =3D $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_O= FFSET) +DEFINE VARIABLE_FW_SIZE =3D $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_S= IZE) - $(VARS_OFFSET) + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = =3D $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize = =3D $(ROOT_FW_DOMAIN_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress = =3D $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize = =3D $(FW_DOMAIN_SIZE) =20 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET) -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddre= ss =3D $(CODE_BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = =3D $(VARIABLE_FW_SIZE) =20 -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BAS= E_ADDRESS) -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BAS= E_ADDRESS) + $(SCRATCH_OFFSET) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_= SIZE) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Va= rStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoar= d/VarStore.fdf.inc index c287bb4336..04bddfaa44 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.= fdf.inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.= fdf.inc @@ -1,7 +1,7 @@ ## @file # FDF include file with Layout Regions that define an empty variable stor= e. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# Copyright (C) 2014, Red Hat, Inc. # Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
# @@ -9,7 +9,7 @@ # ## =20 -$(VARS_OFFSET)|0x00007000 +$(VARS_OFFSET)|$(VARS_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize # # NV_VARIABLE_STORE @@ -56,7 +56,7 @@ DATA =3D { 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } =20 -0x007e7000|0x00001000 +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBas= e|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize # #NV_FTW_WROK @@ -72,7 +72,7 @@ DATA =3D { 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } =20 -0x007e8000|0x00018000 +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize # #NV_FTW_SPARE diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index f9f2073a5b..a408737961 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -3,7 +3,7 @@ # This is the the library which provides platform # level opensbi functions follow RISC-V OpenSBI implementation. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -54,3 +54,10 @@ =20 gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock + + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 78bd75e3ac..bcb8b9f908 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -1,7 +1,7 @@ ## @file # RISC-V SEC module. # -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -64,8 +64,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index c4cf6782bd..4fbb201895 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Western Digital Corporation or its affiliates. * * Authors: * Anup Patel @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; } =20 +static int generic_system_reset_check(u32 reset_type, u32 reset_reason) +{ + if (generic_plat && generic_plat->system_reset_check) + return generic_plat->system_reset_check(reset_type, + reset_reason, + generic_plat_match); + return fdt_system_reset_check(reset_type, reset_reason); +} + +static void generic_system_reset(u32 reset_type, u32 reset_reason) +{ + if (generic_plat && generic_plat->system_reset) { + generic_plat->system_reset(reset_type, reset_reason, + generic_plat_match); + return; + } + + fdt_system_reset(reset_type, reset_reason); +} + +#define EDK2_ROOT_FW_REGION 0 +#define EDK2_FW_REGION 1 +#define EDK2_VARIABLE_REGION 2 +#define EDK2_ALL_REGION 3 +#define EDK2_END_REGION 4 +static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 }; + +struct sbi_domain_memregion *get_mem_regions(void) { + /* EDK2 root firmware domain memory region */ + root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize)); + root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress); + root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0; + + /*EDK2 firmware domain memory region */ + root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize)); + root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress); + root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE; + + /*EDK2 firmware domain memory region */ + root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize)); + root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress); + root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE; + + /* EDK2 domain allow everything memory region */ + root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen; + root_memregs[EDK2_ALL_REGION].base =3D 0; + root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE | + SBI_DOMAIN_MEMREGION_WRITEABLE | + SBI_DOMAIN_MEMREGION_EXECUTABLE); + + /* EDK2 domain memory region end */ + root_memregs[EDK2_END_REGION].order =3D 0; + + return root_memregs; +} + const struct sbi_platform_operations platform_ops =3D { - .early_init =3D generic_early_init, - .final_init =3D generic_final_init, - .early_exit =3D generic_early_exit, - .final_exit =3D generic_final_exit, - .domains_init =3D generic_domains_init, - .console_init =3D fdt_serial_init, - .irqchip_init =3D fdt_irqchip_init, - .irqchip_exit =3D fdt_irqchip_exit, - .ipi_init =3D fdt_ipi_init, - .ipi_exit =3D fdt_ipi_exit, + .early_init =3D generic_early_init, + .final_init =3D generic_final_init, + .early_exit =3D generic_early_exit, + .final_exit =3D generic_final_exit, + .domains_root_regions =3D get_mem_regions, + .domains_init =3D generic_domains_init, + .console_init =3D fdt_serial_init, + .irqchip_init =3D fdt_irqchip_init, + .irqchip_exit =3D fdt_irqchip_exit, + .ipi_init =3D fdt_ipi_init, + .ipi_exit =3D fdt_ipi_exit, .get_tlbr_flush_limit =3D generic_tlbr_flush_limit, - .timer_init =3D fdt_timer_init, - .timer_exit =3D fdt_timer_exit, + .timer_init =3D fdt_timer_init, + .timer_exit =3D fdt_timer_exit, }; =20 #if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index e9f030f352..e88a7b8e80 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module. =20 - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -336,7 +336,7 @@ FindAndReportEntryPoints ( =20 **/ VOID -DebutPrintFirmwareContext ( +DebugPrintFirmwareContext ( EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext ) { @@ -398,7 +398,7 @@ TemporaryRamMigration ( // FirmwareContext->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - = (UINTN)OldStack); DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n= ", __FUNCTION__, FirmwareContext)); - DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext); + DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext); =20 register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); asm volatile ("add sp, sp, a0"::"r"(a0):); @@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension ( This function transits to S-mode PEI phase from M-mode SEC phase. =20 @param[in] BootHartId Hardware thread ID of boot hart. - @param[in] FuncArg1 Arg1 delivered from previous phase. + @param[in] Scratch Pointer to sbi_scratch structure. =20 **/ VOID EFIAPI PeiCore ( - IN UINTN BootHartId, - IN UINTN FuncArg1 + IN UINTN BootHartId, + IN struct sbi_scratch *Scratch ) { EFI_SEC_PEI_HAND_OFF SecCoreData; @@ -529,7 +529,7 @@ VOID EFIAPI PeiCore ( // DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - SbiGetMscratchHartid (HartId, &ScratchSpace); + ScratchSpace =3D sbi_hartid_to_scratch (HartId); if(ScratchSpace !=3D NULL) { DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); } @@ -540,9 +540,8 @@ VOID EFIAPI PeiCore ( // Firmware context residents in stack and will be switched to memory wh= en // temporary RAM migration. // - SbiGetMscratchHartid (BootHartId, &ScratchSpace); ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT)); - ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ScratchSpace= ); + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) { DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is new= er than OpenSBI version 0x%x.\n" "There maybe be some backward compatable issues= .\n", @@ -562,13 +561,13 @@ VOID EFIAPI PeiCore ( // // Save Flattened Device tree in firmware context // - FirmwareContext.FlattenedDeviceTree =3D FuncArg1; + FirmwareContext.FlattenedDeviceTree =3D Scratch->next_arg1; =20 // // Set firmware context Hart-specific pointer // for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - SbiGetMscratchHartid (HartId, &ScratchSpace); + ScratchSpace =3D sbi_hartid_to_scratch (HartId); if (ScratchSpace !=3D NULL) { FirmwareContext.HartSpecific[HartId] =3D (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); @@ -588,6 +587,10 @@ VOID EFIAPI PeiCore ( // // Transfer the control to the PEI core // + Scratch->next_addr =3D (UINTN)(*PeiCoreEntryPoint); + Scratch->next_mode =3D PRV_S; + DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %= d\n", __FUNCTION__, BootHartId)); + sbi_init(Scratch); (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable); } =20 @@ -598,34 +601,19 @@ VOID EFIAPI PeiCore ( To register the SBI extension we stay in M-Mode and then transition here, rather than before in sbi_init. =20 - @param[in] ThisHartId Hardware thread ID. - @param[in] FuncArg1 Arg1 delivered from previous phase. + @param[in] ThisHartId Hardware thread ID. + @param[in] Scratch Pointer to sbi_scratch structure. =20 **/ VOID EFIAPI LaunchPeiCore ( IN UINTN ThisHartId, - IN UINTN FuncArg1 + IN struct sbi_scratch *Scratch ) { - UINT32 PeiCoreMode; - - DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__)); - atomic_write (&BootHartDone, (UINT64)TRUE); RegisterFirmwareSbiExtension (); - - PeiCoreMode =3D FixedPcdGet32 (PcdPeiCorePrivilegeMode); - if (PeiCoreMode =3D=3D PRV_S) { - DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION_= _)); - sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FAL= SE); - } else if (PeiCoreMode =3D=3D PRV_M) { - DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION_= _)); - PeiCore (ThisHartId, FuncArg1); - } else { - DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePri= vilegeMode is not supported.\n", __FUNCTION__)); - while (TRUE); - } + PeiCore (ThisHartId, Scratch); } =20 /** @@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack( HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode; =20 if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { - Scratch->next_addr =3D (UINTN)LaunchPeiCore; - Scratch->next_mode =3D PRV_M; - DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart= %d\n", __FUNCTION__, HartId)); - sbi_init(Scratch); + LaunchPeiCore (HartId, Scratch); } =20 // diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index a8157c896e..0a69c50065 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. + * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. * * SPDX-License-Identifier: BSD-2-Clause * @@ -71,9 +71,8 @@ _scratch_init: /* Initialize scratch space */ =20 /* Firmware range and size */ - li a4, FixedPcdGet32 (PcdFwStartAddress) - li a5, FixedPcdGet32 (PcdFwEndAddress) - sub a5, a5, a4 + li a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress) + li a5, FixedPcdGet32 (PcdRootFirmwareDomainSize) sd a4, SBI_SCRATCH_FW_START_OFFSET(tp) sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82315): https://edk2.groups.io/g/devel/message/82315 Mute This Topic: https://groups.io/mt/86435665/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-