From nobody Mon Feb 9 03:13:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82342+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82342+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634538; cv=none; d=zohomail.com; s=zohoarc; b=VRx5Ff2UbMXSnlkVOdGuMFFm7jXP56Iru9hRukNdzk8bX6VxqWldeI2gBIh1w/ACPr6RLlWnJoN5QgdVRm12us2ILT23yJoU8iRfk9g/zQtMBK1/6xZz+F3lL6cFPOtwtMNBEP0QatMGTx6r7Logwcz1qQplYhcf/1Cx80CtLY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634538; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PDo07DH0qYjGDocmFO4NDPD9uY/LzayrU+hCuFxJKtc=; b=MbqcxnUrJHIScpkb3xF3ZpBJu4NHFVOqRPUiIUctVjg1gWVKkWqV7tYDZEXGfRX4OhCswvvlTQuEOeeciYkgCuMeYXxJv4dnNM1XEiGRfvgrzpzf8X/pXA07G3S049fE+77qx2e7ABPeoDYwkEQjpyXg+aYYUqRs/lQYs1k1F3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82342+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634538691921.1697206921258; Tue, 19 Oct 2021 02:08:58 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hkVKYY1788612xjlh2cwjQ3K; Tue, 19 Oct 2021 02:08:58 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7408.1634634534030076795 for ; Tue, 19 Oct 2021 02:08:57 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8W5Mc018505; Tue, 19 Oct 2021 09:08:53 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 3bseymmq25-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:53 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id D2EE556; Tue, 19 Oct 2021 09:08:52 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id C559C48; Tue, 19 Oct 2021 09:08:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Date: Tue, 19 Oct 2021 16:10:06 +0800 Message-Id: <20211019081007.31165-30-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-Proofpoint-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 7YozKZGO2NdPJkHtfQVRYxkZx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634538; bh=gCBaeHrr1ct9dfs19ka2Al1Wt7XaNyi/VvufwKckqcQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ngBTU1JS8/NAcclN2xSkHYvITJvZiFfcI5LD1NEv1hxLhFjxMtXRi0LGmmhSTJ/8kNW Gl54GqRgZERgJyRGbOKSTY/Fd3r3TBa2TbmTGUewaGAHNIP7Se0j4c17EVKHO2djbJiwN gmsppq1d7DtY5VLiqxbvhHtpk2CfZ3owLm4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634540309100003 Content-Type: text/plain; charset="utf-8" Determine total number of hart from DTB instead of using PCD. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../U540.fdf.inc | 1 - .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 - .../PlatformPkg/Universal/Sec/SecMain.inf | 1 - .../PlatformPkg/Universal/Sec/SecMain.c | 12 ++-- .../Universal/Sec/Riscv64/SecEntry.S | 60 +++++++++++++------ 5 files changed, 49 insertions(+), 28 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 1a525dc874..404c0b71ca 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -90,7 +90,6 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSi= ze =3D 0x10000 =20 SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz =3D= 1000000 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock =3D= 1000000000 # 1GHz system clock -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D= 5 # Total cores on U540 platform SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D= 1 # Boot hart ID =20 # diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 2e1227733a..6661ee8204 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -46,9 +46,6 @@ RiscVSpecialPlatformLib =20 [FixedPcd] - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =20 =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index ceb6d25222..b949b6c470 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -61,7 +61,6 @@ =20 [Pcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index f2b2c7b583..17f33a02cc 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -530,7 +530,7 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection; =20 if (FixedPcdGet32 (PcdDeviceTreeAddress)) { - DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress))); + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *= )FixedPcdGet32 (PcdDeviceTreeAddress)))); // // Device tree address is pointed by PcdDeviceTreeAddress. // @@ -647,11 +647,10 @@ VOID EFIAPI SecCoreStartUpWithStack( // ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { - - Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart= \n")); ASSERT (FALSE); } DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1)); @@ -685,6 +684,11 @@ VOID EFIAPI SecCoreStartUpWithStack( NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, T= RUE); }; DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION_= _, HartId)); + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); + ASSERT (FALSE); + } + DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION_= _, HartId, Scratch->next_arg1)); NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, FAL= SE); // // Non boot hart wiil be halted waiting for SBI_HART_STARTING. diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 96087738a3..0fc7817665 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -37,14 +37,39 @@ ASM_FUNC (_ModuleEntryPoint) li a5, FixedPcdGet32 (PcdBootHartId) bne a6, a5, _wait_for_boot_hart =20 - li ra, 0 - call _reset_regs + /* + * Initial the hart count reported in DTB + */ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) =20 + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + /* Get the address of device tree and call generic fw_platform_init */ + call GetDeviceTreeAddress /* a0 return the device tree address */ + beqz a0, skip_fw_init + add a1, a0, 0 /* a1 is device tree */ + csrr a0, CSR_MHARTID /* a0 is boot hart ID */ + call fw_platform_init +skip_fw_init: /* Preload HART details - * s7 -> HART Count + * s7 -> Total HART count from PCD or DTB * s8 -> HART Stack Size */ - li s7, FixedPcdGet32 (PcdHartCount) + la a0, platform +#if __riscv_xlen =3D=3D 64 + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0) +#else + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0) +#endif + /* + * This is the number of HARTs described in + * DTB for this processor. We allocate the + * scratch buffer according to this number. + */ + la a4, _pysical_hart_count + sd s7, (a4) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) =20 /* @@ -113,20 +138,9 @@ _scratch_init: =20 li a4, FixedPcdGet32 (PcdTemporaryRamBase) li a5, FixedPcdGet32 (PcdTemporaryRamSize) - /* Use Temp memory as the stack for calling to C code */ add sp, a4, a5 - /* Get the address of device tree and call generic fw_platform_init */ - call GetDeviceTreeAddress /* a0 return the device tree address */ - beqz a0, skip_fw_init - add a1, a0, 0 /* a1 is device tree */ - csrr a0, CSR_MHARTID /* a0 is hart ID */ - call fw_platform_init -skip_fw_init: - /* Zero out temporary memory */ - li a4, FixedPcdGet32 (PcdTemporaryRamBase) - li a5, FixedPcdGet32 (PcdTemporaryRamSize) add a5, a4, a5 1: li a3, 0x0 @@ -167,7 +181,11 @@ _start_warm: li s7, FixedPcdGet32 (PcdBootableHartNumber) bnez s7, 1f la a4, platform - REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#if __riscv_xlen =3D=3D 64 + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#else + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#endif 1: li s8, FixedPcdGet32 (PcdOpenSbiStackSize) la a4, platform @@ -209,7 +227,8 @@ _start_warm: csrr a0, CSR_MHARTID j _uninitialized_hart_wait 4: - li s7, FixedPcdGet32 (PcdHartCount) + la a5, _pysical_hart_count + ld s7, (a5) /* Find the scratch space for this hart * * Scratch buffer is on the top of stack buffer @@ -275,6 +294,8 @@ _start_warm: .section .data, "aw" _boot_hart_done: RISCV_PTR 0 +_pysical_hart_count: + RISCV_PTR 0 =20 .align 3 .section .entry, "ax", %progbits @@ -293,7 +314,7 @@ _hartid_to_scratch: /* * s0 -> HART Stack Size * s1 -> HART Stack End - * s2 -> Temporary + * s2 -> Total hart count */ la s2, platform #if __riscv_xlen =3D=3D 64 @@ -301,8 +322,9 @@ _hartid_to_scratch: #else lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) #endif - li s2, FixedPcdGet32 (PcdHartCount) =20 + la s1, _pysical_hart_count /* total HART count */ + ld s2, (s1) mul s2, s2, s0 li s1, FixedPcdGet32 (PcdScratchRamBase) add s1, s1, s2 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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