From nobody Mon Feb 9 01:16:22 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82338+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82338+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634534; cv=none; d=zohomail.com; s=zohoarc; b=YBNCkVfa6kbmuxEs9i6sBG4Cjpzd1L1wJFVFueBbZUkcaa7PbQcoZZC2zqufx3XCA87KOm8T0RTT0LL19YT11EzLXraGwnwtEHDRn++IkgCe9EOaoDOVFBBmetA1nqqTKlW3CPpq4YaPKR5MoCtnSH39e5+dpYbbDOOgEfC/B/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634534; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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Tue, 19 Oct 2021 09:08:51 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:50 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 13EFA9A; Tue, 19 Oct 2021 09:08:50 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 050B756; Tue, 19 Oct 2021 09:08:48 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Date: Tue, 19 Oct 2021 16:10:04 +0800 Message-Id: <20211019081007.31165-28-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-Proofpoint-ORIG-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: YU7HI2Ab1SFYAJRJ7muTi7DWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634533; bh=CBpzhdu5YwzquNfKCvvjYLyZhJfDsagAEhnD4FPRF/k=; h=Cc:Date:From:Reply-To:Subject:To; b=Sz2l6e0cB1qw5jDwxrV8XAcu3wHdRDkyO0vmkgedfg2nFpWZqoFL7V+mpowr0zv7MXr 6P49XV9bohdNY9/FJFHoXk9wdy6a/kr3C4Bc834QKIck9JGrIGkvtcGLxvmGI/Hk12Gbs 2VB8sWwVHE6p954ffqMnwctACdMulg6KgEU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634536123100011 Content-Type: text/plain; charset="utf-8" Code changes to incorporate with OpenSBI commit ID: a731c7e36988c3308e1978ecde491f2f6182d490 Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 4 + .../Library/OpensbiPlatformLib/Platform.c | 57 ---- .../Universal/Sec/Edk2OpenSbiPlatform.c | 149 --------- .../PlatformPkg/Universal/Sec/SecMain.c | 48 ++- .../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++-------- 6 files changed, 212 insertions(+), 356 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 909fbffa8d..2e1227733a 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -51,12 +51,4 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =20 - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock - - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize + diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 1cfbef961f..dd5f01ab4d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -66,6 +66,10 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index b477b81d74..c62d235333 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; } =20 -static int generic_system_reset_check(u32 reset_type, u32 reset_reason) -{ - if (generic_plat && generic_plat->system_reset_check) - return generic_plat->system_reset_check(reset_type, - reset_reason, - generic_plat_match); - return fdt_system_reset_check(reset_type, reset_reason); -} - -static void generic_system_reset(u32 reset_type, u32 reset_reason) -{ - if (generic_plat && generic_plat->system_reset) { - generic_plat->system_reset(reset_type, reset_reason, - generic_plat_match); - return; - } - - fdt_system_reset(reset_type, reset_reason); -} - -#define EDK2_ROOT_FW_REGION 0 -#define EDK2_FW_REGION 1 -#define EDK2_VARIABLE_REGION 2 -#define EDK2_ALL_REGION 3 -#define EDK2_END_REGION 4 -static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 }; - -struct sbi_domain_memregion *get_mem_regions(void) { - /* EDK2 root firmware domain memory region */ - root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize)); - root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress); - root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0; - - /*EDK2 firmware domain memory region */ - root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize)); - root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress); - root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE; - - /*EDK2 firmware domain memory region */ - root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize)); - root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress); - root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE; - - /* EDK2 domain allow everything memory region */ - root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen; - root_memregs[EDK2_ALL_REGION].base =3D 0; - root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE | - SBI_DOMAIN_MEMREGION_WRITEABLE | - SBI_DOMAIN_MEMREGION_EXECUTABLE); - - /* EDK2 domain memory region end */ - root_memregs[EDK2_END_REGION].order =3D 0; - - return root_memregs; -} - const struct sbi_platform_operations platform_ops =3D { .early_init =3D generic_early_init, .final_init =3D generic_final_init, .early_exit =3D generic_early_exit, .final_exit =3D generic_final_exit, - .domains_root_regions =3D get_mem_regions, .domains_init =3D generic_domains_init, .console_init =3D fdt_serial_init, .irqchip_init =3D fdt_irqchip_init, diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.= c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c index 79b2f33675..779705489c 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c @@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID) return 0; } =20 -/** Get platform specific root domain memory regions */ -struct sbi_domain_memregion * -Edk2OpensbiPlatformGetMemRegions (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.domains_root_regions) { - return platform_ops.domains_root_regions (); - } - return 0; -} - /** Initialize (or populate) domains for the platform */ int Edk2OpensbiPlatformDomainsInit (VOID) { @@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID) return 0; } =20 -/** Write a character to the platform console output */ -VOID Edk2OpensbiPlatformSerialPutc ( - CHAR8 Ch - ) -{ - if (platform_ops.console_putc) { - return platform_ops.console_putc (Ch); - } -} - -/** Read a character from the platform console input */ -int Edk2OpensbiPlatformSerialGetc (VOID) -{ - if (platform_ops.console_getc) { - return platform_ops.console_getc (); - } - return 0; -} - /** Initialize the platform console */ int Edk2OpensbiPlatformSerialInit (VOID) { @@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID) } } =20 -/** Send IPI to a target HART */ -VOID Edk2OpensbiPlatformIpiSend ( - UINT32 TargetHart - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_send) { - return platform_ops.ipi_send (TargetHart); - } -} - -/** Clear IPI for a target HART */ -VOID Edk2OpensbiPlatformIpiClear ( - UINT32 TargetHart - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_clear) { - return platform_ops.ipi_clear (TargetHart); - } -} - /** Initialize IPI for current HART */ int Edk2OpensbiPlatformIpiInit ( BOOLEAN ColdBoot @@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID) return 0; } =20 -/** Get platform timer value */ -UINT64 Edk2OpensbiPlatformTimerValue (VOID) -{ - if (platform_ops.timer_value) { - return platform_ops.timer_value (); - } - return 0; -} - -/** Start platform timer event for current HART */ -VOID Edk2OpensbiPlatformTimerEventStart ( - UINT64 NextEvent - ) -{ - if (platform_ops.timer_event_start) { - return platform_ops.timer_event_start (NextEvent); - } -} - -/** Stop platform timer event for current HART */ -VOID Edk2OpensbiPlatformTimerEventStop (VOID) -{ - if (platform_ops.timer_event_stop) { - return platform_ops.timer_event_stop (); - } -} - /** Initialize platform timer for current HART */ int Edk2OpensbiPlatformTimerInit ( BOOLEAN ColdBoot @@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID) } } =20 -/** Bringup the given hart */ -int Edk2OpensbiPlatformHartStart ( - UINT32 HartId, - ulong Saddr - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.hart_start) { - return platform_ops.hart_start (HartId, Saddr); - } - return 0; -} -/** - Stop the current hart from running. This call doesn't expect to - return if success. -**/ -int Edk2OpensbiPlatformHartStop (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.hart_stop) { - return platform_ops.hart_stop (); - } - return 0; -} - -/** - Check whether reset type and reason supported by the platform* - -**/ -int Edk2OpensbiPlatformSystemResetCheck ( - UINT32 ResetType, - UINT32 ResetReason - ) -{ - if (platform_ops.system_reset_check) { - return platform_ops.system_reset_check (ResetType, ResetReason); - } - return 0; -} - -/** Reset the platform */ -VOID Edk2OpensbiPlatformSystemReset ( - UINT32 ResetType, - UINT32 ResetReason - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.system_reset) { - return platform_ops.system_reset (ResetType, ResetReason); - } -} - /** platform specific SBI extension implementation probe function */ int Edk2OpensbiPlatformVendorExtCheck ( long ExtId @@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatf= ormOps =3D { .final_exit =3D Edk2OpensbiPlatformFinalExit, .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension, .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN, - .domains_root_regions =3D Edk2OpensbiPlatformGetMemRegions, .domains_init =3D Edk2OpensbiPlatformDomainsInit, - .console_putc =3D Edk2OpensbiPlatformSerialPutc, - .console_getc =3D Edk2OpensbiPlatformSerialGetc, .console_init =3D Edk2OpensbiPlatformSerialInit, .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit, .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit, - .ipi_send =3D Edk2OpensbiPlatformIpiSend, - .ipi_clear =3D Edk2OpensbiPlatformIpiClear, .ipi_init =3D Edk2OpensbiPlatformIpiInit, .ipi_exit =3D Edk2OpensbiPlatformIpiExit, .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit, - .timer_value =3D Edk2OpensbiPlatformTimerValue, - .timer_event_stop =3D Edk2OpensbiPlatformTimerEventStop, - .timer_event_start =3D Edk2OpensbiPlatformTimerEventStart, .timer_init =3D Edk2OpensbiPlatformTimerInit, .timer_exit =3D Edk2OpensbiPlatformTimerExit, - .hart_start =3D Edk2OpensbiPlatformHartStart, - .hart_stop =3D Edk2OpensbiPlatformHartStop, - .system_reset_check =3D Edk2OpensbiPlatformSystemResetCheck, - .system_reset =3D Edk2OpensbiPlatformSystemReset, .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck, .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider, }; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 93ff8a598d..3bc3690047 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -15,10 +15,12 @@ #include #include #include // Reference to header file in opensbi +#include #include // Reference to header file in opensbi -#include // Reference to header file in opensbi +#include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi +#include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi @@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatfor= mOps; atomic_t BootHartDone =3D ATOMIC_INITIALIZER(0); atomic_t NonBootHartMessageLock =3D ATOMIC_INITIALIZER(0); =20 +int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg); + typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartinde= x); =20 +struct sbi_domain_memregion fw_memregs; + +int SecSetEdk2FwMemoryRegions (VOID) { + int Ret; + + Ret =3D 0; + + // + // EDK2 PEI domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdFirmwareDomainSize)); + fw_memregs.base =3D FixedPcdGet32(PcdFirmwareDomainBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE; + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__)); + } + + // + // EDK2 EFI Variable domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdVariableFirmwareRegion= Size)); + fw_memregs.base =3D FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE; + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__)); + } + return Ret; +} + /** Locates a section within a series of sections with the specified section type. @@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit( DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); return 0; } + // + // Setup firmware memory region. + // + if (SecSetEdk2FwMemoryRegions () !=3D 0) { + ASSERT (FALSE); + } + // // Boot HART is already in the process of OpenSBI initialization. // We can let other HART to keep booting. @@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit ( } } =20 - DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__)); + DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUN= CTION__)); DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch)); DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform)); DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext)); @@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch); } =20 -void OpensbiDebugPrint (char *debugstr, ...) +VOID OpensbiDebugPrint (CHAR8 *debugstr, ...) { VA_LIST Marker; =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index dc410703e0..96087738a3 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -18,6 +18,12 @@ =20 #include =20 +.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2 + add \__d0, \__s0, zero + add \__d1, \__s1, zero + add \__d2, \__s2, zero +.endm + .text .align 3 =20 @@ -90,7 +96,11 @@ _scratch_init: la a4, _hartid_to_scratch sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_sc= ratch function in scratch buffer*/ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp) - + /* Store trap-exit function address in scratch space */ + lla a4, _trap_exit + sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp) + /* Clear tmp0 in scratch space */ + sd zero, SBI_SCRATCH_TMP0_OFFSET(tp) #ifdef FW_OPTIONS li a4, FW_OPTIONS sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp) @@ -322,160 +332,174 @@ _uninitialized_hart_wait: wfi j _uninitialized_hart_wait =20 - .align 3 - .section .entry, "ax", %progbits - .align 3 - .globl _trap_handler -_trap_handler: - +.macro TRAP_SAVE_AND_SETUP_SP_T0 /* Swap TP and MSCRATCH */ - csrrw tp, CSR_MSCRATCH, tp + csrrw tp, CSR_MSCRATCH, tp =20 /* Save T0 in scratch space */ - REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp) + REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp) =20 - /* Check which mode we came from */ - csrr t0, CSR_MSTATUS - srl t0, t0, MSTATUS_MPP_SHIFT - and t0, t0, PRV_M - xori t0, t0, PRV_M - beq t0, zero, _trap_handler_m_mode - - /* We came from S-mode or U-mode */ -_trap_handler_s_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Setup exception stack */ - add sp, tp, -(SBI_TRAP_REGS_SIZE) - - /* Jump to code common for all modes */ - j _trap_handler_all_mode - - /* We came from M-mode */ -_trap_handler_m_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Re-use current SP as exception stack */ - add sp, sp, -(SBI_TRAP_REGS_SIZE) - -_trap_handler_all_mode: - /* Save original SP (from T0) on stack */ - REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp) + /* + * Set T0 to appropriate exception stack + * + * Came_From_M_Mode =3D ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1; + * Exception_Stack =3D TP ^ (Came_From_M_Mode & (SP ^ TP)) + * + * Came_From_M_Mode =3D 0 =3D=3D> Exception_Stack =3D TP + * Came_From_M_Mode =3D -1 =3D=3D> Exception_Stack =3D SP + */ + csrr t0, CSR_MSTATUS + srl t0, t0, MSTATUS_MPP_SHIFT + and t0, t0, PRV_M + slti t0, t0, PRV_M + add t0, t0, -1 + xor sp, sp, tp + and t0, t0, sp + xor sp, sp, tp + xor t0, tp, t0 + + /* Save original SP on exception stack */ + REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0) + + /* Set SP to exception stack and make room for trap registers */ + add sp, t0, -(SBI_TRAP_REGS_SIZE) =20 /* Restore T0 from scratch space */ - REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp) + REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp) =20 /* Save T0 on stack */ - REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp) =20 /* Swap TP and MSCRATCH */ - csrrw tp, CSR_MSCRATCH, tp + csrrw tp, CSR_MSCRATCH, tp +.endm =20 +.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush /* Save MEPC and MSTATUS CSRs */ - csrr t0, CSR_MEPC - REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) - csrr t0, CSR_MSTATUS - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) - REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) -#if __riscv_xlen =3D=3D 32 - csrr t0, CSR_MISA - srli t0, t0, ('H' - 'A') - andi t0, t0, 0x1 - beq t0, zero, _skip_mstatush_save - csrr t0, CSR_MSTATUSH - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) -_skip_mstatush_save: -#endif + csrr t0, CSR_MEPC + REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrr t0, CSR_MSTATUS + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) +.if \have_mstatush + csrr t0, CSR_MSTATUSH + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) +.else + REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) +.endif +.endm + +.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0 + /* Save all general regisers except SP and T0 */ + REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) + REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp) + REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp) +.endm + +.macro TRAP_CALL_C_ROUTINE + /* Call C routine */ + add a0, sp, zero + call sbi_trap_handler +.endm + +.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0 + /* Restore all general regisers except A0 and T0 */ + REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0) + REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0) + REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0) + REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0) + REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0) + REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0) + REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0) + REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0) + REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0) + REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0) + REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0) + REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0) + REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0) + REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0) + REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0) + REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0) + REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0) + REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0) + REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0) + REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0) + REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0) + REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0) + REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0) + REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0) + REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0) + REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0) + REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0) + REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0) + REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0) +.endm + +.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush + /* Restore MEPC and MSTATUS CSRs */ + REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0) + csrw CSR_MEPC, t0 + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0) + csrw CSR_MSTATUS, t0 +.if \have_mstatush + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0) + csrw CSR_MSTATUSH, t0 +.endif +.endm + +.macro TRAP_RESTORE_A0_T0 + /* Restore T0 */ + REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0) =20 - /* Save all general registers except SP and T0 */ - REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) - REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) - REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp) - REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp) - REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp) - REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp) - REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp) - REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp) - REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp) - REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp) - REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp) - REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp) - REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp) - REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp) - REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp) - REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp) - REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp) - REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp) - REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp) - REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp) - REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp) - REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp) - REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp) - REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp) - REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp) - REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp) - REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp) - REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp) - REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp) - REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + /* Restore A0 */ + REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0) +.endm =20 - /* Call C routine */ - add a0, sp, zero - call sbi_trap_handler - - /* Restore all general registers except SP and T0 */ - REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp) - REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp) - REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp) - REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp) - REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp) - REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp) - REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp) - REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp) - REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp) - REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp) - REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp) - REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp) - REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp) - REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp) - REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp) - REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp) - REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp) - REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp) - REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp) - REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp) - REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp) - REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp) - REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp) - REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp) - REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp) - REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp) - REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp) - REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp) - REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + .section .entry, "ax", %progbits + .align 3 + .globl _trap_handler + .globl _trap_exit +_trap_handler: + TRAP_SAVE_AND_SETUP_SP_T0 =20 - /* Restore MEPC and MSTATUS CSRs */ - REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) - csrw CSR_MEPC, t0 - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) - csrw CSR_MSTATUS, t0 -#if __riscv_xlen =3D=3D 32 - csrr t0, CSR_MISA - srli t0, t0, ('H' - 'A') - andi t0, t0, 0x1 - beq t0, zero, _skip_mstatush_restore - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) - csrw CSR_MSTATUSH, t0 -_skip_mstatush_restore: -#endif + TRAP_SAVE_MEPC_MSTATUS 0 =20 - /* Restore T0 */ - REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0 + + TRAP_CALL_C_ROUTINE + +_trap_exit: + TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0 + + TRAP_RESTORE_MEPC_MSTATUS 0 =20 - /* Restore SP */ - REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp) + TRAP_RESTORE_A0_T0 =20 mret =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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