From nobody Mon Feb 9 02:28:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82319+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82319+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634506; cv=none; d=zohomail.com; s=zohoarc; b=XNMz+VbU8Ro2ctj9XB/4bdhFXDBGJ1iAmhE45ABdGqTYvUbCfQHpi3Q2iFFZObqh21dzr1lG97lhe5DABXuDQjbrhgm+b5MAlCA4lIEOgNs79x1KM0WSInrKZzc2IDTzelk/6blTaKoClPgtGu20xII4j2lbHp8JoloO//88TUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634506; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1ZFKtb4eEGq9XtSuzCK9M2Wu6tr7m438h8VtSTbHgs0=; b=U9GYJwhQwIxaADaFIj+6oFKuw/1KPh/JHDCXtystnrr/XqbbGXsjMnIenO5v8F70d3q8vWsZF02Z9e8ZOlCYt0f4smwivP0dTYRDfuZdg011Zam4RxuWktDGAryCRd2uk5o/lwSniB3AJGCutXmOUNissq1vfQ5HlJBXsBViDdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82319+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634506792308.9672105768685; Tue, 19 Oct 2021 02:08:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ySkgYY1788612x30yyNzF2et; Tue, 19 Oct 2021 02:08:26 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7305.1634634505981371978 for ; Tue, 19 Oct 2021 02:08:26 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J86nB2022318; Tue, 19 Oct 2021 09:08:25 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bst7b8g68-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:25 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id C4D5C62; Tue, 19 Oct 2021 09:08:24 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id B527648; Tue, 19 Oct 2021 09:08:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Date: Tue, 19 Oct 2021 16:09:46 +0800 Message-Id: <20211019081007.31165-10-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-Proofpoint-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: MZuALcKJV8NjxAHCEc67pL3Ex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634506; bh=YM+Tz6BbklRmnrycOtsugTSL6b5ayWzOBr/OC24etkk=; h=Cc:Date:From:Reply-To:Subject:To; b=DYh/QmFjYYF9iLiZ+Br5lUaOctgDi7QSazdH2V2t6J8Dp1EJab/gD01TvGRqkHieUcm zsf7DS7E0p90rw2yg6HM8NE+Q2hLkEQd4RciiJxd6TczRy6ewkRkJqJ7BEzxmT/CtrY0r UtiZfvXqHNF4ChLJGL3uaGE6ugBqqpOxYVA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634507183100020 Content-Type: text/plain; charset="utf-8" Add CLINT to Device Tree on U540 platform for M-mode timer and IPI. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../DeviceTree/fu540-c000.dtsi | 591 +++++++++--------- 1 file changed, 304 insertions(+), 287 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/DeviceTree/fu540-c000.dtsi index e44b6f7c56..1d8518cfb7 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi @@ -1,287 +1,304 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -/*#include */ -#include "sifive-fu540-prci.h" - -/ { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - ethernet0 =3D ð0; - }; - - chosen { - }; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - cpu0: cpu@0 { - compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <16384>; - reg =3D <0>; - riscv,isa =3D "rv64imac"; - status =3D "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <1>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <2>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <3>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <4>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells =3D <1>; - compatible =3D "sifive,plic-1.0.0"; - reg =3D <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev =3D <53>; - interrupt-controller; - interrupts-extended =3D < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible =3D "sifive,fu540-c000-prci"; - reg =3D <0x0 0x10000000 0x0 0x1000>; - clocks =3D <&hfclk>, <&rtcclk>; - #clock-cells =3D <1>; - }; - uart0: serial@10010000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10010000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <4>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - dma: dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; - reg =3D <0x0 0x3000000 0x0 0x8000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <23 24 25 26 27 28 29 30>; - #dma-cells =3D <1>; - }; - uart1: serial@10011000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10011000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <5>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - i2c0: i2c@10030000 { - compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg =3D <0x0 0x10030000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <50>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - reg-shift =3D <2>; - reg-io-width =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi0: spi@10040000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <51>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi1: spi@10041000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <52>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi2: spi@10050000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10050000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <6>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - eth0: ethernet@10090000 { - compatible =3D "sifive,fu540-c000-gem"; - interrupt-parent =3D <&plic0>; - interrupts =3D <53>; - reg =3D <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address =3D [00 00 00 00 00 00]; - clock-names =3D "pclk", "hclk"; - clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - pwm0: pwm@10020000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10020000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <42 43 44 45>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - pwm1: pwm@10021000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10021000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <46 47 48 49>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible =3D "sifive,fu540-c000-ccache", "cache"; - cache-block-size =3D <64>; - cache-level =3D <2>; - cache-sets =3D <1024>; - cache-size =3D <2097152>; - cache-unified; - interrupt-parent =3D <&plic0>; - interrupts =3D <1 2 3>; - reg =3D <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent =3D <&plic0>; - interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg =3D <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells =3D <2>; - interrupt-controller; - #interrupt-cells =3D <2>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - }; -}; +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +/**@file + SiFive U540 platform Device Tree + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "sifive-fu540-prci.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + ethernet0 =3D ð0; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu@0 { + compatible =3D "sifive,e51", "sifive,rocket0", "ri= scv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + status =3D "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl= e-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial@10010000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0"; + reg =3D <0x0 0x10010000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + dma: dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <23 24 25 26 27 28 29 30>; + #dma-cells =3D <1>; + }; + uart1: serial@10011000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0"; + reg =3D <0x0 0x10011000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <5>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + i2c0: i2c@10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2= c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi@10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi@10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi@10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet@10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm0: pwm@10020000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10020000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <42 43 44 45>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + pwm1: pwm@10021000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10021000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <46 47 48 49>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible =3D "sifive,fu540-c000-ccache", "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic0>; + interrupts =3D <1 2 3>; + reg =3D <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible =3D "sifive,fu540-c000-gpio", "sifive,g= pio0"; + interrupt-parent =3D <&plic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1= 3>, + <14>, <15>, <16>, <17>, <18>, <19>, <= 20>, + <21>, <22>; + reg =3D <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + clint: clint@2000000 { + compatible =3D "riscv,clint0"; + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg =3D <0x0 0x2000000 0x0 0xc0000>; + }; + }; +}; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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