From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82318+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82318+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634506; cv=none; d=zohomail.com; s=zohoarc; b=XwV0fc3amF/lkTJRrsfJRrg5KWPybZAMuOJYcRtpFWTOFrPnULmjT60/XnJW0H3H8f0KfRQdGv7ATgIj2+x/MbUnIhucQUR5vxnek+DRkxAbqi/hmvAA9qSoZH9VpZgAHVw2vbqYp38QWdscwxcg5yHELIpI7Pa4iNp26g58vhI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634506; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qk8uUASZfkfbDQ1nJlvuQpZ96V/SOEDCZjkQ0tTB8xI=; b=TQqvaBOTVXyMuD+egDt8mZs7VVi/iuXne1XHbcmRqHtYwO1mqOs4QJWGgbOM3BYzNZTaIQBcENZEobA2MeqlNjGOVyi381W6qebknQ7Pfn4hBtpcbHtypka0jZzWKltk3+On2N/1Pv6U4+4LnI6s9yYB7t9XnW2AkoXYKLSzyVU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82318+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634506388123.1908877772886; Tue, 19 Oct 2021 02:08:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mBMAYY1788612xIhbHacujZ6; Tue, 19 Oct 2021 02:08:25 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7328.1634634496365987367 for ; Tue, 19 Oct 2021 02:08:24 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J61ulu018328; Tue, 19 Oct 2021 09:08:16 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gpt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:14 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id B3BFE5F; Tue, 19 Oct 2021 09:08:13 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 077D748; Tue, 19 Oct 2021 09:08:11 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document Date: Tue, 19 Oct 2021 16:09:38 +0800 Message-Id: <20211019081007.31165-2-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> X-Proofpoint-GUID: 9ycZggOtCcYD3AEfLU0Cb2W8-6DSagbA X-Proofpoint-ORIG-GUID: 9ycZggOtCcYD3AEfLU0Cb2W8-6DSagbA X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: y1UQOPPjO89yG8TXAYmIdY1jx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634505; bh=Ko6x4XbHAl2MOTar4XZ0GymvGZTxD2svQ3XsLFCABBE=; h=Cc:Date:From:Reply-To:Subject:To; b=oEE60MWXrXeHfymshGVt80NklypfHtqxdkkuEVMabERQ9wIeDZKdsH3xMzhk+dGENaD brm2i4wU2rKqv6odD+eZiNXP9xQ1w7Eg/EQxkxrTENdktL33fkzJuDgEmyj0je34/Cbx2 eniBdXYrMNlsRSSJ45K9mmq8SnrQENpJ058= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634507369100025 Content-Type: text/plain; charset="utf-8" Update EDK2 RISC-V port architectural diagrams. Cc: Daniel Schaefer Cc: Sunil V L Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- Platform/RISC-V/PlatformPkg/Readme.md | 132 +- .../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++ .../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++ 3 files changed, 3336 insertions(+), 14 deletions(-) create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2Bo= otProcess.svg create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2Fw= Domain.svg diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 4b933a2e0f..66fba15544 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -2,6 +2,113 @@ =20 ## EDK2 RISC-V Platform Project =20 +### EDK2 RISC-V Design and the Boot Processes +RISC-V edk2 port is designed base on edk2 boot phases and leverage [RISC-V= OpenSBI](https://github.com/riscv/opensbi) (which is the implementation of= [RISC-V SBI](https://github.com/riscv/riscv-sbi-doc)) as an edk2 library. = The design concept is to leverage RISC-V SBI implementation, the basic RISC= -V HARTs and the platform initialization. However, it still keeps the edk2 = build mechanism and the boot processes. RISC-V OpenSBI is built as +an library and linked with edk2 SEC module. The design diagram and the boo= t flow is shown in below figure, + +#### RISC-V EDK2 Port Design Diagrams +![RISC-V EDK2 Port](https://github.com/tianocore/edk2-platforms/blob/maste= r/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg?raw= =3Dtrue) + +#### SEC Phase +As the most of edk2 platforms SEC implementations, RISC-V edk2 port SEC mo= dule initiates the fundamental platform +boot environment. RISC-V edk2 SEC module linked with [RiscVOpensbiLib](#ri= scvopensbilib-library) that pulls in the OpenSBI core source files into the= build as a library. SEC module invokes sbi_init() to execute through the O= penSBI +initialization flow. Afterwards, SEC phase hands off to PEI phase via Open= SBI with the ***NextAddress*** and ***NextMode*** are configured. +The entire SEC phase with ***RiscVOpensbiLib*** is executed in the Machine= -mode (M-mode) which is the highest +and the mandatory privilege mode of RISC-V HART. The SBI implementation is= also executed in the M-mode that +provides the Supervisor Binary Interface for the entities run in the Super= visor-mode (S-mode). The default +privilege mode is configured to S-mode for the next phase after SEC, that = says the PEI, DXE and BDS phases are +default executed in S-mode unless the corresponding [PCDs](#risc-v-platfor= m-pcd-settings) are configured +differently from the default settings according to the OEM platform design. + +##### RiscVOpensbiLib Library +[Indicated as #1 in the figure](#risc-v-edk2-port-design-diagrams) +> ***RiscVOpensbiLib*** is a edk2 wrapper library of OpenSBI. SEC module i= s the only consumer of ***RiscVOpensbiLib*** across the entire edk2 boot pr= ocesses. The sub-module under ***RiscVOpensbiLib*** is updated +to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib***= provides the RISC-V SBI +implementation and initialize the OpenSBI boot flow. SEC module is also li= nked with below libraries, +- edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that prov= ides the generic RISC-V platform initialization code. +- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) lib= rary which is provided by the RISC-V +platform vendor for the platform-specific initialization. The underlying i= mplementation of above two edk2 libraries +are from OpenSBI project. edk2 libraries are introduced as the wrapper lib= raries that separates and organizes OpenSBI core and platform code based on= edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***R= iscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://gi= thub.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) = while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V = PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platfo= rm/RISC-V/PlatformPkg). +- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is = provided by the platform vendor and located under edk2 RISC-V platform-spec= ific folder. + +##### OpenSbiPlatformLib Library +[Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams) +> ***OpenSbiPlatformLib*** provides the generic RISC-V platform initializa= tion code. Platform vendor can just utilize this library if they don't have= additional requirements on the platform initialization. + +##### RiscVSpecifialPlatformLib Library +[Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams) +> The major use case of this library is to facilitate the interfaces for p= latform vendors to provide the special +platform initialization based on the generic platform initialization libra= ry. + +##### Edk2OpensbiPlatformWrapperLib Library +[Indicated as #4 in the figure](#risc-v-edk2-port-design-diagrams) +> In order to providing the flexibility to edk2 RISC-V firmware solution, = ***Edk2OpensbiPlatformWrapperLib*** is the wrapper library of [OpenSbiPlatf= ormLib](#OpenSbiPlatformLib-library) to provide the interfaces for OEM. The= ***platform_ops_address***in the generic platform structure is replaced wi= th ***Edk2OpensbiplatformOps*** in SEC +module. The platform function invoked by OpenSBI core is hooked to ***Edk2= OpensbiPlatformWrapperLib***. This gives +a change to OEM for implementing platform-specific initialization before a= nd after the generic platform code. OEM +can override this library under their platform folder on demand without to= uching ***RiscVOpensbiLib*** library +source files and other common source files. + +##### Next Phase Address and Privilege Mode +[Indicated as #5 in the figure](#risc-v-edk2-port-design-diagrams) +> Once OpenSBI finishes the boot initialization, it will jump to the next = phase with the default privilege set to +S-mode. In order to facilitate the flexibility for a variant of platform d= emands. EDK2 RISC-V provides the [PCDs](#risc-v-platform-pcd-settings) as t= he configurable privilege for the next phase. Whether to have PEI or later +phases executed in the default S-mode or to keep the RISC-V edk2 boot phas= e privilege in M-mode is at platform design discretion. The SEC module sets= the next phase address to the PEI Core entry point with a configurable +privilege according to the PCD. + +#### PEI Phase +SEC module hands off the boot process to PEI core in the privilege configu= red by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is= forced to S-mode)*. PEI and later phases are allowed to executed in M-mode +if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mo= de) for the virtualization. RISC-V edk2 port provides its own instance ***P= eiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-= port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppili= b-library) in order to support the S-mode PEI phase. PEI core requires [Ris= cVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve= the information of RISC-V HARTs and platform (e.g. FDT) configurations tha= t built up in SEC phase. ***PeiServicePointer*** is also maintained in the = ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved= by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library)= library. + +##### PlatformSecPpiLib Library +[Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams) + +> Some platform has the PEI protocol interface (PPI) prepared in SEC phase= and pass the PPI description to PEI phase for the installation. That means= the PPI code resides in SEC module and executed in PEI phase. Due to the S= EC +(with OpenSBI) is protected by the RISC-V Physical Memory Protection (PMP)= through [OpenSBI firmware domain](#edk2-opensbi-firmware-domain), the SEC = can be only accessed and executed when RISC-V HART is operated in M-mode. T= he SEC PPI passed to PEI is not able to be executed by any PEI modules. Thu= s we have ***PlatformSecPpiLib*** library for the platforms that requires t= o install the PPI at the early stage of PEI core instead of installing PPI +during PEI dispatcher that maybe too late for some platform use cases. ***= PlatformSecPpiLib*** is currently +executed in S-mode because we force to switch RISC-V boot HART to S-mode w= hen SEC hands of boot process to PEI +phase. ***PlatformSecPpiLib*** can also executed in M-mode once we have th= e full implementation of [***PcdPeiCorePrivilegeMode***.](#risc-v-platform-= pcd-settings) + +##### RiscVFirmwareContextLib Library +[Indicated as #9 in the figure](#risc-v-edk2-port-design-diagrams) + +> The ***OpenSBI FirmwareContext*** is a structure member in sbi_platform,= that can carry the firmware +solution-defined information to edk2 boot phases after SEC. edk2 defines i= ts own ***FirmwareContext*** as below in +the current implementation. + + typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + UINT64 FlattenedDeviceTree; // Pointer to Flattened= Device tree + UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_= HAND_OFF passed to PEI Core. + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX= _HART_SUPPORTED]; + } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +> ***RiscVFirmwareContextLib*** library is used by PEI module for obtainin= g the ***FirmwareContext*** pointer. + +##### PeiServiceTablePointerOpensbi Library +[Indicated as #10 in the figure](#risc-v-edk2-port-design-diagrams) + +> ***PeiServiceTablePointerOpensbi*** is the library that provides Get/Set= PeiServiceTablePointer. ***RiscVFirmwareContextLib*** is the underlying li= brary for the operations on PEI service table pointer. + +##### PEI OpenSBI PPI +[Indicated as #11 in the figure](#risc-v-edk2-port-design-diagrams) + +> edk2 PEI OpenSBI PPI *(TODO)* provides the unified interface for all PEI= drivers to invoke SBI services. + +#### DXE Phase +DXE IPL PEI module hands off the boot process to DXE Core in the privilege= configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently is not impleme= nted yet)*. edk2 DXE OpenSBI protocol *(TODO, indicated as #12 in the figur= e)* provides the unified interface for all DXE drivers to invoke SBI servic= es. + +#### BDS Phase +The implementation of RISC-V edk2 port in BDS phase is the same as it is i= n DXE phase which is executed in the +privilege configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently the = privilege is forced to S-mode)*. The +OpenSBI is also provided through edk2 DXE OpenSBI Protocol*(TODO, indicate= d as #12 in the figure)*. However, BDS must transits the privilege mode to = S-mode before it handing off the boot process to S-mode OS, OS boot loader = or EFI application. + +#### EDK2 OpenSBI Firmware Domain + +![RISC-V EDK2 FW Domain](https://github.com/tianocore/edk2-platforms/blob/= master/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg?ra= w=3Dtrue) + +OpenSBI implements the firmware domain mechanism to protect the root firmw= are (which is the OpenSBI itself) as the M-mode only access and execute reg= ion. RISC-V edk2 port configures the root firmware domain via [PCDs](#risc-= v-platform-pcd-settings) to protect SEC firmware volume, memory and OpenSBI= stuff. The firmware region (non-root firmware) that accommodates PEI and D= XE phase FV regions, while EFI variable region is reported as a separate fi= rmware region as it shows in above figure. + ### EDK2 Build Architecture for RISC-V The edk2 build architecture which is supported and verified on edk2 code b= ase for RISC-V platforms is `RISCV64`. @@ -49,18 +156,9 @@ Then you can build the edk2 firmware image for RISC-V p= latforms. build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc ``` =20 -## RISC-V OpenSBI Library -RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of -[RISC-V SBI (Supervisor Binary Interface) specification](https://github.co= m/riscv/riscv-sbi-doc). -For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library -[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi= ) in EDK2 -RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC drive= r without -any modifications and provides the interfaces for supervisor mode executio= n environment -to execute privileged operations. - ## RISC-V Platform PCD settings ### EDK2 Firmware Volume Settings -EDK2 Firmware volume related PCDs which declared in platform FDF file. +EDK2 Firmware volume related PCDs which is declared in platform FDF file. =20 | **PCD name** |**Usage**| |--------------|---------| @@ -86,10 +184,14 @@ The PCD settings regard to EFI Variable ### RISC-V Physical Memory Protection (PMP) Region Settings Below PCDs could be set in platform FDF file. =20 -| **PCD name** |**Usage**| -|--------------|---------| -|PcdFwStartAddress| The starting address of firmware region to protected b= y PMP| -|PcdFwEndAddress| The ending address of firmware region to protected by PM= P| +| **PCD name** |**Usage**|**Access Permission in M-mode**|**Access Permiss= ion in S-mode**| +|--------------|---------|---------|---------| +|PcdRootFirmwareDomainBaseAddress| The starting address of root firmware d= omain protected by PMP|Full access|No Access| +|PcdRootFirmwareDomainSize| The size of root firmware domain|-|-| +|PcdFirmwareDomainBaseAddress| The starting address of firmware domain tha= t can be accessed and executed in S-mode|Full access|Readable and Executabl= e| +|PcdFirmwareDomainSize| The size of firmware domain|-|-| +|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variabl= e region that can be accessed in S-mode|Full access|Readale and Writable| +|PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-= |-| =20 ### RISC-V Processor HART Settings =20 @@ -98,6 +200,7 @@ Below PCDs could be set in platform FDF file. |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| |PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value| +|PcdBootableHartIndexToId| if PcdBootableHartNumber =3D=3D 0, hart_index2i= d is built from Device Tree, otherwise this is an array of HART index to HA= RT ID| =20 ### RISC-V OpenSBI Settings =20 @@ -109,6 +212,7 @@ Below PCDs could be set in platform FDF file. |PcdTemporaryRamBase| The base address of temporary memory for PEI phase| |PcdTemporaryRamSize| The temporary memory size for PEI phase| |PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI pha= se| +|PcdDxeCorePrivilegeMode (TODO)|The target RISC-V privilege mode for edk2 = DXE phase| =20 ## Supported Operating Systems Currently support boot to EFI Shell and Linux kernel. diff --git a/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProce= ss.svg b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.s= vg new file mode 100644 index 0000000000..dfd47a75b9 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg @@ -0,0 +1,1928 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page-2 + + + + + Rectangle.356 + + + + + + + Rectangle.229 + + + + + + + Rectangle.178 + + + + + + + Rounded Rectangle.359 + RiscVOpensbiLib + + + + + + + + + + + + + + + + + + + + + + RiscVOpensbiLib = + + Rectangle.200 + + + + + + + + + + Rectangle.216 + + + + + + + + + + Side to side 1.223 + + + + + + + + + + + Rectangle.305 + Privilege Mode Switch + + + + + + + + + + Privi= lege Mode Switch + + Rectangle.322 + Privilege in Supervisor Mode + + + + + + + + + + Privi= lege in Supervisor Mode + + Rectangle.339 + Power on / Reset + + + + + + + Power= on / Reset + + Rectangle.217 + + + + + + + + + + Rounded Rectangle.230 + Edk2OpensbiPlatformWrapperLib + + + + + + + + + + + + + + + + + + + + + + = Edk2OpensbiPlatformWrapperLib<= /tspan> + + Rounded Rectangle.183 + OpenSbi PlatformLib + + + + + + + + + + + + + + + + + + + + + + OpenSbiPlatformLi= b + + Rectangle.176 + BDS + + + + + + + BDS + + Rounded Rectangle.180 + Generic Platform Functions + + + + + + + + + + + + + + + + + + + + + + Generic Platform Functions = + + Rounded Rectangle.182 + RiscVSpecial PlatformLib + + + + + + + + + + + + + + + + + + + + + + = RiscVSpecialPlatformLi= b + + Rounded Rectangle.184 + HART index to ID array + + + + + + + + + + + + + + + + + + + + + + HART index to ID array + + Rounded Rectangle.185 + Boot HART ID + + + + + + + + + + + + + + + + + + + + + + Boot HART ID + + Rounded Rectangle.181 + Special Platform Override + + + + + + + + + + + + + + + + + + + + + + Special Platform Override = + + Sheet.192 + + + + Sheet.193 + + + + Sheet.197 + + + + Sheet.199 + + + + Sheet.201 + PEI Core + + + + PEI Core + + Rounded Rectangle.203 + PlatformSecPpiLib + + + + + + + + + + + + + + + + + + + + + + = PlatformSecPpiLib + + Rounded Rectangle.204 + RiscVFirmwareConextLib + + + + + + + + + + + + + + + + + + + + + + = RiscVFirmwareConextLib<= /tspan> + + Bottom to top 1 + + + + + + + + Rounded Rectangle + OpenSBI Library (SBI Implementation) + + + + + + + + + + + + + + + + + + + + + + OpenSBI Library (SBI Impleme= ntation) + + Sheet.212 + + + + Sheet.213 + + + + Sheet.218 + + + + Sheet.219 + + + + Sheet.222 + + + + Sheet.225 + + + + Rounded Rectangle.227 + DXE SBI Procotol + + + + + + + + + + + + + + + + + + + + + + DXE SBI Procotol + + Sheet.228 + + + + Sheet.209 + + + + Rounded Rectangle.224 + PEI SBI PPI + + + + + + + + + + + + + + + + + + + + + + PEI SBI PPI + + Rounded Rectangle.198 + SBI Implementation + + + + + + + + + + + + + + + + + + + + + + SBI Implementatio= n + + Rounded Rectangle.226 + SBI Implementation + + + + + + + + + + + + + + + + + + + + + + SBI Implementatio= n + + Sheet.215 + + + + Sheet.231 + + + + Sheet.237 + + + + Bottom to top 1.239 + + + + + + + + Link + + + + + + + + Link.242 + + + + + + + + Bottom to top 1.244 + + + + + + + + Sheet.245 + + + + Rounded Rectangle.249 + OEM can override this library instance to hook before/af= ter e... + + + + + + + + + + + + + + + + + + + + + + OEM can override this library= instance to= hook before/after each OpenSbi platform operation API for platform <= tspan + x=3D"26.07" dy=3D"1.2em" class=3D"st16">specific p= urposes + + Directed line 1 + + + + + + + Link.256 + + + + + + + + Bottom to top 1.257 + + + + + + + + Bottom to top 1.258 + + + + + + + + Link.260 + + + + + + + + Bottom to top 1.261 + + + + + + + + Bottom to top 1.262 + + + + + + + + Sheet.271 + + + + + + + Rounded Rectangle.274 + DXE SBI Procotol + + + + + + + + + + + + + + + + + + + + + + DXE SBI Procotol + + Sheet.275 + + + + Rounded Rectangle.276 + SBI Implementation + + + + + + + + + + + + + + + + + + + + + + SBI Implementatio= n + + Sheet.279 + PcdBootbaleHartNumber PcdBootbaleHartIndexToId + + + + PcdBootbaleH= artNumberPcdBootbaleH= artIndexToId + + Configure.282 + + + + + + + + Curve connect 3.285 + + + + + + + Sheet.286 + PcdBootHartId + + + + PcdBootHartI= d + + Configure.288 + + + + + + + + Curve connect 3.289 + + + + + + + Link.294 + + + + + + + + Bottom to top 1.297 + + + + + + + + Rounded Rectangle.202 + PeiCoreEntryPointLib + + + + + + + + + + + + + + + + + + + + + + = PeiCoreEntryPointLib + + Link.300 + + + + + + + + Sheet.214 + + + + Side to side 1 + + + + + + + + + + + Rectangle.304 + Privilege Mode Switch + + + + + + + + + + Privi= lege Mode Switch + + Rectangle.174 + PEI + + + + + + + PEI + + Rectangle.175 + DXE + + + + + + + DXE + + Sheet.306 + PcdPeiCorePrivilegeMode + + + + PcdPeiCorePrivilegeMode = + + Configure.307 + + + + + + + + Sheet.309 + PcdPDxeCorePrivilegeMode + + + + PcdPDxeCorePrivilegeMode = + + Configure.310 + + + + + + + + Curve connect 3.312 + + + + + + + Curve connect 3.313 + + + + + + + Rounded Rectangle.315 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + = PEI Driver + + Rounded Rectangle.314 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + = PEI Driver + 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Sheet.340 + + + + + + + Rectangle.324 + Runtime OS + + + + + + + + + + Runtime= OS + + Rounded Rectangle.342 + SBI Implementation + + + + + + + + + + + + + + + + + + + + + + SBI Implementatio= n + + Data process.343 + 2 + + + + + + + + + + + + 2 + + Data process.344 + 3 + + + + + + + + + + + + 3 + + Data process.345 + 4 + + + + + + + + + + + + 4 + + Data process.347 + 5 + + + + + + + + + + + + 5 + + Data process.348 + 6 + + + + + + + + + + + + 6 + + Data process.349 + 7 + + + + + + + + + + + + 7 + + Data process.350 + 8 + + + + + + + + + + + + 8 + + Data process.351 + 9 + + + + + + + + + + + + 9 + + Data process.352 + 11 + + + + + + + + + + + + 11 + + Data process.353 + 6 + + + + + + + + + + + + 6 + + Data process.354 + 12 + + + + + + + + + + + + 12 + + Sheet.357 + + + + Rectangle + SEC + + + + + + + SEC + + Data process.360 + 1 + + + + + + + + + + + + 1 + + Sheet.361 + + + + Sheet.362 + + + + Link.363 + + + + + + + + Bottom to top 1.364 + + + + + + + + Rounded Rectangle.365 + PeiServiceTablePointerOpensbi + + + + + + + + + + + + + + + + + + + + + + = PeiServiceTablePointerOpen= sbi + + Data process.367 + 10 + + + + + + + + + + + + 10 + + Sheet.368 + + + + diff --git a/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.= svg b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg new file mode 100644 index 0000000000..e2f00e1357 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg @@ -0,0 +1,1290 @@ + + + + + + + + + + + + + + + + + + + Page-2 + + + + + Box + + + + + + + Sheet.417 + + Rounded Rectangle.385 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.386 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.387 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.421 + PEI Core + + + + PEI Core + + Sheet.422 + DXE Core + + + + DXE Core + + Rectangle.390 + + + + + + + + + + Rounded Rectangle.391 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Rounded Rectangle.392 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rectangle.393 + PEI/DXE Firmware Volume + + + + + + + PEI/DXE Firmware Volume<= /text> + + Rounded Rectangle.394 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.395 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.396 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.397 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.431 + PEI Core + + + + PEI Core + + Sheet.432 + DXE Core + + + + DXE Core + + + Sheet.401 + + Rounded Rectangle.385 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.386 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.387 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.405 + PEI Core + + + + PEI Core + + Sheet.406 + DXE Core + + + + DXE Core + + Rectangle.390 + + + + + + + + + + Rounded Rectangle.391 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Rounded Rectangle.392 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rectangle.393 + PEI/DXE Firmware Volume + + + + + + + PEI/DXE Firmware Volume<= /text> + + Rounded Rectangle.394 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.395 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.396 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.397 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.415 + PEI Core + + + + PEI Core + + Sheet.416 + DXE Core + + + + DXE Core + + + Rectangle.178 + + + + + + + + + + Rounded Rectangle.365 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver + + Rounded Rectangle.359 + RiscVOpensbiLib + + + + + + + + + + + + + + + + + + + + + + RiscVOpensbiLib = + + Rounded Rectangle + OpenSBI Library (SBI Implementation) + + + + + + + + + + + + + + + + + + + + + + OpenSBI Library (SBI Impleme= ntation) + + Sheet.213 + + + + Sheet.264 + PcdFirmwareDomainSize PcdFirmwareDomainBaseAddress + + + + PcdFirmwareD= omainSizePcdFirmwareD= omainBaseAddress + + Sheet.160 + PcdRootFirmwareDomainBaseAddress PcdRootFirmwareDomainSi= ze + + + + PcdRootFirmwa= reDomainBaseAddressPcdRootFirmw= areDomainSize + + Configure.283 + + + + + + + + Configure.284 + + + + + + + + Sheet.290 + PcdVariableFirmwareRegionBaseAddress PcdVariableFirmware= Regio... + + + + PcdVariableFi= rmwareRegionBaseAddressPcdVariableF= irmwareRegionSize + + Configure.291 + + + + + + + + Rounded Rectangle.315 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver + + Rounded Rectangle.314 + SEC Libraries + + + + + + + + + + + + + + + + + + + + + + SEC Libraries + + Sheet.179 + SecMain + + + + = SecMain= + + Rectangle + SEC Firmware Volumn + + + + + + + SEC Firmware Volumn = + + Sheet.400 + + Rounded Rectangle.385 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.386 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.387 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.388 + PEI Core + + + + PEI Core + + Sheet.389 + DXE Core + + + + DXE Core + + Rectangle.390 + + + + + + + + + + Rounded Rectangle.391 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Rounded Rectangle.392 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rectangle.393 + PEI/DXE Firmware Volume + + + + + + + PEI/DXE Firmware Volume<= /text> + + Rounded Rectangle.394 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.395 + DXE Driver + + + + + + + + + + + + + + + + + + + + + + DXE Driver = + + Rounded Rectangle.396 + PEI Driver + + + + + + + + + + + + + + + + + + + + + + PEI Driver = + + Rounded Rectangle.397 + PEI Drivers + + + + + + + + + + + + + + + + + + + + + + PEI Drivers = + + Sheet.398 + PEI Core + + + + PEI Core + + Sheet.399 + DXE Core + + + + DXE Core + + + Rectangle.433 + + + + + + + + + + Rectangle.441 + EFI Variable + + + + + + + EFI Variable + + Sheet.442 + + + + Sheet.443 + + + + Sheet.444 + + + + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82318): https://edk2.groups.io/g/devel/message/82318 Mute This Topic: https://groups.io/mt/86435668/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82317+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82317+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634505; cv=none; d=zohomail.com; s=zohoarc; b=dsxmcO3OIZ335vjZq2oAYhgtWswnFvGxf0X6X5yHM/FFlrrYsZJ78jH4XfFpXUvsI9I2HZ1TbU7GJ6yfeuOD5OVVLVJZ6aN453UxtyqAyMOGMHHvmWWVOV0R8Czip+JhRE6nika4mTOZyHP5V1ayq3B2KSwKRYIskW+7UU4Qwko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634505; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NvGdvh0VpLmBrg1Y9AcGOiTQevePqwh6rGX2vFKiEZA=; b=RFEk7qCAobjzUBA5k8hXKOOTlJF1/N+woG8xhQQXzAbXaOveOASJFlI6QnxZSojYjXUFONEBpCLG9ucRuOxG9UrPxqJqETMhDTsU0JTLBlwc0yIriTSxgJt1tEsjf4cLLxSuoSYvCwa0wIFWvV2kO994lrGwPbu7Wbvs0kIo7MM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82317+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634505315299.5389772030776; Tue, 19 Oct 2021 02:08:25 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JpPlYY1788612xVB552eMNhi; Tue, 19 Oct 2021 02:08:25 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7330.1634634498108700986 for ; Tue, 19 Oct 2021 02:08:24 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8CF9P020959; Tue, 19 Oct 2021 09:08:17 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 3bsta50efd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:16 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 0A51DC3; Tue, 19 Oct 2021 09:08:15 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id EFAAB48; Tue, 19 Oct 2021 09:08:13 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Date: Tue, 19 Oct 2021 16:09:39 +0800 Message-Id: <20211019081007.31165-3-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5vmMlaQB4py_A_1EWbkQcR6rlu4DS61X X-Proofpoint-ORIG-GUID: 5vmMlaQB4py_A_1EWbkQcR6rlu4DS61X X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: Pt5aOjGOi5FIwGFe0zxcHReAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634505; bh=M0LMZFvsqtKkHASdtk/hH7uhQpgUSLHFLA+vccefAU0=; h=Cc:Date:From:Reply-To:Subject:To; b=SWwnYKbfaOziDFDChut2XELVsBnXEus1MrAZHumIqUW3Y4iVVpZ2SRLFYeWkBWp67VB 3tEFAzDXXDtcAf4i6+hb4JyLVw3g8Q/kY/Cscp32OjvNZp0rngws9fy5CFzfTv8RC0R8o 5hQhjwSj6502Q94Ly5AXvoenKIdI2FdBKA4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634507128100018 Content-Type: text/plain; charset="utf-8" - Add RISC-V PeiCoreEntryPoint library that incorporates with opensbi next phase switching mechanism. - Use RiscVFirmwareContext library to get the pointer of opensbi FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 7 +- .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +++++++ .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 97 +++++++++++++++++++ .../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +++ 4 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.uni diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 5d9674a965..8eec09549f 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -1,7 +1,7 @@ #/** @file # RISC-V platform package. # -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -58,6 +58,10 @@ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf =20 +[LibraryClasses.common.PEI_CORE] + # RISC-V platform PEI core entry point. + PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/= PeiCoreEntryPoint.inf + [LibraryClasses.common.PEIM] FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/= FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf @@ -77,6 +81,7 @@ Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/Platfo= rmUpdateProgressLibNull.inf Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/= FirmwareContextProcessorSpecificLib.inf Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R= iscVPlatformTempMemoryInitLibNull.inf + Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf =20 [Components.common.SEC] Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo= reEntryPoint.inf new file mode 100644 index 0000000000..e16a974636 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.inf @@ -0,0 +1,36 @@ +## @file +# Module entry point library for PEI core on RISC-V with RISC-V OpenSBI. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiCoreEntryPoint + MODULE_UNI_FILE =3D PeiCoreEntryPoint.uni + FILE_GUID =3D 2EBF4D2C-99B2-4A09-8C5C-318FB0EF7250 + MODULE_TYPE =3D PEI_CORE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiCoreEntryPoint|PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PeiCoreEntryPoint.c + +[Packages] + MdePkg/MdePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + RiscVFirmwareContextLib + diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCore= EntryPoint.c new file mode 100644 index 0000000000..2fd0f2315b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.c @@ -0,0 +1,97 @@ +/** @file + Entry point to a the PEI Core on RISC-V platform with RISC-V OpenSBI. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +// +// The Library classes this module produced +// +#include +#include +#include +#include + +/** + The entry point of PE/COFF Image for the PEI Core. + + This function is the entry point for the PEI Foundation, which allows th= e SEC phase + to pass information about the stack, temporary RAM and the Boot Firmware= Volume. + In addition, it also allows the SEC phase to pass services and data forw= ard for use + during the PEI phase in the form of one or more PPIs. + There is no limit to the number of additional PPIs that can be passed fr= om SEC into + the PEI Foundation. As part of its initialization phase, the PEI Foundat= ion will add + these SEC-hosted PPIs to its PPI database such that both the PEI Foundat= ion and any + modules can leverage the associated service calls and/or code in these e= arly PPIs. + This function is required to call ProcessModuleEntryPointList() with the= Context + parameter set to NULL. ProcessModuleEntryPoint() is never expected to r= eturn. + The PEI Core is responsible for calling ProcessLibraryConstructorList() = as soon as + the PEI Services Table and the file handle for the PEI Core itself have = been established. + If ProcessModuleEntryPointList() returns, then ASSERT() and halt the sys= tem. + + @param SecCoreData This is actually the RISC-V boot HART ID passed in a= 0 register. + + @param PpiList This is actually the EFI_RISCV_OPENSBI_FIRMWARE_CONT= EXT passed + in a1 register. + +**/ +VOID +EFIAPI +_ModuleEntryPoint( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList +) +{ + EFI_SEC_PEI_HAND_OFF *ThisSecCoreData; + EFI_PEI_PPI_DESCRIPTOR *ThisPpiList; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList; + SetFirmwareContextPointer (FirmwareContext); + ThisSecCoreData =3D (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandO= ffData; + ThisPpiList =3D (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoff= Ppi; + ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL); + + // + // Should never return + // + ASSERT(FALSE); + CpuDeadLoop (); +} + + +/** + Required by the EBC compiler and identical in functionality to _ModuleEn= tryPoint(). + + This function is required to call _ModuleEntryPoint() passing in SecCore= Data and PpiList. + + @param SecCoreData Points to a data structure containing information ab= out the PEI core's + operating environment, such as the size and location= of temporary RAM, + the stack location and the BFV location. + + @param PpiList Points to a list of one or more PPI descriptors to b= e installed + initially by the PEI core. An empty PPI list consis= ts of + a single descriptor with the end-tag + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. + As part of its initialization phase, the PEI Foundat= ion will + add these SEC-hosted PPIs to its PPI database, such = that both + the PEI Foundationand any modules can leverage the a= ssociated + service calls and/or code in these early PPIs. + +**/ +VOID +EFIAPI +EfiMain ( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList + ) +{ + _ModuleEntryPoint (SecCoreData, PpiList); +} diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.uni b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo= reEntryPoint.uni new file mode 100644 index 0000000000..1955b7a05b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.uni @@ -0,0 +1,14 @@ +// /** @file +// Module entry point library for PEI core on RISC-V with RISC-V OpenSBI. +// +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V module ent= ry point library for PEI core" + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V module ent= ry point library for PEI core." + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82317): https://edk2.groups.io/g/devel/message/82317 Mute This Topic: https://groups.io/mt/86435667/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82315+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82315+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634503; cv=none; d=zohomail.com; s=zohoarc; b=dv81AFrExCgrXtB3uTtbdXQJfb7EzqUFQZhiCBoZY0oB7qh8QEaVJOa55dB6TtXgW2E1Vr6Cop/GYF3/xjPn/dHeSiImXPoMPmZPJiZ23iLeWhXCgALYTJAjVVsszqB2Z4ul3xav3qyL9suQD0uunNuZIV6S01WpHSO2WX8h+XQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634503; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zZFVyqb5bGmJAegM8dmoHAQLAe/U0muE0IF/J8Yq/yw=; b=GXMQLOxWY6L+d6X3sMWRws6v0rN5wCoFmQN/PmoDpUX5NcxoLWwpdcNWZr8/DwgT52U8lJt2obmZkamRX2+6EYO1PrHgrmubzGkmfQW3Ky/qR6gnToMV3L+Rqf+ehlXNNu4ikgBs4ja5ADJLmH6DDdrlxtYV8fC1XhMlw//WJlQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82315+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634503167943.039081213172; Tue, 19 Oct 2021 02:08:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id iWEbYY1788612xkFOBwe6K61; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.7152.1634634498110023633 for ; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19ILhMZa008004; Tue, 19 Oct 2021 09:08:17 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qrv9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:16 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 6A30C62; Tue, 19 Oct 2021 09:08:16 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 5C13E4B; Tue, 19 Oct 2021 09:08:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Date: Tue, 19 Oct 2021 16:09:40 +0800 Message-Id: <20211019081007.31165-4-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: x2IGIjS1iQCcMGLIipob44dcdj-r4zlO X-Proofpoint-ORIG-GUID: x2IGIjS1iQCcMGLIipob44dcdj-r4zlO X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: kGGylzMkyqC5UcvXJrJM4CeSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634502; bh=xqJXYP8VmnEw4wO//aw7WuQtjX0nUSouZt4mu9tKCa4=; h=Cc:Date:From:Reply-To:Subject:To; b=G2SR0dSO/ZZ7X9ThgCUiJPkjpxTEkx73Nm02CZZXkWdW9HhIaTci8FkCXOMrNPNmuoM 8ik3oK1rqf/ve+0qUUgW7eXIiQ9t9+/dOnSCVqgdiqU6i1s4OV1kBEB2Hm/mzeex066XL MuI2wqxeWsmn5GmaBdtp3cL0+5v79z506ro= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634504760100001 Content-Type: text/plain; charset="utf-8" Incorporate with opensbi to create three firmware domains, - Boot firmware domain, which built with opensbi library as M-mode access only region. - Firmware domain which includes PEI and DXE regions, the PMP attribute is readable, wriable and executable. - EFI Variable region which is readable and writable. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 40 ++++----- .../U540.fdf.inc | 80 +++++++++++++----- .../VarStore.fdf.inc | 8 +- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 9 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 6 +- .../Library/OpensbiPlatformLib/Platform.c | 84 ++++++++++++++++--- .../PlatformPkg/Universal/Sec/SecMain.c | 53 +++++------- .../Universal/Sec/Riscv64/SecEntry.S | 7 +- 8 files changed, 188 insertions(+), 99 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index ad15a155fe..7e41e7bdb2 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -1,7 +1,7 @@ ## @file RiscVPlatformPkg.dec # This Package provides UEFI RISC-V platform modules and libraries. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,33 +31,33 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 016 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 017 - + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 006 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 007 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0= |UINT32|0x00001008 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32= |0x00001009 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UIN= T32|0x0000100a + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0= 000100b + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= |0x0|UINT32|0x0000100c + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UI= NT32|0x0000100d # # Definition of EFI Variable region # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015 -# -# Firmware region which is protected by PMP. -# - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001040 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001041 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001042 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001043 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001044 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001045 + # # Definition of RISC-V Hart # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084 # # The bootable hart core number, which is incorporate with OpenSBI platfor= m hart_index2id value. # - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01085 # # Definitions for OpenSbi # @@ -73,7 +73,7 @@ [PcdsPatchableInModule] =20 [PcdsFeatureFlag] - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001200 =20 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] =20 diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 8e7afc2d82..f708f4d8be 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -1,7 +1,7 @@ ## @file # Definitions of Flash definition file on SiFive Freedom U540 HiFive Unle= ashed RISC-V platform # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -10,37 +10,77 @@ DEFINE BLOCK_SIZE =3D 0x1000 =20 DEFINE FW_BASE_ADDRESS =3D 0x80000000 -DEFINE FW_SIZE =3D 0x00820000 -DEFINE FW_BLOCKS =3D 0x820 +DEFINE FW_SIZE =3D 0x00900000 +DEFINE FW_BLOCKS =3D 0x900 =20 # # 0x000000-0x7DFFFF code # 0x7E0000-0x800000 variables # DEFINE CODE_BASE_ADDRESS =3D 0x80000000 -DEFINE CODE_SIZE =3D 0x007E0000 -DEFINE CODE_BLOCKS =3D 0x7E0 +DEFINE CODE_SIZE =3D 0x00800000 +DEFINE CODE_BLOCKS =3D 0x800 DEFINE VARS_BLOCKS =3D 0x20 =20 -DEFINE SECFV_OFFSET =3D 0x00000000 -DEFINE SECFV_SIZE =3D 0x00030000 -DEFINE PEIFV_OFFSET =3D 0x00030000 -DEFINE PEIFV_SIZE =3D 0x00080000 -DEFINE SCRATCH_OFFSET =3D 0x000b0000 -DEFINE SCRATCH_SIZE =3D 0x00010000 -DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng -DEFINE FVMAIN_SIZE =3D 0x0018C000 -DEFINE VARS_OFFSET =3D 0x007E0000 -DEFINE VARS_SIZE =3D 0x00020000 -DEFINE DTB_OFFSET =3D 0x00800000 -DEFINE DTB_SIZE =3D 0x00002000 +# +# SEC + opensbi library is the root FW domain. +# The base address must be round up to log2. +# +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00040000 +DEFINE ROOT_FW_DOMAIN_SIZE =3D $(SECFV_SIZE) + +# +# Other FV regions are in the second FW domain. +# The size of memory region must be power of 2. +# The base address must be aligned with the size. +# +# FW memory region +# +DEFINE PEIFV_OFFSET =3D 0x00400000 +DEFINE PEIFV_SIZE =3D 0x00180000 +DEFINE FVMAIN_OFFSET =3D 0x00580000 +DEFINE FVMAIN_SIZE =3D 0x00280000 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D 0x00800000 +DEFINE VARS_SIZE =3D 0x00007000 +DEFINE VARS_FTW_WORKING_OFFSET =3D 0x00807000 +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00001000 +DEFINE VARS_FTW_SPARE_OFFSET =3D 0x00808000 +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00018000 + +# +# Device Tree memory region +# +DEFINE DTB_OFFSET =3D 0x00840000 +DEFINE DTB_SIZE =3D 0x00002000 + +# +# Scratch area memory region +# +DEFINE SCRATCH_OFFSET =3D 0x00880000 +DEFINE SCRATCH_SIZE =3D 0x00010000 + + +DEFINE FW_DOMAIN_SIZE =3D $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_O= FFSET) +DEFINE VARIABLE_FW_SIZE =3D $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_S= IZE) - $(VARS_OFFSET) + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = =3D $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize = =3D $(ROOT_FW_DOMAIN_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress = =3D $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize = =3D $(FW_DOMAIN_SIZE) =20 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET) -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddre= ss =3D $(CODE_BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = =3D $(VARIABLE_FW_SIZE) =20 -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BAS= E_ADDRESS) -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BAS= E_ADDRESS) + $(SCRATCH_OFFSET) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_= SIZE) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Va= rStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoar= d/VarStore.fdf.inc index c287bb4336..04bddfaa44 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.= fdf.inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.= fdf.inc @@ -1,7 +1,7 @@ ## @file # FDF include file with Layout Regions that define an empty variable stor= e. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# Copyright (C) 2014, Red Hat, Inc. # Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
# @@ -9,7 +9,7 @@ # ## =20 -$(VARS_OFFSET)|0x00007000 +$(VARS_OFFSET)|$(VARS_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize # # NV_VARIABLE_STORE @@ -56,7 +56,7 @@ DATA =3D { 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } =20 -0x007e7000|0x00001000 +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBas= e|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize # #NV_FTW_WROK @@ -72,7 +72,7 @@ DATA =3D { 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } =20 -0x007e8000|0x00018000 +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize # #NV_FTW_SPARE diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index f9f2073a5b..a408737961 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -3,7 +3,7 @@ # This is the the library which provides platform # level opensbi functions follow RISC-V OpenSBI implementation. # -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -54,3 +54,10 @@ =20 gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock + + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 78bd75e3ac..bcb8b9f908 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -1,7 +1,7 @@ ## @file # RISC-V SEC module. # -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -64,8 +64,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index c4cf6782bd..4fbb201895 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Western Digital Corporation or its affiliates. * * Authors: * Anup Patel @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; } =20 +static int generic_system_reset_check(u32 reset_type, u32 reset_reason) +{ + if (generic_plat && generic_plat->system_reset_check) + return generic_plat->system_reset_check(reset_type, + reset_reason, + generic_plat_match); + return fdt_system_reset_check(reset_type, reset_reason); +} + +static void generic_system_reset(u32 reset_type, u32 reset_reason) +{ + if (generic_plat && generic_plat->system_reset) { + generic_plat->system_reset(reset_type, reset_reason, + generic_plat_match); + return; + } + + fdt_system_reset(reset_type, reset_reason); +} + +#define EDK2_ROOT_FW_REGION 0 +#define EDK2_FW_REGION 1 +#define EDK2_VARIABLE_REGION 2 +#define EDK2_ALL_REGION 3 +#define EDK2_END_REGION 4 +static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 }; + +struct sbi_domain_memregion *get_mem_regions(void) { + /* EDK2 root firmware domain memory region */ + root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize)); + root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress); + root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0; + + /*EDK2 firmware domain memory region */ + root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize)); + root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress); + root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE; + + /*EDK2 firmware domain memory region */ + root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize)); + root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress); + root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE; + + /* EDK2 domain allow everything memory region */ + root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen; + root_memregs[EDK2_ALL_REGION].base =3D 0; + root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE | + SBI_DOMAIN_MEMREGION_WRITEABLE | + SBI_DOMAIN_MEMREGION_EXECUTABLE); + + /* EDK2 domain memory region end */ + root_memregs[EDK2_END_REGION].order =3D 0; + + return root_memregs; +} + const struct sbi_platform_operations platform_ops =3D { - .early_init =3D generic_early_init, - .final_init =3D generic_final_init, - .early_exit =3D generic_early_exit, - .final_exit =3D generic_final_exit, - .domains_init =3D generic_domains_init, - .console_init =3D fdt_serial_init, - .irqchip_init =3D fdt_irqchip_init, - .irqchip_exit =3D fdt_irqchip_exit, - .ipi_init =3D fdt_ipi_init, - .ipi_exit =3D fdt_ipi_exit, + .early_init =3D generic_early_init, + .final_init =3D generic_final_init, + .early_exit =3D generic_early_exit, + .final_exit =3D generic_final_exit, + .domains_root_regions =3D get_mem_regions, + .domains_init =3D generic_domains_init, + .console_init =3D fdt_serial_init, + .irqchip_init =3D fdt_irqchip_init, + .irqchip_exit =3D fdt_irqchip_exit, + .ipi_init =3D fdt_ipi_init, + .ipi_exit =3D fdt_ipi_exit, .get_tlbr_flush_limit =3D generic_tlbr_flush_limit, - .timer_init =3D fdt_timer_init, - .timer_exit =3D fdt_timer_exit, + .timer_init =3D fdt_timer_init, + .timer_exit =3D fdt_timer_exit, }; =20 #if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index e9f030f352..e88a7b8e80 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module. =20 - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -336,7 +336,7 @@ FindAndReportEntryPoints ( =20 **/ VOID -DebutPrintFirmwareContext ( +DebugPrintFirmwareContext ( EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext ) { @@ -398,7 +398,7 @@ TemporaryRamMigration ( // FirmwareContext->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - = (UINTN)OldStack); DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n= ", __FUNCTION__, FirmwareContext)); - DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext); + DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext); =20 register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); asm volatile ("add sp, sp, a0"::"r"(a0):); @@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension ( This function transits to S-mode PEI phase from M-mode SEC phase. =20 @param[in] BootHartId Hardware thread ID of boot hart. - @param[in] FuncArg1 Arg1 delivered from previous phase. + @param[in] Scratch Pointer to sbi_scratch structure. =20 **/ VOID EFIAPI PeiCore ( - IN UINTN BootHartId, - IN UINTN FuncArg1 + IN UINTN BootHartId, + IN struct sbi_scratch *Scratch ) { EFI_SEC_PEI_HAND_OFF SecCoreData; @@ -529,7 +529,7 @@ VOID EFIAPI PeiCore ( // DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - SbiGetMscratchHartid (HartId, &ScratchSpace); + ScratchSpace =3D sbi_hartid_to_scratch (HartId); if(ScratchSpace !=3D NULL) { DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); } @@ -540,9 +540,8 @@ VOID EFIAPI PeiCore ( // Firmware context residents in stack and will be switched to memory wh= en // temporary RAM migration. // - SbiGetMscratchHartid (BootHartId, &ScratchSpace); ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT)); - ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ScratchSpace= ); + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) { DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is new= er than OpenSBI version 0x%x.\n" "There maybe be some backward compatable issues= .\n", @@ -562,13 +561,13 @@ VOID EFIAPI PeiCore ( // // Save Flattened Device tree in firmware context // - FirmwareContext.FlattenedDeviceTree =3D FuncArg1; + FirmwareContext.FlattenedDeviceTree =3D Scratch->next_arg1; =20 // // Set firmware context Hart-specific pointer // for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - SbiGetMscratchHartid (HartId, &ScratchSpace); + ScratchSpace =3D sbi_hartid_to_scratch (HartId); if (ScratchSpace !=3D NULL) { FirmwareContext.HartSpecific[HartId] =3D (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); @@ -588,6 +587,10 @@ VOID EFIAPI PeiCore ( // // Transfer the control to the PEI core // + Scratch->next_addr =3D (UINTN)(*PeiCoreEntryPoint); + Scratch->next_mode =3D PRV_S; + DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %= d\n", __FUNCTION__, BootHartId)); + sbi_init(Scratch); (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable); } =20 @@ -598,34 +601,19 @@ VOID EFIAPI PeiCore ( To register the SBI extension we stay in M-Mode and then transition here, rather than before in sbi_init. =20 - @param[in] ThisHartId Hardware thread ID. - @param[in] FuncArg1 Arg1 delivered from previous phase. + @param[in] ThisHartId Hardware thread ID. + @param[in] Scratch Pointer to sbi_scratch structure. =20 **/ VOID EFIAPI LaunchPeiCore ( IN UINTN ThisHartId, - IN UINTN FuncArg1 + IN struct sbi_scratch *Scratch ) { - UINT32 PeiCoreMode; - - DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__)); - atomic_write (&BootHartDone, (UINT64)TRUE); RegisterFirmwareSbiExtension (); - - PeiCoreMode =3D FixedPcdGet32 (PcdPeiCorePrivilegeMode); - if (PeiCoreMode =3D=3D PRV_S) { - DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION_= _)); - sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FAL= SE); - } else if (PeiCoreMode =3D=3D PRV_M) { - DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION_= _)); - PeiCore (ThisHartId, FuncArg1); - } else { - DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePri= vilegeMode is not supported.\n", __FUNCTION__)); - while (TRUE); - } + PeiCore (ThisHartId, Scratch); } =20 /** @@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack( HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode; =20 if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { - Scratch->next_addr =3D (UINTN)LaunchPeiCore; - Scratch->next_mode =3D PRV_M; - DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart= %d\n", __FUNCTION__, HartId)); - sbi_init(Scratch); + LaunchPeiCore (HartId, Scratch); } =20 // diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index a8157c896e..0a69c50065 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. + * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. * * SPDX-License-Identifier: BSD-2-Clause * @@ -71,9 +71,8 @@ _scratch_init: /* Initialize scratch space */ =20 /* Firmware range and size */ - li a4, FixedPcdGet32 (PcdFwStartAddress) - li a5, FixedPcdGet32 (PcdFwEndAddress) - sub a5, a5, a4 + li a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress) + li a5, FixedPcdGet32 (PcdRootFirmwareDomainSize) sd a4, SBI_SCRATCH_FW_START_OFFSET(tp) sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82315): https://edk2.groups.io/g/devel/message/82315 Mute This Topic: https://groups.io/mt/86435665/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82316+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82316+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634504; cv=none; d=zohomail.com; s=zohoarc; b=fWBuQLBGPx5H6+rLCamJdFkFJ6k0IuxtL6DHlR2gCgNmVlOBC4IG1h8Tt1KWYhKpbeRSMOtZLOzmJPq+FVf72Gx1S9hxvG9Bv5dFDAFOmrR9Kg/W23SMHOeEbaYLGLdCZEKoO03jcEIKg+WS7wIRJrJVp6npd4+rqTgYKNRZSIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634504; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sR105agiZMGQ8i6EUjiiDzlM+6QGQjoToJRoq5zmq10=; b=f1QY7UD+aL6i77GJ+hSr8uSl+waHM+31zLEdOvGpEwW9zC8d7/5pzfqiaUCc1YzyMCLUVx9qGtvdga2C+nkB/oqpsUM5888Ge3CF0+k7gR9k4/DKpc1+VpV9L7uqxTb03wo5xlFfeHqsCoHUGnWpeBvYKX/6e/v/qxUA9P2cBkw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82316+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634504447118.56253056682863; Tue, 19 Oct 2021 02:08:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0Gi6YY1788612xQIwszusAvx; Tue, 19 Oct 2021 02:08:24 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.7153.1634634499027483369 for ; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J84WcU030460; Tue, 19 Oct 2021 09:08:18 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 3bst6drgn3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:18 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id CA65A5F; Tue, 19 Oct 2021 09:08:17 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id BB9044B; Tue, 19 Oct 2021 09:08:16 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library Date: Tue, 19 Oct 2021 16:09:41 +0800 Message-Id: <20211019081007.31165-5-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: DzOg-wqE2kXfs57B_gZ4qmZY0YX0Ond8 X-Proofpoint-GUID: DzOg-wqE2kXfs57B_gZ4qmZY0YX0Ond8 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: ua04M6YVNSgWDDd5q0bMT9Qyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634504; bh=bZp3nq61eZzIL2kjXx84LejJCpBzSXEtkZ5gQ5rjK8A=; h=Cc:Date:From:Reply-To:Subject:To; b=bY89Ls+nOh8/fZu8ibasloPyLEjfcZMCy1pmaQYaohTwjNU7/e5qqcfatiooZpgzEUo oPZSo54l/e1DHCsJHyjhqL5ilQZ+mC1vGYyaINRzHpjEXac3GCTZDInMordy4BnLCgN3z C92w/diIYLL+Y5DLm+urwoNbKXsiDTyq14U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634505058100014 Content-Type: text/plain; charset="utf-8" 1. Use RISC-V PeiCoreEntryPoint library instance for opensbi to switch to the next phase with arg0 as HART Id and arg1 as the SEC to PEI handoff data. 2. Introduce EDK2 opensbi platform operation functions. With this, OEM can has its won platform initialization code before and/or after opensbi vendor platform functions. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 3 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 2 + .../PlatformPkg/Universal/Sec/SecMain.h | 10 + .../Include/IndustryStandard/RiscVOpensbi.h | 8 +- .../Universal/Sec/Edk2OpenSbiPlatform.c | 426 ++++++++++++++++++ .../PlatformPkg/Universal/Sec/SecMain.c | 152 +++++-- 6 files changed, 547 insertions(+), 54 deletions(-) create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPl= atform.c diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 5d2ccafaca..be23fc39fd 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -181,7 +181,6 @@ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSscratchLib/RiscVFirmwareContextSscratchLib.inf PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf - PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf @@ -191,6 +190,8 @@ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf !endif PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + # RISC-V platform PEI core entry point. + PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/= PeiCoreEntryPoint.inf =20 [LibraryClasses.common.PEIM] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index bcb8b9f908..4207c83413 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -23,11 +23,13 @@ =20 [Sources] SecMain.c + Edk2OpenSbiPlatform.c =20 [Sources.RISCV64] Riscv64/SecEntry.S =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.h index 94ea46263c..c04ddbad7f 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h @@ -28,6 +28,16 @@ #include #include =20 +int +SecPostOpenSbiPlatformEarlylInit( + IN BOOLEAN ColdBoot + ); + +int +SecPostOpenSbiPlatformFinalInit ( + IN BOOLEAN ColdBoot + ); + VOID SecMachineModeTrapHandler ( IN VOID diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h index e7ac6d26ee..d639429306 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -1,7 +1,7 @@ /** @file SBI inline function calls. =20 - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -46,8 +46,10 @@ typedef struct { // structure. Referr= ed by both C code and assembly code. =20 typedef struct { - VOID *PeiServiceTable; // PEI Service table - UINT64 FlattenedDeviceTree; // Pointer to Flattened Device t= ree + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + UINT64 FlattenedDeviceTree; // Pointer to Flattened Devic= e tree + UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_O= FF passed to PEI Core. EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED]; } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.= c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c new file mode 100644 index 0000000000..79b2f33675 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c @@ -0,0 +1,426 @@ +/* + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SecMain.h" + +extern struct sbi_platform_operations platform_ops; + +int Edk2OpensbiPlatformEarlyInit ( + BOOLEAN ColdBoot + ) +{ + int ReturnCode; + + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_init) { + ReturnCode =3D platform_ops.early_init (ColdBoot); + if (ReturnCode) { + return ReturnCode; + } + } + if (ColdBoot =3D=3D TRUE) { + return SecPostOpenSbiPlatformEarlylInit(ColdBoot); + } + return 0; +} + +int Edk2OpensbiPlatformFinalInit ( + BOOLEAN ColdBoot + ) +{ + int ReturnCode; + + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.final_init) { + ReturnCode =3D platform_ops.final_init (ColdBoot); + if (ReturnCode) { + return ReturnCode; + } + } + if (ColdBoot =3D=3D TRUE) { + return SecPostOpenSbiPlatformFinalInit(ColdBoot); + } + return 0; +} + +VOID Edk2OpensbiPlatformEarlyExit ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_exit) { + return platform_ops.early_exit (); + } +} + +/** Platform final exit */ +VOID Edk2OpensbiPlatformFinalExit ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_exit) { + return platform_ops.early_exit (); + } +} + +/** + For platforms that do not implement misa, non-standard + methods are needed to determine cpu extension. +**/ +int Edk2OpensbiPlatforMMISACheckExtension ( + CHAR8 Extension + ) +{ + if (platform_ops.misa_check_extension) { + return platform_ops.misa_check_extension (Extension); + } + return 0; +} + +/** + For platforms that do not implement misa, non-standard + methods are needed to get MXL field of misa. +**/ +int Edk2OpensbiPlatforMMISAGetXLEN (VOID) +{ + if (platform_ops.misa_get_xlen) { + return platform_ops.misa_get_xlen (); + } + return 0; +} + +/** Get platform specific root domain memory regions */ +struct sbi_domain_memregion * +Edk2OpensbiPlatformGetMemRegions (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.domains_root_regions) { + return platform_ops.domains_root_regions (); + } + return 0; +} + +/** Initialize (or populate) domains for the platform */ +int Edk2OpensbiPlatformDomainsInit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.domains_init) { + return platform_ops.domains_init (); + } + return 0; +} + +/** Write a character to the platform console output */ +VOID Edk2OpensbiPlatformSerialPutc ( + CHAR8 Ch + ) +{ + if (platform_ops.console_putc) { + return platform_ops.console_putc (Ch); + } +} + +/** Read a character from the platform console input */ +int Edk2OpensbiPlatformSerialGetc (VOID) +{ + if (platform_ops.console_getc) { + return platform_ops.console_getc (); + } + return 0; +} + +/** Initialize the platform console */ +int Edk2OpensbiPlatformSerialInit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.console_init) { + return platform_ops.console_init (); + } + return 0; +} + +/** Initialize the platform interrupt controller for current HART */ +int Edk2OpensbiPlatformIrqchipInit ( + BOOLEAN ColdBoot + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.irqchip_init) { + return platform_ops.irqchip_init (ColdBoot); + } + return 0; +} + +/** Exit the platform interrupt controller for current HART */ +VOID Edk2OpensbiPlatformIrqchipExit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.irqchip_exit) { + return platform_ops.irqchip_exit (); + } +} + +/** Send IPI to a target HART */ +VOID Edk2OpensbiPlatformIpiSend ( + UINT32 TargetHart + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_send) { + return platform_ops.ipi_send (TargetHart); + } +} + +/** Clear IPI for a target HART */ +VOID Edk2OpensbiPlatformIpiClear ( + UINT32 TargetHart + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_clear) { + return platform_ops.ipi_clear (TargetHart); + } +} + +/** Initialize IPI for current HART */ +int Edk2OpensbiPlatformIpiInit ( + BOOLEAN ColdBoot + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_init) { + return platform_ops.ipi_init (ColdBoot); + } + return 0; +} + +/** Exit IPI for current HART */ +VOID Edk2OpensbiPlatformIpiExit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_exit) { + return platform_ops.ipi_exit (); + } +} + +/** Get tlb flush limit value **/ +UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.get_tlbr_flush_limit) { + return platform_ops.get_tlbr_flush_limit (); + } + return 0; +} + +/** Get platform timer value */ +UINT64 Edk2OpensbiPlatformTimerValue (VOID) +{ + if (platform_ops.timer_value) { + return platform_ops.timer_value (); + } + return 0; +} + +/** Start platform timer event for current HART */ +VOID Edk2OpensbiPlatformTimerEventStart ( + UINT64 NextEvent + ) +{ + if (platform_ops.timer_event_start) { + return platform_ops.timer_event_start (NextEvent); + } +} + +/** Stop platform timer event for current HART */ +VOID Edk2OpensbiPlatformTimerEventStop (VOID) +{ + if (platform_ops.timer_event_stop) { + return platform_ops.timer_event_stop (); + } +} + +/** Initialize platform timer for current HART */ +int Edk2OpensbiPlatformTimerInit ( + BOOLEAN ColdBoot + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.timer_init) { + return platform_ops.timer_init (ColdBoot); + } + return 0; +} + +/** Exit platform timer for current HART */ +VOID Edk2OpensbiPlatformTimerExit (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.timer_exit) { + return platform_ops.timer_exit (); + } +} + +/** Bringup the given hart */ +int Edk2OpensbiPlatformHartStart ( + UINT32 HartId, + ulong Saddr + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.hart_start) { + return platform_ops.hart_start (HartId, Saddr); + } + return 0; +} +/** + Stop the current hart from running. This call doesn't expect to + return if success. +**/ +int Edk2OpensbiPlatformHartStop (VOID) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.hart_stop) { + return platform_ops.hart_stop (); + } + return 0; +} + +/** + Check whether reset type and reason supported by the platform* + +**/ +int Edk2OpensbiPlatformSystemResetCheck ( + UINT32 ResetType, + UINT32 ResetReason + ) +{ + if (platform_ops.system_reset_check) { + return platform_ops.system_reset_check (ResetType, ResetReason); + } + return 0; +} + +/** Reset the platform */ +VOID Edk2OpensbiPlatformSystemReset ( + UINT32 ResetType, + UINT32 ResetReason + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.system_reset) { + return platform_ops.system_reset (ResetType, ResetReason); + } +} + +/** platform specific SBI extension implementation probe function */ +int Edk2OpensbiPlatformVendorExtCheck ( + long ExtId + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.vendor_ext_check) { + return platform_ops.vendor_ext_check (ExtId); + } + return 0; +} + + +/** platform specific SBI extension implementation provider */ +int Edk2OpensbiPlatformVendorExtProvider ( + long ExtId, + long FuncId, + const struct sbi_trap_regs *Regs, + unsigned long *OutValue, + struct sbi_trap_info *OutTrap + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.vendor_ext_provider) { + return platform_ops.vendor_ext_provider ( + ExtId, + FuncId, + Regs, + OutValue, + OutTrap + ); + } + return 0; +} + +const struct sbi_platform_operations Edk2OpensbiPlatformOps =3D { + .early_init =3D Edk2OpensbiPlatformEarlyInit, + .final_init =3D Edk2OpensbiPlatformFinalInit, + .early_exit =3D Edk2OpensbiPlatformEarlyExit, + .final_exit =3D Edk2OpensbiPlatformFinalExit, + .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension, + .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN, + .domains_root_regions =3D Edk2OpensbiPlatformGetMemRegions, + .domains_init =3D Edk2OpensbiPlatformDomainsInit, + .console_putc =3D Edk2OpensbiPlatformSerialPutc, + .console_getc =3D Edk2OpensbiPlatformSerialGetc, + .console_init =3D Edk2OpensbiPlatformSerialInit, + .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit, + .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit, + .ipi_send =3D Edk2OpensbiPlatformIpiSend, + .ipi_clear =3D Edk2OpensbiPlatformIpiClear, + .ipi_init =3D Edk2OpensbiPlatformIpiInit, + .ipi_exit =3D Edk2OpensbiPlatformIpiExit, + .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit, + .timer_value =3D Edk2OpensbiPlatformTimerValue, + .timer_event_stop =3D Edk2OpensbiPlatformTimerEventStop, + .timer_event_start =3D Edk2OpensbiPlatformTimerEventStart, + .timer_init =3D Edk2OpensbiPlatformTimerInit, + .timer_exit =3D Edk2OpensbiPlatformTimerExit, + .hart_start =3D Edk2OpensbiPlatformHartStart, + .hart_stop =3D Edk2OpensbiPlatformHartStop, + .system_reset_check =3D Edk2OpensbiPlatformSystemResetCheck, + .system_reset =3D Edk2OpensbiPlatformSystemReset, + .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck, + .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider, +}; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index e88a7b8e80..44984b0078 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -23,6 +23,8 @@ #include // Reference to header file in opensbi #include // Reference to header file in opensbi =20 +extern struct sbi_platform_operations Edk2OpensbiPlatformOps; + // // Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done. // @@ -31,27 +33,6 @@ atomic_t NonBootHartMessageLock =3D ATOMIC_INITIALIZER(0= ); =20 typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartinde= x); =20 -STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { - TemporaryRamMigration -}; - -STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { - TemporaryRamDone -}; - -STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gEfiTemporaryRamSupportPpiGuid, - &mTemporaryRamSupportPpi - }, - { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gEfiTemporaryRamDonePpiGuid, - &mTemporaryRamDonePpi - }, -}; - /** Locates a section within a series of sections with the specified section type. @@ -491,6 +472,91 @@ RegisterFirmwareSbiExtension ( =20 return EFI_SUCCESS; } + +/** + OpenSBI platform early init hook. + +**/ +int +SecPostOpenSbiPlatformEarlylInit( + IN BOOLEAN ColdBoot + ) +{ + // + // Boot HART is already in the process of OpenSBI initialization. + // We can let other HART to keep booting. + // + DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__)); + atomic_write (&BootHartDone, (UINT64)TRUE); + return 0; +} + +/** + OpenSBI platform final init hook. + We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT. + +**/ +int +SecPostOpenSbiPlatformFinalInit ( + IN BOOLEAN ColdBoot + ) +{ + UINT32 HartId; + struct sbi_scratch *SbiScratch; + struct sbi_scratch *ScratchSpace; + struct sbi_platform *SbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUN= CTION__)); + + SbiScratch =3D sbi_scratch_thishart_ptr(); + SbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(SbiScratch); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->f= irmware_context; + + // + // Print out scratch address of each hart + // + DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); + for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { + if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { + continue; + } + ScratchSpace =3D sbi_hartid_to_scratch (HartId); + if(ScratchSpace !=3D NULL) { + DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); + } else { + DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId= )); + } + } + + // + // Set firmware context Hart-specific pointer + // + for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { + if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { + continue; + } + ScratchSpace =3D sbi_hartid_to_scratch (HartId); + if (ScratchSpace !=3D NULL) { + FirmwareContext->HartSpecific[HartId] =3D + (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); + DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-spe= cific at address: 0x%x\n", + __FUNCTION__, + HartId, + FirmwareContext->HartSpecific [HartId] + )); + } + } + + DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__)); + DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch)); + DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform)); + DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext)); + SbiScratch->next_arg1 =3D (unsigned long)FirmwareContext; + + return 0; +} + /** Transion from SEC phase to PEI phase. =20 This function transits to S-mode PEI phase from M-mode SEC phase. @@ -508,9 +574,7 @@ VOID EFIAPI PeiCore ( EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; EFI_FIRMWARE_VOLUME_HEADER *BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)Fix= edPcdGet32(PcdRiscVPeiFvBase); EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext; - struct sbi_scratch *ScratchSpace; struct sbi_platform *ThisSbiPlatform; - UINT32 HartId; =20 FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint); =20 @@ -524,17 +588,6 @@ VOID EFIAPI PeiCore ( SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; =20 - // - // Print out scratch address of each hart - // - DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); - for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - ScratchSpace =3D sbi_hartid_to_scratch (HartId); - if(ScratchSpace !=3D NULL) { - DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); - } - } - // // Set up OpepSBI firmware context pointer on boot hart OpenSbi scratch. // Firmware context residents in stack and will be switched to memory wh= en @@ -564,20 +617,10 @@ VOID EFIAPI PeiCore ( FirmwareContext.FlattenedDeviceTree =3D Scratch->next_arg1; =20 // - // Set firmware context Hart-specific pointer + // Transfer the control to the PEI core // - for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - ScratchSpace =3D sbi_hartid_to_scratch (HartId); - if (ScratchSpace !=3D NULL) { - FirmwareContext.HartSpecific[HartId] =3D - (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); - DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-spe= cific at address: 0x%x\n", - __FUNCTION__, - HartId, - FirmwareContext.HartSpecific [HartId] - )); - } - } + FirmwareContext.SecPeiHandOffData =3D (UINT64)&SecCoreData; + // // Set supervisor translation mode to Bare mode // @@ -585,13 +628,12 @@ VOID EFIAPI PeiCore ( RiscVSetSupervisorAddressTranslationRegister ((UINT64)RISCV_SATP_MODE_OF= F << RISCV_SATP_MODE_BIT_POSITION); =20 // - // Transfer the control to the PEI core + // Scratch->next_arg1 is the device tree. // - Scratch->next_addr =3D (UINTN)(*PeiCoreEntryPoint); + Scratch->next_addr =3D (UINTN)(PeiCoreEntryPoint); Scratch->next_mode =3D PRV_S; DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %= d\n", __FUNCTION__, BootHartId)); sbi_init(Scratch); - (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable); } =20 /** @@ -715,6 +757,7 @@ VOID EFIAPI SecCoreStartUpWithStack( { UINT64 BootHartDoneSbiInit; UINT64 NonBootHartMessageLockValue; + struct sbi_platform *ThisSbiPlatform; EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext; =20 Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); @@ -737,6 +780,14 @@ VOID EFIAPI SecCoreStartUpWithStack( HartFirmwareContext->MachineImplId.Value64_H =3D 0; HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode; =20 + // + // Hook platorm_ops with EDK2 one. Thus we can have interface + // call out to OEM EDK2 platform code in M-mode before switching + // to S-mode in opensbo init. + // + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); + ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; + if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { LaunchPeiCore (HartId, Scratch); } @@ -768,6 +819,7 @@ VOID EFIAPI SecCoreStartUpWithStack( // Non boot hart wiil be halted waiting for SBI_HART_STARTING. // Use HSM ecall to start non boot hart (SBI_EXT_HSM_HART_START) later o= n, // + Scratch->next_mode =3D PRV_S; sbi_init(Scratch); } =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82316): https://edk2.groups.io/g/devel/message/82316 Mute This Topic: https://groups.io/mt/86435666/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82313+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82313+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634503; cv=none; d=zohomail.com; s=zohoarc; b=fdWGdCe+5TP5Gnz8aj4Z8xfh8krjCN6WPLc25eAJtzaJGZMulevOtiSGp4Ne+56GsZS+hxrSSfLl+I/xkPf6axnlFekZwkvlUnGUExhdgCF9TvnKRx2HzA9HqCMwez6o3uY6IOubhTlW5pVIOvH3R2a6evfAYUekwO/VJO1ySdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634503; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rOPNWg6ohWJbADztFv33Tir1rFexgdG2PxkeZlwBssc=; b=BafA4/yZTntD8EPuaChLbe/i+s34CzG3KN3P/eDIsQ9FNPRhQsdGSABVjO2MPFwzrMAHTsGAAAGk1MTizqp8az0eqNyzMXjFPf9wXaZ0h09MgJp3bMFez4E8xjs+bbIPplTCfOX81l0Iox2seQTpQqlb3X1i5Rx25AXPufOv8s8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82313+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634503975845.6609503296656; Tue, 19 Oct 2021 02:08:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Bf9gYY1788612xiKvev5GZFs; Tue, 19 Oct 2021 02:08:23 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7304.1634634500366225397 for ; Tue, 19 Oct 2021 02:08:22 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J869tN021715; Tue, 19 Oct 2021 09:08:20 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bst7b8g5c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:20 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 3628D76; Tue, 19 Oct 2021 09:08:19 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 26DB248; Tue, 19 Oct 2021 09:08:17 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor Date: Tue, 19 Oct 2021 16:09:42 +0800 Message-Id: <20211019081007.31165-6-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: O2xTd6G1OnUaN8UU1js29GuWodxLzUry X-Proofpoint-GUID: O2xTd6G1OnUaN8UU1js29GuWodxLzUry X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: KAa4kJK7pyEeQfsmmpR3JgdNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634503; bh=jqOE2G30NoG9kd3HqsqHR+9cRHXZv3KBswkrfTImuz0=; h=Cc:Date:From:Reply-To:Subject:To; b=b311iHCSJqlFhj3srbxAdKlZ+b4g9AzXh36Dg/Rv+MWOJ6XsZnogZX5QXtb99NZamab MzMa9955QChF9xPW/HLMhQK+X2QvnVA8oFGhbygmGj9yU3ElgMyQD4TgwV/hTbw3HFnXe Or5k7cmY6jkuQfIgTc7UnwYxAlBBEASyuzg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634504860100005 Content-Type: text/plain; charset="utf-8" The library to provide the platform PPI descriptors in PEI core entry before executing PEI core. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++ .../PlatformSecPpiLibNull.inf | 36 +++++++++++++++++++ .../Include/Library/PlatformSecPpiLib.h | 24 +++++++++++++ .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 +++++++++++++++ 4 files changed, 90 insertions(+) create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNu= ll/PlatformSecPpiLibNull.inf create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSec= PpiLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNu= ll/PlatformSecPpiLib.c diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 8eec09549f..b96324e961 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -61,6 +61,7 @@ [LibraryClasses.common.PEI_CORE] # RISC-V platform PEI core entry point. PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/= PeiCoreEntryPoint.inf + PlatformSecPpiLib|Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibN= ull/PlatformSecPpiLibNull.inf =20 [LibraryClasses.common.PEIM] FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/= FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf @@ -82,6 +83,7 @@ Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/= FirmwareContextProcessorSpecificLib.inf Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R= iscVPlatformTempMemoryInitLibNull.inf Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf + Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpi= LibNull.inf =20 [Components.common.SEC] Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/Plat= formSecPpiLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiL= ibNull/PlatformSecPpiLibNull.inf new file mode 100644 index 0000000000..22f5751655 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSec= PpiLibNull.inf @@ -0,0 +1,36 @@ +## @file +# Library instance to to provide PPI before PEI Core +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformSecPpiLib + FILE_GUID =3D A2CDDADC-CB65-4EED-9CAE-192B0BDD6C84 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecPpiLib|PEI_CORE + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PlatformSecPpiLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + #BaseLib + #PrintLib + diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.= h b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h new file mode 100644 index 0000000000..88468e660b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h @@ -0,0 +1,24 @@ +/** @file + RISC-V platform SEC PPI before PEI Core. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISCV_PLATFORM_SEC_PPI_H_ +#define RISCV_PLATFORM_SEC_PPI_H_ + +#include + +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList +); + +#endif diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/Plat= formSecPpiLib.c b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull= /PlatformSecPpiLib.c new file mode 100644 index 0000000000..d5c089b02d --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSec= PpiLib.c @@ -0,0 +1,28 @@ +/**@file + NULL library instance of PlatformSecPpiLib + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList +) +{ + *ThisPpiList =3D NULL; + return EFI_NOT_FOUND; +} + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82313): https://edk2.groups.io/g/devel/message/82313 Mute This Topic: https://groups.io/mt/86435663/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82320+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82320+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634507; cv=none; d=zohomail.com; s=zohoarc; b=C9S9urgzMkdd1QWUHN3Sjndfjaj4geLsY14V45dGGmu/Y2m96xlNrz94Svt8QoN2GOEM4EWnqM2JN7FHeoac8qSCF5ZJcWae4y74TKEuA1aF7Eb+XGb3dn43XGHQalej/vlEzUI1ThwInJc45dv1T4U6keZmJlFF1dI54T7wlVo= ARC-Message-Signature: i=1; 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Tue, 19 Oct 2021 02:08:26 -0700 X-Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8n1IU031360; Tue, 19 Oct 2021 09:08:21 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bstud84ts-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:21 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 963A25C; Tue, 19 Oct 2021 09:08:20 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8783F4A; Tue, 19 Oct 2021 09:08:19 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib Date: Tue, 19 Oct 2021 16:09:43 +0800 Message-Id: <20211019081007.31165-7-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZykyEeZlLmdQvDwtPmBGlNBW6XHK_P8C X-Proofpoint-ORIG-GUID: ZykyEeZlLmdQvDwtPmBGlNBW6XHK_P8C X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: pQ5UUSRQh7rdqzbssCgSzCzbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634507; bh=SUoE1Cq2yEK7yodjvu16v4aZ484HDuiJ1OSV5EGwzEo=; h=Cc:Date:From:Reply-To:Subject:To; b=Jv3AFB8/9sPNxJvgGPZdVLTMxQoyOXRZ4iRdbysBhxpYoqTHbDAU0ucNPmCPTO0Nwtb tR3TcFvjCzQUgZQEG7xdMgx7oy4X0ALnk5Vz0kXtbrhTFgznMV4i0Q7qygEnya85bmxpV SvQ9LIw3Z+dK8l4iI32invd00Cfs3Xk/SHw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634509301100029 Content-Type: text/plain; charset="utf-8" Provide PlatormSecPpiLib instance for U540 Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 + .../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 +++++ .../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/P= latformSecPpiLib.inf create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/P= latformSecPpiLib.c diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index be23fc39fd..d12af19825 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -192,6 +192,7 @@ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf # RISC-V platform PEI core entry point. PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/= PeiCoreEntryPoint.inf + PlatformSecPpiLib|Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/= PlatformSecPpiLib.inf =20 [LibraryClasses.common.PEIM] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/Platform= SecPpiLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/Platf= ormSecPpiLib.inf new file mode 100644 index 0000000000..7e9e1a5e20 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiL= ib.inf @@ -0,0 +1,43 @@ +## @file +# Library instance to to provide PPI before PEI Core +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformSecPpiLib + FILE_GUID =3D 8F8E049E-F193-427C-998E-1E8FE2612D94 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecPpiLib|PEI_CORE + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PlatformSecPpiLib.c + +[Ppis] +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + RiscVFirmwareContextLib diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/Platform= SecPpiLib.c b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/Platfor= mSecPpiLib.c new file mode 100644 index 0000000000..ef84e8c1bc --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiL= ib.c @@ -0,0 +1,148 @@ +/**@file + Library to install platform PPI before PEI Core + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); + +STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** Temporary RAM migration function. + + This function migrates the data from temporary RAM to permanent + memory. + + @param[in] PeiServices PEI service + @param[in] TemporaryMemoryBase Temporary memory base address + @param[in] PermanentMemoryBase Permanent memory base address + @param[in] CopySize Size to copy + +**/ +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + DEBUG ((DEBUG_INFO, + "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n", + __FUNCTION__, + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + GetFirmwareContextPointer (&FirmwareContext); + FirmwareContext =3D (VOID *)FirmwareContext + (unsigned long)((UINTN)New= Stack - (UINTN)OldStack); + SetFirmwareContextPointer (FirmwareContext); + + // + // Relocate PEI Service ** + // + FirmwareContext->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - = (UINTN)OldStack); + DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n= ", __FUNCTION__, FirmwareContext)); + DEBUG ((DEBUG_INFO, "OpenSBI Firmware Context at 0x%x\n", FirmwareContex= t)); + DEBUG ((DEBUG_INFO, " PEI Service at 0x%x\n\n", FirmwareCont= ext->PeiServiceTable)); + + register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +/** Temprary RAM done function. + +**/ +EFI_STATUS EFIAPI TemporaryRamDone ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FU= NCTION__)); + return EFI_SUCCESS; +} +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList +) +{ + *ThisPpiList =3D mPrivateDispatchTable; + return EFI_SUCCESS; +} + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82320): https://edk2.groups.io/g/devel/message/82320 Mute This Topic: https://groups.io/mt/86435670/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82323+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82323+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634511; cv=none; d=zohomail.com; s=zohoarc; b=KRjTKhb8DOE/Srrl934b6B322VEx/CajvwlDgk99Xmfa34VHpTb95iilG6UxjoHJwKYPuKClz+HTN1D3vY8e2VgfZ0YfU/IWZzWeBKQ6Dxh1DLiqTdl8MAW95tapvgMkvzQZrHQSOdu8q/kDmddn5C3CRX2IonEHFssHLqJq42c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634511; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ou3x1bdtGNcs1wgdmL0J+1uhI+IaTTKqaym7UbUFS8k=; b=LcK3hPqvpLxVPRu1vG3G0okmaKbwWPYo5NivRNBbrMVeGeL0cH5SGplPlMlyDmX7pZ9f96NteoEO4zfGmfoQP9g0XRsPuK8O4keZ9HIjfVRJXXtLaXTBYAB33KLkWmby2SiTPsWb792gtabfKOKRNhlzX/X8Jk8h6jpvYDRvxe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82323+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634511637667.6214922458857; Tue, 19 Oct 2021 02:08:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OparYY1788612x76sabpBEob; Tue, 19 Oct 2021 02:08:31 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7398.1634634502842422685 for ; Tue, 19 Oct 2021 02:08:30 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J84La2029873; Tue, 19 Oct 2021 09:08:22 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 3bst6drgnq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:22 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 010904E; Tue, 19 Oct 2021 09:08:21 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id E737A48; Tue, 19 Oct 2021 09:08:20 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib Date: Tue, 19 Oct 2021 16:09:44 +0800 Message-Id: <20211019081007.31165-8-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: V6EgZKBhjgkjDoKed80e_dNO12gSTTlv X-Proofpoint-GUID: V6EgZKBhjgkjDoKed80e_dNO12gSTTlv X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: IDn8RVcM4uQ8bm1W8ttDkBS2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634511; bh=rabTFwxG1t439yMB3Rv++bYrY4vxxuvXE76bs9DdycA=; h=Cc:Date:From:Reply-To:Subject:To; b=AzeeEtQIjC+SRPyzD+vc0/KI1FNQ2NouhZ6DAgb9rTL0/5OaVEs4GMVDVigCuHH6N2C agnmypHN9gkzdir/nXvQ43Kzt7wB+PBzOjDDbUmUgdGHkd79DPT3vSnR7AQbOySKXm3lS 9hWaamKLiAaiZCDuOihujX4M5CkiaJEqziQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634513642100002 Content-Type: text/plain; charset="utf-8" Use PlatformSecPpiLib to get PPI descriptor and remove PPI descriptor related code from SEC. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 + .../PlatformPkg/Universal/Sec/SecMain.inf | 4 - .../PlatformPkg/Universal/Sec/SecMain.h | 17 ---- .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 15 +++- .../PlatformPkg/Universal/Sec/SecMain.c | 84 ------------------- 5 files changed, 14 insertions(+), 107 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo= reEntryPoint.inf index e16a974636..4f3af27bcf 100644 --- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.inf +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.inf @@ -32,5 +32,6 @@ [LibraryClasses] BaseLib DebugLib + PlatformSecPpiLib RiscVFirmwareContextLib =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 4207c83413..9736277fa1 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -52,10 +52,6 @@ RiscVOpensbiPlatformLib RiscVEdk2SbiLib =20 -[Ppis] - gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED - gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED - [FixedPcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.h index c04ddbad7f..496799efc0 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h @@ -25,8 +25,6 @@ #include #include #include -#include -#include =20 int SecPostOpenSbiPlatformEarlylInit( @@ -49,19 +47,4 @@ SecStartupPhase2 ( IN VOID *Context ); =20 -EFI_STATUS -EFIAPI -TemporaryRamMigration ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize - ); - -EFI_STATUS -EFIAPI -TemporaryRamDone ( - VOID - ); - #endif // _SECMAIN_H_ diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCore= EntryPoint.c index 2fd0f2315b..16488b7bc9 100644 --- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.c +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 /** @@ -49,15 +50,25 @@ _ModuleEntryPoint( IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList ) { + EFI_STATUS Status; EFI_SEC_PEI_HAND_OFF *ThisSecCoreData; EFI_PEI_PPI_DESCRIPTOR *ThisPpiList; EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; =20 FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList; SetFirmwareContextPointer (FirmwareContext); + FirmwareContext->BootHartId =3D (UINT64)SecCoreData; + ThisSecCoreData =3D (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandO= ffData; - ThisPpiList =3D (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoff= Ppi; - ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL); + Status =3D GetPlatformPrePeiCorePpiDescriptor (&ThisPpiList); + if (EFI_ERROR (Status)) { + ThisPpiList =3D NULL; + } + + // + // Invoke PEI Core entry point. + // + ProcessModuleEntryPointList(ThisSecCoreData, ThisPpiList, NULL); =20 // // Should never return diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 44984b0078..fb0adbca54 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -312,90 +312,6 @@ FindAndReportEntryPoints ( =20 return; } -/* - Print out the content of firmware context. - -**/ -VOID -DebugPrintFirmwareContext ( - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext - ) -{ - DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context at 0x%x\n", __FUNCTION= __, FirmwareContext)); - DEBUG ((DEBUG_INFO, "%a: PEI Service at 0x%x\n\n", __FUNCTI= ON__, FirmwareContext->PeiServiceTable)); -} -/** Temporary RAM migration function. - - This function migrates the data from temporary RAM to permanent - memory. - - @param[in] PeiServices PEI service - @param[in] TemporaryMemoryBase Temporary memory base address - @param[in] PermanentMemoryBase Permanent memory base address - @param[in] CopySize Size to copy - -**/ -EFI_STATUS -EFIAPI -TemporaryRamMigration ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize - ) -{ - VOID *OldHeap; - VOID *NewHeap; - VOID *OldStack; - VOID *NewStack; - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; - - DEBUG ((DEBUG_INFO, - "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n", - __FUNCTION__, - TemporaryMemoryBase, - PermanentMemoryBase, - (UINT64)CopySize - )); - - OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; - NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); - - OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); - NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; - - CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap - CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack - - // - // Reset firmware context pointer - // - SbiGetFirmwareContext (&FirmwareContext); - FirmwareContext =3D (VOID *)FirmwareContext + (unsigned long)((UINTN)New= Stack - (UINTN)OldStack); - SbiSetFirmwareContext (FirmwareContext); - - // - // Relocate PEI Service ** - // - FirmwareContext->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - = (UINTN)OldStack); - DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n= ", __FUNCTION__, FirmwareContext)); - DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext); - - register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); - asm volatile ("add sp, sp, a0"::"r"(a0):); - return EFI_SUCCESS; -} - -/** Temprary RAM done function. - -**/ -EFI_STATUS EFIAPI TemporaryRamDone ( - VOID - ) -{ - DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FU= NCTION__)); - return EFI_SUCCESS; -} =20 /** Handles SBI calls of EDK2's SBI FW extension. --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82323): https://edk2.groups.io/g/devel/message/82323 Mute This Topic: https://groups.io/mt/86435675/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82322+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82322+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634509; cv=none; d=zohomail.com; s=zohoarc; b=NFhAKXgFVW5BvV6Fp/FyY8U/9X4/rhYQ56j9xfZ8SvuJQcMTpKnmoynxl6iTklwYdG2Xoj3s7pxVh1yPms/FOZnHYU6AwGDX3SvWjtn7TOsQnA/rqOrqbhI1C+b460dRkodn/cypJyBSNUhz4Ehk+rJxEwTVvcr7fbu3TCwe4bo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=B9CXGJRERBUSrINcyGYKkj3p7kVsMnXinT7Xe65p7B4=; b=KNuVla1h7y5ZYTKOJq671op3Qni+SQ+e3vCEmz5U+f8v/TMs4tYRcQ4lVz+E9vbD0q91kLStUcyEDi+UTvEX6eGiJumq9jP/US3nlWRogCZCl+qTdOBdJCbUoJW3hklSlf3n+l6Hrtp5Ok072whUOs1XT/k+sZA5/mX8ZYNLAY8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82322+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634509398231.0960021805239; Tue, 19 Oct 2021 02:08:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0jdFYY1788612xdNZ4vGH4hJ; Tue, 19 Oct 2021 02:08:29 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7275.1634634504464178453 for ; Tue, 19 Oct 2021 02:08:28 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8W6Ou012314; Tue, 19 Oct 2021 09:08:24 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qrw2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:24 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 62B194E; Tue, 19 Oct 2021 09:08:23 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 536464B; Tue, 19 Oct 2021 09:08:22 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib Date: Tue, 19 Oct 2021 16:09:45 +0800 Message-Id: <20211019081007.31165-9-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: w8ra750Tij4C2qY0zYQBgJ_gi4_m_9BC X-Proofpoint-ORIG-GUID: w8ra750Tij4C2qY0zYQBgJ_gi4_m_9BC X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: wm4KxC6YuUL0fmj4WZ1D5afIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634509; bh=A9K7ZthQU5KSw11K9bzU9x0Cgyfxc5Gz8ACUK3elP2o=; h=Cc:Date:From:Reply-To:Subject:To; b=q7Wl2OQ3XivEsvZ0JX1+f8xaEXX59TTlZBifls/7uHtpXUQNiClguaa7EyjksNYA+I1 LZDIlZ6ZCEM1A4hY5KCVCBoRranH2/0Hw2Jrt/+xi2iiRF2Pa2Gw95uZIrv4xmAcBZ5FG cpwcfVcnTANO/PB9Tz5NsqC1QqX1YG0X5DY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634511430100002 Content-Type: text/plain; charset="utf-8" CoreInfoHob uses RiscVFirmwareContextLib to get the pointer of FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 ++- Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreI= nfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCo= reInfoHobLib.inf index d741f04747..4fe7827313 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL= ib.inf @@ -34,9 +34,10 @@ =20 [LibraryClasses] BaseLib - PcdLib MemoryAllocationLib + PcdLib PrintLib + RiscVFirmwareContextLib SiliconSiFiveU54CoreInfoLib =20 [Guids] diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c index 326c4525bb..37363a0028 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -1,7 +1,7 @@ /**@file Build up platform processor information of SiFive U54 core. =20 - Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -17,7 +17,7 @@ #include #include #include -#include +#include =20 #include #include @@ -63,7 +63,7 @@ CreateU54E51CoreProcessorSpecificDataHob ( return EFI_INVALID_PARAMETER; } =20 - SbiGetFirmwareContext (&FirmwareContext); + GetFirmwareContextPointer (&FirmwareContext); ASSERT (FirmwareContext !=3D NULL); if (FirmwareContext =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_OPENSBI_F= IRMWARE_CONTEXT of hart %d\n", HartId)); --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82322): https://edk2.groups.io/g/devel/message/82322 Mute This Topic: https://groups.io/mt/86435673/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82319+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82319+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634506; cv=none; d=zohomail.com; s=zohoarc; b=XNMz+VbU8Ro2ctj9XB/4bdhFXDBGJ1iAmhE45ABdGqTYvUbCfQHpi3Q2iFFZObqh21dzr1lG97lhe5DABXuDQjbrhgm+b5MAlCA4lIEOgNs79x1KM0WSInrKZzc2IDTzelk/6blTaKoClPgtGu20xII4j2lbHp8JoloO//88TUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634506; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1ZFKtb4eEGq9XtSuzCK9M2Wu6tr7m438h8VtSTbHgs0=; b=U9GYJwhQwIxaADaFIj+6oFKuw/1KPh/JHDCXtystnrr/XqbbGXsjMnIenO5v8F70d3q8vWsZF02Z9e8ZOlCYt0f4smwivP0dTYRDfuZdg011Zam4RxuWktDGAryCRd2uk5o/lwSniB3AJGCutXmOUNissq1vfQ5HlJBXsBViDdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82319+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634506792308.9672105768685; Tue, 19 Oct 2021 02:08:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ySkgYY1788612x30yyNzF2et; Tue, 19 Oct 2021 02:08:26 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7305.1634634505981371978 for ; Tue, 19 Oct 2021 02:08:26 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J86nB2022318; Tue, 19 Oct 2021 09:08:25 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bst7b8g68-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:25 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id C4D5C62; Tue, 19 Oct 2021 09:08:24 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id B527648; Tue, 19 Oct 2021 09:08:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Date: Tue, 19 Oct 2021 16:09:46 +0800 Message-Id: <20211019081007.31165-10-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-Proofpoint-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: MZuALcKJV8NjxAHCEc67pL3Ex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634506; bh=YM+Tz6BbklRmnrycOtsugTSL6b5ayWzOBr/OC24etkk=; h=Cc:Date:From:Reply-To:Subject:To; b=DYh/QmFjYYF9iLiZ+Br5lUaOctgDi7QSazdH2V2t6J8Dp1EJab/gD01TvGRqkHieUcm zsf7DS7E0p90rw2yg6HM8NE+Q2hLkEQd4RciiJxd6TczRy6ewkRkJqJ7BEzxmT/CtrY0r UtiZfvXqHNF4ChLJGL3uaGE6ugBqqpOxYVA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634507183100020 Content-Type: text/plain; charset="utf-8" Add CLINT to Device Tree on U540 platform for M-mode timer and IPI. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../DeviceTree/fu540-c000.dtsi | 591 +++++++++--------- 1 file changed, 304 insertions(+), 287 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/DeviceTree/fu540-c000.dtsi index e44b6f7c56..1d8518cfb7 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi @@ -1,287 +1,304 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -/*#include */ -#include "sifive-fu540-prci.h" - -/ { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - ethernet0 =3D ð0; - }; - - chosen { - }; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - cpu0: cpu@0 { - compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <16384>; - reg =3D <0>; - riscv,isa =3D "rv64imac"; - status =3D "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <1>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <2>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <3>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <4>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells =3D <1>; - compatible =3D "sifive,plic-1.0.0"; - reg =3D <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev =3D <53>; - interrupt-controller; - interrupts-extended =3D < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible =3D "sifive,fu540-c000-prci"; - reg =3D <0x0 0x10000000 0x0 0x1000>; - clocks =3D <&hfclk>, <&rtcclk>; - #clock-cells =3D <1>; - }; - uart0: serial@10010000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10010000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <4>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - dma: dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; - reg =3D <0x0 0x3000000 0x0 0x8000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <23 24 25 26 27 28 29 30>; - #dma-cells =3D <1>; - }; - uart1: serial@10011000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10011000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <5>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - i2c0: i2c@10030000 { - compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg =3D <0x0 0x10030000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <50>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - reg-shift =3D <2>; - reg-io-width =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi0: spi@10040000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <51>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi1: spi@10041000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <52>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi2: spi@10050000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10050000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <6>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - eth0: ethernet@10090000 { - compatible =3D "sifive,fu540-c000-gem"; - interrupt-parent =3D <&plic0>; - interrupts =3D <53>; - reg =3D <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address =3D [00 00 00 00 00 00]; - clock-names =3D "pclk", "hclk"; - clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - pwm0: pwm@10020000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10020000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <42 43 44 45>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - pwm1: pwm@10021000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10021000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <46 47 48 49>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible =3D "sifive,fu540-c000-ccache", "cache"; - cache-block-size =3D <64>; - cache-level =3D <2>; - cache-sets =3D <1024>; - cache-size =3D <2097152>; - cache-unified; - interrupt-parent =3D <&plic0>; - interrupts =3D <1 2 3>; - reg =3D <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent =3D <&plic0>; - interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg =3D <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells =3D <2>; - interrupt-controller; - #interrupt-cells =3D <2>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - }; -}; +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +/**@file + SiFive U540 platform Device Tree + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "sifive-fu540-prci.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + ethernet0 =3D ð0; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu@0 { + compatible =3D "sifive,e51", "sifive,rocket0", "ri= scv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + status =3D "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl= e-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial@10010000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0"; + reg =3D <0x0 0x10010000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + dma: dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <23 24 25 26 27 28 29 30>; + #dma-cells =3D <1>; + }; + uart1: serial@10011000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0"; + reg =3D <0x0 0x10011000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <5>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + i2c0: i2c@10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2= c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi@10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi@10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi@10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet@10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm0: pwm@10020000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10020000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <42 43 44 45>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + pwm1: pwm@10021000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0"; + reg =3D <0x0 0x10021000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <46 47 48 49>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible =3D "sifive,fu540-c000-ccache", "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic0>; + interrupts =3D <1 2 3>; + reg =3D <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible =3D "sifive,fu540-c000-gpio", "sifive,g= pio0"; + interrupt-parent =3D <&plic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1= 3>, + <14>, <15>, <16>, <17>, <18>, <19>, <= 20>, + <21>, <22>; + reg =3D <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + clint: clint@2000000 { + compatible =3D "riscv,clint0"; + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg =3D <0x0 0x2000000 0x0 0xc0000>; + }; + }; +}; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82319): https://edk2.groups.io/g/devel/message/82319 Mute This Topic: https://groups.io/mt/86435669/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82321+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82321+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634509; cv=none; d=zohomail.com; s=zohoarc; b=PsRDhTyAuFbzn2Kniv6d93G3K0MUowD7f/A2uzi4Qpggb10kOofWDgFFz2sFVB0ipKntdCn20f7sG0ZHGl4JmStByDlFByho1CP4vUKMjFkGtKeP7DEVzVrgmpX5jvkh+0QSOyDM/o/vB8jFBraB8tTkSuPjSqRd4ilD2nU+2A4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=I/GTvxxJY1zkLZkfakK5jmFFqb0OQ+JmdbZGd55aX8c=; b=fAuXNZYYUMtPaNbnxv1bJ+rJzgDbUEldtrbgaDw2q5ZAewiWwLRogX1/m5g4NMl/AYhGXXySY2CiFfRjklOW+03g3MqQiMRgz3V2Sh0dHTABY/7+14zw8IaUunsprp2K00I3XyVOPCNRTaCoYIb1lt3BZhBB08koB3Kw0NUIyH8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82321+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634509789195.05582259175867; Tue, 19 Oct 2021 02:08:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id nsBHYY1788612xX427aFskNx; Tue, 19 Oct 2021 02:08:29 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7276.1634634507235827302 for ; Tue, 19 Oct 2021 02:08:28 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8CJbV021113; Tue, 19 Oct 2021 09:08:27 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 3bsta50egw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:26 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 32F3292; Tue, 19 Oct 2021 09:08:26 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 236DC4D; Tue, 19 Oct 2021 09:08:24 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Date: Tue, 19 Oct 2021 16:09:47 +0800 Message-Id: <20211019081007.31165-11-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: YjaF4DiTFXZQebb9izgstJ0CtPK7KxPf X-Proofpoint-ORIG-GUID: YjaF4DiTFXZQebb9izgstJ0CtPK7KxPf X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: wDHzngbwXJUiqRhGci6f7kmex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634509; bh=S0YVHLTl9KtjkQFfZoK7eZ+sA5BpRYVRJ5e+BqbpfXg=; h=Cc:Date:From:Reply-To:Subject:To; b=BsYB+LxH5zitxJNLMzJEdbxLkEd5X48+mPH7Z03tybt4UM2w0FXuw55/ebopjsSZO2N h05iESc7P1Oxq2Zmv+xPB1V8ViTQa3fYVJu/rPuT3IdHMTyc51VKTMtRe3UyyQ9Enj6Ra rCHN2eIDITMFe5pIdhpqRhvN8KSCKgx7GGQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634511455100004 Content-Type: text/plain; charset="utf-8" This is the library instance to provide platform_override for the special RISC-V platform. This module incorporates with OpensbiPlatformLib and RISC-V Opensbi library. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 + .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++ .../RiscVSpecialPlatformLib.inf | 36 +++++++++++++++++++ .../Include/Library/RiscVSpecialPlatformLib.h | 20 +++++++++++ .../RiscVSpecialPlatformLib.c | 19 ++++++++++ 5 files changed, 78 insertions(+) create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatfor= mLib/RiscVSpecialPlatformLib.inf create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecia= lPlatformLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatfor= mLib/RiscVSpecialPlatformLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dec index 08279a97b1..9c8b57cce3 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec @@ -19,6 +19,7 @@ Include/Library Library/RiscVOpensbiLib/opensbi # OpenSBI header file reference = ("include/sbi/...") Library/RiscVOpensbiLib/opensbi/include # Header file reference from ope= nsbi files, ("sbi/...") + Library/RiscVOpensbiLib/opensbi/platform/generic/include # Header file r= eference from opensbi files, ("sbi/...") =20 [LibraryClasses] RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index b96324e961..ec8875be14 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -71,6 +71,7 @@ =20 [LibraryClasses.common.SEC] ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecial= PlatformLib/RiscVSpecialPlatformLib.inf =20 [LibraryClasses.common.DXE_DRIVER] PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf @@ -84,6 +85,7 @@ Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R= iscVPlatformTempMemoryInitLibNull.inf Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpi= LibNull.inf + Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecial= PlatformLib.inf =20 [Components.common.SEC] Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ri= scVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecia= lPlatformLib/RiscVSpecialPlatformLib.inf new file mode 100644 index 0000000000..567eeee56d --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpec= ialPlatformLib.inf @@ -0,0 +1,36 @@ +## @file +# Null library instance to provide platform_override for the +# special RISC-V platform. This module incorporates with +# OpensbiPlatformLib and RISC-V Opensbi library. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSpecialPlatformLib + FILE_GUID =3D 79361802-18B6-458A-8C79-DA6256DEF776 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSpecialPlatformLib|SEC + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVSpecialPlatformLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatfo= rmLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformL= ib.h new file mode 100644 index 0000000000..644bb08ebf --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h @@ -0,0 +1,20 @@ +/** @file + library definition to provide platform_override of special platforms. + This library incorporates with OpensbiPlatformLib and RISC-V Opensbi lib= rary + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISCV_SPECIAL_PLATFORM_LIB_ +#define RISCV_SPECIAL_PLATFORM_LIB_ + +#include + +// +// This is declared under Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbi= Lib/opensbi/platform/generic/include/ +// +#include + +#endif diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ri= scVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialP= latformLib/RiscVSpecialPlatformLib.c new file mode 100644 index 0000000000..3a77ff6b17 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpec= ialPlatformLib.c @@ -0,0 +1,19 @@ +/**@file + Library to provide platform_override for the special + RISC-V platform. This module incorporates with + OpensbiPlatformLib and RISC-V Opensbi library. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +const struct platform_override *SpecialPlatformArray =3D NULL; +INTN NumberOfPlaformsInArray; + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82321): https://edk2.groups.io/g/devel/message/82321 Mute This Topic: https://groups.io/mt/86435672/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82331+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82331+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634522; cv=none; d=zohomail.com; s=zohoarc; b=HjB4JIEV2D8MUewFTFQBvK0hN2JOsq1+Z6wETvjjdscHuWBdUtqBnbSCmuTySTSVirPRBFD+Ar3/YhR//YMl8tITxS58OfWa+Gqp+ypSvjP5jEn+pQDniViDTrNIhLC/zwuzxdqQ6rsQLU7vA6w3D+ZON8ijSGoiu+hYOOfti3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634522; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6RQSI4YeaFjpRrUwuY12rzDgzk9BRo0AmvGlqIiRULM=; b=k2DMcgAXdcXPNH4BLkM0/M40hhQzdju6vdtwvqH/rneO0lnFealwYGbbQHco4+jz6aFuhNfOTw+uzmRKiOreL7x4bh8cVVRd7p/Jnc4ixP3TL1OzN03J3oTEbtV6rHYzILY08Di1aySygbs4ZBaVfhUP3/ssrCtf1Gv7x8Z2EmM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82331+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 163463452276649.16190797756849; Tue, 19 Oct 2021 02:08:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AeJpYY1788612xtOjDSylcbf; Tue, 19 Oct 2021 02:08:42 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7401.1634634508457345765 for ; Tue, 19 Oct 2021 02:08:40 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J84Yq1030517; Tue, 19 Oct 2021 09:08:28 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com with ESMTP id 3bst6drgpg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:28 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 933686A; Tue, 19 Oct 2021 09:08:27 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8401B4F; Tue, 19 Oct 2021 09:08:26 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540 Date: Tue, 19 Oct 2021 16:09:48 +0800 Message-Id: <20211019081007.31165-12-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pMkSp9cJsOcEN7BQFfrX4K7-myeObQ64 X-Proofpoint-GUID: pMkSp9cJsOcEN7BQFfrX4K7-myeObQ64 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: mJRzNlmNBMjYdDPFiLy8qQQhx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634522; bh=QNJCuuO915QBJypl/2CSfkH6gBOZBf0uh5z9vEZp39I=; h=Cc:Date:From:Reply-To:Subject:To; b=VSVH/1DKIZN5OKlayS3AB53C/czsdcOxOx/NbFORzg9csc1FQtHQwJa47VPvL09W4J4 28cAtcUgHgz8rasxYLA73NcJd6cM59WThQUcwzsCocgsLIOM18Lk+hTyUnLjXPaf5nUpN 9RDllfjDdt9c0TrCCSjtvNaZslTdZH6SWvE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634524917100029 Content-Type: text/plain; charset="utf-8" Provide platform_override of U540 platform. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 + .../RiscVSpecialPlatformLib.inf | 36 ++++++++++++ .../RiscVSpecialPlatformLib/SifiveFu540.c | 56 +++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedB= oard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedB= oard/Library/RiscVSpecialPlatformLib/SifiveFu540.c diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index d12af19825..71dbca0e96 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -163,6 +163,7 @@ =20 ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + RiscVSpecialPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf =20 !ifdef $(SOURCE_DEBUG_ENABLE) DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/SiFive= /U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLi= b/RiscVSpecialPlatformLib.inf new file mode 100644 index 0000000000..26f475ca45 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/R= iscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf @@ -0,0 +1,36 @@ +## @file +# Null library instance to provide platform_override for the +# special RISC-V platform. This module incorporates with +# OpensbiPlatformLib and RISC-V Opensbi library. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSpecialPlatformLib + FILE_GUID =3D FE0AE3E6-90A4-421D-851D-E092CBEEE645 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSpecialPlatformLib|SEC + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + SifiveFu540.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/RiscVSpecialPlatformLib/SifiveFu540.c b/Platform/SiFive/U5SeriesPkg/F= reedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/SifiveFu540.c new file mode 100644 index 0000000000..e89403f7ff --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/R= iscVSpecialPlatformLib/SifiveFu540.c @@ -0,0 +1,56 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +#include +#include +#include + +static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match) +{ + /* + * The sfence.vma by virtual address does not work on + * SiFive FU540 so we return remote TLB flush limit as zero. + */ + return 0; +} + +static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match) +{ + /* + * SiFive Freedom U540 has an erratum that prevents S-mode software + * to access a PMP protected region using 1GB page table mapping, so + * always add the no-map attribute on this platform. + */ + fdt_reserved_memory_nomap_fixup(fdt); + + return 0; +} + +static const struct fdt_match sifive_fu540_match[] =3D { + { .compatible =3D "sifive,fu540" }, + { .compatible =3D "sifive,fu540g" }, + { .compatible =3D "sifive,fu540-c000" }, + { .compatible =3D "sifive,hifive-unleashed-a00" }, + { }, +}; + +const struct platform_override sifive_fu540 =3D { + .match_table =3D sifive_fu540_match, + .tlbr_flush_limit =3D sifive_fu540_tlbr_flush_limit, + .fdt_fixup =3D sifive_fu540_fdt_fixup, +}; + +const struct platform_override *special_platforms[] =3D { + &sifive_fu540, +}; +INTN NumberOfPlaformsInArray =3D array_size(special_platforms); --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82331): https://edk2.groups.io/g/devel/message/82331 Mute This Topic: https://groups.io/mt/86435683/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82326+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82326+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634517; cv=none; d=zohomail.com; s=zohoarc; b=AOX7+cosL+VRj9ELrx7zqBD57sYehIkz0uHwDq/OUUdqeI6G5yy0pbzqXr/cBfEkrsAOyBR2LnTSZJp5poWFIpJVBLMqmleCUkENZ9yTWlw+tJLg04oYvi23OVZWLtA6JOBhl8S7xXja+F3onDJykkVa9kXmSwsDdnq/95yr640= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634517; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5tUerDdxXYA3DFbyxbLY9lGm4/+yZCvRC2gXBZeIBdo=; b=jv0wyzxW8FbpgbeWYCW+J2Vn7M2S/s/7QiP567W/ffyNJczHYIbgZ9gu6SQCXsO4SJ17STsbnNAaS+lzZY77KbnuadIWgIyFMqDk/XjKuuL4T2yXnGNyaavj3tdl387Tkv6XyAQCV06fFkXzw/Bd63LNIZniaak2idAtX83J7Vo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82326+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634517258319.12805020456346; Tue, 19 Oct 2021 02:08:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 54naYY1788612xzmgy4VBUrI; Tue, 19 Oct 2021 02:08:36 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7307.1634634510127855160 for ; Tue, 19 Oct 2021 02:08:36 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J81rT1029136; Tue, 19 Oct 2021 09:08:30 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gs5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:29 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id F217C6A; Tue, 19 Oct 2021 09:08:28 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id E4F4C4E; Tue, 19 Oct 2021 09:08:27 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library Date: Tue, 19 Oct 2021 16:09:49 +0800 Message-Id: <20211019081007.31165-13-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: EmXl6wY_4M0Ra8ottq0l-xgnv9veBsXo X-Proofpoint-ORIG-GUID: EmXl6wY_4M0Ra8ottq0l-xgnv9veBsXo X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 1wIK8LWOcj4bWeCsAdlW25b2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634516; bh=GP9srVSiRbYW+BjaHKljJWcH9hF/bspbb5zcK6Gqvyo=; h=Cc:Date:From:Reply-To:Subject:To; b=H1lI68WdQ/g+QtyX7TtP6tUntMWI/4M62onS8SPgXsbjTqvp6pxhc2b2uWJwg2YEd07 cWpFn5v0RNm8S84xh/lCaCbNiFcayCk9scF7582BLyHEHkadcFRC1zAk3yS0z6BC3dvVk nuVjD1YU19l4w7RxcZ+HXng7RI48+HDki2Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634518386100006 Content-Type: text/plain; charset="utf-8" This is the generic library for all RISC-V platforms. Remove the dependencies of SiFive U540 platform. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 +- .../OpensbiPlatformLib/PlatformOverride.h | 30 ------------ .../Library/OpensbiPlatformLib/Platform.c | 25 +++++++--- .../Library/OpensbiPlatformLib/SifiveFu540.c | 47 ------------------- 4 files changed, 19 insertions(+), 86 deletions(-) delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= PlatformOverride.h delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= SifiveFu540.c diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index a408737961..909fbffa8d 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -25,8 +25,6 @@ =20 [Sources] Platform.c - SifiveFu540.c - PlatformOverride.h =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -45,6 +43,7 @@ PcdLib PrintLib RiscVCpuLib + RiscVSpecialPlatformLib =20 [FixedPcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= mOverride.h b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfo= rmOverride.h deleted file mode 100644 index 467ebbd4b8..0000000000 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverri= de.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2020 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel - */ - -#ifndef __PLATFORM_OVERRIDE_H__ -#define __PLATFORM_OVERRIDE_H__ - -#include - -struct platform_override { - const struct fdt_match *match_table; - u64 (*features)(const struct fdt_match *match); - u64 (*tlbr_flush_limit)(const struct fdt_match *match); - int (*early_init)(bool cold_boot, const struct fdt_match *match); - int (*final_init)(bool cold_boot, const struct fdt_match *match); - void (*early_exit)(const struct fdt_match *match); - void (*final_exit)(const struct fdt_match *match); - int (*system_reset_check)(u32 reset_type, u32 reset_reason, - const struct fdt_match *match); - void (*system_reset)(u32 reset_type, u32 reset_reason, - const struct fdt_match *match); - int (*fdt_fixup)(void *fdt, const struct fdt_match *match); -}; - -#endif diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index 4fbb201895..06cd1a299f 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -5,10 +5,16 @@ * * Authors: * Anup Patel + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + */ =20 #include -#include +#include + #include #include #include @@ -24,11 +30,12 @@ #include #include =20 -extern const struct platform_override sifive_fu540; - -static const struct platform_override *special_platforms[] =3D { - &sifive_fu540, -}; +// +// SpecialPlatformArray and NumberOfSpecialPlatform are +// provided by RiscVSpecialPlatformLib library. +// +extern const struct platform_override *special_platforms[]; +extern INTN NumberOfPlaformsInArray; =20 static const struct platform_override *generic_plat =3D NULL; static const struct fdt_match *generic_plat_match =3D NULL; @@ -39,7 +46,11 @@ static void fw_platform_lookup_special(void *fdt, int ro= ot_offset) const struct platform_override *plat; const struct fdt_match *match; =20 - for (pos =3D 0; pos < array_size(special_platforms); pos++) { + if (special_platforms =3D=3D NULL || NumberOfPlaformsInArray =3D=3D 0)= { + return; + } + + for (pos =3D 0; pos < (int)NumberOfPlaformsInArray; pos++) { plat =3D special_platforms[pos]; if (!plat->match_table) continue; diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveF= u540.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540= .c deleted file mode 100644 index 748b058840..0000000000 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2020 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel - */ - -#include -#include -#include - -static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match) -{ - /* - * The sfence.vma by virtual address does not work on - * SiFive FU540 so we return remote TLB flush limit as zero. - */ - return 0; -} - -static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match) -{ - /* - * SiFive Freedom U540 has an erratum that prevents S-mode software - * to access a PMP protected region using 1GB page table mapping, so - * always add the no-map attribute on this platform. - */ - fdt_reserved_memory_nomap_fixup(fdt); - - return 0; -} - -static const struct fdt_match sifive_fu540_match[] =3D { - { .compatible =3D "sifive,fu540" }, - { .compatible =3D "sifive,fu540g" }, - { .compatible =3D "sifive,fu540-c000" }, - { .compatible =3D "sifive,hifive-unleashed-a00" }, - { }, -}; - -const struct platform_override sifive_fu540 =3D { - .match_table =3D sifive_fu540_match, - .tlbr_flush_limit =3D sifive_fu540_tlbr_flush_limit, - .fdt_fixup =3D sifive_fu540_fdt_fixup, -}; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82326): https://edk2.groups.io/g/devel/message/82326 Mute This Topic: https://groups.io/mt/86435678/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82325+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82325+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634516; cv=none; d=zohomail.com; s=zohoarc; b=DU0seXHNEuwSAbf1vV2pAUU2EJvIVXlQ97nXMSea4ilypn+CmFcK2LxSbFdlgHRl3ytf6Ji7sCvFyi0oUKCxFCtnyAkC4PLOMfSplxuNsara4vfYBmGqRMlYNq+9tGIqdy9i58+opLXie/n7FqtheYmVdP1U79yTG6GWh4TbeJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634516; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HsNOpMNgOSr+zvIWEJmNWewwOZA8LQztAw6dNjCPQwQ=; b=SA5Hx6Q40Wp28SaoU0S5AZ2ei1jvS03hWNl3FTsCrXQul2nEkMX5w26TDrJroAys6vyaRZYNuiwAIsT6lwnZC0GSm7/k4QP889jt7dZxgESIF3y5R9fWz6y4SO6xR6JFIOpTtBlr88GGY64TF1ybKerjDu8cFXygLcyaV89SoJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82325+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634516296682.4055556511338; Tue, 19 Oct 2021 02:08:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tmYAYY1788612xwm2KAjQxMr; Tue, 19 Oct 2021 02:08:36 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7278.1634634511479646315 for ; Tue, 19 Oct 2021 02:08:35 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J81swS005268; Tue, 19 Oct 2021 09:08:31 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qrww-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:31 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 5E6B36B; Tue, 19 Oct 2021 09:08:30 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 4F96A48; Tue, 19 Oct 2021 09:08:29 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull Date: Tue, 19 Oct 2021 16:09:50 +0800 Message-Id: <20211019081007.31165-14-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: bWDxyvcgjJ7CtoxEdJEYSH4pG9-8F4SV X-Proofpoint-ORIG-GUID: bWDxyvcgjJ7CtoxEdJEYSH4pG9-8F4SV X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: FZmgIYZUYPy8kOVLKZsNNnOQx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634516; bh=hmb7jvZCFDKyqYGfX1neTZYUX8x5i5M0bf79KOeShJU=; h=Cc:Date:From:Reply-To:Subject:To; b=KL0GAX+MvE+ObZGztHJ4liTZaC8hOZq0w2EDP1vAZKMx/gbvYGLjKsNtkhZl/1qg0hP /mhRdehDarlteiFAVm+J3SlQ9cLdRP3DkhOzrZGplGJ2hxoKvaP7+eQVtp7sPZxq+hiH1 1juvUk0DaG20RqU0soCINKTxaZ8aL1oNkoQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634518253100002 Content-Type: text/plain; charset="utf-8" Remove Null instance of OpensbilatformLibNull, OpensbilatformLib is the generic one for RsicVPlatformPkg. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 +- .../OpensbiPlatformLibNull.inf | 38 -------------- .../Library/OpensbiPlatformLibNull/Platform.c | 51 ------------------- 3 files changed, 1 insertion(+), 90 deletions(-) delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibN= ull/OpensbiPlatformLibNull.inf delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibN= ull/Platform.c diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index ec8875be14..93b3cd8de9 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -77,7 +77,7 @@ PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf =20 [Components.common] - Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatfo= rmLibNull.inf + Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLi= b.inf Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMe= moryTestLibNull.inf Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootM= anagerLib.inf Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/Platfo= rmUpdateProgressLibNull.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Ope= nsbiPlatformLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatfo= rmLibNull/OpensbiPlatformLibNull.inf deleted file mode 100644 index 125a1220bc..0000000000 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPla= tformLibNull.inf +++ /dev/null @@ -1,38 +0,0 @@ -## @file -# RISC-V OpenSbi Platform NULL Library -# -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001b - BASE_NAME =3D RiscVOpensbiPlatformLibNull - FILE_GUID =3D 9424ED54-EBDA-4FB5-8FF6-8291B07BB151 - MODULE_TYPE =3D SEC - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D RiscVOpensbiPlatformLib - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D RISCV64 -# - -[Sources] - Platform.c - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - DebugAgentLib - - diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Pla= tform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platfo= rm.c deleted file mode 100644 index b7e39d19c1..0000000000 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * - * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
- * - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Atish Patra - */ - -#include -#include - -const struct sbi_platform_operations platform_ops =3D { - .early_init =3D NULL, - .final_init =3D NULL, - .early_exit =3D NULL, - .final_exit =3D NULL, - .domains_root_regions =3D NULL, - .domains_init =3D NULL, - .console_putc =3D NULL, - .console_getc =3D NULL, - .console_init =3D NULL, - .irqchip_init =3D NULL, - .irqchip_exit =3D NULL, - .ipi_send =3D NULL, - .ipi_clear =3D NULL, - .ipi_init =3D NULL, - .ipi_exit =3D NULL, - .get_tlbr_flush_limit =3D NULL, - .timer_value =3D NULL, - .timer_event_stop =3D NULL, - .timer_event_start =3D NULL, - .timer_init =3D NULL, - .timer_exit =3D NULL, - .system_reset_check =3D NULL, - .system_reset =3D NULL, -}; - -struct sbi_platform platform =3D { - .opensbi_version =3D OPENSBI_VERSION, - .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01), - .name =3D "NULL Platform", - .features =3D 0, - .hart_count =3D 0, - .hart_index2id =3D 0, - .hart_stack_size =3D 0, - .platform_ops_addr =3D 0, -}; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82325): https://edk2.groups.io/g/devel/message/82325 Mute This Topic: https://groups.io/mt/86435677/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82327+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82327+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634519; cv=none; d=zohomail.com; s=zohoarc; b=ThhZhIv9VawqvSM3C3/a55gDOkzxSQNB3TVE0TmnRJ+P2HP7tiZHNy7+1U3kVtDfaVB+IGBdZShtK7GMwMZAiFkIcQA4JVbmDN64BN9YZZYyeFd5+Ad9iWfmWbchzzWPSVxCpCsb7/lxe4O4sNto/NPUvHIh4ZsFq64UHQ/8uvs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634519; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6yOwe11AgCt4SNrvNejX0YfHFnJ9mNS45S/Jd/mVW9k=; b=GTIffBqm/x4klmeUji08xxEh0KvF4lbrAj6qv/Yu19Wn6u9DwF9K8toVrWM9tYrMs+J0oVyG3nSFW+TrFu7deAwm8uiEAkyqwX9LIg2JByFx1wN4lQVibfHrBS0/IChW7oXABEyNxhgtWxEM0EW1kIooCMfLusE8usOJkczTH/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82327+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634519250170.01564838694298; Tue, 19 Oct 2021 02:08:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GlWhYY1788612x7ETJfxk96e; Tue, 19 Oct 2021 02:08:38 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.7154.1634634514249341246 for ; Tue, 19 Oct 2021 02:08:38 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J41xF6026456; Tue, 19 Oct 2021 09:08:32 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bs9u4ygub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:32 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id BCCD75C; Tue, 19 Oct 2021 09:08:31 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id AF69451; Tue, 19 Oct 2021 09:08:30 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Date: Tue, 19 Oct 2021 16:09:51 +0800 Message-Id: <20211019081007.31165-15-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7VzD1J5C09Bxuv06ZbWq9k8Gt6xBN_UU X-Proofpoint-GUID: 7VzD1J5C09Bxuv06ZbWq9k8Gt6xBN_UU X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: sNjXbZAECaQAqTep0ezrFPggx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634518; bh=ftS4foHFEd/nnjdQo8HIiUfFIeNXW0WCsUoF4q7BM2M=; h=Cc:Date:From:Reply-To:Subject:To; b=VNHBTeAiCNcWyyXO/72A9GydQ31A9xlFyzY3qv5xHUoXr3PocNKgBUivG/1OtIPZrRy SGKIugymiwU8XXZtE/CJlPCAuxgGHkMkAmJkaxDmEWenM96uf2I1Hj34ehhySzE2ZQETg LYUQqZ1ubXoIrxEOs3ohuxyTVp+awjOSZ1c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634520528100013 Content-Type: text/plain; charset="utf-8" Initial hart index to Id array by invoking OpenSBI fw_platform_init function. Introduce PcdBootableHartIndexToId PCD which could be used to overwrite the hart_index2Id arrary built from Devie tree according to platform demand. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 13 +++- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 3 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 2 + .../PlatformPkg/Universal/Sec/SecMain.c | 62 ++++++++++++++++--- .../Universal/Sec/Riscv64/SecEntry.S | 29 ++++++++- 5 files changed, 96 insertions(+), 13 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 7e41e7bdb2..947ae40e20 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -55,10 +55,21 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083 gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084 # -# The bootable hart core number, which is incorporate with OpenSBI platfor= m hart_index2id value. +# The bootable hart core number, which incorporates with OpenSBI platform = hart_index2id value. +# PcdBootableHartNumber =3D 0 means the number of bootable hart comes from= Device Tree. +# Otherwise the number assigned in PcdBootableHartNumber overwrite it. # gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01085 # +# PcdBootableHartIndexToId is valid if PcdBootableHartNumber !=3D 0. +# If PcdBootableHartNumber !=3D 0, then PcdBootableHartIndexToId is an arr= ay of +# bootable hart ID. +# For example, +# if PcdBootableHartNumber =3D=3D 3 then PcdBootableHartIndexToId could be= defined +# as {0x1, 0x2, 0x3}. +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId|NULL|VOID*|= 0x00001086 +# # Definitions for OpenSbi # gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001100 diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 93b3cd8de9..97d5dd08a0 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -39,7 +39,8 @@ !include MdePkg/MdeLibs.dsc.inc =20 [LibraryClasses.common] - RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatf= ormLibNull/OpensbiPlatformLibNull.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatf= ormLib/OpensbiPlatformLib.inf RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 9736277fa1..1cfbef961f 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -41,6 +41,7 @@ DebugAgentLib DebugLib ExtractGuidedSectionLib + FdtLib IoLib PcdLib PeCoffLib @@ -62,6 +63,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index fb0adbca54..51d9edfe75 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -615,16 +615,17 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection; =20 if (FixedPcdGet32 (PcdDeviceTreeAddress)) { + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess.\n")); return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddres= s)); } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) { + DEBUG ((DEBUG_INFO, "Use DBT FV\n")); Status =3D FindFfsFileAndSection ( (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbF= vBase), EFI_FV_FILETYPE_FREEFORM, EFI_SECTION_RAW, &FoundSection - ); + ); if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n= ")); return NULL; } FoundSection ++; @@ -635,6 +636,35 @@ GetDeviceTreeAddress ( } return NULL; } +/** + Overwrite hart_index2id array if platform would like to use the + bootable harts other than those declared in Device Tree + + @param[in] SbiPlatform Pointer to SBI platform + @retval hart_index2id Index to ID value may be overwrote. + @retval hart_count Index to ID value may be overwrote. + +**/ +VOID +Edk2PlatformHartIndex2Id ( + IN struct sbi_platform *SbiPlatform + ) +{ + UINT32 Index; + UINT32 *HartIndexToId; + UINT32 BootableHartCount; + UINT8 *PlatformHartIndex2IdArray; + + BootableHartCount =3D FixedPcdGet32(PcdBootableHartNumber); + if (BootableHartCount !=3D 0) { + HartIndexToId =3D (UINT32 *)SbiPlatform->hart_index2id; + PlatformHartIndex2IdArray =3D (UINT8 *)FixedPcdGetPtr (PcdBootableHart= IndexToId); + for (Index =3D 0; Index < BootableHartCount; Index++) { + *(HartIndexToId + Index) =3D (UINT32)(*(PlatformHartIndex2IdArray + = Index)); + } + SbiPlatform->hart_count =3D BootableHartCount; + } +} =20 /** This function initilizes hart specific information and SBI. @@ -671,17 +701,13 @@ VOID EFIAPI SecCoreStartUpWithStack( IN struct sbi_scratch *Scratch ) { + UINT32 HardIndex; UINT64 BootHartDoneSbiInit; UINT64 NonBootHartMessageLockValue; struct sbi_platform *ThisSbiPlatform; EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext; =20 - Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); - if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); - ASSERT (FALSE); - } - DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1)); + DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", Har= tId)); =20 // // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart. @@ -705,6 +731,18 @@ VOID EFIAPI SecCoreStartUpWithStack( ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; =20 if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { + + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); + ASSERT (FALSE); + } + + DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count= )); + DEBUG ((DEBUG_INFO, "HART index to HART ID:\n")); + for (HardIndex =3D 0; HardIndex < ThisSbiPlatform->hart_count; HardInd= ex ++) { + DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisS= biPlatform->hart_index2id [HardIndex])); + } LaunchPeiCore (HartId, Scratch); } =20 @@ -739,3 +777,11 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch); } =20 +void xxxx (char *debugstr, ...) +{ + VA_LIST Marker; + + VA_START (Marker, debugstr); + DebugVPrint (DEBUG_INFO, debugstr, Marker); + VA_END (Marker); +} diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 0a69c50065..dc410703e0 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -101,16 +101,35 @@ _scratch_init: /* Loop to next hart */ blt t1, s7, _scratch_init =20 - /* Fill-out temporary memory with 55aa*/ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + /* Get the address of device tree and call generic fw_platform_init */ + call GetDeviceTreeAddress /* a0 return the device tree address */ + beqz a0, skip_fw_init + add a1, a0, 0 /* a1 is device tree */ + csrr a0, CSR_MHARTID /* a0 is hart ID */ + call fw_platform_init +skip_fw_init: + + /* Zero out temporary memory */ li a4, FixedPcdGet32 (PcdTemporaryRamBase) li a5, FixedPcdGet32 (PcdTemporaryRamSize) add a5, a4, a5 1: - li a3, 0x5AA55AA55AA55AA5 + li a3, 0x0 sd a3, (a4) add a4, a4, __SIZEOF_POINTER__ blt a4, a5, 1b =20 + /* Overwrite hart_index2id array of + platform would like to use the bootable hart + other than it defined in Device Tree */ + la a0, platform + call Edk2PlatformHartIndex2Id + /* Update boot hart flag */ la a4, _boot_hart_done li a5, 1 @@ -136,6 +155,10 @@ _start_warm: csrw CSR_MIP, zero =20 li s7, FixedPcdGet32 (PcdBootableHartNumber) + bnez s7, 1f + la a4, platform + REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +1: li s8, FixedPcdGet32 (PcdOpenSbiStackSize) la a4, platform =20 @@ -205,7 +228,7 @@ _start_warm: /* Setup stack */ add sp, tp, zero =20 - /* Setup stack for the Hart executing EFI to top of temporary ram*/ + /* Setup stack for the boot hart executing EFI to top of temporary ram*/ csrr a6, CSR_MHARTID li a5, FixedPcdGet32 (PcdBootHartId) bne a6, a5, 1f --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82327): https://edk2.groups.io/g/devel/message/82327 Mute This Topic: https://groups.io/mt/86435679/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82324+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82324+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634516; cv=none; d=zohomail.com; s=zohoarc; b=ls2gN+CiSSBSmiUFWkqzD9+LpumF4C92RXsTzeHlcO+TSVe3LMHQBoekWaDPnFopgHjEI0riBKA3hRNeHS6/8naHt841l+NIWr+1Nm/+IQMZFbd38CwpPCrZBb4XybJyM/XqlSUewSv5CCWa6+H5Niq/MxmMbSAqY+GP343wLVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634516; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sgHKqMkQ3tO9qP6gXULW6109QN8BKQCabxDHRj1sxNQ=; b=DDOdyEa/z83pceZW3ElvybFufOgsSBYiKhtPehU7PCp7NRv5xeCy/p5wENW6rld3LPoVMVyZUSrn2QPOJ1UAg+2Abq5PmwTSJgzHH6TyPp2pMBVgaNifrIhdFCSu1EZS+jszlc8Szt7LqP4qwTF0pAz1LzoW4YGyDrAH6VxTy/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82324+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634516833935.0122766271668; Tue, 19 Oct 2021 02:08:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fRofYY1788612x8YNuMDkiHF; Tue, 19 Oct 2021 02:08:36 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.7279.1634634514755820028 for ; Tue, 19 Oct 2021 02:08:35 -0700 X-Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J91tms003260; Tue, 19 Oct 2021 09:08:34 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsu140275-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:33 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 2A1137B; Tue, 19 Oct 2021 09:08:33 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 1B40451; Tue, 19 Oct 2021 09:08:31 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Date: Tue, 19 Oct 2021 16:09:52 +0800 Message-Id: <20211019081007.31165-16-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: JubhAc_GS0cE6tx1NchLcKn9e5nExm_Y X-Proofpoint-ORIG-GUID: JubhAc_GS0cE6tx1NchLcKn9e5nExm_Y X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: FihQvZQ1gxUNNQoI5zRxQRjKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634516; bh=SrWluJgwy/+snakhnUg1Uxc4jtLE9XDdG1i3A/pt+Vw=; h=Cc:Date:From:Reply-To:Subject:To; b=qdgOPAwDz1BzcdSxeq6fJhfBBl8dfXH0b/xw8ZOI1ejfpx7pDuBzYe2gGqlXRphbjDH RdnV5YpMRu3OcEU9QoAsy0OUicZbFYmqCGK0CG8YV6cj0MKzcNQ0XHknUKTJ42/T0b1/Z UP5tJjNc5q5+M4/9XFUo2fh8mxZ3pqvX0UM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634518298100003 Content-Type: text/plain; charset="utf-8" Remove platform code from generic OpensbiPlatfomLib. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../Library/OpensbiPlatformLib/Platform.c | 25 ++++++------------- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index 06cd1a299f..b477b81d74 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -270,24 +270,13 @@ const struct sbi_platform_operations platform_ops =3D= { .timer_exit =3D fdt_timer_exit, }; =20 -#if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4 -#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber) -static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] =3D {1, 2, 3, 4}; -#endif - struct sbi_platform platform =3D { - .opensbi_version =3D OPENSBI_VERSION, - .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01), - .name =3D "Generic", - .features =3D SBI_PLATFORM_DEFAULT_FEATURES, - .hart_count =3D SBI_HARTMASK_MAX_BITS, -// TODO: Workaround for U540. Not sure why we need this. OpenSBI doesn't n= eed it. -#if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4 - .hart_index2id =3D U540_hart_index2id, -#else - .hart_index2id =3D generic_hart_index2id, -#endif - // TODO: Any reason why it shouldn't just be SBI_PLATFORM_DEFAULT_HART_S= TACK_SIZE? - .hart_stack_size =3D FixedPcdGet32(PcdOpenSbiStackSize), + .opensbi_version =3D OPENSBI_VERSION, + .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01), + .name =3D "Generic", + .features =3D SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count =3D SBI_HARTMASK_MAX_BITS, + .hart_index2id =3D generic_hart_index2id, + .hart_stack_size =3D FixedPcdGet32(PcdOpenSbiStackSize), // The stack= given by SEC for each hart .platform_ops_addr =3D (unsigned long)&platform_ops }; --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82324): https://edk2.groups.io/g/devel/message/82324 Mute This Topic: https://groups.io/mt/86435676/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82328+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82328+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634520; cv=none; d=zohomail.com; s=zohoarc; b=cCrPNoP6jq8ouJB91RllVcNyacchO2GZPZgiW/0wFplaTwoOh86kR/7A/CY4JQBcWhXozt8pEw7qx12Er0YOc+LqifykrjQ8H/55On53Vq/6XFQKXSNG+1ZWKeRpMvvc1Ts5MSDiwvBiP6R7C4honHIOsWJkvM/yfUmYURV0nQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634520; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MjibJUCsbSrkcSL6C+P/kPPTxnm0EJXJoirqzjuuluI=; b=Ey7602vbzIHN0cwK/byxLrFVvrXaon3iZJ2Re4IaLTCcLvo4CnusYLFNUwWT+leaSmnvbmL4CulYZAk9ZiScSNGmXbiPXeWdPk/nbV3vW0w3GjsPsGP51CAUO3V8iwfH9X0sD3zeeRO1GIocGK0EOhREJZWJIKvv0ULKsRaveII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82328+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634520384981.2878265875797; Tue, 19 Oct 2021 02:08:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DOMNYY1788612xXyvG9jyuii; Tue, 19 Oct 2021 02:08:40 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7331.1634634515581338470 for ; Tue, 19 Oct 2021 02:08:39 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8CJbW021113; Tue, 19 Oct 2021 09:08:35 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 3bsta50ej3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:35 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 8D34655; Tue, 19 Oct 2021 09:08:34 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 7BDEB4C; Tue, 19 Oct 2021 09:08:33 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540 Date: Tue, 19 Oct 2021 16:09:53 +0800 Message-Id: <20211019081007.31165-17-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: H-fjGeoM-V87mcH1PBGRJ9xiQYc2dz22 X-Proofpoint-ORIG-GUID: H-fjGeoM-V87mcH1PBGRJ9xiQYc2dz22 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: qPS7a2HL7LUxG87ACFmPJ7vkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634520; bh=Pg1o/2mmdGOd7r1YJO52MiCShf8Ce4wrCQVLLzqzLf0=; h=Cc:Date:From:Reply-To:Subject:To; b=XjHepOGi5JqUCqtyc+QLqobedKRp/AgRpyD3LrmzXh16crA+dVzGVwGGCKqakgPneNX bDfqbezOwX8ICMyxKJ2Pez587hBa+amy6UunU9H62xwZFRwdmm07GsXCUVyrDj8wFhs69 AM6xwhYFaJXWpPRmmFbTivn2MYBvdtPaa5Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634520645100016 Content-Type: text/plain; charset="utf-8" Only use four harts on U540 reference code. This overwrites the bootable harts declared in Device Tree. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index f708f4d8be..1a525dc874 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -92,9 +92,16 @@ SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFreq= uencyInHerz =3D 1000000 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock =3D= 1000000000 # 1GHz system clock SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D= 5 # Total cores on U540 platform SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D= 1 # Boot hart ID -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber =3D= 4 # The bootable hart core number. - = # Which is incorporate with OpenSBI - = # platform hart_index2id value. + +# +# The bootable hart number the platform would like to use during boot. +# +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber =3D= 4 +# +# Only use hart ID 1, 2, 3, 4 +# +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId =3D= {0x1,0x2,0x3,0x4} + = # during boot SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores =3D= 4 # Total U5 cores enabled on U540 platform SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported =3D= True # E51 MC exists. SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase =3D= 0x10010000 # Serial port base address --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82328): https://edk2.groups.io/g/devel/message/82328 Mute This Topic: https://groups.io/mt/86435680/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82334+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82334+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634528; cv=none; d=zohomail.com; s=zohoarc; b=jo4DH/bedQtb3DMQDI/Lugajdud7XyC7e4lo3hKQcn7bdM/J/vLYa6BRi6UkjblS9bJTj05IZlE9GPMYqNDFO01/rt3IknioPtS1njiuvui67iTs+uCT5xSY6UjECiqleD7fKnAgjuJl255WIJ80kKzZaxt7O8pF3RomS8J0qcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634528; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=EjNedy4NtqU7zCvhLj+ej8gLWh2CHioiYeX0a1RMQAQ=; b=Mym8zys73cHPGcWvH/nf8JC5lfkNYL51CubXkJ8u5k5qjcE0FFzS/Ny3FY4EThFPOehTse3/lCY7fJJwU6bcwX/cpfoEjZk1Q6BswmqZz71jyixq/hCMaDxmeLfLHvhxagECqkFJZ9i2psnkrOilxuaMXhvkp/7PCbrf+h70+14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82334+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 163463452890181.9334563011846; Tue, 19 Oct 2021 02:08:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id b9MLYY1788612xx0ksbgXKKt; Tue, 19 Oct 2021 02:08:48 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.7403.1634634518565854858 for ; Tue, 19 Oct 2021 02:08:47 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J6Vv8M018227; Tue, 19 Oct 2021 09:08:36 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bs9u4ygup-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:36 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 0279A63; Tue, 19 Oct 2021 09:08:36 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id DEE0D4D; Tue, 19 Oct 2021 09:08:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check Date: Tue, 19 Oct 2021 16:09:54 +0800 Message-Id: <20211019081007.31165-18-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: bifApod_trVYmnFYAiwxL6q0zOl6nseK X-Proofpoint-GUID: bifApod_trVYmnFYAiwxL6q0zOl6nseK X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: qUwDgBpLD9gBCFSimFuO6FyDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634528; bh=t2KvOLYXPcDYSxxLeRK6NQGzyhkeNQzReyL5BW6tri4=; h=Cc:Date:From:Reply-To:Subject:To; b=FgvLZ0X2BDTxWeS8znjKekIfLi8rGnZMlRKW76JnKUwFv97zGQ1u54+Z93JKC9Fd8Ge LqPQIoHRkVE+qZS86GTjuAz2MnOKNxi/3Zcu293m1F0fj9WLXP6ryTF0wiPpeJ9Iax1dm EDImh3D4OHTkFCFxJ2I4dyFF0ZSRGgvQxJA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634529476100002 Content-Type: text/plain; charset="utf-8" Remove hart count check because the bootable hart count may be varied according to the harts declared in Device tree and PcdBootableHartNumber PCD. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfo= Hob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c index bc1b252946..c147028add 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c +++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -75,14 +75,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob ( } DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U5 platform\n", = HartIdNumber - (UINT32)MCSupport)); =20 - if (HartIdNumber !=3D FixedPcdGet32 (PcdHartCount)) { - DEBUG ((DEBUG_ERROR, "Improper core settings...\n")); - DEBUG ((DEBUG_ERROR, " PcdHartCount\n")); - DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n")); - DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n")); - ASSERT (FALSE); - } - return Status; + return EFI_SUCCESS; } =20 /** --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82334): https://edk2.groups.io/g/devel/message/82334 Mute This Topic: https://groups.io/mt/86435687/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82329+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82329+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634520; cv=none; d=zohomail.com; s=zohoarc; b=CsbEIOh9DuC+6sfKRvOv5/lSXvZM1g9gU3zoSCtDHPgVdh2lYYmIMBXIivLKd8JgDft7xhV+jwnsih7eisSO50TqYlwt/iI0AgKR9qgv6uCI/y7ERwzAAXWZz8j/J2GEc/vi44Fal8TpO0bUK/hIQ/1FpTzKIRNbAWtSKn1Vymg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634520; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1lOBweYr0xYwvbSFrRXa1VPhIHdkhm8K6y1KkNetsIY=; b=kp493tvSKsn5HrJsLrfPKBgcmYwOkSM05LV4xsuWoU2/VOhkBqifcrpCO5+Y7LQPxggJYY2f97VuPu74RBVVyBGBLbFq5JbM/+aCIir5dC+my0IEh3AHW4eodIklnv7Q3LFsBigDwiQ6g2xqIjCzuD7FVx1eulh5FOZFoNaI4eE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82329+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634520800463.0833704402929; Tue, 19 Oct 2021 02:08:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jiJKYY1788612xAPhs4j1F7X; Tue, 19 Oct 2021 02:08:40 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.7333.1634634518984126627 for ; Tue, 19 Oct 2021 02:08:39 -0700 X-Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19IN1wQW011104; Tue, 19 Oct 2021 09:08:38 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsb1x6vxc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:38 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 6378166; Tue, 19 Oct 2021 09:08:37 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 543AA4F; Tue, 19 Oct 2021 09:08:36 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Date: Tue, 19 Oct 2021 16:09:55 +0800 Message-Id: <20211019081007.31165-19-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: XDH3qWSyv3YMuLI0Zpk5jj7nTtqRlO1x X-Proofpoint-ORIG-GUID: XDH3qWSyv3YMuLI0Zpk5jj7nTtqRlO1x X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: YTCEd5lW9Djtyqmx3uE59F51x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634520; bh=JLXMDXGx9TGBQ3phpkMMa2Vrv9YufxHPm3Xo8GEEcKI=; h=Cc:Date:From:Reply-To:Subject:To; b=D6uQkmKsjyoNt+O+tNjw8TyI8Jmu2FL54R6E5Qa734q2107SngIzj3UR59TPUeFxcKI BTr+oUMzgwx06wHJ9dTp373mqyH9qhBH4zs2aKSzhV/FEJAbpKmzITA/Ll4+jzIEibatw 1yjir+UTZoS0f1DHSbkAj1MOocyCe4LTwTQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634522670100022 Content-Type: text/plain; charset="utf-8" Rename RiscVSpecialPlatformLib to RiscVSpecialPlatformLibNull because this is the NULL instance for RiscVPlatformPkg. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 ++-- .../RiscVSpecialPlatformLibNull.inf} | 0 .../RiscVSpecialPlatformLib.c | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib/RiscVS= pecialPlatformLib.inf =3D> RiscVSpecialPlatformLibNull/RiscVSpecialPlatform= LibNull.inf} (100%) rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib =3D> R= iscVSpecialPlatformLibNull}/RiscVSpecialPlatformLib.c (76%) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 97d5dd08a0..bbb043f9ed 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -72,7 +72,7 @@ =20 [LibraryClasses.common.SEC] ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf - RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecial= PlatformLib/RiscVSpecialPlatformLib.inf + RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecial= PlatformLibNull/RiscVSpecialPlatformLibNull.inf =20 [LibraryClasses.common.DXE_DRIVER] PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf @@ -86,7 +86,7 @@ Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R= iscVPlatformTempMemoryInitLibNull.inf Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpi= LibNull.inf - Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecial= PlatformLib.inf + Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpe= cialPlatformLibNull.inf =20 [Components.common.SEC] Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ri= scVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecia= lPlatformLibNull/RiscVSpecialPlatformLibNull.inf similarity index 100% rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ris= cVSpecialPlatformLib.inf rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/R= iscVSpecialPlatformLibNull.inf diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ri= scVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialP= latformLibNull/RiscVSpecialPlatformLib.c similarity index 76% rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/Ris= cVSpecialPlatformLib.c rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/R= iscVSpecialPlatformLib.c index 3a77ff6b17..18c152001c 100644 --- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpec= ialPlatformLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscV= SpecialPlatformLib.c @@ -14,6 +14,7 @@ // #include =20 -const struct platform_override *SpecialPlatformArray =3D NULL; +const struct platform_override *special_platforms =3D NULL; +const struct platform_override *SpecialPlatformArray =3D NULL; INTN NumberOfPlaformsInArray; =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82329): https://edk2.groups.io/g/devel/message/82329 Mute This Topic: https://groups.io/mt/86435681/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82330+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82330+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634521; cv=none; d=zohomail.com; s=zohoarc; b=nvH3+s3Pd/o7xFwU6p7qXB4mW32yIVJv79s84cn6mS9xiFtNLDsOHvfJU7bbOrhVJj7KkRhbBEf/1dDWbUfdvkHYuqLI03XWMsSlrJiLpTfgrNZP67YE6KHyDXIG/8HfN0HAlNRYWEndjoRZKBdsd5DF3gevTgIuERe8FTanabk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634521; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8ILqsi6aYc1/caglEjn+b+5zaRWOnIUQyaRXDGV1IUc=; b=m7Mfh9LkbKZPxiTndd4KKCQn5MxDfQkwjZ77qmtz3iUT5a0o5ZIZeEXiD6Bj6BAn6C5i1h+lmZu/dXJ0pnjevw1qMiXU449pbiV80G5IPCQoICGoVzIENp7eTvYSn7VfVTtUSlzMdVEl+d/Of9Q6Xl8zTj/82zf84gPrC1cLwww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82330+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634521215374.87687837822875; Tue, 19 Oct 2021 02:08:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RQz6YY1788612xzZi1bKYt11; Tue, 19 Oct 2021 02:08:40 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.7155.1634634520091604128 for ; Tue, 19 Oct 2021 02:08:40 -0700 X-Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J7W94C023173; Tue, 19 Oct 2021 09:08:39 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsbpkeht2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:39 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id CBF734E; Tue, 19 Oct 2021 09:08:38 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id B51D74C; Tue, 19 Oct 2021 09:08:37 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib Date: Tue, 19 Oct 2021 16:09:56 +0800 Message-Id: <20211019081007.31165-20-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: k3lrOiSr8qGpy68DUni50RvGjf-yASpS X-Proofpoint-ORIG-GUID: k3lrOiSr8qGpy68DUni50RvGjf-yASpS X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: FXe4WQKdqLhXYGi2QNJRWv3kx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634520; bh=EyNnsnbr4wnatDvPFZyz0PMqM+azOMZ0q/PfGM7Ok8k=; h=Cc:Date:From:Reply-To:Subject:To; b=ih3Qz8ddIcernPEYGihAAgTptuJcsCTeQ53Wz0Yu4iYZBGx+UovEQCU8AULClAq/4/f eOYOOBCqZDLdlI9cUm+JCT4829YPGEV7th4j4dN9GGcCjhuu/Tam7vvg8c+0HRqgvac74 tz9aUIkdlW1DYc9yb4Zi+H34NPr7D8jxiSU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634522823100026 Content-Type: text/plain; charset="utf-8" Add SortLib to run ram disk. Need to override generic library. Cc: Daniel Schaefer Cc: Sunil V L Signed-off-by: Daniel Schaefer Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 71dbca0e96..4d16adfc82 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -532,6 +532,9 @@ OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf } =20 ShellPkg/Application/Shell/Shell.inf { --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82330): https://edk2.groups.io/g/devel/message/82330 Mute This Topic: https://groups.io/mt/86435682/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82333+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82333+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634525; cv=none; d=zohomail.com; s=zohoarc; b=M39lCU5Vs9D06xX0xGC0FhB0H4dp6lPmNGg1mCMP+YDy+XKTAWTyvJoyLQlcchYKT4o1bGLiL5JJN6ToRu4r9/WGqkJa7hYJm0Vdfdcq2fP1ApWVIgpzuQ2ZplXWu4L9pjXD6AlxKDA5n1S6LVNRXawtLmkVe0LyZPyxWi+N74s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634525; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=2jZOZltyiZdHy+WHPqV0M7sKpRCFWknEEuMlSFFvTYI=; b=ImAhwQhSdqrBO/HUezMzb1bzaWBXR+QZ0Cr+XeWY+ab479arAKiPFvN9Fn30StGwItTyg27j4z8kY8W/6f7H+kSiPdf0PgI+cGfLhuhzVFBvS79dfHw2Hc6Tnmd1WZH7vmrKpFnmykq5yYwSB6lZyQTb5tit0vcQE/hX922c1HM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82333+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634525824961.5538125702337; Tue, 19 Oct 2021 02:08:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id uFFzYY1788612xEDxXfR268O; Tue, 19 Oct 2021 02:08:45 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7308.1634634521452487849 for ; Tue, 19 Oct 2021 02:08:44 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8W5MY018505; Tue, 19 Oct 2021 09:08:41 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 3bseymmq08-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:41 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 42CA34F; Tue, 19 Oct 2021 09:08:40 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 2A1EF4D; Tue, 19 Oct 2021 09:08:38 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library Date: Tue, 19 Oct 2021 16:09:57 +0800 Message-Id: <20211019081007.31165-21-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: -RKfCTknsMZ_Vzx6HfPxNYs0ca6bt-_2 X-Proofpoint-GUID: -RKfCTknsMZ_Vzx6HfPxNYs0ca6bt-_2 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: aSIJaLYs0IYTgAg56Nx6PTFXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634525; bh=4+O4qw1gJeqowZdSKsHsf3And8Ju0YRcqEXp4E+4khM=; h=Cc:Date:From:Reply-To:Subject:To; b=cLA/kFA+6aONw/oOa14oOlo9ydauv7hm3Suv51AtrlNzc9ZbxFq4hXB2BxXc8vTS4PL aFBLt2aM4PagQ+KJ2Xd6wIC5lbrTuepP41LaH//5smNvvpEMa1C6gLSwQzBkhcfXyf1l7 vHclL5g1EALenXKM4jYWLXRYjKf585DQCn0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634527150100001 Content-Type: text/plain; charset="utf-8" Update opensbi library to a731c7e36988c3308e1978ecde491f2f6182d490, which is based on v0.9. Cc: Daniel Schaefer Cc: Sunil V L Signed-off-by: Daniel Schaefer Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/= Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi index 937caee083..a731c7e369 160000 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi @@ -1 +1 @@ -Subproject commit 937caee0833115f69d697ca190001ba0aa5c7368 +Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82333): https://edk2.groups.io/g/devel/message/82333 Mute This Topic: https://groups.io/mt/86435686/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82332+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82332+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634526; cv=none; d=zohomail.com; s=zohoarc; b=erzo1YtdhKC2ZcKLC7Xt3HlaW/Mjx6JklR22PGsf1vl/EKVhdLe6YPF5OKdLbu/jcZjWtnqb0B6nlNWcj/UO9zoZsOudV6jCCc5WcRFcFj/KowOGyjq7dYR9Kx3Ohdf+LqZwvrVRd87cHg6J8I5eK0dyFpHG+KtaHwPGHAhFEdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634526; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=O0ZWdXfAcBTXCIcMJk6c51Nh6QzJ3uiQK00hoveqDHQ=; b=NK0sMmsi2sER2Tn1pJwfLPtGsTMd+jfve4uggMSb438zVKJWUbyJ/H7tP3tOfqtjko0UYibikJAuT2K7W+W/maToYv5j6ssueXbgOwx0kOoLVxABk9E8dDfq052eNvVcUoVAnfhK+T/rY2FJUeGkZj9W2bEI0CJG/fEIEe7e2uE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82332+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634526205240.7211068258996; Tue, 19 Oct 2021 02:08:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id u3mKYY1788612xtdQffzX5YZ; Tue, 19 Oct 2021 02:08:45 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7310.1634634523022490278 for ; Tue, 19 Oct 2021 02:08:44 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19ILhNO1008060; Tue, 19 Oct 2021 09:08:42 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qryg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:42 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id A41264F; Tue, 19 Oct 2021 09:08:41 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 9470D48; Tue, 19 Oct 2021 09:08:40 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart Date: Tue, 19 Oct 2021 16:09:58 +0800 Message-Id: <20211019081007.31165-22-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: elPg4Nonfmk7uXOWBGUrulK0ksiXWKId X-Proofpoint-ORIG-GUID: elPg4Nonfmk7uXOWBGUrulK0ksiXWKId X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: sDLMZTSWkwXjrnvA4lScAF9Tx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634525; bh=upkc3ujYq2xDQpoJ73W0bxNzgbIaEKgi75K92WF8VJg=; h=Cc:Date:From:Reply-To:Subject:To; b=paI42oat3rhwqMA+uX3CjnSUr95usC13bThzWHIL/20ZCyxIToIBfVAZp8nOX1L6nsG 3IxPENf6mwAs8CB+mZ0GP40elWi0jSumOCkTl1zElvBMH9v8Myqgq9rkZIYAlDRxrEYBh DY/cpVJPZWhaOwDDamJLCYj0HwadUnSfyBQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634527193100004 Content-Type: text/plain; charset="utf-8" Check Coldboot or Warmboot hart in SEC OpenSBI platform function. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 51d9edfe75..9b162fb3b6 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -398,6 +398,13 @@ SecPostOpenSbiPlatformEarlylInit( IN BOOLEAN ColdBoot ) { + UINT32 HartId; + + if (!ColdBoot) { + HartId =3D current_hartid(); + DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); + return 0; + } // // Boot HART is already in the process of OpenSBI initialization. // We can let other HART to keep booting. @@ -423,6 +430,12 @@ SecPostOpenSbiPlatformFinalInit ( struct sbi_platform *SbiPlatform; EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; =20 + if (!ColdBoot) { + HartId =3D current_hartid(); + DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); + return 0; + } + DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUN= CTION__)); =20 SbiScratch =3D sbi_scratch_thishart_ptr(); @@ -777,7 +790,7 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch); } =20 -void xxxx (char *debugstr, ...) +void OpensbiDebugPrint (char *debugstr, ...) { VA_LIST Marker; =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82332): https://edk2.groups.io/g/devel/message/82332 Mute This Topic: https://groups.io/mt/86435685/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82340+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82340+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634534; cv=none; d=zohomail.com; s=zohoarc; b=UXpu8exEiYqCSuyDuv3BpJUAhzlWWowWL8/lkonlOMzlG6pI1aJtETD9oCnwCGw+NSp9wPfsuS0bY8rSbkBY9PqcB6VYroT29jlF0+pRYc5Oe2GSLT9AN3e2qlilRe3DRHdrIWjkVHzWEPplbXJ2dtofr0iUpssd01wGH+fBvzc= ARC-Message-Signature: i=1; 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Tue, 19 Oct 2021 02:08:53 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8CFAF020969; Tue, 19 Oct 2021 09:08:43 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 3bsta50ekr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:43 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 1067455; Tue, 19 Oct 2021 09:08:43 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 01D0A4B; Tue, 19 Oct 2021 09:08:41 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Date: Tue, 19 Oct 2021 16:09:59 +0800 Message-Id: <20211019081007.31165-23-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: 1R0rKjcdjI_EUuVxwSePhYixzDie2WIb X-Proofpoint-ORIG-GUID: 1R0rKjcdjI_EUuVxwSePhYixzDie2WIb X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: gTkE2UpzOj8VDssdkb16k2Ppx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634534; bh=40RGYEtHXwJYOf2GU5tCBB9k0OnVl74kJFv528sZBGs=; h=Cc:Date:From:Reply-To:Subject:To; b=fG8TsI7DRCJprNYZZsHPzAmvtJdaf62Ln61mqWIOLKGcLHq1PgUFYH0l7mRX4mtMJwN 5VrKugKwZ9+JoAySeCt/EYC9JbPKk3SaNvO/fOzhXT75LYO3g7FHHLD3TDbIWwYE1P3O+ w/7pbCjfQh0ifd38Bs1UH1bOxR6UJg2U0KM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634536070100009 Content-Type: text/plain; charset="utf-8" Add more comments to SecMain.c Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 9b162fb3b6..93ff8a598d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -628,7 +628,10 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection; =20 if (FixedPcdGet32 (PcdDeviceTreeAddress)) { - DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess.\n")); + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress))); + // + // Device tree address is pointed by PcdDeviceTreeAddress. + // return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddres= s)); } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) { DEBUG ((DEBUG_INFO, "Use DBT FV\n")); @@ -720,7 +723,7 @@ VOID EFIAPI SecCoreStartUpWithStack( struct sbi_platform *ThisSbiPlatform; EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext; =20 - DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", Har= tId)); + //DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", H= artId)); =20 // // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart. @@ -750,7 +753,7 @@ VOID EFIAPI SecCoreStartUpWithStack( DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); ASSERT (FALSE); } - + DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1)); DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count= )); DEBUG ((DEBUG_INFO, "HART index to HART ID:\n")); for (HardIndex =3D 0; HardIndex < ThisSbiPlatform->hart_count; HardInd= ex ++) { --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82340): https://edk2.groups.io/g/devel/message/82340 Mute This Topic: https://groups.io/mt/86435695/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82335+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82335+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634530; cv=none; d=zohomail.com; s=zohoarc; b=QyHwY8YsNPY1Wv0+EyhV/o3pBBAdcSNaGVlhr0WlGkoN/Ay1ck8DBo/h/byvlgHld54w7x49CoYC6ZZlzVQ4ZE62gwHcAHplGyaAc/dzXpEWjl9d8vUPV9d4knsElSRgqUxWlDsX3CmtGsJvzOZaAtHX5skSIX0x1xI0Qcb3dxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634530; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zvaMO7HnI2sZLiZcUohWaKVGY7Sghaa1SSUR4RLbjXE=; b=Rc//BszhBzxY0J0DymH+8wSmUPt4WplPArresC4DqUMpIrVyVYFRBoxtAsXmd13Zlwvhvvb9h/TV19HjA+cd6RNORApO+2slyig6Knn0POd8B5wqugX81qlshzpN51o2GyORHbJq954fkP5IS7YJOjEz8/khtjEsWI//R/ohRxU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82335+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634530538274.52536750563456; Tue, 19 Oct 2021 02:08:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id D7auYY1788612xHV4rsAovOB; Tue, 19 Oct 2021 02:08:50 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7280.1634634525737042338 for ; Tue, 19 Oct 2021 02:08:49 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J91tM6017711; Tue, 19 Oct 2021 09:08:45 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qs05-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:45 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 7283462; Tue, 19 Oct 2021 09:08:44 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 62B274A; Tue, 19 Oct 2021 09:08:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances Date: Tue, 19 Oct 2021 16:10:00 +0800 Message-Id: <20211019081007.31165-24-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: CTrae0VZ-_E3GuevROCMwPLReHcC_qXA X-Proofpoint-ORIG-GUID: CTrae0VZ-_E3GuevROCMwPLReHcC_qXA X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 6Y3Ad1CkmHyQSPgrxwAga9kfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634530; bh=5jf7HUksUNBoA6q4R7ysWPwQ8nGaoGLMzfCeuHc0goI=; h=Cc:Date:From:Reply-To:Subject:To; b=NEpPLdeMhR7jj/UuE0//SosRbXj0UVHrlykBZU+xTkT9enN8TSFMTovbqjeQqUP1Pdt iTI2FSijRNPTF+o8giymcsQbOttpMxRBuXvtaP3WECn90G9halpR/bCiriNfBGSSZswzY LDdfVMf07yhZcGzAP1g90KMSZsrmTjmTEU4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634531604100001 Content-Type: text/plain; charset="utf-8" Create library instances of reading Machine mode timer. - MacineModeTimerLib is used to read mtime CSR through platfrom library. - EmulatedMacineModeTimerLib is used to read mtime CSR through shadow CSR. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 + .../EmulatedMachineModeTimerLib.inf | 34 +++++++++++++++++ .../MachineModeTimerLib.inf | 38 +++++++++++++++++++ .../Include/IndustryStandard/RiscV.h | 5 +++ .../Include/Library/RiscVCpuLib.h | 3 ++ .../EmulatedMachineModeTimerLib.S | 24 ++++++++++++ .../MachineModeTimerLib/MachineModeTimerLib.S | 25 ++++++++++++ 7 files changed, 131 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineMod= eTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineMod= eTimer/MachineModeTimerLib/MachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineMod= eTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineMod= eTimer/MachineModeTimerLib/MachineModeTimerLib.S diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 531319322c..3b5738957d 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -44,6 +44,8 @@ RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf + MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf + #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/Silicon/RISC-= V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLi= b/EmulatedMachineModeTimerLib.inf new file mode 100644 index 0000000000..369028a9a6 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Emulate= dMachineModeTimerLib/EmulatedMachineModeTimerLib.inf @@ -0,0 +1,34 @@ +## @file +# Library to read Machine Mode Timer. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D EmulatedMachineModeTimerLib + FILE_GUID =3D 81B82615-D85C-4377-8BFF-7442322E2835 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MachineModeTimerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + +[Sources.RISCV64] + EmulatedMachineModeTimerLib.S + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= MachineModeTimerLib/MachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/L= ibrary/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf new file mode 100644 index 0000000000..71d4315445 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Machine= ModeTimerLib/MachineModeTimerLib.inf @@ -0,0 +1,38 @@ +## @file +# Library to read Machine Mode Timer. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D MachineModeTimerLib + FILE_GUID =3D 6390D8AA-E0E6-4625-A515-9BB2DC7BBCAB + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MachineModeTimerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + +[Sources.RISCV64] + MachineModeTimerLib.S + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + RiscVCpuLib + RiscVPlatformTimerLib + + + diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index f6726bda24..c9715a2ee2 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -154,4 +154,9 @@ #define RISCV_CSR_MTOHOST 0x780 #define RISCV_CSR_MFROMHOST 0x781 =20 +// +// User mode CSR +// +#define RISCV_CSR_CYCLE 0xc00 +#define RISCV_CSR_TIME 0xc01 #endif diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index f70723567e..8d51152fa9 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -32,6 +32,9 @@ RiscVGetMachineTrapCause (VOID); UINT64 RiscVReadMachineTimer (VOID); =20 +UINT64 +RiscVReadMachineTimerInterface (VOID); + VOID RiscVSetMachineTimerCmp (UINT64); =20 diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/Silicon/RISC-V/= ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/= EmulatedMachineModeTimerLib.S new file mode 100644 index 0000000000..1acd0ab062 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Emulate= dMachineModeTimerLib/EmulatedMachineModeTimerLib.S @@ -0,0 +1,24 @@ +//------------------------------------------------------------------------= ------ +// +// Read Machine mode timer using shadow CSR. +// +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimerInterface) +// +// Read machine mode timer CSR through shadow CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimerInterface): + csrr a0, RISCV_CSR_TIME + ret diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= MachineModeTimerLib/MachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Lib= rary/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S new file mode 100644 index 0000000000..16f8bdd70a --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Machine= ModeTimerLib/MachineModeTimerLib.S @@ -0,0 +1,25 @@ +//------------------------------------------------------------------------= ------ +// +// Read mtimer through platform library. +// +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimerInterface) +// +// Read machine mode timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimerInterface): + call RiscVReadMachineTimer + ret + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82335): https://edk2.groups.io/g/devel/message/82335 Mute This Topic: https://groups.io/mt/86435688/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82341+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82341+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634539; cv=none; d=zohomail.com; s=zohoarc; b=KsZbDMul3KVU4wJWN8nArhima2w+X0WrVCMyI91a+81jwFzQMVPdbIe/7i3ys6ntAVP+OR0OzELhtPrFyFqw7Sstr8xq8PCWZbZ4DOk/6a40yHwJgTBATMtir+/YglEyTMZzt1kssniy9a5aK4hjfkDoYvOJzLsiPo+vWryKr/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634539; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KZcvZQEUq5QxnyWfyahOkkQlxubJZu7HaNgKd/ZrPCM=; b=JCfnGl1D9daSZJNAjyiBSJn9vjOGodE2W67/IoTqAPWaCVayOWYLFD5jE3AeyNT101M90wNHlMsJ6KxaIuiEUHzC/WjQzu/q6B4WPKWSrePpwuwOx0H/yYWmhxs621NLBu2Mx0riwbuUwU8mngmT+VPcExamh+5VYe2GHCrcB5U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82341+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634539231483.32709726083044; Tue, 19 Oct 2021 02:08:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jsE0YY1788612xH87kMsd04K; Tue, 19 Oct 2021 02:08:58 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7406.1634634526929114080 for ; Tue, 19 Oct 2021 02:08:57 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8Vt0E028635; Tue, 19 Oct 2021 09:08:46 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com with ESMTP id 3bst6drgsb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:46 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id D58636A; Tue, 19 Oct 2021 09:08:45 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id C4ED253; Tue, 19 Oct 2021 09:08:44 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library Date: Tue, 19 Oct 2021 16:10:01 +0800 Message-Id: <20211019081007.31165-25-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: SwWtQJdXZq0M_Oz5tpsgi2TmV5k5fNur X-Proofpoint-GUID: SwWtQJdXZq0M_Oz5tpsgi2TmV5k5fNur X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 2mwoJCnnYmhc1B3ynyckvnnxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634538; bh=FIbO0xrV0h+lrxmr6E7Lrr3lS8cycKpReqrAJOZSVEg=; h=Cc:Date:From:Reply-To:Subject:To; b=dAUawRqr+1Aep+2m5ws0E7KI/mN1SEyhWQ7AtUQgFKZ9ztljUmstVa7RgDg+xJhXwOV xZWdBSQvVrsFrg0kL2KgQxUwE21DN2VfByxsMohFjD0fhmQ+SFylcSv4Xhl+fbcqJgghq foL27CrAeid5WgPzvoMVTMTqqm/zLk4FEXk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634540297100002 Content-Type: text/plain; charset="utf-8" Use mtime CSR library interface to access mtime CSR. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 3 ++- Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 + .../ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 6 +++--- Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTim= erLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf index c914d3b4b6..3c61149da8 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.i= nf +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.i= nf @@ -30,5 +30,6 @@ BaseLib PcdLib RiscVCpuLib - RiscVPlatformTimerLib + MachineModeTimerLib + =20 diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Sili= con/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf index 29cc4413bd..a422c12e32 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf @@ -26,6 +26,7 @@ CpuLib CpuExceptionHandlerLib DebugLib + MachineModeTimerLib RiscVCpuLib TimerLib UefiBootServicesTableLib diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c index 97fe2aef4b..54ca99787e 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -36,9 +36,9 @@ InternalRiscVTimerDelay ( // // The target timer count is calculated here // - Ticks =3D RiscVReadMachineTimer () + Delay; + Ticks =3D RiscVReadMachineTimerInterface () + Delay; Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); - while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPA= RE_BITS - 1))) =3D=3D 0) { + while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TI= MER_COMPARE_BITS - 1))) =3D=3D 0) { CpuPause (); } } while (Times-- > 0); @@ -118,7 +118,7 @@ GetPerformanceCounter ( VOID ) { - return (UINT64)RiscVReadMachineTimer (); + return (UINT64)RiscVReadMachineTimerInterface (); } =20 /**return diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c index b8b8e91a6c..3104c6d2de 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c @@ -223,7 +223,7 @@ CpuGetTimerValue ( return EFI_INVALID_PARAMETER; } =20 - *TimerValue =3D (UINT64)RiscVReadMachineTimer (); + *TimerValue =3D (UINT64)RiscVReadMachineTimerInterface (); if (TimerPeriod !=3D NULL) { *TimerPeriod =3D DivU64x32 ( 1000000000000000u, --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82341): https://edk2.groups.io/g/devel/message/82341 Mute This Topic: https://groups.io/mt/86435698/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82336+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82336+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634531; cv=none; d=zohomail.com; s=zohoarc; b=n7cm/bAOoTMxOmY2Iae3Bfs43pc740eilsOXucqLVDU+e4iDaxmh70x1J8vhBYUaxM+ZWl023lTRBR6oDLWVoBFXh+gbHDp0uacC3GXTiNVHE2MqtxcdHU7u8P+zPqtQVePRt5AjOb22E5rqK7TWyBSLUerKbMOKs+lwOOEBYN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634531; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MnmKxIvk5wSSd64bVLKQ1PQK2/BayYFjGpOshqgiOtw=; b=hsKoZ6mf4Eot5Xgsl5aeG37o5cOIBd6MU62FKOthiw9wI9Z1ACoP8mHzdxMB+BAeGqXi1ovBRLGv/dHXIBrq5MiKaq63Q9KKj22czFgTfSVBFUlqZR/2S/8ocSzMbZ5KHXg98QrHYchBCyz9vBDovKOFc1HSdckryHCAXZzhu9U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82336+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634531028656.8217542467396; Tue, 19 Oct 2021 02:08:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5mbxYY1788612xApYwFsViJJ; Tue, 19 Oct 2021 02:08:50 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7281.1634634528484674495 for ; Tue, 19 Oct 2021 02:08:49 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J81swW005268; Tue, 19 Oct 2021 09:08:48 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qs0g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:48 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 4569EB4; Tue, 19 Oct 2021 09:08:47 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 33C0248; Tue, 19 Oct 2021 09:08:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 25/30] Silicon/SiFive: Use mtime CSR library Date: Tue, 19 Oct 2021 16:10:02 +0800 Message-Id: <20211019081007.31165-26-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: pArvweNFQOkZj9pTZJ8yJlAJKH0lnTc8 X-Proofpoint-ORIG-GUID: pArvweNFQOkZj9pTZJ8yJlAJKH0lnTc8 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: ALyBYFx2wUIm4qLSjWdTA1cyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634530; bh=slXfSt0GyIqpBN9v8lx8YuI4QXzarKD1vrIL9kl0J6E=; h=Cc:Date:From:Reply-To:Subject:To; b=F14txi/aHZSW9o9wvK1B4Ln3a3BcytkWNF4b5KJTOjP/S1vCaQAu0xz75Btf1+0+72B aW3ZIR2iiz6LigBwhHYksIqX5ycwmFqHUDs3XuIvErLy4GdxljSc8+8/i7CWNJd4EEGVH SiXmx8wLg6dMpdKNbsgBxwy4nkSZyW10hUg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634531669100003 Content-Type: text/plain; charset="utf-8" Use mtime CSR library interface to access mtime CSR in Timer DXE driver. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 ++ .../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 + .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 14 +++++--------- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 4d16adfc82..c29b36e9bb 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -148,6 +148,8 @@ RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf + #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf + MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf =20 =20 diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.in= f b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf index 25cb3bb8b4..4571621a2e 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf @@ -30,6 +30,7 @@ BaseLib DebugLib IoLib + MachineModeTimerLib RiscVCpuLib RiscVEdk2SbiLib UefiBootServicesTableLib diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c b/P= latform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c index 065ecdda86..deb5799277 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c @@ -15,9 +15,6 @@ #include #include =20 -STATIC volatile VOID * const p_mtime =3D (VOID *)CLINT_REG_MTIME; -#define MTIME (*p_mtime) -#define MTIMECMP(i) (p_mtimecmp[i]) BOOLEAN TimerHandlerReentry =3D FALSE; =20 // @@ -73,7 +70,7 @@ TimerInterruptHandler ( // MMode timer occurred when processing // SMode timer handler. // - RiscvTimer =3D readq_relaxed(p_mtime); + RiscvTimer =3D RiscVReadMachineTimerInterface(); SbiSetTimer (RiscvTimer +=3D mTimerPeriod); csr_clear(CSR_SIP, MIP_STIP); return; @@ -91,7 +88,7 @@ TimerInterruptHandler ( if (mTimerNotifyFunction !=3D NULL) { mTimerNotifyFunction (mTimerPeriod); } - RiscvTimer =3D readq_relaxed(p_mtime); + RiscvTimer =3D RiscVReadMachineTimerInterface(); SbiSetTimer (RiscvTimer +=3D mTimerPeriod); gBS->RestoreTPL (OriginalTPL); csr_set(CSR_SIE, MIP_STIP); // enable SMode timer int @@ -185,10 +182,9 @@ TimerDriverSetTimerPeriod ( return EFI_SUCCESS; } =20 - mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us - - RiscvTimer =3D readq_relaxed(p_mtime); - SbiSetTimer(RiscvTimer + mTimerPeriod); + mTimerPeriod =3D TimerPeriod; // convert unit from 100ns to 1us + RiscvTimer =3D RiscVReadMachineTimerInterface(); + SbiSetTimer(RiscvTimer + mTimerPeriod / 10); =20 mCpu->EnableInterrupt(mCpu); csr_set(CSR_SIE, MIP_STIP); // enable timer int --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82336): https://edk2.groups.io/g/devel/message/82336 Mute This Topic: https://groups.io/mt/86435689/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82337+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82337+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634532; cv=none; d=zohomail.com; s=zohoarc; b=PfwBve5UhTxjCieei9C6WgePWxB28j/IaPljjAn/GPr6NwXCG5DCi7eOmdAFHEX4PpURKNjgEXZKoDJo1IKGn9IWRAeTjmM61PkccHaXe+RzkFrLeOADFUBIU2ievxtI18OZj6EEGmQNIN4qtX35m33/oFkjQ+bLHJja7zdMzWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634532; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KPU2Cx2DF9/rfbRLIlfzppNXAv/TQu/lKZsFSENjK1E=; b=CpUs3n+2aGnkbiYkU+3u+iChNGYEu2xeSPr+FRaqxgGJ+E5GriQnsToOYbDUUBbneUWkWdxZieXAFvmusoSeirOe4EZ/isvi/z1w5gYcJD8ksrzO/v4roxo+gkKzoBengsydayqDw238F4kxCrGiIGaLDyMY0gR39fV0GKC4qzo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82337+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634532702515.1458682185058; Tue, 19 Oct 2021 02:08:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AA46YY1788612xJTuWt1rEjH; Tue, 19 Oct 2021 02:08:52 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.7157.1634634529572297913 for ; Tue, 19 Oct 2021 02:08:51 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J81sZG029192; Tue, 19 Oct 2021 09:08:49 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gv8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:49 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id A597B4E; Tue, 19 Oct 2021 09:08:48 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 979404C; Tue, 19 Oct 2021 09:08:47 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable Date: Tue, 19 Oct 2021 16:10:03 +0800 Message-Id: <20211019081007.31165-27-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: Feh_XBAT73RNdk51gsm1xtFViXRmAJSE X-Proofpoint-ORIG-GUID: Feh_XBAT73RNdk51gsm1xtFViXRmAJSE X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: zh8Jj8nZ61waghyxlSfvn0wmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634532; bh=owEHPeZBxxGZvpWT9k0GuRiePTXFGVi27AQMHB+IW3M=; h=Cc:Date:From:Reply-To:Subject:To; b=prEa1/+3tzG6QGh9TljxzRkbIq46wdVYOEZHp0u0or0IMQE1PIJBPAP366/RIqvnRsv bJbq+eOYUnFOI19TTvNE5VvJ6nEBX984HdVd0kM/LTddFmbrlef68AfNFDGhCdmXXDSrI LfshsD/Mjo5db4fhhEAxmhKOz+s7QOCiUfE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634533959100001 Content-Type: text/plain; charset="utf-8" Remove global variable from SerialPortLib because this module is not necessarily executed in memory. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 + .../Library/SerialIoLib/SerialPortLib.c | 58 +++++++++++++++---- 2 files changed, 49 insertions(+), 10 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h b/Platform/= SiFive/U5SeriesPkg/Include/SifiveU5Uart.h index 0ccb98e874..be8dce8c96 100644 --- a/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h +++ b/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h @@ -10,6 +10,7 @@ #ifndef SIFIVE_U5_SERIES_UART_H_ #define SIFIVE_U5_SERIES_UART_H_ =20 +#include #include =20 #endif diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.= c b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c index 7bc73a0b82..42e5aa7b76 100644 --- a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c +++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c @@ -8,6 +8,7 @@ **/ =20 #include +#include #include #include #include @@ -41,7 +42,7 @@ #define UART_BAUDRATE 115200 #define SYS_CLK FixedPcdGet32(PcdU5PlatformSystemClock) =20 -BOOLEAN Initiated =3D FALSE; +BOOLEAN Initiated =3D TRUE; =20 /** Get value from serial port register. @@ -55,7 +56,9 @@ UINT32 GetReg ( IN UINT32 RegIndex ) { - return MmioRead32 (FixedPcdGet32(PcdU5UartBase) + (RegIndex * 0x4)); + STATIC volatile UINT32 * const uart =3D (UINT32 *)FixedPcdGet32(PcdU5Uar= tBase); + + return readl ((volatile void *)(uart + RegIndex)); } =20 /** @@ -70,7 +73,9 @@ VOID SetReg ( IN UINT32 Value ) { - MmioWrite32 (Value, FixedPcdGet32(PcdU5UartBase) + (RegIndex * 0x4)); + STATIC volatile UINT32 * const uart =3D (UINT32 *)FixedPcdGet32(PcdU5Uar= tBase); + + writel (Value, (volatile void *)(uart + RegIndex)); } =20 /** @@ -104,7 +109,36 @@ UINT32 SifiveUartGetChar (VOID) } return -1; } +/** + Find minimum divisor divides in_freq to max_target_hz; + Based on uart driver n SiFive FSBL. + + f_baud =3D f_in / (div + 1) =3D> div =3D (f_in / f_baud) - 1 + The nearest integer solution requires rounding up as to not exceed max_t= arget_hz. + div =3D ceil(f_in / f_baud) - 1 + =3D floor((f_in - 1 + f_baud) / f_baud) - 1 + This should not overflow as long as (f_in - 1 + f_baud) does not exceed + 2^32 - 1, which is unlikely since we represent frequencies in kHz. + + @param Freq The given clock to UART. + @param MaxTargetHZ Target baudrate. =20 +**/ +UINT32 +UartMinClkDivisor ( + IN UINT64 Freq, + IN UINT64 MaxTargetHZ + ) +{ + UINT64 Quotient; + + Quotient =3D (Freq + MaxTargetHZ - 1) / (MaxTargetHZ); + if (Quotient =3D=3D 0) { + return 0; + } else { + return Quotient - 1; + } +} /** Initialize the serial device hardware. =20 @@ -116,20 +150,24 @@ UINT32 SifiveUartGetChar (VOID) @retval RETURN_DEVICE_ERROR The serail device could not be initialized. =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI SerialPortInitialize ( VOID ) { - if (Initiated) { - return RETURN_SUCCESS; + UINT32 Divisor; + UINT32 CurrentDivisor; + + Divisor =3D UartMinClkDivisor (SYS_CLK / 2, UART_BAUDRATE); + if (Divisor =3D=3D 0) { + return EFI_INVALID_PARAMETER; } - if (sifive_uart_init (FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BA= UDRATE) !=3D 0) { - return EFI_DEVICE_ERROR; + CurrentDivisor =3D GetReg(UART_REG_DIV); + if (Divisor !=3D CurrentDivisor) { + sifive_uart_init (FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BAUD= RATE); } - Initiated =3D TRUE; - return RETURN_SUCCESS; + return EFI_SUCCESS; } =20 /** --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82337): https://edk2.groups.io/g/devel/message/82337 Mute This Topic: https://groups.io/mt/86435691/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82338+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82338+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634534; cv=none; d=zohomail.com; s=zohoarc; b=YBNCkVfa6kbmuxEs9i6sBG4Cjpzd1L1wJFVFueBbZUkcaa7PbQcoZZC2zqufx3XCA87KOm8T0RTT0LL19YT11EzLXraGwnwtEHDRn++IkgCe9EOaoDOVFBBmetA1nqqTKlW3CPpq4YaPKR5MoCtnSH39e5+dpYbbDOOgEfC/B/0= ARC-Message-Signature: i=1; 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Tue, 19 Oct 2021 02:08:52 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J7Wc19031246; Tue, 19 Oct 2021 09:08:51 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:50 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 13EFA9A; Tue, 19 Oct 2021 09:08:50 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 050B756; Tue, 19 Oct 2021 09:08:48 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Date: Tue, 19 Oct 2021 16:10:04 +0800 Message-Id: <20211019081007.31165-28-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-Proofpoint-ORIG-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: YU7HI2Ab1SFYAJRJ7muTi7DWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634533; bh=CBpzhdu5YwzquNfKCvvjYLyZhJfDsagAEhnD4FPRF/k=; h=Cc:Date:From:Reply-To:Subject:To; b=Sz2l6e0cB1qw5jDwxrV8XAcu3wHdRDkyO0vmkgedfg2nFpWZqoFL7V+mpowr0zv7MXr 6P49XV9bohdNY9/FJFHoXk9wdy6a/kr3C4Bc834QKIck9JGrIGkvtcGLxvmGI/Hk12Gbs 2VB8sWwVHE6p954ffqMnwctACdMulg6KgEU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634536123100011 Content-Type: text/plain; charset="utf-8" Code changes to incorporate with OpenSBI commit ID: a731c7e36988c3308e1978ecde491f2f6182d490 Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 4 + .../Library/OpensbiPlatformLib/Platform.c | 57 ---- .../Universal/Sec/Edk2OpenSbiPlatform.c | 149 --------- .../PlatformPkg/Universal/Sec/SecMain.c | 48 ++- .../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++-------- 6 files changed, 212 insertions(+), 356 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 909fbffa8d..2e1227733a 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -51,12 +51,4 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =20 - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock - - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize + diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 1cfbef961f..dd5f01ab4d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -66,6 +66,10 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index b477b81d74..c62d235333 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; } =20 -static int generic_system_reset_check(u32 reset_type, u32 reset_reason) -{ - if (generic_plat && generic_plat->system_reset_check) - return generic_plat->system_reset_check(reset_type, - reset_reason, - generic_plat_match); - return fdt_system_reset_check(reset_type, reset_reason); -} - -static void generic_system_reset(u32 reset_type, u32 reset_reason) -{ - if (generic_plat && generic_plat->system_reset) { - generic_plat->system_reset(reset_type, reset_reason, - generic_plat_match); - return; - } - - fdt_system_reset(reset_type, reset_reason); -} - -#define EDK2_ROOT_FW_REGION 0 -#define EDK2_FW_REGION 1 -#define EDK2_VARIABLE_REGION 2 -#define EDK2_ALL_REGION 3 -#define EDK2_END_REGION 4 -static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 }; - -struct sbi_domain_memregion *get_mem_regions(void) { - /* EDK2 root firmware domain memory region */ - root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize)); - root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress); - root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0; - - /*EDK2 firmware domain memory region */ - root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize)); - root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress); - root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE; - - /*EDK2 firmware domain memory region */ - root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize)); - root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress); - root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE; - - /* EDK2 domain allow everything memory region */ - root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen; - root_memregs[EDK2_ALL_REGION].base =3D 0; - root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE | - SBI_DOMAIN_MEMREGION_WRITEABLE | - SBI_DOMAIN_MEMREGION_EXECUTABLE); - - /* EDK2 domain memory region end */ - root_memregs[EDK2_END_REGION].order =3D 0; - - return root_memregs; -} - const struct sbi_platform_operations platform_ops =3D { .early_init =3D generic_early_init, .final_init =3D generic_final_init, .early_exit =3D generic_early_exit, .final_exit =3D generic_final_exit, - .domains_root_regions =3D get_mem_regions, .domains_init =3D generic_domains_init, .console_init =3D fdt_serial_init, .irqchip_init =3D fdt_irqchip_init, diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.= c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c index 79b2f33675..779705489c 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c @@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID) return 0; } =20 -/** Get platform specific root domain memory regions */ -struct sbi_domain_memregion * -Edk2OpensbiPlatformGetMemRegions (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.domains_root_regions) { - return platform_ops.domains_root_regions (); - } - return 0; -} - /** Initialize (or populate) domains for the platform */ int Edk2OpensbiPlatformDomainsInit (VOID) { @@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID) return 0; } =20 -/** Write a character to the platform console output */ -VOID Edk2OpensbiPlatformSerialPutc ( - CHAR8 Ch - ) -{ - if (platform_ops.console_putc) { - return platform_ops.console_putc (Ch); - } -} - -/** Read a character from the platform console input */ -int Edk2OpensbiPlatformSerialGetc (VOID) -{ - if (platform_ops.console_getc) { - return platform_ops.console_getc (); - } - return 0; -} - /** Initialize the platform console */ int Edk2OpensbiPlatformSerialInit (VOID) { @@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID) } } =20 -/** Send IPI to a target HART */ -VOID Edk2OpensbiPlatformIpiSend ( - UINT32 TargetHart - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_send) { - return platform_ops.ipi_send (TargetHart); - } -} - -/** Clear IPI for a target HART */ -VOID Edk2OpensbiPlatformIpiClear ( - UINT32 TargetHart - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_clear) { - return platform_ops.ipi_clear (TargetHart); - } -} - /** Initialize IPI for current HART */ int Edk2OpensbiPlatformIpiInit ( BOOLEAN ColdBoot @@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID) return 0; } =20 -/** Get platform timer value */ -UINT64 Edk2OpensbiPlatformTimerValue (VOID) -{ - if (platform_ops.timer_value) { - return platform_ops.timer_value (); - } - return 0; -} - -/** Start platform timer event for current HART */ -VOID Edk2OpensbiPlatformTimerEventStart ( - UINT64 NextEvent - ) -{ - if (platform_ops.timer_event_start) { - return platform_ops.timer_event_start (NextEvent); - } -} - -/** Stop platform timer event for current HART */ -VOID Edk2OpensbiPlatformTimerEventStop (VOID) -{ - if (platform_ops.timer_event_stop) { - return platform_ops.timer_event_stop (); - } -} - /** Initialize platform timer for current HART */ int Edk2OpensbiPlatformTimerInit ( BOOLEAN ColdBoot @@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID) } } =20 -/** Bringup the given hart */ -int Edk2OpensbiPlatformHartStart ( - UINT32 HartId, - ulong Saddr - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.hart_start) { - return platform_ops.hart_start (HartId, Saddr); - } - return 0; -} -/** - Stop the current hart from running. This call doesn't expect to - return if success. -**/ -int Edk2OpensbiPlatformHartStop (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.hart_stop) { - return platform_ops.hart_stop (); - } - return 0; -} - -/** - Check whether reset type and reason supported by the platform* - -**/ -int Edk2OpensbiPlatformSystemResetCheck ( - UINT32 ResetType, - UINT32 ResetReason - ) -{ - if (platform_ops.system_reset_check) { - return platform_ops.system_reset_check (ResetType, ResetReason); - } - return 0; -} - -/** Reset the platform */ -VOID Edk2OpensbiPlatformSystemReset ( - UINT32 ResetType, - UINT32 ResetReason - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.system_reset) { - return platform_ops.system_reset (ResetType, ResetReason); - } -} - /** platform specific SBI extension implementation probe function */ int Edk2OpensbiPlatformVendorExtCheck ( long ExtId @@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatf= ormOps =3D { .final_exit =3D Edk2OpensbiPlatformFinalExit, .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension, .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN, - .domains_root_regions =3D Edk2OpensbiPlatformGetMemRegions, .domains_init =3D Edk2OpensbiPlatformDomainsInit, - .console_putc =3D Edk2OpensbiPlatformSerialPutc, - .console_getc =3D Edk2OpensbiPlatformSerialGetc, .console_init =3D Edk2OpensbiPlatformSerialInit, .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit, .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit, - .ipi_send =3D Edk2OpensbiPlatformIpiSend, - .ipi_clear =3D Edk2OpensbiPlatformIpiClear, .ipi_init =3D Edk2OpensbiPlatformIpiInit, .ipi_exit =3D Edk2OpensbiPlatformIpiExit, .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit, - .timer_value =3D Edk2OpensbiPlatformTimerValue, - .timer_event_stop =3D Edk2OpensbiPlatformTimerEventStop, - .timer_event_start =3D Edk2OpensbiPlatformTimerEventStart, .timer_init =3D Edk2OpensbiPlatformTimerInit, .timer_exit =3D Edk2OpensbiPlatformTimerExit, - .hart_start =3D Edk2OpensbiPlatformHartStart, - .hart_stop =3D Edk2OpensbiPlatformHartStop, - .system_reset_check =3D Edk2OpensbiPlatformSystemResetCheck, - .system_reset =3D Edk2OpensbiPlatformSystemReset, .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck, .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider, }; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 93ff8a598d..3bc3690047 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -15,10 +15,12 @@ #include #include #include // Reference to header file in opensbi +#include #include // Reference to header file in opensbi -#include // Reference to header file in opensbi +#include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi +#include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi #include // Reference to header file in opensbi @@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatfor= mOps; atomic_t BootHartDone =3D ATOMIC_INITIALIZER(0); atomic_t NonBootHartMessageLock =3D ATOMIC_INITIALIZER(0); =20 +int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg); + typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartinde= x); =20 +struct sbi_domain_memregion fw_memregs; + +int SecSetEdk2FwMemoryRegions (VOID) { + int Ret; + + Ret =3D 0; + + // + // EDK2 PEI domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdFirmwareDomainSize)); + fw_memregs.base =3D FixedPcdGet32(PcdFirmwareDomainBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE; + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__)); + } + + // + // EDK2 EFI Variable domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdVariableFirmwareRegion= Size)); + fw_memregs.base =3D FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE; + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__)); + } + return Ret; +} + /** Locates a section within a series of sections with the specified section type. @@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit( DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); return 0; } + // + // Setup firmware memory region. + // + if (SecSetEdk2FwMemoryRegions () !=3D 0) { + ASSERT (FALSE); + } + // // Boot HART is already in the process of OpenSBI initialization. // We can let other HART to keep booting. @@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit ( } } =20 - DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__)); + DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUN= CTION__)); DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch)); DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform)); DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext)); @@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch); } =20 -void OpensbiDebugPrint (char *debugstr, ...) +VOID OpensbiDebugPrint (CHAR8 *debugstr, ...) { VA_LIST Marker; =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index dc410703e0..96087738a3 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -18,6 +18,12 @@ =20 #include =20 +.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2 + add \__d0, \__s0, zero + add \__d1, \__s1, zero + add \__d2, \__s2, zero +.endm + .text .align 3 =20 @@ -90,7 +96,11 @@ _scratch_init: la a4, _hartid_to_scratch sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_sc= ratch function in scratch buffer*/ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp) - + /* Store trap-exit function address in scratch space */ + lla a4, _trap_exit + sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp) + /* Clear tmp0 in scratch space */ + sd zero, SBI_SCRATCH_TMP0_OFFSET(tp) #ifdef FW_OPTIONS li a4, FW_OPTIONS sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp) @@ -322,160 +332,174 @@ _uninitialized_hart_wait: wfi j _uninitialized_hart_wait =20 - .align 3 - .section .entry, "ax", %progbits - .align 3 - .globl _trap_handler -_trap_handler: - +.macro TRAP_SAVE_AND_SETUP_SP_T0 /* Swap TP and MSCRATCH */ - csrrw tp, CSR_MSCRATCH, tp + csrrw tp, CSR_MSCRATCH, tp =20 /* Save T0 in scratch space */ - REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp) + REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp) =20 - /* Check which mode we came from */ - csrr t0, CSR_MSTATUS - srl t0, t0, MSTATUS_MPP_SHIFT - and t0, t0, PRV_M - xori t0, t0, PRV_M - beq t0, zero, _trap_handler_m_mode - - /* We came from S-mode or U-mode */ -_trap_handler_s_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Setup exception stack */ - add sp, tp, -(SBI_TRAP_REGS_SIZE) - - /* Jump to code common for all modes */ - j _trap_handler_all_mode - - /* We came from M-mode */ -_trap_handler_m_mode: - /* Set T0 to original SP */ - add t0, sp, zero - - /* Re-use current SP as exception stack */ - add sp, sp, -(SBI_TRAP_REGS_SIZE) - -_trap_handler_all_mode: - /* Save original SP (from T0) on stack */ - REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp) + /* + * Set T0 to appropriate exception stack + * + * Came_From_M_Mode =3D ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1; + * Exception_Stack =3D TP ^ (Came_From_M_Mode & (SP ^ TP)) + * + * Came_From_M_Mode =3D 0 =3D=3D> Exception_Stack =3D TP + * Came_From_M_Mode =3D -1 =3D=3D> Exception_Stack =3D SP + */ + csrr t0, CSR_MSTATUS + srl t0, t0, MSTATUS_MPP_SHIFT + and t0, t0, PRV_M + slti t0, t0, PRV_M + add t0, t0, -1 + xor sp, sp, tp + and t0, t0, sp + xor sp, sp, tp + xor t0, tp, t0 + + /* Save original SP on exception stack */ + REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0) + + /* Set SP to exception stack and make room for trap registers */ + add sp, t0, -(SBI_TRAP_REGS_SIZE) =20 /* Restore T0 from scratch space */ - REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp) + REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp) =20 /* Save T0 on stack */ - REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp) =20 /* Swap TP and MSCRATCH */ - csrrw tp, CSR_MSCRATCH, tp + csrrw tp, CSR_MSCRATCH, tp +.endm =20 +.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush /* Save MEPC and MSTATUS CSRs */ - csrr t0, CSR_MEPC - REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) - csrr t0, CSR_MSTATUS - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) - REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) -#if __riscv_xlen =3D=3D 32 - csrr t0, CSR_MISA - srli t0, t0, ('H' - 'A') - andi t0, t0, 0x1 - beq t0, zero, _skip_mstatush_save - csrr t0, CSR_MSTATUSH - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) -_skip_mstatush_save: -#endif + csrr t0, CSR_MEPC + REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrr t0, CSR_MSTATUS + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) +.if \have_mstatush + csrr t0, CSR_MSTATUSH + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) +.else + REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) +.endif +.endm + +.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0 + /* Save all general regisers except SP and T0 */ + REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) + REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp) + REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp) +.endm + +.macro TRAP_CALL_C_ROUTINE + /* Call C routine */ + add a0, sp, zero + call sbi_trap_handler +.endm + +.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0 + /* Restore all general regisers except A0 and T0 */ + REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0) + REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0) + REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0) + REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0) + REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0) + REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0) + REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0) + REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0) + REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0) + REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0) + REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0) + REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0) + REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0) + REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0) + REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0) + REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0) + REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0) + REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0) + REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0) + REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0) + REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0) + REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0) + REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0) + REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0) + REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0) + REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0) + REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0) + REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0) + REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0) +.endm + +.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush + /* Restore MEPC and MSTATUS CSRs */ + REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0) + csrw CSR_MEPC, t0 + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0) + csrw CSR_MSTATUS, t0 +.if \have_mstatush + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0) + csrw CSR_MSTATUSH, t0 +.endif +.endm + +.macro TRAP_RESTORE_A0_T0 + /* Restore T0 */ + REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0) =20 - /* Save all general registers except SP and T0 */ - REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) - REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) - REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp) - REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp) - REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp) - REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp) - REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp) - REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp) - REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp) - REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp) - REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp) - REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp) - REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp) - REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp) - REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp) - REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp) - REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp) - REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp) - REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp) - REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp) - REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp) - REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp) - REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp) - REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp) - REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp) - REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp) - REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp) - REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp) - REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp) - REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + /* Restore A0 */ + REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0) +.endm =20 - /* Call C routine */ - add a0, sp, zero - call sbi_trap_handler - - /* Restore all general registers except SP and T0 */ - REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp) - REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp) - REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp) - REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp) - REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp) - REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp) - REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp) - REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp) - REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp) - REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp) - REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp) - REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp) - REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp) - REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp) - REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp) - REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp) - REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp) - REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp) - REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp) - REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp) - REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp) - REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp) - REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp) - REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp) - REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp) - REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp) - REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp) - REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp) - REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + .section .entry, "ax", %progbits + .align 3 + .globl _trap_handler + .globl _trap_exit +_trap_handler: + TRAP_SAVE_AND_SETUP_SP_T0 =20 - /* Restore MEPC and MSTATUS CSRs */ - REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) - csrw CSR_MEPC, t0 - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) - csrw CSR_MSTATUS, t0 -#if __riscv_xlen =3D=3D 32 - csrr t0, CSR_MISA - srli t0, t0, ('H' - 'A') - andi t0, t0, 0x1 - beq t0, zero, _skip_mstatush_restore - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp) - csrw CSR_MSTATUSH, t0 -_skip_mstatush_restore: -#endif + TRAP_SAVE_MEPC_MSTATUS 0 =20 - /* Restore T0 */ - REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0 + + TRAP_CALL_C_ROUTINE + +_trap_exit: + TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0 + + TRAP_RESTORE_MEPC_MSTATUS 0 =20 - /* Restore SP */ - REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp) + TRAP_RESTORE_A0_T0 =20 mret =20 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82338): https://edk2.groups.io/g/devel/message/82338 Mute This Topic: https://groups.io/mt/86435693/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82339+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82339+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634533; cv=none; d=zohomail.com; s=zohoarc; b=FUyGkBV5yEBfAQMCn+UAFYQ20L2bW43aw7yBqqfXfwcw0vn8XPWp0TXEeFALGeuZ22PJNYbTjrPj/m+mkgi1vK6cE9KnG1eA6vHMu6vSUDqfWJZ9ZbW8G1IhvIFDpHpcgqTeiTjZNPfOTC16QJyWq/rY2Esok6tPf6ePtQTeSak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634533; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Msq40oZ4kLrbYDgguSvoti44nfy24OqlSZcN4BGEVa4=; b=V/d0ihHBHHj5mCnN4tiaqc5kpFmNIA2/dMPloRzWtzVOKji3TQ4pRvDfyJitGezj42WiSeKCkokwwggRKBL2viQqh26ZjGrXQIKzYdWLvM95DQqwY7+PHDMyE6W6+mSG2whDbD1ISGxt8S0b5gYJKkQONoH/iTWLOaAkm8S58jo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82339+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634533674403.46691607927346; Tue, 19 Oct 2021 02:08:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3L5PYY1788612xE50ZCQPBgO; Tue, 19 Oct 2021 02:08:53 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7335.1634634532765481745 for ; Tue, 19 Oct 2021 02:08:52 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J61ulw018328; Tue, 19 Oct 2021 09:08:52 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gvm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:52 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 73F6B5E; Tue, 19 Oct 2021 09:08:51 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 6599948; Tue, 19 Oct 2021 09:08:50 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook. Date: Tue, 19 Oct 2021 16:10:05 +0800 Message-Id: <20211019081007.31165-29-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: h-GdOwzb3YUHGqO7rkfNCwUEMnUoxAvT X-Proofpoint-ORIG-GUID: h-GdOwzb3YUHGqO7rkfNCwUEMnUoxAvT X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: SfJplO5aSGsh2oNDLYHJ53dex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634533; bh=zQAxFK10Sh1hs+uOHr+tnxrxbX67BQFSHSiV0/V87Hk=; h=Cc:Date:From:Reply-To:Subject:To; b=qdAA58SAnV8+4kJLKbCVfC/0mvPf6EqtU01TnIIkrFhFO02pli4//LzY4eFg3DRqog9 JknVMnsaKQF+rD2E6nJKCslg5GAdsW4DOTL1jVCc1IKYvTGDtTWXq/IBRgIAQrjLGDvKt JPIdP0Mz045NxadAYWkoQ4TEh3iSwqGYx2s= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634534201100006 Content-Type: text/plain; charset="utf-8" Separate EDK2 Opensbi platform operations hooks from Secmain as an individual library which can be override by OEM platform. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 + .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +- .../FreedomU500VC707Board/U500.dsc | 1 + .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 + .../Edk2OpensbiPlatformWrapperLib.inf | 44 ++ .../PlatformPkg/Universal/Sec/SecMain.inf | 10 +- .../Library/Edk2OpensbiPlatformWrapperLib.h | 16 + .../PlatformPkg/Universal/Sec/SecMain.h | 1 + .../Edk2OpensbiPlatformWrapperLib.c | 530 ++++++++++++++++++ .../Universal/Sec/Edk2OpenSbiPlatform.c | 277 --------- .../PlatformPkg/Universal/Sec/SecMain.c | 141 ----- 11 files changed, 600 insertions(+), 426 deletions(-) create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatform= WrapperLib/Edk2OpensbiPlatformWrapperLib.inf create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2Opensbi= PlatformWrapperLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatform= WrapperLib/Edk2OpensbiPlatformWrapperLib.c delete mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPl= atform.c diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 947ae40e20..19206556ce 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -20,6 +20,7 @@ [LibraryClasses] FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProce= ssorSpecificLib.h RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryIn= itLib.h + Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h =20 [Guids] gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index bbb043f9ed..47a0fc4494 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -43,7 +43,6 @@ RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatf= ormLib/OpensbiPlatformLib.inf RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf - RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf @@ -72,6 +71,8 @@ =20 [LibraryClasses.common.SEC] ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf + Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2Op= ensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecial= PlatformLibNull/RiscVSpecialPlatformLibNull.inf =20 [LibraryClasses.common.DXE_DRIVER] @@ -87,6 +88,7 @@ Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpi= LibNull.inf Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpe= cialPlatformLibNull.inf + Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2Op= ensbiPlatformWrapperLib.inf =20 [Components.common.SEC] Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/P= latform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc index f14511120e..e680e330ed 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc @@ -158,6 +158,7 @@ =20 ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2Op= ensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf =20 !ifdef $(SOURCE_DEBUG_ENABLE) DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index c29b36e9bb..98a6a69ca3 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -165,6 +165,7 @@ =20 ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2Op= ensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf RiscVSpecialPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf =20 !ifdef $(SOURCE_DEBUG_ENABLE) diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapper= Lib/Edk2OpensbiPlatformWrapperLib.inf b/Platform/RISC-V/PlatformPkg/Library= /Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf new file mode 100644 index 0000000000..8c268c556d --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.inf @@ -0,0 +1,44 @@ +## @file +# EDK2 OpenSBI generic platform wrapper library +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D Edk2OpensbiPlatformWrapperLib + FILE_GUID =3D 364395A3-21BA-400C-96F7-5D9817F6FEE5 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D Edk2OpensbiPlatformWrapperLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + Edk2OpensbiPlatformWrapperLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize + +[LibraryClasses] + BaseLib + DebugLib + DebugAgentLib + PcdLib + PrintLib diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index dd5f01ab4d..ceb6d25222 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -23,7 +23,6 @@ =20 [Sources] SecMain.c - Edk2OpenSbiPlatform.c =20 [Sources.RISCV64] Riscv64/SecEntry.S @@ -40,6 +39,7 @@ BaseMemoryLib DebugAgentLib DebugLib + Edk2OpensbiPlatformWrapperLib ExtractGuidedSectionLib FdtLib IoLib @@ -62,14 +62,10 @@ [Pcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatfor= mWrapperLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlat= formWrapperLib.h new file mode 100644 index 0000000000..4da0a64a8c --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrappe= rLib.h @@ -0,0 +1,16 @@ +/** @file + Definition of EDK2 OpenSBI generic platform wrapper library + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_ +#define EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_ + +#include + +extern struct sbi_platform_operations Edk2OpensbiPlatformOps; + +#endif diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.h index 496799efc0..6188778fc4 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapper= Lib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/E= dk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c new file mode 100644 index 0000000000..6c5c1a789f --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.c @@ -0,0 +1,530 @@ +/* + EDK2 OpenSBI generic platform wrapper library + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct sbi_platform_operations platform_ops; +extern atomic_t BootHartDone; + +/** + Add firmware memory domain. + + @retval OpenSBI error code. + +**/ +INT32 +SecSetEdk2FwMemoryRegions ( + VOID + ) +{ + INT32 Ret; + struct sbi_domain_memregion fw_memregs; + + Ret =3D 0; + + // + // EDK2 PEI domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdFirmwareDomainSize)); + fw_memregs.base =3D FixedPcdGet32(PcdFirmwareDomainBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE; + Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__)); + } + + // + // EDK2 EFI Variable domain memory region + // + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdVariableFirmwareRegion= Size)); + fw_memregs.base =3D FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress); + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE; + Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs); + if (Ret !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__)); + } + return Ret; +} +/** + OpenSBI platform early init hook. + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +SecPostOpenSbiPlatformEarlylInit( + IN BOOLEAN ColdBoot + ) +{ + UINT32 HartId; + + if (!ColdBoot) { + HartId =3D current_hartid(); + DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); + return 0; + } + // + // Setup firmware memory region. + // + if (SecSetEdk2FwMemoryRegions () !=3D 0) { + ASSERT (FALSE); + } + + // + // Boot HART is already in the process of OpenSBI initialization. + // We can let other HART to keep booting. + // + DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__)); + atomic_write (&BootHartDone, (UINT64)TRUE); + return 0; +} + +/** + OpenSBI platform final init hook. + We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT. + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +SecPostOpenSbiPlatformFinalInit ( + IN BOOLEAN ColdBoot + ) +{ + UINT32 HartId; + struct sbi_scratch *SbiScratch; + struct sbi_scratch *ScratchSpace; + struct sbi_platform *SbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + if (!ColdBoot) { + HartId =3D current_hartid(); + DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); + return 0; + } + + DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUN= CTION__)); + + SbiScratch =3D sbi_scratch_thishart_ptr(); + SbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(SbiScratch); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->f= irmware_context; + + // + // Print out scratch address of each hart + // + DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); + for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { + if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { + continue; + } + ScratchSpace =3D sbi_hartid_to_scratch (HartId); + if(ScratchSpace !=3D NULL) { + DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); + } else { + DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId= )); + } + } + + // + // Set firmware context Hart-specific pointer + // + for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { + if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { + continue; + } + ScratchSpace =3D sbi_hartid_to_scratch (HartId); + if (ScratchSpace !=3D NULL) { + FirmwareContext->HartSpecific[HartId] =3D + (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); + DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-spe= cific at address: 0x%x\n", + __FUNCTION__, + HartId, + FirmwareContext->HartSpecific [HartId] + )); + } + } + + DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUN= CTION__)); + DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch)); + DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform)); + DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext)); + SbiScratch->next_arg1 =3D (unsigned long)FirmwareContext; + + return 0; +} +/** + OpenSBI platform early init hook. + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformEarlyInit ( + IN BOOLEAN ColdBoot + ) +{ + INT32 ReturnCode; + + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_init) { + ReturnCode =3D platform_ops.early_init (ColdBoot); + if (ReturnCode) { + return ReturnCode; + } + } + if (ColdBoot =3D=3D TRUE) { + return SecPostOpenSbiPlatformEarlylInit(ColdBoot); + } + return 0; +} +/** + OpenSBI platform final init hook. + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformFinalInit ( + IN BOOLEAN ColdBoot + ) +{ + INT32 ReturnCode; + + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.final_init) { + ReturnCode =3D platform_ops.final_init (ColdBoot); + if (ReturnCode) { + return ReturnCode; + } + } + if (ColdBoot =3D=3D TRUE) { + return SecPostOpenSbiPlatformFinalInit(ColdBoot); + } + return 0; +} +/** + OpenSBI platform early exit hook. + +**/ +VOID +Edk2OpensbiPlatformEarlyExit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_exit) { + return platform_ops.early_exit (); + } +} + +/** + Platform final exit hook + + **/ +VOID +Edk2OpensbiPlatformFinalExit ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.early_exit) { + return platform_ops.early_exit (); + } +} + +/** + For platforms that do not implement misa, non-standard + methods are needed to determine cpu extension. + + @param[in] Extension Check ISA extension. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatforMMISACheckExtension ( + IN CHAR8 Extension + ) +{ + if (platform_ops.misa_check_extension) { + return platform_ops.misa_check_extension (Extension); + } + return 0; +} + +/** + Get the XLEN. + + @retval Return the XLEN + +**/ +INT32 +Edk2OpensbiPlatforMMISAGetXLEN ( + VOID +) +{ + if (platform_ops.misa_get_xlen) { + return platform_ops.misa_get_xlen (); + } + return 0; +} + +/** + Initialize (or populate) domains for the platform* + + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformDomainsInit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.domains_init) { + return platform_ops.domains_init (); + } + return 0; +} + +/** + Initialize the platform console + + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformSerialInit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.console_init) { + return platform_ops.console_init (); + } + return 0; +} + +/** + Initialize the platform interrupt controller for current HART + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformIrqchipInit ( + IN BOOLEAN ColdBoot +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.irqchip_init) { + return platform_ops.irqchip_init (ColdBoot); + } + return 0; +} + +/** + Exit the platform interrupt controller for current HART + +**/ +VOID +Edk2OpensbiPlatformIrqchipExit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.irqchip_exit) { + return platform_ops.irqchip_exit (); + } +} + +/** + Initialize IPI for current HART + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformIpiInit ( + IN BOOLEAN ColdBoot +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_init) { + return platform_ops.ipi_init (ColdBoot); + } + return 0; +} + +/** + Exit IPI for current HART + +**/ +VOID +Edk2OpensbiPlatformIpiExit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.ipi_exit) { + return platform_ops.ipi_exit (); + } +} + +/** + Get tlb flush limit value + + @retval Cache flush limit value. + +**/ +UINT64 +Edk2OpensbiPlatformTlbrFlushLimit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.get_tlbr_flush_limit) { + return platform_ops.get_tlbr_flush_limit (); + } + return 0; +} + +/** + Initialize platform timer for current HART + + @param[in] ColdBoot Is cold boot path or warm boot path. + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformTimerInit ( + IN BOOLEAN ColdBoot +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.timer_init) { + return platform_ops.timer_init (ColdBoot); + } + return 0; +} + +/** + Exit platform timer for current HART + +**/ +VOID +Edk2OpensbiPlatformTimerExit ( + VOID +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.timer_exit) { + return platform_ops.timer_exit (); + } +} + +/** + Check platform vendor SBI extension. + + @param[in] ExtId Extension ID. + @retval OpenSBI error code. + + **/ +INT32 +Edk2OpensbiPlatformVendorExtCheck ( + IN long ExtId +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.vendor_ext_check) { + return platform_ops.vendor_ext_check (ExtId); + } + return 0; +} + +/** + Platform specific SBI extension implementation provider + + @param[in] ExtId SBI extension ID. + @param[in] FuncId Function ID. + @param[in] Regs The trap register. + @param[in] OutValue Value returned from SBI. + @param[in] OutTrap The trap infomation after calling to SBI. + + @retval OpenSBI error code. + +**/ +INT32 +Edk2OpensbiPlatformVendorExtProvider ( + IN long ExtId, + IN long FuncId, + IN CONST struct sbi_trap_regs *Regs, + IN unsigned long *OutValue, + IN struct sbi_trap_info *OutTrap +) +{ + DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (platform_ops.vendor_ext_provider) { + return platform_ops.vendor_ext_provider ( + ExtId, + FuncId, + Regs, + OutValue, + OutTrap + ); + } + return 0; +} + +CONST struct sbi_platform_operations Edk2OpensbiPlatformOps =3D { + .early_init =3D Edk2OpensbiPlatformEarlyInit, + .final_init =3D Edk2OpensbiPlatformFinalInit, + .early_exit =3D Edk2OpensbiPlatformEarlyExit, + .final_exit =3D Edk2OpensbiPlatformFinalExit, + .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension, + .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN, + .domains_init =3D Edk2OpensbiPlatformDomainsInit, + .console_init =3D Edk2OpensbiPlatformSerialInit, + .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit, + .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit, + .ipi_init =3D Edk2OpensbiPlatformIpiInit, + .ipi_exit =3D Edk2OpensbiPlatformIpiExit, + .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit, + .timer_init =3D Edk2OpensbiPlatformTimerInit, + .timer_exit =3D Edk2OpensbiPlatformTimerExit, + .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck, + .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider, +}; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.= c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c deleted file mode 100644 index 779705489c..0000000000 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "SecMain.h" - -extern struct sbi_platform_operations platform_ops; - -int Edk2OpensbiPlatformEarlyInit ( - BOOLEAN ColdBoot - ) -{ - int ReturnCode; - - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.early_init) { - ReturnCode =3D platform_ops.early_init (ColdBoot); - if (ReturnCode) { - return ReturnCode; - } - } - if (ColdBoot =3D=3D TRUE) { - return SecPostOpenSbiPlatformEarlylInit(ColdBoot); - } - return 0; -} - -int Edk2OpensbiPlatformFinalInit ( - BOOLEAN ColdBoot - ) -{ - int ReturnCode; - - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.final_init) { - ReturnCode =3D platform_ops.final_init (ColdBoot); - if (ReturnCode) { - return ReturnCode; - } - } - if (ColdBoot =3D=3D TRUE) { - return SecPostOpenSbiPlatformFinalInit(ColdBoot); - } - return 0; -} - -VOID Edk2OpensbiPlatformEarlyExit ( - VOID - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.early_exit) { - return platform_ops.early_exit (); - } -} - -/** Platform final exit */ -VOID Edk2OpensbiPlatformFinalExit ( - VOID - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.early_exit) { - return platform_ops.early_exit (); - } -} - -/** - For platforms that do not implement misa, non-standard - methods are needed to determine cpu extension. -**/ -int Edk2OpensbiPlatforMMISACheckExtension ( - CHAR8 Extension - ) -{ - if (platform_ops.misa_check_extension) { - return platform_ops.misa_check_extension (Extension); - } - return 0; -} - -/** - For platforms that do not implement misa, non-standard - methods are needed to get MXL field of misa. -**/ -int Edk2OpensbiPlatforMMISAGetXLEN (VOID) -{ - if (platform_ops.misa_get_xlen) { - return platform_ops.misa_get_xlen (); - } - return 0; -} - -/** Initialize (or populate) domains for the platform */ -int Edk2OpensbiPlatformDomainsInit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.domains_init) { - return platform_ops.domains_init (); - } - return 0; -} - -/** Initialize the platform console */ -int Edk2OpensbiPlatformSerialInit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.console_init) { - return platform_ops.console_init (); - } - return 0; -} - -/** Initialize the platform interrupt controller for current HART */ -int Edk2OpensbiPlatformIrqchipInit ( - BOOLEAN ColdBoot - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.irqchip_init) { - return platform_ops.irqchip_init (ColdBoot); - } - return 0; -} - -/** Exit the platform interrupt controller for current HART */ -VOID Edk2OpensbiPlatformIrqchipExit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.irqchip_exit) { - return platform_ops.irqchip_exit (); - } -} - -/** Initialize IPI for current HART */ -int Edk2OpensbiPlatformIpiInit ( - BOOLEAN ColdBoot - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_init) { - return platform_ops.ipi_init (ColdBoot); - } - return 0; -} - -/** Exit IPI for current HART */ -VOID Edk2OpensbiPlatformIpiExit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.ipi_exit) { - return platform_ops.ipi_exit (); - } -} - -/** Get tlb flush limit value **/ -UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.get_tlbr_flush_limit) { - return platform_ops.get_tlbr_flush_limit (); - } - return 0; -} - -/** Initialize platform timer for current HART */ -int Edk2OpensbiPlatformTimerInit ( - BOOLEAN ColdBoot - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.timer_init) { - return platform_ops.timer_init (ColdBoot); - } - return 0; -} - -/** Exit platform timer for current HART */ -VOID Edk2OpensbiPlatformTimerExit (VOID) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.timer_exit) { - return platform_ops.timer_exit (); - } -} - -/** platform specific SBI extension implementation probe function */ -int Edk2OpensbiPlatformVendorExtCheck ( - long ExtId - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.vendor_ext_check) { - return platform_ops.vendor_ext_check (ExtId); - } - return 0; -} - - -/** platform specific SBI extension implementation provider */ -int Edk2OpensbiPlatformVendorExtProvider ( - long ExtId, - long FuncId, - const struct sbi_trap_regs *Regs, - unsigned long *OutValue, - struct sbi_trap_info *OutTrap - ) -{ - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); - - if (platform_ops.vendor_ext_provider) { - return platform_ops.vendor_ext_provider ( - ExtId, - FuncId, - Regs, - OutValue, - OutTrap - ); - } - return 0; -} - -const struct sbi_platform_operations Edk2OpensbiPlatformOps =3D { - .early_init =3D Edk2OpensbiPlatformEarlyInit, - .final_init =3D Edk2OpensbiPlatformFinalInit, - .early_exit =3D Edk2OpensbiPlatformEarlyExit, - .final_exit =3D Edk2OpensbiPlatformFinalExit, - .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension, - .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN, - .domains_init =3D Edk2OpensbiPlatformDomainsInit, - .console_init =3D Edk2OpensbiPlatformSerialInit, - .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit, - .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit, - .ipi_init =3D Edk2OpensbiPlatformIpiInit, - .ipi_exit =3D Edk2OpensbiPlatformIpiExit, - .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit, - .timer_init =3D Edk2OpensbiPlatformTimerInit, - .timer_exit =3D Edk2OpensbiPlatformTimerExit, - .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck, - .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider, -}; diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 3bc3690047..f2b2c7b583 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -25,49 +25,12 @@ #include // Reference to header file in opensbi #include // Reference to header file in opensbi =20 -extern struct sbi_platform_operations Edk2OpensbiPlatformOps; - // // Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done. // atomic_t BootHartDone =3D ATOMIC_INITIALIZER(0); atomic_t NonBootHartMessageLock =3D ATOMIC_INITIALIZER(0); =20 -int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg); - -typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartinde= x); - -struct sbi_domain_memregion fw_memregs; - -int SecSetEdk2FwMemoryRegions (VOID) { - int Ret; - - Ret =3D 0; - - // - // EDK2 PEI domain memory region - // - fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdFirmwareDomainSize)); - fw_memregs.base =3D FixedPcdGet32(PcdFirmwareDomainBaseAddress); - fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE; - Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); - if (Ret !=3D 0) { - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__)); - } - - // - // EDK2 EFI Variable domain memory region - // - fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdVariableFirmwareRegion= Size)); - fw_memregs.base =3D FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress); - fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE; - Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs); - if (Ret !=3D 0) { - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__)); - } - return Ret; -} - /** Locates a section within a series of sections with the specified section type. @@ -424,109 +387,6 @@ RegisterFirmwareSbiExtension ( return EFI_SUCCESS; } =20 -/** - OpenSBI platform early init hook. - -**/ -int -SecPostOpenSbiPlatformEarlylInit( - IN BOOLEAN ColdBoot - ) -{ - UINT32 HartId; - - if (!ColdBoot) { - HartId =3D current_hartid(); - DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); - return 0; - } - // - // Setup firmware memory region. - // - if (SecSetEdk2FwMemoryRegions () !=3D 0) { - ASSERT (FALSE); - } - - // - // Boot HART is already in the process of OpenSBI initialization. - // We can let other HART to keep booting. - // - DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__)); - atomic_write (&BootHartDone, (UINT64)TRUE); - return 0; -} - -/** - OpenSBI platform final init hook. - We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT. - -**/ -int -SecPostOpenSbiPlatformFinalInit ( - IN BOOLEAN ColdBoot - ) -{ - UINT32 HartId; - struct sbi_scratch *SbiScratch; - struct sbi_scratch *ScratchSpace; - struct sbi_platform *SbiPlatform; - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; - - if (!ColdBoot) { - HartId =3D current_hartid(); - DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId)); - return 0; - } - - DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUN= CTION__)); - - SbiScratch =3D sbi_scratch_thishart_ptr(); - SbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(SbiScratch); - FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->f= irmware_context; - - // - // Print out scratch address of each hart - // - DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__)); - for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { - continue; - } - ScratchSpace =3D sbi_hartid_to_scratch (HartId); - if(ScratchSpace !=3D NULL) { - DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= )); - } else { - DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId= )); - } - } - - // - // Set firmware context Hart-specific pointer - // - for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) { - if (sbi_platform_hart_invalid(SbiPlatform, HartId)) { - continue; - } - ScratchSpace =3D sbi_hartid_to_scratch (HartId); - if (ScratchSpace !=3D NULL) { - FirmwareContext->HartSpecific[HartId] =3D - (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); - DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-spe= cific at address: 0x%x\n", - __FUNCTION__, - HartId, - FirmwareContext->HartSpecific [HartId] - )); - } - } - - DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUN= CTION__)); - DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch)); - DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform)); - DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext)); - SbiScratch->next_arg1 =3D (unsigned long)FirmwareContext; - - return 0; -} =20 /** Transion from SEC phase to PEI phase. =20 @@ -787,7 +647,6 @@ VOID EFIAPI SecCoreStartUpWithStack( // ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; - if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { =20 Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82339): https://edk2.groups.io/g/devel/message/82339 Mute This Topic: https://groups.io/mt/86435694/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82342+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82342+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634538; cv=none; d=zohomail.com; s=zohoarc; b=VRx5Ff2UbMXSnlkVOdGuMFFm7jXP56Iru9hRukNdzk8bX6VxqWldeI2gBIh1w/ACPr6RLlWnJoN5QgdVRm12us2ILT23yJoU8iRfk9g/zQtMBK1/6xZz+F3lL6cFPOtwtMNBEP0QatMGTx6r7Logwcz1qQplYhcf/1Cx80CtLY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634538; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PDo07DH0qYjGDocmFO4NDPD9uY/LzayrU+hCuFxJKtc=; b=MbqcxnUrJHIScpkb3xF3ZpBJu4NHFVOqRPUiIUctVjg1gWVKkWqV7tYDZEXGfRX4OhCswvvlTQuEOeeciYkgCuMeYXxJv4dnNM1XEiGRfvgrzpzf8X/pXA07G3S049fE+77qx2e7ABPeoDYwkEQjpyXg+aYYUqRs/lQYs1k1F3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82342+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634634538691921.1697206921258; Tue, 19 Oct 2021 02:08:58 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hkVKYY1788612xjlh2cwjQ3K; Tue, 19 Oct 2021 02:08:58 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7408.1634634534030076795 for ; Tue, 19 Oct 2021 02:08:57 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8W5Mc018505; Tue, 19 Oct 2021 09:08:53 GMT X-Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 3bseymmq25-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:53 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id D2EE556; Tue, 19 Oct 2021 09:08:52 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id C559C48; Tue, 19 Oct 2021 09:08:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Date: Tue, 19 Oct 2021 16:10:06 +0800 Message-Id: <20211019081007.31165-30-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-Proofpoint-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 7YozKZGO2NdPJkHtfQVRYxkZx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634538; bh=gCBaeHrr1ct9dfs19ka2Al1Wt7XaNyi/VvufwKckqcQ=; h=Cc:Date:From:Reply-To:Subject:To; b=ngBTU1JS8/NAcclN2xSkHYvITJvZiFfcI5LD1NEv1hxLhFjxMtXRi0LGmmhSTJ/8kNW Gl54GqRgZERgJyRGbOKSTY/Fd3r3TBa2TbmTGUewaGAHNIP7Se0j4c17EVKHO2djbJiwN gmsppq1d7DtY5VLiqxbvhHtpk2CfZ3owLm4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634540309100003 Content-Type: text/plain; charset="utf-8" Determine total number of hart from DTB instead of using PCD. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../U540.fdf.inc | 1 - .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 - .../PlatformPkg/Universal/Sec/SecMain.inf | 1 - .../PlatformPkg/Universal/Sec/SecMain.c | 12 ++-- .../Universal/Sec/Riscv64/SecEntry.S | 60 +++++++++++++------ 5 files changed, 49 insertions(+), 28 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 1a525dc874..404c0b71ca 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -90,7 +90,6 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSi= ze =3D 0x10000 =20 SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz =3D= 1000000 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock =3D= 1000000000 # 1GHz system clock -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D= 5 # Total cores on U540 platform SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D= 1 # Boot hart ID =20 # diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 2e1227733a..6661ee8204 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -46,9 +46,6 @@ RiscVSpecialPlatformLib =20 [FixedPcd] - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =20 =20 diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index ceb6d25222..b949b6c470 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -61,7 +61,6 @@ =20 [Pcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index f2b2c7b583..17f33a02cc 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -530,7 +530,7 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection; =20 if (FixedPcdGet32 (PcdDeviceTreeAddress)) { - DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress))); + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *= )FixedPcdGet32 (PcdDeviceTreeAddress)))); // // Device tree address is pointed by PcdDeviceTreeAddress. // @@ -647,11 +647,10 @@ VOID EFIAPI SecCoreStartUpWithStack( // ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch); ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps; + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) { - - Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress (); if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart= \n")); ASSERT (FALSE); } DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1)); @@ -685,6 +684,11 @@ VOID EFIAPI SecCoreStartUpWithStack( NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, T= RUE); }; DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION_= _, HartId)); + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) { + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n")); + ASSERT (FALSE); + } + DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION_= _, HartId, Scratch->next_arg1)); NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, FAL= SE); // // Non boot hart wiil be halted waiting for SBI_HART_STARTING. diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 96087738a3..0fc7817665 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -37,14 +37,39 @@ ASM_FUNC (_ModuleEntryPoint) li a5, FixedPcdGet32 (PcdBootHartId) bne a6, a5, _wait_for_boot_hart =20 - li ra, 0 - call _reset_regs + /* + * Initial the hart count reported in DTB + */ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) =20 + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + /* Get the address of device tree and call generic fw_platform_init */ + call GetDeviceTreeAddress /* a0 return the device tree address */ + beqz a0, skip_fw_init + add a1, a0, 0 /* a1 is device tree */ + csrr a0, CSR_MHARTID /* a0 is boot hart ID */ + call fw_platform_init +skip_fw_init: /* Preload HART details - * s7 -> HART Count + * s7 -> Total HART count from PCD or DTB * s8 -> HART Stack Size */ - li s7, FixedPcdGet32 (PcdHartCount) + la a0, platform +#if __riscv_xlen =3D=3D 64 + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0) +#else + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0) +#endif + /* + * This is the number of HARTs described in + * DTB for this processor. We allocate the + * scratch buffer according to this number. + */ + la a4, _pysical_hart_count + sd s7, (a4) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) =20 /* @@ -113,20 +138,9 @@ _scratch_init: =20 li a4, FixedPcdGet32 (PcdTemporaryRamBase) li a5, FixedPcdGet32 (PcdTemporaryRamSize) - /* Use Temp memory as the stack for calling to C code */ add sp, a4, a5 - /* Get the address of device tree and call generic fw_platform_init */ - call GetDeviceTreeAddress /* a0 return the device tree address */ - beqz a0, skip_fw_init - add a1, a0, 0 /* a1 is device tree */ - csrr a0, CSR_MHARTID /* a0 is hart ID */ - call fw_platform_init -skip_fw_init: - /* Zero out temporary memory */ - li a4, FixedPcdGet32 (PcdTemporaryRamBase) - li a5, FixedPcdGet32 (PcdTemporaryRamSize) add a5, a4, a5 1: li a3, 0x0 @@ -167,7 +181,11 @@ _start_warm: li s7, FixedPcdGet32 (PcdBootableHartNumber) bnez s7, 1f la a4, platform - REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#if __riscv_xlen =3D=3D 64 + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#else + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) +#endif 1: li s8, FixedPcdGet32 (PcdOpenSbiStackSize) la a4, platform @@ -209,7 +227,8 @@ _start_warm: csrr a0, CSR_MHARTID j _uninitialized_hart_wait 4: - li s7, FixedPcdGet32 (PcdHartCount) + la a5, _pysical_hart_count + ld s7, (a5) /* Find the scratch space for this hart * * Scratch buffer is on the top of stack buffer @@ -275,6 +294,8 @@ _start_warm: .section .data, "aw" _boot_hart_done: RISCV_PTR 0 +_pysical_hart_count: + RISCV_PTR 0 =20 .align 3 .section .entry, "ax", %progbits @@ -293,7 +314,7 @@ _hartid_to_scratch: /* * s0 -> HART Stack Size * s1 -> HART Stack End - * s2 -> Temporary + * s2 -> Total hart count */ la s2, platform #if __riscv_xlen =3D=3D 64 @@ -301,8 +322,9 @@ _hartid_to_scratch: #else lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) #endif - li s2, FixedPcdGet32 (PcdHartCount) =20 + la s1, _pysical_hart_count /* total HART count */ + ld s2, (s1) mul s2, s2, s0 li s1, FixedPcdGet32 (PcdScratchRamBase) add s1, s1, s2 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82342): https://edk2.groups.io/g/devel/message/82342 Mute This Topic: https://groups.io/mt/86435699/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 16:47:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82343+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82343+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1634634542; cv=none; d=zohomail.com; s=zohoarc; b=iiw+iRkarTaVvMpUZfeNYkyAqYm82th5FgRoVJxe6OGi5ksFfR+Mux0s5ilePUre02XrqjXPDUM1u6ADjwNHBxAVAP1C5w17ZoRvRfIQgxt1PfyW4zCCMXQMg6qdisEQvZUk6eJjcQ2O+CQkx+DT8TtEyvvgtOSPlQg0k76bLbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634634542; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=gUkx5xHji990J3bg2jq9IIDguDIhUmNAlNRQMyfpw6A=; b=SDNJK3knAIT6QloEwEQ6quc3vJxdLkOSxyOSuE8tKqxp/NJGCYNiruGo2+4R0Sr6jD51EjFO9wdUUGDYrgv5fcsYWUePNBnPyGt+wD6PiO8IvPX2/H+LE2DSuc72D4nntOaEOsBJgGz0fSId6BQviPdZUfmztkqf6fLAwA8M11I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82343+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16346345426281010.312890903316; Tue, 19 Oct 2021 02:09:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id x51XYY1788612xYapFmzkNNl; Tue, 19 Oct 2021 02:09:02 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7409.1634634535322290786 for ; Tue, 19 Oct 2021 02:09:01 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J86JqT021896; Tue, 19 Oct 2021 09:08:55 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 3bst7b8g9v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:54 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 3FAD992; Tue, 19 Oct 2021 09:08:54 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 306EF48; Tue, 19 Oct 2021 09:08:53 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver Date: Tue, 19 Oct 2021 16:10:07 +0800 Message-Id: <20211019081007.31165-31-abner.chang@hpe.com> In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: L5TVtZ3J7t4i-VDXydlC_X2hekdoIare X-Proofpoint-GUID: L5TVtZ3J7t4i-VDXydlC_X2hekdoIare X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: rRTzogSUo8z2e3PJiehSOvM0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634634542; bh=/cevGV+0hnq9Ar7lB7xaSaIxmyXiTyjxEWqNN9KkecM=; h=Cc:Date:From:Reply-To:Subject:To; b=uFQ7hy43NraZCkAz6HqZGUmVtDFRgB5jrbiaqxXmrrhE42mdYrjLEP/pRAfx5X35pcP GyeaBR1pljO9W0n6i0OHhF9EYgdpJp5WXMGB/ea7wtV6LtiWqlfPoQ28W8v7UDJaxmnr5 KoTNb98qKk1u5SLCYrKphhjPpCItiN1ccl8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634634544576100001 Content-Type: text/plain; charset="utf-8" Add PCI CpuIo protocol to RISC-V. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 + .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 ++ .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 ++++++++++++++++++ 3 files changed, 602 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciC= puIo2Dxe.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciC= puIo2Dxe.c diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 3b5738957d..5c7425421b 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -105,3 +105,4 @@ Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf + Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dx= e.inf b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf new file mode 100644 index 0000000000..736143bf4c --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf @@ -0,0 +1,47 @@ +## @file +# Produces the CPU I/O 2 Protocol by using the services of the I/O Librar= y. +# +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# (C) Copyright 2021 Hewlett Packard Enterprise Development LP
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciCpuIo2Dxe + FILE_GUID =3D 4032D393-69E6-42BF-BBEA-08F3297374E8 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciCpuIo2Initialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + PciCpuIo2Dxe.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation + +[Protocols] + gEfiCpuIo2ProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dx= e.c b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c new file mode 100644 index 0000000000..03e3070682 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c @@ -0,0 +1,554 @@ +/** @file + Produces the CPU I/O 2 Protocol. + +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+(C) Copyright 2021 Hewlett Packard Enterprise Development LP
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle =3D NULL; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] =3D { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber of + bytes moved is Width size * Count, starting at= Address. + @param[in] Buffer For read operations, the destination buffer to= store the results. + For write operations, the source buffer from w= hich to write data. + + @retval EFI_SUCCESS The parameters for this request pass the = checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >=3D EfiCpuIoWidthFifoUint8 && Width <=3D EfiCpuIoWidthFifoUin= t64) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + return EFI_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the= maximum + // allowed address. The maximum address implied by the parameters passe= d in is + // Address + Size * Count. If the following condition is met, then the = transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all overflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count =3D=3D 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Reads memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + } + } + return EFI_SUCCESS; +} + +/** + Writes memory-mapped registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuMemoryServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + } + } + return EFI_SUCCESS; +} + +/** + Reads I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[out] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceRead ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + } + } + + return EFI_SUCCESS; +} + +/** + Write I/O registers. + + The I/O operations are carried out exactly as requested. The caller is r= esponsible + for satisfying any alignment and I/O width restrictions that a PI System= on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read= or + write operation is performed Count times from the first element of Buffe= r. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number= of + bytes moved is Width size * Count, starting at Addr= ess. + @param[in] Buffer For read operations, the destination buffer to stor= e the results. + For write operations, the source buffer from which = to write data. + + @retval EFI_SUCCESS The data was read from or written to the = PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +EFIAPI +CpuIoServiceWrite ( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + // + // Make sure the parameters are valid + // + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Address +=3D PcdGet64 (PcdPciIoTranslation); + + // + // Select loop based on the width of the transfer + // + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); + + for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) { + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + } + } + + return EFI_SUCCESS; +} + +// +// CPU I/O 2 Protocol instance +// +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { + { + CpuMemoryServiceRead, + CpuMemoryServiceWrite + }, + { + CpuIoServiceRead, + CpuIoServiceWrite + } +}; + + +/** + The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry po= int. + +**/ +EFI_STATUS +EFIAPI +PciCpuIo2Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mHandle, + &gEfiCpuIo2ProtocolGuid, &mCpuIo2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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