From nobody Fri Dec 19 20:52:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82293+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82293+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1634624436; cv=none; d=zohomail.com; s=zohoarc; b=LdFCOiFlT3sllyPCR3iFUe6gdLs1A252wjoldaqFmFMACkWRnvzk5KgfdT2lt0miHQ5ms8cj4EIlEJ/CYVLfGT+6STP8nVRaCjpF0EWQBSbs5qOl7OT9FfZKmAqASAF/x4soXVSj9SkKoImvcrmW+rh9U1OdwwSbyBhiyINw4Co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634624436; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1ghDRGH9k0oADWDd/HCLEccXcLHRKNxaiYjgJT+/9JU=; b=FE5F+4Ca9h5U+OkxEiN/G8KfGm1eK9BitvFWfBOB86QQL8U19SBwJzTKqmjPLL24loYzbTtlru1ndaelkv8T/CkuYI0tjh2yL7OiNr6TNEYxt4vXEDU+ZZE0obzvUO5ThTggaTOUXm/0NRCLc5OMBNneAJ54sOD2cJ/8lWBSuYw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82293+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634624436155950.0986913148297; Mon, 18 Oct 2021 23:20:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gY9kYY1788612xdzPF9A9htF; Mon, 18 Oct 2021 23:20:35 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.6133.1634624433123803422 for ; Mon, 18 Oct 2021 23:20:34 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10141"; a="314632451" X-IronPort-AV: E=Sophos;i="5.85,383,1624345200"; d="scan'208";a="314632451" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2021 23:20:34 -0700 X-IronPort-AV: E=Sophos;i="5.85,383,1624345200"; d="scan'208";a="566783118" X-Received: from gdong1-mobl1.amr.corp.intel.com ([10.213.170.103]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2021 23:20:32 -0700 From: "Guo Dong" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Maurice Ma , Benjamin You Subject: [edk2-devel] [`edk2-devel][PATCH V2 4/8] UefiPayloadPkg: Add SpiFlashLib Date: Mon, 18 Oct 2021 23:20:11 -0700 Message-Id: <20211019062015.1092-5-guo.dong@intel.com> In-Reply-To: <20211019062015.1092-1-guo.dong@intel.com> References: <20211019062015.1092-1-guo.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,guo.dong@intel.com X-Gm-Message-State: kEMYzwNxDh3e0vsYq3dW1IUxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634624435; bh=bEZ87NIl6rf4ImH4JNSSXVo/UKO8pdgs6dPFlkzBTo8=; h=Cc:Date:From:Reply-To:Subject:To; b=LdhLtlhaJARyN6K0r8n5XCbc4YgvFx2OVmhHRilO4Y593O5YW0QHXJPz+26AzPXLtab wUkstPIq+c+EZ2i7VElRuFzpl4UnS9mposXGMYXiXvGYuJQ8Uv1Pn+Ok6nKanW2ffEYsL Y+0oFLfJ1EDVZI9vJWQ2CgXCjk1pTiYrbss= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634625339578100002 Content-Type: text/plain; charset="utf-8" From: Guo Dong This is a common SPI Flash library used for the Intel platform that supports SPI hardware sequence. This library provides actual SPI flash operation via Intel PCH SPI controller. Signed-off-by: Guo Dong Cc: Ray Ni Cc: Maurice Ma Cc: Benjamin You Reviewed-by: Ray Ni Reviewed-by: Benjamin You --- .../Include/Guid/SpiFlashInfoGuid.h | 38 + UefiPayloadPkg/Include/Library/SpiFlashLib.h | 215 +++++ UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c | 173 ++++ UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h | 129 +++ .../Library/SpiFlashLib/SpiCommon.h | 208 +++++ .../Library/SpiFlashLib/SpiFlashLib.c | 857 ++++++++++++++++++ .../Library/SpiFlashLib/SpiFlashLib.inf | 48 + UefiPayloadPkg/UefiPayloadPkg.dec | 1 + 8 files changed, 1669 insertions(+) create mode 100644 UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h create mode 100644 UefiPayloadPkg/Include/Library/SpiFlashLib.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf diff --git a/UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h b/UefiPayloadPk= g/Include/Guid/SpiFlashInfoGuid.h new file mode 100644 index 0000000000..6241463007 --- /dev/null +++ b/UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h @@ -0,0 +1,38 @@ +/** @file + This file defines the hob structure for the SPI flash variable info. + + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_FLASH_INFO_GUID_H_ +#define SPI_FLASH_INFO_GUID_H_ + +#include +// +// SPI Flash infor hob GUID +// +extern EFI_GUID gSpiFlashInfoGuid; + +// +// Set this bit if platform need disable SMM write protection when writing= flash +// in SMM mode using this method: -- AsmWriteMsr32 (0x1FE, MmioRead32 (0x= FED30880) | BIT0); +// +#define FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT BIT0 + +// +// Reuse ACPI definition +// +typedef EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE PLD_GENERIC_ADDRESS; +#define SPACE_ID_PCI_CONFIGURATION EFI_ACPI_3_0_PCI_CONFIGURA= TION_SPACE +#define REGISTER_BIT_WIDTH_DWORD EFI_ACPI_3_0_DWORD + +typedef struct { + UINT8 Revision; + UINT8 Reserved; + UINT16 Flags; + PLD_GENERIC_ADDRESS SpiAddress; +} SPI_FLASH_INFO; + +#endif diff --git a/UefiPayloadPkg/Include/Library/SpiFlashLib.h b/UefiPayloadPkg/= Include/Library/SpiFlashLib.h new file mode 100644 index 0000000000..59840afb70 --- /dev/null +++ b/UefiPayloadPkg/Include/Library/SpiFlashLib.h @@ -0,0 +1,215 @@ +/** @file + PCH SPI Common Driver implements the SPI Host Controller Compatibility I= nterface. + + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_FLASH_LIB_H_ +#define SPI_FLASH_LIB_H_ + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +/** + Read SFDP data from the flash part. + + @param[in] ComponentNumber The Component Number for chip select + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle, the max number is 64 + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadSfdp ( + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] ComponentNumber The Component Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadJedecId ( + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashWriteStatus ( + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadStatus ( + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Read SC Soft Strap Values + + @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining SC Soft Strap Value. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiReadPchSoftStrap ( + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT UINT8 *SoftStrapValue + ); + + +/** + Read data from the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashErase ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Write data to the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Initialize an SPI library. + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_NOT_FOUND The expected SPI info could not be found +**/ +EFI_STATUS +EFIAPI +SpiConstructor ( + VOID + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiGetRegionAddress ( + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, OPTIONAL + OUT UINT32 *RegionSize OPTIONAL + ); + +#endif + diff --git a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c b/UefiPayloadPkg/L= ibrary/SpiFlashLib/PchSpi.c new file mode 100644 index 0000000000..1dafce19cb --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c @@ -0,0 +1,173 @@ +/** @file + + Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "SpiCommon.h" + +/** + Acquire SPI MMIO BAR. + + @param[in] PchSpiBase PCH SPI PCI Base Address + + @retval Return SPI BAR Address + +**/ +UINT32 +AcquireSpiBar0 ( + IN UINTN PchSpiBase + ) +{ + return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK); +} + +/** + Release SPI MMIO BAR. Do nothing. + + @param[in] PchSpiBase PCH SPI PCI Base Address + +**/ +VOID +ReleaseSpiBar0 ( + IN UINTN PchSpiBase + ) +{ +} + + + +/** + This function is to enable/disable BIOS Write Protect in SMM phase. + + @param[in] EnableSmmSts Flag to Enable/disable Bios write protect + +**/ +VOID +CpuSmmDisableBiosWriteProtect ( + IN BOOLEAN EnableSmmSts + ) +{ + UINT32 Data32; + + if(EnableSmmSts){ + // + // Disable BIOS Write Protect in SMM phase. + // + Data32 =3D MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0); + AsmWriteMsr32 (0x000001FE, Data32); + } else { + // + // Enable BIOS Write Protect in SMM phase + // + Data32 =3D MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0); + AsmWriteMsr32 (0x000001FE, Data32); + } + + // + // Read FED30880h back to ensure the setting went through. + // + Data32 =3D MmioRead32 (0xFED30880); +} + + +/** + This function is a hook for Spi to disable BIOS Write Protect. + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + IN UINTN PchSpiBase, + IN UINT8 CpuSmmBwp + ) +{ + + // + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. + // + MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8)); + + // + // Enable the access to the BIOS space for both read and write cycles + // + MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE); + + if (CpuSmmBwp !=3D 0) { + CpuSmmDisableBiosWriteProtect (TRUE); + } + + return EFI_SUCCESS; +} + +/** + This function is a hook for Spi to enable BIOS Write Protect. + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + IN UINTN PchSpiBase, + IN UINT8 CpuSmmBwp + ) +{ + + // + // Disable the access to the BIOS space for write cycles + // + MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE)); + + if (CpuSmmBwp !=3D 0) { + CpuSmmDisableBiosWriteProtect (FALSE); + } +} + +/** + This function disables SPI Prefetching and caching, + and returns previous BIOS Control Register value before disabling. + + @param[in] PchSpiBase PCH SPI PCI Base Address + + @retval Previous BIOS Control Register value + +**/ +UINT8 +SaveAndDisableSpiPrefetchCache ( + IN UINTN PchSpiBase + ) +{ + UINT8 BiosCtlSave; + + BiosCtlSave =3D MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC; + + MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \ + (UINT32) (~B_SPI_BCR_SRC), \ + (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)); + + return BiosCtlSave; +} + +/** + This function updates BIOS Control Register with the given value. + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] BiosCtlValue BIOS Control Register Value to be updated + +**/ +VOID +SetSpiBiosControlRegister ( + IN UINTN PchSpiBase, + IN UINT8 BiosCtlValue + ) +{ + MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlV= alue); +} diff --git a/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h b/UefiPayloadPkg/= Library/SpiFlashLib/RegsSpi.h new file mode 100644 index 0000000000..5f22623675 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h @@ -0,0 +1,129 @@ +/** @file + Register names for SPI device. + + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef REGS_SPI_H_ +#define REGS_SPI_H_ + +#define R_SPI_BASE 0x10 ///< 32-bit Memory = Base Address Register +#define B_SPI_BAR0_MASK 0x0FFF +#define R_SPI_BCR 0xDC ///< BIOS Control = Register +#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Confi= guration (SRC) +#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disab= le, Cache Disable +#define B_SPI_BCR_SYNC_SS BIT8 +#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect = Disable (WPD) + +/// +/// SPI Host Interface Registers +#define R_SPI_HSFS 0x04 ///< Hardware Seque= ncing Flash Status and Control Register(32bits) +#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byt= e Count ( <=3D 64), Count =3D (Value in this field) + 1. +#define N_SPI_HSFS_FDBC 24 +#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle. +#define N_SPI_HSFS_CYCLE 17 +#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Re= ad +#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Wr= ite +#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K= Block Erase +#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64= K Sector Erase +#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Re= ad SFDP +#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Re= ad JEDEC ID +#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Wr= ite Status +#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Re= ad Status +#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go. +#define B_SPI_HSFS_FDV BIT14 ///< Flash Descript= or Valid +#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in P= rogress +#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Er= ror +#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Do= ne + + +#define R_SPI_FADDR 0x08 ///< SPI Flash Address +#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address= Mask (0~26bit) + + +#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits) + +#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Acce= ss Permissions Register +#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for= Region4 PlatformData +#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for= Region3 GbE +#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access fo= r Region2 SEC +#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access fo= r Region1 BIOS +#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access fo= r Region0 Flash Descriptor +#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read acces= s for Region4 PlatformData +#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read acces= s for Region3 GbE +#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Acces= s for Region2 SEC +#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Acces= s for Region1 BIOS +#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Acces= s for Region0 Flash Descriptor + + +#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (F= lash Descriptor) (32bits) +#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12] +#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12] +#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12] +#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2] + +#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (B= IOS) (32bits) +#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12] +#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12] +#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12] +#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2] + +#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (S= EC) (32bits) +#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12] +#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifi= es address bits [26:12] +#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12] +#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifie= s address bits [26:2] + +#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE= )(32bits) +#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12] +#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifi= es address bits [26:12] +#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12] +#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifie= s address bits [26:2] + +#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (P= latform Data) (32bits) +#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12] +#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12] +#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12] +#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2] + + +#define S_SPI_FREGX 4 ///< Size of Flash Reg= ion register +#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limi= t [30:16] represents [26:12], [11:0] are assumed to be FFFh +#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit = position +#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit = represents position +#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base= , [14:0] represents [26:12] + + +#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Obser= vability Control Register (32 bits) +#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flas= h Descriptor Section Select +#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and D= escriptor Map +#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component +#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Sect= ion Index + +#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Obser= vability Data Register (32 bits) + + +#define R_SPI_LVSCC 0xC4 /// + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SPI_COMMON_LIB_H_ +#define SPI_COMMON_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "RegsSpi.h" + +/// +/// Maximum time allowed while waiting the SPI cycle to complete +/// Wait Time =3D 6 seconds =3D 6000000 microseconds +/// Wait Period =3D 10 microseconds +/// +#define WAIT_TIME 6000000 ///< Wait Time =3D 6 seconds =3D 6000000 m= icroseconds +#define WAIT_PERIOD 10 ///< Wait Period =3D 10 microseconds + +/// +/// Flash cycle Type +/// +typedef enum { + FlashCycleRead, + FlashCycleWrite, + FlashCycleErase, + FlashCycleReadSfdp, + FlashCycleReadJedecId, + FlashCycleWriteStatus, + FlashCycleReadStatus, + FlashCycleMax +} FLASH_CYCLE_TYPE; + +/// +/// Flash Component Number +/// +typedef enum { + FlashComponent0, + FlashComponent1, + FlashComponentMax +} FLASH_COMPONENT_NUM; + +/// +/// Private data structure definitions for the driver +/// +#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + UINT32 AcpiTmrReg; + UINTN PchSpiBase; + UINT16 RegionPermission; + UINT32 SfdpVscc0Value; + UINT32 SfdpVscc1Value; + UINT32 StrapBaseAddress; + UINT8 NumberOfComponents; + UINT16 Flags; + UINT32 Component1StartAddr; +} SPI_INSTANCE; + + +/** + Acquire SPI MMIO BAR + + @param[in] PchSpiBase PCH SPI PCI Base Address + + @retval Return SPI BAR Address + +**/ +UINT32 +AcquireSpiBar0 ( + IN UINTN PchSpiBase + ); + + +/** + Release SPI MMIO BAR. Do nothing. + + @param[in] PchSpiBase PCH SPI PCI Base Address + + @retval None + +**/ +VOID +ReleaseSpiBar0 ( + IN UINTN PchSpiBase + ); + + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + IN UINTN PchSpiBase, + IN UINT8 CpuSmmBwp + ); + +/** + This function is a hook for Spi to enable BIOS Write Protect + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not + + @retval None + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + IN UINTN PchSpiBase, + IN UINT8 CpuSmmBwp + ); + + +/** + This function disables SPI Prefetching and caching, + and returns previous BIOS Control Register value before disabling. + + @param[in] PchSpiBase PCH SPI PCI Base Address + + @retval Previous BIOS Control Register value + +**/ +UINT8 +SaveAndDisableSpiPrefetchCache ( + IN UINTN PchSpiBase + ); + +/** + This function updates BIOS Control Register with the given value. + + @param[in] PchSpiBase PCH SPI PCI Base Address + @param[in] BiosCtlValue BIOS Control Register Value to be updated + + @retval None + +**/ +VOID +SetSpiBiosControlRegister ( + IN UINTN PchSpiBase, + IN UINT8 BiosCtlValue + ); + + +/** + This function sends the programmed SPI command to the slave device. + + @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the data received or sent during the SPI cycle. + + @retval EFI_SUCCESS SPI command completes successfully. + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly. + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in= hardware sequencing mode + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. +**/ +EFI_STATUS +SendSpiCmd ( + IN FLASH_REGION_TYPE FlashRegionType, + IN FLASH_CYCLE_TYPE FlashCycleType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN OUT UINT8 *Buffer + ); + +/** + Wait execution cycle to complete on the SPI interface. + + @param[in] PchSpiBar0 Spi MMIO base address + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check + + @retval TRUE SPI cycle completed on the interface. + @retval FALSE Time out while waiting the SPI cycle to = complete. + It's not safe to program the next comman= d on the SPI interface. +**/ +BOOLEAN +WaitForSpiCycleComplete ( + IN UINT32 PchSpiBar0, + IN BOOLEAN ErrorCheck + ); + +#endif diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c b/UefiPayload= Pkg/Library/SpiFlashLib/SpiFlashLib.c new file mode 100644 index 0000000000..71dfcef740 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c @@ -0,0 +1,857 @@ +/** @file + Generic driver using Hardware Sequencing registers. + + Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "SpiCommon.h" + +SPI_INSTANCE *mSpiInstance =3D NULL; + +/** + Get SPI Instance from library global data.. + + @retval SpiInstance Return SPI instance +**/ +SPI_INSTANCE * +GetSpiInstance ( + VOID +) +{ + if (mSpiInstance =3D=3D NULL) { + mSpiInstance =3D AllocatePool (sizeof(SPI_INSTANCE)); + if (mSpiInstance =3D=3D NULL) { + return NULL; + } + ZeroMem (mSpiInstance, sizeof(SPI_INSTANCE)); + } + + return mSpiInstance; +} + + +/** + Initialize an SPI library. + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_NOT_FOUND The expected SPI info could not be found +**/ +EFI_STATUS +EFIAPI +SpiConstructor ( + VOID + ) +{ + UINT32 ScSpiBar0; + UINT8 Comp0Density; + SPI_INSTANCE *SpiInstance; + EFI_HOB_GUID_TYPE *GuidHob; + SPI_FLASH_INFO *SpiFlashInfo; + + // + // Find SPI flash hob + // + GuidHob =3D GetFirstGuidHob (&gSpiFlashInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + SpiFlashInfo =3D (SPI_FLASH_INFO *) GET_GUID_HOB_DATA (GuidHob); + + // + // Initialize the SPI instance + // + SpiInstance =3D GetSpiInstance (); + if (SpiInstance =3D=3D NULL) { + return EFI_NOT_FOUND; + } + DEBUG ((DEBUG_INFO, "SpiInstance =3D %08X\n", SpiInstance)); + + SpiInstance->Signature =3D SC_SPI_PRIVATE_DATA_SIGNATURE; + SpiInstance->Handle =3D NULL; + + // + // Check the SPI address + // + if ((SpiFlashInfo->SpiAddress.AddressSpaceId !=3D EFI_ACPI_3_0_PCI_CONF= IGURATION_SPACE) || + (SpiFlashInfo->SpiAddress.RegisterBitWidth !=3D 32) || + (SpiFlashInfo->SpiAddress.RegisterBitOffset !=3D 0) || + (SpiFlashInfo->SpiAddress.AccessSize !=3D EFI_ACPI_3_0_DWORD)){ + DEBUG ((DEBUG_ERROR, "SPI FLASH HOB is not expected. need check the ho= b or enhance SPI flash driver.\n")); + } + SpiInstance->PchSpiBase =3D (UINT32)(UINTN)SpiFlashInfo->SpiAddress.Addr= ess; + SpiInstance->Flags =3D SpiFlashInfo->Flags; + DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase)); + + ScSpiBar0 =3D AcquireSpiBar0 (SpiInstance->PchSpiBase); + DEBUG ((DEBUG_INFO, "ScSpiBar0 at 0x%08X\n", ScSpiBar0)); + + if (ScSpiBar0 =3D=3D 0) { + ASSERT (FALSE); + } + + if ((MmioRead32 (ScSpiBar0 + R_SPI_HSFS) & B_SPI_HSFS_FDV) =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "SPI Flash descriptor invalid, cannot use Hardwar= e Sequencing registers!\n")); + ASSERT (FALSE); + } + + MmioOr32 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_= MEMORY_SPACE); + SpiInstance->RegionPermission =3D MmioRead16 (ScSpiBar0 + R_SPI_FRAP); + SpiInstance->SfdpVscc0Value =3D MmioRead32 (ScSpiBar0 + R_SPI_LVSCC); + SpiInstance->SfdpVscc1Value =3D MmioRead32 (ScSpiBar0 + R_SPI_UVSCC); + + // + // Select to Flash Map 0 Register to get the number of flash Component + // + MmioAndThenOr32 ( + ScSpiBar0 + R_SPI_FDOC, + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0) + ); + + // + // Copy Zero based Number Of Components + // + SpiInstance->NumberOfComponents =3D (UINT8) ((MmioRead16 (ScSpiBar0 + R_= SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC); + + MmioAndThenOr32 ( + ScSpiBar0 + R_SPI_FDOC, + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP) + ); + + // + // Copy Component 0 Density + // + Comp0Density =3D (UINT8) MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLC= OMP_COMP1_MASK; + SpiInstance->Component1StartAddr =3D (UINT32) (SIZE_512KB << Comp0Densit= y); + + // + // Select FLASH_MAP1 to get Flash SC Strap Base Address + // + MmioAndThenOr32 ( + (ScSpiBar0 + R_SPI_FDOC), + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1) + ); + + SpiInstance->StrapBaseAddress =3D MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & = B_SPI_FDBAR_FPSBA; + + // + // Align FPSBA with address bits for the SC Strap portion of flash descr= iptor + // + SpiInstance->StrapBaseAddress &=3D B_SPI_FDBAR_FPSBA; + + return EFI_SUCCESS; +} + + +/** + Read data from the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the data received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + Status =3D SendSpiCmd (FlashRegionType, FlashCycleRead, Address, ByteCou= nt, Buffer); + return Status; +} + +/** + Write data to the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + Status =3D SendSpiCmd (FlashRegionType, FlashCycleWrite, Address, ByteCo= unt, Buffer); + return Status; +} + +/** + Erase some area on the flash part. + + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashErase ( + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ) +{ + EFI_STATUS Status; + + Status =3D SendSpiCmd (FlashRegionType, FlashCycleErase, Address, ByteCo= unt, NULL); + return Status; +} + +/** + Read SFDP data from the flash part. + + @param[in] ComponentNumber The Component Number for chip select + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle, the max number is 64 + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadSfdp ( + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ) +{ + EFI_STATUS Status; + UINT32 Address; + SPI_INSTANCE *SpiInstance; + + SpiInstance =3D GetSpiInstance (); + if (SpiInstance =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if ((ByteCount > 64) || (ComponentNumber > SpiInstance->NumberOfComponen= ts)) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Address =3D 0; + if (ComponentNumber =3D=3D FlashComponent1) { + Address =3D SpiInstance->Component1StartAddr; + } + + Status =3D SendSpiCmd (0, FlashCycleReadSfdp, Address, ByteCount, SfdpDa= ta); + return Status; +} + +/** + Read Jedec Id from the flash part. + + @param[in] ComponentNumber The Component Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadJedecId ( + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ) +{ + EFI_STATUS Status; + UINT32 Address; + SPI_INSTANCE *SpiInstance; + + SpiInstance =3D GetSpiInstance (); + if (SpiInstance =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if (ComponentNumber > SpiInstance->NumberOfComponents) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Address =3D 0; + if (ComponentNumber =3D=3D FlashComponent1) { + Address =3D SpiInstance->Component1StartAddr; + } + + Status =3D SendSpiCmd (0, FlashCycleReadJedecId, Address, ByteCount, Jed= ecId); + return Status; +} + +/** + Write the status register in the flash part. + + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashWriteStatus ( + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ) +{ + EFI_STATUS Status; + + Status =3D SendSpiCmd (0, FlashCycleWriteStatus, 0, ByteCount, StatusVal= ue); + return Status; +} + +/** + Read status register in the flash part. + + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiFlashReadStatus ( + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ) +{ + EFI_STATUS Status; + + Status =3D SendSpiCmd (0, FlashCycleReadStatus, 0, ByteCount, StatusValu= e); + return Status; +} + +/** + Read SC Soft Strap Values + + @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining SC Soft Strap Value. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiReadPchSoftStrap ( + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT UINT8 *SoftStrapValue + ) +{ + UINT32 StrapFlashAddr; + EFI_STATUS Status; + SPI_INSTANCE *SpiInstance; + + SpiInstance =3D GetSpiInstance (); + if (SpiInstance =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + ASSERT (SpiInstance->StrapBaseAddress !=3D 0); + // + // SC Strap Flash Address =3D FPSBA + RamAddr + // + StrapFlashAddr =3D SpiInstance->StrapBaseAddress + SoftStrapAddr; + + Status =3D SendSpiCmd (FlashRegionDescriptor, FlashCycleRead, StrapFlash= Addr, ByteCount, SoftStrapValue); + return Status; +} + +/** + This function sends the programmed SPI command to the slave device. + + @param[in] FlashRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the data received or sent during the SPI cycle. + + @retval EFI_SUCCESS SPI command completes successfully. + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly. + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in= hardware sequencing mode + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. +**/ +EFI_STATUS +SendSpiCmd ( + IN FLASH_REGION_TYPE FlashRegionType, + IN FLASH_CYCLE_TYPE FlashCycleType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINT32 Index; + UINTN SpiBaseAddress; + UINT32 ScSpiBar0; + UINT32 LimitAddress; + UINT32 HardwareSpiAddr; + UINT16 PermissionBit; + UINT32 SpiDataCount; + UINT32 FlashCycle; + UINT8 BiosCtlSave; + SPI_INSTANCE *SpiInstance; + UINT32 Data32; + + SpiInstance =3D GetSpiInstance (); + if (SpiInstance =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + Status =3D EFI_SUCCESS; + SpiBaseAddress =3D SpiInstance->PchSpiBase; + ScSpiBar0 =3D AcquireSpiBar0 (SpiBaseAddress); + BiosCtlSave =3D 0; + SpiInstance->RegionPermission =3D MmioRead16 (ScSpiBar0 + R_SPI_FRAP); + + // + // If it's write cycle, disable Prefetching, Caching and disable BIOS Wr= ite Protect + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D Fl= ashCycleErase)) { + Status =3D DisableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flag= s & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT); + if (EFI_ERROR (Status)) { + goto SendSpiCmdEnd; + } + BiosCtlSave =3D SaveAndDisableSpiPrefetchCache (SpiBaseAddress); + } + + // + // Make sure it's safe to program the command. + // + if (!WaitForSpiCycleComplete (ScSpiBar0, FALSE)) { + Status =3D EFI_DEVICE_ERROR; + goto SendSpiCmdEnd; + } + + HardwareSpiAddr =3D Address; + if ((FlashCycleType =3D=3D FlashCycleRead) || + (FlashCycleType =3D=3D FlashCycleWrite) || + (FlashCycleType =3D=3D FlashCycleErase)) { + + switch (FlashRegionType) { + case FlashRegionDescriptor: + if (FlashCycleType =3D=3D FlashCycleRead) { + PermissionBit =3D B_SPI_FRAP_BRRA_FLASHD; + } else { + PermissionBit =3D B_SPI_FRAP_BRWA_FLASHD; + } + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD); + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0= _BASE; + LimitAddress =3D (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG= 0_LIMIT; + break; + + case FlashRegionBios: + if (FlashCycleType =3D=3D FlashCycleRead) { + PermissionBit =3D B_SPI_FRAP_BRRA_BIOS; + } else { + PermissionBit =3D B_SPI_FRAP_BRWA_BIOS; + } + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS); + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1= _BASE; + LimitAddress =3D (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG= 1_LIMIT; + break; + + case FlashRegionMe: + if (FlashCycleType =3D=3D FlashCycleRead) { + PermissionBit =3D B_SPI_FRAP_BRRA_SEC; + } else { + PermissionBit =3D B_SPI_FRAP_BRWA_SEC; + } + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC); + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2= _BASE; + LimitAddress =3D (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG= 2_LIMIT; + break; + + case FlashRegionGbE: + if (FlashCycleType =3D=3D FlashCycleRead) { + PermissionBit =3D B_SPI_FRAP_BRRA_GBE; + } else { + PermissionBit =3D B_SPI_FRAP_BRWA_GBE; + } + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE); + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3= _BASE; + LimitAddress =3D (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG= 3_LIMIT; + break; + + case FlashRegionPlatformData: + if (FlashCycleType =3D=3D FlashCycleRead) { + PermissionBit =3D B_SPI_FRAP_BRRA_PLATFORM; + } else { + PermissionBit =3D B_SPI_FRAP_BRWA_PLATFORM; + } + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA); + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4= _BASE; + LimitAddress =3D (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG= 4_LIMIT; + break; + + case FlashRegionAll: + // + // FlashRegionAll indicates address is relative to flash device + // No error checking for this case + // + LimitAddress =3D 0; + PermissionBit =3D 0; + break; + + default: + Status =3D EFI_UNSUPPORTED; + goto SendSpiCmdEnd; + } + + if ((LimitAddress !=3D 0) && (Address > LimitAddress)) { + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + } + + // + // If the operation is read, but the region attribute is not read allo= wed, return error. + // If the operation is write, but the region attribute is not write al= lowed, return error. + // + if ((PermissionBit !=3D 0) && ((SpiInstance->RegionPermission & Permis= sionBit) =3D=3D 0)) { + Status =3D EFI_ACCESS_DENIED; + goto SendSpiCmdEnd; + } + } + + // + // Check for SC SPI hardware sequencing required commands + // + FlashCycle =3D 0; + switch (FlashCycleType) { + case FlashCycleRead: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE); + break; + + case FlashCycleWrite: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE); + break; + + case FlashCycleErase: + if (((ByteCount % SIZE_4KB) !=3D 0) || ((HardwareSpiAddr % SIZE_4KB) != =3D 0)) { + DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n")= ); + ASSERT (FALSE); + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + } + break; + + case FlashCycleReadSfdp: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCL= E); + break; + + case FlashCycleReadJedecId: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_= CYCLE); + break; + + case FlashCycleWriteStatus: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_C= YCLE); + break; + + case FlashCycleReadStatus: + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CY= CLE); + break; + + default: + // + // Unrecognized Operation + // + ASSERT (FALSE); + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + break; + } + + do { + SpiDataCount =3D ByteCount; + if ((FlashCycleType =3D=3D FlashCycleRead) || (FlashCycleType =3D=3D F= lashCycleWrite)) { + // + // Trim at 256 byte boundary per operation, + // - SC SPI controller requires trimming at 4KB boundary + // - Some SPI chips require trimming at 256 byte boundary for write = operation + // - Trimming has limited performance impact as we can read / write = at most 64 byte + // per operation + // + if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 = - 1))) { + SpiDataCount =3D (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)= ) - (UINT32) (HardwareSpiAddr); + } + // + // Calculate the number of bytes to shift in/out during the SPI data= cycle. + // Valid settings for the number of bytes during each data portion o= f the + // SC SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48,= 56, 64 + // + if (SpiDataCount >=3D 64) { + SpiDataCount =3D 64; + } else if ((SpiDataCount &~0x07) !=3D 0) { + SpiDataCount =3D SpiDataCount &~0x07; + } + } + + if (FlashCycleType =3D=3D FlashCycleErase) { + if (((ByteCount / SIZE_64KB) !=3D 0) && + ((ByteCount % SIZE_64KB) =3D=3D 0) && + ((HardwareSpiAddr % SIZE_64KB) =3D=3D 0)) { + if (HardwareSpiAddr < SpiInstance->Component1StartAddr) { + // + // Check whether Component0 support 64k Erase + // + if ((SpiInstance->SfdpVscc0Value & B_SPI_LVSCC_EO_64K) !=3D 0) { + SpiDataCount =3D SIZE_64KB; + } else { + SpiDataCount =3D SIZE_4KB; + } + } else { + // + // Check whether Component1 support 64k Erase + // + if ((SpiInstance->SfdpVscc1Value & B_SPI_LVSCC_EO_64K) !=3D 0) { + SpiDataCount =3D SIZE_64KB; + } else { + SpiDataCount =3D SIZE_4KB; + } + } + } else { + SpiDataCount =3D SIZE_4KB; + } + if (SpiDataCount =3D=3D SIZE_4KB) { + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_C= YCLE); + } else { + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_= CYCLE); + } + } + + // + // If it's write cycle, load data into the SPI data buffer. + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D = FlashCycleWriteStatus)) { + if ((SpiDataCount & 0x07) !=3D 0) { + // + // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7 + // + for (Index =3D 0; Index < SpiDataCount; Index++) { + MmioWrite8 (ScSpiBar0 + R_SPI_FDATA00 + Index, Buffer[Index]); + } + } else { + // + // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64 + // + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) { + MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *) (Buf= fer + Index)); + } + } + } + + // + // Set the Flash Address + // + MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32) (HardwareSpiAddr & B_SP= I_FADDR_MASK)); + + // + // Set Data count, Flash cycle, and Set Go bit to start a cycle + // + MmioAndThenOr32 ( + ScSpiBar0 + R_SPI_HSFS, + (UINT32) (~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)), + (UINT32) (((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_S= PI_HSFS_CYCLE_FGO) + ); + + // + // Wait for command execution complete. + // + if (!WaitForSpiCycleComplete (ScSpiBar0, TRUE)) { + Status =3D EFI_DEVICE_ERROR; + goto SendSpiCmdEnd; + } + + // + // If it's read cycle, load data into the caller's buffer. + // + if ((FlashCycleType =3D=3D FlashCycleRead) || + (FlashCycleType =3D=3D FlashCycleReadSfdp) || + (FlashCycleType =3D=3D FlashCycleReadJedecId) || + (FlashCycleType =3D=3D FlashCycleReadStatus)) { + if ((SpiDataCount & 0x07) !=3D 0) { + // + // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7 + // + for (Index =3D 0; Index < SpiDataCount; Index++) { + Buffer[Index] =3D MmioRead8 (ScSpiBar0 + R_SPI_FDATA00 + Index); + } + } else { + // + // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64 + // + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) { + *(UINT32 *) (Buffer + Index) =3D MmioRead32 (ScSpiBar0 + R_SPI_F= DATA00 + Index); + } + } + } + + HardwareSpiAddr +=3D SpiDataCount; + Buffer +=3D SpiDataCount; + ByteCount -=3D SpiDataCount; + } while (ByteCount > 0); + +SendSpiCmdEnd: + /// + /// Restore the settings for SPI Prefetching and Caching and enable BIOS= Write Protect + /// + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D Fl= ashCycleErase)) { + EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_S= PI_DISABLE_SMM_WRITE_PROTECT); + SetSpiBiosControlRegister (SpiBaseAddress, BiosCtlSave); + } + + ReleaseSpiBar0 (SpiBaseAddress); + + return Status; +} + +/** + Wait execution cycle to complete on the SPI interface. + + @param[in] ScSpiBar0 Spi MMIO base address + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check + + @retval TRUE SPI cycle completed on the interface. + @retval FALSE Time out while waiting the SPI cycle to = complete. + It's not safe to program the next comman= d on the SPI interface. +**/ +BOOLEAN +WaitForSpiCycleComplete ( + IN UINT32 ScSpiBar0, + IN BOOLEAN ErrorCheck + ) +{ + UINT64 WaitTicks; + UINT64 WaitCount; + UINT32 Data32; + + // + // Convert the wait period allowed into to tick count + // + WaitCount =3D WAIT_TIME / WAIT_PERIOD; + // + // Wait for the SPI cycle to complete. + // + for (WaitTicks =3D 0; WaitTicks < WaitCount; WaitTicks++) { + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_HSFS); + if ((Data32 & B_SPI_HSFS_SCIP) =3D=3D 0) { + MmioWrite32 (ScSpiBar0 + R_SPI_HSFS, B_SPI_HSFS_FCERR | B_SPI_HSFS_F= DONE); + if (((Data32 & B_SPI_HSFS_FCERR) !=3D 0) && ErrorCheck) { + return FALSE; + } else { + return TRUE; + } + } + MicroSecondDelay ( WAIT_PERIOD); + } + return FALSE; +} + +/** + Get the SPI region base and size, based on the enum type + + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiGetRegionAddress ( + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, OPTIONAL + OUT UINT32 *RegionSize OPTIONAL + ) +{ + UINT32 ScSpiBar0; + UINT32 ReadValue; + UINT32 Base; + SPI_INSTANCE *SpiInstance; + + if (FlashRegionType >=3D FlashRegionMax) { + return EFI_INVALID_PARAMETER; + } + + SpiInstance =3D GetSpiInstance(); + if (SpiInstance =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + if (FlashRegionType =3D=3D FlashRegionAll) { + if (BaseAddress !=3D NULL) { + *BaseAddress =3D 0; + } + if (RegionSize !=3D NULL) { + *RegionSize =3D SpiInstance->Component1StartAddr; + } + return EFI_SUCCESS; + } + + ScSpiBar0 =3D AcquireSpiBar0 (SpiInstance->PchSpiBase); + ReadValue =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX *= (UINT32) FlashRegionType); + ReleaseSpiBar0 (SpiInstance->PchSpiBase); + + // + // If the region is not used, the Region Base is 7FFFh and Region Limit = is 0000h + // + if (ReadValue =3D=3D B_SPI_FREGX_BASE_MASK) { + return EFI_DEVICE_ERROR; + } + + Base =3D (ReadValue & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE; + if (BaseAddress !=3D NULL) { + *BaseAddress =3D Base; + } + + if (RegionSize !=3D NULL) { + *RegionSize =3D ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREG= X_LIMIT) + 1) << + N_SPI_FREGX_LIMIT_REPR) - Base; + } + + return EFI_SUCCESS; +} + diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf b/UefiPaylo= adPkg/Library/SpiFlashLib/SpiFlashLib.inf new file mode 100644 index 0000000000..3e023079fc --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf @@ -0,0 +1,48 @@ +## @file +# Library instance for SPI flash library using SPI hardware sequence +# +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SpiFlashLib + FILE_GUID =3D 6F96AFCB-DE89-4ca1-A63F-8703EE8FDE50 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SpiFlashLib + CONSTRUCTOR =3D SpiConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + RegsSpi.h + SpiCommon.h + PchSpi.c + SpiFlashLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiPayloadPkg/UefiPayloadPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + IoLib + PciLib + HobLib + TimerLib + BaseLib + +[Guids] + gSpiFlashInfoGuid + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayload= Pkg.dec index 4c3bd0c2eb..3ffdce550d 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dec +++ b/UefiPayloadPkg/UefiPayloadPkg.dec @@ -37,6 +37,7 @@ gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98,= 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } } gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,= 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } } =20 + gSpiFlashInfoGuid =3D { 0x2d4aac1b, 0x91a5, 0x4cd5, { 0x9b, 0x5c,= 0xb4, 0x0f, 0x5d, 0x28, 0x51, 0xa1 } } gSmmRegisterInfoGuid =3D { 0xaa9bd7a7, 0xcafb, 0x4499, { 0xa4, 0xa9,= 0xb, 0x34, 0x6b, 0x40, 0xa6, 0x22 } } gS3CommunicationGuid =3D { 0x88e31ba1, 0x1856, 0x4b8b, { 0xbb, 0xdf,= 0xf8, 0x16, 0xdd, 0x94, 0xa, 0xef } } =20 --=20 2.32.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82293): https://edk2.groups.io/g/devel/message/82293 Mute This Topic: https://groups.io/mt/86433936/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-