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Tue, 19 Oct 2021 03:49:19 +0000 From: "Daniel Schaefer" To: CC: Abner Chang , Sunil V L , Daniel Schaefer Subject: [edk2-devel] [edk2-platforms] [PATCH v3 04/14] Silicon/RISC-V: Introduce FirmwareContext library Date: Tue, 19 Oct 2021 11:48:39 +0800 Message-ID: <20211019034849.16847-5-daniel.schaefer@hpe.com> In-Reply-To: <20211019034849.16847-1-daniel.schaefer@hpe.com> References: <20211019034849.16847-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: SG2PR03CA0134.apcprd03.prod.outlook.com (2603:1096:4:c8::7) To DF4PR8401MB0923.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760f::13) MIME-Version: 1.0 X-Received: from zbook-nix.wireless.hpe.com (15.211.146.34) by SG2PR03CA0134.apcprd03.prod.outlook.com (2603:1096:4:c8::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.11 via Frontend Transport; Tue, 19 Oct 2021 03:49:17 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 858e30df-2186-4705-ceea-08d992b36dde X-MS-TrafficTypeDiagnostic: DF4PR8401MB1321: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1824; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: X6bVODeUvx7UqYCQRJ6hDZDXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634615375; bh=5kg/mzOMnN2k1203BykPzkTbrDMLaV0XWbW6sR2mRpo=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Gn0htX7485xYAKNfUy2n/KAqoFGhMbpQvZliMaEr/NCjIXi6gwG78UH58gmEYOZeRyF zbqM8VOeXRu3wf1F0r7WHdtnhbRIu4SxDyI//ZwpBKYT2xa6y/e+UCuI9tYYE4gQ5TBoB ijDnXx6T2ngusZFRwu+D9zXpWqHXWHL7xdA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634615377032100009 Content-Type: text/plain; charset="utf-8" From: Abner Chang Add RISC-V FirmwareContext library for different FirmwareContext implementations. This instance uses SBI firmware extension to get the pointer to FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Reviewed-by: Abner Chang Reviewed-by: Daniel Schaefer Signed-off-by: Abner Chang --- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec = | 1 + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc = | 4 +- Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwa= reContextSbiLib.inf | 34 +++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVF= irmwareContextSscratchLib.inf | 33 +++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirm= wareContextStvecLib.inf | 34 +++++++++++++ Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h = | 3 +- Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h = | 14 +++++- Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h = | 43 ++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwa= reContextSbiLib.c | 52 ++++++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVF= irmwareContextSscratchLib.c | 48 ++++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirm= wareContextStvecLib.c | 48 ++++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S = | 34 ++++++++++++- 12 files changed, 344 insertions(+), 4 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dec index 0b64b33f0fba..08279a97b1c5 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec @@ -24,6 +24,7 @@ RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h RiscVCpuLib|Include/Library/RiscVCpuLib.h RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h + RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h =20 [Guids] gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 5c5cfcb525ca..1292ba1beab7 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -65,13 +65,14 @@ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformT= imerLibNull/RiscVPlatformTimerLib.inf - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf =20 [LibraryClasses.common.PEI_CORE] PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf + RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf =20 [LibraryClasses.common.PEIM] PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf + RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf @@ -92,6 +93,7 @@ [Components] Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandle= rDxeLib.inf + Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirm= wareContextSbiLib.inf Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/Pe= iServicesTablePointerLibOpenSbi.inf Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatf= ormTimerLib.inf diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscV= FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf new file mode 100644 index 000000000000..168b70545390 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf @@ -0,0 +1,34 @@ +## @file +# Instance of OpebSBI Firmware Conext Library +# +# This iinstance uses RISC-V OpenSBI Firmware Extension SBI. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVFirmwareContextSbiLib + FILE_GUID =3D 3709E048-6794-427A-B728-BFE3FFD6D461 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Sources] + RiscVFirmwareContextSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVEdk2SbiLib + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Lib= rary/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf new file mode 100644 index 000000000000..750c1cf51ffa --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.inf @@ -0,0 +1,33 @@ +## @file +# Instance of OpebSBI Firmware Conext Library +# +# This instance uses RISC-V Supervisor mode SCRATCH CSR +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVFirmwareContextSscratchLib + FILE_GUID =3D 3709E048-6794-427A-B728-BFE3FFD6D461 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Sources] + RiscVFirmwareContextSscratchLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/R= iscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf new file mode 100644 index 000000000000..fa894cda9164 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.inf @@ -0,0 +1,34 @@ +## @file +# Instance of OpebSBI Firmware Conext Library +# +# This iinstance Supervisor mode STVEC CSR +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVFirmwareContextStvecLib + FILE_GUID =3D 42DCFFAC-1DBD-4264-80A3-85CC7167AC82 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Sources] + RiscVFirmwareContextStvecLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + + diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index 2a992394edbb..f6726bda240b 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -1,7 +1,7 @@ /** @file RISC-V package definitions. =20 - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -96,6 +96,7 @@ #define SSTATUS_SIE_BIT_POSITION 1 #define SSTATUS_SPP_BIT_POSITION 8 #define RISCV_CSR_SUPERVISOR_SIE 0x104 +#define RISCV_CSR_SUPERVISOR_STVEC 0x105 #define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140 #define RISCV_CSR_SUPERVISOR_SEPC 0x141 #define RISCV_CSR_SUPERVISOR_SCAUSE 0x142 diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index f37d4c20d068..f70723567e22 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -1,7 +1,7 @@ /** @file RISC-V CPU library definitions. =20 - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID); VOID RiscVSetSupervisorAddressTranslationRegister(UINT64); =20 +VOID +RiscVSetSupervisorScratch (UINT64); + +UINT64 +RiscVGetSupervisorScratch (VOID); + +VOID +RiscVSetSupervisorStvec (UINT64); + +UINT64 +RiscVGetSupervisorStvec (VOID); + #endif diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareConte= xtLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextL= ib.h new file mode 100644 index 000000000000..f35c4e0c5123 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h @@ -0,0 +1,43 @@ +/** @file + Library to get/set Firmware Context. + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_ +#define RISCV_FIRMWARE_CONTEXT_LIB_H_ + +#include +#include + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +#endif diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFi= rmwareContextSbiLib/RiscVFirmwareContextSbiLib.c new file mode 100644 index 000000000000..6125618eaf4d --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.c @@ -0,0 +1,52 @@ +/** @file + This iinstance uses RISC-V OpenSBI Firmware Extension SBI to + get the pointer of firmware context. + + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + SbiGetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + // + // We don't have to set firmware context pointer using + // OpenSBI FW Extension SBI. + // +} + diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Libra= ry/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c new file mode 100644 index 000000000000..2504e17132c4 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.c @@ -0,0 +1,48 @@ +/** @file + This instance uses Supervisor mode SCRATCH CSR to get/set the + pointer of firmware context. + + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through Supervisor mode SCRATCH CSR. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorScratch (); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through Supervisor mode SCRATCH CSR. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr); +} diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ris= cVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c new file mode 100644 index 000000000000..7d1675355a50 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c @@ -0,0 +1,48 @@ +/** @file + This instance uses This iinstance Supervisor mode STVEC CSR to + get/set the pointer of firmware context. + + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through Supervisor mode STVEC CSR. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorStvec (); +} + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through Supervisor mode STVEC CSR + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr); +} diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index 06ba80cb5fcb..e242c9b866a1 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -2,7 +2,7 @@ // // RISC-V CPU functions. // -// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId) csrr a0, RISCV_CSR_MACHINE_MIMPID ret =20 +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH + ret + +// +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, RISCV_CSR_SUPERVISOR_STVEC + ret + // // Set Supervisor Address Translation and // Protection Register. --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#82275): https://edk2.groups.io/g/devel/message/82275 Mute This Topic: https://groups.io/mt/86432320/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-