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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: ELIfprHljF28GyJ8iHMwKNGLx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634615452; bh=WqLV1WuzZod7TE9mtoJexbLY9KzU+7vQDqbkHa0bFCw=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=gu9eBpaI2il4sIIXTddzPG5/fsMJ9zEFp+0CEGcTASwxAoq1qFiUSdqoFgT323DbI0y ySnWwbe4fz+63Tc2KpXRoec+26Kx8mMDcaMkIKnjdCE8fm2U54qIXviNc8zh4I2Fph4y5 c+8bj/EvsCF0jEops+l35lWoJY1RHVEG55A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634615453547100002 Content-Type: text/plain; charset="utf-8" New platform files require more space in SEC. Behavior is determined not by source code but by device tree. Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/Opensb= iPlatformLib/OpensbiPlatformLib.inf | 2 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/Opensb= iPlatformLib/PlatformOverride.h | 27 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/Opensb= iPlatformLib/Platform.c | 390 ++++++++++---------- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/Opensb= iPlatformLib/SifiveFu540.c | 47 +++ Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc = | 6 +- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc = | 6 +- 6 files changed, 281 insertions(+), 197 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/SiFive/U5SeriesP= kg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatfo= rmLib.inf index 317aaceb2519..f9f2073a5ba4 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/OpensbiPlatformLib.inf +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/OpensbiPlatformLib.inf @@ -25,6 +25,8 @@ =20 [Sources] Platform.c + SifiveFu540.c + PlatformOverride.h =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/OpensbiPlatformLib/PlatformOverride.h b/Platform/SiFive/U5SeriesPkg/F= reedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/PlatformOverride.h new file mode 100644 index 000000000000..9b6fcdc15f45 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/PlatformOverride.h @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __PLATFORM_OVERRIDE_H__ +#define __PLATFORM_OVERRIDE_H__ + +#include + +struct platform_override { + const struct fdt_match *match_table; + u64 (*features)(const struct fdt_match *match); + u64 (*tlbr_flush_limit)(const struct fdt_match *match); + int (*early_init)(bool cold_boot, const struct fdt_match *match); + int (*final_init)(bool cold_boot, const struct fdt_match *match); + void (*early_exit)(const struct fdt_match *match); + void (*final_exit)(const struct fdt_match *match); + int (*system_reset)(u32 reset_type, const struct fdt_match *match); + int (*fdt_fixup)(void *fdt, const struct fdt_match *match); +}; + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/OpensbiPlatformLib/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU5= 40HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c index aa6274be965b..fe6e2a8c943a 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/Platform.c +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/Platform.c @@ -1,216 +1,224 @@ /* - * - * Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
- * * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2020 Western Digital Corporation or its affiliates. * * Authors: - * Atish Patra + * Anup Patel */ =20 #include +#include #include -#include -#include -#include -#include +#include #include +#include #include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include =20 -#define U540_HART_COUNT FixedPcdGet32(PcdHartCount) -#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber) -#define U540_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) -#define U540_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) +extern const struct platform_override sifive_fu540; =20 -#define U540_SYS_CLK FixedPcdGet32(PcdU5PlatformSystemClock) - -#define U540_PLIC_ADDR 0xc000000 -#define U540_PLIC_NUM_SOURCES 0x35 -#define U540_PLIC_NUM_PRIORITIES 7 - -#define U540_UART_ADDR FixedPcdGet32(PcdU5UartBase) - -#define U540_UART_BAUDRATE 115200 - -/* PRCI clock related macros */ -//TODO: Do we need a separate driver for this ? -#define U540_PRCI_BASE_ADDR 0x10000000 -#define U540_PRCI_CLKMUXSTATUSREG 0x002C -#define U540_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) - -/* Full tlb flush always */ -#define U540_TLB_RANGE_FLUSH_LIMIT 0 - -unsigned long log2roundup(unsigned long x); - -static struct plic_data plic =3D { - .addr =3D U540_PLIC_ADDR, - .num_src =3D U540_PLIC_NUM_SOURCES, +static const struct platform_override *special_platforms[] =3D { + &sifive_fu540, }; =20 -static struct clint_data clint =3D { - .addr =3D CLINT_REG_BASE_ADDR, - .first_hartid =3D 0, - .hart_count =3D U540_HART_COUNT, - .has_64bit_mmio =3D TRUE, -}; - -static void U540_modify_dt(void *fdt) -{ - fdt_cpu_fixup(fdt); - - fdt_fixups(fdt); - - /* - * SiFive Freedom U540 has an erratum that prevents S-mode software - * to access a PMP protected region using 1GB page table mapping, so - * always add the no-map attribute on this platform. - */ - fdt_reserved_memory_nomap_fixup(fdt); -} - -static int U540_final_init(bool cold_boot) -{ - void *fdt; - struct sbi_scratch *ThisScratch; - - if (!cold_boot) - return 0; - - fdt =3D sbi_scratch_thishart_arg1_ptr(); - U540_modify_dt(fdt); - // - // Set PMP of firmware regions to R and X. We will lock this in the en= d of PEI. - // This region only protects SEC, PEI and Scratch buffer. - // - ThisScratch =3D sbi_scratch_thishart_ptr (); - pmp_set(0, PMP_R | PMP_X | PMP_W, ThisScratch->fw_start, log2roundup (= ThisScratch->fw_size)); - return 0; -} - -static u32 U540_pmp_region_count(u32 hartid) -{ - return 1; -} - -static int U540_pmp_region_info(u32 hartid, u32 index, - ulong *prot, ulong *addr, ulong *log2size) -{ - int ret =3D 0; - - switch (index) { - case 0: - *prot =3D PMP_R | PMP_W | PMP_X; - *addr =3D 0; - *log2size =3D __riscv_xlen; - break; - default: - ret =3D -1; - break; - }; - - return ret; -} - -static int U540_console_init(void) -{ - unsigned long peri_in_freq; - - peri_in_freq =3D U540_SYS_CLK/2; - return sifive_uart_init(U540_UART_ADDR, peri_in_freq, U540_UART_BAUDRA= TE); -} - -static int U540_irqchip_init(bool cold_boot) -{ - int rc; - u32 hartid =3D current_hartid(); - - if (cold_boot) { - rc =3D plic_cold_irqchip_init(&plic); - if (rc) - return rc; - } - - return plic_warm_irqchip_init(&plic, - (hartid) ? (2 * hartid - 1) : 0, - (hartid) ? (2 * hartid) : -1); -} - -static int U540_ipi_init(bool cold_boot) -{ - int rc; - - if (cold_boot) { - rc =3D clint_cold_ipi_init(&clint); - if (rc) - return rc; - - } - - return clint_warm_ipi_init(); -} - -static u64 U540_get_tlbr_flush_limit(void) -{ - return U540_TLB_RANGE_FLUSH_LIMIT; -} - -static int U540_timer_init(bool cold_boot) -{ - int rc; - - if (cold_boot) { - rc =3D clint_cold_timer_init(&clint, NULL); - if (rc) - return rc; - } - - return clint_warm_timer_init(); -} -/** - * The U540 SoC has 5 HARTs, Boot HART ID is determined by - * PcdBootHartId. +static const struct platform_override *generic_plat =3D NULL; +static const struct fdt_match *generic_plat_match =3D NULL; + +static void fw_platform_lookup_special(void *fdt, int root_offset) +{ + int pos, noff; + const struct platform_override *plat; + const struct fdt_match *match; + + for (pos =3D 0; pos < array_size(special_platforms); pos++) { + plat =3D special_platforms[pos]; + if (!plat->match_table) + continue; + + noff =3D fdt_find_match(fdt, -1, plat->match_table, &match); + if (noff < 0) + continue; + + generic_plat =3D plat; + generic_plat_match =3D match; + break; + } +} + +extern struct sbi_platform platform; +static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] =3D { 0 }; + +/* + * The fw_platform_init() function is called very early on the boot HART + * OpenSBI reference firmwares so that platform specific code get chance + * to update "platform" instance before it is used. + * + * The arguments passed to fw_platform_init() function are boot time state + * of A0 to A4 register. The "arg0" will be boot HART id and "arg1" will + * be address of FDT passed by previous booting stage. + * + * The return value of fw_platform_init() function is the FDT location. If + * FDT is unchanged (or FDT is modified in-place) then fw_platform_init() + * can always return the original FDT location (i.e. 'arg1') unmodified. */ -static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] =3D {1, 2, 3, 4}; +unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4) +{ + const char *model, *mmu_type; + void *fdt =3D (void *)arg1; + u32 hartid, hart_count =3D 0; + int rc, root_offset, cpus_offset, cpu_offset, len; + + root_offset =3D fdt_path_offset(fdt, "/"); + if (root_offset < 0) + goto fail; + + fw_platform_lookup_special(fdt, root_offset); + + model =3D fdt_getprop(fdt, root_offset, "model", &len); + if (model) + sbi_strncpy(platform.name, model, sizeof(platform.name)); + + if (generic_plat && generic_plat->features) + platform.features =3D generic_plat->features(generic_plat_match); + + cpus_offset =3D fdt_path_offset(fdt, "/cpus"); + if (cpus_offset < 0) + goto fail; + + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) { + rc =3D fdt_parse_hart_id(fdt, cpu_offset, &hartid); + if (rc) + continue; + + if (SBI_HARTMASK_MAX_BITS <=3D hartid) + continue; + + mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", &len); + if (!mmu_type || !len) + hartid =3D -1U; =20 -static int U540_system_reset(u32 type) + generic_hart_index2id[hart_count++] =3D hartid; + } + + platform.hart_count =3D hart_count; + + /* Return original FDT pointer */ + return arg1; + +fail: + while (1) + wfi(); +} + +static int generic_early_init(bool cold_boot) { - /* For now nothing to do. */ + int rc; + + if (generic_plat && generic_plat->early_init) { + rc =3D generic_plat->early_init(cold_boot, generic_plat_match); + if (rc) + return rc; + } + + if (!cold_boot) return 0; + + return fdt_reset_init(); +} + +static int generic_final_init(bool cold_boot) +{ + void *fdt; + int rc; + + if (generic_plat && generic_plat->final_init) { + rc =3D generic_plat->final_init(cold_boot, generic_plat_match); + if (rc) + return rc; + } + + if (!cold_boot) + return 0; + + fdt =3D sbi_scratch_thishart_arg1_ptr(); + + fdt_cpu_fixup(fdt); + fdt_fixups(fdt); + + if (generic_plat && generic_plat->fdt_fixup) { + rc =3D generic_plat->fdt_fixup(fdt, generic_plat_match); + if (rc) + return rc; + } + + return 0; +} + +static void generic_early_exit(void) +{ + if (generic_plat && generic_plat->early_exit) + generic_plat->early_exit(generic_plat_match); +} + +static void generic_final_exit(void) +{ + if (generic_plat && generic_plat->final_exit) + generic_plat->final_exit(generic_plat_match); +} + +static u64 generic_tlbr_flush_limit(void) +{ + if (generic_plat && generic_plat->tlbr_flush_limit) + return generic_plat->tlbr_flush_limit(generic_plat_match); + return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; +} + +static int generic_system_reset(u32 reset_type) +{ + if (generic_plat && generic_plat->system_reset) + return generic_plat->system_reset(reset_type, + generic_plat_match); + return fdt_system_reset(reset_type); } =20 const struct sbi_platform_operations platform_ops =3D { - .pmp_region_count =3D U540_pmp_region_count, - .pmp_region_info =3D U540_pmp_region_info, - .final_init =3D U540_final_init, - .console_putc =3D sifive_uart_putc, - .console_getc =3D sifive_uart_getc, - .console_init =3D U540_console_init, - .irqchip_init =3D U540_irqchip_init, - .ipi_send =3D clint_ipi_send, - .ipi_clear =3D clint_ipi_clear, - .ipi_init =3D U540_ipi_init, - .get_tlbr_flush_limit =3D U540_get_tlbr_flush_limit, - .timer_value =3D clint_timer_value, - .timer_event_stop =3D clint_timer_event_stop, - .timer_event_start =3D clint_timer_event_start, - .timer_init =3D U540_timer_init, - .system_reset =3D U540_system_reset + .early_init =3D generic_early_init, + .final_init =3D generic_final_init, + .early_exit =3D generic_early_exit, + .final_exit =3D generic_final_exit, + .console_putc =3D fdt_serial_putc, + .console_getc =3D fdt_serial_getc, + .console_init =3D fdt_serial_init, + .irqchip_init =3D fdt_irqchip_init, + .irqchip_exit =3D fdt_irqchip_exit, + .ipi_send =3D fdt_ipi_send, + .ipi_clear =3D fdt_ipi_clear, + .ipi_init =3D fdt_ipi_init, + .ipi_exit =3D fdt_ipi_exit, + .get_tlbr_flush_limit =3D generic_tlbr_flush_limit, + .timer_value =3D fdt_timer_value, + .timer_event_stop =3D fdt_timer_event_stop, + .timer_event_start =3D fdt_timer_event_start, + .timer_init =3D fdt_timer_init, + .timer_exit =3D fdt_timer_exit, + .system_reset =3D generic_system_reset, }; =20 -const struct sbi_platform platform =3D { - .opensbi_version =3D OPENSBI_VERSION, // The O= penSBI version this platform table is built bassed on. - .platform_version =3D SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI P= latform version 1.0 - .name =3D "SiFive Freedom U540", - .features =3D SBI_PLATFORM_DEFAULT_FEATURES, - .hart_count =3D U540_BOOTABLE_HART_COUNT, - .hart_index2id =3D U540_hart_index2id, - .hart_stack_size =3D U540_HART_STACK_SIZE, - .platform_ops_addr =3D (unsigned long)&platform_ops +struct sbi_platform platform =3D { + .opensbi_version =3D OPENSBI_VERSION, + .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01), + .name =3D "Generic", + .features =3D SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count =3D SBI_HARTMASK_MAX_BITS, + .hart_index2id =3D generic_hart_index2id, + .hart_stack_size =3D SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, + .platform_ops_addr =3D (unsigned long)&platform_ops }; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Li= brary/OpensbiPlatformLib/SifiveFu540.c b/Platform/SiFive/U5SeriesPkg/Freedo= mU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/SifiveFu540.c new file mode 100644 index 000000000000..748b058840e0 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/O= pensbiPlatformLib/SifiveFu540.c @@ -0,0 +1,47 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include + +static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match) +{ + /* + * The sfence.vma by virtual address does not work on + * SiFive FU540 so we return remote TLB flush limit as zero. + */ + return 0; +} + +static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match) +{ + /* + * SiFive Freedom U540 has an erratum that prevents S-mode software + * to access a PMP protected region using 1GB page table mapping, so + * always add the no-map attribute on this platform. + */ + fdt_reserved_memory_nomap_fixup(fdt); + + return 0; +} + +static const struct fdt_match sifive_fu540_match[] =3D { + { .compatible =3D "sifive,fu540" }, + { .compatible =3D "sifive,fu540g" }, + { .compatible =3D "sifive,fu540-c000" }, + { .compatible =3D "sifive,hifive-unleashed-a00" }, + { }, +}; + +const struct platform_override sifive_fu540 =3D { + .match_table =3D sifive_fu540_match, + .tlbr_flush_limit =3D sifive_fu540_tlbr_flush_limit, + .fdt_fixup =3D sifive_fu540_fdt_fixup, +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc= b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc index 13c14a4a2c76..e88aee8c0212 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc @@ -23,10 +23,10 @@ DEFINE CODE_BLOCKS =3D 0x7E0 DEFINE VARS_BLOCKS =3D 0x20 =20 DEFINE SECFV_OFFSET =3D 0x00000000 -DEFINE SECFV_SIZE =3D 0x00020000 -DEFINE PEIFV_OFFSET =3D 0x00020000 +DEFINE SECFV_SIZE =3D 0x00030000 +DEFINE PEIFV_OFFSET =3D 0x00030000 DEFINE PEIFV_SIZE =3D 0x00080000 -DEFINE SCRATCH_OFFSET =3D 0x000a0000 +DEFINE SCRATCH_OFFSET =3D 0x000b0000 DEFINE SCRATCH_SIZE =3D 0x00010000 DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng DEFINE FVMAIN_SIZE =3D 0x0018C000 diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 723632dc792d..8e7afc2d82c4 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -23,10 +23,10 @@ DEFINE CODE_BLOCKS =3D 0x7E0 DEFINE VARS_BLOCKS =3D 0x20 =20 DEFINE SECFV_OFFSET =3D 0x00000000 -DEFINE SECFV_SIZE =3D 0x00020000 -DEFINE PEIFV_OFFSET =3D 0x00020000 +DEFINE SECFV_SIZE =3D 0x00030000 +DEFINE PEIFV_OFFSET =3D 0x00030000 DEFINE PEIFV_SIZE =3D 0x00080000 -DEFINE SCRATCH_OFFSET =3D 0x000a0000 +DEFINE SCRATCH_OFFSET =3D 0x000b0000 DEFINE SCRATCH_SIZE =3D 0x00010000 DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng DEFINE FVMAIN_SIZE =3D 0x0018C000 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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