From nobody Fri May 3 00:02:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+82225+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82225+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1634565458; cv=none; d=zohomail.com; s=zohoarc; b=ZkGaPyxGKfLEgTQW0UmffPD8yOW2/4rsmTj9fYqVZb/6JnZevTnK6LTiw5CW2yvCDuGs9cywY3FG5r6zNADNV94ump28tUNqlwhk+q6YXdQdbrM1u4CW94bW1zNMPTlmkcpv+baFw0lKft0XZ6mWv0Gs/jvmlmKl9nUlCutuPfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1634565458; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=G1hw2lzHPToQYkW5+cszeIxnAO+JCEsyNrGW5L0QIjA=; b=JwiPFZeU2LuzoaagxlyjclQ0GyPMAugKB0MCi72ge3xgAJy5wAbo+WueIflHbe0IIIZqMEPX5qe2PhdwVXY/GMuC2KDHlL5BuDCtvfhBH0mSNoRVKOSiqLaGsRxIMBvRCcDYokU1YXnaybIAXJaCRVqNL73i5A267DCbNwh8xM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+82225+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1634565458942184.48767760130784; Mon, 18 Oct 2021 06:57:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dEQIYY1788612xqwRBP75H5Y; Mon, 18 Oct 2021 06:57:38 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.36957.1634565456303725835 for ; Mon, 18 Oct 2021 06:57:37 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10140"; a="228133439" X-IronPort-AV: E=Sophos;i="5.85,382,1624345200"; d="scan'208";a="228133439" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2021 06:57:26 -0700 X-IronPort-AV: E=Sophos;i="5.85,382,1624345200"; d="scan'208";a="443418202" X-Received: from mczajkow-mobl.ger.corp.intel.com ([10.213.2.138]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2021 06:57:24 -0700 From: "Maciej Czajkowski" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [edk2platforms][PATCH v2 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol Date: Mon, 18 Oct 2021 15:57:19 +0200 Message-Id: <20211018135719.689-2-maciej.czajkowski@intel.com> In-Reply-To: <20211018135719.689-1-maciej.czajkowski@intel.com> References: <20211018135719.689-1-maciej.czajkowski@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,maciej.czajkowski@intel.com X-Gm-Message-State: XPAkEPYbKbCrQHH60doGNRGMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1634565458; bh=9ex1BmHFruFVJPNZdbzQb5QIsuFKkfw0D71z9YCm7EM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=C7nVs2D7dsrYUfPEuGHb3K9WG5EhE8e9KnJzJqkRZbCRiRT1FIdkP+94a9Tx97RDu7E bmb1c1EmapuyxT9xZnxEKNIe3A31XSge4J+OKS+Uk3Nglf9u9p32bAvYAeFVyTa1db7Pl AkkD25rtEQpCBborz86agJWcSdEeeI/26rE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1634565461003100006 Content-Type: text/plain; charset="utf-8" Added IntelDieInfoProtocol header into IntelSiliconPkg tree. The purpose is to have generic and unified interface for getting information about dies installed in the system. It will be implemented by silicon code. Change-Id: Iedc414d435c27f37e6f12e7affd046a0a9e7e19d Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Maciej Czajkowski --- Notes: v2: - added interface description - added die specific GUIDs into .dec file Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h | 11= 7 ++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | = 9 ++ 2 files changed, 126 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoPro= tocol.h b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtoc= ol.h new file mode 100644 index 000000000000..954c9ee10c22 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfoProtocol.h @@ -0,0 +1,117 @@ +/** @file + IntelDieInfoProtocol definition + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _DIE_INFO_PROTOCOL_H_ +#define _DIE_INFO_PROTOCOL_H_ + +typedef struct _INTEL_DIE_INFO_PROTOCOL INTEL_DIE_INFO_PROTOCOL; +typedef INTEL_DIE_INFO_PROTOCOL INTEL_DIE_INFO_PPI; + +extern EFI_GUID gIntelDieInfoProtocolGuid; +extern EFI_GUID gIntelDieInfoPpiGuid; + +extern EFI_GUID gIntelDieInfoPchGuid; +extern EFI_GUID gIntelDieInfoSocGuid; +extern EFI_GUID gIntelDieInfoIoGuid; +extern EFI_GUID gIntelDieInfoCpuGuid; +extern EFI_GUID gIntelDieInfoGfxGuid; + +#define INTEL_DIE_INFO_PPI_GUID \ +{ 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x08, 0xF1, 0x25, 0xF2, 0x40, = 0x37 }} + +#define INTEL_DIE_INFO_PROTOCOL_GUID \ +{ 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x08, 0xF1, 0x25, 0xF2, 0x40, = 0x37 }} + +#define DIE_INFO_PROTOCOL_REVISION 1 +#define DIE_INFO_PROTOCOL_SIGNATURE SIGNATURE_32 ('I', 'D', 'I', 'P') + +#define DIE_INFO_PCH_GUID \ +{ 0x62CB6D68, 0x4771, 0x4569, { 0x81, 0xFA, 0x1E, 0x99, 0x6E, 0xA9, 0x91, = 0xC5 }} + +#define DIE_INFO_SOC_GUID \ +{ 0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5D, 0xDA, 0xCA, 0x03, 0x74, = 0xD0 }} + +#define DIE_INFO_IO_GUID \ +{ 0x23DA4C74, 0x54A0, 0x4E01, { 0x83, 0xB1, 0x8C, 0xA7, 0x43, 0x43, 0x1F, = 0xF0 }} + +#define DIE_INFO_CPU_GUID \ +{ 0x6E5AF2E3, 0x5D84, 0x48F2, { 0x84, 0x28, 0x99, 0xE4, 0x93, 0x4F, 0x51, = 0xE4 }} + +#define DIE_INFO_GFX_GUID \ +{ 0x1D3D2599, 0x7A1C, 0x4B1E, { 0x8C, 0xC5, 0x0F, 0x88, 0x27, 0xA0, 0x2E, = 0xEC }} + +/** + Returns pointer to constant string representing die name. + Name is specific to die type. + + @param[in] This Pointer to the DieInfoProtocol context structure + @retval Pointer to the const string +**/ +typedef +CONST CHAR8* +(EFIAPI *INTEL_DIE_INFO_GET_DIE_NAME_STR) ( + IN INTEL_DIE_INFO_PROTOCOL *This + ); + +/** + Returns pointer to constant string representing stepping of the die. + + @param[in] This Pointer to the DieInfoProtocol context structure + @retval Pointer to the const string +**/ +typedef +CONST CHAR8* +(EFIAPI *INTEL_DIE_INFO_GET_STEPPING_STR) ( + IN INTEL_DIE_INFO_PROTOCOL *This + ); + +/** + Returns pointer to constant string representing SKU of the die. + + @param[in] This Pointer to the DieInfoProtocol context structure + @retval Pointer to the const string +**/ +typedef +CONST CHAR8* +(EFIAPI *INTEL_DIE_INFO_GET_SKU_STR) ( + IN INTEL_DIE_INFO_PROTOCOL *This + ); + +/** + Protocol/PPI definition. + The purpose of this interface is to serve die-specific informations in a= unified, generic way. + It will be produced by silicon code per die, and can be consumed by any = module that needs contained information. + + Revision 1: + - Initial version. +**/ +struct _INTEL_DIE_INFO_PROTOCOL { + UINT32 Signature; ///< Protocol signature + UINT32 Revision; ///< Current protocol revision + /** + Type of the die that particular instance is reffering to. See DIE_INFO= _*_GUID + **/ + EFI_GUID Type; + /** + Index of the die in the system. + **/ + UINT32 DieIndex; + /** + Generation and die specific ID number. + **/ + UINT64 DieId; + /** + Generation and die specific stepping ID. + **/ + UINT32 SteppingId; + + INTEL_DIE_INFO_GET_DIE_NAME_STR GetNameStr; + INTEL_DIE_INFO_GET_STEPPING_STR GetSteppingStr; + INTEL_DIE_INFO_GET_SKU_STR GetSkuStr; +}; + +#endif // _DIE_INFO_PROTOCOL_H_ diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 2461ab8e06e7..fe9b13ba28c7 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -70,12 +70,21 @@ [Guids] ## Include/Guid/MicrocodeShadowInfoHob.h gEdkiiMicrocodeStorageTypeFlashGuid =3D { 0x2cba01b3, 0xd391, 0x4598, { = 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } } =20 + ## Include/Protocol/IntelDieInfoProtocol.h + gIntelDieInfoPchGuid =3D { 0x62CB6D68, 0x4771, 0x4569, { 0x81, 0xFA, 0x1= E, 0x99, 0x6E, 0xA9, 0x91, 0xC5 }} + gIntelDieInfoSocGuid =3D { 0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5= D, 0xDA, 0xCA, 0x03, 0x74, 0xD0 }} + gIntelDieInfoIoGuid =3D { 0x23DA4C74, 0x54A0, 0x4E01, { 0x83, 0xB1, 0x8C= , 0xA7, 0x43, 0x43, 0x1F, 0xF0 }} + gIntelDieInfoCpuGuid =3D { 0x6E5AF2E3, 0x5D84, 0x48F2, { 0x84, 0x28, 0x9= 9, 0xE4, 0x93, 0x4F, 0x51, 0xE4 }} + gIntelDieInfoGfxGuid =3D { 0x1D3D2599, 0x7A1C, 0x4B1E, { 0x8C, 0xC5, 0x0= F, 0x88, 0x27, 0xA0, 0x2E, 0xEC }} + [Ppis] gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1= , 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } + gIntelDieInfoPpiGuid =3D { 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x0= 8, 0xF1, 0x25, 0xF2, 0x40, 0x37 }} =20 [Protocols] gEdkiiPlatformVTdPolicyProtocolGuid =3D { 0x3d17e448, 0x466, 0x4e20, { 0= x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} + gIntelDieInfoProtocolGuid =3D { 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85= , 0x08, 0xF1, 0x25, 0xF2, 0x40, 0x37 }} =20 ## Protocol for device security policy. # Include/Protocol/PlatformDeviceSecurityPolicy.h --=20 2.27.0.windows.1 --------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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