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Sun, 10 Oct 2021 18:30:57 +0000 X-Received: from PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::e5a7:9474:4463:d258]) by PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::e5a7:9474:4463:d258%2]) with mapi id 15.20.4587.025; Sun, 10 Oct 2021 18:30:57 +0000 From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: nd@arm.com, Khasim Syed Mohammed , Chandni Cherukuri Subject: [edk2-devel] [PATCH v2 2/7] Silicon/ARM/NeoverseN1Soc: Define new PCDs and configure memory map Date: Sun, 10 Oct 2021 23:59:51 +0530 Message-Id: <20211010182956.13526-3-khasim.mohammed@arm.com> In-Reply-To: <20211010182956.13526-1-khasim.mohammed@arm.com> References: <20211010182956.13526-1-khasim.mohammed@arm.com> X-ClientProxiedBy: LO4P123CA0392.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18f::19) To PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) MIME-Version: 1.0 X-Received: from e116623.arm.com (217.140.99.251) by LO4P123CA0392.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.20 via Frontend Transport; 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6542 Original-Authentication-Results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: cb3d4d32-958d-4df6-9033-08d98c1c199e X-Microsoft-Antispam-Message-Info: 9HSMG4NDVM7eT8XGHGBZZwsuZbPly1TzTr+yvwvR7TRnGI8rXcf6mQlSwfm5vVaTr1H3d4dh//HSQ0CgVdavEcIzkKAT4ML7tRnpIhHccAZxbJVr+BRY/mtWUoIUIYtNaQmRMZ5ORmmh36H/QjJSmW7A1/RRHggH5FgV0h0vB/ID3AzMYaNcKjhQpRvCHDeIEkytUdxjeIuhrzkG7sARXGJ3heXbfFn2IRIiG0sSnznQVPbaxm+6MMfTLrtSPG4Fzueb0nZH9wgHF8uJTF25OklwFcb9MBT2xxVMIowRqBMKrhyq3m+3bFcdSTwD/yg8PbFR+cKIUF0CK944Tjjmwv/YH465wgwxhxwU97OVtwBNSVO6mtoNaMF18ezja+SlbDG/vvi32kHTiN+B6egFY+tULrCd1bD5ObV/KMkfqtPsHtH7lVTd6Z0xPaDBcsACy/x9zRDYTSMUiziSnOYJJWZnWD5RhzZUVRZ8C4IL/TQWrUX1Xj+rQ4BFzOGWST9aJDVmt79w5okCMZAmDnU6mcMCnU6w6HHJqG83E4rz48SCL6gdsMu2oywGgrBNRyw+4owKXyiD+lZa/YFsf/7oBxk8VXbjRT//Aeom351pGIshOBsVzxL5CYqzC3bFupgwk1lQfYxU7ayAyQN08CdETz3OZR9bsmoP6NM9KFVoPZ0QlFoPM+XGKYAQcAwRSQtu5pA6xmD8s1ODDs3NBo6IXg== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2021 18:31:06.3554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e365654-1dd9-4b87-eb5e-08d98c1c1f69 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB2681 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,khasim.mohammed@arm.com X-Gm-Message-State: 2py0kEJT07xncazMuxqHd6Rax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1633890672; bh=2tjY5DD1vJCkSwPZKFqvoSH7Rw5+GUVseizizoqLBTI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=tES4dd8tiUERl9SFtD9CG4urj40D/2FVDfTpO2Rtn2wTiGBXqaWdTVPH/4+SDec4qyn f/rBxcKlmonJU2VNkvpswRahDHQPlfrznH3/F4U+0vZOnqUGh3LP3vnH4INbm5T0MQC9K pc8xxc0v2/BLcW9SQDeLbpCSC8NrcAo0eXQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1633891576644100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch introduces new PCDs required to enable chip to chip interface and corresponding memory map is updated. Signed-off-by: Chandni Cherukuri Signed-off-by: Khasim Syed Mohammed Reviewed-by: Pierre Gondois --- .../Library/PlatformLib/PlatformLib.inf | 28 +++++-- .../Library/PlatformLib/PlatformLibMem.c | 84 ++++++++++++++++--- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 35 +++++++- 3 files changed, 125 insertions(+), 22 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 166c9e0444..8e2154aadf 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -1,6 +1,7 @@ ## @file +# Platform Library for N1Sdp. # -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -29,13 +30,17 @@ AArch64/Helper.S | GCC =20 [FixedPcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdArmPrimaryCore - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base @@ -45,7 +50,12 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize =20 - gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =20 [Guids] gEfiHobListGuid ## CONSUMES ## SystemTable diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index f9b3d03753..1c4a445c5e 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -1,9 +1,9 @@ /** @file -* -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #include @@ -13,7 +13,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 =20 /** Returns the Virtual Memory Map of the platform. @@ -21,21 +21,23 @@ This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. =20 - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR descr= ibing - a Physical-to-Virtual Memory mapping. This = array - must be ended by a zero-filled entry. + @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des= cribing + a Physical-to-Virtual Memory mapping. Thi= s array + must be ended by a zero-filled entry. **/ VOID ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap ) { - UINTN Index =3D 0; + UINTN Index; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; NEOVERSEN1SOC_PLAT_INFO *PlatInfo; UINT64 DramBlock2Size; + UINT64 RemoteDdrSize; =20 + Index =3D 0; PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE; DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * @@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap ( FixedPcdGet64 (PcdDramBlock2Base), DramBlock2Size); =20 + if (PlatInfo->MultichipMode =3D=3D 1) { + RemoteDdrSize =3D ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBa= se), + PcdGet64 (PcdSystemMemorySize) + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base= ), + RemoteDdrSize + ); + } + ASSERT (VirtualMemoryMap !=3D NULL); Index =3D 0; =20 @@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64Siz= e); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + // CCIX RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixRootPortC= onfigBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixRootPortC= onfigBaseSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixExpressBa= seAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixExpressBa= seAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdCcixBus= Max) - + FixedPcdGet32 (PcdCcixBusMi= n) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdCcixMmio32Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdCcixMmio32Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdCcixMmio32Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // CCIX MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdCcixMmio64Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdCcixMmio64Bas= e); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdCcixMmio64Siz= e); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BASE; VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BASE; @@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIPH_B= ASE0_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + if (PlatInfo->MultichipMode =3D=3D 1) { + //Remote DDR (2GB) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemor= ySize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_THROUGH; + + //Remote DDR + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdExtMemorySp= ace) + + PcdGet64 (PcdDramBlock2Bas= e); + VirtualMemoryTable[Index].Length =3D RemoteDdrSize; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_THROUGH; + } + // End of Table VirtualMemoryTable[++Index].PhysicalBase =3D 0; VirtualMemoryTable[Index].VirtualBase =3D 0; diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index 54b793a937..eea2d58402 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -1,5 +1,7 @@ +## @file +# Describes the entire platform configuration. # -# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,8 +35,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x000= 00008 - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x000000= 09 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x0000= 0008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0= x0000000A gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x00= 00000B gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0= x0000000C @@ -44,3 +46,30 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64= |0x00000010 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x= 00000011 gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00= 000012 + + # CCIX + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UIN= T32|0x00000019 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x00000= 01B + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0= x00000001D + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x00= 00001E + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0= x00000001F + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00= 000020 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00= 000021 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x= 00000022 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64= |0x00000023 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x= 00000024 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00= 000025 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000= 000|UINT32|0x00000026 + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000= |UINT32|0x00000027 + + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0= x00000029 + + # Remote Chip PCIe + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000= |UINT64|0x0000004A + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x4000000= 0000|UINT64|0x0000004B + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x4000000= 0000|UINT64|0x0000004C --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#81727): https://edk2.groups.io/g/devel/message/81727 Mute This Topic: https://groups.io/mt/86219906/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-