From nobody Tue Apr 23 09:17:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+81667+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+81667+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1633680092; cv=none; d=zohomail.com; s=zohoarc; b=VHidWEyZQ9mInTzHRpihFIsnjMTCnAldn4SyPrJ1In5gusw2swSpwEoUCzXxYVdnyf2qx80ZtXBt/goEvJmxucMcHUpBeChd6ovDx4Ev3JTSqTD2ix9x1o/N12pngoGLriepfs26uiy8esxJaEZDPW09sNjhze/rlZOuhh0lSMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1633680092; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=bhEB/+TBPGvT91lFqAIINCUSExXZfLO6/pLROAN+bcA=; b=I4wfOKAHqANg0KbfRouXDTmYY2XcY/Kn4xC6Tzt8D1C2pKhpjzXfCu9xZanA/iuh3+1gXXjoE0b/a1UOhCZSjcBiuK8QOzJXesZrEWGaIyQERR4pvBC2BVW/3c3rMLGk/9ZaD1pzffYbaNDnJKS+/zY24mbGYAX7Dqi+EjLnmvk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+81667+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1633680092628480.1674211736063; Fri, 8 Oct 2021 01:01:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5ELfYY1788612xGHuWHahGoV; Fri, 08 Oct 2021 01:01:32 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.6170.1633680090908781851 for ; Fri, 08 Oct 2021 01:01:31 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="213600456" X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="213600456" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2021 01:01:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,357,1624345200"; d="scan'208";a="459085239" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga002.jf.intel.com with ESMTP; 08 Oct 2021 01:01:25 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Jenny Huang , Ray Ni , Rangasai V Chaganty , Robert Kowalewski Subject: [edk2-devel] [PATCH] IntelSiliconPkg/IntelVTdDmarPei: Fix DMA buffer overlap issue Date: Fri, 8 Oct 2021 16:01:16 +0800 Message-Id: <20211008080116.10096-1-w.sheng@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: yBkpJF6PIbqXRDYKZvj3aRUHx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1633680092; bh=vv4L/A9c/yEr3eKKogFCIo0clza566m070XutSS+Eu8=; h=Cc:Date:From:Reply-To:Subject:To; b=O+NUqIfH33ShEEvlNbhM7XxIXy4IwVB6b92Mpeh//g69VY43e2j4m4RnlC3C0qk+zez Aw7sxvUnfJ6T9CH8cj/sO5fPjw7l2OwOMhwxhHf6uBhhORR15jyyqyfEWEQxhGp+hvXqw ZCgBDUTAHxhY4Kl85qStTtwe6iqbJlPBOLw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1633680094621100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" gEdkiiVTdInfoPpiGuid notify could be called more than one time in PEI post memory phase. The DMA buffer should be set only once to prevent the memory overlap, because PeiIoMmuAllocateBuffer always allocate memory from the same buffer. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3667 Change-Id: I726314ae081e070e0655ca7ae845af8263d42a74 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Robert Kowalewski --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c | 52 ++++++++++++------= ---- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h | 1 - .../Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 2 +- 3 files changed, 30 insertions(+), 25 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmarPei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/I= ntelVTdDmarPei.c index a8f7bfee..89419625 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.c @@ -535,7 +535,7 @@ InitDmaBuffer( 4. Protection regions will be conveyed through VTD_PMR_INFO_HOB =20 When gVtdPmrInfoDataHobGuid dosen't exist, it means: - 1. IntelVTdDmar driver will calcuate the PMR memory alignment + 1. IntelVTdDmar driver will calcuate the protected memory alignment 2. Dma buffer is reserved by AllocateAlignedPages() **/ =20 @@ -545,31 +545,37 @@ InitDmaBuffer( return EFI_INVALID_PARAMETER; } =20 - if (VtdPmrHobPtr =3D=3D NULL) { - // - // Allocate memory for DMA buffer - // - DmaBufferInfo->DmaBufferBase =3D (UINT64) (UINTN) AllocateAlignedPages= (EFI_SIZE_TO_PAGES ((UINTN) DmaBufferInfo->DmaBufferSize), 0); - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { - DEBUG ((DEBUG_ERROR, " InitDmaBuffer : OutOfResource\n")); - return EFI_OUT_OF_RESOURCES; + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + if (VtdPmrHobPtr !=3D NULL) { + // + // Get the protected memory ranges information from the VTd PMR hob + // + VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); + + if ((VtdPmrHob->ProtectedHighBase - VtdPmrHob->ProtectedLowLimit) < = DmaBufferInfo->DmaBufferSize) { + DEBUG ((DEBUG_INFO, " DmaBufferSize not enough\n")); + return EFI_INVALID_PARAMETER; + } + DmaBufferInfo->DmaBufferBase =3D VtdPmrHob->ProtectedLowLimit; + } else { + // + // Allocate memory for DMA buffer + // + DmaBufferInfo->DmaBufferBase =3D (UINT64) (UINTN) AllocateAlignedPag= es (EFI_SIZE_TO_PAGES ((UINTN) DmaBufferInfo->DmaBufferSize), 0); + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_ERROR, " InitDmaBuffer : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } + DEBUG ((DEBUG_INFO, "Alloc DMA buffer success.\n")); } - DmaBufferInfo->DmaBufferLimit =3D DmaBufferInfo->DmaBufferBase + DmaBu= fferInfo->DmaBufferSize; - DEBUG ((DEBUG_INFO, "Alloc DMA buffer success.\n")); - } else { - // - // Get the PMR ranges information for the VTd PMR hob - // - VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); - DmaBufferInfo->DmaBufferBase =3D VtdPmrHob->ProtectedLowLimit; - DmaBufferInfo->DmaBufferLimit =3D VtdPmrHob->ProtectedHighBase; + + DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + = DmaBufferInfo->DmaBufferSize; + DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; + + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%lx\n", DmaBufferInfo= ->DmaBufferSize)); + DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%lx\n", DmaBufferInfo= ->DmaBufferBase)); } - DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + Dm= aBufferInfo->DmaBufferSize; - DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; =20 - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%lx\n", DmaBufferInfo->= DmaBufferSize)); - DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%lx\n", DmaBufferInfo->= DmaBufferBase)); - DEBUG ((DEBUG_INFO, " DmaBufferLimit : 0x%lx\n", DmaBufferInfo->= DmaBufferLimit)); DEBUG ((DEBUG_INFO, " DmaBufferCurrentTop : 0x%lx\n", DmaBufferInfo->= DmaBufferCurrentTop)); DEBUG ((DEBUG_INFO, " DmaBufferCurrentBottom : 0x%lx\n", DmaBufferInfo->= DmaBufferCurrentBottom)); =20 diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmarPei.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/I= ntelVTdDmarPei.h index e23a6c8e..4c9b0933 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= rPei.h @@ -56,7 +56,6 @@ typedef struct { typedef struct { UINT64 DmaBufferBase; UINT64 DmaBufferSize; - UINT64 DmaBufferLimit; UINT64 DmaBufferCurrentTop; UINT64 DmaBufferCurrentBottom; } DMA_BUFFER_INFO; diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Tran= slationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/= TranslationTable.c index 6676b2a9..0baa2ccc 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translation= Table.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translation= Table.c @@ -846,7 +846,7 @@ CreateFixedSecondLevelPagingEntry ( Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); DmaBufferInfo =3D GET_GUID_HOB_DATA (Hob); BaseAddress =3D DmaBufferInfo->DmaBufferBase; - Length =3D DmaBufferInfo->DmaBufferLimit - DmaBufferInfo->DmaBufferBase; + Length =3D DmaBufferInfo->DmaBufferSize; IoMmuAccess =3D EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE; =20 DEBUG ((DEBUG_INFO, " BaseAddress =3D 0x%lx\n", BaseAddress)); --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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