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Wed, 6 Oct 2021 11:57:44 +0000 From: "Daniel Schaefer" To: CC: , Abner Chang , Sunil V L Subject: [edk2-devel] [edk2-platforms][PATCH v2 07/14] U540: Add and build device tree Date: Wed, 6 Oct 2021 19:56:45 +0800 Message-ID: <20211006115652.3635489-8-daniel.schaefer@hpe.com> In-Reply-To: <20211006115652.3635489-1-daniel.schaefer@hpe.com> References: <20211006115652.3635489-1-daniel.schaefer@hpe.com> X-ClientProxiedBy: HK2PR0401CA0022.apcprd04.prod.outlook.com (2603:1096:202:2::32) To DF4PR8401MB0923.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760f::13) MIME-Version: 1.0 X-Received: from localhost.localdomain (123.193.59.220) by HK2PR0401CA0022.apcprd04.prod.outlook.com (2603:1096:202:2::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.17 via Frontend Transport; Wed, 6 Oct 2021 11:57:42 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 86a41ed1-58b3-426d-2f20-08d988c08191 X-MS-TrafficTypeDiagnostic: DF4PR8401MB0331: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:785; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,daniel.schaefer@hpe.com X-Gm-Message-State: R1jGUfnc9vYYdfO9Sq4QedClx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1633521508; bh=Gc8oeQWc1lxCeuSQOCdCGl5HiUpZ03RiOtkyE8Djw/A=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=ENfVD4FVDIls3AIwY5EG2m9v0Riykxs4VLNXuESzmjP8lF/e3iBz4tWsEevP1X9MV2R FSN4HwnRnJlBfTZCBhp3ROJCrXXw80zPAVjzoC+d5eFKkQgm2q9OtOkiLwS5xCi3Fd3Ar eoE541loJHy/JZssBZnrO1VBh4csOCEnGiw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1633521510053100001 Content-Type: text/plain; charset="utf-8" Device Tree is taken from Uboot. Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Signed-off-by: Daniel Schaefer --- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf= .inc | 35 +++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U54= 0DeviceTree.inf | 25 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu5= 40-c000.dtsi | 287 ++++++++++++++++++++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpi= o.h | 42 +++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hif= ive-unleashed-a00.dts | 106 ++++++++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sif= ive-fu540-prci.h | 18 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc = | 2 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf = | 6 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc = | 8 +- 9 files changed, 526 insertions(+), 3 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBo= ard/DeviceTree.fdf.inc new file mode 100644 index 0000000000..fb28be2767 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e.fdf.inc @@ -0,0 +1,35 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(DTB_OFFSET)|$(DTB_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVDtbFvSize +FV =3D DTBFV + +[FV.DTBFV] +BlockSize =3D 0x1000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +INF RuleOverride =3D DTB Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnle= ashedBoard/DeviceTree/U540DeviceTree.inf diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/U540DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFive= UnleashedBoard/DeviceTree/U540DeviceTree.inf new file mode 100644 index 0000000000..92c4211ccd --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/U540DeviceTree.inf @@ -0,0 +1,25 @@ +## @file +# +# Device tree description of the Hifive Unleashed platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D U540DeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + gpio.h + hifive-unleashed-a00.dts + fu540-c000.dtsi + sifive-fu540-prci.h + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/DeviceTree/fu540-c000.dtsi new file mode 100644 index 0000000000..e44b6f7c56 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +/*#include */ +#include "sifive-fu540-prci.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + ethernet0 =3D ð0; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu@0 { + compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + status =3D "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial@10010000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10010000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + dma: dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <23 24 25 26 27 28 29 30>; + #dma-cells =3D <1>; + }; + uart1: serial@10011000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10011000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <5>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + i2c0: i2c@10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi@10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi@10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi@10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet@10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm0: pwm@10020000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg =3D <0x0 0x10020000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <42 43 44 45>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + pwm1: pwm@10021000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg =3D <0x0 0x10021000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <46 47 48 49>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible =3D "sifive,fu540-c000-ccache", "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic0>; + interrupts =3D <1 2 3>; + reg =3D <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent =3D <&plic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, + <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>; + reg =3D <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + }; +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/gpio.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoa= rd/DeviceTree/gpio.h new file mode 100644 index 0000000000..c029467e82 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain inte= rface. + * Open Source/Emitter is the combination of single-ended open source inte= rface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/hifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU540= HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..df06f1c8c4 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/hifive-unleashed-a00.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" +/*#include */ +#include "gpio.h" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SiFive HiFive Unleashed A00"; + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path =3D "serial0"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <33333333>; + clock-output-names =3D "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D ; + clock-output-names =3D "rtcclk"; + }; + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 10 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&qspi0 { + status =3D "okay"; + flash@0 { + compatible =3D "issi,is25wp256", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qspi2 { + status =3D "okay"; + mmc@0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&gpio { + status =3D "okay"; +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/sifive-fu540-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiv= eUnleashedBoard/DeviceTree/sifive-fu540-prci.h new file mode 100644 index 0000000000..6a0b70a37d --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/sifive-fu540-prci.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 2b00176c27..e971993b7b 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -489,6 +489,8 @@ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/SerialDxe/SerialDxe.inf =20 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U= 540DeviceTree.inf + # # SMBIOS Support # diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.f= df index 7471737728..820e19d113 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf @@ -33,6 +33,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUe= fiRiscVPlatformPkgToken FV =3D FVMAIN_COMPACT =20 !include VarStore.fdf.inc +!include DeviceTree.fdf.inc =20 ##########################################################################= ###### =20 @@ -325,3 +326,8 @@ FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { RAW ACPI |.acpi RAW ASL |.aml } + +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN |.dtb + } diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index f72947da61..723632dc79 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -10,8 +10,8 @@ DEFINE BLOCK_SIZE =3D 0x1000 =20 DEFINE FW_BASE_ADDRESS =3D 0x80000000 -DEFINE FW_SIZE =3D 0x00800000 -DEFINE FW_BLOCKS =3D 0x800 +DEFINE FW_SIZE =3D 0x00820000 +DEFINE FW_BLOCKS =3D 0x820 =20 # # 0x000000-0x7DFFFF code @@ -32,13 +32,15 @@ DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power= of 2 for PMP setting DEFINE FVMAIN_SIZE =3D 0x0018C000 DEFINE VARS_OFFSET =3D 0x007E0000 DEFINE VARS_SIZE =3D 0x00020000 +DEFINE DTB_OFFSET =3D 0x00800000 +DEFINE DTB_SIZE =3D 0x00002000 =20 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE) =20 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BAS= E_ADDRESS) -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BAS= E_ADDRESS) + $(SCRATCH_OFFSET) SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_= SIZE) --=20 2.33.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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