From nobody Sun Feb 8 23:26:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79477+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79477+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1629279652; cv=none; d=zohomail.com; s=zohoarc; b=Xc3iN3Da53D36Q9hqw+B7S308Ah7IlqWT5FQqHI23gZNJInWjS/mvMjpG8A8VcRWx8k7t9h5pnf3oyYsexvBLU+Z3LiJDAy9i1/VBt6nBn6TJWTrFm8f/IX9Te8iZWbAs8Ca/x7mLI6rDBEb9QWvsK4f7w+ti8Z4WxMeRftSkZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629279652; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=isZxDst2BMQUA/+haA+yhG4DmiYd8mARL+Maq/+ouEk=; b=Ef6+xt73dkibA4DtMhF+mGK2snKxuLROwl1jwQdHcHEZ9VT7WEfnJOErY0/Vn7JefY2tJxgaqVQkVu9K8rWOGu0aACNkO4LRamLJI6xo3QqJba329yVpKKy98ivAq0QzEBBhH9OST6JOsg5/21ihsVoiwi2rxQjAqjXZeV7p2oY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79477+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1629279652351877.9631592574606; Wed, 18 Aug 2021 02:40:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id d637YY1788612xMyTBR0yTUs; Wed, 18 Aug 2021 02:40:51 -0700 X-Received: from azure-sdnproxy-2.icoremail.net (azure-sdnproxy-2.icoremail.net [52.229.168.213]) by mx.groups.io with SMTP id smtpd.web10.52285.1629279649396249207 for ; Wed, 18 Aug 2021 02:40:50 -0700 X-Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-1 (Coremail) with SMTP id AQAAfwC3iLVl1Rxhv9twAg--.36091S2; Wed, 18 Aug 2021 17:39:49 +0800 (CST) X-Received: from localhost.localdomain (unknown [223.104.21.14]) by mail (Coremail) with SMTP id AQAAfwCXMX2V1RxhgDMAAA--.1385S5; Wed, 18 Aug 2021 17:40:44 +0800 (CST) From: "Ling Jia" To: devel@edk2.groups.io Cc: Leif Lindholm , Ling Jia Subject: [edk2-devel] [PATCH v4 03/10] Silicon/Phytium: Added SMBIOS support to FT2000/4 Date: Wed, 18 Aug 2021 17:40:17 +0800 Message-Id: <20210818094024.40104-4-jialing@phytium.com.cn> In-Reply-To: <20210818094024.40104-1-jialing@phytium.com.cn> References: <20210818094024.40104-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAfwCXMX2V1RxhgDMAAA--.1385S5 X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ X-Coremail-Antispam: 1Uk129KBjvAXoWfAw13CF45ZrW8Cw1rCFykKrg_yoW5JrWkZo W7Wa1fJayFgrW8Zw47CrZ7Gr48ZF4I9w43tr9FyFyfZF4qv3y3KryUWa45ZrZIk3yjg398 C348J3s5JrW0vFW8n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jialing@phytium.com.cn X-Gm-Message-State: cO4VFd4IfnrfDU1IwQmlHvrBx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1629279651; bh=4JEM1RXMo6LV5ZQj1vm/xysahGK5a0iuYlMhiQk3SLg=; h=Cc:Date:From:Reply-To:Subject:To; b=HxXQhCd+iqgySV0sNo0LX0mMcIMcKXzhCpi4OVxxOaGtaU1p1F6m7bw5uK1Z9ozT3D2 ZKsEI7IkS2Wsx3rCCVS9dRMa0x2NuSl9OZF3u5XanUdLzOi8t/rqL3Q3mOjgl8H2kwoJ5 kZij3AKsbAL+8/ImJJ5cL7Q5SxYBIKlSoxU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1629279654717100001 Content-Type: text/plain; charset="utf-8" This driver installs SMBIOS information for FT2000/4. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc = | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 6 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f | 47 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = | 943 ++++++++++++++++++++ 4 files changed, 1002 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 6f38acb636..28e52e15e3 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -286,6 +286,12 @@ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe= .inf =20 + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.= inf + # # Bds # diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index f435f7cb51..3106a43fb7 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -178,6 +178,12 @@ READ_LOCK_STATUS =3D TRUE # INF ShellPkg/Application/Shell/Shell.inf =20 + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform= Dxe.inf + # # Bds # diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl= atformDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/Smbio= sPlatformDxe.inf new file mode 100644 index 0000000000..69a021e048 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD= xe.inf @@ -0,0 +1,47 @@ +#/** @file +# This driver installs SMBIOS information for Phytium. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SmbiosPlatformDxe + FILE_GUID =3D d64f09f8-40dc-11eb-9be6-f7a038f956ba + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmbiosTablePublishEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D AARCH64 +# +[Sources] + SmbiosPlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + DebugLib + IoLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + gEfiGlobalVariableGuid + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl= atformDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosP= latformDxe.c new file mode 100644 index 0000000000..4a1f77dfb2 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD= xe.c @@ -0,0 +1,943 @@ +/** @file + This driver installs SMBIOS information for Phytium Durian platforms. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +#include +#include +#include + +// SMBIOS tables often reference each other using +// fixed constants, define a list of these constants +// for our hardcoded tables + +#define TYPE0_STRINGS \ + "PHYTIUM LTD\0" /* Vendor */ \ + "V1.0\0" /* BiosVersion */ \ + __DATE__"\0" /* BiosReleaseDate */ + +#define TYPE1_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "Phytium Durian Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + "Not Set\0" /* SerialNumber */ \ + "Not set\0" /* SKUNumber */ \ + "FT-2000/4\0" /* Family */ \ + +#define TYPE2_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "Phytium Durian Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + "Not Set\0" /* Serial */ \ + "Not Set\0" /* BaseBoardAssetTag */ \ + "Not Set\0" /* BaseBoardChassisLocation */ + +#define TYPE3_STRINGS \ + "PHYTIUM LTD\0" /* Manufacturer */ \ + "None\0" /* Version */ \ + "Not Set\0" /* Serial */ \ + "Not Set\0" /* AssetTag */ + +#define TYPE4_STRINGS \ + "FT-2000/4\0" /* socket type */ \ + "PHYTIUM LTD\0" /* manufactuer */ \ + "FT-2000/4\0" /* processor version */ \ + "Not Set\0" /* SerialNumber */ \ + "Not Set\0" /* processor 2 description */ \ + "Not Set\0" /* AssetTag */ + + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ + +#define TYPE7_L1DATA_STRINGS \ + "L1 Data Cache\0" /* L1 data */ + + +#define TYPE7_L1INS_STRINGS \ + "L1 Instruction Cache\0" /* L1 ins */ + +#define TYPE7_L2_STRINGS \ + "L2 Cache\0" /* L2 */ + +#define TYPE7_L3_STRINGS \ + "L3 Cache\0" /* L3 */ + + +#define TYPE9_STRINGS \ + "PCIE_SLOT0\0" /* Slot0 */ \ + "PCIE_SLOT1\0" /* Slot1 */ \ + "PCIE_SLOT2\0" /* Slot2 */ \ + "PCIE_SLOT3\0" /* Slot3 */ + +#define TYPE9_STRINGS_PCIE0X16 \ + "PCIE0_X16\0" + +#define TYPE9_STRINGS_PCIE0X1 \ + "PCIE0_X1\0" + +#define TYPE9_STRINGS_PCIE1X16 \ + "PCIE1_X16\0" + +#define TYPE9_STRINGS_PCIE1X1 \ + "PCIE1_X1\0" + +#define TYPE13_STRINGS \ + "en|US|iso8859-1\0" \ + "zh|CN|unicode\0" + + +#define TYPE16_STRINGS \ + "\0" /* nothing */ + +#define TYPE17_STRINGS_CHANNEL0 \ + "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \ + "Bank0\0" /* bank description */ \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" + +#define TYPE17_STRINGS_CHANNEL1 \ + "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \ + "Bank0\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" \ + "Not Set\0" + + +#define TYPE19_STRINGS \ + "\0" /* nothing */ + +#define TYPE32_STRINGS \ + "\0" /* nothing */ + +#define TYPE39_STRINGS \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ \ + "Not specified\0" /* not specified*/ + +#define TYPE38_STRINGS \ + "\0" + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE0 Base; + INT8 Strings[sizeof (TYPE0_STRINGS)]; +} ARM_TYPE0; + +typedef struct { + SMBIOS_TABLE_TYPE1 Base; + UINT8 Strings[sizeof (TYPE1_STRINGS)]; +} ARM_TYPE1; + +typedef struct { + SMBIOS_TABLE_TYPE2 Base; + UINT8 Strings[sizeof (TYPE2_STRINGS)]; +} ARM_TYPE2; + +typedef struct { + SMBIOS_TABLE_TYPE3 Base; + UINT8 Strings[sizeof (TYPE3_STRINGS)]; +} ARM_TYPE3; + +typedef struct { + SMBIOS_TABLE_TYPE4 Base; + UINT8 Strings[sizeof (TYPE4_STRINGS)]; +} ARM_TYPE4; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L1DATA_STRINGS)]; +} ARM_TYPE7_L1DATA; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L1INS_STRINGS)]; +} ARM_TYPE7_L1INS; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L2_STRINGS)]; +} ARM_TYPE7_L2; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_L3_STRINGS)]; +} ARM_TYPE7_L3; + + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS)]; +} ARM_TYPE9; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X16)]; +} ARM_TYPE9_PCIE0X16; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X1)]; +} ARM_TYPE9_PCIE0X1; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X16)]; +} ARM_TYPE9_PCIE1X16; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X1)]; +} ARM_TYPE9_PCIE1X1; + + +typedef struct { + SMBIOS_TABLE_TYPE13 Base; + UINT8 Strings[sizeof (TYPE13_STRINGS)]; +} ARM_TYPE13; + +typedef struct { + SMBIOS_TABLE_TYPE16 Base; + UINT8 Strings[sizeof (TYPE16_STRINGS)]; +} ARM_TYPE16; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL0)]; +} ARM_TYPE17_CHANNEL0; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL1)]; +} ARM_TYPE17_CHANNEL1; + +typedef struct { + SMBIOS_TABLE_TYPE19 Base; + UINT8 Strings[sizeof (TYPE19_STRINGS)]; +} ARM_TYPE19; + +typedef struct { + SMBIOS_TABLE_TYPE32 Base; + UINT8 Strings[sizeof (TYPE32_STRINGS)]; +} ARM_TYPE32; + +typedef struct { + SMBIOS_TABLE_TYPE38 Base; + UINT8 Strings[sizeof (TYPE38_STRINGS)]; +} ARM_TYPE38; + +typedef struct { + SMBIOS_TABLE_TYPE39 Base; + UINT8 Strings[sizeof (TYPE39_STRINGS)]; +} ARM_TYPE39; + +enum SMBIOS_REFRENCE_HANDLES { + SMBIOS_HANDLE_L1I =3D 0x1000, + SMBIOS_HANDLE_L1D, + SMBIOS_HANDLE_L2, + SMBIOS_HANDLE_L3, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_CLUSTER, + SMBIOS_HANDLE_MEMORY, + SMBIOS_HANDLE_DIMM_0, + SMBIOS_HANDLE_DIMM_1 +}; + +#define SERIAL_LEN 10 //this must be less than the buffer len allocated i= n the type1 structure + +#pragma pack() + +//BIOS Information (Type 0) +ARM_TYPE0 BiosInfo_Type0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, //Vendor + 2, //BiosVersion + 0x8800, //BiosSegment + 3, //BiosReleaseDate + 0xFF, //BiosSize + { //BiosCharacteristics + 0, // Reserved = :2 + 0, // Unknown = :1 + 0, // BiosCharacteristicsN= otSupported :1 + 0, // IsaIsSupported = :1 + 0, // McaIsSupported = :1 + 0, // EisaIsSupported = :1 + 1, // PciIsSupported = :1 + 0, // PcmciaIsSupported = :1 + 0, // PlugAndPlayIsSupport= ed :1 + 0, // ApmIsSupported = :1 + 1, // BiosIsUpgradable = :1 + 0, // BiosShadowingAllowed= :1 + 0, // VlVesaIsSupported = :1 + 0, // EscdSupportIsAvailab= le :1 + 1, // BootFromCdIsSupporte= d :1 + 1, // SelectableBootIsSupp= orted :1 + 0, // RomBiosIsSocketed = :1 + 0, // BootFromPcmciaIsSupp= orted :1 + 0, // EDDSpecificationIsSu= pported :1 + 0, // JapaneseNecFloppyIsS= upported :1 + 0, // JapaneseToshibaFlopp= yIsSupported :1 + 0, // Floppy525_360IsSuppo= rted :1 + 0, // Floppy525_12IsSuppor= ted :1 + 0, // Floppy35_720IsSuppor= ted :1 + 0, // Floppy35_288IsSuppor= ted :1 + 0, // PrintScreenIsSupport= ed :1 + 0, // Keyboard8042IsSuppor= ted :1 + 0, // SerialIsSupported = :1 + 0, // PrinterIsSupported = :1 + 0, // CgaMonoIsSupported = :1 + 0, // NecPc98 = :1 + 0 // ReservedForVendor = :3 + }, + { + 0x03, //BIOSCharacteristicsEx= tensionBytes[0] + 0x0D //BIOSCharacteristicsEx= tensionBytes[1] + }, + 0xFF, //SystemBiosMajorReleas= e; + 0xFF, //SystemBiosMinorReleas= e; + 0xFF, //EmbeddedControllerFir= mwareMajorRelease; + 0xFF, //EmbeddedControllerFir= mwareMinorRelease; + }, + TYPE0_STRINGS +}; + +//System Information (Type 1). +ARM_TYPE1 SystemInfo_Type1 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + 1, // Manufacturer + 2, // ProductName + 3, // Version + 4, // SerialNumber + { // Uuid + 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa,= 0xbb, 0xcc} + }, + SystemWakeupTypePowerSwitch, // SystemWakeupType + 5, // SKUNumber, + 6 // Family + }, + TYPE1_STRINGS +}; + +//Base Board (or Module) Information (Type 2) +ARM_TYPE2 BaseboardInfo_Type2 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Len= gth + SMBIOS_HANDLE_MOTHERBOARD // Handle + }, + 1, // BaseBoard= Manufacturer + 2, // BaseBoard= ProductName + 3, // BaseBoard= Version + 4, // BaseBoard= SerialNumber + 5, // BaseBoard= AssetTag + { // FeatureFl= ag + 1, // Motherboa= rd :1 + 0, // RequiresD= aughterCard :1 + 0, // Removable= :1 + 1, // Replaceab= le :1 + 0, // HotSwappa= ble :1 + 0 // Reserved = :3 + }, + 6, // BaseBoard= ChassisLocation + 0, // ChassisHa= ndle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfC= ontainedObjectHandles; + { + 0 + } // Contained= ObjectHandles[1]; + }, + TYPE2_STRINGS +}; + +//System Enclosure or Chassis (Type 3) +ARM_TYPE3 SystemEnclosure_Type3 =3D { + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type, + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Len= gth + SMBIOS_HANDLE_CHASSIS // Handle + }, + 1, // Manufactr= urer + MiscChassisTypeMainServerChassis, // Type + 2, // Version + 3, // SerialNum= ber + 4, // AssetTag + ChassisStateSafe, // BootupSta= te + ChassisStateSafe, // PowerSupp= lyState + ChassisStateSafe, // ThermalSt= ate + ChassisSecurityStatusNone, // SecurityS= tate + { + 0, // OemDefine= d[0] + 0, // OemDefine= d[1] + 0, // OemDefine= d[2] + 0 // OemDefine= d[3] + }, + 2, // Height + 1, // NumberofP= owerCords + 0, // Contained= ElementCount + 0, // Contained= ElementRecordLength + { // Contained= Elements[0] + { + 0, // Contained= ElementType + 0, // Contained= ElementMinimum + 0 // Contained= ElementMaximum + } + } + }, + TYPE3_STRINGS +}; + +//Processor Infomation (Type 4) +ARM_TYPE4 ProcessorInfo_Type4 =3D { + { + { //Header + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE4), //Length + SMBIOS_HANDLE_CLUSTER //Handle + }, + 1, //Socket + CentralProcessor, //ProcessorType + ProcessorFamilyIndicatorFamily2, //ProcessorFamily + 2, //ProcessorManufacture + { //ProcessorId + { //Signature + 0 + }, + { //FeatureFlags + 0 + } + }, + 3, //ProcessorVersion + { //Voltage + 0, 0, 0, 1, 0, 1 + }, + 1, //ExternalClock + 1, //MaxSpeed + 0, //CurrentSpeed + 0x41, //Status + ProcessorUpgradeUnknown, //ProcessorUpgrade + SMBIOS_HANDLE_L1D, //L1Ins + SMBIOS_HANDLE_L2, //L1Data + SMBIOS_HANDLE_L3, //L2 + 4, //SerialNumber + 5, //AssetTag + 6, //PartNumber + + 4, //CoreCount + 0, //EnabledCoreCount + 0, //ThreadCount + 0x00EC, //ProcessorCharacteristics + + ProcessorFamilyARMv8, //ProcessorFamily2 + + 0, //CoreCount2 + 0, //EnabledCoreCount2 + 0 //ThreadCount2 + }, + TYPE4_STRINGS +}; + +//Cache Information (Type7) L1 DATA +ARM_TYPE7_L1DATA L1Data_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L1D //Handle + }, + 1, //SocketDesignation + 0x0180, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeData, //SystemCacheType + CacheAssociativity8Way, //Associativity + 128, + 128 + }, + TYPE7_L1DATA_STRINGS +}; + +//Cache Information (Type7) L1 INS +ARM_TYPE7_L1INS L1Ins_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L1I //Handle + }, + 1, //SocketDesignation + 0x0180, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorParity, //ErrorCorrectionType + CacheTypeInstruction, //SystemCacheType + CacheAssociativity8Way, //Associativity + 128, + 128 + }, + TYPE7_L1INS_STRINGS +}; + +//Cache Information (Type7) L2 +ARM_TYPE7_L2 L2_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L2 //Handle + }, + 1, //SocketDesignation + 0x0281, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeUnified, //SystemCacheType + CacheAssociativity8Way, //Associativity + 4096, + 4096 + }, + TYPE7_L2_STRINGS +}; + +//Cache Information (Type7) L3 +ARM_TYPE7_L3 L3_Type7 =3D { + { + { //Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type + sizeof (SMBIOS_TABLE_TYPE7), //Length + SMBIOS_HANDLE_L3 //Handle + }, + 1, //SocketDesignation + 0x0281, //CacheConfiguration + 0, //MaximumCacheSize + 0, //InstalledSize + { //SupportedSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + { //CurrentSRAMType + 0, 0, 0, 0, 0, 1, 0, 0 + }, + 0, //CacheSpeed + CacheErrorSingleBit, //ErrorCorrectionType + CacheTypeUnified, //SystemCacheType + CacheAssociativity8Way, //Associativity + 4096, + 4096 + }, + TYPE7_L3_STRINGS +}; + +//PCIE0_X16 (Type 9) +ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth16X, + SlotUsageInUse, + SlotLengthLong, + 0, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0, + 0, + 0, + }, + TYPE9_STRINGS_PCIE0X16 +}; + +//PCIE0_X1 (Type 9) +ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth1X, + SlotUsageAvailable, + SlotLengthShort, + 1, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE0X1 +}; + +//PCIE1_X16 (Type 9) +ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth16X, + SlotUsageAvailable, + SlotLengthLong, + 2, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE1X16 +}; + +//PCIE1_X1 (Type 9) +ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 1, + SlotTypePciX, + SlotDataBusWidth1X, + SlotUsageAvailable, + SlotLengthShort, + 3, + {0, 0, 1, 1, 0, 0, 0, 0}, //unknown + {1, 0, 0, 0, 0}, //PME and SMBUS + 0xFF, + 0xFF, + 0xFF, + }, + TYPE9_STRINGS_PCIE1X1 +}; + +//Bios Language Information (Type13) +ARM_TYPE13 BiosLangInfo_Type13 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 2, + 0, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 2 + }, + TYPE13_STRINGS +}; + +//Physical Memory Array (Type 16) +ARM_TYPE16 MemArray_Type16 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length + SMBIOS_HANDLE_MEMORY + }, + MemoryArrayLocationSystemBoard, + MemoryArrayUseSystemMemory, + MemoryErrorCorrectionNone, + 0x1000000, //16G + 0xFFFE, + 2 + }, + TYPE16_STRINGS +}; + +//Memory Device (Type17) +ARM_TYPE17_CHANNEL0 MemDev_Type17_0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM_0 + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this wo= uld be 72) + 64, //data width of this device (64-bits) + 0x4000, //16GB + 0x09, //FormFactor + 0, //not part of a set + 1, //right side of board + 2, //bank 0 + MemoryTypeDdr4, //LP DDR4 + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered + 2400, //2400Mhz DDR + 3, //Manufacturer + 4, //serial + 5, //asset tag + 6, //part number + 0, //attrbute + 0x2000, // 8G + 2400, //2400MHz + 1500, //Max V + 1500, //Max V + 1500, //Configure V + }, + TYPE17_STRINGS_CHANNEL0 +}; + +//Memory Device (Type17) +ARM_TYPE17_CHANNEL1 MemDev_Type17_1 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM_1 + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this wo= uld be 72) + 64, //data width of this device (64-bits) + 0x2000, //8GB + 0x09, //FormFactor + 0, //not part of a set + 1, //right side of board + 2, //bank 0 + MemoryTypeDdr4, //LP DDR4 + {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered + 2400, //2400Mhz DDR + 3, //varies between diffrent production runs + 4, //serial + 5, //asset tag + 6, //part number + 0, //attrbute + 0x4000, // 16G + 2400, //2400MHz + 1500, //Max V + 1500, //Max V + 1500, //Configure V + }, + TYPE17_STRINGS_CHANNEL1 +}; + +//Memory Array Mapped Address (Type 19) +ARM_TYPE19 MemArrayMapAddr_Type19 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + 0, + 0x1000000, //16G + SMBIOS_HANDLE_MEMORY, //handle + 2, + 0, //starting addr of first 2GB + 0, //ending addr of first 2GB + }, + TYPE19_STRINGS +}; + +//System Boot Information (Type 32) +ARM_TYPE32 SystemBoot_Type32 =3D { + { + { + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type, + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED + }, + { // Reserved[6] + 0, + 0, + 0, + 0, + 0, + 0 + }, + BootInformationStatusNoError // BootInformationSta= tus + }, + TYPE32_STRINGS +}; + +VOID *DefaultCommonTables[]=3D +{ + &BiosInfo_Type0, + &SystemInfo_Type1, + &BaseboardInfo_Type2, + &SystemEnclosure_Type3, + &ProcessorInfo_Type4, + &L1Data_Type7, + &L1Ins_Type7, + &L2_Type7, + &L3_Type7, + &Pcie0X16_Type9, + &Pcie0X1_Type9, + &Pcie1X16_Type9, + &Pcie1X1_Type9, + &MemArray_Type16, + &MemDev_Type17_0, + &MemDev_Type17_1, + &MemArrayMapAddr_Type19, + &BiosLangInfo_Type13, + &SystemBoot_Type32, + NULL +}; + + +/** + Installed a whole table worth of structructures. + + @param[in] Smbios The Pointer of Smbios Protocol. + + @retval EFI_SUCCESS Table data successfully installed. + @retval Other Table data was not installed. + +**/ +EFI_STATUS +InstallStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN VOID *DefaultTables[] + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT32 TableEntry; + + Status =3D EFI_SUCCESS; + + for ( TableEntry =3D0; DefaultTables[TableEntry] !=3D NULL; TableEntry++) + { + SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry]= )->Handle; + Status =3D Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) DefaultTables[TableEntry] + ); + if (EFI_ERROR (Status)) + break; + } + + return Status; +} + + +/** + Installed All SMBIOS information. + + @param[in] Smbios The Pointer of Smbios Protocol. + + @retval EFI_SUCCESS SMBIOS information successfully installed. + @retval Other SMBIOS information was not installed. + +**/ +STATIC +EFI_STATUS +InstallAllStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + Status =3D InstallStructures (Smbios, DefaultCommonTables); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +/** + Find the smbios protocol and installed SMBIOS information + for ARM platforms. + + @param[in] ImageHandle Module's image handle. + @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE. + + @retval EFI_SUCCESS Smbios data successfully installed. + @retval Other Smbios data was not installed. + +**/ +EFI_STATUS +EFIAPI +SmbiosTablePublishEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Find the SMBIOS protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&Smbios + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InstallAllStructures (Smbios); + + return Status; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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