From nobody Fri May 3 10:14:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79391+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79391+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1629150937; cv=none; d=zohomail.com; s=zohoarc; b=FvqiOL63XZAVdwzGnSpH/42wQbYc2rXJ6TDWZujH37ZNHZ+A3NK8bn4ijAE9RHyN7uXgCMS76INquyC8kJixWr6tK9r1bB8BzoWzm5fblQPGZvvYeujRFNTn2a84ekE/KkpzUbWBhfGlnWdiyHRsuik63davkRybL52Enq7Nd/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629150937; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=qVnfxEsUvKDG61lYNONZwOFsWcyYZfFvYajci0B6BZQ=; b=QVV5L/oEs3+QjWXbGyjUecfFQTY8Hd1DK/TBO1OECwfeJ0hkKGyQTGEUvwPyb4+QpUebqUZ3ugYaYfljnLAB/Ve3igT30yJvPznKLdiet+5dorh8R33eUCUz4H9aO5Z0rxdx3HXVj6YveV3J1NQCWaa/hLZ8LmSmPp69Wc0i+qA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79391+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16291509376668.019100319160998; Mon, 16 Aug 2021 14:55:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4dcCYY1788612x2s4JPrALZw; Mon, 16 Aug 2021 14:55:37 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.31227.1629150936433545725 for ; Mon, 16 Aug 2021 14:55:36 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="301531423" X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; d="scan'208";a="301531423" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 14:55:34 -0700 X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; d="scan'208";a="519914266" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.255.228.201]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 14:55:34 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty , Benjamin Doron , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Default for PeciC10Reset should be 1 Date: Mon, 16 Aug 2021 14:53:44 -0700 Message-Id: <20210816215344.29742-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: pevaRu5NdldMh30OjRisQCfox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1629150937; bh=XbJb7TB2Sny2qap1gyFRzjneHy5svos0k7kJnxn6K8I=; h=Cc:Date:From:Reply-To:Subject:To; b=B5wXfEeFhgvxmNCKYGDaDN4hsu+N6nuNEJywLui8spqIMgnor5V7hmlBxzgktff8ZW2 7uWa+dO8kPUhKuQ5Oiu5swLeID6mJcsLbkA1bGgCqphywPyEjOQDWuE1Fg5hUwSXlxlUW 9aQZxq+STmXSlW+Id26f8MjKctRYeAEfz84= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1629150939090100001 Content-Type: text/plain; charset="utf-8" The default value for CpuConfigLibPreMemConfig->PeciC10Reset should be 1 so that Peci Reset on C10 exit is disabled. Other bug fixes in KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c 1. PCI configuration space can only be read 32-bits at a time. Converted MmioRead64 to MmioRead32. 2. Added a RShiftU64() call to prevent compiler instrinsics from being inserted. Since this is a 64-bit integer shift done in IA-32 mode it is possible for intrinsic calls to be added. Cc: Chasel Chiu Cc: Sai Chaganty Cc: Benjamin Doron Cc: Michael Kubacki Signed-off-by: Nate DeSimone Reviewed-by: Chasel Chiu --- .../PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 30 +++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPr= eMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCp= uPolicyLibPreMem/PeiCpuPolicyLib.c index 35041322a7..9a334d8ec2 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pe= iCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pe= iCpuPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -45,13 +45,31 @@ LoadCpuConfigLibPreMemConfigDefault ( CpuConfigLibPreMemConfig->BootFrequency =3D 1; // Maximum n= on-turbo Performance CpuConfigLibPreMemConfig->ActiveCoreCount =3D 0; // All cores= active CpuConfigLibPreMemConfig->VmxEnable =3D CPU_FEATURE_ENABLE; - CpuConfigLibPreMemConfig->CpuRatio =3D ((AsmReadMsr64 (MSR_PLATFORM_INFO= ) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); + CpuConfigLibPreMemConfig->CpuRatio =3D RShiftU64 (AsmReadMsr64 (MSR_PLAT= FORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK; + /// /// FCLK Frequency /// - CpuFamily =3D GetCpuFamily(); - CpuSku =3D GetCpuSku(); - MchBar =3D MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_S= A_MCHBAR) &~BIT0; + CpuFamily =3D GetCpuFamily (); + CpuSku =3D GetCpuSku (); + + DEBUG_CODE_BEGIN (); + /// + /// Ensure the upper 7-bits [38:32] of MCHBAR are zero so we can access = MCHBAR in 32-bit mode. + /// + MchBar =3D MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_S= A_MCHBAR + 0x4) & 0x7F; + if (MchBar !=3D 0x0) { + DEBUG (( + DEBUG_ERROR, + "Error: [%a]:[%dL] MCHBAR configured to >4GB\n", + __FUNCTION__, + __LINE__ + )); + } + ASSERT (MchBar =3D=3D 0x0); + DEBUG_CODE_END (); + + MchBar =3D MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_S= A_MCHBAR) &~BIT0; if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, = SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF)) { PegDisabled =3D MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CP= L_OFFSET) & BIT3; } else { @@ -67,6 +85,8 @@ LoadCpuConfigLibPreMemConfigDefault ( } else { CpuConfigLibPreMemConfig->FClkFrequency =3D 0; // 800MHz } + + CpuConfigLibPreMemConfig->PeciC10Reset =3D 1; // Disables Peci Reset on= C10 exit } =20 /** --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79391): https://edk2.groups.io/g/devel/message/79391 Mute This Topic: https://groups.io/mt/84935132/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-