From nobody Wed May 1 06:14:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79328+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79328+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1629086566; cv=none; d=zohomail.com; s=zohoarc; b=HWZXKxl+Vpy8OMEgU40SDsUOChDMavHpkV3B/I8aT4zDkk20Z2MaVr71xygevkH9Wb5PzxWyTrmoodhmdMEkRBXtfG/mDAFMqJUTHkIdHM0kdSOYOYt7Lga1e3v1K9C//1OiH40wAwoo/bj+bZG3qAjNYY22cmsXfADm1RaXiI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1629086566; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=sjKjzKHoJRDEGzbtwDv3SU6GTUbMSz4xxBIcwmKwT6E=; b=TePY7N3O8azy9y6phb+aEXwj6EHOaDPiqlkAyXovRTK7IA1/fKb6oLrf4Vm4CHsUqe+cDf7ClcsXEpK6h9bnYdmIDyt52VoaDGyCkHzJnPuvziQzqY2ngj6cVolUZQT/S8JWjbYFM0UY5+/6gJA1DRweED1eyyo6h1qklnkVIbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79328+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1629086566744377.7463552970836; Sun, 15 Aug 2021 21:02:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FFaVYY1788612x03PSpEipkQ; Sun, 15 Aug 2021 21:02:46 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.19894.1629086565268162236 for ; Sun, 15 Aug 2021 21:02:46 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215820122" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215820122" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:02:43 -0700 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="448315774" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.115.121]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:02:43 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty , Benjamin Doron , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Default for PeciC10Reset should be 1 Date: Sun, 15 Aug 2021 21:02:38 -0700 Message-Id: <20210816040238.29564-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: dlqcvdMmgTZRK3YNpOV7qJ8wx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1629086566; bh=3LNfMsUKBcj+VC8V9Ga/dDhj6NFX5U/uUsN+DIHKZY8=; h=Cc:Date:From:Reply-To:Subject:To; b=ayZ9HDrsvqY06aR9P5GeWPJN35AtjB0y0Wb2yQTFVbFpWt1B+Rw+RHMhwcyFni/piTc C+Lb7rKIjRfDEiNdqyqItgUaWsTpAC0NW4PALcPtUfw2xTo5LGlBhR0NMj4nNdjA1IbxY /UemN+nuzyu0zhi2z7nQM32r8uXiJ7TzsP0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1629086568426100002 Content-Type: text/plain; charset="utf-8" The default value for CpuConfigLibPreMemConfig->PeciC10Reset should be 1 so that Peci Reset on C10 exit is disabled. Other bug fixes in KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c 1. PCI configuration space can only be read 32-bits at a time. Converted MmioRead64 to MmioRead32. 2. Added a RShiftU64() call to prevent compiler instrinsics from being inserted. Since this is a 64-bit integer shift done in IA-32 mode it is possible for intrinsic calls to be added. Cc: Chasel Chiu Cc: Sai Chaganty Cc: Benjamin Doron Cc: Michael Kubacki Signed-off-by: Nate DeSimone Reviewed-by: Chasel Chiu Reviewed-by: Michael Kubacki > Reviewed-by: Michael Kubacki --- .../Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPr= eMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCp= uPolicyLibPreMem/PeiCpuPolicyLib.c index 35041322a7..85baa46208 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pe= iCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pe= iCpuPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -45,13 +45,14 @@ LoadCpuConfigLibPreMemConfigDefault ( CpuConfigLibPreMemConfig->BootFrequency =3D 1; // Maximum n= on-turbo Performance CpuConfigLibPreMemConfig->ActiveCoreCount =3D 0; // All cores= active CpuConfigLibPreMemConfig->VmxEnable =3D CPU_FEATURE_ENABLE; - CpuConfigLibPreMemConfig->CpuRatio =3D ((AsmReadMsr64 (MSR_PLATFORM_INFO= ) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); + CpuConfigLibPreMemConfig->CpuRatio =3D RShiftU64 (AsmReadMsr64 (MSR_PLAT= FORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK; + /// /// FCLK Frequency /// CpuFamily =3D GetCpuFamily(); CpuSku =3D GetCpuSku(); - MchBar =3D MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_S= A_MCHBAR) &~BIT0; + MchBar =3D MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_S= A_MCHBAR) &~BIT0; if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, = SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF)) { PegDisabled =3D MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CP= L_OFFSET) & BIT3; } else { @@ -67,6 +68,8 @@ LoadCpuConfigLibPreMemConfigDefault ( } else { CpuConfigLibPreMemConfig->FClkFrequency =3D 0; // 800MHz } + + CpuConfigLibPreMemConfig->PeciC10Reset =3D 1; // Disables Peci Reset on= C10 exit } =20 /** --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79328): https://edk2.groups.io/g/devel/message/79328 Mute This Topic: https://groups.io/mt/84916474/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-