From nobody Sun May 5 21:12:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79063+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79063+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1628633053; cv=none; d=zohomail.com; s=zohoarc; b=MHRE2YCsylqWpQaP53g++6NUEof2itPlmfWlRM6tDz2DPsmg+uVEzeBtOHgk70N/HTyxn+vi53qY5DoGXXTj8xda7xGgBRgFwf1pxAscIBHIXe9FtZvoGPvDcWnA27CK8E1e/ag4ZPEYmaQlg6s+yS908Ee/dzrY11fE23mWU2c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628633053; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=7s6dDhxZ1JGpiXguY4u4jRjV9HPO6St4ofCiSP/XKDA=; b=RgZ6/TGGvPcleaCPFFzEzTipCPf753jFLTQ8V6XmFuTQQS4XClv3pU0CP7FYSeE26Mh5YrSbTAt5W//fagOga6FeVx0bz0g5WOhUvu90v8I9+ZFVCjBgCP123FwflftIzKA6d5x5VubDxe3v7Pu86o1yV3ly1QFz2GV9dYM8CTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79063+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628633053240559.5606939136425; Tue, 10 Aug 2021 15:04:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pQJzYY1788612xZB8eKCETcN; Tue, 10 Aug 2021 15:04:12 -0700 X-Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web08.1629.1628633051394230223 for ; Tue, 10 Aug 2021 15:04:12 -0700 X-Received: by mail-lj1-f175.google.com with SMTP id m9so986564ljp.7 for ; Tue, 10 Aug 2021 15:04:11 -0700 (PDT) X-Gm-Message-State: jae8aQSJHZJf0r88LcWIVW5dx1787277AA= X-Google-Smtp-Source: ABdhPJy9ui/UV36lPfZelEUt/SH9tsZbg+dA/6a96qh7eWgLSJPRf8VcSjkEGfmCwCQH/SEvCbdbhg== X-Received: by 2002:a2e:bc1a:: with SMTP id b26mr20936649ljf.132.1628633049445; Tue, 10 Aug 2021 15:04:09 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id y3sm1984374ljj.121.2021.08.10.15.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Aug 2021 15:04:08 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH v2] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Date: Wed, 11 Aug 2021 00:04:03 +0200 Message-Id: <20210810220403.3504123-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628633052; bh=6L2HnsdbFpctYZW3LwA/mbcvP/3ONwQPEqWaVtGTrRQ=; h=Cc:Date:From:Reply-To:Subject:To; b=sYHoXfhAM/T97ztyh1M0VsQh5RRUoYZ5AHPRv+PlcA+Zo2k3R64Ju+BBQgAAtg6Gi78 0GyCK+OnYetNCCnO+oB9Y770uIpn/t1ALIdcfIDLnO5yZMNc3ppxvHpPI9oWwSlCKN1Sd Iv/UiNFwTTC7AtnSQWboOXi2js1Uzi0YC3E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628633054378100001 Content-Type: text/plain; charset="utf-8" BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas --- Changelog: v1->v2: * Rebase on top of tree Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 60 ++++++= ++++++++++ 5 files changed, 280 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 7931dc3ef8..a7d1c76e07 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -92,6 +112,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -123,6 +147,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -151,6 +179,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -170,6 +202,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -189,6 +225,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -208,6 +248,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -235,6 +279,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -261,6 +309,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -278,6 +330,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0101") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -312,6 +368,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -351,6 +411,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -429,6 +493,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -449,6 +517,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -475,6 +547,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index 8c098cd14c..7335e443c6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -21,21 +21,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -43,6 +59,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -68,6 +88,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -99,6 +123,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -127,6 +155,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -146,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -165,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -192,6 +232,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -218,6 +262,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -240,6 +288,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -318,6 +370,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -344,6 +400,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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