From nobody Sat May 4 20:14:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79014+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79014+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628570224; cv=none; d=zohomail.com; s=zohoarc; b=YJKTEv2nuCS7oN+Q6MqptsicbQg7lOcd1PZLap3+/BzNRlLmx1u8nB9paw8Q3KZmkyBDZ7UG+Edk2TFnqSrNQfeihijSuqDpKTQMev+hpLxmgeKyS+cu8aktSAhH24+PJhEWeHi2i97ChmeEdw8I8blkgAXW+rA610kuxLXGSUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628570224; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=/Ix3/ROZLxEg+6H57efDywiHm0bfAmzQKGHe1e8Qkxw=; b=dEBzdjVv7bA0WGXB8/0MuecqtjgjfPJAUynCdoj4JvywatlTddk+Qgp9RNq2X5cuVGcJXGKHeODRzeLOvO+HuBmJF/dy0/6yo3BP9OMP0IJhljfKKjN7vnCVJ1u4Y2RtYdDTM13bdIP9jVAplW6WDPQ6YDtamiUpuFYrt2zFhhc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79014+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628570224741595.8990398083795; Mon, 9 Aug 2021 21:37:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id lX75YY1788612xEg2uTBgMt1; Mon, 09 Aug 2021 21:37:04 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.3952.1628570223230878935 for ; Mon, 09 Aug 2021 21:37:03 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="214562944" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="214562944" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 21:37:02 -0700 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="421704789" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.209.34.61]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 21:37:02 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki , Benjamin Doron Subject: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Update SA_MISC_PEI_PREMEM_CONFIG Date: Mon, 9 Aug 2021 21:36:54 -0700 Message-Id: <20210810043654.26833-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: X84w7HyberyZXYLqCDiti1nox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628570224; bh=nNSC1dXZy6wcgGUMQc743JJBDdJa/XtVcT4MgS/uo/g=; h=Cc:Date:From:Reply-To:Subject:To; b=JzS9Y2QqBG1TAwQN7i4sSmdB8IvFltdUsDH0qah5pBHnqF2jlYrksC7oKhmhvq7L1tK Vpm2WdAnrCD+LE1Nx3R4tJoObkmgv058//V9zBRPxvJ16b34NcfesKS1sjzvDTGgWO3ad 3K5RyW5il5H64pow+E5klwhUyot09EzYThc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628570226306100001 Content-Type: text/plain; charset="utf-8" Updates SA_MISC_PEI_PREMEM_CONFIG from revision 1 to revision 3. Add initialization of the policy values. Cc: Chasel Chiu Cc: Michael Kubacki Cc: Benjamin Doron Signed-off-by: Nate DeSimone Reviewed-by: Chasel Chiu --- .../KabylakeRvp3/OpenBoardPkg.dsc | 24 +++--- .../PeiSiliconPolicyUpdateLib.c | 39 +++++++++- .../PeiSiliconPolicyUpdateLib.inf | 9 ++- .../ConfigBlock/SaMiscPeiPreMemConfig.h | 77 ++++++++++++++++++- .../Library/PeiSaPolicyLib/PeiSaPolicyLib.c | 37 ++++++++- 5 files changed, 169 insertions(+), 17 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 8523ab3f4f..f64555e391 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -182,17 +182,6 @@ # Board-specific ####################################### PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 - # - # FSP API mode - # - SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf -!else - # - # FSP Dispatch mode and non-FSP build (EDK2 build) - # - SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf -!endif =20 [LibraryClasses.IA32.SEC] ####################################### @@ -200,6 +189,7 @@ ####################################### TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicy= UpdateLibNull/SiliconPolicyUpdateLibNull.inf =20 [LibraryClasses.common.PEIM] ####################################### @@ -222,6 +212,18 @@ ####################################### # Board Package ####################################### +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode + # + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf +!endif + # Thunderbolt !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/Pe= iSiliconPolicyUpdateLib.c index 5cc7c03c61..2dce9be63c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -1,7 +1,7 @@ /** @file Provides silicon policy update library functions. =20 -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -398,6 +398,8 @@ SiliconPolicyUpdatePreMem ( SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; VOID *Buffer; + UINTN VariableSize; + VOID *MemorySavedData; UINT8 SpdAddressTable[4]; =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); @@ -417,6 +419,41 @@ SiliconPolicyUpdatePreMem ( // Pass board specific SpdAddressTable to policy // CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) Spd= AddressTable, (sizeof (UINT8) * 4)); + + // + // Set size of SMRAM + // + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm = and fast boot paths. + // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI a= dded in FSP 2.1, hence + // the platform specific S3DataPtr must be used instead. + // + VariableSize =3D 0; + MemorySavedData =3D NULL; + Status =3D PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHob= Guid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + if (!EFI_ERROR (Status)) { + MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData; + } + + // + // In FSP Dispatch Mode these BAR values are initialized by SiliconP= olicyInitPreMem() in + // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitP= reMem.c; this function calls + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to i= nitialize all Config Blocks + // with default policy values (including these BAR values.) PEI_PREM= EM_SI_DEFAULT_POLICY_INIT_PPI + // is implemented in the FSP. Make sure the value that FSP is using = matches the value we are using. + // + ASSERT (PcdGet64 (PcdMchBaseAddress) <=3D 0xFFFFFFFF); + ASSERT (MiscPeiPreMemConfig->MchBar =3D=3D (UINT32) PcdGet64 (PcdM= chBaseAddress)); + ASSERT (MiscPeiPreMemConfig->SmbusBar =3D=3D PcdGet16 (PcdSmbusBaseA= ddress)); } MemConfigNoCrc =3D NULL; Status =3D GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &= MemConfigNoCrc); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index 97ec70f611..5c2da68bf9 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -1,7 +1,7 @@ ### @file # Component information file for silicon policy update library # -# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -11,7 +11,7 @@ INF_VERSION =3D 0x00010005 BASE_NAME =3D PeiSiliconPolicyUpdateLib FILE_GUID =3D 14F5D83D-76A5-4241-BEC5-987E70E233D5 - MODULE_TYPE =3D BASE + MODULE_TYPE =3D PEIM VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SiliconPolicyUpdateLib =20 @@ -33,6 +33,7 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec KabylakeOpenBoardPkg/OpenBoardPkg.dec @@ -49,11 +50,15 @@ gHsioPciePreMemConfigGuid ## CONSUMES gHsioSataPreMemConfigGuid ## CONSUMES gSaMiscPeiPreMemConfigGuid ## CONSUMES + gFspNonVolatileStorageHobGuid ## CONSUMES =20 [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gSiPkgTokenSpaceGuid.PcdMchBaseAddress + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gSiPkgTokenSpaceGuid.PcdTsegSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlo= ck/SaMiscPeiPreMemConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/I= nclude/ConfigBlock/SaMiscPeiPreMemConfig.h index 4aa02e3142..2ed587f425 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi= scPeiPreMemConfig.h +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi= scPeiPreMemConfig.h @@ -1,7 +1,7 @@ /** @file Policy details for miscellaneous configuration in System Agent =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -14,18 +14,91 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SA_MC_MAX_SOCKETS 4 #endif =20 -#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 1 +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3 =20 /** This configuration block is to configure SA Miscellaneous variables duri= ng PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, IedSize, MmioSize required etc. Revision 1: - Initial version. + Revision 2: + - Added SgDelayAfterOffMethod, SgDelayAfterLinkEnable and SgGenSpeedChan= geEnable. + Revision 3: + - Added BdatTestType and BdatSchema. **/ typedef struct { CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory DIMMs' = SPD address for reading SPD data. example: SpdAddressTable[0]=3D0xA2(C0D= 0), SpdAddressTable[1]=3D0xA0(C0D1), SpdAddressTable[2]=3D0xA2(C1D0), SpdAd= dressTable[3]=3D0xA0(C1D1) + VOID *S3DataPtr; ///< Offset 32 Memory data sa= ve pointer for S3 resume. The memory space should be allocated and filled w= ith proper S3 resume data on a resume path UINT32 MchBar; ///< Offset 36 Address of Sys= tem Agent MCHBAR: 0xFED10000 + UINT32 DmiBar; ///< Offset 40 Address of Sys= tem Agent DMIBAR: 0xFED18000 + UINT32 EpBar; ///< Offset 44 Address of Sys= tem Agent EPBAR: 0xFED19000 + UINT32 SmbusBar; ///< Offset 48 Address of Sys= tem Agent SMBUS BAR: 0xEFA0 + UINT32 GdxcBar; ///< Offset 52 Address of Sys= tem Agent GDXCBAR: 0xFED84000 + /** + Offset 56 Size of TSEG in bytes. (Must be power of 2) + 0x400000: 4MB for Release build (When IED enabled, it will be 8= MB) + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disab= led) + **/ + UINT32 TsegSize; + UINT32 EdramBar; ///< Offset 60 Address of Sys= tem Agent EDRAMBAR: 0xFED80000 + /** + Offset 64 + (Test) Size of IED region in bytes. + 0 : IED Disabled (no memory occupied) + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) + Note: Enabling IED may also enlarge TsegSize together. + **/ + UINT32 IedSize; + UINT8 UserBd; ///< Offset 68 0=3DMobile/= Mobile Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Server + UINT8 SgMode; ///< Offset 69 SgMode: 0= =3DDisabled, 1=3DSG Muxed, 2=3DSG Muxless, 3=3DPEG + UINT16 SgSubSystemId; ///< Offset 70 Switchable Gra= phics Subsystem ID: 2212 + UINT16 SgDelayAfterPwrEn; ///< Offset 72 Dgpu Delay aft= er Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D3= 00 microseconds + UINT16 SgDelayAfterHoldReset; ///< Offset 74 Dgpu Delay aft= er Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100= microseconds + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 76:= 0 :1=3DSkip External Gfx Device Scan; 0=3DScan for external graphics dev= ices. Set this policy to skip External Graphics card scanning if the pl= atform uses Internal Graphics only. + UINT32 BdatEnable:1; ///< (Test) OFfset 76:= 1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=3DF= ALSE, 1=3DTRUE\n Please refer to the MRC documentation for more details + UINT32 TxtImplemented:1; ///< OFfset 76:2 :This field = currently is used to tell MRC if it should run after TXT initializatoin com= pleted: 0=3DRun without waiting for TXT, 1=3DRun after TXT initializ= ation by callback + /** + Offset 76:3 : + (Test) Scan External Discrete Graphics Devices for Legacy Only V= GA OpROMs + + When enabled, if the primary graphics device is an external discrete gr= aphics device, Si will scan the + graphics device for legacy only VGA OpROMs. If the primary graphics de= vice only implements legacy VBIOS, then the + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1. + + This is intended to ease the implementation of a BIOS feature to automa= tically enable CSM if the Primary Gfx device + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling = CSM won't result in no video being displayed. + This is useful for platforms that implement PCIe slots that allow the e= nd user to install an arbitrary Gfx device. + + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is i= gnored otherwise. + + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defaul= t) + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM + **/ + UINT32 ScanExtGfxForLegacyOpRom:1; + UINT32 RsvdBits0 :28; ///< OFfset 76:4 :Reserved fo= r future use + UINT8 LockPTMregs; ///< (Test) Offset 80 = Lock PCU Thermal Management registers: 0=3DFALSE, 1=3DTRUE + UINT8 BdatTestType; ///< Offset 81 When BdatEnabl= e is set to TRUE, this option selects the type of data which will be popula= ted in the BIOS Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMarg= in 2D. + UINT8 BdatSchema; ///< Offset 82 When BdatEnabl= e is set to TRUE, this option selects the BDAT Schema version which will be= used to format BDAT Test results: 0=3DSchema 2, 1=3DSchema 6B + UINT8 Rsvd1; ///< Offset 83 Reserved for f= uture use + /** + Offset 84 : + Size of reserved MMIO space for PCI devices\n + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB, + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected. + **/ + UINT16 MmioSize; + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base addre= ss of a Reserved memory buffer allocated in previous boot for S3 resume use= d. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT64 SystemMemoryLength; ///< Offset 96 Total system m= emory length from previous boot, this is required for S3 resume. Originally= it is retrieved from AcpiVariableCompatibility variable. + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of a= Reserved memory buffer allocated in previous boot for S3 resume used. Orig= inally it is retrieved from AcpiVariableCompatibility variable. + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 108= Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanEx= tGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 112= Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom fea= ture. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >=3D 16MB! + UINT16 SgDelayAfterOffMethod; ///< Offset 128 Dgpu Delay af= ter off method is called using Setup option: 0=3DMinimal, 1000=3DMaximum, <= b>300=3D300 microseconds + UINT16 SgDelayAfterLinkEnable; ///< Offset 130 Delay after l= ink enable method is called using Setup option: 0=3DMinimal, 1000=3DMaximum= , 100=3D100 microseconds + UINT8 SgGenSpeedChangeEnable; ///< Offset 132 Enable/Disabl= e Gen speed changes using Setup option: 0=3DDisable, 1=3DEnable + UINT8 Rsvd3[3]; ///< Offset 133 Reserved for = future use } SA_MISC_PEI_PREMEM_CONFIG; #pragma pack(pop) =20 diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPoli= cyLib/PeiSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Libra= ry/PeiSaPolicyLib/PeiSaPolicyLib.c index eb18d993e7..5210856346 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/P= eiSaPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/P= eiSaPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file provides services for PEI policy default initialization =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -19,6 +19,9 @@ extern EFI_GUID gMemoryConfigNoCrcGuid; extern EFI_GUID gGraphicsPeiConfigGuid; extern EFI_GUID gVtdConfigGuid; =20 +#define DEFAULT_OPTION_ROM_TEMP_BAR 0x80000000 +#define DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT 0xC0000000 + // // Function call to Load defaults for Individial IP Blocks // @@ -33,6 +36,38 @@ LoadSaMiscPeiPreMemDefault ( =20 DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Name =3D %g\n",= &MiscPeiPreMemConfig->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Header.HobLengt= h =3D 0x%x\n", MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength)); + + // + // Policy initialization commented out here is because it's the same wit= h default 0 and no need to re-do again. + // + MiscPeiPreMemConfig->LockPTMregs =3D 1; + + // + // Initialize the Platform Configuration + // + MiscPeiPreMemConfig->MchBar =3D (UINT32) PcdGet64 (PcdMchBa= seAddress); + MiscPeiPreMemConfig->DmiBar =3D 0xFED18000; + MiscPeiPreMemConfig->EpBar =3D 0xFED19000; + MiscPeiPreMemConfig->EdramBar =3D 0xFED80000; + MiscPeiPreMemConfig->SmbusBar =3D PcdGet16 (PcdSmbusBaseAddre= ss); + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); + MiscPeiPreMemConfig->GdxcBar =3D 0xFED84000; + + // + // Initialize the Switchable Graphics Default Configuration + // + MiscPeiPreMemConfig->SgDelayAfterHoldReset =3D 100; //100ms + MiscPeiPreMemConfig->SgDelayAfterPwrEn =3D 300; //300ms + MiscPeiPreMemConfig->SgDelayAfterOffMethod =3D 0; + MiscPeiPreMemConfig->SgDelayAfterLinkEnable =3D 0; + MiscPeiPreMemConfig->SgGenSpeedChangeEnable =3D 0; + + /// + /// Initialize the DataPtr for S3 resume + /// + MiscPeiPreMemConfig->S3DataPtr =3D NULL; + MiscPeiPreMemConfig->OpRomScanTempMmioBar =3D DEFAULT_OPTION_ROM_TE= MP_BAR; + MiscPeiPreMemConfig->OpRomScanTempMmioLimit =3D DEFAULT_OPTION_ROM_TE= MP_MEM_LIMIT; } =20 VOID --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79014): https://edk2.groups.io/g/devel/message/79014 Mute This Topic: https://groups.io/mt/84786791/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-