From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79006+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79006+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566583; cv=none; d=zohomail.com; s=zohoarc; b=IFEQym7+vPNDFMwm+zU7pfFTPEnmqKjsHPIOKxDRWMBp30/xmg29rzHiZd3hJ1SqpPFYcTQOZQy6+GjVYPKNtmbJCcxN+TROscuek2LLUf7eJFEHsd/KDP2hs0VltmMYSRFQASzQCQMh/GNHn/bkJSJe6lpWUOxKjav0qN/4mzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566583; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=c65M1KB6pN6HYD9rSTMYqGPjbV76t0FAmAHn5ZDwULQ=; b=lCqUEOWw0SubNxWWs6Z5DpnN3SeSh1z+6Ls4nVDENv7/2LFL/vt7Bvgx5mdNVb5GbAybRQkVuJQLCzJ1S58FiB1ozjVTSmHghLVRlIZF1LTUrW6rIVe29Pkzd3WCy5LCv6SyWPpZfT3dsOJOoBL6vYfx7RkuWIye32soQ80npHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79006+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628566583289783.5751900089077; Mon, 9 Aug 2021 20:36:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ebI7YY1788612xlSBLWXMCD7; Mon, 09 Aug 2021 20:36:22 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.3561.1628566581926532039 for ; Mon, 09 Aug 2021 20:36:22 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C3331042; Mon, 9 Aug 2021 20:36:21 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 433D63F70D; Mon, 9 Aug 2021 20:36:21 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH v2 1/6] Platform/RaspberryPi: Add XHCI/PCI selection menu Date: Mon, 9 Aug 2021 22:36:13 -0500 Message-Id: <20210810033618.5139-2-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: UsK1kDoy1vx0oBy0u8tFuHDnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566582; bh=6ZypNGBnowr43GArJvmWlRavAM0ZW6b+lA47Tite1wI=; h=Cc:Date:From:Reply-To:Subject:To; b=kUI/vFMZc/lo3R6FFkbRz9ixqh2tvF5neDng9yLjpoLp3aHp5hRVo7WivkwEV30CzyB B6p4yCM4f0nMhHLCXrexcLlV/2+cDLBzA0hMT63GBQeg9l4wAp31RAy0petTclKGXYHMJ +a6W81+XfJRZlcMCGCYNMxpWS9cDqowq2/8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566583888100004 Content-Type: text/plain; charset="utf-8" Arm has standardized a PCI SMC conduit that can be used to access the PCI config space in a standardized way. This functionality doesn't yet exist in many OS/Distro's. Lets add another advanced config item that allows the user to toggle between presenting the XHCI on the base RPi4 as a platform device, or presenting this newer PCIe conduit. The CM4 doesn't have an attached XHCI controller soldered to the PCIe, so PCIe mode is the default. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++++= ++++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 + .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++ Platform/RaspberryPi/Include/ConfigVars.h | 4 +++ Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++ Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++ Platform/RaspberryPi/RaspberryPi.dec | 1 + 8 files changed, 84 insertions(+) diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 9e78cb47ad..87f6b4e7bb 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[]; STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol; STATIC UINT32 mModelFamily =3D 0; STATIC UINT32 mModelInstalledMB =3D 0; +STATIC UINT32 mModelRevision =3D 0; =20 STATIC EFI_MAC_ADDRESS mMacAddress; =20 @@ -271,6 +272,40 @@ SetupVariables ( ASSERT_EFI_ERROR (Status); } =20 + if (mModelFamily >=3D 4) { + if (((mModelRevision >> 4) & 0xFF) =3D=3D 0x14) { + /* + * Enable PCIe by default on CM4 + */ + Status =3D PcdSet32S (PcdXhciPci, 2); + ASSERT_EFI_ERROR (Status); + } else { + Size =3D sizeof (UINT32); + Status =3D gRT->GetVariable (L"XhciPci", + &gConfigDxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || (Var32 =3D=3D 0)) { + /* + * Enable XHCI by default + */ + Status =3D PcdSet32S (PcdXhciPci, 0); + ASSERT_EFI_ERROR (Status); + } else { + /*=20 + * Enable PCIe + */ + Status =3D PcdSet32S (PcdXhciPci, 1); + ASSERT_EFI_ERROR (Status); + } + } + } else { + /*=20 + * Disable PCIe and XHCI + */ + Status =3D PcdSet32S (PcdXhciPci, 0); + ASSERT_EFI_ERROR (Status); + } + Size =3D sizeof (AssetTagVar); Status =3D gRT->GetVariable (L"AssetTag", &gConfigDxeFormSetGuid, @@ -888,6 +923,13 @@ ConfigInitialize ( DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\= n", mModelInstalledMB)); } =20 + Status =3D mFwProtocol->GetModelRevision (&mModelRevision); + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n", S= tatus)); + } else { + DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevisi= on)); + } + Status =3D SetupVariables (); if (Status !=3D EFI_SUCCESS) { DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status)); diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platfor= m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf index 4bb2d08550..e6e22ad82e 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf @@ -94,6 +94,7 @@ gRaspberryPiTokenSpaceGuid.PcdFanOnGpio gRaspberryPiTokenSpaceGuid.PcdFanTemp gRaspberryPiTokenSpaceGuid.PcdUartInUse + gRaspberryPiTokenSpaceGuid.PcdXhciPci =20 [Depex] gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni index 466fa852cb..5ec17072c3 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni @@ -57,6 +57,11 @@ #string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperatur= e" #string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C" =20 +#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe" +#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB pl= atform device or PCIe bridge" +#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI" +#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe" + #string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag" #string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asse= t Tag" =20 diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr index fa34eab809..18b3ec726e 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr @@ -56,6 +56,11 @@ formset name =3D FanTemp, guid =3D CONFIGDXE_FORM_SET_GUID; =20 + efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA, + attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, + name =3D XhciPci, + guid =3D CONFIGDXE_FORM_SET_GUID; + efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA, attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, name =3D SystemTableMode, @@ -212,6 +217,18 @@ formset default =3D 60, endnumeric; endif; + + suppressif ideqval XhciPci.Value =3D=3D 2; + grayoutif NOT ideqval SystemTableMode.Mode =3D=3D SYSTEM_TABLE_M= ODE_ACPI; + oneof varid =3D XhciPci.Value, + prompt =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT), + help =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP), + flags =3D NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRE= D, + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), val= ue =3D 0, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), val= ue =3D 1, flags =3D 0; + endoneof; + endif; + endif; #endif string varid =3D AssetTag.AssetTag, prompt =3D STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT), diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/Raspberry= Pi/Include/ConfigVars.h index 142317985a..a5b32b5284 100644 --- a/Platform/RaspberryPi/Include/ConfigVars.h +++ b/Platform/RaspberryPi/Include/ConfigVars.h @@ -77,6 +77,10 @@ typedef struct { } ADVANCED_FANTEMP_VARSTORE_DATA; =20 typedef struct { + UINT32 Value; +} ADVANCED_XHCIPCI_VARSTORE_DATA; + +typedef struct { #define SYSTEM_TABLE_MODE_ACPI 0 #define SYSTEM_TABLE_MODE_BOTH 1 #define SYSTEM_TABLE_MODE_DT 2 diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3= /RPi3.dsc index 1c8a5408e7..6ab5d1ae6d 100644 --- a/Platform/RaspberryPi/RPi3/RPi3.dsc +++ b/Platform/RaspberryPi/RPi3/RPi3.dsc @@ -520,6 +520,12 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode (not valid on rpi3) + # + # 0 - DISABLED + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4= /RPi4.dsc index dcf9bb5f11..babcbb2f41 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -536,6 +536,14 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode + # + # 0 - XHCI Enabled (default on !cm4) + # 1 - PCIe Enabled + # 2 - PCIe Enabled (default on cm4) + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/Ra= spberryPi.dec index 2ca25ff9e6..797be59274 100644 --- a/Platform/RaspberryPi/RaspberryPi.dec +++ b/Platform/RaspberryPi/RaspberryPi.dec @@ -71,3 +71,4 @@ gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021 + gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022 --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79006): https://edk2.groups.io/g/devel/message/79006 Mute This Topic: https://groups.io/mt/84786149/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79007+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79007+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566584; cv=none; d=zohomail.com; s=zohoarc; b=fEoCj3alfp0ZrSfsCuGkuZCNDUvuj2Y65QBswf7x5sydgwmZtLqqQsAHqeN4BumfHIbQXHYADcThbSQZ0Z5U72+KMFApdSQO1vhaE3DuwKUZGI5dzDeWp51D8d/o/2obwWJtyBVHN4c1mOSPlB38reNhBmZxU2SFxPMPeqEc5Gc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=I7NSIjqX2tI8zWg6VPB6sDCEQtEHX8ZLmFKBgos9NYk=; b=b0iS1LV/8dZb6dl/87m2glsp3hs2UCQvUa5M1AM0XkmUw+TtQfY8LWJkNcnKCZNobZ4jh/zCbK2IAeAJAbRO76MX2mvzp58cHsTatlnTUgDUdtSKPrOm8soblMHFF2CdF9FikZUL9TvUyvPCoMzutyTifOV63DwlIojZR+uT22w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79007+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162856658401564.45250174121452; Mon, 9 Aug 2021 20:36:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XknJYY1788612x4zrbuY4AnW; Mon, 09 Aug 2021 20:36:23 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.3584.1628566582979803760 for ; Mon, 09 Aug 2021 20:36:23 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A91046D; Mon, 9 Aug 2021 20:36:22 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 604CF3F70D; Mon, 9 Aug 2021 20:36:22 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH v2 2/6] Platform/RaspberryPi: Break XHCI into its own SSDT Date: Mon, 9 Aug 2021 22:36:14 -0500 Message-Id: <20210810033618.5139-3-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: LVcmDBtFl6XhgEQSOMoMehwax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566583; bh=Vrmf06HXQe+U4WpjovQ8boZKHy1sXerIr0mFRw8lktU=; h=Cc:Date:From:Reply-To:Subject:To; b=nwb09gh2zkoa2vIknmjwwXavLByIgJ2isWStPT4/VdeMh1rRIwO2MM3HQwhR8SJ2cDy z/VS/Nl2NhbM59WZXXGUfyQsDKFbh7vxqrPZfSwzVVCFMR6GRojCa7z4pssHcJ4fdtGi9 LoYQcC3xhR5te0wycYzcuRN/9e9eq1RxarE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566585852100010 Content-Type: text/plain; charset="utf-8" Lets prepare to switch between XHCI and PCI by moving the XHCI definition into its own SSDT. That way we can select it based on the menu settings. The resource producer/consumer flag is also corrected. Reviewed-by: Andrei Warkentin Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 + Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 -- Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++----= ---- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++ 4 files changed, 31 insertions(+), 16 deletions(-) diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index 1ddc9ca5fe..f3e8d950c1 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -38,6 +38,7 @@ SpcrPl011.aslc Pptt.aslc SsdtThermal.asl + Xhci.asl =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryP= i/AcpiTables/Dsdt.asl index 1ee6379f46..b594d50bdf 100644 --- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl +++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl @@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", = 2) Scope (\_SB_) { include ("Pep.asl") -#if (RPI_MODEL =3D=3D 4) - include ("Xhci.asl") -#endif =20 Device (CPU0) { diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryP= i/AcpiTables/Xhci.asl index bc3fea60f9..9b37277956 100644 --- a/Platform/RaspberryPi/AcpiTables/Xhci.asl +++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl @@ -9,6 +9,8 @@ =20 #include =20 +#include "AcpiTables.h" + /* * The following can be used to remove parenthesis from * defined macros that the compiler complains about. @@ -24,12 +26,17 @@ */ #define XHCI_REG_LENGTH 0x1000 =20 -Device (SCB0) { - Name (_HID, "ACPI0004") - Name (_UID, 0x0) - Name (_CCA, 0x0) +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) =20 - Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings /* * Container devices with _DMA must have _CRS, meaning SCB0 * to provide all resources that XHC0 consumes (except @@ -57,15 +64,15 @@ Device (SCB0) { Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) Return (RBUF) - } + } =20 - Name (_DMA, ResourceTemplate() { + Name (_DMA, ResourceTemplate() { /* * XHC0 is limited to DMA to first 3GB. Note this * only applies to PCIe, not GENET or other devices * next to the A72. */ - QWordMemory (ResourceConsumer, + QWordMemory (ResourceProducer, , MinFixed, MaxFixed, @@ -79,10 +86,10 @@ Device (SCB0) { , , ) - }) + }) =20 - Device (XHC0) - { + Device (XHC0) + { Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x0) // _UID: Unique ID Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute @@ -131,5 +138,7 @@ Device (SCB0) { Debug =3D "xHCI enable" Store (0x6, CMND) } - } -} + } // end XHC0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 87f6b4e7bb..7c5786303d 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdSdIsArasan), SsdtEmmcNameOpReplace }, +#if (RPI_MODEL =3D=3D 4) + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'), + 0, + PcdToken(PcdXhciPci), + NULL + }, +#endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), 0, --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79007): https://edk2.groups.io/g/devel/message/79007 Mute This Topic: https://groups.io/mt/84786150/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79008+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79008+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566585; cv=none; d=zohomail.com; s=zohoarc; b=TkCE+PxBXhxmf8P/9iEfLFT94IzoBiRsAL4qovadb5N4G3hm0Yh/Wbi6vq1/6rpgMnia5Emb3ogevrGkICKpjo7jdtDT4veRaCNhxPDCNwNQiTH4InEmmWwPYlRnt/vBTNmFBgsN+qAnfaXM/nd8B7QN8hZP4Og19QymwFvncGc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566585; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PfX0HX89Wf1bNnAesSeXobGHwIk/QLRwPzvSlgKSVdw=; b=QPyzeGcx4zgrqDnFyGkXhcA0BLRYRyfeJgIwSWzrLWtH00ADYRx9v6Uh9rhfG17b95omAsXt6mzICHJaRfIlUxX/PGEGBxsT0vuVwS05cOpV/KnpmoUzgg1BDAfOqJkbG5zw79Qofh0YaR1rigY4y2YzOrnTl6uVHXoafrBDp7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79008+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628566585236924.1661745975151; Mon, 9 Aug 2021 20:36:25 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id smVtYY1788612xbrg9JT5qn6; Mon, 09 Aug 2021 20:36:24 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.3562.1628566584071990273 for ; Mon, 09 Aug 2021 20:36:24 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B19511042; Mon, 9 Aug 2021 20:36:23 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C1183F70D; Mon, 9 Aug 2021 20:36:23 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH v2 3/6] Platform/RaspberryPi: Add PCIe SSDT Date: Mon, 9 Aug 2021 22:36:15 -0500 Message-Id: <20210810033618.5139-4-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: qr6UTSQUfwj3SbsdtD4qQMYgx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566584; bh=wfSHnOiH25bloxLlLlFFUEw/TM0/j/DtKR3jfHyDQ4c=; h=Cc:Date:From:Reply-To:Subject:To; b=e/rgFnTDeCwYwVskFBqx+iyCiQBNnI1qbR22qqT2/rMjARbYKov6GEJ9S4sifbjd/oK ce42aTgGCZR/CUG8F35afsRmbK++VEpUOPbi3EIySztREP5WTkv0PNOPCVlDkacuPSZE0 UTvBp+iNP08ZJJI1ntq/eEup/lGkiMEMdFg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566586011100014 Content-Type: text/plain; charset="utf-8" Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port on a machine without a MCFG it attempts to connect to the SMC conduit. The RPi definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/AcpiTables/Pci.asl | 209 +++++++++++++++++= ++++ Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 + 3 files changed, 218 insertions(+) create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index f3e8d950c1..da2a6db85f 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -39,6 +39,7 @@ Pptt.aslc SsdtThermal.asl Xhci.asl + Pci.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -59,6 +60,8 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl new file mode 100644 index 0000000000..31527d87b5 --- /dev/null +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl @@ -0,0 +1,209 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_W= INDOW) +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMI= O_LEN) +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM= _WIN) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define RT_REG_LENGTH 0x1000 + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x1) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { + // Container devices with _DMA must have _CRS,=20 + // meaning SCB0 to provide all resources that + // PCI0 consumes (except interrupts). + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, RT_REG_LENGTH - 1, MMBE) + Add (MMLE, RT_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + // PCIe can only DMA to first 3GB with early SOC's + // But we keep the restriction on the later ones + // To avoid DMA translation problems. + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // Mark the PCI noncoherent + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + Package (4) { 0x0000FFFF, 0, zero, 175 }, + Package (4) { 0x0000FFFF, 1, zero, 176 }, + Package (4) { 0x0000FFFF, 2, zero, 177 }, + Package (4) { 0x0000FFFF, 3, zero, 178 } + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + QWordMemory ( // 32-bit BAR Windows in 64-bit addr + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, //cacheable? is that right? + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_B= EGIN + 1, // SANITIZED_PCIE_MMIO_LEN += SANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_B= EGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN += 1 + ,,,MMI1,,TypeTranslation + ) + }) // end Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMI= E) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // end Method(_CRS) + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmw= are + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 7c5786303d..4c40820858 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdXhciPci), NULL }, + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'), + PcdToken(PcdXhciPci), + 0, + NULL + }, #endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79008): https://edk2.groups.io/g/devel/message/79008 Mute This Topic: https://groups.io/mt/84786151/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79009+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79009+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566586; cv=none; d=zohomail.com; s=zohoarc; b=DICh1IyjEex+tELyeiAhwETSQXa/HCmXY6R6ltP2g71V0A8YoddkjTVAsk0mSNvAfe5lOSSFFN3OEhXrLiUtWV6/vdJyQAnDat2e52BqqrCaXHkdyR6p+jsLuWHlSnuBXlL0vVA0jfhkmITJdh0bnpI7cX4cB/2T1k56Ge6AVbM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566586; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vVZ2jFXjqhxZpiZQ1S96MOq5/HPBVQe7+gH1IFJ2b94=; b=cNKKEz2OfDOW6nCMp9le1lSFikQfihR5U1uoBTPJTetyhqlcjE/+1LoxP/T+R9OaZjVGJ/EFDmvx1Qv3vuUk/uHjjS9+fvLt9yOcCNDmbQQYOhK4gW3c8HZQgDFnwP9e8np8KfP+vPvGPXkjxRPHd+TafxxaKdNd3MTHwb+Z87U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79009+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628566586225399.0411792585901; Mon, 9 Aug 2021 20:36:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7LZdYY1788612xbpngtlSKKY; Mon, 09 Aug 2021 20:36:25 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.3586.1628566585164239365 for ; Mon, 09 Aug 2021 20:36:25 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF7C26D; Mon, 9 Aug 2021 20:36:24 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 756B23F70D; Mon, 9 Aug 2021 20:36:24 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton , =?UTF-8?q?Ren=C3=A9=20Treffer?= Subject: [edk2-devel] [PATCH v2 4/6] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Date: Mon, 9 Aug 2021 22:36:16 -0500 Message-Id: <20210810033618.5139-5-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: Pgs9Jf5MnWnMzm36APLxiAhhx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566585; bh=0jIb6BMhsM8fCyQ4cPq2s7OE8EIgCUxO4ngkmtnmq80=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=TXIdtDHHDjgWwjf00WhO/q0+YXBTiAj13zHFjzzQlWQ2Haq+mFRWKjbrnYef3Bi8bbC vFUvvV1jSil5xZkuud9lw7BrUGSsHgrbsqzf+dkBt3DIL7douV81nIKKZIeS2kJwFfRnh JyRIYOpMu4bTDxVUin2UzPrpBze0IH9mNmQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566588045100018 Content-Type: text/plain; charset="utf-8" The CM4 has an actual PCIe slot, so the device filtering need to be a little less restrictive WRT busses with more than 1 device given that switches can now appear in the topology. Since it is possible to start numbering the busses with a non-zero value, the bus restriction should be based on the secondary side of the root port. This isn't likely but its better than hard-coding the limit. Suggested-by: Ren=C3=A9 Treffer Signed-off-by: Jeremy Linton --- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++---= ---- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 44ce3b4b99..6d15e82fa2 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 typedef enum { PciCfgWidthUint8 =3D 0, @@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; + UINT32 HostPortSec; =20 Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset */ @@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + HostPortSec =3D MmioRead8 (PCIE_REG_BASE + + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + /* - * Scan things out directly rather than translating the "bus" to a d= evice, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus <=3D HostPortSec)) { return 0xFFFFFFFF; } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79009): https://edk2.groups.io/g/devel/message/79009 Mute This Topic: https://groups.io/mt/84786152/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79010+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79010+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566586; cv=none; d=zohomail.com; s=zohoarc; b=GCfVG/2ECmrqVNPeykEIZsB9E9fPiiONdopc3d0cfHPGgbVZBNBiOCkVCPLPXJLmnkULP2o2y+dL7fjtMOYukwT3I86nt1JDEMq/kgHP2b1H8KmXkQEv9HIG1eQdDgrtvJeWB4U9AAOmRBm03yC0/a/SjEvn7z9qBTBfT2yZ6Kk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566586; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jMUAHCgtYaPWBxymiwDyk0p9jbPopfaaOPHyNkx5TNQ=; b=Ue/xd644/NkbxRlRkVBJhlDrKyjj8nC0iiqjaTDuQUVHKVnV/GMGaKvh2ygDOBceRUgg5gQH6isqI753JC7kuqFiy8/NWWs1UHJzfXqvdv7EfmXRObUf+v30UiPhTXO+yeOZHHnMybIO6PPpWXLojn4gAs6K+Lc5fCRaxjQy41A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79010+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628566586929347.47511694447815; Mon, 9 Aug 2021 20:36:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZpNzYY1788612xfu7zFHVycR; Mon, 09 Aug 2021 20:36:26 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.3538.1628566586124937640 for ; Mon, 09 Aug 2021 20:36:26 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C69BA113E; Mon, 9 Aug 2021 20:36:25 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C4EB3F70D; Mon, 9 Aug 2021 20:36:25 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH v2 5/6] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Date: Mon, 9 Aug 2021 22:36:17 -0500 Message-Id: <20210810033618.5139-6-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: ah3ebivaj77xNaOSnbyPZiFQx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566586; bh=DgDUTk/oKm6xiBgl+AIYqj2ONeaBWq/674OJz9tVQEU=; h=Cc:Date:From:Reply-To:Subject:To; b=HkSE8vtomTz1JKVXm6AdWD5WMI+VfLaF/4w0nXy26/G2+GD733mXIFhyhBdpQOZTM/f OOto4y1zVmgsxwfeHOXz1E/FWH7MuoDwVE67iMHD34rN7FYV2jl6FuPn4DInRKAHLnQ68 A4YGZj5u0HVKnDhEZcyy+OdRcH5SGuEPE9U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566588147100021 Content-Type: text/plain; charset="utf-8" The existing code fails to create/finish configuring the pcie subsystem if it fails to get a linkup. This is reasonable on the RPi4 because it generally won't happen, and the OS could not see the root port. Now that the OS can see the root port, its a bit odd if it only shows up when something is plugged into the first slot. Lets move the link up check into the config accessor where it will be used to restrict sending CFG TLP's out the port when nothing is plugged in. Thus avoiding a SERROR during probe. Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 ---= -- .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++= ++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n", D= ata, Timeout)); =20 - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Data)= ); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 6d15e82fa2..b627e5730b 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( return 0xFFFFFFFF; } =20 + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data= )); + return 0xFFFFFFFF; + } + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); mPciSegmentLastAccess =3D Address; } --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79010): https://edk2.groups.io/g/devel/message/79010 Mute This Topic: https://groups.io/mt/84786153/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 06:41:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79011+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79011+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628566588; cv=none; d=zohomail.com; s=zohoarc; b=Z10rcRMMzLc1AimI3U+oxeiSfp3JBaRaClbm0jNZGtgEvChcAxpDX7qJ3pzHgqf46tMD7OsUd+nSkxLgz7JazMKHji6yI2PKf08CxIsOp6gugwfazWRQkDxtOZZJ7qhfdP1MLm2banTpbZMGqMhcM53aZLqw9Bra9lhhn1kO18M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628566588; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Wjmu625UiYzBIqCGBPg6YC8hEfMYjwMT1WHCbxBmHNY=; b=nXfsGZl8v0JiYcE2eDiVD1YfrFYrSqeDBQzGpc3ICPgLqeKtslttXCzcywkX+RRPN+i4cG6MJEO99+PeCTZbZtwWm/8JO/EwitmRsevVjv8y1puAIlv3Ii7IgLlPs+DgLw4hohsx2n/ckMe613R+DD8UiabItLga0xscy88wwtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79011+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628566588179188.7360651587345; Mon, 9 Aug 2021 20:36:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CHWwYY1788612xLmHbtDt041; Mon, 09 Aug 2021 20:36:27 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.3587.1628566587141669196 for ; Mon, 09 Aug 2021 20:36:27 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0DA46D; Mon, 9 Aug 2021 20:36:26 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CF353F70D; Mon, 9 Aug 2021 20:36:26 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH v2 6/6] Platform/RaspberryPi: Enable NVMe boot on CM4 Date: Mon, 9 Aug 2021 22:36:18 -0500 Message-Id: <20210810033618.5139-7-jeremy.linton@arm.com> In-Reply-To: <20210810033618.5139-1-jeremy.linton@arm.com> References: <20210810033618.5139-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: hiKqPJNWOseaCSh6G9H7Bdd0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628566587; bh=bNNZsQueXJ6X1Lp5l2QZ8j1F/s+BCgdRZoUgmA7tJJA=; h=Cc:Date:From:Reply-To:Subject:To; b=Pierur/0u0tcm9ZjzlhMl+aZ87KXvV1EpSoGMTOvjrqr3aeR9wYg8ZIIw9CYJr/Vyml BKihgHwbm02z2Az3SumTb1xIdF4kYqYH4dH49gjp6/xKFfdQ5h0ALJkpXZi9gRnQG70jV IcWgVbFtYijIBljCJTcTjvIVnnMiXbs73TE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628566590122100025 Content-Type: text/plain; charset="utf-8" The CM4 has a number of carrier boards with PCIe slots. With the PCIe changes in place its quite possible to utilize a NVMe root device. Lets allow people to boot from it. Reviewed-by: Andrei Warkentin Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++ Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4= /RPi4.dsc index babcbb2f41..25c29a0fbf 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -754,6 +754,11 @@ } =20 # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # # UEFI application (Shell Embedded Boot Loader) # ShellPkg/Application/Shell/Shell.inf { diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RPi4= /RPi4.fdf index 3534cd3dc3..0c782d2f35 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.fdf +++ b/Platform/RaspberryPi/RPi4/RPi4.fdf @@ -283,6 +283,11 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf =20 # + # NVMe boot devices + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # # SCSI Bus and Disk Driver # INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79011): https://edk2.groups.io/g/devel/message/79011 Mute This Topic: https://groups.io/mt/84786154/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-