From nobody Mon Feb 9 16:35:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78858+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78858+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1628365060; cv=none; d=zohomail.com; s=zohoarc; b=mlApCNkk7RumDjIXvn7SOkvoNXTSWkG7HESCKol8RZJA9uJP9eyyLMxltsGj89EwJ17tjjhF4BVzVv8h2mkG358fnFNv4wV7CEZaypm0+5haqfTjTl2EZdM3fLN/0a1ewNVqBDHbuc5OllSbsqaViPXdmFeGV740TPAqUHqbcGc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628365060; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+ZJy8iFeRZ4d5DyFryk0GQwQHf5VIePdCEqX6QQ8Mgw=; b=kZ8bPhWk2LN8Zm4P5B+tcsnMOXBk3Qecbe3TObrUZXDpHOVFV7TSZ1TCyMhnU5aQOXB9+gASnGjrfM7fL1MTFwpA5I3PFIzWxcu4UY7a0Eqg+UpvLRTxl+JxhVJS5BQpAxw3Nq4OyEIjjY018NSaHwpEBtRsAtD6Xd0kNZk3+Yc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78858+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628365060088126.93296417088288; Sat, 7 Aug 2021 12:37:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QDsOYY1788612xQrqjKdF0fM; Sat, 07 Aug 2021 12:37:39 -0700 X-Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mx.groups.io with SMTP id smtpd.web10.2194.1628365058462750321 for ; Sat, 07 Aug 2021 12:37:39 -0700 X-Received: by mail-lj1-f177.google.com with SMTP id u13so17220898lje.5 for ; Sat, 07 Aug 2021 12:37:38 -0700 (PDT) X-Gm-Message-State: LzQsjAlW7AKLZuPQeWKYQnLvx1787277AA= X-Google-Smtp-Source: ABdhPJyWuiTPVcP7XpCYz1wR3EBdH752bKLqRkb0fX8EjcPTHSMBzjmdeakqidCGbiupG4Yf8PuHqw== X-Received: by 2002:a2e:580e:: with SMTP id m14mr10464726ljb.9.1628365056620; Sat, 07 Aug 2021 12:37:36 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id bq33sm103635lfb.88.2021.08.07.12.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Aug 2021 12:37:36 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH v2 3/3] SolidRun/Cn913xCEx7Eval: Add platform support Date: Sat, 7 Aug 2021 21:36:40 +0200 Message-Id: <20210807193641.3355697-4-mw@semihalf.com> In-Reply-To: <20210807193641.3355697-1-mw@semihalf.com> References: <20210807193641.3355697-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628365059; bh=J/KCUofZm+YaLKC4lUR2m3iyARuVQNTg7JGg1XvtH6o=; h=Cc:Date:From:Reply-To:Subject:To; b=p7cQOByyEkQurpO5SyRel2iEfNPFFalJJ/KB2hh022kKBb14RwWGuaG3HZLlL++ipSR umMvlP+aRpOVMGv5BNN0orPgi+KFgxOtAa2mA6oraO3N0oJLvnlEuSVsznHmtdFvla7OR K4zFKAXNLgqEowQU/9rHiHFkgownW6gma5E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628365061463100002 Content-Type: text/plain; charset="utf-8" This patch adds the required platform description files, along with the hardware configuration libraries, for the SolidRun CN913x CEx7 Evaluation Board. Supported interfaces: * SPI flash & memory-mapped variable storage access * uSD * eMMC * 7x PCIE root complex * USB * Networking: * 1Gbps RGMII via PHY * 2500Base-X via quad 1Gpbs switch * 5Gbps via SFP cage and PHY Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc = | 54 ++++ Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc = | 64 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc = | 64 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc = | 68 +++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc = | 57 ++++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.i= nf | 30 ++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.inf | 38 +++ Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h= | 31 +++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.h | 13 + Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c= | 294 ++++++++++++++++++++ Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni= tLib.c | 89 ++++++ Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc = | 17 ++ 12 files changed, 819 insertions(+) create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.inf create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.h create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo= ardDescriptionLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib= /NonDiscoverableInitLib.c create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc new file mode 100644 index 0000000000..ad0983087d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc @@ -0,0 +1,54 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# Copyright (c) 2021 Semihalf.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SGMII2 3.125 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc new file mode 100644 index 0000000000..c6b0cefa8d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc @@ -0,0 +1,64 @@ +## @file +# Component description file for the CN9131 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# Copyright (c) 2021 Semihalf.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|3 + + # CP115 #1 MPP + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 } + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0= x2, 0x8, 0x8, 0x9 } + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: SFI 5.15625 Gbps + # 3: SATA1 5 Gbps + # 4: PCIE1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc new file mode 100644 index 0000000000..34f9a3f2fb --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc @@ -0,0 +1,64 @@ +## @file +# Component description file for the CN9132 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# Copyright (c) 2021 Semihalf.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|4 + + # CP115 #2 MPP + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x0, 0x7, 0x7 } + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0= x2, 0x2, 0x8, 0x8, 0xFF } + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0= x0, 0x0, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + # ComPhy2 + # 0: PCIE0 5 Gbps + # 1: USB3_HOST0 5 Gbps + # 2: SFI 5.15625 Gbps + # 3: SATA1 5 Gbps + # 4: PCIE1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST= 0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0= } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc new file mode 100644 index 0000000000..17463c09c6 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc @@ -0,0 +1,68 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# Copyright (c) 2021 Semihalf.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|2 + + # APN807 MPP + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + + # CP115 #0 MPP + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0= x2, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0= xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + + # SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + + # RTC + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + + # Variable store + gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000 +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xEF3D0= 000 diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc new file mode 100644 index 0000000000..6cb82acb13 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc @@ -0,0 +1,57 @@ +## @file +# Component description file for the CN913x CEx7 Evaluation Board +# +# Copyright (c) 2021 Semihalf +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D Cn913xCEx7Eval + PLATFORM_GUID =3D 4e2ffdd1-c82e-497e-936b-76217e54848a + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k= .fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/SolidRun/Cn913xCEx7Eval/Cn91= 3xCEx7Eval.fdf.inc + CAPSULE_ENABLE =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +!include MdePkg/MdeLibs.dsc.inc +!include Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc +!include Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc + +[Components.common] + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf + +[Components.AARCH64] + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf + +[LibraryClasses.common] + NonDiscoverableInitLib|Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableI= nitLib/NonDiscoverableInitLib.inf + ArmadaBoardDescLib|Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/= BoardDescriptionLib.inf + +[PcdsFixedAtBuild.common] + #Platform description + gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun" + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Bo= ard" + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Board= DescriptionLib.inf new file mode 100644 index 0000000000..ea13ff7ad7 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.inf @@ -0,0 +1,30 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# Copyright (C) 2021, Semihalf
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn913xCEx7EvalBoardDescriptionLib + FILE_GUID =3D 97c47d82-b9b9-4bff-9175-3f26671efea6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaBoardDescLib + +[Sources] + BoardDescriptionLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf new file mode 100644 index 0000000000..c58ba8397a --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf @@ -0,0 +1,38 @@ +## @file +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+# Copyright (c) 2021, Semihalf. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D Cn913xCExEvalNonDiscoverableInitLib + FILE_GUID =3D 8e6a8766-df51-497f-9743-fc0d9170ced8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NonDiscoverableInitLib + +[Sources] + NonDiscoverableInitLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + MvGpioLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Depex] + gMarvellPlatformInitCompleteProtocolGuid diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.h b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe= scriptionLib.h new file mode 100644 index 0000000000..6e04c9cd9e --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.h @@ -0,0 +1,31 @@ +/** +* +* Copyright (C) 2021, Semihalf. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef BOARD_DESCRIPTION_LIB_H__ +#define BOARD_DESCRIPTION_LIB_H__ + +#define IO_WIN_ALR_OFFSET(WinId) (0xF06F0000 + 0x0 + (0x10 * (WinId= ))) +#define IO_WIN_AHR_OFFSET(WinId) (0xF06F0000 + 0x8 + (0x10 * (WinId= ))) +#define IO_WIN_CR_OFFSET(WinId) (0xF06F0000 + 0xC + (0x10 * (WinId= ))) +#define IO_WIN_ENABLE_BIT 0x1 +#define IO_WIN_ADDRESS_SHIFT 16 +#define IO_WIN_ADDRESS_MASK 0xFFFFFFF0 + +#define MCI0_TARGET_ID 0x0 +#define MCI1_TARGET_ID 0x1 +#define CP1_PCIE_WIN64_BASE 0x890000000 +#define CP1_PCIE_WIN64_SIZE 0x30000000 +#define CP1_PCIE_WIN64_ID 0x5 +#define CP2_PCIE_WIN64_BASE 0x8c0000000 +#define CP2_PCIE_WIN64_SIZE 0x30000000 +#define CP2_PCIE_WIN64_ID 0x6 + +#define CP0_GPIO1_DATA_OUT_REG 0xF2440140 +#define CP0_GPIO1_OUT_EN_REG 0xF2440144 +#define CP0_GPIO1_PIN_MASK (1 << 7) + +#endif diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.h b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi= b/NonDiscoverableInitLib.h new file mode 100644 index 0000000000..937b84b99d --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h @@ -0,0 +1,13 @@ +/** +* +* Copyright (c) 2021, Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef NON_DISCOVERABLE_INIT_LIB_H__ +#define NON_DISCOVERABLE_INIT_LIB_H__ + +#define CN913X_CEX7_AP_SDMMC_VCCQ_PIN 26 + +#endif diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.c b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe= scriptionLib.c new file mode 100644 index 0000000000..f5bb6302fe --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.c @@ -0,0 +1,294 @@ +/** +* +* Copyright (C) 2021, Semihalf. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "BoardDescriptionLib.h" + +STATIC +VOID +ConfigureIoWindow ( + UINT64 WinBaseAddress, + UINT64 WinSize, + UINTN WinId, + UINT32 WinTargetId + ) +{ + UINT32 AddressHigh; + UINT32 AddressLow; + UINT64 MaxAddress; + + /* Disable IO window. */ + MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), 0); + + /* Calculate the end address. */ + MaxAddress =3D (WinBaseAddress + WinSize - 1); + + AddressLow =3D (UINT32)((WinBaseAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WI= N_ADDRESS_MASK); + AddressLow |=3D IO_WIN_ENABLE_BIT; + AddressHigh =3D (UINT32)((MaxAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_A= DDRESS_MASK); + + /* Write start address and end address for IO window. */ + MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), AddressLow); + MmioWrite32 (IO_WIN_AHR_OFFSET(WinId), AddressHigh); + + /* Write window target. */ + MmioWrite32 (IO_WIN_CR_OFFSET(WinId), WinTargetId); +} + +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + /* + * Due to lack of sufficient number of IO windows registers, + * the CP1/CP2 PCIE configuration must be performed after the + * early firmware stages. Replace the MCI 0/1 indirect + * windows, which are no longer needed. + */ + ConfigureIoWindow ( + CP1_PCIE_WIN64_BASE, + CP1_PCIE_WIN64_SIZE, + CP1_PCIE_WIN64_ID, + MCI0_TARGET_ID + ); + + ConfigureIoWindow ( + CP2_PCIE_WIN64_BASE, + CP2_PCIE_WIN64_SIZE, + CP2_PCIE_WIN64_ID, + MCI1_TARGET_ID + ); + + /* Enable FAN */ + MmioAnd32 (CP0_GPIO1_DATA_OUT_REG, ~CP0_GPIO1_PIN_MASK); + MmioAnd32 (CP0_GPIO1_OUT_EN_REG, ~CP0_GPIO1_PIN_MASK); + + return EFI_SUCCESS; +} + +// +// GPIO Expander +// +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + /* No GPIO expanders on board */ + *GpioExpanders =3D NULL; + *GpioExpanderCount =3D 0; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] =3D { + { /* CP0 PCIE0 @0xF2600000 */ + .PcieDbiAddress =3D 0xF2600000, + .ConfigSpaceAddress =3D 0x800000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xFE, + .PcieIoTranslation =3D 0x80FF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xC0000000, + .PcieMmio32WinSize =3D 0x20000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x810000000, + .PcieMmio64WinSize =3D 0x80000000, + }, + { /* CP1 PCIE0 @0xF4600000 */ + .PcieDbiAddress =3D 0xF4600000, + .ConfigSpaceAddress =3D 0xE2000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xE2F00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xE3000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x890000000, + .PcieMmio64WinSize =3D 0x10000000, + }, + { /* CP1 PCIE1 @0xF4620000 */ + .PcieDbiAddress =3D 0xF4620000, + .ConfigSpaceAddress =3D 0xE4000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xE4F00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xE5000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x8A0000000, + .PcieMmio64WinSize =3D 0x10000000, + }, + { /* CP1 PCIE2 @0xF4640000 */ + .PcieDbiAddress =3D 0xF4640000, + .ConfigSpaceAddress =3D 0xE6000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xE6F00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xE7000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x8B0000000, + .PcieMmio64WinSize =3D 0x10000000, + }, + { /* CP2 PCIE0 @0xF6600000 */ + .PcieDbiAddress =3D 0xF6600000, + .ConfigSpaceAddress =3D 0xE9000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xE9F00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xEA000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x8C0000000, + .PcieMmio64WinSize =3D 0x10000000, + }, + { /* CP2 PCIE1 @0xF6620000 */ + .PcieDbiAddress =3D 0xF6620000, + .ConfigSpaceAddress =3D 0xEB000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xEBF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xEC000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x8D0000000, + .PcieMmio64WinSize =3D 0x10000000, + }, + { /* CP2 PCIE2 @0xF6640000 */ + .PcieDbiAddress =3D 0xF6640000, + .ConfigSpaceAddress =3D 0xED000000, + .HaveResetGpio =3D FALSE, + .PcieResetGpio =3D { 0 }, + .PcieBusMin =3D 0, + .PcieBusMax =3D 0xE, + .PcieIoTranslation =3D 0xEDF00000, + .PcieIoWinBase =3D 0x0, + .PcieIoWinSize =3D 0x10000, + .PcieMmio32Translation =3D 0, + .PcieMmio32WinBase =3D 0xEE000000, + .PcieMmio32WinSize =3D 0x1000000, + .PcieMmio64Translation =3D 0, + .PcieMmio64WinBase =3D 0x8E0000000, + .PcieMmio64WinSize =3D 0x10000000, + }, +}; + +/** + Return the number and description of PCIE controllers used on the platfo= rm. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfull= y. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers =3D mPcieController; + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe= scLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + TRUE, /* Xenon1v8Enabled */ + /* + * Force 4-bit bus width - work-around for non + * functional HS400 mode. + */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc =3D mSdMmcDescTemplate; + *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.c b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi= b/NonDiscoverableInitLib.c new file mode 100644 index 0000000000..18312ac403 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c @@ -0,0 +1,89 @@ +/** +* +* Copyright (c) 2017, Linaro Ltd. All rights reserved. +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* Copyright (c) 2021, Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "NonDiscoverableInitLib.h" + +STATIC +EFI_STATUS +EFIAPI +ConfigurePins ( + IN CONST MV_GPIO_PIN *VbusPin, + IN UINTN PinCount, + IN MV_GPIO_DRIVER_TYPE DriverType + ) +{ + EMBEDDED_GPIO_MODE Mode; + EMBEDDED_GPIO_PIN Gpio; + EMBEDDED_GPIO *GpioProtocol; + EFI_STATUS Status; + UINTN Index; + + Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _)); + return Status; + } + + for (Index =3D 0; Index < PinCount; Index++) { + Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0; + Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber); + GpioProtocol->Set (GpioProtocol, Gpio, Mode); + VbusPin++; + } + + return EFI_SUCCESS; +} + +STATIC CONST MV_GPIO_PIN mApSdMmcPins[] =3D { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP0_CONTROLLER0, + CN913X_CEX7_AP_SDMMC_VCCQ_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +ApSdMmcInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mApSdMmcPins, + ARRAY_SIZE (mApSdMmcPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + +NON_DISCOVERABLE_DEVICE_INIT +EFIAPI +NonDiscoverableDeviceInitializerGet ( + IN NON_DISCOVERABLE_DEVICE_TYPE Type, + IN UINTN Index + ) +{ + if (Type =3D=3D NonDiscoverableDeviceTypeSdhci && Index =3D=3D 0) { + return ApSdMmcInit; + } + + return NULL; +} diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc b/Plat= form/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc new file mode 100644 index 0000000000..6cf2be0b1e --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc @@ -0,0 +1,17 @@ +# +# Copyright (c) 2021 Semihalf +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-board additional content of the DXE phase firmware volume + + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf + + # DTB + INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf + + # ACPI support +!if $(ARCH) =3D=3D AARCH64 + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf +!endif --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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