From nobody Mon Apr 29 16:13:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78789+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78789+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628237793; cv=none; d=zohomail.com; s=zohoarc; b=ezK27gYKAieONVhKBlrNSD/MVVbDLYD7vWv3Fj2XShwT7xfPeSr4toEa4t1njxkZXhFa1ZFrVJV9sRMb0G7OZIybQ74c6Fk4VfwP3qclIMctc5FbRYfRN2nfovrwzgjOUoTqRjiCUOKezxIoluJ1XPVnyWly6DGQKSXRWrF7SBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628237793; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=nnbcM8ypf9QCummTZWghkQc7VPWIRxtfZt6TNE6PVIs=; b=bG0MeaEshyZMrgxyL1H7JlrcRNqyIfZfogo/lY9+zYdUnl/HX6w4eQg+bkg1FBlqZHU4L6+BNmuMYOAeuuaosWb07Z4M1omz4+pbCxOZ6515gcdbVMDEfl34jc2V8IgRjc7bDaTuZDeWfvQMkLNw3nQ8swhLBeBfJqPhXOs6b6k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78789+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628237793090291.3768399815473; Fri, 6 Aug 2021 01:16:33 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7lJOYY1788612xKQxbl4UNlD; Fri, 06 Aug 2021 01:16:32 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.2218.1628237791800744519 for ; Fri, 06 Aug 2021 01:16:32 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10067"; a="236307489" X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="236307489" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2021 01:16:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="669332885" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.182.63]) by fmsmga006.fm.intel.com with ESMTP; 06 Aug 2021 01:16:29 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Guo Dong , Maurice Ma , Benjamin You Subject: [edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader Date: Fri, 6 Aug 2021 16:16:26 +0800 Message-Id: <20210806081626.802-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: pXThUCyvMcspAvWkpny9yeAkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628237792; bh=Rs4R87H7noYox4XNQwyKMSw5n55WPBbiXHR2ygQQb8o=; h=Cc:Date:From:Reply-To:Subject:To; b=vRP7EG+ywcQW6Tq4f3Rb7vQKIOlx36+PG7syPNcAKjAw67n3flYH810Gju+xELgnPQm 8NJQ8FFFMIgzoTj/ObuwxE0rSwz/GCSarQPAeRMYt8n1jFbEvfO3K0MY80rI2ArvVS3h9 tBG+QV+gxOfdSkfvWs1zlD0Yyla/52R3rBU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628237794088100003 Content-Type: text/plain; charset="utf-8" The patch removes the dep on PcdUse5LevelPageTable. Now the payload inherits the 5-level paging setting from bootloader in IA-32e mode and uses 4-level paging in legacy protected mode. This fix the potential issue when bootloader enables 5-level paging but 64bit payload sets 4-level page table to CR3 resulting CPU exception because PcdUse5LevelPageTable is FALSE. Signed-off-by: Ray Ni Cc: Guo Dong Cc: Ray Ni Cc: Maurice Ma Cc: Benjamin You Reviewed-by: Guo Dong Reviewed-by: Maurice Ma --- .../UefiPayloadEntry/UefiPayloadEntry.inf | 1 - .../UniversalPayloadEntry.inf | 1 - .../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++----------- 3 files changed, 16 insertions(+), 24 deletions(-) diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPay= loadPkg/UefiPayloadEntry/UefiPayloadEntry.inf index 8d42925fcd..9b6fab66a1 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf +++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf @@ -80,7 +80,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES =20 diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/Ue= fiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf index 416a620598..aae62126e9 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf +++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf @@ -85,7 +85,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES - gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES =20 diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayl= oadPkg/UefiPayloadEntry/X64/VirtualMemory.c index a1c4ad6ff4..9daa46c12c 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c @@ -15,7 +15,7 @@ 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:In= struction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 -Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -668,7 +668,6 @@ CreateIdentityMappingPageTables ( ) { UINT32 RegEax; - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 RegEdx; UINT8 PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAddress; @@ -687,7 +686,7 @@ CreateIdentityMappingPageTables ( UINTN TotalPagesNum; UINTN BigPageAddress; VOID *Hob; - BOOLEAN Page5LevelSupport; + BOOLEAN Enable5LevelPaging; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask; @@ -730,18 +729,16 @@ CreateIdentityMappingPageTables ( } } =20 - Page5LevelSupport =3D FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_F= EATURE_FLAGS_SUB_LEAF_INFO, NULL, - &EcxFlags.Uint32, NULL, NULL - ); - if (EcxFlags.Bits.FiveLevelPage !=3D 0) { - Page5LevelSupport =3D TRUE; - } - } + // + // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled. + // Because this code runs at both IA-32e (64bit) mode and legacy protect= ed (32bit) mode, + // below logic inherits the 5-level paging setting from bootloader in IA= -32e mode + // and uses 4-level paging in legacy protected mode. + // + Cr4.UintN =3D AsmReadCr4 (); + Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); =20 - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", = PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); + DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=3D%u 5LevelPaging=3D%u 1G= Page=3D%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport)); =20 // // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses @@ -749,7 +746,7 @@ CreateIdentityMappingPageTables ( // due to either unsupported by HW, or disabled by PCD. // ASSERT (PhysicalAddressBits <=3D 52); - if (!Page5LevelSupport && PhysicalAddressBits > 48) { + if (!Enable5LevelPaging && PhysicalAddressBits > 48) { PhysicalAddressBits =3D 48; } =20 @@ -784,7 +781,7 @@ CreateIdentityMappingPageTables ( // // Substract the one page occupied by PML5 entries if 5-Level Paging is = disabled. // - if (!Page5LevelSupport) { + if (!Enable5LevelPaging) { TotalPagesNum--; } =20 @@ -799,7 +796,7 @@ CreateIdentityMappingPageTables ( // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. // PageMap =3D (VOID *) BigPageAddress; - if (Page5LevelSupport) { + if (Enable5LevelPaging) { // // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. // @@ -819,7 +816,7 @@ CreateIdentityMappingPageTables ( PageMapLevel4Entry =3D (VOID *) BigPageAddress; BigPageAddress +=3D SIZE_4KB; =20 - if (Page5LevelSupport) { + if (Enable5LevelPaging) { // // Make a PML5 Entry // @@ -911,10 +908,7 @@ CreateIdentityMappingPageTables ( ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); } =20 - if (Page5LevelSupport) { - Cr4.UintN =3D AsmReadCr4 (); - Cr4.Bits.LA57 =3D 1; - AsmWriteCr4 (Cr4.UintN); + if (Enable5LevelPaging) { // // For the PML5 entries we are not using fill in a null entry. // --=20 2.32.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78789): https://edk2.groups.io/g/devel/message/78789 Mute This Topic: https://groups.io/mt/84703873/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-