[edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

Ni, Ray posted 1 patch 2 years, 7 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/edk2 tags/patchew/20210806081626.802-1-ray.ni@intel.com
.../UefiPayloadEntry/UefiPayloadEntry.inf     |  1 -
.../UniversalPayloadEntry.inf                 |  1 -
.../UefiPayloadEntry/X64/VirtualMemory.c      | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)
[edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader
Posted by Ni, Ray 2 years, 7 months ago
The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from
bootloader in IA-32e mode and uses 4-level paging in
legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging
but 64bit payload sets 4-level page table to CR3 resulting CPU
exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
 .../UefiPayloadEntry/UefiPayloadEntry.inf     |  1 -
 .../UniversalPayloadEntry.inf                 |  1 -
 .../UefiPayloadEntry/X64/VirtualMemory.c      | 38 ++++++++-----------
 3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask    ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ## SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES
 
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask    ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ## SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES
 
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
 
-Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
   )
 {
   UINT32                                        RegEax;
-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX   EcxFlags;
   UINT32                                        RegEdx;
   UINT8                                         PhysicalAddressBits;
   EFI_PHYSICAL_ADDRESS                          PageAddress;
@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
   UINTN                                         TotalPagesNum;
   UINTN                                         BigPageAddress;
   VOID                                          *Hob;
-  BOOLEAN                                       Page5LevelSupport;
+  BOOLEAN                                       Enable5LevelPaging;
   BOOLEAN                                       Page1GSupport;
   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;
   UINT64                                        AddressEncMask;
@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
     }
   }
 
-  Page5LevelSupport = FALSE;
-  if (PcdGetBool (PcdUse5LevelPageTable)) {
-    AsmCpuidEx (
-      CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,
-      &EcxFlags.Uint32, NULL, NULL
-      );
-    if (EcxFlags.Bits.FiveLevelPage != 0) {
-      Page5LevelSupport = TRUE;
-    }
-  }
+  //
+  // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.
+  // Because this code runs at both IA-32e (64bit) mode and legacy protected (32bit) mode,
+  // below logic inherits the 5-level paging setting from bootloader in IA-32e mode
+  // and uses 4-level paging in legacy protected mode.
+  //
+  Cr4.UintN = AsmReadCr4 ();
+  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
 
-  DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));
+  DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));
 
   //
   // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses
@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
   //  due to either unsupported by HW, or disabled by PCD.
   //
   ASSERT (PhysicalAddressBits <= 52);
-  if (!Page5LevelSupport && PhysicalAddressBits > 48) {
+  if (!Enable5LevelPaging && PhysicalAddressBits > 48) {
     PhysicalAddressBits = 48;
   }
 
@@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
   //
   // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled.
   //
-  if (!Page5LevelSupport) {
+  if (!Enable5LevelPaging) {
     TotalPagesNum--;
   }
 
@@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
   // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
   //
   PageMap         = (VOID *) BigPageAddress;
-  if (Page5LevelSupport) {
+  if (Enable5LevelPaging) {
     //
     // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
     //
@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
     PageMapLevel4Entry = (VOID *) BigPageAddress;
     BigPageAddress    += SIZE_4KB;
 
-    if (Page5LevelSupport) {
+    if (Enable5LevelPaging) {
       //
       // Make a PML5 Entry
       //
@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
     ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
   }
 
-  if (Page5LevelSupport) {
-    Cr4.UintN = AsmReadCr4 ();
-    Cr4.Bits.LA57 = 1;
-    AsmWriteCr4 (Cr4.UintN);
+  if (Enable5LevelPaging) {
     //
     // For the PML5 entries we are not using fill in a null entry.
     //
-- 
2.32.0.windows.1



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Re: [edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader
Posted by Guo Dong 2 years, 7 months ago
Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com> 
Sent: Friday, August 6, 2021 1:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit payload sets 4-level page table to CR3 resulting CPU exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
 .../UefiPayloadEntry/UefiPayloadEntry.inf     |  1 -
 .../UniversalPayloadEntry.inf                 |  1 -
 .../UefiPayloadEntry/X64/VirtualMemory.c      | 38 ++++++++-----------
 3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask    ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ## SOMETIMES_CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask    ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ## SOMETIMES_CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize                            ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>  SPDX-License-Identifier: BSD-2-Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
   ) {   UINT32                                        RegEax;-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX   EcxFlags;   UINT32                                        RegEdx;   UINT8                                         PhysicalAddressBits;   EFI_PHYSICAL_ADDRESS                          PageAddress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
   UINTN                                         TotalPagesNum;   UINTN                                         BigPageAddress;   VOID                                          *Hob;-  BOOLEAN                                       Page5LevelSupport;+  BOOLEAN                                       Enable5LevelPaging;   BOOLEAN                                       Page1GSupport;   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;   UINT64                                        AddressEncMask;@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
     }   } -  Page5LevelSupport = FALSE;-  if (PcdGetBool (PcdUse5LevelPageTable)) {-    AsmCpuidEx (-      CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,-      &EcxFlags.Uint32, NULL, NULL-      );-    if (EcxFlags.Bits.FiveLevelPage != 0) {-      Page5LevelSupport = TRUE;-    }-  }+  //+  // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.+  // Because this code runs at both IA-32e (64bit) mode and legacy protected (32bit) mode,+  // below logic inherits the 5-level paging setting from bootloader in IA-32e mode+  // and uses 4-level paging in legacy protected mode.+  //+  Cr4.UintN = AsmReadCr4 ();+  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); -  DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+  DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));    //   // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
   //  due to either unsupported by HW, or disabled by PCD.   //   ASSERT (PhysicalAddressBits <= 52);-  if (!Page5LevelSupport && PhysicalAddressBits > 48) {+  if (!Enable5LevelPaging && PhysicalAddressBits > 48) {     PhysicalAddressBits = 48;   } @@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
   //   // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled.   //-  if (!Page5LevelSupport) {+  if (!Enable5LevelPaging) {     TotalPagesNum--;   } @@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
   // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.   //   PageMap         = (VOID *) BigPageAddress;-  if (Page5LevelSupport) {+  if (Enable5LevelPaging) {     //     // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.     //@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
     PageMapLevel4Entry = (VOID *) BigPageAddress;     BigPageAddress    += SIZE_4KB; -    if (Page5LevelSupport) {+    if (Enable5LevelPaging) {       //       // Make a PML5 Entry       //@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
     ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));   } -  if (Page5LevelSupport) {-    Cr4.UintN = AsmReadCr4 ();-    Cr4.Bits.LA57 = 1;-    AsmWriteCr4 (Cr4.UintN);+  if (Enable5LevelPaging) {     //     // For the PML5 entries we are not using fill in a null entry.     //-- 
2.32.0.windows.1



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Re: [edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader
Posted by Ma, Maurice 2 years, 3 months ago
Reviewed-by: Maurice Ma <maurice.ma@intel.com>


> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Friday, August 6, 2021 1:16
> To: devel@edk2.groups.io
> Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice
> <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
> Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from
> bootloader
> 
> The patch removes the dep on PcdUse5LevelPageTable.
> Now the payload inherits the 5-level paging setting from bootloader in IA-32e
> mode and uses 4-level paging in legacy protected mode.
> 
> This fix the potential issue when bootloader enables 5-level paging but 64bit
> payload sets 4-level page table to CR3 resulting CPU exception because
> PcdUse5LevelPageTable is FALSE.
> 
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Guo Dong <guo.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Benjamin You <benjamin.you@intel.com>
> ---
>  .../UefiPayloadEntry/UefiPayloadEntry.inf     |  1 -
>  .../UniversalPayloadEntry.inf                 |  1 -
>  .../UefiPayloadEntry/X64/VirtualMemory.c      | 38 ++++++++-----------
>  3 files changed, 16 insertions(+), 24 deletions(-)
> 
> diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
> b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
> index 8d42925fcd..9b6fab66a1 100644
> --- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
> +++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
> @@ -80,7 +80,6 @@
> 
> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
> ## CONSUMES
> gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ##
> CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> ## CONSUMES-
> gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ##
> SOMETIMES_CONSUMES
> gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ##
> CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize
> ## CONSUMES diff --git
> a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
> b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
> index 416a620598..aae62126e9 100644
> --- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
> +++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
> @@ -85,7 +85,6 @@
> 
> gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
> ## CONSUMES
> gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask               ##
> CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> ## CONSUMES-
> gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable                  ##
> SOMETIMES_CONSUMES
> gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase                            ##
> CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize
> ## CONSUMES diff --git
> a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
> b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
> index a1c4ad6ff4..9daa46c12c 100644
> --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
> +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
> @@ -15,7 +15,7 @@
>      2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
> 2:Instruction Set Reference, Intel     3) IA-32 Intel(R) Architecture Software
> Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright
> (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006
> - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD
> Incorporated. All rights reserved.<BR>  SPDX-License-Identifier: BSD-2-
> Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
>    ) {   UINT32                                        RegEax;-
> CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX   EcxFlags;   UINT32
> RegEdx;   UINT8                                         PhysicalAddressBits;
> EFI_PHYSICAL_ADDRESS                          PageAddress;@@ -687,7 +686,7 @@
> CreateIdentityMappingPageTables (
>    UINTN                                         TotalPagesNum;   UINTN
> BigPageAddress;   VOID                                          *Hob;-  BOOLEAN
> Page5LevelSupport;+  BOOLEAN                                       Enable5LevelPaging;
> BOOLEAN                                       Page1GSupport;   PAGE_TABLE_1G_ENTRY
> *PageDirectory1GEntry;   UINT64                                        AddressEncMask;@@ -
> 730,18 +729,16 @@ CreateIdentityMappingPageTables (
>      }   } -  Page5LevelSupport = FALSE;-  if (PcdGetBool
> (PcdUse5LevelPageTable)) {-    AsmCpuidEx (-
> CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
> CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,-
> &EcxFlags.Uint32, NULL, NULL-      );-    if (EcxFlags.Bits.FiveLevelPage != 0) {-
> Page5LevelSupport = TRUE;-    }-  }+  //+  // Check CR4.LA57[bit12] to
> determin whether 5-Level Paging is enabled.+  // Because this code runs at
> both IA-32e (64bit) mode and legacy protected (32bit) mode,+  // below logic
> inherits the 5-level paging setting from bootloader in IA-32e mode+  // and
> uses 4-level paging in legacy protected mode.+  //+  Cr4.UintN = AsmReadCr4
> ();+  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); -  DEBUG
> ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n",
> PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+  DEBUG
> ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u
> 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));
> //   // IA-32e paging translates 48-bit linear addresses to 52-bit physical
> addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
>    //  due to either unsupported by HW, or disabled by PCD.   //   ASSERT
> (PhysicalAddressBits <= 52);-  if (!Page5LevelSupport && PhysicalAddressBits >
> 48) {+  if (!Enable5LevelPaging && PhysicalAddressBits > 48)
> {     PhysicalAddressBits = 48;   } @@ -784,7 +781,7 @@
> CreateIdentityMappingPageTables (
>    //   // Substract the one page occupied by PML5 entries if 5-Level Paging is
> disabled.   //-  if (!Page5LevelSupport) {+  if (!Enable5LevelPaging)
> {     TotalPagesNum--;   } @@ -799,7 +796,7 @@
> CreateIdentityMappingPageTables (
>    // By architecture only one PageMapLevel4 exists - so lets allocate storage
> for it.   //   PageMap         = (VOID *) BigPageAddress;-  if (Page5LevelSupport)
> {+  if (Enable5LevelPaging) {     //     // By architecture only one
> PageMapLevel5 exists - so lets allocate storage for it.     //@@ -819,7 +816,7
> @@ CreateIdentityMappingPageTables (
>      PageMapLevel4Entry = (VOID *) BigPageAddress;     BigPageAddress    +=
> SIZE_4KB; -    if (Page5LevelSupport) {+    if (Enable5LevelPaging) {       //       //
> Make a PML5 Entry       //@@ -911,10 +908,7 @@
> CreateIdentityMappingPageTables (
>      ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof
> (PAGE_MAP_AND_DIRECTORY_POINTER));   } -  if (Page5LevelSupport) {-
> Cr4.UintN = AsmReadCr4 ();-    Cr4.Bits.LA57 = 1;-    AsmWriteCr4
> (Cr4.UintN);+  if (Enable5LevelPaging) {     //     // For the PML5 entries we are
> not using fill in a null entry.     //--
> 2.32.0.windows.1



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