From nobody Mon Nov 25 01:54:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78735+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78735+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628181371; cv=none; d=zohomail.com; s=zohoarc; b=WyGB05EqGJPqif8Sr70hXd6NM2yY4Ztgj5U+jzj/BjYVRk8hzp+pAfJ15Sk4No3C3xf1lhygLb5xTEIEzmOcUIqOk3mbkgTXL9Zr+/01ghOD7TxLF4rgNsgcVd4NVKQQUyE/41xlrt8luDoccDrcJ4N2EDzNzoVW3h+WBiyXv5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628181371; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=V2YertH0NOlQ5cF3xIH5XR0RyZDaSMUuUJmJb0r17OA=; b=kYS+rejryVDlABDEDSAY5b8Yu2N889g//nTicpbmfpPD5mSumnVkjfCO5sLdXUb8o1Ym+ZEqpf02rEn5Tmt1caIPvr2gpE0UGwzUY4TaAXI8iMPADb6A+w5xCwmIxJ/5BYhoxp+aKgkE9ZsNTHWTcho7TGSpZNj1/xgC9HWtChQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78735+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628181371862908.3167411031326; Thu, 5 Aug 2021 09:36:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HBl0YY1788612xou4YbxwU1h; Thu, 05 Aug 2021 09:36:11 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.11374.1628181365708775674 for ; Thu, 05 Aug 2021 09:36:05 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49BAC11FB; Thu, 5 Aug 2021 09:36:05 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EDB4A3F66F; Thu, 5 Aug 2021 09:36:04 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu Date: Thu, 5 Aug 2021 11:35:47 -0500 Message-Id: <20210805163551.488035-2-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: OjYcDpQnBtuxYV4S1mvJkcb2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628181371; bh=N/JPRP969P6DrsoQzZDreYsad0Z2L95P3fzeG9rvDCI=; h=Cc:Date:From:Reply-To:Subject:To; b=kIsinHqKmT0pD8ei8XZ/W7MK4jfbw37YezWhHcwmooiYV6Z+8VvxOLN3jRYOEKvaN/l h9Vv4mgzckm3C8d0IfYTlf7YamPztXGDa+BfqbZ5AfMpbWZ3FdUOCUaAjDTiKwbIXBzba J72UREBC9pnIFRhbmE2WTi5iYdBA9e28GnQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628181372792100004 Content-Type: text/plain; charset="utf-8" Arm has standardized a PCI SMC conduit that can be used to access the PCI config space in a standardized way. This functionality doesn't yet exist in many OS/Distro's. Lets add another advanced config item that allows the user to toggle between presenting the XHCI on the base RPi4 as a platform device, or presenting this newer PCIe conduit. The CM4 doesn't have an attached XHCI controller soldered to the PCIe, so we hide the menu and only allow PCIe mode. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++++= ++++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 + .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++ .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++ Platform/RaspberryPi/Include/ConfigVars.h | 4 +++ Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++ Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++ Platform/RaspberryPi/RaspberryPi.dec | 1 + 8 files changed, 84 insertions(+) diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 9e78cb47ad..87f6b4e7bb 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[]; STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol; STATIC UINT32 mModelFamily =3D 0; STATIC UINT32 mModelInstalledMB =3D 0; +STATIC UINT32 mModelRevision =3D 0; =20 STATIC EFI_MAC_ADDRESS mMacAddress; =20 @@ -271,6 +272,40 @@ SetupVariables ( ASSERT_EFI_ERROR (Status); } =20 + if (mModelFamily >=3D 4) { + if (((mModelRevision >> 4) & 0xFF) =3D=3D 0x14) { + /* + * Enable PCIe by default on CM4 + */ + Status =3D PcdSet32S (PcdXhciPci, 2); + ASSERT_EFI_ERROR (Status); + } else { + Size =3D sizeof (UINT32); + Status =3D gRT->GetVariable (L"XhciPci", + &gConfigDxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || (Var32 =3D=3D 0)) { + /* + * Enable XHCI by default + */ + Status =3D PcdSet32S (PcdXhciPci, 0); + ASSERT_EFI_ERROR (Status); + } else { + /*=20 + * Enable PCIe + */ + Status =3D PcdSet32S (PcdXhciPci, 1); + ASSERT_EFI_ERROR (Status); + } + } + } else { + /*=20 + * Disable PCIe and XHCI + */ + Status =3D PcdSet32S (PcdXhciPci, 0); + ASSERT_EFI_ERROR (Status); + } + Size =3D sizeof (AssetTagVar); Status =3D gRT->GetVariable (L"AssetTag", &gConfigDxeFormSetGuid, @@ -888,6 +923,13 @@ ConfigInitialize ( DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\= n", mModelInstalledMB)); } =20 + Status =3D mFwProtocol->GetModelRevision (&mModelRevision); + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n", S= tatus)); + } else { + DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevisi= on)); + } + Status =3D SetupVariables (); if (Status !=3D EFI_SUCCESS) { DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status)); diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platfor= m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf index 4bb2d08550..e6e22ad82e 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf @@ -94,6 +94,7 @@ gRaspberryPiTokenSpaceGuid.PcdFanOnGpio gRaspberryPiTokenSpaceGuid.PcdFanTemp gRaspberryPiTokenSpaceGuid.PcdUartInUse + gRaspberryPiTokenSpaceGuid.PcdXhciPci =20 [Depex] gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni index 466fa852cb..5ec17072c3 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni @@ -57,6 +57,11 @@ #string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperatur= e" #string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C" =20 +#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe" +#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB pl= atform device or PCIe bridge" +#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI" +#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe" + #string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag" #string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asse= t Tag" =20 diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Plat= form/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr index fa34eab809..18b3ec726e 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr @@ -56,6 +56,11 @@ formset name =3D FanTemp, guid =3D CONFIGDXE_FORM_SET_GUID; =20 + efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA, + attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, + name =3D XhciPci, + guid =3D CONFIGDXE_FORM_SET_GUID; + efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA, attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME= _ACCESS | EFI_VARIABLE_NON_VOLATILE, name =3D SystemTableMode, @@ -212,6 +217,18 @@ formset default =3D 60, endnumeric; endif; + + suppressif ideqval XhciPci.Value =3D=3D 2; + grayoutif NOT ideqval SystemTableMode.Mode =3D=3D SYSTEM_TABLE_M= ODE_ACPI; + oneof varid =3D XhciPci.Value, + prompt =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT), + help =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP), + flags =3D NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRE= D, + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), val= ue =3D 0, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), val= ue =3D 1, flags =3D 0; + endoneof; + endif; + endif; #endif string varid =3D AssetTag.AssetTag, prompt =3D STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT), diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/Raspberry= Pi/Include/ConfigVars.h index 142317985a..a5b32b5284 100644 --- a/Platform/RaspberryPi/Include/ConfigVars.h +++ b/Platform/RaspberryPi/Include/ConfigVars.h @@ -77,6 +77,10 @@ typedef struct { } ADVANCED_FANTEMP_VARSTORE_DATA; =20 typedef struct { + UINT32 Value; +} ADVANCED_XHCIPCI_VARSTORE_DATA; + +typedef struct { #define SYSTEM_TABLE_MODE_ACPI 0 #define SYSTEM_TABLE_MODE_BOTH 1 #define SYSTEM_TABLE_MODE_DT 2 diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3= /RPi3.dsc index 1c8a5408e7..6ab5d1ae6d 100644 --- a/Platform/RaspberryPi/RPi3/RPi3.dsc +++ b/Platform/RaspberryPi/RPi3/RPi3.dsc @@ -520,6 +520,12 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode (not valid on rpi3) + # + # 0 - DISABLED + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4= /RPi4.dsc index dcf9bb5f11..babcbb2f41 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -536,6 +536,14 @@ =20 gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr= yPiTokenSpaceGuid|0x0|0 =20 + # Select XHCI/PCIe mode + # + # 0 - XHCI Enabled (default on !cm4) + # 1 - PCIe Enabled + # 2 - PCIe Enabled (default on cm4) + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0= x0|0 + # # Common UEFI ones. # diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/Ra= spberryPi.dec index 2ca25ff9e6..797be59274 100644 --- a/Platform/RaspberryPi/RaspberryPi.dec +++ b/Platform/RaspberryPi/RaspberryPi.dec @@ -71,3 +71,4 @@ gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021 + gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022 --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78735): https://edk2.groups.io/g/devel/message/78735 Mute This Topic: https://groups.io/mt/84688697/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 01:54:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78736+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628181372; cv=none; d=zohomail.com; s=zohoarc; b=C8aeWIc/6kDtS0Pq5P6UT7gMI5hNS+jF0ETNggwY89uOxToSbixTP5Fn00W/QMWCOXOzKfSzmFEh4E/5C+rBiBu4X5konXdkoJdIJ/9AVLvbAH6F7E+usA2iV8BwHF57FtIySI02u1jdv44NYxPJCBYy3v8puFwGtLEt4UO7oJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628181372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PSdxqCXMZWyQDa4V74zHR8AfCU+jKeY9R9oon5SAtqU=; b=H/THW33k33Ttm5zi5f0DY0Z7mxT1n3o8DnBO4hfUZbptImyuQCqClLacM8VEvOHCvTvU1yInE87Oy8bsW/tzg1/zOme8Y5rUVOVHbC5enpFfFv4Kl8fkxfPah3hMhKSIvwO1Dley+GjCLHv20A4wwenujf0PsoNmthjUiX2SXhA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78736+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628181372452700.0558589700688; Thu, 5 Aug 2021 09:36:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mQfJYY1788612xO7bgZ1glh9; Thu, 05 Aug 2021 09:36:11 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.11376.1628181366913029124 for ; Thu, 05 Aug 2021 09:36:07 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8448612FC; Thu, 5 Aug 2021 09:36:06 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32F783F66F; Thu, 5 Aug 2021 09:36:06 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT Date: Thu, 5 Aug 2021 11:35:48 -0500 Message-Id: <20210805163551.488035-3-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: y14YscvHi4Awf6LLf71n3ZQOx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628181371; bh=Y+idHw6pdlCohg06l7kjkrp22+GrQqONR1/iFI9uXhY=; h=Cc:Date:From:Reply-To:Subject:To; b=kmPfFoTvEERyTY177eluueu8xtkMg+CN0leoOqPKqogDFoUrhrORerDXyhDKj6EJiKB Ns6PZTEU5WI9bt3PiTfvhWKRr2zTNS1D8uPg5rfl/HdIhZRlYVntIheDNKfH2rRBAg+X2 hvcSnT4L7YrPkCWH65Ei9iO86U02AW7lips= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628181372833100006 Content-Type: text/plain; charset="utf-8" Lets prepare to switch between XHCI and PCI by moving the XHCI definition into its own SSDT. That way we can select it based on the menu settings. Signed-off-by: Jeremy Linton Reviewed-by: Andrei Warkentin --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 + Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 -- Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++----= ---- Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++ 4 files changed, 31 insertions(+), 16 deletions(-) diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index 1ddc9ca5fe..f3e8d950c1 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -38,6 +38,7 @@ SpcrPl011.aslc Pptt.aslc SsdtThermal.asl + Xhci.asl =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryP= i/AcpiTables/Dsdt.asl index 1ee6379f46..b594d50bdf 100644 --- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl +++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl @@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", = 2) Scope (\_SB_) { include ("Pep.asl") -#if (RPI_MODEL =3D=3D 4) - include ("Xhci.asl") -#endif =20 Device (CPU0) { diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryP= i/AcpiTables/Xhci.asl index bc3fea60f9..9b37277956 100644 --- a/Platform/RaspberryPi/AcpiTables/Xhci.asl +++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl @@ -9,6 +9,8 @@ =20 #include =20 +#include "AcpiTables.h" + /* * The following can be used to remove parenthesis from * defined macros that the compiler complains about. @@ -24,12 +26,17 @@ */ #define XHCI_REG_LENGTH 0x1000 =20 -Device (SCB0) { - Name (_HID, "ACPI0004") - Name (_UID, 0x0) - Name (_CCA, 0x0) +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) =20 - Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings /* * Container devices with _DMA must have _CRS, meaning SCB0 * to provide all resources that XHC0 consumes (except @@ -57,15 +64,15 @@ Device (SCB0) { Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) Return (RBUF) - } + } =20 - Name (_DMA, ResourceTemplate() { + Name (_DMA, ResourceTemplate() { /* * XHC0 is limited to DMA to first 3GB. Note this * only applies to PCIe, not GENET or other devices * next to the A72. */ - QWordMemory (ResourceConsumer, + QWordMemory (ResourceProducer, , MinFixed, MaxFixed, @@ -79,10 +86,10 @@ Device (SCB0) { , , ) - }) + }) =20 - Device (XHC0) - { + Device (XHC0) + { Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x0) // _UID: Unique ID Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute @@ -131,5 +138,7 @@ Device (SCB0) { Debug =3D "xHCI enable" Store (0x6, CMND) } - } -} + } // end XHC0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 87f6b4e7bb..7c5786303d 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdSdIsArasan), SsdtEmmcNameOpReplace }, +#if (RPI_MODEL =3D=3D 4) + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'), + 0, + PcdToken(PcdXhciPci), + NULL + }, +#endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), 0, --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78736): https://edk2.groups.io/g/devel/message/78736 Mute This Topic: https://groups.io/mt/84688698/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 01:54:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78737+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78737+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628181372; cv=none; d=zohomail.com; s=zohoarc; b=Cd6bPV5z/1kfTcWoXU8SOWiouKsqmzzbws60uhFCOTwKepDvgtSxGUz270VgB9etHGOdipy/TFbloYyEzG6iq9vTdb3Ffe/nG3ETF11IG6okE26fRXi+W3/ZbQ/M0g+/MUxLBkIH//y4cEg18MetJrgV0xLTP/PjCilmocpptis= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628181372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=b3QXeUQnU/9sPLiG0wERkxVLUlJNp6KD3FWgnhY8CxY=; b=ENJpWB52AFUxDo1eBH/iHxOQQTyatSVxfi4LxKyWWGX/qYEcSmDwHz89zFMrf8t0+YSq4j9yI70PglA12ZsRW7sqBRwfzciPZRd6XgN4Z9piXn1fmI+hiONta9jqpQHvHVWSrrepVzrUH7cGVlIeZ7kwjXw48+BoY/W4HSsog9U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78737+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628181372847602.5945825604047; Thu, 5 Aug 2021 09:36:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id czoQYY1788612xv49NaLfQUR; Thu, 05 Aug 2021 09:36:12 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.11379.1628181367998496714 for ; Thu, 05 Aug 2021 09:36:08 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A288B11FB; Thu, 5 Aug 2021 09:36:07 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4C4EE3F66F; Thu, 5 Aug 2021 09:36:07 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Date: Thu, 5 Aug 2021 11:35:49 -0500 Message-Id: <20210805163551.488035-4-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: ctenedJIWjzLQy03GdO7tEG7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628181372; bh=XEi2/1bZNubARGzQCd7Q38LqzLyPFmrd/OItWXi0f5I=; h=Cc:Date:From:Reply-To:Subject:To; b=EdqZv8fsvW0GWIcd4FSu80pN8A94q/8+9XYHo5PfWza66BcNydemjD6Yt1Duu0XFG01 FwGnGbU+gUqyhF5F74YhOt1D5JvJj/gAd/0HbJr81YKFnc1cEVnmaNkE3ybJRgjKaLXns 1B7XxDuYN7GFUgeL4AHROhm6UQE1xiEXj64= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628181374852100015 Content-Type: text/plain; charset="utf-8" Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port, on a machine without a MADT it attempts to connect to the SMC conduit. The RPi definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++= ++++ Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 + 3 files changed, 246 insertions(+) create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index f3e8d950c1..da2a6db85f 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -39,6 +39,7 @@ Pptt.aslc SsdtThermal.asl Xhci.asl + Pci.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -59,6 +60,8 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl new file mode 100644 index 0000000000..34474f13ef --- /dev/null +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl @@ -0,0 +1,237 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_W= INDOW) +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMI= O_LEN) +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM= _WIN) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define RT_REG_LENGTH 0x1000 + +// copy paste job from juno +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ + Device(Link_Name) { = \ + Name(_HID, EISAID("PNP0C0F")) = \ + Name(_UID, Unique_Id) = \ + Name(_PRS, ResourceTemplate() { = \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq = } \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, /* uses the same format as _ADR */ = \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INT= B, 2-INTC, 3-INTD). */ \ + Link, /* Interrupt allocated via Link device. */ = \ + Zero /* global system interrupt number (no used) */ = \ + } +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { + // Container devices with _DMA must have _CRS,=20 + // meaning SCB0 to provide all resources that + // PCI0 consumes (except interrupts). + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, RT_REG_LENGTH - 1, MMBE) + Add (MMLE, RT_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + // PCIe can only DMA to first 3GB with early SOC's + // But we keep the restriction on the later ones + // To avoid DMA translation problems. + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 175) + LNK_DEVICE(2, LNKB, 176) + LNK_DEVICE(3, LNKC, 177) + LNK_DEVICE(4, LNKD, 178) + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // Mark the PCI noncoherent + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + QWordMemory ( // 32-bit BAR Windows in 64-bit addr + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, //cacheable? is that right? + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_B= EGIN + 1, // SANITIZED_PCIE_MMIO_LEN += SANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_B= EGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN += 1 + ,,,MMI1,,TypeTranslation + ) + }) // end Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMI= E) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // end Method(_CRS) + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmw= are + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 7c5786303d..4c40820858 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdXhciPci), NULL }, + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'), + PcdToken(PcdXhciPci), + 0, + NULL + }, #endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78737): https://edk2.groups.io/g/devel/message/78737 Mute This Topic: https://groups.io/mt/84688699/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 01:54:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78738+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78738+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628181373; cv=none; d=zohomail.com; s=zohoarc; b=nYdKqZSWxFp5Lhbf/g1ZQ352R2QhZ7ej/wXDYUawPkOlu5VPbxdKYBntbpeLMQINjspflQ7ZPn3PY8YXlxsqVgaKQbhuYpgXAvB+BDUy7JsyY38HfeJARfYbO+NGclulFTWBjbPTT0qrXwiwAoNWUsyyV2NcRPNUEQVm5Ua58M4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628181373; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wYUXQDCOLwtNS4WuBd5ZjNhLP7IgATRhbgHRuqy9UD0=; b=IO6zGWQArJRZcVEeDwMcQDM5iTr9O9SLEY6ZV0DMgGNrlaPoI0+6Z/AQINovHugraSjdAruVpJkzzJYF/Ymu2vMIiukn7vBWoiTWzWLsFJVCtoS84QokiMgORAli/Zll7fMFb46iQvO460SNHFeumCNDTHSY1I6aYZnzLsLXl3U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78738+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628181373237129.66190765190197; Thu, 5 Aug 2021 09:36:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WOgEYY1788612xCHcoXFiZq6; Thu, 05 Aug 2021 09:36:12 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.11385.1628181369586880046 for ; Thu, 05 Aug 2021 09:36:09 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D9DC31B; Thu, 5 Aug 2021 09:36:09 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B099D3F66F; Thu, 5 Aug 2021 09:36:08 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton , =?UTF-8?q?Ren=C3=A9=20Treffer?= Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Date: Thu, 5 Aug 2021 11:35:50 -0500 Message-Id: <20210805163551.488035-5-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: iK22Hw2POW9qMrHWAFsZrvoFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628181372; bh=q6euhF0raGrIzfK1OgU+bO0mvuiegoyMtGOx/gVmYuI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sVZ5pMcSWYmj/ByJuzjuPIhajxbZhYHryhizUWkfvtRD0gqcYjvJsBr02HaM2COsqzh g43PrEQ6lD6aQ2dPoyprWGMg42MsYinM9w/hT5zuwqw9kuqB0I90wzlSuP+8SAaULswOX 2nihLm4/naD+7NWnMpEs+w1plFfmU+SNvp0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628182276815100002 Content-Type: text/plain; charset="utf-8" The CM4 has an actual pcie slot, so we need to move the linkup check to the configuration probe logic. Further the device restriction logic needs to be relaxed to support downstream PCIe switches. Suggested-by: Ren=C3=A9 Treffer Signed-off-by: Jeremy Linton Reviewed-by: Andrei Warkentin --- .../Bcm2711PciHostBridgeLibConstructor.c | 5 ----- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++---= ---- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n", D= ata, Timeout)); =20 - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Data)= ); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 44ce3b4b99..3ccc131eab 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; =20 Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset */ @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + =20 /* - * Scan things out directly rather than translating the "bus" to a d= evice, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus < 2)) { return 0xFFFFFFFF; } + + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data= )); + return 0xFFFFFFFF; + } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78738): https://edk2.groups.io/g/devel/message/78738 Mute This Topic: https://groups.io/mt/84688700/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 01:54:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78739+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1628181373; cv=none; d=zohomail.com; s=zohoarc; b=fAV//a/so33biquBconTm0qc+uhXyvu4Vf8ulDLcyB4yl5cmYPJE2idK2ZyfmLVqGpbdPzqAS+hp09ZxPTJ83CG1ipSWuLfKRu8ltqY/iJE1AwSCKFxii2naWpL+qBMirzQkGzufE60fOMVcawJ7NUF8icYwlAk9D7oz1C0Pfd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628181373; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lzjrg6RuvmuyxTPxpKK+zJrPMhsvmMSy86pRf2rE87s=; b=HJCmzXImWb+APMENvew4XheWTNqlahMKMuzv5oyvqRmQjyIjAVcM+daDsaqOV4nNRWe6oZMImUXNKp/AJOcZFnxuF07PDfa4eAUYA9MYtb+EHRgD8ByWq/qZaJzt0F5f2yI36KujnMYWWJwuSs/wHzV9s7RjMLLAFJ0BmsUm4u0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78739+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628181373626884.8548391146109; Thu, 5 Aug 2021 09:36:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dexNYY1788612xoIxmxYAZ0a; Thu, 05 Aug 2021 09:36:13 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.11322.1628181370652190570 for ; Thu, 05 Aug 2021 09:36:10 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D1FE11FB; Thu, 5 Aug 2021 09:36:10 -0700 (PDT) X-Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E8E863F66F; Thu, 5 Aug 2021 09:36:09 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton Subject: [edk2-devel] [PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4 Date: Thu, 5 Aug 2021 11:35:51 -0500 Message-Id: <20210805163551.488035-6-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-1-jeremy.linton@arm.com> References: <20210805163551.488035-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jeremy.linton@arm.com X-Gm-Message-State: sLJKmNbyw4pZezi9PnL9pWNPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628181373; bh=VLwU8WGZjYSs6n+p0kzWccdwLAj0XSsxmnfgY6vglpI=; h=Cc:Date:From:Reply-To:Subject:To; b=xRJjgL9jjeS+50MY8VVm+5OeR1Hi5JoKN1k+aGxjQSJm34mX5KyBEJgiQV7PBA8+YKI hz7/bbKWLo+DpoTiYn/e4k9xa6w91O6IuO0fEBYM1g6Iu+tNoiRC6F9tGjOOLV2iPoZEy Gjgcexxm0K+J0zqJdGdoIwOynO/LwUOn0sM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628181375098100019 Content-Type: text/plain; charset="utf-8" The CM4 has a number of carrier boards with PCIe slots. With the PCIe changes in place its quite possible to setup a NVMe root device. Lets allow people to boot from it. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++ Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4= /RPi4.dsc index babcbb2f41..25c29a0fbf 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -754,6 +754,11 @@ } =20 # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # # UEFI application (Shell Embedded Boot Loader) # ShellPkg/Application/Shell/Shell.inf { diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RPi4= /RPi4.fdf index 3534cd3dc3..0c782d2f35 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.fdf +++ b/Platform/RaspberryPi/RPi4/RPi4.fdf @@ -283,6 +283,11 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf =20 # + # NVMe boot devices + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # # SCSI Bus and Disk Driver # INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf --=20 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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