From nobody Tue Apr 30 19:19:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78703+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78703+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628147876; cv=none; d=zohomail.com; s=zohoarc; b=F/ZV+Dq7q6UEAdVc/qgWIetd0z31lYRf7L6UFFa/YyuUGDvIpZJZcprc/Ls5kIShFR6udkXzKos6p+D5tU59bzNrkv5bLXXociae2fdv0KRGlLVf72LS8Vyca7j4UCS5aIXxoljZAAhfh+QRAVTepj+Y95+RKpT5+7fwvXV9Vkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628147876; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=VHzXYFc28o1uwFEWXz5W+EyCn7tvmgjqJFOVo0GtAg4=; b=Xbk4iXPY9x0te+3wZN2tYralp60RIiOmaQyemsePixhu2QwNGWXRDO+dfpfkMJuzhJR5f7sN06VUQb661qiRmxx46ZQi8BUqZf1/9s0sbarC9/BDR4jdp19ZT4HmLtNOPeROZoEdAPvwdOu7neux8iM+cwn2RXXCjI+4NqYExBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78703+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628147876160347.4512627142965; Thu, 5 Aug 2021 00:17:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3YrlYY1788612xkGLK0bbIIk; Thu, 05 Aug 2021 00:17:55 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web09.5722.1628147874769464736 for ; Thu, 05 Aug 2021 00:17:55 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10066"; a="277843675" X-IronPort-AV: E=Sophos;i="5.84,296,1620716400"; d="scan'208";a="277843675" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2021 00:17:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,296,1620716400"; d="scan'208";a="569301176" X-Received: from lins2x-desk1.gar.corp.intel.com ([10.225.33.149]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2021 00:17:51 -0700 From: "JackX Lin" To: devel@edk2.groups.io Cc: JackX Lin , Chasel Chiu , Jenny Huang , Jiewen Yao , Ray Ni , Rangasai V Chaganty , Donald Kuo , Chandana C Kumar , Tinax Chen Subject: [edk2-devel] [edk2-platforms: PATCH V4] Platform/Intel: Correct CPU APIC IDs Date: Thu, 5 Aug 2021 15:17:18 +0800 Message-Id: <20210805071718.1604-1-JackX.Lin@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,JackX.Lin@intel.com X-Gm-Message-State: ZgdRiajSd7FxzJeWKfqXuOcdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628147875; bh=GPcSGlNmh/p3mO4ywWe/wldcjdvOQ0/rerMNjOXkQE8=; h=Cc:Date:From:Reply-To:Subject:To; b=Uud4j58teuiq5kkAa8L9nSvKakExngzm4LXynlN7Bbz9+H9SbyXV9HX2xpJmP0JhqhS ShSgnpsK09LEudKNa4GaFPZyyvLLd5HbfAYRaPl4uQZNFG3LWeguT2lU02Mu1XPYYligA xBTZM+Pc3Ja6sBqRDSGRHjw54jL9yw6v194= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628147877917100002 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3365 BIOS cannot find correct AcpiProcId in mApicIdMap because of there is no suitable map, that causes ACPI_BIOS_ERROR. Remove mApicIdMap for determing AcpiProcId, uses normal countings instead. Signed-off-by: JackX Lin Cc: Chasel Chiu Cc: Jenny Huang Cc: Jiewen Yao Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Donald Kuo Cc: Chandana C Kumar Cc: Tinax Chen Cc: JackX Lin Change-Id: Ib64e519686b2f324a0a57c3b5bba220a7b75fda1 --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 538 +++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++--------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------ 1 file changed, 206 insertions(+), 332 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b= /Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 2b51c34ef2..4d9c709e4f 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -1,22 +1,19 @@ /** @file ACPI Platform Driver =20 -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include "AcpiPlatform.h" =20 -#define MAX_CPU_NUM (FixedPcdGet32(PcdMaxCpuThreadCount) * FixedPcdGet32(P= cdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuSocketCount)) - #pragma pack(1) =20 typedef struct { UINT32 AcpiProcessorId; UINT32 ApicId; UINT32 Flags; - UINT32 SwProcApicId; UINT32 SocketNum; } EFI_CPU_ID_ORDER_MAP; =20 @@ -50,7 +47,7 @@ VOID *mLocalTable[] =3D { &Wsmt, }; =20 -EFI_ACPI_TABLE_PROTOCOL *mAcpiTable; +EFI_ACPI_TABLE_PROTOCOL *mAcpiTable; =20 UINT32 mNumOfBitShift =3D 6; BOOLEAN mForceX2ApicId; @@ -58,138 +55,19 @@ BOOLEAN mX2ApicEnabled; =20 EFI_MP_SERVICES_PROTOCOL *mMpService; BOOLEAN mCpuOrderSorted; -EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM]; -UINTN mNumberOfCPUs =3D 0; +EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable =3D NULL; +UINTN mNumberOfCpus =3D 0; UINTN mNumberOfEnabledCPUs =3D 0; =20 -// following are possible APICID Map for SKX -static const UINT32 ApicIdMapA[] =3D { //for SKUs have number of core > 16 - //it is 14 + 14 + 14 + 14 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x00000010, 0x00000011, - 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017, = 0x00000018, 0x00000019, - 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x00000020, 0x00000021, = 0x00000022, 0x00000023, - 0x00000024, 0x00000025, 0x00000026, 0x00000027, 0x00000028, 0x00000029, = 0x0000002A, 0x0000002B, - 0x0000002C, 0x0000002D, 0x00000030, 0x00000031, 0x00000032, 0x00000033, = 0x00000034, 0x00000035, - 0x00000036, 0x00000037, 0x00000038, 0x00000039, 0x0000003A, 0x0000003B, = 0x0000003C, 0x0000003D -}; - -static const UINT32 ApicIdMapB[] =3D { //for SKUs have number of cores <= =3D 16 use 32 ID space - //it is 16+16 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, = 0x00000016, 0x00000017, - 0x00000018, 0x00000019, 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, = 0x0000001E, 0x0000001F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - - -static const UINT32 ApicIdMapC[] =3D { //for SKUs have number of cores <= =3D 16 use 64 ID space - //it is 16+0+16+0 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, = 0x00000026, 0x00000027, - 0x00000028, 0x00000029, 0x0000002A, 0x0000002B, 0x0000002C, 0x0000002D, = 0x0000002E, 0x0000002F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - -static const UINT32 ApicIdMapD[] =3D { //for SKUs have number of cores <= =3D 8 use 16 ID space - //it is 16 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - -const UINT32 *mApicIdMap =3D NULL; - /** - This function detect the APICID map and update ApicID Map pointer + Find BSP in mCpuApicIdOrderTable. =20 - @param None + This function searches mCpuApicIdOrderTable to find the BSP ApicId, and = returns a number where the BSP is. =20 - @retval VOID - -**/ -VOID DetectApicIdMap(VOID) -{ - UINTN CoreCount; - - CoreCount =3D 0; - - if(mApicIdMap !=3D NULL) { - return; //aleady initialized - } - - mApicIdMap =3D ApicIdMapA; // default to > 16C SKUs - - CoreCount =3D mNumberOfEnabledCPUs / 2; - DEBUG ((DEBUG_INFO, "CoreCount - %d\n", CoreCount)); - - //DEBUG((EFI_D_ERROR, ":: Default to use Map A @ %08X FusedCoreCount: %0= 2d, sktlevel: %d\n",mApicIdMap, FusedCoreCount, mNumOfBitShift)); - // Dont assert for single core, single thread system. - //ASSERT (CoreCount !=3D 0); - - if(CoreCount <=3D 16) { - - if(mNumOfBitShift =3D=3D 4) { - mApicIdMap =3D ApicIdMapD; - //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap)); - } - - if(mNumOfBitShift =3D=3D 5) { - mApicIdMap =3D ApicIdMapB; - //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap)); - } - - if(mNumOfBitShift =3D=3D 6) { - mApicIdMap =3D ApicIdMapC; - //DEBUG((EFI_D_ERROR, ":: Use Map C @ %08X\n",mApicIdMap)); - } - - } - - return; -} - -/** - This function return the CoreThreadId of ApicId from ACPI ApicId Map arr= ay - - @param ApicId - - @retval Index of ACPI ApicId Map array + @param[in] ApicId Apic ID. =20 + @return Where the BSP is. **/ -UINT32 -GetIndexFromApicId ( - UINT32 ApicId - ) -{ - UINT32 CoreThreadId; - UINT32 i; - - ASSERT (mApicIdMap !=3D NULL); - - CoreThreadId =3D ApicId & ((1 << mNumOfBitShift) - 1); - - for(i =3D 0; i < (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdM= axCpuThreadCount)); i++) { - if(mApicIdMap[i] =3D=3D CoreThreadId) { - break; - } - } - - ASSERT (i <=3D (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMax= CpuThreadCount))); - - return i; -} - UINT32 ApicId2SwProcApicId ( UINT32 ApicId @@ -197,7 +75,7 @@ ApicId2SwProcApicId ( { UINT32 Index; =20 - for (Index =3D 0; Index < MAX_CPU_NUM; Index++) { + for (Index =3D 0; Index < mNumberOfCpus; Index++) { if ((mCpuApicIdOrderTable[Index].Flags =3D=3D 1) && (mCpuApicIdOrderTa= ble[Index].ApicId =3D=3D ApicId)) { return Index; } @@ -207,21 +85,25 @@ ApicId2SwProcApicId ( =20 } =20 +/** + Print Cpu Apic ID Table + + @param[in] CpuApicIdOrderTable Data will be dumped. +**/ VOID -DebugDisplayReOrderTable( - VOID +DebugDisplayReOrderTable ( + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable ) { UINT32 Index; =20 - DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\n"= )); - for (Index=3D0; IndexGetProcessorInfo ( - mMpService, - CurrProcessor, - &ProcessorInfoBuffer - ); + mMpService, + CurrProcessor, + &ProcessorInfoBuffer + ); =20 if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) !=3D 0)= { - if(ProcessorInfoBuffer.ProcessorId & 1) { //is 2nd thread - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[(I= ndex - 1) + MAX_CPU_NUM / 2]; - } else { //is primary thread - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[In= dex]; - Index++; - } + CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[= Index]; CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId; CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROCES= SOR_ENABLED_BIT) !=3D 0); CpuIdMapPtr->SocketNum =3D (UINT32)ProcessorInfoBuffer.Location.Pa= ckage; - CpuIdMapPtr->AcpiProcessorId =3D (CpuIdMapPtr->SocketNum * FixedPc= dGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + GetInde= xFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId; - CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.Locati= on.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.ProcessorId) = & CoreThreadMask)); - if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it star= ts from base 0 and contiguous - //may not necessory!!!!! - } + CpuIdMapPtr->AcpiProcessorId =3D ((UINT32)ProcessorInfoBuffer.Loca= tion.Package * (UINT32)mNumberOfCpus * 2) + Index; =20 //update processorbitMask if (CpuIdMapPtr->Flags =3D=3D 1) { - if(mForceX2ApicId) { CpuIdMapPtr->SocketNum &=3D 0x7; CpuIdMapPtr->AcpiProcessorId &=3D 0xFF; //keep lower 8bit due = to use Proc obj in dsdt - CpuIdMapPtr->SwProcApicId &=3D 0xFF; } } } else { //not enabled - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Inde= x]; + CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&TempCpuApicIdOrderTable[I= ndex]; CpuIdMapPtr->ApicId =3D (UINT32)-1; CpuIdMapPtr->Flags =3D 0; CpuIdMapPtr->AcpiProcessorId =3D (UINT32)-1; - CpuIdMapPtr->SwProcApicId =3D (UINT32)-1; CpuIdMapPtr->SocketNum =3D (UINT32)-1; } //end if PROC ENABLE } //end for CurrentProcessor =20 //keep for debug purpose - DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThread= Mask =3D %x, mNumOfBitShift =3D %x\n", CoreThreadMask, mNumOfBitShift)); - DebugDisplayReOrderTable(); + DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. CoreThreadM= ask =3D %x, mNumOfBitShift =3D %x\n", CoreThreadMask, mNumOfBitShift)); + DebugDisplayReOrderTable (TempCpuApicIdOrderTable); =20 //make sure 1st entry is BSP if(mX2ApicEnabled) { - BspApicId =3D (UINT32)AsmReadMsr64(0x802); + BspApicId =3D (UINT32)AsmReadMsr64 (0x802); } else { BspApicId =3D (*(volatile UINT32 *)(UINTN)0xFEE00020) >> 24; } - DEBUG ((EFI_D_INFO, "BspApicId - 0x%x\n", BspApicId)); + DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", BspApicId)); =20 - if(mCpuApicIdOrderTable[0].ApicId !=3D BspApicId) { + if (TempCpuApicIdOrderTable[0].ApicId !=3D BspApicId) { //check to see if 1st entry is BSP, if not swap it Index =3D ApicId2SwProcApicId(BspApicId); =20 - if(MAX_CPU_NUM <=3D Index) { - DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index = Bufferflow\n")); + if(mNumberOfCpus <=3D Index) { + DEBUG ((DEBUG_ERROR, "Asserting the SortCpuLocalApicInTable Index = Bufferflow\n")); return EFI_INVALID_PARAMETER; } =20 - TempVal =3D mCpuApicIdOrderTable[Index].ApicId; - mCpuApicIdOrderTable[Index].ApicId =3D mCpuApicIdOrderTable[0].ApicI= d; - mCpuApicIdOrderTable[0].ApicId =3D TempVal; - mCpuApicIdOrderTable[Index].Flags =3D mCpuApicIdOrderTable[0].Flags; - mCpuApicIdOrderTable[0].Flags =3D 1; - TempVal =3D mCpuApicIdOrderTable[Index].SwProcApicId; - mCpuApicIdOrderTable[Index].SwProcApicId =3D mCpuApicIdOrderTable[0]= .SwProcApicId; - mCpuApicIdOrderTable[0].SwProcApicId =3D TempVal; + TempVal =3D TempCpuApicIdOrderTable[Index].ApicId; + TempCpuApicIdOrderTable[Index].ApicId =3D TempCpuApicIdOrderTable[0]= .ApicId; + TempCpuApicIdOrderTable[0].ApicId =3D TempVal; + TempCpuApicIdOrderTable[Index].Flags =3D TempCpuApicIdOrderTable[0].= Flags; + TempCpuApicIdOrderTable[0].Flags =3D 1; //swap AcpiProcId - TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorId; - mCpuApicIdOrderTable[Index].AcpiProcessorId =3D mCpuApicIdOrderTable= [0].AcpiProcessorId; - mCpuApicIdOrderTable[0].AcpiProcessorId =3D TempVal; - + TempVal =3D TempCpuApicIdOrderTable[Index].AcpiProcessorId; + TempCpuApicIdOrderTable[Index].AcpiProcessorId =3D TempCpuApicIdOrde= rTable[0].AcpiProcessorId; + TempCpuApicIdOrderTable[0].AcpiProcessorId =3D TempVal; } =20 //Make sure no holes between enabled threads - for(CurrProcessor =3D 0; CurrProcessor < MAX_CPU_NUM; CurrProcessor++)= { - - if(mCpuApicIdOrderTable[CurrProcessor].Flags =3D=3D 0) { - //make sure disabled entry has ProcId set to FFs - mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32)-1; - mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D (UINT32)-1; - mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32)-1; - - for(Index =3D CurrProcessor+1; Index < MAX_CPU_NUM; Index++) { - if(mCpuApicIdOrderTable[Index].Flags =3D=3D 1) { - //move enabled entry up - mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1; - mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCpuApicIdOrder= Table[Index].ApicId; - mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D mCpuAp= icIdOrderTable[Index].AcpiProcessorId; - mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCpuApicI= dOrderTable[Index].SwProcApicId; - mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCpuApicIdOr= derTable[Index].SocketNum; - //disable moved entry - mCpuApicIdOrderTable[Index].Flags =3D 0; - mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1; - mCpuApicIdOrderTable[Index].AcpiProcessorId =3D (UINT32)-1; - mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1; - break; - } - } + mCpuApicIdOrderTable =3D AllocateZeroPool (mNumberOfCpus * sizeof (EFI= _CPU_ID_ORDER_MAP)); + + for (CurrProcessor =3D 0, Index =3D 0; Index < mNumberOfCpus; Index++)= { + if ((TempCpuApicIdOrderTable[Index].ApicId & 1) =3D=3D 0) { // prima= ry thread + mCpuApicIdOrderTable[CurrProcessor].ApicId =3D TempCpuApicIdOrderT= able[Index].ApicId; + mCpuApicIdOrderTable[CurrProcessor].Flags =3D TempCpuApicIdOrderTa= ble[Index].Flags; + mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D TempCpuApicIdOrd= erTable[Index].SocketNum; + mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D TempCpuApi= cIdOrderTable[Index].AcpiProcessorId; + CurrProcessor++; + } + } + + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + if ((TempCpuApicIdOrderTable[Index].ApicId & 1) =3D=3D 1) { //second= thread + mCpuApicIdOrderTable[CurrProcessor].ApicId =3D TempCpuApicIdOrderT= able[Index].ApicId; + mCpuApicIdOrderTable[CurrProcessor].Flags =3D TempCpuApicIdOrderTa= ble[Index].Flags; + mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D TempCpuApicIdOrd= erTable[Index].SocketNum; + mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D TempCpuApi= cIdOrderTable[Index].AcpiProcessorId; + CurrProcessor++; + } + } + + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + if (TempCpuApicIdOrderTable[Index].Flags =3D=3D 0) { // not enabled + mCpuApicIdOrderTable[CurrProcessor].ApicId =3D TempCpuApicIdOrderT= able[Index].ApicId; + mCpuApicIdOrderTable[CurrProcessor].Flags =3D TempCpuApicIdOrderTa= ble[Index].Flags; + mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D TempCpuApicIdOrd= erTable[Index].SocketNum; + mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D TempCpuApi= cIdOrderTable[Index].AcpiProcessorId; + CurrProcessor++; } } =20 //keep for debug purpose - DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n")); - DebugDisplayReOrderTable(); + DEBUG ((DEBUG_INFO, "APIC ID Order Table ReOrdered\n")); + DebugDisplayReOrderTable (mCpuApicIdOrderTable); =20 mCpuOrderSorted =3D TRUE; } @@ -602,11 +472,11 @@ InitializeMadtHeader ( } =20 Status =3D InitializeHeader ( - &MadtHeader->Header, - EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, - 0 - ); + &MadtHeader->Header, + EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + 0 + ); if (EFI_ERROR (Status)) { return Status; } @@ -784,11 +654,11 @@ BuildAcpiTable ( // Allocate the memory needed for the table. // Status =3D AllocateTable ( - TableSpecificHdrLength, - Structures, - StructureCount, - &InternalTable - ); + TableSpecificHdrLength, + Structures, + StructureCount, + &InternalTable + ); if (EFI_ERROR (Status)) { return Status; } @@ -871,18 +741,22 @@ InstallMadtFromScratch ( NewMadtTable =3D NULL; MaxMadtStructCount =3D 0; =20 - DetectApicIdMap(); + mCpuApicIdOrderTable =3D AllocateZeroPool (mNumberOfCpus * sizeof (EFI_C= PU_ID_ORDER_MAP)); + if (mCpuApicIdOrderTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structur= e pointer array\n")); + return EFI_OUT_OF_RESOURCES; + } =20 // Call for Local APIC ID Reorder Status =3D SortCpuLocalApicInTable (); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status)); + DEBUG ((DEBUG_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status)); goto Done; } =20 MaxMadtStructCount =3D (UINT32) ( - MAX_CPU_NUM + // processor local APIC structures - MAX_CPU_NUM + // processor local x2APIC structures + mNumberOfCpus + // processor local APIC structures + mNumberOfCpus + // processor local x2APIC structures 1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures 2 + // interrupt source override structures 1 + // local APIC NMI structures @@ -906,11 +780,11 @@ InstallMadtFromScratch ( // Status =3D InitializeMadtHeader (&MadtTableHeader); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "InitializeMadtHeader failed: %r\n", Status)); + DEBUG ((DEBUG_ERROR, "InitializeMadtHeader failed: %r\n", Status)); goto Done; } =20 - DEBUG ((EFI_D_INFO, "Number of CPUs detected =3D %d \n", mNumberOfCPUs)); + DEBUG ((DEBUG_INFO, "Number of CPUs detected =3D %d \n", mNumberOfCpus)); =20 // // Build Processor Local APIC Structures and Processor Local X2APIC Stru= ctures @@ -923,7 +797,7 @@ InstallMadtFromScratch ( ProcLocalX2ApicStruct.Reserved[0] =3D 0; ProcLocalX2ApicStruct.Reserved[1] =3D 0; =20 - for (Index =3D 0; Index < MAX_CPU_NUM; Index++) { + for (Index =3D 0; Index < mNumberOfCpus; Index++) { // // If x2APIC mode is not enabled, and if it is possible to express the // APIC ID as a UINT8, use a processor local APIC structure. Otherwise, @@ -936,10 +810,10 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &ProcLocalApicStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &ProcLocalApicStruct, + &MadtStructs[MadtStructsIndex++] + ); } else if (mCpuApicIdOrderTable[Index].ApicId !=3D 0xFFFFFFFF) { ProcLocalX2ApicStruct.Flags =3D (UINT8) mCpuApicIdOrderTa= ble[Index].Flags; ProcLocalX2ApicStruct.X2ApicId =3D mCpuApicIdOrderTable[Inde= x].ApicId; @@ -947,13 +821,13 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct, + &MadtStructs[MadtStructsIndex++] + ); } if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: = %r\n", Status)); + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: = %r\n", Status)); goto Done; } } @@ -965,44 +839,44 @@ InstallMadtFromScratch ( IoApicStruct.Length =3D sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE); IoApicStruct.Reserved =3D 0; =20 - PcIoApicEnable =3D PcdGet32(PcdPcIoApicEnable); + PcIoApicEnable =3D PcdGet32 (PcdPcIoApicEnable); =20 - if (FixedPcdGet32(PcdMaxCpuSocketCount) <=3D 4) { + if (FixedPcdGet32 (PcdMaxCpuSocketCount) <=3D 4) { IoApicStruct.IoApicId =3D PcdGet8(PcdIoApicId); IoApicStruct.IoApicAddress =3D PcdGet32(PcdIoApicAddress); IoApicStruct.GlobalSystemInterruptBase =3D 0; ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &IoApicStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &IoApicStruct, + &MadtStructs[MadtStructsIndex++] + ); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", St= atus)); + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", St= atus)); goto Done; } } =20 for (PcIoApicIndex =3D 0; PcIoApicIndex < PcdGet8(PcdPcIoApicCount); PcI= oApicIndex++) { - PcIoApicMask =3D (1 << PcIoApicIndex); - if ((PcIoApicEnable & PcIoApicMask) =3D=3D 0) { - continue; - } + PcIoApicMask =3D (1 << PcIoApicIndex); + if ((PcIoApicEnable & PcIoApicMask) =3D=3D 0) { + continue; + } =20 - IoApicStruct.IoApicId =3D (UINT8)(PcdGet8(PcdPcIoAp= icIdBase) + PcIoApicIndex); - IoApicStruct.IoApicAddress =3D CurrentIoApicAddress; - CurrentIoApicAddress =3D (CurrentIoApicAddress & 0= xFFFF8000) + 0x8000; - IoApicStruct.GlobalSystemInterruptBase =3D (UINT32)(24 + (PcIoApicIn= dex * 8)); - ASSERT (MadtStructsIndex < MaxMadtStructCount); - Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &IoApicStruct, - &MadtStructs[MadtStructsIndex++] - ); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", = Status)); - goto Done; - } + IoApicStruct.IoApicId =3D (UINT8)(PcdGet8(PcdPcIoApic= IdBase) + PcIoApicIndex); + IoApicStruct.IoApicAddress =3D CurrentIoApicAddress; + CurrentIoApicAddress =3D (CurrentIoApicAddress & 0xF= FFF8000) + 0x8000; + IoApicStruct.GlobalSystemInterruptBase =3D (UINT32)(24 + (PcIoApicInde= x * 8)); + ASSERT (MadtStructsIndex < MaxMadtStructCount); + Status =3D CopyStructure ( + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &IoApicStruct, + &MadtStructs[MadtStructsIndex++] + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", St= atus)); + goto Done; + } } =20 // @@ -1021,12 +895,12 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &IntSrcOverrideStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &IntSrcOverrideStruct, + &MadtStructs[MadtStructsIndex++] + ); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ2 source override) failed:= %r\n", Status)); + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ2 source override) failed:= %r\n", Status)); goto Done; } =20 @@ -1040,12 +914,12 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &IntSrcOverrideStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &IntSrcOverrideStruct, + &MadtStructs[MadtStructsIndex++] + ); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ9 source override) failed:= %r\n", Status)); + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ9 source override) failed:= %r\n", Status)); goto Done; } =20 @@ -1060,12 +934,12 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &LocalApciNmiStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &LocalApciNmiStruct, + &MadtStructs[MadtStructsIndex++] + ); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Stat= us)); + DEBUG ((DEBUG_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Stat= us)); goto Done; } =20 @@ -1084,10 +958,10 @@ InstallMadtFromScratch ( =20 ASSERT (MadtStructsIndex < MaxMadtStructCount); Status =3D CopyStructure ( - &MadtTableHeader.Header, - (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct, - &MadtStructs[MadtStructsIndex++] - ); + &MadtTableHeader.Header, + (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct, + &MadtStructs[MadtStructsIndex++] + ); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "CopyMadtStructure (x2APIC NMI) failed: %r\n", = Status)); goto Done; @@ -1098,14 +972,14 @@ InstallMadtFromScratch ( // Build Madt Structure from the Madt Header and collection of pointers = in MadtStructs[] // Status =3D BuildAcpiTable ( - (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader, - sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER), - MadtStructs, - MadtStructsIndex, - (UINT8 **)&NewMadtTable - ); + (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader, + sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER), + MadtStructs, + MadtStructsIndex, + (UINT8 **) &NewMadtTable + ); if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "BuildAcpiTable failed: %r\n", Status)); + DEBUG ((DEBUG_ERROR, "BuildAcpiTable failed: %r\n", Status)); goto Done; } =20 @@ -1113,11 +987,11 @@ InstallMadtFromScratch ( // Publish Madt Structure to ACPI // Status =3D mAcpiTable->InstallAcpiTable ( - mAcpiTable, - NewMadtTable, - NewMadtTable->Header.Length, - &TableHandle - ); + mAcpiTable, + NewMadtTable, + NewMadtTable->Header.Length, + &TableHandle + ); =20 Done: // @@ -1136,6 +1010,10 @@ Done: FreePool (NewMadtTable); } =20 + if (mCpuApicIdOrderTable !=3D NULL) { + FreePool (mCpuApicIdOrderTable); + } + return Status; } =20 @@ -1155,8 +1033,8 @@ InstallMcfgFromScratch ( PciSegmentInfo =3D GetPciSegmentInfo (&SegmentCount); =20 McfgTable =3D AllocateZeroPool ( - sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_T= ABLE_HEADER) + - sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE= _BASE_ADDRESS_ALLOCATION_STRUCTURE) * SegmentCount + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_= TABLE_HEADER) + + sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPAC= E_BASE_ADDRESS_ALLOCATION_STRUCTURE) * SegmentCount ); if (McfgTable =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "Could not allocate MCFG structure\n")); @@ -1164,11 +1042,11 @@ InstallMcfgFromScratch ( } =20 Status =3D InitializeHeader ( - &McfgTable->Header, - EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRES= S_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, - 0 - ); + &McfgTable->Header, + EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BA= SE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVIS= ION, + 0 + ); if (EFI_ERROR (Status)) { return Status; } @@ -1192,11 +1070,11 @@ InstallMcfgFromScratch ( // Publish Madt Structure to ACPI // Status =3D mAcpiTable->InstallAcpiTable ( - mAcpiTable, - McfgTable, - McfgTable->Header.Length, - &TableHandle - ); + mAcpiTable, + McfgTable, + McfgTable->Header.Length, + &TableHandle + ); =20 return Status; } @@ -1280,7 +1158,7 @@ PlatformUpdateTables ( switch (Table->Signature) { =20 case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE: - ASSERT(FALSE); + ASSERT (FALSE); break; =20 case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE: @@ -1324,9 +1202,9 @@ PlatformUpdateTables ( FadtHeader->XGpe1Blk.AccessSize =3D 0; } =20 - DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table )); - DEBUG(( EFI_D_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch= )); - DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags )); + DEBUG ((DEBUG_INFO, "ACPI FADT table @ address 0x%x\n", Table)); + DEBUG ((DEBUG_INFO, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch)= ); + DEBUG ((DEBUG_INFO, " Flags 0x%x\n", FadtHeader->Flags)); break; =20 case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE: @@ -1346,12 +1224,12 @@ PlatformUpdateTables ( HpetBlockId.Bits.VendorId =3D HpetCapabilities.Bits.VendorId; HpetTable->EventTimerBlockId =3D HpetBlockId.Uint32; HpetTable->MainCounterMinimumClockTickInPeriodicMode =3D (UINT16)HpetC= apabilities.Bits.CounterClockPeriod; - DEBUG(( EFI_D_ERROR, "ACPI HPET table @ address 0x%x\n", Table )); - DEBUG(( EFI_D_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddres= s) )); + DEBUG ((DEBUG_INFO, "ACPI HPET table @ address 0x%x\n", Table)); + DEBUG ((DEBUG_INFO, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress= ))); break; =20 case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADD= RESS_DESCRIPTION_TABLE_SIGNATURE: - ASSERT(FALSE); + ASSERT (FALSE); break; =20 default: @@ -1403,8 +1281,8 @@ IsHardwareChange ( // pFADT->XDsdt // HWChangeSize =3D HandleCount + 1; - HWChange =3D AllocateZeroPool( sizeof(UINT32) * HWChangeSize ); - ASSERT( HWChange !=3D NULL ); + HWChange =3D AllocateZeroPool (sizeof(UINT32) * HWChangeSize); + ASSERT(HWChange !=3D NULL); =20 if (HWChange =3D=3D NULL) return; =20 @@ -1445,14 +1323,14 @@ IsHardwareChange ( // Calculate CRC value with HWChange data. // Status =3D gBS->CalculateCrc32(HWChange, HWChangeSize, &CRC); - DEBUG((DEBUG_INFO, "CRC =3D %x and Status =3D %r\n", CRC, Status)); + DEBUG ((DEBUG_INFO, "CRC =3D %x and Status =3D %r\n", CRC, Status)); =20 // // Set HardwareSignature value based on CRC value. // FacsPtr =3D (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT= ->FirmwareCtrl; FacsPtr->HardwareSignature =3D CRC; - FreePool( HWChange ); + FreePool (HWChange); } =20 VOID @@ -1475,17 +1353,16 @@ UpdateLocalTable ( =20 if (Version !=3D EFI_ACPI_TABLE_VERSION_NONE) { Status =3D mAcpiTable->InstallAcpiTable ( - mAcpiTable, - CurrentTable, - CurrentTable->Length, - &TableHandle - ); + mAcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); ASSERT_EFI_ERROR (Status); } } } =20 - VOID EFIAPI AcpiEndOfDxeEvent ( @@ -1493,16 +1370,14 @@ AcpiEndOfDxeEvent ( VOID *ParentImageHandle ) { - if (Event !=3D NULL) { - gBS->CloseEvent(Event); + gBS->CloseEvent (Event); } =20 - // // Calculate Hardware Signature value based on current platform configur= ations // - IsHardwareChange(); + IsHardwareChange (); } =20 /** @@ -1526,7 +1401,6 @@ InstallAcpiPlatform ( EFI_STATUS Status; EFI_EVENT EndOfDxeEvent; =20 - Status =3D gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID = **)&mMpService); ASSERT_EFI_ERROR (Status); =20 @@ -1550,19 +1424,19 @@ InstallAcpiPlatform ( // Determine the number of processors // mMpService->GetNumberOfProcessors ( - mMpService, - &mNumberOfCPUs, - &mNumberOfEnabledCPUs - ); - ASSERT (mNumberOfCPUs <=3D MAX_CPU_NUM && mNumberOfEnabledCPUs >=3D 1); - DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs)); + mMpService, + &mNumberOfCpus, + &mNumberOfEnabledCPUs + ); + + DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus)); DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs)= ); =20 DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled)); DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId)); =20 // support up to 64 threads/socket - AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL= ); + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NUL= L); mNumOfBitShift &=3D 0x1F; DEBUG ((DEBUG_INFO, "mNumOfBitShift - 0x%x\n", mNumOfBitShift)); =20 --=20 2.32.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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