From nobody Mon Feb 9 22:38:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78484+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78484+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880462; cv=none; d=zohomail.com; s=zohoarc; b=b0SdX43kcUaEjU20HPr71athwjG9k0/ksKvKWUvr9S50v1lFDD5aazjv5MiZWai4O704HFlZWtbVdiKjePpY5lt4mu7LnqnzbvnrwgiEHBdB20UV2aMXQj3AtzK4I151HZR5SDvqqcFOgGDK8Ahoc+SPgvDe/5GUkUPQ5Jl5S+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880462; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sHRip4U5JvIOaWM8SZ+lffnNs3yoZzRsyYQNn+gQkiQ=; b=a6e3vx9hMMefQR4fabMhbFuak2MuAVqygO/GJFwLmhmp8pMjcUPMux4F9jH3jdQGxKHC4GQNEbBUajYJO2Dgd7yWgy49ZZYdRvHLnnV9Ce6liv6Oa6GPh4M6HkiVaIqV3xS5i4KZco7DvYh1gg261F+fYkseUqL9IksAWp3k/W0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78484+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162788046259982.40254144484129; Sun, 1 Aug 2021 22:01:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9HoRYY1788612xJyupnXCs2S; Sun, 01 Aug 2021 22:01:02 -0700 X-Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) by mx.groups.io with SMTP id smtpd.web08.16085.1627880461426155379 for ; Sun, 01 Aug 2021 22:01:01 -0700 X-Received: by mail-lf1-f43.google.com with SMTP id m13so31437065lfg.13 for ; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) X-Gm-Message-State: IxFMSIhtxORg98yfq6OJlnshx1787277AA= X-Google-Smtp-Source: ABdhPJyBLp5EYXV1NGpEI46a0vI5Lh5m+cM3psysIdDDiNOvIpyzcOMG0iCKZ5/cTFnLUed9daGHjw== X-Received: by 2002:ac2:54a4:: with SMTP id w4mr11655857lfk.344.1627880459499; Sun, 01 Aug 2021 22:00:59 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:00:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Date: Mon, 2 Aug 2021 07:00:46 +0200 Message-Id: <20210802050051.2831716-2-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880462; bh=HDC1nQF+rJf5+7jwYy8sPyWSXguhvJDYGAvk6uT8efo=; h=Cc:Date:From:Reply-To:Subject:To; b=kNolUqwRej+W9gFgdE9DR8vT07z3ZmnqgJTGfDHlgPgUjqqPGD2TCnuYvcPZbnsafjK WEW5tWwthv9wUNkwd+xUGoPXZW3HcRoXMjh/RkqXYeEuaYgk4aPIi12VbAnrj9O2JyZYX M8VXk/UsQELOFfulMYe6cMXAOVvHnggcsmA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880463087100004 Content-Type: text/plain; charset="utf-8" Until now the virtual memory map for the single PCIE configuration space was hardcoded via PCDs and assumed adjacency to the SoC MMIO region (0xf0000000 - 4GB). Remove this limitation by splitting the regions and allowing to obtain the PCIE configuration space settings from ArmadaBoardDescLib. It is a preparation patch for adding support for multiple PCIE controllers. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 += ++++++++++++++- 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 756d875f6c..41d9cb9247 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -100,8 +100,5 @@ # RTC gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 - # SoC Configuration Space - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 - # Variable store gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index d398d9432f..b1aa0ae4d0 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -400,9 +400,6 @@ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 =20 - # SoC Configuration Space - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000 - !if $(CAPSULE_ENABLE) [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index 94427177ef..8b77a07ab3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -20,6 +20,7 @@ Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaBoardDescLib ArmadaSoCDescLib ArmLib ArmSmcLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index cc19694d37..853c1b4e56 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include =20 +#include #include #include #include @@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighStart; UINT64 MemHighSize; UINT64 ConfigSpaceBaseAddr; + UINTN PcieControllerCount; + UINTN PcieIndex; + MV_PCIE_CONTROLLER CONST *PcieControllers; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; EFI_STATUS Status; =20 @@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap ( mVirtualMemoryTable[Index].Length =3D MemLowSize; mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; =20 - // Configuration space + // SoC MMIO configuration space mVirtualMemoryTable[++Index].PhysicalBase =3D ConfigSpaceBaseAddr; mVirtualMemoryTable[Index].VirtualBase =3D ConfigSpaceBaseAddr; mVirtualMemoryTable[Index].Length =3D SIZE_4GB - ConfigSpaceBas= eAddr; mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; =20 + // PCIE ECAM + Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControll= erCount); + ASSERT_EFI_ERROR (Status); + for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) { + mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; + mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; + mVirtualMemoryTable[Index].Length =3D SIZE_256MB; + mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE; + } + if (MemSize > MemLowSize) { // // If we have more than MemLowSize worth of DRAM, the remainder will be --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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