From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78484+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78484+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880462; cv=none; d=zohomail.com; s=zohoarc; b=b0SdX43kcUaEjU20HPr71athwjG9k0/ksKvKWUvr9S50v1lFDD5aazjv5MiZWai4O704HFlZWtbVdiKjePpY5lt4mu7LnqnzbvnrwgiEHBdB20UV2aMXQj3AtzK4I151HZR5SDvqqcFOgGDK8Ahoc+SPgvDe/5GUkUPQ5Jl5S+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880462; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sHRip4U5JvIOaWM8SZ+lffnNs3yoZzRsyYQNn+gQkiQ=; b=a6e3vx9hMMefQR4fabMhbFuak2MuAVqygO/GJFwLmhmp8pMjcUPMux4F9jH3jdQGxKHC4GQNEbBUajYJO2Dgd7yWgy49ZZYdRvHLnnV9Ce6liv6Oa6GPh4M6HkiVaIqV3xS5i4KZco7DvYh1gg261F+fYkseUqL9IksAWp3k/W0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78484+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162788046259982.40254144484129; Sun, 1 Aug 2021 22:01:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9HoRYY1788612xJyupnXCs2S; Sun, 01 Aug 2021 22:01:02 -0700 X-Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) by mx.groups.io with SMTP id smtpd.web08.16085.1627880461426155379 for ; Sun, 01 Aug 2021 22:01:01 -0700 X-Received: by mail-lf1-f43.google.com with SMTP id m13so31437065lfg.13 for ; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) X-Gm-Message-State: IxFMSIhtxORg98yfq6OJlnshx1787277AA= X-Google-Smtp-Source: ABdhPJyBLp5EYXV1NGpEI46a0vI5Lh5m+cM3psysIdDDiNOvIpyzcOMG0iCKZ5/cTFnLUed9daGHjw== X-Received: by 2002:ac2:54a4:: with SMTP id w4mr11655857lfk.344.1627880459499; Sun, 01 Aug 2021 22:00:59 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:00:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces Date: Mon, 2 Aug 2021 07:00:46 +0200 Message-Id: <20210802050051.2831716-2-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880462; bh=HDC1nQF+rJf5+7jwYy8sPyWSXguhvJDYGAvk6uT8efo=; h=Cc:Date:From:Reply-To:Subject:To; b=kNolUqwRej+W9gFgdE9DR8vT07z3ZmnqgJTGfDHlgPgUjqqPGD2TCnuYvcPZbnsafjK WEW5tWwthv9wUNkwd+xUGoPXZW3HcRoXMjh/RkqXYeEuaYgk4aPIi12VbAnrj9O2JyZYX M8VXk/UsQELOFfulMYe6cMXAOVvHnggcsmA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880463087100004 Content-Type: text/plain; charset="utf-8" Until now the virtual memory map for the single PCIE configuration space was hardcoded via PCDs and assumed adjacency to the SoC MMIO region (0xf0000000 - 4GB). Remove this limitation by splitting the regions and allowing to obtain the PCIE configuration space settings from ArmadaBoardDescLib. It is a preparation patch for adding support for multiple PCIE controllers. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 -= -- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 += ++++++++++++++- 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 756d875f6c..41d9cb9247 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -100,8 +100,5 @@ # RTC gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 - # SoC Configuration Space - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 - # Variable store gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index d398d9432f..b1aa0ae4d0 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -400,9 +400,6 @@ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 =20 - # SoC Configuration Space - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000 - !if $(CAPSULE_ENABLE) [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index 94427177ef..8b77a07ab3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -20,6 +20,7 @@ Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaBoardDescLib ArmadaSoCDescLib ArmLib ArmSmcLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index cc19694d37..853c1b4e56 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include =20 +#include #include #include #include @@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighStart; UINT64 MemHighSize; UINT64 ConfigSpaceBaseAddr; + UINTN PcieControllerCount; + UINTN PcieIndex; + MV_PCIE_CONTROLLER CONST *PcieControllers; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; EFI_STATUS Status; =20 @@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap ( mVirtualMemoryTable[Index].Length =3D MemLowSize; mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; =20 - // Configuration space + // SoC MMIO configuration space mVirtualMemoryTable[++Index].PhysicalBase =3D ConfigSpaceBaseAddr; mVirtualMemoryTable[Index].VirtualBase =3D ConfigSpaceBaseAddr; mVirtualMemoryTable[Index].Length =3D SIZE_4GB - ConfigSpaceBas= eAddr; mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_DEVICE; =20 + // PCIE ECAM + Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControll= erCount); + ASSERT_EFI_ERROR (Status); + for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) { + mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; + mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; + mVirtualMemoryTable[Index].Length =3D SIZE_256MB; + mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE; + } + if (MemSize > MemLowSize) { // // If we have more than MemLowSize worth of DRAM, the remainder will be --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78484): https://edk2.groups.io/g/devel/message/78484 Mute This Topic: https://groups.io/mt/84605049/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78485+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78485+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880463; cv=none; d=zohomail.com; s=zohoarc; b=Z7xZ/MwZyWfeZIR5yQgiwG/m/HraAoUmyjPypbgqUkPDVeBtJF3QeAyhPxXyd7LRc5ncxeqWe5/i6UQWRbF5lgjdu+KgXXYuSLiBK4TUj8F1mUzMYU1PUqtNZk2PtY46E7gCmmtQJTXwF8gCOgXaR8J3tEvnxgQDP8pyY1CkYkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880463; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qrw7EX3PbnWxjuj4S4OMUEZvBju/a/cE2bivDliAn+M=; b=jK4CCaXInKQxCgZBynNsFZdbgZ8CiPbpNtLHs7a6fJ10Y6jNa3S+R/h1Lan3g00mghtguM4cVfOW5CaLX3h3fJq4ObOxLjHohMEY2U0zUzJZCyCTWDJZGg+eKWmBLs0VD15/QVEa4EIkLc2Bvc1+vSfG4OhgChYUeaHv5ufaFSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78485+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1627880463254819.462301909698; Sun, 1 Aug 2021 22:01:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RBmpYY1788612xoItVgHIONO; Sun, 01 Aug 2021 22:01:02 -0700 X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web12.16047.1627880462147930050 for ; Sun, 01 Aug 2021 22:01:02 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id e5so22322614ljp.6 for ; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) X-Gm-Message-State: 0A5g4C0l8uWNl9NrMc9ax7Tqx1787277AA= X-Google-Smtp-Source: ABdhPJx4imLdIDW2nuqApoZMPc1WZvqfzyjlU3DsovT957rDEjOaHfzcI2sgpMh/WYZJ11nPCAu7Tw== X-Received: by 2002:a2e:321a:: with SMTP id y26mr9921638ljy.463.1627880460511; Sun, 01 Aug 2021 22:01:00 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:00 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 2/6] Marvell: Armada7k8k/OcteonTx: Allow tuning PCIE config space size Date: Mon, 2 Aug 2021 07:00:47 +0200 Message-Id: <20210802050051.2831716-3-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880462; bh=gcmJtBBLFv1G+wj3MUaQ5Vu/UATAxoWXx1PvX/Ap2PM=; h=Cc:Date:From:Reply-To:Subject:To; b=GOAnwp0fUKPNPH/HBakYoQTSD57/QBEvduVWbxevOlPvQrI3ka9coneFxcZJVYUS7h+ 4RLhI8nbAXLToyMecQmHMMTJ9uF6OqpSjnB7dLd1nOYl7jWAKsvfS+IUkxuRoSBGlKBKU bmj0EYTnYhZUSAjcxdvqwPOsEmQ9HJOTg0g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880465110100009 Content-Type: text/plain; charset="utf-8" Until now it was assumed that the configuration space size is 256MB. Allow setting different values in the board description library instance for each platform. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 4 ++= +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 2ad19aae7a..80c55eb3a7 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -111,6 +111,7 @@ typedef struct { typedef struct { EFI_PHYSICAL_ADDRESS PcieDbiAddress; EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + UINT64 ConfigSpaceSize; BOOLEAN HaveResetGpio; MV_GPIO_PIN PcieResetGpio; UINT64 PcieBusMin; diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index 853c1b4e56..43aacb7a11 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -141,7 +141,9 @@ ArmPlatformGetVirtualMemoryMap ( for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) { mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd= ex].ConfigSpaceAddress; - mVirtualMemoryTable[Index].Length =3D SIZE_256MB; + mVirtualMemoryTable[Index].Length =3D (PcieControllers[PcieIn= dex].ConfigSpaceSize =3D=3D 0) ? + SIZE_256MB : + PcieControllers[PcieIndex= ].ConfigSpaceSize; mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI= BUTE_DEVICE; } =20 --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78485): https://edk2.groups.io/g/devel/message/78485 Mute This Topic: https://groups.io/mt/84605050/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78486+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78486+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880464; cv=none; d=zohomail.com; s=zohoarc; b=IQowicgm3tLnD+YBh7UbbleDKMGa6Z+lHLwOmWfBmujbrJ/pGowTJQCR8+TDzS/aCvSi90rdIV6ZKO8W+xVq/MPNGZ5jw7qFoTmYXtvWzp/Nc1KTA7C9E5iVoStQ4z/g5ZxxrM7TruHoHKB/tyvJ0IhEMZp4LSdYbyQGBicm8kQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880464; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GiqIR1xq7WkhOGOcMLp6rr/Zi5QM3cctEBa1GKJjbpI=; b=I93u5mZ4YLZOzJkaj+8PaDD6EHXSSZqvrXk7Ov1aSwOZ6iGFcD5myuNwRZ/FSFxFKnAtCZNb/qE82Kb0c37z5Gs/fYp+ZPeUT/hjJKjccdr5zJypP3pUxzmZlFB8n5QhMUx7KnMP6yXgUFZgR353iQoCxJqppWxssxz1HkvbqoA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78486+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162788046418437.10178692483419; Sun, 1 Aug 2021 22:01:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LAn6YY1788612xORX1QEPWyw; Sun, 01 Aug 2021 22:01:03 -0700 X-Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mx.groups.io with SMTP id smtpd.web10.16138.1627880463166850112 for ; Sun, 01 Aug 2021 22:01:03 -0700 X-Received: by mail-lf1-f44.google.com with SMTP id bq29so5897074lfb.5 for ; Sun, 01 Aug 2021 22:01:02 -0700 (PDT) X-Gm-Message-State: laclCtITgTn6zV7nb2grvFl1x1787277AA= X-Google-Smtp-Source: ABdhPJy2M9H1pnv/O5f3f8n2ID5uuyoCScLFCXDUiVLAKG1DXBOpHk5CCww4QIgZe7OgwjgD5LrkIg== X-Received: by 2002:ac2:53ab:: with SMTP id j11mr3837004lfh.391.1627880461544; Sun, 01 Aug 2021 22:01:01 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation Date: Mon, 2 Aug 2021 07:00:48 +0200 Message-Id: <20210802050051.2831716-4-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880463; bh=oNjgykaYrVCkXWDpnfm/xexNaoZMTsnIY8anE32HLOE=; h=Cc:Date:From:Reply-To:Subject:To; b=mvCn21+ONryf5KxEulpngLKGzLl891MqJC1r4fsd2hM7A7PJy7G2uEfSm1Ln5zuK/Li qGofoW9cYcWGgZmcSxlVMXFqNP6kmFL5ihbt1+yIlGmv+p2Elqhy/0o/ZkZl7nmsz7ULb bxnln86yXGQASrNLKG2w+YeTEBmedHLN5K4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627881367427100001 Content-Type: text/plain; charset="utf-8" On CN913x-based platforms it is possible to have up to 9 PCIE root complexes. In such case it may be necessary to configure more configuration spaces with smaller bus count, so that to fit the memory layout constraints. For that purpose remove forcing ECAM base to be divisible by SIZE_256MB. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLibConstructor.c | 1 - 1 file changed, 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k= 8kPciHostBridgeLib/PciHostBridgeLibConstructor.c index 067e57a2dc..87e57aeae3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLibConstructor.c @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor ( PcieController =3D &(BoardPcieDescription->PcieControllers[Index]); =20 ASSERT (PcieController->PcieBusMin =3D=3D 0); - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB =3D=3D 0); =20 if (PcieController->HaveResetGpio =3D=3D TRUE) { /* Reset PCIE slot */ --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78486): https://edk2.groups.io/g/devel/message/78486 Mute This Topic: https://groups.io/mt/84605051/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78487+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78487+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880465; cv=none; d=zohomail.com; s=zohoarc; b=eat8F+pjOZyveD6He/t3MoogP4Nm1UfqweZjH1JTybspp7H+Vc29g0f0sRsd7gH88G+K7D6Bpv38JBdfa9/9ji76oK0PvuqTJ8yMY6u1QnQ9epnkMMPegJJtdOHlCVYPmkzZwdyqNa0wz/6OUVvD/Jehc8p+0B+ShLiumucmIoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880465; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vj388C0mnmBV9Yv1fpJ6BblrkzVhxox2cflG9MlInLs=; b=a2/25e0SAavQiNBIEbzoCh0mxhMIexodIW3eX8hJJ9cPFK0LlNNW1Xb7vEz83vlKfGPLjaYPmTY9Dnm12n/IpHq9Rl41BeHJPVxxegupwSZHFPQfYzaheI7PIT0883K1YaP2IqOz5qNWIv+uA3beY49BWxiG2OSUyb0amzw2hxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78487+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1627880465524517.540274595365; Sun, 1 Aug 2021 22:01:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eOcnYY1788612xWYC6R5CPIM; Sun, 01 Aug 2021 22:01:05 -0700 X-Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mx.groups.io with SMTP id smtpd.web09.15978.1627880464277219633 for ; Sun, 01 Aug 2021 22:01:04 -0700 X-Received: by mail-lf1-f51.google.com with SMTP id h14so31457313lfv.7 for ; Sun, 01 Aug 2021 22:01:04 -0700 (PDT) X-Gm-Message-State: 7g4YlDEePdu5wNdjgDSRFzlHx1787277AA= X-Google-Smtp-Source: ABdhPJwkrOcHuCx0dVhKHRAbZOouEH4eQUzpc6cBYSUVz7dQ1O/lZpI3s5ek7OhXWMFJCmcn1VVVyQ== X-Received: by 2002:a19:7103:: with SMTP id m3mr11598409lfc.5.1627880462616; Sun, 01 Aug 2021 22:01:02 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:02 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Kamil Koczurek , Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 4/6] Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support Date: Mon, 2 Aug 2021 07:00:49 +0200 Message-Id: <20210802050051.2831716-5-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880465; bh=ucht/7JZAoyFPMjMRzyq/HjonKXfWwZSw+0JYPgPRPg=; h=Cc:Date:From:Reply-To:Subject:To; b=TFz3Ig6O0ysyt3pO/A+02z88WW7V0y+Wsv9aQbZqax1GsWMjxHTt6buzLN0qlLGZiGy o0h+yYjpZLGpD5jF4uigqbu1J/eO+aTW1+R6Jvt+pcx1rNDNTVeraUzlegmID5SLXzAPU lSLRCx1AwItItVt52weXYxRsAH/qDeqOEtM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880467498100017 Content-Type: text/plain; charset="utf-8" From: Kamil Koczurek In order to support more than one PCIE port, PciHostBridgeLib must generate appropriate device paths according to the board description and assign correct segment numbers instead of a hard-coded 0. Additionally, PciSegmentLib has to operate on a proper config spaces base address (depending on the segment number). Add the library constructor routine and obtain the necessary data from the Marvell board description protocol. Remove unused PCIE-related PCD's. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc = | 4 -- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc = | 4 -- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.i= nf | 11 ++-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg= eLib.c | 15 +++-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c= | 69 +++++++++++++++++++- 5 files changed, 86 insertions(+), 17 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 41d9cb9247..e4d4c8e073 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -93,10 +93,6 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 - # PCIE - gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000 - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 - # RTC gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index b1aa0ae4d0..25f3fc8dd8 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -396,10 +396,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 =20 - # PCIE - gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000 - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - !if $(CAPSULE_ENABLE) [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci= SegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib= /PciSegmentLib.inf index f5f1b8409b..d3876791e9 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf @@ -16,18 +16,21 @@ MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D PciSegmentLib + CONSTRUCTOR =3D Armada7k8kPciSegmentLibConstructor =20 [Sources] PciSegmentLib.c =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaBoardDescLib + ArmadaSoCDescLib BaseLib - DebugLib - IoLib =20 -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress +[Protocols] + gMarvellBoardDescProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBr= idgeLib/PciHostBridgeLib.c index 52fa5a4c1a..ad52062d73 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.c @@ -9,6 +9,7 @@ **/ #include =20 +#include #include #include #include @@ -27,7 +28,7 @@ typedef struct { } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; #pragma pack () =20 -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D { +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePathTe= mplate =3D { { { ACPI_DEVICE_PATH, @@ -38,7 +39,7 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeD= evicePath =3D { } }, EISA_PNP_ID (0x0A08), // PCI Express - 0 + 0 // AcpiDevicePath.UID }, =20 { @@ -74,6 +75,7 @@ PciHostBridgeGetRootBridges ( { MV_BOARD_PCIE_DESCRIPTION CONST *BoardPcieDescription; MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *EfiPciRootBridgeDevicePath; MV_PCIE_CONTROLLER CONST *PcieController; PCI_ROOT_BRIDGE *PciRootBridges; PCI_ROOT_BRIDGE *RootBridge; @@ -119,10 +121,15 @@ PciHostBridgeGetRootBridges ( =20 /* Fill information of all root bridge instances */ for (Index =3D 0; Index < *Count; Index++, RootBridge++) { + EfiPciRootBridgeDevicePath =3D AllocateCopyPool ( + sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH= ), + &mEfiPciRootBridgeDevicePathTemplate + ); + EfiPciRootBridgeDevicePath->AcpiDevicePath.UID =3D Index; =20 PcieController =3D &(BoardPcieDescription->PcieControllers[Index]); =20 - RootBridge->Segment =3D 0; + RootBridge->Segment =3D Index; RootBridge->Supports =3D 0; RootBridge->Attributes =3D RootBridge->Supports; =20 @@ -168,7 +175,7 @@ PciHostBridgeGetRootBridges ( =20 RootBridge->NoExtendedConfigSpace =3D FALSE; =20 - RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBri= dgeDevicePath; + RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)EfiPciRootBridg= eDevicePath; } =20 return PciRootBridges; diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci= SegmentLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/P= ciSegmentLib.c index 283190959e..02ceb17825 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.c @@ -9,12 +9,20 @@ =20 **/ =20 +#include #include =20 #include #include #include +#include #include +#include + +#include + +UINT64 *mConfigSpaceAddresses; +UINTN mPcieControllerCount; =20 typedef enum { PciCfgWidthUint8 =3D 0, @@ -34,6 +42,15 @@ typedef enum { #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) =20 +/** + Extract segment number from PCI Segment address + + @param A The address to process. + +**/ +#define SEGMENT_INDEX(A) \ + (((A) & 0x0000ffff00000000) >> 32) + /** Internal worker function to obtain config space base address. =20 @@ -49,7 +66,9 @@ PciSegmentLibGetConfigBase ( IN UINT64 Address ) { - return PcdGet64 (PcdPciExpressBaseAddress); + ASSERT (SEGMENT_INDEX (Address) < mPcieControllerCount); + + return mConfigSpaceAddresses[SEGMENT_INDEX (Address)]; } =20 /** @@ -1388,3 +1407,51 @@ PciSegmentWriteBuffer ( =20 return ReturnValue; } + +/** + Obtain base addresses of PCIe configuration spaces. + + @retval EFI_SUCEESS Routine executed properly. + @retval Other Return error status. + +**/ +EFI_STATUS +EFIAPI +Armada7k8kPciSegmentLibConstructor ( + VOID + ) +{ + CONST MV_BOARD_PCIE_DESCRIPTION *PcieDesc; + MARVELL_BOARD_DESC_PROTOCOL *Proto; + EFI_STATUS Status; + UINTN Index; + + Status =3D gBS->LocateProtocol ( + &gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&Proto + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D Proto->PcieDescriptionGet (Proto, &PcieDesc); + if (EFI_ERROR (Status)) { + return Status; + } + + mConfigSpaceAddresses =3D AllocateZeroPool ( + PcieDesc->PcieControllerCount * sizeof (UINT64) + ); + if (mConfigSpaceAddresses =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < PcieDesc->PcieControllerCount; Index++) { + mConfigSpaceAddresses[Index] =3D PcieDesc->PcieControllers[Index].Conf= igSpaceAddress; + } + + mPcieControllerCount =3D PcieDesc->PcieControllerCount; + + return EFI_SUCCESS; +} --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78487): https://edk2.groups.io/g/devel/message/78487 Mute This Topic: https://groups.io/mt/84605052/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78488+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78488+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880466; cv=none; d=zohomail.com; s=zohoarc; b=C3wJHiSd8Fy+PIpPVnUWhaueqFcP8FEptQMpaWOHTTlkW82PlzFA+gP/usOiQudq6uq1X4CRdnnbAT6JMbBtV12LYZBo2bWTWRmcR3eiy0Az9kENF87GnbqSVbJnZ+MPOvbyFFJxnht0tI9UuNQCN+yjkzyZXhqMgii8S6+WM98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880466; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=apk4+tz5o0eF+cbHlk0Zg8EzPoN2E/ycKjpwV/quztY=; b=dCxWXPpyaRZL4tjPbGfYLym7ZS6xQ4VFO413xOxfqNjBt4RH7/qAjAqrIxuwGAJo69mQ9OLko9Lg8CnGlSrxEgg/HYQf04rLFOYPJoFY67Q6Fz3rUnrlDvabhmY7I9uAUhEK+O3enZTbny1coitffz+dumOgxCnzwGZgHyMzHqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78488+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1627880466387428.85809000114386; Sun, 1 Aug 2021 22:01:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dpPuYY1788612xMw4CptUqXx; Sun, 01 Aug 2021 22:01:06 -0700 X-Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mx.groups.io with SMTP id smtpd.web09.15979.1627880465404505256 for ; Sun, 01 Aug 2021 22:01:05 -0700 X-Received: by mail-lf1-f52.google.com with SMTP id x8so18141580lfe.3 for ; Sun, 01 Aug 2021 22:01:05 -0700 (PDT) X-Gm-Message-State: RzAsjVs2fIyqVzIlN6HElby9x1787277AA= X-Google-Smtp-Source: ABdhPJwjxPLpb28SmD1vO4nggncIHuz/FShklX4o/KpapN+k9wpKslW9MEX7/DCKqjUWT7ythZVh4Q== X-Received: by 2002:ac2:4c1a:: with SMTP id t26mr4601143lfq.328.1627880463657; Sun, 01 Aug 2021 22:01:03 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:03 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 5/6] Marvell: Armada7k8k/OcteonTX: Enable additional board configuration Date: Mon, 2 Aug 2021 07:00:50 +0200 Message-Id: <20210802050051.2831716-6-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880466; bh=yV7dC+PV+JwPz2A96BbiIndXdjovveGoBFrrfLDEPeA=; h=Cc:Date:From:Reply-To:Subject:To; b=aVYLoy7Pp3jRjKFn6+36+ivwdGhdo4iI5vtRGAB6lHtI+uQfbgbC3V9AE7hhJmhRNqH Ivvd5KR2XL82Pq3C4av9lWxy3y5PhH1T2eqeP8f7xmgHpTfW0j0jZZASR/klk3EcFy2rm SLlkPvfq4p5+RDkjR75DGZMTCNpxotsQSJs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880467653100021 Content-Type: text/plain; charset="utf-8" Introduce new board description library extension that allows to execute custom initialization sequence. Add stubs for all existing platforms. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf = | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h = | 9 +++++++++ Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDe= scLib.c | 11 +++++++++++ Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDe= scLib.c | 11 +++++++++++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c = | 11 +++++++++++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c = | 11 +++++++++++ Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0Mc= BinBoardDescLib.c | 11 +++++++++++ Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c = | 2 ++ 8 files changed, 67 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf= b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index b63e9b6325..398baebcf5 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -26,6 +26,7 @@ Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaBoardDescLib ArmadaIcuLib ArmSmcLib ComPhyLib diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 80c55eb3a7..6dc296371d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -11,6 +11,15 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +EFIAPI +ArmadaBoardInit ( + VOID + ); + // // COMPHY controllers per-board description // diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLi= b/Armada70x0DbBoardDescLib.c index b0b6855bbb..33e40d0bd9 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c @@ -16,6 +16,17 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + // // GPIO Expander // diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada8= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLi= b/Armada80x0DbBoardDescLib.c index 2b119fa2a7..e4ee2e04ae 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.c @@ -16,6 +16,17 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + // // GPIO Expanders // diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescL= ib.c index 2755600f53..d53c7086a1 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -16,6 +16,17 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + // // GPIO Expander // diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescL= ib.c index d2846dde30..920c7436c2 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c @@ -16,6 +16,17 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + // // GPIO Expander // diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/= Armada80x0McBinBoardDescLib.c b/Platform/SolidRun/Armada80x0McBin/Armada80x= 0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c index ebe7386df1..b11195c5a1 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.c @@ -15,6 +15,17 @@ #include #include =20 +// +// General purpose routine for per-board initalization +// +EFI_STATUS +ArmadaBoardInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + // // GPIO Expander // diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c b= /Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c index 927abb9400..78ad1c8a7a 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c @@ -110,6 +110,8 @@ ArmadaPlatInitDxeEntryPoint ( UtmiPhyInit (); MppInitialize (); ArmadaIcuInitialize (); + Status =3D ArmadaBoardInit (); + ASSERT_EFI_ERROR (Status); =20 /* * Enable EL3 PMU interrupt handler and --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78488): https://edk2.groups.io/g/devel/message/78488 Mute This Topic: https://groups.io/mt/84605053/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 14:08:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78489+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78489+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1627880468; cv=none; d=zohomail.com; s=zohoarc; b=bPFuNAOzHcv+M0Mq2nd1kbZrcJlXWcqR9pQTRQnFC6JGF7xHrmYa8jNE83fpCoHfWNi1j84PS9hLRvHkgcvI6ZaD8JD5YSdwNYtklYCRGYJv+G4T+nR936VUL9cum2s6//87OyBdE9T6WAYpXCd8JqfjiI1rP7dV82B0kUgfZV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627880468; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fOKPIMXe/7P2Zc3ZnQbv2et4Tg3+FForGa3aiQ8Or/8=; b=UCzPFMtrUZHcwnyKezWxmnv3v11dLiI/BooMpKAtIo73yMxKU2m3k8KMIvup9DV945gNCzolVdNVsPSmS2sJzbOCyXxyBx2xZ0glMFO/wdTwkpKzzxJWxbNKm3/te0FtADopsG/jqkAihen4nHa4pGkM8r7XquBq7x2v3ptVGGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78489+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1627880468467670.8821833019583; Sun, 1 Aug 2021 22:01:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Cw7PYY1788612xwkBxNwywrR; Sun, 01 Aug 2021 22:01:08 -0700 X-Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mx.groups.io with SMTP id smtpd.web08.16087.1627880467107605438 for ; Sun, 01 Aug 2021 22:01:07 -0700 X-Received: by mail-lf1-f54.google.com with SMTP id h2so31505149lfu.4 for ; Sun, 01 Aug 2021 22:01:06 -0700 (PDT) X-Gm-Message-State: zWYo4bvAIaEPG11mfRSxitWIx1787277AA= X-Google-Smtp-Source: ABdhPJy9zpuY30QeNhfYDC4Zk3PA+Rs0bkT3mElmtZPubL1clViJzlRCO2pT6mJ/luX1oL9GOtIf8A== X-Received: by 2002:a05:6512:a8c:: with SMTP id m12mr3868767lfu.526.1627880464689; Sun, 01 Aug 2021 22:01:04 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id g17sm359163lfv.210.2021.08.01.22.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 22:01:04 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 6/6] Marvell: IcuLib: Rework default interrupt map Date: Mon, 2 Aug 2021 07:00:51 +0200 Message-Id: <20210802050051.2831716-7-mw@semihalf.com> In-Reply-To: <20210802050051.2831716-1-mw@semihalf.com> References: <20210802050051.2831716-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1627880468; bh=gETCYTvOR0HoGFnq7c3QTs06eL9EfZ09rdJZ9pGqt5c=; h=Cc:Date:From:Reply-To:Subject:To; b=TlZHBxXWqt728JLdXySEHATUyiZKm2zH5oN843tcWqPdRsx1my8lqJcRMNzFpppqQf3 IPJ1HxkXfywKqeXkgXoKSBQqgJzlYW31QcO7r9cCVV5Weu22i0h1PMcaBLOHuli7Ps86u XpFJM0Q+00Ivoug5mo2DBsDh2SlUkCoI38k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1627880469777100026 Content-Type: text/plain; charset="utf-8" The ICU to GIC interrupt mapping was fixed to support the maximum of two CP11x south bridge units. Rework the default map to use only the interrupts wired to controllers supported in the ACPI tables. Thanks to above all necessary IRQs from the CN913x SoCs (maximum 3 CP11x) can be mapped and passed to the OS. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 48 ++++---- Silicon/Marvell/Library/IcuLib/IcuLib.h | 6 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 61 +++++++---- Silicon/Marvell/Library/IcuLib/IcuLib.c | 115 ++++++------= -------- 4 files changed, 95 insertions(+), 135 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico= n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h index b106790913..a2b7b00b0d 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -11,28 +11,28 @@ =20 **/ =20 -#define CP_GIC_SPI_CP0_PCI0 64 -#define CP_GIC_SPI_CP0_PCI1 65 -#define CP_GIC_SPI_CP0_PCI2 66 -#define CP_GIC_SPI_CP0_SDMMC 67 -#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 -#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 -#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 -#define CP_GIC_SPI_CP0_EIP_RNG0 105 -#define CP_GIC_SPI_CP0_USB_H1 112 -#define CP_GIC_SPI_CP0_USB_H0 113 -#define CP_GIC_SPI_CP0_SATA_H0 114 -#define CP_GIC_SPI_CP0_UART0 121 -#define CP_GIC_SPI_CP0_UART1 122 +#define CP_GIC_SPI_CP0_SDMMC 64 +#define CP_GIC_SPI_PP2_CP0_PORT0 65, 68, 71, 74, 77, 90 +#define CP_GIC_SPI_PP2_CP0_PORT1 66, 69, 72, 75, 78, 89 +#define CP_GIC_SPI_PP2_CP0_PORT2 67, 70, 73, 76, 79, 88 +#define CP_GIC_SPI_CP0_EIP_RNG0 80 +#define CP_GIC_SPI_CP0_USB_H1 81 +#define CP_GIC_SPI_CP0_USB_H0 82 +#define CP_GIC_SPI_CP0_SATA_H0 83 +#define CP_GIC_SPI_CP0_UART0 84 +#define CP_GIC_SPI_CP0_UART1 85 +#define CP_GIC_SPI_CP0_UART2 86 +#define CP_GIC_SPI_CP0_UART3 87 =20 -#define CP_GIC_SPI_CP1_PCI0 288 -#define CP_GIC_SPI_CP1_PCI1 289 -#define CP_GIC_SPI_CP1_PCI2 290 -#define CP_GIC_SPI_CP1_SDMMC 291 -#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 -#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 -#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 -#define CP_GIC_SPI_CP1_EIP_RNG0 329 -#define CP_GIC_SPI_CP1_USB_H1 336 -#define CP_GIC_SPI_CP1_USB_H0 337 -#define CP_GIC_SPI_CP1_SATA_H0 338 +#define CP_GIC_SPI_CP1_SDMMC 96 +#define CP_GIC_SPI_PP2_CP1_PORT0 97, 100, 103, 106, 109, 122 +#define CP_GIC_SPI_PP2_CP1_PORT1 98, 101, 104, 107, 110, 121 +#define CP_GIC_SPI_PP2_CP1_PORT2 99, 102, 105, 108, 111, 120 +#define CP_GIC_SPI_CP1_EIP_RNG0 112 +#define CP_GIC_SPI_CP1_USB_H1 113 +#define CP_GIC_SPI_CP1_USB_H0 114 +#define CP_GIC_SPI_CP1_SATA_H0 115 +#define CP_GIC_SPI_CP1_UART0 116 +#define CP_GIC_SPI_CP1_UART1 117 +#define CP_GIC_SPI_CP1_UART2 118 +#define CP_GIC_SPI_CP1_UART3 119 diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.h index 22027f6bc0..cc1fc5754b 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.h +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h @@ -22,7 +22,7 @@ #include #include =20 -#define ICU_REG_BASE(Cp) (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E00= 00) +#define ICU_REG_BASE(CpIndex) (ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E00= 00) =20 #define ICU_GROUP_REGISTER_BASE_OFFSET 0x10 #define ICU_SET_SPI_AL(x) (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * = x)) @@ -35,7 +35,7 @@ #define ICU_IS_EDGE_OFFSET 28 #define ICU_GROUP_OFFSET 29 =20 -#define ICU_MAX_SUPPORTED_UNITS 2 -#define ICU_MAX_IRQS_PER_CP 64 +#define ICU_MAX_SUPPORTED_UNITS 3 +#define ICU_SPI_OFFSET(CpIndex) ((CpIndex) * 32) =20 #define MAX_ICU_IRQS 207 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h index 83006ebd8a..fea820f9ed 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -11,28 +11,41 @@ =20 **/ =20 -#define CP_GIC_SPI_CP0_PCI0 64 -#define CP_GIC_SPI_CP0_PCI1 65 -#define CP_GIC_SPI_CP0_PCI2 66 -#define CP_GIC_SPI_CP0_SDMMC 67 -#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 -#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 -#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 -#define CP_GIC_SPI_CP0_EIP_RNG0 105 -#define CP_GIC_SPI_CP0_USB_H1 112 -#define CP_GIC_SPI_CP0_USB_H0 113 -#define CP_GIC_SPI_CP0_SATA_H0 114 -#define CP_GIC_SPI_CP0_UART0 121 -#define CP_GIC_SPI_CP0_UART1 122 +#define CP_GIC_SPI_CP0_SDMMC 64 +#define CP_GIC_SPI_PP2_CP0_PORT0 65, 68, 71, 74, 77, 90 +#define CP_GIC_SPI_PP2_CP0_PORT1 66, 69, 72, 75, 78, 89 +#define CP_GIC_SPI_PP2_CP0_PORT2 67, 70, 73, 76, 79, 88 +#define CP_GIC_SPI_CP0_EIP_RNG0 80 +#define CP_GIC_SPI_CP0_USB_H1 81 +#define CP_GIC_SPI_CP0_USB_H0 82 +#define CP_GIC_SPI_CP0_SATA_H0 83 +#define CP_GIC_SPI_CP0_UART0 84 +#define CP_GIC_SPI_CP0_UART1 85 +#define CP_GIC_SPI_CP0_UART2 86 +#define CP_GIC_SPI_CP0_UART3 87 =20 -#define CP_GIC_SPI_CP1_PCI0 288 -#define CP_GIC_SPI_CP1_PCI1 289 -#define CP_GIC_SPI_CP1_PCI2 290 -#define CP_GIC_SPI_CP1_SDMMC 291 -#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 -#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 -#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 -#define CP_GIC_SPI_CP1_EIP_RNG0 329 -#define CP_GIC_SPI_CP1_USB_H1 336 -#define CP_GIC_SPI_CP1_USB_H0 337 -#define CP_GIC_SPI_CP1_SATA_H0 338 +#define CP_GIC_SPI_CP1_SDMMC 96 +#define CP_GIC_SPI_PP2_CP1_PORT0 97, 100, 103, 106, 109, 122 +#define CP_GIC_SPI_PP2_CP1_PORT1 98, 101, 104, 107, 110, 121 +#define CP_GIC_SPI_PP2_CP1_PORT2 99, 102, 105, 108, 111, 120 +#define CP_GIC_SPI_CP1_EIP_RNG0 112 +#define CP_GIC_SPI_CP1_USB_H1 113 +#define CP_GIC_SPI_CP1_USB_H0 114 +#define CP_GIC_SPI_CP1_SATA_H0 115 +#define CP_GIC_SPI_CP1_UART0 116 +#define CP_GIC_SPI_CP1_UART1 117 +#define CP_GIC_SPI_CP1_UART2 118 +#define CP_GIC_SPI_CP1_UART3 119 + +#define CP_GIC_SPI_CP2_SDMMC 288 +#define CP_GIC_SPI_PP2_CP2_PORT0 289, 292, 295, 298, 301, 314 +#define CP_GIC_SPI_PP2_CP2_PORT1 290, 293, 296, 299, 302, 313 +#define CP_GIC_SPI_PP2_CP2_PORT2 291, 294, 297, 300, 303, 312 +#define CP_GIC_SPI_CP2_EIP_RNG0 304 +#define CP_GIC_SPI_CP2_USB_H1 305 +#define CP_GIC_SPI_CP2_USB_H0 306 +#define CP_GIC_SPI_CP2_SATA_H0 307 +#define CP_GIC_SPI_CP2_UART0 308 +#define CP_GIC_SPI_CP2_UART1 309 +#define CP_GIC_SPI_CP2_UART2 310 +#define CP_GIC_SPI_CP2_UART3 311 diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c index 4d9f17445e..e4cb993c7e 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.c +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -16,73 +16,34 @@ STATIC EFI_EVENT mEfiExitBootServicesEvent; =20 STATIC CONST ICU_IRQ IrqMapNonSecure[] =3D { - {22, 0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */ - {23, 1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ - {24, 2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ - {27, 3, IcuIrqTypeLevel}, /* SD/MMC */ - {33, 4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */ - {34, 4, IcuIrqTypeLevel}, /* HB1 AXI monitor */ - {35, 4, IcuIrqTypeLevel}, /* AP AXI monitor */ - {36, 4, IcuIrqTypeLevel}, /* PPv2 AXI monitor */ - {39, 5, IcuIrqTypeLevel}, /* PPv2 Irq */ - {40, 6, IcuIrqTypeLevel}, /* PPv2 Irq */ - {41, 7, IcuIrqTypeLevel}, /* PPv2 Irq */ - {43, 8, IcuIrqTypeLevel}, /* PPv2 Irq */ - {44, 9, IcuIrqTypeLevel}, /* PPv2 Irq */ - {45, 10, IcuIrqTypeLevel}, /* PPv2 Irq */ - {47, 11, IcuIrqTypeLevel}, /* PPv2 Irq */ - {48, 12, IcuIrqTypeLevel}, /* PPv2 Irq */ - {49, 13, IcuIrqTypeLevel}, /* PPv2 Irq */ - {51, 14, IcuIrqTypeLevel}, /* PPv2 Irq */ - {52, 15, IcuIrqTypeLevel}, /* PPv2 Irq */ - {53, 16, IcuIrqTypeLevel}, /* PPv2 Irq */ - {55, 17, IcuIrqTypeLevel}, /* PPv2 Irq */ - {56, 18, IcuIrqTypeLevel}, /* PPv2 Irq */ - {57, 19, IcuIrqTypeLevel}, /* PPv2 Irq */ - {59, 20, IcuIrqTypeLevel}, /* PPv2 Irq */ - {60, 21, IcuIrqTypeLevel}, /* PPv2 Irq */ - {61, 22, IcuIrqTypeLevel}, /* PPv2 Irq */ - {63, 23, IcuIrqTypeLevel}, /* PPv2 Irq */ - {64, 24, IcuIrqTypeLevel}, /* PPv2 Irq */ - {65, 25, IcuIrqTypeLevel}, /* PPv2 Irq */ - {67, 26, IcuIrqTypeLevel}, /* PPv2 Irq */ - {68, 27, IcuIrqTypeLevel}, /* PPv2 Irq */ - {69, 28, IcuIrqTypeLevel}, /* PPv2 Irq */ - {71, 29, IcuIrqTypeLevel}, /* PPv2 Irq */ - {72, 30, IcuIrqTypeLevel}, /* PPv2 Irq */ - {73, 31, IcuIrqTypeLevel}, /* PPv2 Irq */ - {78, 32, IcuIrqTypeLevel}, /* MG Irq */ - {79, 33, IcuIrqTypeLevel}, /* GPIO 56-63 */ - {80, 34, IcuIrqTypeLevel}, /* GPIO 48-55 */ - {81, 35, IcuIrqTypeLevel}, /* GPIO 40-47 */ - {82, 36, IcuIrqTypeLevel}, /* GPIO 32-39 */ - {83, 37, IcuIrqTypeLevel}, /* GPIO 24-31 */ - {84, 38, IcuIrqTypeLevel}, /* GPIO 16-23 */ - {85, 39, IcuIrqTypeLevel}, /* GPIO 8-15 */ - {86, 40, IcuIrqTypeLevel}, /* GPIO 0-7 */ - {88, 41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */ - {89, 42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */ - {90, 43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */ - {91, 44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */ - {92, 45, IcuIrqTypeLevel}, /* EIP-197 int */ - {95, 46, IcuIrqTypeLevel}, /* EIP-150 Irq */ - {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */ - {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */ - {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */ - {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */ - {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */ - {115, 52, IcuIrqTypeLevel}, /* NAND Irq */ - {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */ - {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */ - {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */ - {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */ - {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */ - {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */ - {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */ - {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */ - {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */ - {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */ - {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */ + {27, 0, IcuIrqTypeLevel}, /* SD/MMC */ + {39, 1, IcuIrqTypeLevel}, /* PPv2 Irq */ + {40, 2, IcuIrqTypeLevel}, /* PPv2 Irq */ + {41, 3, IcuIrqTypeLevel}, /* PPv2 Irq */ + {43, 4, IcuIrqTypeLevel}, /* PPv2 Irq */ + {44, 5, IcuIrqTypeLevel}, /* PPv2 Irq */ + {45, 6, IcuIrqTypeLevel}, /* PPv2 Irq */ + {47, 7, IcuIrqTypeLevel}, /* PPv2 Irq */ + {48, 8, IcuIrqTypeLevel}, /* PPv2 Irq */ + {49, 9, IcuIrqTypeLevel}, /* PPv2 Irq */ + {51, 10, IcuIrqTypeLevel}, /* PPv2 Irq */ + {52, 11, IcuIrqTypeLevel}, /* PPv2 Irq */ + {53, 12, IcuIrqTypeLevel}, /* PPv2 Irq */ + {55, 13, IcuIrqTypeLevel}, /* PPv2 Irq */ + {56, 14, IcuIrqTypeLevel}, /* PPv2 Irq */ + {57, 15, IcuIrqTypeLevel}, /* PPv2 Irq */ + {88, 16, IcuIrqTypeLevel}, /* EIP-197 ring-0 */ + {105, 17, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */ + {106, 18, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */ + {107, 19, IcuIrqTypeLevel}, /* SATA Host-1 Irq */ + {109, 19, IcuIrqTypeLevel}, /* SATA Host-0 Irq */ + {122, 20, IcuIrqTypeLevel}, /* UART 0 Irq */ + {123, 21, IcuIrqTypeLevel}, /* UART 1 Irq */ + {124, 22, IcuIrqTypeLevel}, /* UART 2 Irq */ + {125, 23, IcuIrqTypeLevel}, /* UART 3 Irq */ + {127, 24, IcuIrqTypeLevel}, /* GOP-3 Irq */ + {128, 25, IcuIrqTypeLevel}, /* GOP-2 Irq */ + {129, 26, IcuIrqTypeLevel}, /* GOP-0 Irq */ }; =20 /* @@ -177,7 +138,7 @@ IcuConfigure ( /* Get the base of the GIC SPI ID in the MSI message */ SpiBase =3D IcuDesc->IcuSpiBase; /* Get multiple CP110 instances SPI ID shift */ - SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + SpiOffset =3D ICU_SPI_OFFSET (CpIndex); /* Get MSI addresses per interrupt group */ Msi =3D IcuDesc->IcuMsi; =20 @@ -230,7 +191,7 @@ IcuClearGicSpi ( /* Get the base of the GIC SPI ID in the MSI message */ SpiBase =3D IcuDesc->IcuSpiBase; /* Get multiple CP110 instances SPI ID shift */ - SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + SpiOffset =3D ICU_SPI_OFFSET (CpIndex); /* Get MSI addresses per interrupt group */ Msi =3D IcuDesc->IcuMsi; =20 @@ -254,10 +215,6 @@ IcuCleanUp ( IcuDesc =3D Context; =20 CpCount =3D FixedPcdGet8 (PcdMaxCpCount); - if (CpCount > ICU_MAX_SUPPORTED_UNITS) { - CpCount =3D ICU_MAX_SUPPORTED_UNITS; - } - for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { IcuClearGicSpi (CpIndex, IcuDesc); } @@ -272,18 +229,8 @@ ArmadaIcuInitialize ( UINTN CpCount, CpIndex; EFI_STATUS Status; =20 - /* - * Due to limited amount of interrupt lanes, only 2 units can be - * wired to the GIC. - */ CpCount =3D FixedPcdGet8 (PcdMaxCpCount); - if (CpCount > ICU_MAX_SUPPORTED_UNITS) { - DEBUG ((DEBUG_ERROR, - "%a: Default ICU to GIC mapping is available for maximum %d CP110 un= its", - __FUNCTION__, - ICU_MAX_SUPPORTED_UNITS)); - CpCount =3D ICU_MAX_SUPPORTED_UNITS; - } + ASSERT (CpCount <=3D ICU_MAX_SUPPORTED_UNITS); =20 /* Obtain SoC description of the ICU */ Status =3D ArmadaSoCDescIcuGet (&IcuDesc); --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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