From nobody Mon Feb 9 22:03:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77883+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77883+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687065; cv=none; d=zohomail.com; s=zohoarc; b=VGzd+X3OyZ7NVGxulE+MYy6gSGPRSu9VnMgFyKMMd6j1UeHNJjuItEFdh+V22rK51gJ3HwIVWzPOSRxA/rNVwurYc/FrAKQ0a11lTnwuYW1qI3U8x3pF3pLz2FSWQU78lKTfLlamNK7Aqn917A67GkK3YtgEJB5m8x47O8nY+88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687065; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mZRxZxCTXzT7ldyfn3hrOyzSt2+k6FicJzdszu23ZVc=; b=TiG0ou7hG38Xf5I2ojmw05xdEtIxx94ndaZoLk7GoEB3ehW8QQQRvsYpeeuXvxH+AeVKMM7+7kYPy5Udeun7oQPcfKPLMKgqExGn3WDVBItxpWAwlNAAPbtEqHMPOi/UE/K3bfHdzNhLq89fdjXupzKST/nd9oKiIiRLnuHVjz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77883+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687065081496.0998267665627; Mon, 19 Jul 2021 02:31:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id W1tPYY1788612xTyOIH227GG; Mon, 19 Jul 2021 02:31:04 -0700 X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web11.25521.1626687063875090442 for ; Mon, 19 Jul 2021 02:31:04 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id u14so25407175ljh.0 for ; Mon, 19 Jul 2021 02:31:03 -0700 (PDT) X-Gm-Message-State: TQpnZLmdEvKian406Lf1dKnax1787277AA= X-Google-Smtp-Source: ABdhPJybaW/VKWJMMFrM6QQxW6gzv3qF2anbfKjajCAARR4YSv8ZvpIvCUaX//Twp7zXpMISDjmL5Q== X-Received: by 2002:a05:651c:12c4:: with SMTP id 4mr9689512lje.320.1626687062190; Mon, 19 Jul 2021 02:31:02 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table Date: Mon, 19 Jul 2021 11:30:12 +0200 Message-Id: <20210719093015.1490932-5-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687064; bh=dgkC7n2lyJDCTbM/hjW7fv5omt/MRpKN8VjvxU/LSu0=; h=Cc:Date:From:Reply-To:Subject:To; b=chsIG9I17iSaMC5d2RBn9L2lKD1d3ZACUfBf4X7UbXxroVusg+EtDjQlyIpxG9C55QE MsLQ9n+8qZ+1C8+D11MdZRmiexju286BYTY3VfaSjHtLW8UyU4j+6cHfYzx0wQfbmXehH 8xhrioEHnuPSStsWYJ2I1QSf7rAEU883Ft0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687066682100014 Content-Type: text/plain; charset="utf-8" The DBG2 table is mandatory as per SBBR v1.2 specification. Expose it via J25 jumper on the Armada 8040 MacchiatoBin platform. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 +++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 +++++= +++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 33 +++++= ++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 - 7 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D= bg2.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D= bg2.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 7cf9ecfbfd..98e5cc8b6e 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -18,6 +18,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] + Armada80x0McBin/Dbg2.aslc Armada80x0McBin/Dsdt.asl Armada80x0McBin/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/M= arvell/Armada7k8k/AcpiTables/AcpiHeader.h index 90ab607845..9d83ba7837 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h @@ -11,6 +11,8 @@ =20 #include =20 +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} #define ACPI_OEM_REVISION 0 #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h new file mode 100644 index 0000000000..b8ac770ed5 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define ARMADA80X0_MCBIN_DBG2_UART_REG_BASE 0xF2702100 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico= n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h index dd33cb5e7b..b106790913 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112 #define CP_GIC_SPI_CP0_USB_H0 113 #define CP_GIC_SPI_CP0_SATA_H0 114 +#define CP_GIC_SPI_CP0_UART0 121 +#define CP_GIC_SPI_CP0_UART1 122 =20 #define CP_GIC_SPI_CP1_PCI0 288 #define CP_GIC_SPI_CP1_PCI1 289 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.asl= c b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc new file mode 100644 index 0000000000..1e6d99ee9e --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include + +#include "AcpiHeader.h" +#include "Armada80x0McBin/Dbg2.h" + +#pragma pack(1) + +#define ARMADA7K8K_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2'= , 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 =3D { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegist= ers */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB= GP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (ARMADA80X0_MCBIN_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + ARMADA7K8K_UART_STR, /* NameSpaceStrin= g */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Dbg2; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 1ecbd0309c..a7d1c76e07 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -8,6 +8,7 @@ =20 **/ =20 +#include "Armada80x0McBin/Dbg2.h" #include "Armada80x0McBin/Pcie.h" #include "IcuInterrupts.h" =20 @@ -246,6 +247,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x00) // _UID: U= nique ID Method (_STA) // _STA: D= evice status { Return (0xF) @@ -272,6 +274,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) }) } =20 + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } + Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + ARMADA80X0_MCBIN_DBG2_UART_REG_BASE, // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_UART1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (SMI0) { Name (_HID, "MRVL0100") // _HID: H= ardware ID diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Spcr.aslc index 6efc175bdf..48e6699f52 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -15,8 +15,6 @@ =20 #include "AcpiHeader.h" =20 -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77883): https://edk2.groups.io/g/devel/message/77883 Mute This Topic: https://groups.io/mt/84304357/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-