From nobody Mon Feb 9 15:45:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77881+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77881+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687063; cv=none; d=zohomail.com; s=zohoarc; b=hAnG/j3hOy5DGJ+n7QTb7oH5eanzd9TTgw70laf0B0qxolI39ek3U1nIqagYOJfkke35NKU1mqExyja235uXV9D/xmuIrzYlULdqI9qWsjbjuCCufg5yICEadXcHOYJyoQfcW56XCGLVQgnDngpDMDcyIqbTBjTITNoVYqIGqA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687063; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7bU9qBBssjb/si/Aq1qD971r7LIcEjm9uqePWP9pOYA=; b=Ns0F8+gIgrfgtgbnen5X+Gmf6rBY23kzn3QybW8Vn7N4cqeALoFaFNc1S409liOagEZOLl1+a+OFl2ehXJEjV8Vc+0zr3faWr+DozzdFj1IFhHB4nItGnPA2vxekuynxaPq7/RG649TLM2QtC3FYgLuLPugh3B1OUie4GARbZeM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77881+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687063361864.028524878328; Mon, 19 Jul 2021 02:31:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JI6PYY1788612xTDm51L3l2D; Mon, 19 Jul 2021 02:31:02 -0700 X-Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) by mx.groups.io with SMTP id smtpd.web08.25751.1626687061896248585 for ; Mon, 19 Jul 2021 02:31:02 -0700 X-Received: by mail-lf1-f50.google.com with SMTP id f30so22548151lfv.10 for ; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) X-Gm-Message-State: aKX26RdxoP1g5RmgnywTQjZGx1787277AA= X-Google-Smtp-Source: ABdhPJw9ZkA4njQAOUwRtl4zfmZ5fdAWMO4nCsqsmq/CruVzH/JpHz3B0kNrA47JczTQBxB+Sx7JkA== X-Received: by 2002:ac2:562e:: with SMTP id b14mr17542937lff.620.1626687060083; Mon, 19 Jul 2021 02:31:00 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:30:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Date: Mon, 19 Jul 2021 11:30:10 +0200 Message-Id: <20210719093015.1490932-3-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687062; bh=79MfK9KkL89iDi6wziEhKEt5tadvQW8wN6UBIUAK7nI=; h=Cc:Date:From:Reply-To:Subject:To; b=jTpPNKN4t+8c4l9/WlOxTXFvodnolSBaw0yWmVBEo5qTS+sZlSSttNblMtFILtoeoCl vxuSYPOgb1S0zWyjrZNyBrJB2YvhwnbLIKPwkFCfucfFkgS8v2EnDPJwYVNmvjE5dmzdQ gGp0pJyYS2iIoTHPqyXZcBwinp5spRE7cFU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687064700100008 Content-Type: text/plain; charset="utf-8" BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 ++++++= +++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 ++++++= +++++++++ 5 files changed, 272 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index d26945d933..1ecbd0309c 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0101") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index d76a2a902b..536df8ab4b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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