From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77880+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77880+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687061; cv=none; d=zohomail.com; s=zohoarc; b=aj+nXQUGEK0/JGNlEfMLKP9q2hMjpjmEr9V7gvz+nNnMsK0dZMrl4fg/tEsJhwuW2P2oZE9n0L7+LibDEq62YEI9Z9MhGNAWK082wmbeDL8krk1DEiokBvmxAUdV1SIIbQ/+/sPNRoV5frtgOXl1Gvcwonwy+X60M9zK62Nc1VY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687061; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uTRRM0FvWl3/RhidlnJLnrRzhpxkiXjH4cAj5I9H+1k=; b=SotPXtVPaB2HoMavlnjdQpdRhxBlUBClcoCtZqSg876jE4bCYOjJHpGcal8xQqEO0a/aLTFEcwhRLWqQ4TpksramHYCLZ4nxkO9kmOwUdgZtTMvXDE9y3WacvrEeJ4axN5I9WNuxcULQitpgbukt3yipPwBJqJKm8kfrFWYw4rw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77880+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687061906236.19319346975487; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8wVaYY1788612xP1UAL6oZy9; Mon, 19 Jul 2021 02:31:01 -0700 X-Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mx.groups.io with SMTP id smtpd.web12.25682.1626687060840747761 for ; Mon, 19 Jul 2021 02:31:01 -0700 X-Received: by mail-lf1-f52.google.com with SMTP id a12so29101208lfb.7 for ; Mon, 19 Jul 2021 02:31:00 -0700 (PDT) X-Gm-Message-State: PtFn5Te0FwDk8SlpyVyGCXSqx1787277AA= X-Google-Smtp-Source: ABdhPJw8NtYNDlhRWt9vjUPaaBdWAcNbezWSHjmob9WImk9aizKfTia4Jg95PdFUIOaTTwU3nM2eBQ== X-Received: by 2002:a19:670f:: with SMTP id b15mr18271812lfc.128.1626687058905; Mon, 19 Jul 2021 02:30:58 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:30:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Date: Mon, 19 Jul 2021 11:30:09 +0200 Message-Id: <20210719093015.1490932-2-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687061; bh=Wp7uZlOD7QCIZqeJzO46sPM8aU3RBQncPQJtXbxQSN4=; h=Cc:Date:From:Reply-To:Subject:To; b=sFpl339nFatGRIQP+I10VEf4AY0TyfpB6eniziO6uuDOICDWzI9kOAmCDKxAQzfGEQw T6bqsv19kqmX0rBMm7xVRmsXX4sji/b8+24JmL3oAeW31hX0DRwdw/CcQwelgWsQZovqQ v0WhjTKn9UQQssRcGMSchByP1vJ9G4gor8Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687062279100001 Content-Type: text/plain; charset="utf-8" From: Grzegorz Bernacki The latest changes in MdeModulePkg/Universal/BdsDxe require VariablePolicyHelperLib resolution. Fix that for all platforms based on the Marvell SoCs. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 939fbf14d9..c919d4bfab 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -175,6 +175,7 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf =20 [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf @@ -197,6 +198,7 @@ !endif DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf =20 [LibraryClasses.ARM, LibraryClasses.AARCH64] # @@ -563,7 +565,6 @@ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeas= urementLibNull.inf VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib= /VariablePolicyHelperLib.inf } =20 # UEFI application (Shell Embedded Boot Loader) --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77880): https://edk2.groups.io/g/devel/message/77880 Mute This Topic: https://groups.io/mt/84304354/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77881+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77881+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687063; cv=none; d=zohomail.com; s=zohoarc; b=hAnG/j3hOy5DGJ+n7QTb7oH5eanzd9TTgw70laf0B0qxolI39ek3U1nIqagYOJfkke35NKU1mqExyja235uXV9D/xmuIrzYlULdqI9qWsjbjuCCufg5yICEadXcHOYJyoQfcW56XCGLVQgnDngpDMDcyIqbTBjTITNoVYqIGqA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687063; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7bU9qBBssjb/si/Aq1qD971r7LIcEjm9uqePWP9pOYA=; b=Ns0F8+gIgrfgtgbnen5X+Gmf6rBY23kzn3QybW8Vn7N4cqeALoFaFNc1S409liOagEZOLl1+a+OFl2ehXJEjV8Vc+0zr3faWr+DozzdFj1IFhHB4nItGnPA2vxekuynxaPq7/RG649TLM2QtC3FYgLuLPugh3B1OUie4GARbZeM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77881+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687063361864.028524878328; Mon, 19 Jul 2021 02:31:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JI6PYY1788612xTDm51L3l2D; Mon, 19 Jul 2021 02:31:02 -0700 X-Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) by mx.groups.io with SMTP id smtpd.web08.25751.1626687061896248585 for ; Mon, 19 Jul 2021 02:31:02 -0700 X-Received: by mail-lf1-f50.google.com with SMTP id f30so22548151lfv.10 for ; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) X-Gm-Message-State: aKX26RdxoP1g5RmgnywTQjZGx1787277AA= X-Google-Smtp-Source: ABdhPJw9ZkA4njQAOUwRtl4zfmZ5fdAWMO4nCsqsmq/CruVzH/JpHz3B0kNrA47JczTQBxB+Sx7JkA== X-Received: by 2002:ac2:562e:: with SMTP id b14mr17542937lff.620.1626687060083; Mon, 19 Jul 2021 02:31:00 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:30:59 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Date: Mon, 19 Jul 2021 11:30:10 +0200 Message-Id: <20210719093015.1490932-3-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687062; bh=79MfK9KkL89iDi6wziEhKEt5tadvQW8wN6UBIUAK7nI=; h=Cc:Date:From:Reply-To:Subject:To; b=jTpPNKN4t+8c4l9/WlOxTXFvodnolSBaw0yWmVBEo5qTS+sZlSSttNblMtFILtoeoCl vxuSYPOgb1S0zWyjrZNyBrJB2YvhwnbLIKPwkFCfucfFkgS8v2EnDPJwYVNmvjE5dmzdQ gGp0pJyYS2iIoTHPqyXZcBwinp5spRE7cFU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687064700100008 Content-Type: text/plain; charset="utf-8" BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 ++++++= +++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 ++++++= +++++++++ 5 files changed, 272 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index d26945d933..1ecbd0309c 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "MRVL0101") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x01) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF4760000, 0x7D) @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000) diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index d76a2a902b..536df8ab4b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x000) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU1) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x001) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU2) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x100) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } Device (CPU3) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, 0x101) // _UID: Unique ID + Method (_STA) // _STA: Device status + { + Return (0xF) + } } =20 Device (AHC0) @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_CLS, Package (0x03) // _CLS: Class Code { 0x01, @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x00) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } =20 Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings { @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings { @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "MRVL0100") // _HID: H= ardware ID Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID Name (_CCA, 0x01) // Cache-c= oherent controller Name (_UID, 0x00) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000) @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) { Name (_HID, "PRP0001") // _HID= : Hardware ID Name (_UID, 0x00) // _UID= : Unique ID + Method (_STA) // _STA= : Device status + { + Return (0xF) + } Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF2760000, 0x7D) @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Method (_STA) // _STA: Device status + { + Return (0xF) + } Name (_PRT, Package () // _PRT: PCI Routing Table { Package () { 0xFFFF, 0x0, 0x0, 0x40 }, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77881): https://edk2.groups.io/g/devel/message/77881 Mute This Topic: https://groups.io/mt/84304355/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77882+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77882+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687064; cv=none; d=zohomail.com; s=zohoarc; b=l/BN9tACmJzot1TA2JN37Z7F01JIPaCvhCBSAu9jjNqjCc5cd99fAJGzq5DhBA7IELhpq3fbJ2BIPmzDA5CFy34FZGc+fqQi5Km0fvhWThfU4BEE5Ulxnao7T8zZqYL85CRuHdyx+e2ZsWtpWpZjG09kR3JAruBufWdRZtVPIrc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687064; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pwMFCB+M6fqNQVt+eTwyrEvFoc6BO+u30YPU+ras58Q=; b=oBcciym40GJUU5Uwc7V7LB/2owDkemxAY4svDzm67jgekgX3mNa9pWsMS0eyYLlpHoFHhl8N0DZkadooDd4Mygx9xh8uztw7++MMOXFJ1Aj9gtUPtRSLr8d/2vbujoxufl5L/LxurV+jLwTU1R55pTLyHGqm1CPvbhCyWayn/3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77882+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16266870644081012.3556497043063; Mon, 19 Jul 2021 02:31:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OlCWYY1788612x1WOzAvDLPD; Mon, 19 Jul 2021 02:31:03 -0700 X-Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mx.groups.io with SMTP id smtpd.web08.25752.1626687063028851700 for ; Mon, 19 Jul 2021 02:31:03 -0700 X-Received: by mail-lf1-f51.google.com with SMTP id i5so29131165lfe.2 for ; Mon, 19 Jul 2021 02:31:02 -0700 (PDT) X-Gm-Message-State: c6I18VUIg6I0UflgRgKeg9xZx1787277AA= X-Google-Smtp-Source: ABdhPJwe4BhymFX+FzlQlOptBxgcDAnZYQUPcWhYu37TkaJuptWdRgiBz5ZvpxCvdBmM21BIJywx/Q== X-Received: by 2002:ac2:558f:: with SMTP id v15mr10130940lfg.326.1626687061216; Mon, 19 Jul 2021 02:31:01 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:00 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table Date: Mon, 19 Jul 2021 11:30:11 +0200 Message-Id: <20210719093015.1490932-4-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687063; bh=Eg5cfjm81MEKWcE8JV/XM8tgxkp0jIT/Bf3gPLEnPvI=; h=Cc:Date:From:Reply-To:Subject:To; b=NUdHwUkFgJMf3D6u9jfnVVpUbY7QMSfmTHRtjIe19mnum7XMwLJJuvY99f+xaYw0dKB Qb8uIJG2pI66Ib9u+yY80H2qYhpQDTwc3FzmmukkkJfJpzueyX7tgOsF+qtTwSbrlmu+y zEWwJp0THzPaGbX901/bIym1RDqjpfZJ91w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687066555100011 Content-Type: text/plain; charset="utf-8" The DBG2 table is mandatory as per SBBR v1.2 specification. Introduce it via CP0_UART0 interface. Note: in order to use it, DPR58 and DPR59 must be switched to positions 2-3. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +- Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 +++++++++= +++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 33 +++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 - 9 files changed, 124 insertions(+), 4 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.= aslc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index 33fb7ccc08..756d875f6c 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -32,8 +32,8 @@ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0x9 } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0xA } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf index 191a747585..2cd13aa2b6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -18,6 +18,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] + Cn913xDbA/Dbg2.aslc Cn913xDbA/Dsdt.asl Cn913xDbA/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf index bbf1b5133a..0c9fb82682 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -19,6 +19,7 @@ =20 [Sources] Cn9131DbA/Ssdt.asl + Cn913xDbA/Dbg2.aslc Cn913xDbA/Dsdt.asl Cn913xDbA/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon= /Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h index 283867692e..b93799dd03 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h @@ -11,6 +11,8 @@ =20 #include =20 +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} #define ACPI_OEM_REVISION 0 #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h b/Sil= icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h new file mode 100644 index 0000000000..4584967016 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define CN913X_DBG2_UART_REG_BASE 0xF2702000 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili= con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h index 6befe2ae54..83006ebd8a 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112 #define CP_GIC_SPI_CP0_USB_H0 113 #define CP_GIC_SPI_CP0_SATA_H0 114 +#define CP_GIC_SPI_CP0_UART0 121 +#define CP_GIC_SPI_CP0_UART1 122 =20 #define CP_GIC_SPI_CP1_PCI0 288 #define CP_GIC_SPI_CP1_PCI1 289 diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc b/= Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc new file mode 100644 index 0000000000..bea55d0114 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include + +#include "AcpiHeader.h" +#include "Cn913xDbA/Dbg2.h" + +#pragma pack(1) + +#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x= 00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 =3D { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegist= ers */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB= GP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + CN913X_UART_STR, /* NameSpaceStrin= g */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Dbg2; diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index 536df8ab4b..7335e443c6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -9,6 +9,7 @@ =20 **/ =20 +#include "Cn913xDbA/Dbg2.h" #include "Cn913xDbA/Pcie.h" #include "IcuInterrupts.h" =20 @@ -199,6 +200,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x00) // _UID: U= nique ID Method (_STA) // _STA: D= evice status { Return (0xF) @@ -225,6 +227,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) }) } =20 + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } + Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + CN913X_DBG2_UART_REG_BASE, // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_UART0 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (SMI0) { Name (_HID, "MRVL0100") // _HID: H= ardware ID diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma= rvell/OcteonTx/AcpiTables/T91/Spcr.aslc index 2a3415f0a6..2dda2def81 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc @@ -15,8 +15,6 @@ =20 #include "AcpiHeader.h" =20 -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77882): https://edk2.groups.io/g/devel/message/77882 Mute This Topic: https://groups.io/mt/84304356/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77883+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77883+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687065; cv=none; d=zohomail.com; s=zohoarc; b=VGzd+X3OyZ7NVGxulE+MYy6gSGPRSu9VnMgFyKMMd6j1UeHNJjuItEFdh+V22rK51gJ3HwIVWzPOSRxA/rNVwurYc/FrAKQ0a11lTnwuYW1qI3U8x3pF3pLz2FSWQU78lKTfLlamNK7Aqn917A67GkK3YtgEJB5m8x47O8nY+88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687065; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mZRxZxCTXzT7ldyfn3hrOyzSt2+k6FicJzdszu23ZVc=; b=TiG0ou7hG38Xf5I2ojmw05xdEtIxx94ndaZoLk7GoEB3ehW8QQQRvsYpeeuXvxH+AeVKMM7+7kYPy5Udeun7oQPcfKPLMKgqExGn3WDVBItxpWAwlNAAPbtEqHMPOi/UE/K3bfHdzNhLq89fdjXupzKST/nd9oKiIiRLnuHVjz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77883+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687065081496.0998267665627; Mon, 19 Jul 2021 02:31:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id W1tPYY1788612xTyOIH227GG; Mon, 19 Jul 2021 02:31:04 -0700 X-Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web11.25521.1626687063875090442 for ; Mon, 19 Jul 2021 02:31:04 -0700 X-Received: by mail-lj1-f181.google.com with SMTP id u14so25407175ljh.0 for ; Mon, 19 Jul 2021 02:31:03 -0700 (PDT) X-Gm-Message-State: TQpnZLmdEvKian406Lf1dKnax1787277AA= X-Google-Smtp-Source: ABdhPJybaW/VKWJMMFrM6QQxW6gzv3qF2anbfKjajCAARR4YSv8ZvpIvCUaX//Twp7zXpMISDjmL5Q== X-Received: by 2002:a05:651c:12c4:: with SMTP id 4mr9689512lje.320.1626687062190; Mon, 19 Jul 2021 02:31:02 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:01 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table Date: Mon, 19 Jul 2021 11:30:12 +0200 Message-Id: <20210719093015.1490932-5-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687064; bh=dgkC7n2lyJDCTbM/hjW7fv5omt/MRpKN8VjvxU/LSu0=; h=Cc:Date:From:Reply-To:Subject:To; b=chsIG9I17iSaMC5d2RBn9L2lKD1d3ZACUfBf4X7UbXxroVusg+EtDjQlyIpxG9C55QE MsLQ9n+8qZ+1C8+D11MdZRmiexju286BYTY3VfaSjHtLW8UyU4j+6cHfYzx0wQfbmXehH 8xhrioEHnuPSStsWYJ2I1QSf7rAEU883Ft0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687066682100014 Content-Type: text/plain; charset="utf-8" The DBG2 table is mandatory as per SBBR v1.2 specification. Expose it via J25 jumper on the Armada 8040 MacchiatoBin platform. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 +++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 +++++= +++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 33 +++++= ++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 - 7 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D= bg2.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D= bg2.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 7cf9ecfbfd..98e5cc8b6e 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -18,6 +18,7 @@ VERSION_STRING =3D 1.0 =20 [Sources] + Armada80x0McBin/Dbg2.aslc Armada80x0McBin/Dsdt.asl Armada80x0McBin/Mcfg.aslc Fadt.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/M= arvell/Armada7k8k/AcpiTables/AcpiHeader.h index 90ab607845..9d83ba7837 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h @@ -11,6 +11,8 @@ =20 #include =20 +#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } + #define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} #define ACPI_OEM_REVISION 0 #define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h b= /Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h new file mode 100644 index 0000000000..b8ac770ed5 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h @@ -0,0 +1,9 @@ +/** + + Copyright (C) 2021, Semihalf. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#define ARMADA80X0_MCBIN_DBG2_UART_REG_BASE 0xF2702100 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico= n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h index dd33cb5e7b..b106790913 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -22,6 +22,8 @@ #define CP_GIC_SPI_CP0_USB_H1 112 #define CP_GIC_SPI_CP0_USB_H0 113 #define CP_GIC_SPI_CP0_SATA_H0 114 +#define CP_GIC_SPI_CP0_UART0 121 +#define CP_GIC_SPI_CP0_UART1 122 =20 #define CP_GIC_SPI_CP1_PCI0 288 #define CP_GIC_SPI_CP1_PCI1 289 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.asl= c b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc new file mode 100644 index 0000000000..1e6d99ee9e --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc @@ -0,0 +1,74 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* Copyright (c) 2021 ARM Ltd. All rights reserved. +* Copyright (c) 2021 Semihalf. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include + +#include "AcpiHeader.h" +#include "Armada80x0McBin/Dbg2.h" + +#pragma pack(1) + +#define ARMADA7K8K_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2'= , 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 =3D { + { + __ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegist= ers */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB= GP_SPEC, + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + MV_UART_AS32 (ARMADA80X0_MCBIN_DBG2_UART_REG_BASE), /* BaseAddress */ + SIZE_4KB, /* AddressSize */ + ARMADA7K8K_UART_STR, /* NameSpaceStrin= g */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable =3D &Dbg2; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 1ecbd0309c..a7d1c76e07 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -8,6 +8,7 @@ =20 **/ =20 +#include "Armada80x0McBin/Dbg2.h" #include "Armada80x0McBin/Pcie.h" #include "IcuInterrupts.h" =20 @@ -246,6 +247,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) { Name (_HID, "MRVL0001") // _HID: H= ardware ID Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x00) // _UID: U= nique ID Method (_STA) // _STA: D= evice status { Return (0xF) @@ -272,6 +274,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) }) } =20 + Device (COM2) + { + Name (_HID, "MRVL0001") // _HID: H= ardware ID + Name (_CID, "HISI0031") // _CID: C= ompatible ID + Name (_UID, 0x01) // _UID: U= nique ID + Method (_STA) // _STA: D= evice status + { + Return (0xF) + } + Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: A= ddress + Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings + { + Memory32Fixed (ReadWrite, + ARMADA80X0_MCBIN_DBG2_UART_REG_BASE, // Address= Base + 0x00000100, // Address= Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, ) + { + CP_GIC_SPI_CP0_UART1 + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", FixedPcdGet32 (PcdSe= rialClockRate) }, + Package () { "reg-io-width", 1 }, + Package () { "reg-shift", 2 }, + } + }) + } + Device (SMI0) { Name (_HID, "MRVL0100") // _HID: H= ardware ID diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Spcr.aslc index 6efc175bdf..48e6699f52 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -15,8 +15,6 @@ =20 #include "AcpiHeader.h" =20 -#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP= I_5_0_BYTE, Address } - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77883): https://edk2.groups.io/g/devel/message/77883 Mute This Topic: https://groups.io/mt/84304357/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77884+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77884+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687066; cv=none; d=zohomail.com; s=zohoarc; b=BJB3t+YYk2HaKVJEQvKCK441VlXkMcIYdLSY0S9B1NxfWRV5FbL0yuuX62aFkEaUVNIsAw9vgx6NSuC326LK1kNHtxpjVCD3A3SgiyNt/hTfD+sILfe1rLWuw6sBHOf/0yOsU7a3OY6LHTjZqUbicaBi8bXIOZFWGErviKjv9xQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687066; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=utjQuTszm3L1+B4nKS8jsdJ6azw0+1glj7hhIrB2/q4=; b=oAjyqLrmKHcgGJMaRWNp81YdOqQeSZ+XeJGoq06uVQVQv9h73FUmZSgvqZPnBPlI/FmjnrxuG/lMksTqFR74ocWvRCJUBlYIH4OcHMX5Wq0sLI9JeHJUscJzlwsTdSz7/vc30EDCfjb72zYBFV4ur3Tg+aYiP0lg9hkM6X1jRKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77884+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687066173967.1771202710571; Mon, 19 Jul 2021 02:31:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4JuZYY1788612xHw1lCQoK1X; Mon, 19 Jul 2021 02:31:05 -0700 X-Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web11.25522.1626687064875277958 for ; Mon, 19 Jul 2021 02:31:05 -0700 X-Received: by mail-lf1-f41.google.com with SMTP id i5so29131300lfe.2 for ; Mon, 19 Jul 2021 02:31:04 -0700 (PDT) X-Gm-Message-State: DHcx1u7zJQktJcMvx1KLXATZx1787277AA= X-Google-Smtp-Source: ABdhPJxjTxZzC80VYoRs45Rbjy3Ck8tND+Z6rUOQwmwlzjKCjsSLBVtdsDoI7MKQgpMHJ8Lc4DuVDg== X-Received: by 2002:ac2:54a2:: with SMTP id w2mr17881690lfk.283.1626687063225; Mon, 19 Jul 2021 02:31:03 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:02 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com Subject: [edk2-devel] [edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Date: Mon, 19 Jul 2021 11:30:13 +0200 Message-Id: <20210719093015.1490932-6-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687065; bh=V8zrTh7FfiVFeJ1cTIgmRCn8V8d0r1Kc5JHrTFY6nXg=; h=Cc:Date:From:Reply-To:Subject:To; b=aJ9abY7ICglBSxFS9Gw/3phbfj5YJSQj4J8EIxO3MCL8vDTKraybv71DKTb2TVj/MMJ m9R6SGyPy0DqCMAbsD8j+OSbZLWv62uw9N78+VeOCGFgt2uMu3f4xO0H5BbhLsUmsGYcC z8+jRTsYH3mbAsq9sM7dPxInrBFB5ASFO+I= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687066713100016 Content-Type: text/plain; charset="utf-8" From: Grzegorz Bernacki Since the beginning of the EDK2 port Marvell platfroms have been using a dated EmbeddedPkg's MonotonicCounter driver. Switch to the actively maintained MonotonicCounterRuntimeDxe, what fixes ACS3.0 BS.GetNextMonotonicCount test case. Signed-off-by: Grzegorz Bernacki --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index c919d4bfab..05e7f68191 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -476,7 +476,7 @@ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf =20 - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index e003623f15..bc7284652b 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -112,7 +112,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77884): https://edk2.groups.io/g/devel/message/77884 Mute This Topic: https://groups.io/mt/84304358/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77885+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77885+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687067; cv=none; d=zohomail.com; s=zohoarc; b=LcG0+2s3SewTkX0AVlIGWVanlk+tUXUolbAVfdmA615JoDIfsWuYirIZ0lnDuUBCWoMwkk/jtnPeuWZOlolVaHmdfPQStNok6IP/T8Cijpzi4oM/dR9AwpNRSnANVwzz6drcKVwMF3V3UrV1NFqvyKUrBJsJqXF0iHgp6cuRtMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687067; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=DUVjZVaCf5JngpiINQRyVbq4+hiQ37rplvaAqG9FFD4=; b=K0sDj0oyE6XXhGA5M14UYNIGncYtSBOnHPonqBIkT/3/v8ZOCsnHUD1886TyrhnCOKQfO+VXNN3AdjIukLuNk47iajbPiFzT2Rqj1VR+TGBcJSP1MDtjaBm8fVWNQZ8jmg3lpO4GDFiQPrfSYQU2A2X/tLWseH4s8aEoYMpim+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77885+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687067234271.87936783812665; Mon, 19 Jul 2021 02:31:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dpCbYY1788612xrT7vqDKGvW; Mon, 19 Jul 2021 02:31:06 -0700 X-Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by mx.groups.io with SMTP id smtpd.web11.25523.1626687066055593332 for ; Mon, 19 Jul 2021 02:31:06 -0700 X-Received: by mail-lf1-f47.google.com with SMTP id s13so7625005lfi.12 for ; Mon, 19 Jul 2021 02:31:05 -0700 (PDT) X-Gm-Message-State: L5fP6E22SgLJUaBiW0XDONu8x1787277AA= X-Google-Smtp-Source: ABdhPJwEOhsG15fnwCCfZ/Uvu+N96OhksFRkJPL5IlA84h+GJRB7ozSI+MwEx3a3myEqmRdkPxncqg== X-Received: by 2002:a05:6512:3395:: with SMTP id h21mr17571475lfg.489.1626687064232; Mon, 19 Jul 2021 02:31:04 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:03 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Date: Mon, 19 Jul 2021 11:30:14 +0200 Message-Id: <20210719093015.1490932-7-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687066; bh=IapJS6Og6vPIffSqT3xax83fdoEHvJjZkeFjsoqTDPA=; h=Cc:Date:From:Reply-To:Subject:To; b=Ocfcz9jjV2N/6cKsIJCr+o8RuGc4gekTA4JRe2fbgSLPe+zck1AcfjWp9/ui+zMj+rl ID5mRi/2ZBxPz3TB6TGLCRsPi5JnUUqKlEaCYQ6T7qTc7EKSTC6hdZz3cMmLzjkZPPjnE joW/l57R9+KRj3NHx70Y3DtgpYM0+ywxWkU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687068760100024 Content-Type: text/plain; charset="utf-8" This patch updates 2 fields of the SMBIOS Type0 table. The "Vendor" and the BiosVersion strings are set according to the values of the newly introduced PCD's. Note, that the gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString could not be used, as its format does match the required by SMBIOS tables (CHAR8 *). Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Marvell.dec | 2 ++ Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 ++ Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index cdf8154d40..482a90da25 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -170,6 +170,8 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 #Platform description + gMarvellTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semih= alf"|VOID*|0x50000104 + gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105 gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100 gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board= "|VOID*|0x50000101 gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103 diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 7722146292..582c0faf25 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -40,6 +40,8 @@ gMarvellTokenSpaceGuid.PcdProductPlatformName gMarvellTokenSpaceGuid.PcdProductSerial gMarvellTokenSpaceGuid.PcdProductVersion + gMarvellTokenSpaceGuid.PcdFirmwareVendor + gMarvellTokenSpaceGuid.PcdFirmwareVersion =20 [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c = b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index a99291e902..ed67a39cb1 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -77,9 +77,9 @@ STATIC SMBIOS_TABLE_TYPE0 mArmadaDefaultType0 =3D { }; =20 STATIC CHAR8 CONST *mArmadaDefaultType0Strings[] =3D { - "EFI Development Kit II / Marvell\0", /* Vendor */ - "EDK II\0", /* BiosVersion */ - __DATE__"\0", /* BiosReleaseDate */ + (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVendor), /* Vendor */ + (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVersion), /* BiosVersion */ + __DATE__"\0", /* BiosReleaseDate */ NULL }; =20 --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77885): https://edk2.groups.io/g/devel/message/77885 Mute This Topic: https://groups.io/mt/84304359/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 07:24:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77886+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77886+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1626687068; cv=none; d=zohomail.com; s=zohoarc; b=k79DPoRqpDSjUl8YiMRbpOmP/FDQCH+09m93Jwlj0gbMhYaZtOm2+BUxbGKW+rfmO1wNFklNAXjN0W9t5DQ0ad2pn9SuPsZ/0r3ytvh0qGqlUB3hgE4ndcSansp20AGOtO9GVqRTEZ6zO9HscBzG294u5tFxl+gTMcGMcW4Ombk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626687068; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qVag0tTa4d138xbvh0Dd/rEF1KjuXF8yVYk1ToHIWsc=; b=HrJZ/YrDY5M4Zoicpogmso6Ezmz6NuC3QasGuy6DjzCzUe0hZ4xlImNwHjrPK4RphfBejO+2qEulPqHn27kzAShbEP6wPmMbrTXXx2kVNwisST+T8WOyxTyb0Tlmm7pV72wHddkWXQ81PxvWZI0cHfjdCIjKmr27K4eSRCk9MvA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77886+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626687068223931.6800912047157; Mon, 19 Jul 2021 02:31:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8fFnYY1788612xFTvBjgOU12; Mon, 19 Jul 2021 02:31:07 -0700 X-Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) by mx.groups.io with SMTP id smtpd.web12.25684.1626687067112007194 for ; Mon, 19 Jul 2021 02:31:07 -0700 X-Received: by mail-lj1-f176.google.com with SMTP id d17so5234041ljq.12 for ; Mon, 19 Jul 2021 02:31:06 -0700 (PDT) X-Gm-Message-State: N6ySLJlnmnvaBtAM1J9Uw7Cpx1787277AA= X-Google-Smtp-Source: ABdhPJwJ2RAicwctcTDd4vg+KWyC+Ncw67VE7MXTx16RdEOoE/jTlr0yx0X3puyV5uAToR+Ob514eg== X-Received: by 2002:a2e:5307:: with SMTP id h7mr21769049ljb.181.1626687065346; Mon, 19 Jul 2021 02:31:05 -0700 (PDT) X-Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id u14sm1252560lfr.86.2021.07.19.02.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 02:31:04 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, upstream@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, jon@solid-run.com, Marcin Wojtas Subject: [edk2-devel] [edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Date: Mon, 19 Jul 2021 11:30:15 +0200 Message-Id: <20210719093015.1490932-8-mw@semihalf.com> In-Reply-To: <20210719093015.1490932-1-mw@semihalf.com> References: <20210719093015.1490932-1-mw@semihalf.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626687067; bh=VlklXKXVHuKO/JNYK/4yxHLT+TzDQ/JoMVfINCgnKrc=; h=Cc:Date:From:Reply-To:Subject:To; b=fNE9/07yC93NqNQXcOGO4RBdy/1qAtYZKnzTmrYfXISjchKCV3VvIHnABRBQAm6CBNV GPMIemp4R87xejf5BqLp4RZTFKL9YYLAwjOkj9HIXy+PZLZENejY68DyeQHDZTk5D889L wN7qRntHvZEYEo02rvr58NLQKbmEG75O8zY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626687068867100027 Content-Type: text/plain; charset="utf-8" After the recent SystemReady ES compliance fixes, ACPI enhancements and other improvements bump revision of the Marvell-based platforms to "EDK2 SH 1.0". Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 05e7f68191..d398d9432f 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -241,7 +241,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0= 000 =20 [PcdsFixedAtBuild.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2 SH 1.0" gArmPlatformTokenSpaceGuid.PcdCoreCount|4 =20 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 @@ -381,6 +381,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302 + gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.0" =20 # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 --=20 2.29.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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