From nobody Mon Feb 9 07:42:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77705+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77705+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136910; cv=none; d=zohomail.com; s=zohoarc; b=fnfkQBJu22BEl2+3Mp9M/0z35kzNMEs3mPMJ70E/HOFhMulLXMIjhMsbGoG6emP8j+AwC+j6vbaQLZx7PLMK5nInvLSj0ktB9Bg7TATBYw+TysMSBzTe0pZv84hDLWcCjKhO/tf9VjkCmaMEQtAv0CgcWkAouGna2Onwy7AcNYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626136910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=hrdE1CRCUZs9Q7Xyz4Fn90Nxe2WSqbikPzSo++4DgSY=; b=X+GDsZX0u0mwmq75c80BRtiobKT4MxYVg24UGc3HTN0kr+e3i7vWR33rF0IgvH6h/05nRQ1jUTWyN2ZQfwFmDcYwSf70dKqg64dQ8HtADlUUJFziwCUIszRz5fVCgxpAzLPVcP1wvkIoTeCpIfDUjFQTWy+PcTaGtLx6GqeAl+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77705+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626136910180570.3795639821882; Mon, 12 Jul 2021 17:41:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CUGoYY1788612xs9MUQRjpZu; Mon, 12 Jul 2021 17:41:49 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.2559.1626136908854305417 for ; Mon, 12 Jul 2021 17:41:49 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723115" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723115" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:48 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422921" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:47 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 03/17] WhitleySiliconPkg: Add Cpu Includes Date: Mon, 12 Jul 2021 17:41:17 -0700 Message-Id: <20210713004131.1782-4-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: 3aLUOoKXIeDUOg0AbPdYKEHxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136909; bh=oNM67MoA6CbjplJIzgIfmz7E+03XsPLbRFZdlZp32KE=; h=Cc:Date:From:Reply-To:Subject:To; b=R36Qc768BhC5Pl7grXQ7GlYpfVkHZl8bJBGZap1sBEeJVAQ7rH7tCfK9J+HoQu5h2Av YdiBqviG9+Ho0WuyzEOceOP7DAH/JxvlXpMjVzOBLo75gkOIqlpFHiybtbgHGt9A+4GLM uAA56b3HnhJzkLV/GgJDPNHk57j/NtqxTnQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136910632100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki --- .../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 101 ++++++ .../Cpu/Include/CpuDataStruct.h | 27 ++ .../Cpu/Include/CpuPolicyPeiDxeCommon.h | 58 ++++ .../Cpu/Include/Guid/CpuNvramData.h | 34 ++ .../Cpu/Include/Library/CpuConfigLib.h | 30 ++ .../Cpu/Include/Library/CpuEarlyDataLib.h | 41 +++ .../Cpu/Include/Library/CpuPpmLib.h | 16 + .../Cpu/Include/PpmPolicyPeiDxeCommon.h | 320 ++++++++++++++++++ .../Cpu/Include/ProcessorPpmSetup.h | 14 + .../Cpu/Include/Protocol/CpuPolicyProtocol.h | 31 ++ .../Cpu/Include/Protocol/PpmPolicyProtocol.h | 16 + 11 files changed, 688 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStru= ct.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPe= iDxeCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvr= amData.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= ConfigLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= EarlyDataLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= PpmLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPe= iDxeCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPp= mSetup.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/Cp= uPolicyProtocol.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/Pp= mPolicyProtocol.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Int= el/WhitleySiliconPkg/Cpu/CpuRcPkg.dec new file mode 100644 index 0000000000..f30558b5d8 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec @@ -0,0 +1,101 @@ +## @file +# Package for support of CPU RC +# This package supports IA32 family processors, with CPU DXE module, CPU P= EIM, CPU S3 module, +# SMM modules, related libraries, and corresponding definitions. +# +# @copyright +# Copyright 2017 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D CpuRcPkg + PACKAGE_GUID =3D 6F855AF8-759E-4834-9AA4-05EC977A51BB + PACKAGE_VERSION =3D 0.5 + +[Includes] + Include + +[LibraryClasses] + CpuConfigLib|Include/Library/CpuConfigLib.h + CpuS3MsrLib|Include/Library/CpuS3MsrLib.h + CpuPpmLib|Include/Library/CpuPpmLib.h + CpuIpLib|Include/Library/CpuIpLib.h + CpuEarlyDataLib|Include/Library/CpuEarlyDataLib.h + CpuInitLib|Include/Library/CpuInitLib.h + PeiCpuLatePolicyLib|Include/Library/PeiCpuLatePolicyLib.h + CpuPolicyLib|Include/Library/CpuPolicyLib.h + +[Guids] + gCpuPkgTokenSpaceGuid =3D { 0x513876ac, 0x4f71, 0x4543, { 0x8a,= 0xf7, 0x27, 0xb, 0x19, 0x2b, 0xed, 0x3c }} + gEfiCpuNvramDataGuid =3D { 0x184220a2, 0xe14c, 0x4497, { 0x85,= 0xbb, 0x14, 0x90, 0xa9, 0xa1, 0xf0, 0xd3 }} + gEfiPmSsdtTableStorageGuid =3D { 0x1d33f981, 0x43f0, 0x4a09, { 0xab,= 0x3b, 0x2f, 0xf4, 0xf7, 0x11, 0x99, 0x9a }} + +[Ppis] + gPpmPolicyPpiGuid =3D { 0xd86e33b4, 0x414f, 0x4941, { 0xb2,= 0x84, 0x31, 0xe0, 0x3b, 0x3f, 0xc0, 0xf7 }} + gPeiCpuLatePolicyPpiGuid =3D { 0x97415556, 0x8c58, 0x4e12, { 0x8e,= 0xaf, 0x1, 0x98, 0x65, 0x50, 0xc5, 0xaa }} + +[Protocols] + gEfiCpuPolicyProtocolGuid =3D { 0xec7c60b4, 0xa82c, 0x42a5, { 0xbe,= 0x76, 0x87, 0xfc, 0xb5, 0x81, 0xa9, 0x1b }} + gPpmPolicyProtocolGuid =3D { 0xd1b6a52c, 0x6810, 0x4957, { 0xa5,= 0xfb, 0x85, 0x7b, 0xb2, 0xb5, 0xa3, 0xda }} + gEfiCpuPpmProtocolGuid =3D { 0x7e6a6cf5, 0xc89c, 0x492f, { 0xac,= 0x37, 0x23, 0x07, 0x84, 0x9c, 0x3a, 0xd5 }} + ## This protocol indicates CPU config context data is ready. + gCpuConfigContextReadyProtocolGuid =3D { 0x63a25a21, 0xeb79, 0x4835, { 0= xaf, 0x76, 0x75, 0x32, 0x7, 0xa1, 0x31, 0xed }} + +[PcdsFeatureFlag] + gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|FALSE|BOOLEAN|0x10000036 + gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|FALSE|BOOLEAN|0x10000038 + gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + + ## Indicates the platform type: desktop, mobile or server.

+ # 0 - desktop
+ # 1 - mobile
+ # 2 - server
+ # @Prompt Platform type. + # @ValidRange 0x80000001 | 0 - 2 + gCpuPkgTokenSpaceGuid.PcdPlatformType|0|UINT8|0x60000003 + gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|0x0|UINT32|0x600000= 04 + + ## Indicates if Intel Enhanced Debug (IED) will be enabled. + # Note that for some processors, IED is optional, but for others, IED i= s required.

+ # TRUE - IED will be enabled.
+ # FALSE - IED will be disabled.
+ # @Prompt Enable IED. + gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|FALSE|BOOLEAN|0x6000000B + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x20000|UINT32|0x6000000C + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamBase|0x0|UINT32|0x6000001D + + ## Specifies the Energy efficiency policy when Energy Performance Bias f= eature is enabled. + # 0 - indicates preference to highest performance. + # 15 - indicates preference to maximize energy saving. + # @Prompt The Energy efficiency policy. + # @ValidRange 0x80000001 | 0 - 15 + gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy|0x0|UINT8|0x60008000 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x600000= 14 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x60000015 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x60000016 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x60000017 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x60000= 01C + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x60000021 + + ## Specifies the register table entry maximum count for every processor = in the CPU config context buffer. + # @Prompt CPU Config Register Table Entry Maximum Count. + gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x6000= 0022 + +[PcdsDynamic, PcdsDynamicEx] + gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 + + gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 + + ## Contains the pointer to a buffer where new socket IDs to be assigned = are stored. + # @Prompt The pointer to a new socket ID buffer. + gCpuPkgTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x= 1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0= x0,0x3,0x0,0x0,0x0}|VOID*|0x60008007 diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h b/= Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..aaabf032f9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +#define inline __inline + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + +#ifndef MAX_CORE +#define MAX_CORE (FixedPcdGet32 (PcdMaxCpuCoreCount)) +#endif + +// +// Total TDP levels for Config TDP + Speed Select (ISS/SST) +// +#define CONFIG_TDP_TOTAL_LEVEL 5 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h new file mode 100644 index 0000000000..6e84e0f7a6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h @@ -0,0 +1,58 @@ +/** @file + Intel CPU PPM policy common structures and macros for both + CPU late policy PPI and CPU policy protocol. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __CPU_POLICY_PEI_DXE_COMMON_HEADER__ +#define __CPU_POLICY_PEI_DXE_COMMON_HEADER__ + +typedef struct { + BOOLEAN CpuTStateEnable; + UINT8 CpuClockModulationDutyCycle; + BOOLEAN CpuAesEnable; + BOOLEAN CpuFastStringEnable; + BOOLEAN CpuMaxCpuidValueLimitEnable; + BOOLEAN CpuMachineCheckEnable; + BOOLEAN CpuMonitorMwaitEnable; + BOOLEAN CpuVtEnable; + BOOLEAN CpuLtEnable; + BOOLEAN CpuX2ApicEnable; + BOOLEAN CpuEistEnable; + BOOLEAN CpuTurboModeEnable; + BOOLEAN CpuHwCoordinationEnable; + UINT8 CpuBootPState; + BOOLEAN CpuPpinControlEnable; + BOOLEAN CpuPeciDownstreamWriteEnable; + BOOLEAN CpuL1NextPagePrefetcherDisable; + BOOLEAN CpuDcuPrefetcherEnable; + BOOLEAN CpuIpPrefetcherEnable; + BOOLEAN CpuMlcStreamerPrefetecherEnable; + BOOLEAN CpuMlcSpatialPrefetcherEnable; + BOOLEAN CpuAmpPrefetchEnable; + BOOLEAN CpuThreeStrikeCounterEnable; + BOOLEAN CpuCStateEnable; + UINT8 CpuPackageCStateLimit; + BOOLEAN CpuC1AutoDemotionEnable; + BOOLEAN CpuC1AutoUndemotionEnable; + UINT8 CpuCoreCStateValue; + UINT16 CpuAcpiLvl2Addr; + BOOLEAN CpuThermalManagementEnable; + UINT8 CpuTccActivationOffset; + BOOLEAN CpuDbpfEnable; + BOOLEAN CpuEnergyPerformanceBiasEnable; + UINT32 CpuIioLlcWaysBitMask; + UINT32 CpuExpandedIioLlcWaysBitMask; + UINT32 CpuRemoteWaysBitMask; + UINT32 CpuRrqCountThreshold; + UINT8 CpuMtoIWa; + BOOLEAN RunCpuPpmInPei; + BOOLEAN AcExceptionOnSplitLockEnable; + BOOLEAN CpuCrashLogGprs; +} CPU_POLICY_COMMON; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.h new file mode 100644 index 0000000000..f033114d16 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.h @@ -0,0 +1,34 @@ +/** @file + GUID used for Cpu Nvram Data entries in the HOB list. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_NVRAM_DATA_GUID_H_ +#define _CPU_NVRAM_DATA_GUID_H_ + +#include + +#define EFI_CPU_NVRAM_DATA_GUID \ + { \ + 0x184220a2, 0xe14c, 0x4497, { 0x85, 0xbb, 0x14, 0x90, 0xa9, 0xa1, 0xf0, = 0xd3 }\ + } + +#define EFI_CPU_NVRAM_DATA_VARIABLE_NAME L"CpuNvramData" + +// +// CPU_NVRAM +// Data that need to be saved in NVRAM for S3 resume +// +typedef struct { // data that need to be saved in= NVRAM for S3 resume + UINT32 flexRatioCsr; // Common for all sockets + UINT64 DesiredCoresCsr[MAX_SOCKET]; // One per socket 64bits + UINT32 DesiredCoresCfg2Csr[MAX_SOCKET]; // One per socket +} CPU_NVRAM; + +extern EFI_GUID gEfiCpuNvramDataGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigL= ib.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h new file mode 100644 index 0000000000..298fe08624 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h @@ -0,0 +1,30 @@ +/** @file + Public include file for the CPU Configuration Library + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include +#include +#include + + +// CPU C State Settings +#define C0_ENABLE 0x00 +#define C6_ENABLE 0x03 + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT32 DefaultSocketId; + UINT32 NewSocketId; +} CPU_SOCKET_ID_INFO; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDa= taLib.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDataL= ib.h new file mode 100644 index 0000000000..7dbc55f765 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDataLib.h @@ -0,0 +1,41 @@ +/** @file + Interface of CPU early data library. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __CPU_EARLY_DATA_LIB_H__ +#define __CPU_EARLY_DATA_LIB_H__ + +#include + +typedef struct { + UINT64 FusedCores[MAX_SOCKET]; // Fused Core Ma= sk in the package 64bits + UINT64 ActiveCores[MAX_SOCKET]; // Active Core M= ask in the package 64bits + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max N= on-turbo Ratio (per socket) + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maxim= um Efficiency Ratio (per socket) + UINT32 PackageBspApicID[MAX_SOCKET]; + UINT8 IssCapableSystem; // 1 =3D All soc= kets config TDP / ISS capable + UINT8 ConfigTdpCapableSystem; // 1 =3D All soc= kets config TDP capable + UINT8 IssConfigTdpMaxLevel; // B2P CONFIG_TD= P_GET_LEVELS_INFO + UINT8 IssConfigTdpCurrentLevel; // B2P CONFIG_TD= P_GET_LEVELS_INFO + UINT8 IssConfigTdpRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_TDP_INFO + UINT16 IssConfigTdpPower[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_TDP_INFO + UINT32 IssConfigTdpPowerMinMax[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_POWER_INFO + UINT8 IssConfigTdpTjmax[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_ICCP_TJMAX_INFO + UINT8 IssConfigTdpCoreCount[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_CORE_MASK + UINT64 IssConfigTdpEnabledCoreMask[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL];= // B2P CONFIG_TDP_GET_CORE_MASK + UINT8 PbfCapableSystem; // 1 = =3D All sockets PBF Capable + UINT8 PbfCapable[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= GET_CONFIG_TDP_CONTROL PBF_SUPPORT Bit[1] + UINT64 PbfP1HiCoreMap[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P P= BF_GET_CORE_MASK_INFO Bits + UINT8 PbfP1HighRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= PBF_GET_P1HI_P1LO_INFO P1_HI + UINT8 PbfP1LowRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= PBF_GET_P1HI_P1LO_INFO P1_LO + UINT32 SstCpSystemStatus; + UINT8 UncoreP0Ratio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= CONFIG_TDP_GET_RATIO_INFO + UINT8 UncorePnRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= CONFIG_TDP_GET_RATIO_INFO +} CPU_VAR_DATA; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.h new file mode 100644 index 0000000000..400cd52080 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.h @@ -0,0 +1,16 @@ +/** @file + This is an implementation of the BootScript at run time. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + +//CSR_PKG_CST_ENTRY_CRITERIA_MASK bit definition (For SKX) +#define SET_PCIEx_MASK 0xF + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCommon.h new file mode 100644 index 0000000000..86c9f4179f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCommon.h @@ -0,0 +1,320 @@ +/** @file + Intel CPU PPM policy common structures and macros for both PPM policy PP= I and + policy protocol. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PPM_POLICY_PEI_DXE_COMMON_HEADER__ +#define __PPM_POLICY_PEI_DXE_COMMON_HEADER__ + + +/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + !!! Keep this file common for both PEI and DXE use !!! + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/ + + +#include + + +#define NUM_CST_LAT_MSR 3 +#define NUM_TURBO_RATIO_GROUP 8 + +// +// Hardware P States Modes +// +typedef enum { + HWP_MODE_DISABLED =3D 0, // also known as legacy P states + HWP_MODE_NATIVE =3D 1, // native with legacy support + HWP_MODE_OOB =3D 2, // out of band + HWP_MODE_NATIVE_NO_LEGACY =3D 3 // native w/o legacy support +} HWP_MODES; + +// +// Power Perf Tuning options +// +// HWP is disabled : OS, BIOS and PECI control all available. OS c= ontrol is the default +// HWP native mode : OS, BIOS and PECI control all available. OS c= ontrol is the default +// HWP is OOB : BIOS and PECI control available. PECI control= is the default +// HWP is native w/o legacy: BIOS and PECI control available. BIOS control= is the default +// +// On CPX, PECI is not available +// +typedef enum { + PWR_PERF_TUNING_OS_CONTROL =3D 0, + PWR_PERF_TUNING_BIOS_CONTROL =3D 1, + PWR_PERF_TUNING_PECI_CONTROL =3D 2 +} POWER_PERF_TUNING_CONTROL; + +#pragma pack(1) + + +typedef struct { + UINT8 PkgCstEntryValCtl; + UINT8 SapmctlValCtl; + UINT8 SkipPkgCstEntry; + UINT8 SwLtrOvrdCtl; + UINT8 PriPlnCurrCfgCtl; + UINT8 CurrentConfig; + UINT8 MsrLock; + UINT8 MsrPkgCstConfigControlLock; + UINT8 MpllOffEnaAuto; + UINT8 DynamicL1Disable; + UINT8 VccsaVccioDisable; + UINT8 PcodeWdogTimerEn; + UINT8 DramRaplPwrLimitLockCsr; + UINT8 EnableLowerLatencyMode; +} ADV_PWR_CTL; + +typedef struct { + UINT8 BidirProchotEnable; + UINT8 C1eEnable; + UINT8 EeTurboDisable; + UINT8 ProchotOutputDisable; + UINT8 SapmControl; + UINT8 PwrPerfSwitch; + POWER_PERF_TUNING_CONTROL PwrPerfTuning; + UINT8 ProchotLock; + UINT8 LtrSwInput; + UINT8 PkgCLatNeg; + UINT8 SetvidDecayDisable; +} POWER_CTL; + +typedef struct { + UINT16 PowerLimit1Power; + UINT8 PowerLimit1En; + UINT16 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT16 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2En; + UINT16 PowerLimit2Time; + UINT8 TurboPowerLimitLock; + UINT8 TurboLimitCsrLock; +} TURBO_POWRER_LIMIT; + +typedef struct { + UINT16 CurrentLimit; + UINT8 PpcccLock; +} PPO_CURRENT_CFG; + +typedef struct { + UINT8 WorkLdConfig; + UINT8 AltEngPerfBIAS; + UINT8 P0TtlTimeHigh1; + UINT8 P0TtlTimeLow1; + UINT16 EngAvgTimeWdw1; +} PERF_BIAS_CONFIG; + +typedef struct { + UINT8 PmaxDetector; + UINT8 PmaxAutoAdjustment; + UINT8 PmaxLoadLine; + UINT8 PmaxSign; + UINT8 PmaxOffset; + UINT8 PmaxOffsetNegative; + UINT8 PmaxTriggerSetup; + UINT16 BasePackageTdp[MAX_SOCKET]; + UINT8 EnhancedPmaxDetector; +} PMAX_CONFIG; + +typedef struct { + UINT8 Iio0PkgcClkGateDis; + UINT8 Iio1PkgcClkGateDis; + UINT8 Iio2PkgcClkGateDis; + UINT8 Kti01PkgcClkGateDis; + UINT8 Kti23PkgcClkGateDis; + UINT8 Kti45PkgcClkGateDis; + UINT8 Mc0PkgcClkGateDis; + UINT8 Mc1PkgcClkGateDis; + UINT8 P0pllOffEna; + UINT8 P1pllOffEna; + UINT8 P2pllOffEna; + UINT8 Kti01pllOffEna; + UINT8 Kti23pllOffEna; + UINT8 Kti45pllOffEna; + UINT8 Mc0pllOffEna; + UINT8 Mc1pllOffEna; + UINT8 Mc0PkgcIoVolRedDis; + UINT8 Mc1PkgcIoVolRedDis; + UINT8 Mc0PkgcDigVolRedDis; + UINT8 Mc1PkgcDigVolRedDis; + UINT8 SetvidDecayDisable; + UINT8 SapmCtlLock; +} SAPM_CTL; + +typedef struct { + UINT8 PerfPLimitEn; + UINT8 PerfPLmtThshld; + UINT8 PerfPLimitClipC; + UINT8 PerfPlimitDifferential; +} PERF_PLIMIT_CTL; + +typedef struct { + UINT8 KtiApmOvrdEn; + UINT8 IomApmOvrdEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 UncrPerfPlmtOvrdEn; +} DYNAMIC_PER_POWER_CTL; + +typedef struct { + UINT16 NonSnpLatVal; + UINT8 NonSnpLatMult; + UINT8 NonSnpLatOvrd; + UINT16 NonSnpLatVld; + UINT16 SnpLatVal; + UINT8 SnpLatMult; + UINT8 SnpLatOvrd; + UINT8 SnpLatVld; +} PCIE_ILTR_OVRD; + +typedef struct { + UINT16 Value; + UINT8 Multiplier; + UINT8 Valid; +} CST_LATENCY_CTL; + + +typedef struct { + BOOLEAN C1e; + + UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET]; + UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET]; + CST_LATENCY_CTL LatencyCtrl[NUM_CST_LAT_MSR]; +} PPM_CSTATE_STRUCT; + +typedef struct { + BOOLEAN Enable; + UINT32 Voltage; + UINT16 RatioLimit[MAX_CORE]; +} PPM_XE_STRUCT; + +typedef struct { + UINT8 RatioLimitRatio[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitRatioMask[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitCores[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitCoresMask[NUM_TURBO_RATIO_GROUP]; +} TURBO_RATIO_LIMIT; + +typedef struct { + HWP_MODES HWPMEnable; + UINT8 HWPMNative; + UINT8 HWPMOOB; + UINT8 HWPMInterrupt; + UINT8 EPPEnable; + UINT8 EPPProfile; + UINT8 APSrocketing; + UINT8 Scalability; + UINT8 PPOTarget; + UINT8 RaplPrioritization; + UINT32 SstCpSystemStatus; + UINT8 OutofBandAlternateEPB; + UINT8 ConfigurePbf; + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority = Cores Bitmap + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio +} PPM_HWPM_STRUCT; + +typedef struct { + UINT8 EnablePkgcCriteria; + UINT8 EnablePkgCCriteriaKti[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaRlink[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaFxr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMcddr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHbm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaIio[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHqm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaNac[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaTip[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMdfs[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHcx[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaDino[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpType[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeIio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoKti[MAX_SOCKET]; + UINT8 EnableLinkInL1Kti[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoRlink[MAX_SOCKET]; + UINT8 EnableLinkInL1Rlink[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoFxr[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMcddr[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHbm[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoIio[MAX_SOCKET]; + UINT8 EnableLinkInL1Iio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHqm[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoNac[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoTip[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMdfs[MAX_SOCKET]; + UINT8 AllowLpStateMdfs[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHcx[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoDino[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskDino[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskDino[MAX_SOCKET]; +} PKGC_SA_PS_CRITERIA_STRUCT; + +typedef struct { + UINT8 ThermalMonitorStatusFilter; + UINT8 ThermalMonitorStatusFilterTimeWindow; +} TM_STATUS_Filter; + +typedef struct { + UINT8 IssCapableSystem; + UINT8 DynamicIss; + UINT8 ConfigTDPLevel; + UINT8 ConfigTDPLock; + UINT16 CurrentPackageTdp[MAX_SOCKET]; + UINT8 FastRaplDutyCycle; + UINT32 ProchotRatio; + UINT8 OverclockingLock; + UINT32 C2C3TT; + UINT8 AvxSupport; + UINT8 AvxLicensePreGrant; + UINT8 AvxIccpLevel; + UINT8 GpssTimer; + + ADV_PWR_CTL AdvPwrMgtCtl; + POWER_CTL PowerCtl; + TURBO_POWRER_LIMIT TurboPowerLimit; + PPO_CURRENT_CFG PpoCurrentCfg; + PERF_BIAS_CONFIG PerfBiasConfig; + PMAX_CONFIG PmaxConfig; + TM_STATUS_Filter ThermalReport; + SAPM_CTL SapmCtl[MAX_SOCKET]; + PERF_PLIMIT_CTL PerPLimitCtl; + DYNAMIC_PER_POWER_CTL DynamicPerPowerCtl; + PCIE_ILTR_OVRD PcieIltrOvrd; + + PPM_CSTATE_STRUCT PpmCst; + PPM_XE_STRUCT PpmXe; + PPM_HWPM_STRUCT Hwpm; + TURBO_RATIO_LIMIT TurboRatioLimit; + + PKGC_SA_PS_CRITERIA_STRUCT PkgcCriteria; + + UINT8 CpuThermalManagement; + UINT8 RunCpuPpmInPei; +} PPM_POLICY_CONFIGURATION; + + +#pragma pack() + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.h new file mode 100644 index 0000000000..8623ca5fd9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.h @@ -0,0 +1,14 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PROCESSOR_PPM_SETUP_H +#define _PROCESSOR_PPM_SETUP_H + +#define PPM_AUTO 0xFF + +#endif // _PROCESSOR_PPM_SETUP_H \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicy= Protocol.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicy= Protocol.h new file mode 100644 index 0000000000..955136139c --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicyProtoco= l.h @@ -0,0 +1,31 @@ +/** @file + Intel CPU policy protocol should be installed after CPU related setting + are set by platform driver. CPU driver only could get CPU policy data af= ter this + protocol installed. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_PROTOCOL_H_ +#define _CPU_POLICY_PROTOCOL_H_ + +#include + +#define CPU_POLICY_PROTOCOL_GUID \ + { \ + 0xec7c60b4, 0xa82c, 0x42a5, { 0xbe, 0x76, 0x87, 0xfc, 0xb5, 0x81, 0xa9= , 0x1b } \ + } + +typedef struct { + UINT64 PlatformCpuSocketNames; + UINT64 PlatformCpuAssetTags; + UINT8 SbspSelection; + CPU_POLICY_COMMON Policy; +} CPU_POLICY_CONFIGURATION; + +extern EFI_GUID gEfiCpuPolicyProtocolGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicy= Protocol.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicy= Protocol.h new file mode 100644 index 0000000000..5534a345de --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicyProtoco= l.h @@ -0,0 +1,16 @@ +/** @file + Intel CPU PPM policy protocol should be installed after CPU related sett= ing + are set by platform driver. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PPM_POLICY_PROTOCOL_H_ +#define _PPM_POLICY_PROTOCOL_H_ + +#include + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77705): https://edk2.groups.io/g/devel/message/77705 Mute This Topic: https://groups.io/mt/84168615/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-