From nobody Mon Feb 9 08:12:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77707+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77707+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136910; cv=none; d=zohomail.com; s=zohoarc; b=hK4OcJfDB+3WlTqvG4Fv/EMGx6enkrLy8Ue7y1wx04mxfKp0wkJT6jBXhBVsJYsQZ9P+TkdwmCbbZh6csq/+H4kxTFHz6hGY1Cinl2bddmNWeUKuxreUTCTzjPEPcVrdYwUh7LhDgyhDJXGo9bvNEnzYUlT2J4XSe0aP7azxcqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626136910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=gLhO3VN1cQV3vRXqbyLWsqtSvTH18MbzafyfetD/MkA=; b=HetnMecKILkCxQ+bZXoaOEBXUXeXv28R5kMswaY3ikLUqNlWaGLYd9+I7NlCso9o/XPVUPDs033+Up6BZA7+VSa5H4kl4HNLeVmBQML2mBkwCnKrxhwIEKjjEsHIQy3Qt5C5aV2sHw2k8FbJJY5AXyH/uf/eLYuHu7AywfCD8sQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77707+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626136910727811.708670548502; Mon, 12 Jul 2021 17:41:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kNTRYY1788612xqEU7XyIIo4; Mon, 12 Jul 2021 17:41:50 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.2663.1626136909548654023 for ; Mon, 12 Jul 2021 17:41:49 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723112" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723112" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:45 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422913" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:45 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 01/17] WhitleySiliconPkg: Add DEC and DSC files Date: Mon, 12 Jul 2021 17:41:15 -0700 Message-Id: <20210713004131.1782-2-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: yptMIxrocelo4PVKMDjnX7r5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136910; bh=eJIDC2e603g/F2NarkkHYPbrComMtTvfUL9+jVdHSTI=; h=Cc:Date:From:Reply-To:Subject:To; b=ILPEJm4Y6gBLPaJmv0I3GlVP6sFIayjRtXjQ+fxS5bB70bYNJCWE/peKXMeYuiwv/HW 7uuExjHSbByRwpYcii78mlBkFc0e+vASv/4fbXOKFfzbGyr7inOt6kqhwiKYXqoHrYN5L SgjB+3DB8S3Ou7sUTQNvD7LaLPNaHkg8vpc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136912690100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki --- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 541 +++++++++ .../WhitleySiliconPkg/MrcCommonConfig.dsc | 71 ++ .../Product/Whitley/SiliconPkg10nmPcds.dsc | 99 ++ .../Intel/WhitleySiliconPkg/SiliconPkg.dec | 1004 +++++++++++++++++ .../WhitleySiliconPkg/WhitleySiliconPkg.dec | 65 ++ 5 files changed, 1780 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc create mode 100644 Silicon/Intel/WhitleySiliconPkg/Product/Whitley/Silicon= Pkg10nmPcds.dsc create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/Wh= itleySiliconPkg/CpRcPkg.dec new file mode 100644 index 0000000000..91eace9aa0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -0,0 +1,541 @@ +## @file +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D CpRcPkg + PACKAGE_GUID =3D 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + # + # Over time these will be removed as definitions are moved + # out of BaseMemoryCoreLib and into the standard Include directory + # + + Library/BaseMemoryCoreLib/Core + Library/BaseMemoryCoreLib/Core/Include + Library/BaseMemoryCoreLib/Platform + +[Guids] + + ## Include/Guid/MemBootHealthGuid.h + gMemBootHealthGuid =3D { 0xACD56900, 0xDEFC, 0x4127, { 0xDE= , 0x12, 0x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F }} + + ## Include/Guid/CpRcPkgTokenSpace.h + gEfiCpRcPkgTokenSpaceGuid =3D { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d= , 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }} + gSystemInfoVarHobGuid =3D { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92= , 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }} + gReferenceCodePolicyHobGuid =3D { 0x5AC718A1, 0xFBA0, 0x4F5F, { 0xAF= , 0x9F, 0x20, 0x4A, 0x1A, 0xF6, 0x15, 0x32 }} + + ## Include/SystemInfoVar.h + gEfiSysInfoVarNvramDataGuid =3D { 0x0E5AD476, 0xE47D, 0x4E50, { 0xAE= , 0x9D, 0x38, 0xDF, 0xE2, 0x71, 0x67, 0x96 }} + gStatusCodeDataTypeExDebugGuid =3D { 0x7859daa2, 0x926e, 0x4b01, { 0x85= , 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }} + gDebugDataGuid =3D { 0xED585D92, 0x8F3D, 0x43E3, { 0xB7= , 0x8D, 0xD1, 0xB8, 0xF9, 0x05, 0x7F, 0xCE }} + gPerfStatsGuid =3D { 0x83f6e752, 0xd9ae, 0x48eb, { 0xab= , 0xd4, 0xb5, 0xe9, 0x84, 0x63, 0x60, 0x68 }} + + ## Include/Guid/RcSimGlobalDataHob.h + gEfiRcSimGlobalDataHobGuid =3D { 0x25a4a61a, 0x5a6d, 0x429e, { 0x99= , 0x2b, 0xbe, 0xeb, 0x8a, 0xbd, 0xd8, 0x40 }} + + # OnBoardSPD library + gOnBoardSpdTableGuid =3D { 0xe15c5c55, 0x09ec, 0x4a95, { 0xa3= , 0x5a, 0x1e, 0x72, 0xa3, 0x2c, 0x4f, 0x0f }} + gSpdTableHobGuid =3D { 0x429E8B23, 0xB8B1, 0x4208, { 0x96= , 0xAA, 0x51, 0x5A, 0x11, 0x62, 0x80, 0x40 }} + + ## Include/Guid/FspInfo.h + gFspInfoHobGuid =3D { 0x4a7bd124, 0xcbea, 0x4b3b, { 0x95= , 0x86, 0x11, 0xe6, 0x68, 0xe9, 0xbc, 0xdd }} + + gEfiMemoryConfigDataGuid =3D { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c= , 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }} + + gMemRasS3DataVariableGuid =3D { 0xe626f9ca, 0xfd71, 0x458c, { 0xb9= , 0x26, 0xbf, 0x40, 0x80, 0x62, 0x42, 0xa9 }} + + gStaticPointerSmmSizeGuid =3D { 0xd0ee5959, 0xbae6, 0x4709, { 0xaa= , 0x2b, 0x55, 0xbe, 0x90, 0x57, 0x65, 0x6d }} + + # Enhanced Warning Log (EWL) BDAT schema Guid + gEwlBdatSchemaGuid =3D { 0xbffe532f, 0xca3b, 0x416c, { 0xa0= , 0xf6, 0xff, 0xe4, 0xe7, 0x1e, 0x3a, 0xd }} + + # Memory SPD Raw data BDAT schema Guid + gSpdBdatSchemaGuid =3D { 0x1b19f809, 0x1d91, 0x4f00, { 0xa3= , 0xf3, 0x7a, 0x67, 0x66, 0x6, 0xd3, 0xb1 }} + + # Memory SPD Raw data version ID Guid + gSpdVersion1Guid =3D { 0x46f60b90, 0x9c94, 0x43ca, { 0xa7= , 0x7c, 0x9, 0xb8, 0x48, 0x99, 0x93, 0x48 }} + + # Memory SPD data variable + gSpdVariableGuid =3D { 0x1f5d405b, 0x9b66, 0x4336, { 0x85= , 0xe9, 0x52, 0xb4, 0xee, 0x6a, 0xca, 0x51 }} + + # Memory training data BDAT schema Guid + gMemTrainingDataBdatSchemaGuid =3D { 0x27aab341, 0x5ef9, 0x4383, { 0xae= , 0x4d, 0x9, 0x12, 0x41, 0xb2, 0xfa, 0xc }} + + # Memory training data version ID Guid + gMemTrainingDataVersion1Guid =3D { 0x37e839b5, 0x4357, 0x47d9, { 0xa1= , 0x3f, 0x6f, 0x9a, 0x43, 0x33, 0xfb, 0xc4 }} + + # Memory training data HOB Guid + gMemTrainingDataHobGuid =3D { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86= , 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }} + + # + # Guid for the BiosId file, used only for RcSim + # + gRcSimBiosIdFileGuid =3D { 0xf0c51ad5, 0x44f0, 0x4622, { 0x95= , 0x15, 0xe2, 0x7, 0x71, 0xf0, 0xe0, 0xf2 }} + gSystemTopologyGuid =3D { 0x743e5992, 0xf2a0, 0x4c9f, { 0xa5= , 0xf5, 0x3b, 0x24, 0xad, 0xe8, 0x7f, 0x4d }} + +[PPIs] + ## Include/Ppi/MemorySetupPolicyPpi.h + gMemoryPolicyPpiGuid =3D { 0x731b6dbc, 0x18ac, 0x4cc3, { 0x9= e, 0xe2, 0x9e, 0x5f, 0x33, 0x39, 0x68, 0x81 }} + +[PcdsFeatureFlag] + ## Indicate whether USRA can support S3 + gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012 + + ## Use this feature PCD to support Single PCIe segment with static MMCFG= Base + gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014 + + ## enable/disable USRA trace. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016 + + ## enable/disable Quiesce feature. + gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017 + + ## Enable / disable CTE build feature. + gEfiCpRcPkgTokenSpaceGuid.PcdCteBuild|FALSE|BOOLEAN|0x0000001C + + ## Enable / disable COSIM build feature. + gEfiCpRcPkgTokenSpaceGuid.PcdCosimBuild|FALSE|BOOLEAN|0x0000001D + + ## Enable / disable DDRT2 buffer build + gEfiCpRcPkgTokenSpaceGuid.PcdDdrt2BufferlessBuild|FALSE|BOOLEAN|0x000000= 4F + + # Backside Rank Margin Tool + gEfiCpRcPkgTokenSpaceGuid.EnableBacksideRmt|FALSE|BOOLEAN|0x0000001F + # Backside Command Rank Margin Tool + gEfiCpRcPkgTokenSpaceGuid.EnableBacksideCmdRmt|FALSE|BOOLEAN|0x00000030 + # RMT Pattern Length + gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthCmd|32767|UINT32|0x00000031 + gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthExtCmdCtlVref|32767|UINT32|0x0= 0000032 + gEfiCpRcPkgTokenSpaceGuid.PcdEnableNgnBcomMargining|FALSE|BOOLEAN|0x0000= 0033 + #Enable per bit margining + gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|TRUE|BOOLEAN|0x00000034 + ## Enable / disable MRS STACKING in the CPGC + gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdr|FALSE|BOOLEAN|0x00000037 + gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdrt|FALSE|BOOLEAN|0x00000038 + gEfiCpRcPkgTokenSpaceGuid.MrsStackingNvdimm|FALSE|BOOLEAN|0x00000039 + # Use this PCD to control if separate CWL_adj calculation for 14nm and 1= 0nm + gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|FALSE|BOOLEAN|0x0000003B + + ## Enable / disable USRA register filter. For Sim and SMM. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterFilterEnable|TRUE|BOOLEAN|0x000= 0002D + ## Enable / disable USRA register log. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterLogEnable|TRUE|BOOLEAN|0x000000= 2E + + ## Enable / disable override of debug levels during MRC call table execu= tion + gEfiCpRcPkgTokenSpaceGuid.PcdDebugLevelsOverride|TRUE|BOOLEAN|0x00000050 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved1|TRUE|BOOLEAN|0x00000051 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved2|FALSE|BOOLEAN|0x0000011c + gEfiCpRcPkgTokenSpaceGuid.PcdReserved3|FALSE|BOOLEAN|0x0000011d + gEfiCpRcPkgTokenSpaceGuid.PcdReserved4|FALSE|BOOLEAN|0x0000011e + + gEfiCpRcPkgTokenSpaceGuid.Reserved15|FALSE|BOOLEAN|0x00000052 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved5|TRUE|BOOLEAN|0x00000053 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved6|FALSE|BOOLEAN|0x00000054 + + #Enable\Disable Mem Boot Health Feature + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|TRUE|BOOLEAN|= 0x00000055 + #Control Opportunistic Self Refresh(OSR) feature. + #PCD hides\shows the OSR Setup knob based on setting + #default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshSupported|FALSE|BOO= LEAN|0x00000115 + + gEfiCpRcPkgTokenSpaceGuid.PcdDprSizeFeatureSupport|FALSE|BOOLEAN|0x00000= 056 + + #SecurityPolicy + gSecurityPolicyDataGuid.PcdCoSignEnable|FALSE|BOOLEAN|0xE000002F + +[PcdsFixedAtBuild] + # + # MRC build time configuration PCD's + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE|BOOLEAN|0x00000100 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|FALSE|BOOLEAN|0x00= 000101 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE|BOOLEAN|0x00000102 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE|BOOLEAN|0= x00000103 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE|BOOLEAN|0x00000104 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE|BOOLEAN|0x00000= 105 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE|BOOLEAN|0= x00000106 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE|BOOLEAN|0x000001= 07 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE|BOOLEAN|0x0= 0000113 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSpdDecodeLibTrace|FALSE|BOOLEAN|0x0= 0000114 + + #PCD controls Setup default for OSR + #Default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshDefault|0|UINT8|0x0= 0000116 + #PCD controls Setup default for DDRT Self Refresh + #Default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSrefDefault|0|UINT8|0x00000117 + + # + # Dimm support + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE|BOOLEAN|0x00000108 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE|BOOLEAN|0x00000109 + + # + # SVID support + # + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidSupported|TRUE|BOOLEAN|0x8000010A + + # + # Miscellaneous MRC options + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE|BOOLEAN|0x= 00000110 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE|BOOLEAN|0x00000112 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|FALSE|BOOLEAN|0x00000111 + + ## Indicates the size of each PCIE segment + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010 + gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013 + ## Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018 + ## Maximum number of sockets supported for this firmware build. + # This PCD should be used sparingly. Dynamic allocation of data and + # dynamic control flows are preferred over using this PCD for static + # data allocation and control. + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019 + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|0x22|UINT32|0x0000001A + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|0x2|UINT32|0x0000001B + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutBaseClock|0x0000001C= |UINT32|0x00000022 + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutThreshold|0x0000000C= |UINT32|0x00000023 + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutCreditLimit|0x000000= 20|UINT32|0x00000024 + ## Enable / Disable USRA trace configuration by IO port + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortEnable|FALSE|BOOL= EAN|0x00000025 + ## Set the specific IO port for trace configuration low byte + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortLow|0x81|UINT8|0x= 00000026 + ## Set the specific IO port for trace configuration high byte + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortHigh|0x82|UINT8|0= x00000027 + + ## PcdUsraTraceConfigurationValue is used to control the USRA trace beha= vior, and the defination shown as below. + # When PcdUsraTraceConfigurationPortEnable is TRUE, this configuration v= alue can be overridden by configuration IO port. + # When PcdUsraTraceConfigurationPortEnable is FALSE, the value can be ov= erridden via the interface SetUsraTraceConfiguration(). + # Bit 0 - Bit 3 : USRA trace Signature,it should always be 0101B. + # Bit 4: Set indicates USRA trace message's format is long m= ode. + # Bit 5: Set indicates get address operation is traced. + # Bit 6: Set indicates modify operation is traced. + # Bit 7: Set indicates write operation is traced. + # Bit 8: Set indicates read operation is traced. + # Bit 9: Set indicates PCIE access is traced. + # Bit 10: Set indicates CSR access is traced. + # Bit 11 - Bit14: Reserved for future uses. + # Bit 15: Set indicates dumps the content of CpuCsrAccessVar = before dumping the register access trace information. + # @Prompt USRA trace configuration settings. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationValue|0x07F5|UINT16|0= x00000028 + ## Default value to USRA trace start at earlier stage, this value can be= overridden by the interface UsraTraceStart() + ## and UsraTraceEnd(). + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceStartAtEarlierStage|FALSE|BOOLEAN|= 0x00000029 + ## Indicates whether it needs to clear temp bus assignment in PCIE commo= n init library + gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE|BOOLEAN|0x00000= 02A + + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion|{0, 0, 0, 0}|RC_VERSION|0x0000001= 5 { + + RcVersion.h + + WhitleySiliconPkg/CpRcPkg.dec + } + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x0033 + + # + # MRC DEFAULT SETTINGS + # + + # PCD NAME | = VALUE| TYPE| PCD NUM. + ## Default Enable / Disable Legacy RMT Feature + gEfiCpRcPkgTokenSpaceGuid.PcdLegacyRmtEnable | = 1| UINT8|0x0000001E + + + # + # Enforce memory POR configurations + # 0 (ENFORCE_POR_EN) - Enforce memory POR + # 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal + # 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations + # + gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | = 0| UINT8|0x00000040 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE= |BOOLEAN|0x0000003A + + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | = FALSE|BOOLEAN|0x00000060 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastColdBootDefault | = TRUE|BOOLEAN|0x00000061 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault | = TRUE|BOOLEAN|0x00000062 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault | = 0xFF| UINT8|0x00000063 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault | = 0xFF| UINT8|0x00000064 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault | = 0x0| UINT8|0x00000065 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | = 0x2| UINT8|0x00000066 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | = FALSE|BOOLEAN|0x00000067 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | = 0x6| UINT8|0x00000068 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOO= LEAN|0x00000069 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | = TRUE| UINT8|0x0000006A + + + #Setup string for Mem boot health check + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHea= lthConfig"| VOID*|0x00000070 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | = FALSE|BOOLEAN|0x00000071 + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | = FALSE|BOOLEAN|0x00000072 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2= | UINT8|0x0000011F + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE= |BOOLEAN|0x00000120 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | = FALSE|BOOLEAN|0x00000075 + #option to choose Mem Boot Health configuration type. 00=3D>Auto (Use de= faults), 01=3D>Manual (Override defaults with setup option), 02=3D>Disable = (Disable feature) + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | = 00| UINT8|0x00000076 + + # The below values are setup\standard\build defaults. Can be overridden = in platform specific dsc + ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS STARTS########= ############################# + #Left edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayLeftEdge | = 5| UINT8|0x00000077 + #Right edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayRightEdge | = 5| UINT8|0x00000078 + #Left edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefLeftEdge | = 5| UINT8|0x00000079 + #Right edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefRightEdge | = 5| UINT8|0x0000007A + #Left edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayLeftEdge | = 5| UINT8|0x0000007B + #Right edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayRightEdge | = 5| UINT8|0x0000007C + #Left edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefLeftEdge | = 5| UINT8|0x0000007D + #Right edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefRightEdge | = 5| UINT8|0x0000007E + ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS ENDS##########= ############################# + + ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS STARTS#######= ############################# + #Left edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayLeftEdge | = 2| UINT8|0x0000007F + #Right edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayRightEdge | = 2| UINT8|0x00000080 + #Left edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefLeftEdge | = 2| UINT8|0x00000081 + #Right edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefRightEdge | = 2| UINT8|0x00000082 + #Left edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayLeftEdge | = 2| UINT8|0x00000083 + #Right edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayRightEdge | = 2| UINT8|0x00000084 + #Left edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefLeftEdge | = 2| UINT8|0x00000085 + #Right edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefRightEdge | = 2| UINT8|0x00000086 + ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS ENDS#########= ############################# + + # Option to enable/disable RMT minimum margin test + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumMarginCheckDefault | = 1| UINT8|0x00000124 + + # Define the default minimum margin thresholds for RMT margin check + # The minimum margin thresholds are applied to both margin directions. + # Rx timing: RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxTimingMargin | = 3| UINT8|0x00000125 + # Rx voltage: RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxVoltageMargin | = 3| UINT8|0x00000126 + # Tx timing: TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxTimingMargin | = 3| UINT8|0x00000127 + # Tx voltage: TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxVoltageMargin | = 3| UINT8|0x00000128 + # Cmd timing: CmdAll + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdTimingMargin | = 5| UINT8|0x00000129 + # Cmd voltage: CmdVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdVoltageMargin | = 5| UINT8|0x00000130 + # Ctl timing: CtlAll + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | = 5| UINT8|0x00000131 + + #Reset on Critical Margin failure to perform Memory Training from scratch + gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | = 1| UINT8|0x00000087 + + #Enable Debug message inside MarginTest + #BIT0 for API Debug messages + #BIT1 for Log messages + #BIT2 for Error messages + #BIT3 for Function trace messages + gEfiCpRcPkgTokenSpaceGuid.PcdEvDebugMsg | = 0| UINT8|0x00000088 + + #Non-Configurable...Number of Signals to test. + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootSignalsToTest | = 4| UINT8|0x00000089 + + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved14| FALSE|BOOLEAN|0= x0000008B + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations | = FALSE|BOOLEAN|0x0000008C + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt| = FALSE|BOOLEAN|0x0000008D + # + # Default SMBUS Speed - see SMB_CLOCK_FREQUENCY + # 0 - SMB_CLK_100K - 100 Khz + # 1 - SMB_CLK_400K - 400 Khz + # 2 - SMB_CLK_700K - 700 Khz + # 3 - SMB_CLK_1M - 1 Mhz + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault | = 0x1| UINT8|0x0000008E + + # + # Throttling mid on temp lo + # 0 - Disabled + # 1 - Enabled + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcThrottlingMidOnTempLo | = 0| UINT8|0x0000008F + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault | = 0x1| UINT8|0x00000090 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCtleTrainingEnable | = TRUE|BOOLEAN|0x00000091 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcImodeTrainingEnable | = TRUE|BOOLEAN|0x00000092 + + + #CLTT settings + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault | = 82| UINT8|0x00000093 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault | = 83| UINT8|0x00000094 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault | = 85| UINT8|0x00000095 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault | = 83| UINT8|0x00000096 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault | = 83| UINT8|0x00000097 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault | = 93| UINT8|0x00000098 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault | = 95| UINT8|0x00000099 + + # + # Allowed debug level at build time configuration + # See RcDebugLib.h for mapping details + # + gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugAllowedLevelsMask | = 0xC7F0190B| UINT32|0x0000009A + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTcoCompTrainingEnable | = FALSE|BOOLEAN|0x0000009B + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault | = 0x1| UINT8|0x0000009C + gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault | = 1| UINT8|0x0000009D + + # + # Enforce memory population POR configurations. + # 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce memory = population POR. + # 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported memo= ry populations. + # 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated memo= ry populations. + gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePopulationPorDefault | = 1| UINT8|0x0000009E + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable | = TRUE|BOOLEAN|0x0000009F + + # + # Legacy ADR flow + # 0 (LEGACY_ADR_MODE_DISABLE) - Pcode driven ADR flow + # 1 (LEGACY_ADR_MODE_ENABLE) - Legacy ADR flow + # + gEfiCpRcPkgTokenSpaceGuid.PcdLegacyAdrDefault | = 0| UINT8|0x000000A0 + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault | = 0x1| UINT8|0x000000A1 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPxcDefault | = 0x1| UINT8|0x000000A2 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdjcDefault | = 0x1| UINT8|0x000000A3 + + # + # Default debug level at build time configuration + # + gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugBuildTimeDefault | = 0x8000190B| UINT32|0x000000A9 + + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMarginInCaCsTm | = TRUE|BOOLEAN|0x000000AC + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault | = 0| UINT8|0x000000AE + + #Only enable for 14nm, not a feature for 10nm and above + # 0 =3D Disable + # 1 =3D TA Floor + # 2 =3D Receive Enable Average + # 3 =3D Receive Enable Average part 1 only + gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption | = 0|UINT8|0x000000A4 + + # + # Timers detinitions for priority promotions + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim | = 0x100| UINT16|0x000000A5 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim | = 0x100| UINT16|0x000000A6 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim | = 0x100| UINT16|0x000000A7 + + #Mrc memory default frequency + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdrFrequencyDefault | = 0x0| UINT8|0x000000A8 + + #MRC Panic Watermark default + # 0 =3D Auto, 1 =3D High, 2 =3D Low + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPanicWatermarkDefault | = 0x0| UINT8|0x000000AA + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved15 | = 0x2| UINT8|0x000000AB + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved16 | = 0x0| UINT8|0x000000AD + + # Additional Buffer Delay for Roundtrip + gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk | = 4| UINT8|0x000000AF + + # Option to enable / disable MCR Support + gEfiCpRcPkgTokenSpaceGuid.PcdMcrSupport | = FALSE|BOOLEAN|0x000000B0 + + # Option to store SPD raw data to BDAT + gEfiCpRcPkgTokenSpaceGuid.SaveSpdToBdat | = TRUE|BOOLEAN|0x00000121 + # Option to store training data to BDAT + gEfiCpRcPkgTokenSpaceGuid.SaveMrcTrainingDataToBdat | = TRUE|BOOLEAN|0x00000122 + + + gEfiCpRcPkgTokenSpaceGuid.PcdVendorMemtestEnable | = TRUE|BOOLEAN|0x00000123 + +[PcdsDynamicEx] + ## | = MMCFG Table Header | = Segment 0 | = Segment 1 | = Segment 2 |= Segment 3 = | Segment 4 = | Segment 5 = | Segment 6 = | Segment 7 = | + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011 + + gEfiCpRcPkgTokenSpaceGuid.PcdSimStaticPointerTableMapPtr|{0x0}|VOID*|0x8= 0000012 + +############### SVID Mapping ################################## + #The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, = and 0x16. + #Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (= VR ID's 0x10 and 0x12). + #Those are typically shared such that MC0/MC2 share the same DDR VR (as = they are on the same side of the CPU) + #and MC1/MC3 share the other. Depending on motherboard layout and other = design constraints, this could change + #This information is per platform basis and can be obtained from platfor= m schematics. + #Need to map this token for MC to SVID based on platform. + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap|{0}|MEM_SVID_MAP|0x80000014 { + + Library/MemVrSvidMapLib.h + + WhitleySiliconPkg/WhitleySiliconPkg.dec + } +############### SVID Mapping ################################## + + # IMON SVID VR address + # Fill with IMON SVID Address + # End the list with 0xFF (IMON_ADDR_LIST_END) + # Assumption, all socket repeat same address + #BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + #BIT 0:3 =3D> SVID ADDRESS + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr|{0xFF}|VCC_IMON|0x0000008A { + + ImonVrSvid.h + + WhitleySiliconPkg/WhitleySiliconPkg.dec + } + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32= |0x00000020 + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x000000= 21 + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035 + gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000= 036 + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x0= 0000118 +## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor + gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C + gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D + +[PcdsDynamic, PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00= 000048 + gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0= x00000049 + gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A + gEfiCpRcPkgTokenSpaceGuid.PcdLtMemSize|0x00500000|UINT32|0x0000004B + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable|FALSE|BOOLEAN|0x0000004C + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size|0x0|UINT64|0x0000004D + + # + # PCD for storing sizeof (SysHost) in PEI for later comparision in DXE + # + + gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize|0x00000000|UINT32|0x00= 00004E diff --git a/Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc b/Silicon/= Intel/WhitleySiliconPkg/MrcCommonConfig.dsc new file mode 100644 index 0000000000..be22c51e44 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc @@ -0,0 +1,71 @@ +## @file +# Memory Reference Code configuration file. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# This file is for common defintions for all MRC build targets. +# This is not for platform specific defintions +# + +[PcdsFixedAtBuild] + +# +# MRC Debug configuration options +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE + +# +# Dimm support +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE + +# +# Miscellaneous MRC options +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE + +[PcdsFixedAtBuild.IA32] + +gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|TRUE + +[BuildOptions] + +# +# Size of NvramData structure, per socket +# + DEFINE NUMBER_OF_SUB_CHANNELS =3D -D SUB_CH=3D1 + + DEFINE NUMBER_OF_MAX_RANK_DIMM =3D -D MAX_RANK_DIMM=3D4 + DEFINE NUMBER_OF_MAX_RANK_CH =3D -D MAX_RANK_CH=3D8 + +*_*_*_CC_FLAGS =3D $(NUMBER_OF_SUB_CHANNELS) $(NUMBER_OF_MAX_RANK_DIMM) $= (NUMBER_OF_MAX_RANK_CH) + +# +# Always define IA32 for PEI, undefine for DXE and SMM +# + +*_*_IA32_CC_FLAGS =3D -D IA32 +*_*_X64_CC_FLAGS =3D -U IA32 + + + + + diff --git a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nm= Pcds.dsc b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPc= ds.dsc new file mode 100644 index 0000000000..4402540f91 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc @@ -0,0 +1,99 @@ +## @file +# Pcd definitions for 14nm & 10nm wave1 & 10nm wave2 CPU. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# PCD definitions section - list of all PCD definitions needed by this Pla= tform. +# +##########################################################################= ###### +[PcdsFixedAtBuild] + + # Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010 + + ## Socket count used to indicate maximum number of CPU sockets supported= by the platform. + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|$(MAX_CORE) + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|$(MAX_THREAD) + + ## Indicates whether it needs to clear temp bus assignment in PCIE commo= n init library + gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE + + # Default SMBUS speed for Whitley is 700Khz - see SMB_CLOCK_FREQUENCY de= finition + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault|0x2 + +!if (($(CPUTARGET) =3D=3D "ICX")) + # Overrides specific to ICX-SP + gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault |0 + + # Enable LRDIMM DB DFE for ICX + PMem + gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault |1 + + # Additional Buffer Delay for Roundtrip + gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk |8 +!endif + + # Memory health check default + # 00=3D>Auto (Use defaults), 01=3D>Manual (Override defaults with setup = option), 02=3D>Disable (Disable feature) +!if (($(CPUTARGET) =3D=3D "ICX")) + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck|2 +!endif + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault|TRUE + + # + # Override MRC default values for SKX, defaults are all set + # for 10nm + # + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault|TRUE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault|0x0 + + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault|82 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault|82 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault|100 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault|83 + + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault|84 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault|93 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault|100 + +!else + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault|0x0 +!if ($(CPUTARGET) =3D=3D "ICX") + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim| 0x290 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim|0x290 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim|0x290 +!endif +!endif + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12|1 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13|FALSE + +# +# Enable DDR4 and DDRT turnaround timing optimization for all Whitley +# platforms +# + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations|TRUE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt|TRUE + + # + # enable NVDIMM support + # + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|TRUE \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel= /WhitleySiliconPkg/SiliconPkg.dec new file mode 100644 index 0000000000..d7039f65c4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec @@ -0,0 +1,1004 @@ +## @file +# Platform Package +# Cross Platform Modules for Tiano +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D ServerSiliconPkg + PACKAGE_GUID =3D DD44D851-9A3E-46E8-A2Ef-D794D014ECC1 + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + Security/Include + Pch/SouthClusterLbg + Pch/SouthClusterLbg/Include + + Cpu/Include + +[Guids] + gMrcThermalHobGuid =3D { 0xca8d15fb, 0x= 8776, 0x4eab, { 0xa8, 0xb8, 0xec, 0x2c, 0x32, 0xcf, 0x2a, 0x9b } } + gEfiPlatformInfoGuid =3D { 0x1e2acc41, 0x= e26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } } + gCpuUncoreTokenSpaceGuid =3D { 0x9044434c, 0x= 40e8, 0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 } } + gProcessorProducerGuid =3D { 0x1bf06aea, 0x= 5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } } + gEfiCpuHtCapableGuid =3D { 0x0d1b9c8e, 0x= f77b, 0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 } } + gEfiMemoryConfigDataHobGuid =3D { 0x1de25879, 0x= 6e2a, 0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 } } + gEfiMemorySetupGuid =3D { 0x3eeff35f, 0x= 147c, 0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 } } + gEfiMemoryMapGuid =3D { 0xf8870015, 0x= 6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } } + gEfiMemoryMapDataHobBdatGuid =3D { 0x3417b225, 0x= 916a, 0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 } } + gEfiMpstNodeDataGuid =3D { 0x418bc604, 0x= f15e, 0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 0x88 } } + gReadyForLockProtocolGuid =3D { 0x8d6f1add, 0x= 45a5, 0x45a8, { 0x8b, 0xb8, 0x0c, 0x3a, 0x95, 0x31, 0x48, 0xfa } } + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + gEfiSocketIioVariableGuid =3D { 0xdd84017e, 0x= 7f52, 0x48f9, { 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0x0d, 0xbe, 0x27 } } + gEfiSocketCommonRcVariableGuid =3D { 0x4402ca38, 0x= 808f, 0x4279, { 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f } } + gEfiSocketMpLinkVariableGuid =3D { 0x2b9b22de, 0x= 2ad4, 0x4abc, { 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c } } + gEfiSocketPciResourceDataGuid =3D { 0xca3ff937, 0x= d646, 0x4936, { 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 } } + gEfiSocketMemoryVariableGuid =3D { 0x98cf19ed, 0x= 4109, 0x4681, { 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 } } + gEfiSocketPowermanagementVarGuid =3D { 0xA1047342, 0x= BDBA, 0x4DAE, { 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 } } + gEfiSocketProcessorCoreVarGuid =3D { 0x07013588, 0x= C789, 0x4E12, { 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C } } + gPrevBootErrSrcHobGuid =3D { 0x5138b5c5, 0x= 9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } } + gSocketPkgListGuid =3D { 0x5c0083db, 0x= 3f7d, 0x4b20, { 0xac, 0x9b, 0x73, 0xfc, 0x65, 0x1b, 0x25, 0x03 } } + gEfiReservedMemoryDataGuid =3D { 0xb5535bba, 0x= c858, 0x4302, { 0x8B, 0xcd, 0xd9, 0x3a, 0x70, 0x72, 0x2f, 0x8c } } + gEfiVolatileMemModeVariableGuid =3D { 0x0633a0f1, 0x= 78fe, 0x4139, { 0xb8, 0x78, 0x00, 0x45, 0xe8, 0x1c, 0xb8, 0xab } } + gSignalBeforeEnterSetupGuid =3D { 0xd9f1669a, 0x= f505, 0x48bd, { 0xa8, 0x92, 0x94, 0xb7, 0xca, 0x90, 0x30, 0x31 } } + gEfiQpiRcParmGuid =3D { 0x8149fbb8, 0x= a2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d } } + gAddressBasedMirrorGuid =3D { 0x7b9be2e0, 0x= e28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } } + gEfiPprVariableGuid =3D { 0x6a159d4f, 0x= 6e6b, 0x4523, { 0xae, 0xb5, 0xf7, 0xaf, 0x1c, 0x44, 0x4b, 0x0f } } + gRasStateVariableGuid =3D { 0x9189541f, 0x= ac0c, 0x4368, { 0x90, 0x62, 0x70, 0xe1, 0x95, 0x7c, 0x34, 0x45 } } + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } + gEfiCpuPolicyDataHobGuid =3D { 0x8d1faf2d, 0x= 08d6, 0x4c05, { 0x8b, 0xd3, 0x3b, 0x6c, 0x0f, 0x0f, 0xff, 0x1a } } + gEfiPsmiPolicyDataHobGuid =3D { 0x42ed3781, 0x= 019a, 0x28ae, { 0x16, 0x3b, 0x9a, 0x50, 0x07, 0x0f, 0x93, 0x6b } } + gPsmiInitDataGuid =3D { 0x63f37a26, 0x= 9764, 0x86aa, { 0x91, 0x85, 0xe1, 0x90, 0xab, 0x56, 0x63, 0x49 } } + gEfiKtiHostInDataHobGuid =3D { 0x3c1526ff, 0x= d33e, 0x4ba8, { 0x97, 0x0d, 0x4b, 0x9f, 0x28, 0x92, 0x50, 0xa5 } } + gEfiKtiHostOutDataHobGuid =3D { 0x7080648f, 0x= 430e, 0x430c, { 0xbc, 0x7a, 0x66, 0x25, 0xd4, 0x58, 0x3b, 0x74 } } + gEfiKtiHostNvramDataHobGuid =3D { 0xac45d3d6, 0x= a36e, 0x43a6, { 0xad, 0x17, 0x0a, 0x45, 0xbb, 0x47, 0xbe, 0xd6 } } + gReferenceCodePolicyTokenSpaceGuid =3D { 0x3268c52f, 0x= d3b3, 0x405d, { 0xb6, 0x91, 0x14, 0x4f, 0xca, 0x42, 0xe4, 0x37 } } # {3268= c52f-d3b3-405d-b691-144fca42e437} + gEfiMktmekeyGuid =3D { 0xca3ff937, 0x= d649, 0x4936, { 0x90, 0xe8, 0x2b, 0x95, 0x06, 0x49, 0xb3, 0x82 } } + gSecurityMemMapHobGuid =3D { 0xeec2c166, 0x= fc41, 0x4506, { 0xbc, 0xd6, 0xf0, 0x19, 0x9e, 0x22, 0x9f, 0xa3 } } + gCxlNodeHobGuid =3D { 0xdd8ae009, 0x= da5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } } + gSgxUefiFwKeyBlobsVariableGuid =3D { 0x60F76511, 0x= DD87, 0x466D, { 0x91, 0xA6, 0x3C, 0x18, 0x00, 0xFA, 0xDC, 0x6F } } + gSgxUefiFwKeyBlobsWithIntegrityVariableGuid =3D { 0x582cc492, 0x= 51ee, 0x46db, { 0x8d, 0x34, 0xd8, 0x7c, 0x8e, 0x9a, 0x10, 0x83 } } + gSgxUefiFwRegistrationStateVariableGuid =3D { 0x2C65F1A3, 0x= 5DD5, 0x4A41, { 0xA5, 0xC1, 0xF6, 0x93, 0x7F, 0x77, 0x85, 0xE5 } } + gSgxUefiFwPlatformManifestVariableGuid =3D { 0x06141EE2, 0x= 7CDD, 0x4FDF, { 0xA4, 0x52, 0xAE, 0x7D, 0x20, 0x42, 0x6E, 0x2D } } + gSgxRegistrationConfigVariableGuid =3D { 0x18b3bc81, 0x= e210, 0x42b9, { 0x9e, 0xc8, 0x2c, 0x5a, 0x7d, 0x4d, 0x89, 0xb6 } } + gSgxRegistrationServerRequestVariableGuid =3D { 0x304E0796, 0x= D515, 0x4698, { 0xAC, 0x6E, 0xE7, 0x6C, 0xB1, 0xA7, 0x1C, 0x28 } } + gSgxRegistrationPackageInfoVariableGuid =3D { 0xAC406DEB, 0x= AB92, 0x42D6, { 0xAF, 0xF7, 0x0D, 0x78, 0xE0, 0x82, 0x6C, 0x68 } } + gSgxRegistrationPackageInfoWithIntegrityVariableGuid =3D { 0x4d5e9417, 0= x46f4, 0x4704, { 0xb2, 0x1f, 0xc7, 0xc6, 0x72, 0x13, 0xa0, 0xda } } + gSgxRegistrationServerResponseVariableGuid =3D { 0x89589C7B, 0x= B2D9, 0x4FC9, { 0xBC, 0xDA, 0x46, 0x3b, 0x98, 0x3B, 0x2F, 0xB7 } } + gSgxRegistrationStatusVariableGuid =3D { 0xF236C5DC, 0x= A491, 0x4BBE, { 0xBC, 0xDD, 0x88, 0x88, 0x57, 0x70, 0xDF, 0x45 } } + gSgxRegistrationServerInfoGuid =3D { 0x83E12F21, 0x= 1A6B, 0xA142, { 0xA7, 0xA9, 0xDA, 0x3A, 0xB6, 0xB7, 0xBD, 0x02 } } + gSgxUefiRegistrationConfigVariableGuid =3D { 0x8d4ca9e8, 0x= 44c3, 0x43e5, { 0x93, 0x5e, 0xb6, 0xcc, 0x8f, 0xc5, 0x56, 0x65 } } + gSgxUefiRegistrationServerRequestVariableGuid =3D { 0xcd24952f, 0x= 8175, 0x4797, { 0x8e, 0x7d, 0xd8, 0x4b, 0x15, 0x6a, 0x82, 0x77 } } + gSgxUefiRegistrationServerResponseVariableGuid =3D { 0x35d93155, 0x= 79dc, 0x4b5e, { 0xb6, 0xdf, 0x8e, 0xfe, 0x17, 0x93, 0xa1, 0x5e } } + gSgxUefiRegistrationStatusVariableGuid =3D { 0xcf24d5e9, 0x= 51e3, 0x45b4, { 0x8f, 0xe2, 0x2f, 0x34, 0x5c, 0x5f, 0x76, 0x6b } } + gSgxLegacyRegistrationSoftwareGuardStatusVariableGuid =3D { 0x9cb2e73f, = 0x7325, 0x40f4, { 0xa4, 0x84, 0x65, 0x9b, 0xb3, 0x44, 0xc3, 0xcd } } + gSgxLegacyRegistrationEpcBiosVariableGuid =3D { 0xc60aa7f6, 0x= e8d6, 0x4956, { 0x8b, 0xa1, 0xfe, 0x26, 0x29, 0x8f, 0x5e, 0x87 } } + gSgxLegacyRegistrationEpcSwVariableGuid =3D { 0xd69a279b, 0x= 58eb, 0x45d1, { 0xa1, 0x48, 0x77, 0x1b, 0xb9, 0xeb, 0x52, 0x51 } } + gVtdConfigGuid =3D { 0x03e5cf63, 0x= bebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54, 0x61, 0x20, 0xf1, 0xc5 } } + gPpmBeforeBiosInitDoneGuid =3D { 0x0fce4563, 0x= bebb, 0x4041, { 0xa7, 0xd7, 0xbe, 0xf4, 0x61, 0x20, 0xf1, 0xc5 } } + gPbspTearDownNemAddressHobGuid =3D { 0x2e45be97, 0x= ddc2, 0x4d47, { 0x8f, 0x3b, 0x74, 0x1d, 0x50, 0xdf, 0x20, 0x98 } } + gKtiAdaptationTableGuid =3D { 0x204012d3, 0x= 584d, 0x4325, { 0xae, 0x9e, 0xd7, 0x4d, 0xd8, 0x18, 0x6a, 0xd1 } } + +# +# +# +# RAS +# + gEfiRasHostGuid =3D { 0x8149fbb8, 0x= a2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d } } + gEfiRasClvTesterGuid =3D { 0x9bd36f4f, 0x= 08dc, 0x4eab, { 0x86, 0x37, 0x2b, 0xc1, 0xbd, 0x5e, 0x0d, 0x95 } } + gRasRcPolicyHobGuid =3D { 0x279ED988, 0x= BFEA, 0x43B4, { 0xB3, 0x79, 0xCE, 0x61, 0xAB, 0xDA, 0xC0, 0xB7 } } + gRasRcConfigHobGuid =3D { 0x437872EF, 0x= 2792, 0x47E6, { 0x97, 0xCA, 0xD3, 0xD8, 0xFF, 0xC7, 0x39, 0xA4 } } + gRasGlobalDataVariableGuid =3D { 0xcb4afa36, 0x= 42bf, 0x400b, { 0x8b, 0x8f, 0x57, 0x39, 0x41, 0xa2, 0x9f, 0x4e } } + +## +## Common +## + gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0= x5f, 0x8f, 0xd7, 0x65, 0x4e}} + +# +# Security +# + gSecurityPolicyDataGuid =3D { 0x1781F59B, 0x71FA, 0x4FB1, { 0xB0,= 0x7A, 0x5C, 0x5E, 0xE2, 0xDF, 0x98, 0x14 }} + gSgxInitDataHobGuid =3D { 0x4EF0BEDC, 0xC5C1, 0x4E69, { 0x82,= 0x18, 0x7D, 0xBE, 0x8A, 0x60, 0x68, 0x8C }} + gSgxPreMemInitHobGuid =3D { 0x9A9E2225, 0xE026, 0x4BFF, { 0x99,= 0x17, 0xF1, 0x23, 0xE1, 0xD4, 0x3A, 0xD5 }} + gTmePreMemInitHobGuid =3D { 0x84495ab7, 0xf97f, 0x4502, { 0x93,= 0x12, 0xf7, 0xf4, 0xab, 0x91, 0x09, 0x6e }} + gMktmeInitDataGuid =3D { 0x52eff441, 0x3a19, 0x4d59, { 0x8c,= 0x05, 0x6f, 0x2d, 0x5b, 0x2f, 0xa6, 0xed }} + gTdxDataHobGuid =3D { 0x05885d44, 0x9588, 0x428e, { 0x9e,= 0xb0, 0x1c, 0xa7, 0xe5, 0x4c, 0xa9, 0x6b }} + gSecurityIpInterdependenceGuid =3D { 0x9abadd78, 0xf5b5, 0x4c8e, { 0xa9,= 0x52, 0x3a, 0x83, 0xbe, 0x90, 0x7a, 0x1a }} + +# +# SouthCluster +# + gPchInfoHobGuid =3D { 0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD= 0, 0x36, 0x5F, 0xD6, 0x3E }} + gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0= x97, 0x38, 0x59, 0xd8 }} + gSiPreMemConfigGuid =3D {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, = 0x25, 0x88, 0xbe, 0xfd, 0xc6}} + gSiPolicyHobGuid =3D {0x4ee8c3b9, 0x47a7, 0x4c8a, {0xbb, 0x60, 0x6d, 0= x90, 0xbf, 0x62, 0x10, 0x3c}} + gSiPreMemPolicyHobGuid =3D {0x9142b7e1, 0x411d, 0x475a, {0xab, 0xfc, 0xf= 7, 0x89, 0xb8, 0x2c, 0x24, 0xc8}} + gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x4= 3, 0x66, 0x99, 0xcb, 0xe4, 0x5b}} + gPchIpInfoHobGuid =3D { 0x69247df8, 0x1ecf, 0x4b11, { 0xba, 0xb4, 0x= 28, 0x5a, 0x77, 0xaf, 0x61, 0x11 }} + + gSetupVariableGuid =3D { 0xEC87D643, 0xEBA4, 0x4BB5, = { 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }} + + gChipsetInitHobGuid =3D {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83,= 0x35, 0xfc, 0xc8, 0xd1, 0xc4}} + + gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xE= B, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} + gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x= 36, 0x61, 0xC6, 0x71, 0x3C, 0x5A}} + gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88= , 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}} + gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, 0x= 1a, 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}} + gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1,= 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} + gHpetPreMemConfigGuid =3D {0x7C75C0F1, 0xA20F, 0x42EB, {0x83, 0xDE, 0x= E8, 0x58, 0xAB, 0x81, 0xC5, 0xDC}} + gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0= x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}} + gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC= 6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}} + gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36= , 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}} + gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C= , 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}} + gHsioPreMemConfigGuid =3D {0xbc9e5787, 0x3ddb, 0x4916, {0x8c, 0xcc, 0x= 82, 0xb8, 0x9, 0x43, 0xe2, 0xf0}} + gDmiPreMemConfigGuid =3D {0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA= 3, 0xCF, 0x53, 0xE6, 0xC1, 0x8A}} + gFiaMuxPreMemConfigGuid =3D {0x65667495, 0xA0DF, 0x4481, {0x8D, 0x36, 0x= 01, 0x01, 0x06, 0x98, 0xFD, 0x81}} + gFiaOverrideStatusHobGuid =3D {0x618D94C1, 0x0EDE, 0x4EE3, {0x98, 0x4F, = 0xB2, 0x07, 0x6B, 0x05, 0x50, 0xFB}} + gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0x= CA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} + gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33,= 0xDE, 0x10, 0x6D, 0x94, 0x84}} + gPcieRpDxeConfigGuid =3D {0x475530EA, 0xBD72, 0x416F, {0x98, 0x9F,0x48= , 0x70, 0x5F, 0x14, 0x4E, 0xD9}} + gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0x= C5, 0x9C, 0x54, 0x07, 0xC4}} + gsSataConfigGuid =3D {0xe447c420, 0x3a8e, 0x4d9b, {0x84, 0xe5, 0x4d, 0= x73, 0x77, 0x69, 0xb8, 0xc6}} + gHsiosSataPreMemConfigGuid =3D {0xc4877b20, 0x3098, 0x4952, {0xb8, 0x0= 1, 0x21,0x8a, 0x27, 0xca, 0x75, 0x91}} + gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, = 0x68, 0xBA, 0x87, 0x3E, 0x6C}} + gCio2ConfigGuid =3D {0xFBC4C192, 0x789D, 0x4038, {0x90, 0xE1, 0x5E, 0x= 6D, 0xFD, 0x52, 0xAF, 0x8A}} + gDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x4= 2, 0x9C, 0x4F, 0x17, 0xBD}} + gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA= 3, 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}} + gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2,= 0xBF, 0x4E, 0x91, 0xC3, 0x4C}} + gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0x= E7, 0x7A, 0xA1, 0x4E, 0x87, 0x76}} + gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x5= 8, 0xEA, 0xAC, 0x5E, 0x29, 0x78}} + gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5= D, 0xB8, 0x1C, 0x57, 0x40}} + gLanConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1= A, 0x59, 0x2B, 0x14, 0x2F}} + gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70= , 0xC4, 0x85, 0xFB, 0xA8, 0x0D}} + gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0x= D3, 0xD3, 0x85, 0xFF, 0x07}} + gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1= , 0x0D, 0xF9, 0xE3, 0xA7}} + gSdCardConfigGuid =3D {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x= 93, 0xF5, 0x90, 0x50, 0x27}} + gEmmcConfigGuid =3D {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C= , 0x68, 0xA4, 0xB2, 0x1D}} + gUfsConfigGuid =3D {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51,= 0x2F, 0x2F, 0x8F, 0xA7}} + gEmmcDxeConfigGuid =3D {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE, 0= xF9, 0x0C, 0xB0, 0xC8, 0x18}} + gPort61ConfigGuid =3D {0x59913475, 0x1960, 0x4099, {0x80, 0xEC, 0xAF, = 0xC7, 0xCF, 0x5F, 0x9F, 0xAC}} + gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x5= 4, 0x20, 0x94, 0x05, 0xD0}} + gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA= , 0x09, 0xE5, 0x78, 0x3A, 0xDB}} + gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x7= 3, 0x8C, 0xD2, 0x23, 0x10, 0x96}} + gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x4= 0, 0x26, 0xCA, 0x34, 0x57}} + gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46,= 0x11, 0xF9, 0x23, 0x9E, 0xAE}} + gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xF= B, 0xB7, 0x66, 0x8B, 0xDE}} + gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xA= A, 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}} + gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE= , 0x5F, 0x4C, 0x8D, 0xF5}} + gWatchDogConfigGuid =3D {0x940EC076, 0x04AF, 0x45DA, {0xAF, 0xFA, 0x6A= , 0xEF, 0xDB, 0x2B, 0x86, 0x55}} + gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0x= F7, 0x5C, 0x4B, 0xE1, 0xE3}} + gHsuartConfigGuid =3D {0xEA329E4E, 0x1725, 0x43E0, {0xBA, 0x69, 0x67, 0= xA3, 0x76, 0x73, 0x45, 0x16}} + gHsioPcieConfigFIAWM20Guid =3D {0x92cd256c, 0xdd71, 0x4707, {0xad, 0x7= a, 0x87, 0xb3, 0xfd, 0x70, 0x08, 0x94}} + gAdrConfigGuid =3D {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xC= F, 0x97, 0x39, 0x0C, 0x65}} + gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6= , 0x56, 0x10, 0xF9, 0x86}} + gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69,= 0x43, 0xF3, 0x38, 0x31, 0x4D}} + gScsInfoHobGuid =3D {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA= , 0xE2, 0x99, 0x78, 0xB2}} + gUsb2PhyConfigGuid =3D {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC,= 0x68, 0x2D, 0xAE, 0xD3, 0xF2}} + gUsb3HsioConfigGuid =3D {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69= , 0xF9, 0xB1, 0xAC, 0x40, 0xD5}} + gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE= , 0x5F, 0x4C, 0x8D, 0xF5}} + gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1, = 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }} + gRcPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0x= d0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gSataControllerDriverGuid =3D { 0xbb929da9, 0x68f7, 0x4035, { 0xb2, 0x2c= , 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 }} + gPchInitVariableGuid =3D { 0xe6c2f70a, 0xb604, 0x4877, { 0x85, 0xba, 0xd= e, 0xec, 0x89, 0xe1, 0x17, 0xeb }} + gPchS3ImageGuid =3D { 0x271dd6f2, 0x54cb, 0x45e6, { 0x85, 0x85, 0x8c, 0x= 92, 0x3c, 0x1a, 0xc7, 0x6 }} + gEfiSmbusArpMapGuid =3D { 0x707be83e, 0x0bf6, 0x40a5, { 0xbe, 0x64, 0x34= , 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }} + mPchSataRsteProtocolGuid =3D { 0x3ea94650, 0xfc5b, 0x11e1, {0xa2, 0x1f, = 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}} + mPchSataRstProtocolGuid =3D { 0xfc5f2e00, 0xfc68, 0x11e1, {0xa2, 0x1f, 0= x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}} + gPchInitPeiVariableGuid =3D { 0xa31b27a4, 0xcae6, 0x48ff, {0x8c, 0x5a, 0= x29, 0x42, 0x21, 0xe6, 0xf3, 0x89 }} + gChipsetInitInfoHobGuid =3D { 0xc1392859, 0x1f65, 0x446e, {0xb3, 0xf5, 0= x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4}} + gPchOemSmmGuid =3D { 0xc0cfaf36, 0x4296, 0x40ba, {0xa9, 0xf1, 0x77, 0x10= , 0x9b, 0x91, 0xce, 0x19}} + gPchPowerCycleResetGuid =3D { 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd= , 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 }} + gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x= 18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} + gPchGlobalResetWithEcGuid =3D { 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x= 3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 }} +#S3 add + gPchS3CodeInLockBoxGuid =3D { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4,= 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}} + gPchS3ContextInLockBoxGuid =3D { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f= , 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}} +#S3 add +# gMeBiosExtensionSetupGuid =3D { 0x1bad711c, 0xd451, 0x4241, { 0xb1= , 0xf3, 0x85, 0x37, 0x81, 0x2e, 0xc, 0x70 } } // SERVER_BIOS_FLAG +# gAmtForcePushPetPolicyGuid =3D { 0xacc8e1e4, 0x9f9f, 0x4e40, { 0xa5= , 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 } } // SERVER_BIOS_FLAG + gEfiAcpiVariableGuid =3D { 0xaf9ffd67, 0xec10, 0x488a, { 0x9d, 0= xfc, 0x6c, 0xbf, 0x5e, 0xe2, 0x2c, 0x2e }} + gEfiCommonPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0= xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gPchPolicyHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0= x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} + gPchChipsetInitHobGuid =3D { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0= xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }} + gWdtHobGuid =3D { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0= xb7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }} + gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gPchPsfErrorHobGuid =3D { 0x9ee875f4, 0xa463, 0x4b29, { 0x88, 0= x79, 0x11, 0x2a, 0x4d, 0x05, 0x47, 0x7f }} + gHdAudioPreMemConfigGuid =3D { 0xD38F1E2B, 0x21B3, 0x43D1, { 0x9F, 0= xA8, 0xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88 }} + gIshPreMemConfigGuid =3D { 0x7C24E649, 0xC1F0, 0x4CF9, { 0x87, 0= x96, 0xE7, 0xA0, 0xEE, 0x34, 0x43, 0xF8 }} + + gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0= xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }} + +## +## PreMem Performance +## + gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, = 0x3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}} + gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, = 0x29, 0x0B, 0x38, 0xC5, 0x32, 0x25}} + gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, = 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}} + gPlatformGpioConfigGuid =3D {0xd66acbe3, 0x3293, 0x4ba1, {0xb0, 0x0b, = 0xb3, 0x8f, 0x64, 0x8d, 0x8d, 0x5e}} +# SouthCluster End +# + + gSocketPkgFpgaGuid =3D { 0x624b948f, 0x= 6eba, 0x4dfd, { 0x9d, 0xda, 0x10, 0xb0, 0x07, 0x3a, 0x37, 0x35 } } # {624B= 948F-6EBA-4DFD-9DDA-10B0073A3735} + gFpgaSocketVariableGuid =3D { 0x75839b0b, 0x= 0a99, 0x4233, { 0x8a, 0xa4, 0x38, 0x66, 0xf6, 0xce, 0xf4, 0xb3 } } # {7583= 9B0B-0A99-4233-8AA4-3866F6CEF4B3} + gFpgaSocketPkgListGuid =3D { 0xa3922b1a, 0x= 35e4, 0x4132, { 0x9c, 0xed, 0x91, 0xd3, 0x8d, 0x71, 0x71, 0xd8 } } # {A392= 2B1A-35E4-4132-9CED-91D38D7171D8} + gFpgaFormSetGuid =3D { 0x22819110, 0x= 7F6F, 0x4852, { 0xB4, 0xBB, 0x13, 0xA7, 0x70, 0x14, 0x9B, 0x0C } } # {2281= 9110-7F6F-4852-B4BB-13A770149B0C} + gFpgaSocketHobGuid =3D { 0xd759c710, 0x= 49ea, 0x4d26, { 0x9f, 0x7c, 0xde, 0x10, 0x64, 0x87, 0x6e, 0x2f } } # {D759= C710-49EA-4D26-9F7C-DE1064876E2F} + gFpgaSocketBbsGbeGuid =3D { 0x28b225ef, 0x= e6b1, 0x4dc0, { 0x8d, 0x4d, 0x49, 0xef, 0xc8, 0x57, 0xcc, 0xdf } } # {28B2= 25EF-E6B1-4dc0-8D4D-49EFC857CCDF} + gFpgaSocketBbsPcieGuid =3D { 0xe4d662cd, 0x= 7ccb, 0x4cb5, { 0xae, 0xce, 0x4e, 0xea, 0x39, 0x8f, 0xf8, 0xe4 } } # {E4D6= 62CD-7CCB-4cb5-AECE-4EEA398FF8E4} + gFpgaSocketN4PeGuid =3D { 0x78d87f9a, 0x= 321e, 0x4a07, { 0x87, 0x5f, 0x8d, 0x83, 0xa3, 0xd0, 0x6e, 0x59 } } # {78D8= 7F9A-321E-4a07-875F-8D83A3D06E59} + gFpgaErrorRecordGuid =3D { 0x09fdcb1e, 0x= e08b, 0x4b64, { 0x89, 0x0c, 0x70, 0xe3, 0x17, 0x4b, 0xe0, 0x7a } } + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } + gEfiAfterPlatformLocksEventGuid =3D { 0x1c5fdaf2, 0x= 9fb3, 0x431b, { 0x8e, 0xcd, 0xb7, 0xd3, 0x5c, 0xbe, 0xfa, 0xe9 } } + gEfiPlatformTxtDeviceMemoryGuid =3D { 0x73d1d476, 0x= a7c9, 0x4efd, { 0x8f, 0x8b, 0xd5, 0x32, 0xef, 0x38, 0x17, 0x08 } } + gEmulationHobGuid =3D { 0xbea8d1f4, 0x= c2fd, 0x4d74, { 0xbd, 0xf2, 0xb7, 0xb5, 0x40, 0x34, 0xd7, 0xc0 } } # {BEA8= D1F4-C2FD-4d74-BDF2-B7B54034D7C0} + gEmulationDfxVariableGuid =3D { 0x41266ead, 0x= 701c, 0x461f, { 0xa6, 0xb1, 0x42, 0xcd, 0x38, 0x7d, 0x1a, 0x6e } } # {41266= EAD-701C-461f-A6B1-42CD387D1A6E} + gEmulationFormSetGuid =3D { 0x52b3b56e, 0x= e716, 0x455f, { 0xa5, 0xe3, 0xb3, 0x14, 0xf1, 0x8e, 0x6c, 0x5d } } # {52B3= B56E-E716-455f-A5E3-B314F18E6C5D} + gCsrPseudoOffsetTableGuid =3D { 0x5921E6F4, 0x= D672, 0x45CA, { 0xBF, 0xF1, 0x34, 0x47, 0xA4, 0x1E, 0x21, 0x4A } } + gEfiKtiEparamInfoGuid =3D { 0xaac08905, 0x= 6700, 0x48aa, { 0xb8, 0x8c, 0xca, 0x1e, 0x53, 0xc5, 0x5d, 0xa0 } } # {AAC0= 8905-6700-48aa-B88C-CA1E53C55DA0} + gIioSiPolicyHobGuid =3D { 0x353bb17b, 0x= 74ac, 0x4895, { 0xb4, 0x61, 0x2c, 0x8c, 0x97, 0x68, 0x30, 0xe6 } } + gIioPcieConfigGuid =3D { 0x5cd68841, 0x= 16c0, 0x4f8e, { 0xba, 0xb, 0x94, 0x7c, 0xa3, 0x47, 0xb7, 0xa0 } } + gPeiPciMmioResMapHobGuid =3D { 0xd8c98608, 0x= 40c4, 0x4ba6, { 0x85, 0x04, 0x1d, 0x23, 0xf2, 0xa5, 0x4b, 0x4e } } # {d8c9= 8608-40c4-4ba6-8504-1d23f2a54b4e} + gImr2BaseAddressHobGuid =3D { 0xea9184fe, 0x= 3bec, 0x436d, { 0x92, 0x14, 0x3f, 0x8c, 0xb5, 0x64, 0xdf, 0xfe } } # {EA91= 84FE-3BEC-436d-9214-3F8CB564DFFE} + +## +## DMA Protection Event GUID +## + gEfiDmaProtectionDisablingEventGroupGuid =3D { 0x05e32339, 0x= 92d4, 0x440e, { 0xb3, 0xb3, 0x9c, 0x9c, 0xbe, 0x79, 0xd3, 0x7f } } # {05E3= 2339-92D4-440e-B3B3-9C9CBE79D37F} + + +## +## Me +## + gAmtForcePushPetPolicyGuid =3D { 0xacc8e1e4, 0x= 9f9f, 0x4e40, { 0xa5, 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 } } + gAmtForcePushPetVariableGuid =3D { 0xd7ac94af, 0x= a498, 0x45ec, { 0xbf, 0xa2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b } } + gMeBiosExtensionSetupGuid =3D { 0xaf013532, 0x= c828, 0x4fbd, { 0x20, 0xae, 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e } } + gMePlatformReadyToBootGuid =3D { 0x03fdf171, 0x= 1d67, 0x4ace, { 0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74 } } + gMeSsdtAcpiTableStorageGuid =3D { 0x9a8f82d5, 0x= 39b1, 0x48da, { 0x92, 0xdc, 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6 } } + gAmtPetQueueHobGuid =3D { 0xca0801d3, 0x= afb1, 0x4dec, { 0x9b, 0x65, 0x93, 0x65, 0xec, 0xc7, 0x93, 0x6b } } + gAmtForcePushPetHobGuid =3D { 0x4efa0db6, 0x= 26dc, 0x4bb1, { 0xa7, 0x6f, 0x14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c } } + gMeDataHobGuid =3D { 0x1e94f097, 0x= 5acd, 0x4089, { 0xb2, 0xe3, 0xb9, 0xa5, 0xc8, 0x79, 0xa7, 0x0c } } + gPciImrHobGuid =3D { 0x49b1eac3, 0x= 0cd6, 0x451e, { 0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35, 0x86 } } + gTpm2AcpiTableStorageGuid =3D { 0x7d279373, 0x= eecc, 0x4d4f, { 0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a } } + gMeBiosPayloadHobGuid =3D { 0x992c52c8, 0x= bc01, 0x4ecd, { 0x20, 0xbf, 0xf9, 0x57, 0x16, 0x0e, 0x9e, 0xf7 } } + gEfiTouchPanelGuid =3D { 0x91b1d27b, 0x= e126, 0x48d1, { 0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8, 0x83, 0x62 } } + gMeFwHobGuid =3D { 0x52885e62, 0x= 4c4d, 0x9546, { 0x2d, 0xba, 0x2a, 0x84, 0x89, 0xee, 0xa8, 0xa3 } } + gMePeiPreMemConfigGuid =3D { 0x67ed113b, 0x= d4ab, 0x43f5, { 0x9c, 0x3c, 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c } } + gMePeiConfigGuid =3D { 0x9bad5628, 0x= 657b, 0x48e3, { 0xb1, 0x11, 0xc3, 0xb9, 0xeb, 0xea, 0xee, 0x17 } } + gMeDxeConfigGuid =3D { 0xad08bacc, 0x= 4906, 0x4d9b, { 0xbe, 0xd1, 0x81, 0xa5, 0x2c, 0x13, 0xdb, 0xf8 } } + gAmtPeiConfigGuid =3D { 0x7254546a, 0x= ace3, 0x4a32, { 0x9a, 0xc2, 0xf0, 0xcc, 0x28, 0x4e, 0x1e, 0x4d } } + gAmtDxeConfigGuid =3D { 0x3f12ab6b, 0x= b04d, 0x4824, { 0xbf, 0xb6, 0x3e, 0xe7, 0x5d, 0x02, 0x0b, 0x84 } } + gIvmProtocolGuid =3D { 0x3C4852D6, 0x= D47B, 0x4F46, { 0xB0, 0x5E, 0xB5, 0xED, 0xC1, 0xAA, 0x44, 0x0E } } + gSdmProtocolGuid =3D { 0xDBA4D603, 0x= D7ED, 0x4931, { 0x88, 0x23, 0x17, 0xAD, 0x58, 0x57, 0x05, 0xD5 } } + gRtmProtocolGuid =3D { 0x5565A099, 0x= 7FE2, 0x45C1, { 0xA2, 0x2B, 0xD7, 0xE9, 0xDF, 0xEA, 0x9A, 0x2E } } + gSvmProtocolGuid =3D { 0xF47ACC04, 0x= D94B, 0x49CA, { 0x87, 0xA6, 0x7F, 0x7D, 0xC0, 0x3F, 0xBA, 0xF3 } } + gMeEopDoneHobGuid =3D { 0x247323af, 0x= c8f1, 0x4b8c, { 0x90, 0x87, 0xaa, 0x4b, 0xa7, 0xb7, 0x6d, 0x6a } } + gMePreMemPolicyHobGuid =3D { 0xe6de74a5, 0x= 021b, 0x4f78, { 0xa3, 0xcd, 0x34, 0xd6, 0x7e, 0xe4, 0x82, 0xbf } } + gMePolicyHobGuid =3D { 0x0341cf17, 0x= bc8f, 0x4a20, { 0xac, 0x28, 0x6c, 0x3c, 0x32, 0x4c, 0xd4, 0x17 } } + gAmtPolicyHobGuid =3D { 0x703eb2cd, 0x= 5ca8, 0x4233, { 0x9d, 0xa3, 0x0d, 0x2d, 0x57, 0xe6, 0x73, 0x34 } } + gAmtMebxDataGuid =3D { 0x912e1538, 0x= 371d, 0x4ea6, { 0xa8, 0x41, 0xd7, 0x6a, 0x08, 0x93, 0x3a, 0x70 } } + + gEfiMeRcVariableGuid =3D { 0x2b26358d, 0x= f899, 0x41c4, { 0x9b, 0xc2, 0x82, 0xa3, 0x38, 0xb9, 0x93, 0xd8 }} + gSpsInfoHobGuid =3D { 0x489d2a71, 0x= ba4a, 0x444c, { 0x9f, 0xe2, 0xa6, 0xb7, 0xe5, 0xcd, 0x78, 0x47 }} + gEfiSpsAcpiTableLocatorGuid =3D { 0x4896840D, 0x= 46BB, 0x412B, { 0xA3, 0x0A, 0xA6, 0x2A, 0xBF, 0xB3, 0x68, 0x2F }} + gIccGuid =3D { 0x64192dca, 0x= d034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 }} + gEfiMePkgTokenSpaceGuid =3D { 0x731d14ec, 0x= 7f7c, 0x4403, { 0x8c, 0x02, 0x96, 0xac, 0x8c, 0x33, 0x5c, 0x2b }} + gConsoleLockGuid =3D { 0x368cda0d, 0x= cf31, 0x4b9b, { 0x8c, 0xf6, 0xe7, 0xd1, 0xbf, 0xff, 0x15, 0x7e }} + gMeInfoSetupGuid =3D { 0x78259433, 0x= 7b6d, 0x4db3, { 0x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d }} + gMeSetupVariableGuid =3D { 0x5432122d, 0x= d034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 }} + gMeTypeHobGuid =3D { 0xc0bc8ed5, 0x= 078c, 0x49c7, { 0x9c, 0xf9, 0xf8, 0x73, 0xff, 0xe5, 0x50, 0x81 }} + gAmtConsoleVariableGuid =3D { 0xd9aaf1e5, 0x= cd14, 0x4312, { 0x9c, 0xa4, 0x85, 0xc3, 0x0a, 0xde, 0x43, 0xe8 }} + gMeUefiFwHealthStatusHobGuid =3D { 0xa9bac5d8, 0x= 27a9, 0x4a32, { 0x9c, 0xda, 0xd3, 0xfb, 0x9d, 0x93, 0xac, 0x65 }} + gMeUmaInfoHobGuid =3D { 0xf70269e6, 0x= c201, 0x4d18, { 0xb7, 0x4d, 0xb8, 0x32, 0x1e, 0x3a, 0xff, 0xdc }} + + gSpsPeiConfigGuid =3D { 0x027be940, 0x= bd58, 0x48f4, { 0x80, 0x19, 0x34, 0xc5, 0xee, 0x79, 0xb8, 0xda }} + gSpsDxeConfigGuid =3D { 0xf9373326, 0x= da54, 0x4e31, { 0x9a, 0x08, 0x06, 0x7d, 0xcb, 0x06, 0x16, 0xbd }} + gSpsPolicyHobGuid =3D { 0xc87d4e27, 0x= 8023, 0x4a7e, { 0x8e, 0xc3, 0xa6, 0x3e, 0x3e, 0xb2, 0x94, 0xdc }} + gSpsSmmWatchdogGuid =3D { 0xf7ec1c4b, 0x= 1683, 0x403b, { 0xa8, 0x76, 0xfd, 0x3b, 0x13, 0x0f, 0x1b, 0x55 }} + +## +## IE +## + gEfiIeRcVariableGuid =3D { 0xd8b85944, 0x= 13b2, 0x41f9, { 0x85, 0xc6, 0xa0, 0xb1, 0x33, 0x78, 0x3e, 0x40 }} + gIeHobGuid =3D { 0x081077fa, 0x= 577d, 0x43b8, { 0xa8, 0xac, 0x9e, 0x0d, 0x31, 0x65, 0xf4, 0xee }} + + gUboxIpInterfaceCpuGuid =3D { 0xfedb4f83, 0x= 3be3, 0x44b2, { 0x8d, 0x29, 0x72, 0xad, 0xd0, 0xb6, 0x3c, 0x18 }} + gUboxIpInterfacePcieGen4Guid =3D { 0x32c49b21, 0x= d303, 0x4cfe, { 0xb7, 0xf5, 0xa1, 0x5f, 0x8f, 0x65, 0xff, 0x6e }} + + gKtiIpInterfaceCpuGuid =3D { 0xCC75DACB, 0x= A115, 0x4FAD, { 0xA7, 0xC6, 0x63, 0x0D, 0xC9, 0xA3, 0x62, 0xB7 }} + gKtiIpInterfacePcieGen4Guid =3D { 0xe899d31e, 0x= aff8, 0x49cb, { 0x8c, 0x1d, 0x58, 0x94, 0x3b, 0x3a, 0x59, 0x72 }} + + gPcuIpInterfaceCpuGuid =3D { 0x86b9e6bc, 0x= acb0, 0x44cd, { 0xa4, 0xb0, 0xda, 0x8d, 0x7d, 0xba, 0xb9, 0xcc }} + gPcuIpInterfacePcieGen4Guid =3D { 0x82682b43, 0x= eedb, 0x49e8, { 0xa2, 0x30, 0xfa, 0x15, 0x36, 0x52, 0x6a, 0x2a }} + + gIioIpInterfaceCpuGuid =3D { 0x96e629a1, 0x= 4f87, 0x434c, { 0xac, 0xa3, 0xef, 0x27, 0xca, 0x1a, 0x5f, 0x5a }} + gIioIpInterfacePcieGen4Guid =3D { 0x0c343cae, 0x= 84f7, 0x4062, { 0xa5, 0x17, 0x1d, 0x5f, 0xdb, 0xc8, 0x5c, 0xa5 }} + + gChaIpInterfaceCpuGuid =3D { 0xaa83b114, 0x= b7c9, 0x4cfa, { 0xb9, 0x8e, 0x8d, 0x7a, 0x26, 0xbb, 0x8c, 0x69 }} + gChaIpInterfacePcieGen4Guid =3D { 0xe2e90cf1, 0x= 214c, 0x469d, { 0xb5, 0xcf, 0xc7, 0xb4, 0x86, 0x7f, 0xf1, 0xf8 }} + + gM2UPcieIpInterfaceCpuGuid =3D { 0x793a789f, 0x= 9764, 0x48fd, { 0xb8, 0xc9, 0xac, 0xdd, 0xfa, 0x5b, 0x4e, 0x26 }} + gM2UPcieIpInterfacePcieGen4Guid =3D { 0x5032faf9, 0x= 6c56, 0x4941, { 0x94, 0x4d, 0x1f, 0xe7, 0x63, 0xe6, 0xab, 0x5f }} + + gKtiSimHelpInterfaceCpuGuid =3D { 0xf2231017, 0x= dad7, 0x4697, { 0xaa, 0xb7, 0xd8, 0x2c, 0x48, 0x4f, 0xe5, 0x7f }} + gKtiSimHelpInterfacePcieGen4Guid =3D { 0x429d26f3, 0x= 8a2d, 0x4fba, { 0xbf, 0x12, 0x8d, 0x9d, 0xe4, 0xef, 0xf9, 0x6d }} + + gPcuMailBoxIpInterfaceCpuGuid =3D { 0x52ee6a0d, 0x= 2c64, 0x4865, { 0xa8, 0xf5, 0x2c, 0x75, 0x81, 0xf7, 0xf9, 0x2a }} + gPcuMailBoxIpInterfacePcieGen4Guid =3D { 0xb096b416, 0x= 520a, 0x42f0, { 0xa4, 0xb3, 0x53, 0x1d, 0x7d, 0xd5, 0x06, 0xc5 }} + gChipsetLockDoneGuid =3D { 0x76FAEB39, 0x= 0DDA, 0x4979, { 0xBE, 0x7B, 0x47, 0x41, 0x05, 0x05, 0x17, 0x81 }} + + gFpgaIpInterfaceGuid =3D { 0x69FC448A, 0x= 28FC, 0x40E3, { 0xAB, 0x2A, 0x70, 0x22, 0xC4, 0x36, 0xCF, 0xED }} + gMsmIpInterfaceCpuGuid =3D { 0x6ebabfae, 0x= cfd2, 0x4fac, { 0x96, 0xa6, 0x8b, 0x2c, 0x0f, 0xc3, 0x08, 0xbd }} + gSpkIpInterfaceCpuGuid =3D { 0x3edf7f6d, 0x= 2061, 0x4941, { 0xb6, 0x31, 0xdd, 0x40, 0xa0, 0xba, 0xcb, 0xad }} + gBiosDoneGuid =3D { 0xaf4c5733, 0x= f4c3, 0x48ba, { 0xa7, 0x48, 0x87, 0x3e, 0x8c, 0xee, 0xd2, 0xf4 }} + +# +# VTD HOB GUIDs Begin +# + ## HOB GUID to get memory information after MRC is done. The hob data wi= ll be used to set the PMR ranges + gVtdPmrInfoDataHobGuid =3D {0x6fb61645, 0xf= 168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } +# +# VTD HOB GUIDs End +# + +[Ppis] + +## +## MdeModulePkg +## +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0= x54, 0xd2, 0xe1, 0x32, 0x3d}} +gPeiSmmAccessPpiGuid =3D {0x268f33a9, 0xcccd, 0x48be, {0x88, 0x17, 0x86,= 0x05, 0x3a, 0xc3, 0x2e, 0xd6}} +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7= , 0x43, 0x05, 0xce, 0x74, 0xc5}} + + gPeiBaseMemoryTestPpiGuid =3D { 0xb6ec423c, 0x= 21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 }} + gPeiPlatformMemorySizePpiGuid =3D { 0x9a7ef41e, 0x= c140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 }} + gEfiPeiMpServicesPpiGuid =3D { 0xee16160a, 0x= e8be, 0x47a6, { 0x82, 0x0a, 0xc6, 0x90, 0x0d, 0xb0, 0x25, 0x0a }} + gSgxInitPpiGuid =3D { 0xD8163BA4, 0x= EFA8, 0x411E, { 0xA0, 0x32, 0x05, 0x0D, 0x56, 0xE9, 0xAF, 0x74 }} + + gEndOfSiInitPpiGuid =3D { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E= , 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} + gMeBeforeDidSentPpiGuid =3D {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5, 0x= 5e, 0xf6, 0xcd, 0x6e, 0x4c, 0x87}} + +## +## Common +## + gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0= x84, 0x8c, 0x5e, 0x86, 0x70}} + gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x9= 7, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} + gPeiOemIioHooksPpiGuid =3D { 0x5265657a, 0xbfac, 0x468e, { 0xae,= 0x81, 0xc, 0x40, 0x7a, 0x1, 0xec, 0x37 }} + +# +# KTI RC +# + gEfiAfterKtiRcGuid =3D { 0x6f079b18, 0x0591, 0x4554, { 0xbb, = 0x8a, 0xfb, 0x95, 0xb1, 0xa5, 0x3f, 0x6b }} + +# +# Security +# + gSecurityAppSgx3v0PpiGuid =3D { 0x4358eeb8, 0xbebf, 0x4f33, { = 0xb5, 0xe7, 0x3b, 0xcb, 0x75, 0xb7, 0xc2, 0x1c }} + gSecurityFruCpuFeatureSgx3v0PpiGuid =3D { 0xa56c1a20, 0x9011, 0x4e1c, { = 0x8d, 0x8a, 0x31, 0xff, 0x0b, 0xdf, 0x6c, 0x7d }} + +# +# SouthCluster +# + gPchPmcXramOffsetDataPpiGuid =3D { 0xc1392859, 0x1f65, 0x446e, { 0xa3, = 0xf6, 0x85, 0x36, 0xfc, 0xc7, 0xd1, 0xc4 }} + gPchPlatformPolicyPpiGuid =3D { 0xdfe2b897, 0xe8e, 0x4926, { 0xbc, = 0x69, 0xe5, 0xed, 0xd3, 0xf9, 0x38, 0xe1 }} + gPchIpInfoPpiGuid =3D { 0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, = 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d, 0xa5 }} + gPeiUsbControllerPpiGuid =3D { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, = 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }} + gPchUsbPolicyPpiGuid =3D { 0xc02b0573, 0x2b4e, 0x4a31, { 0xa3, = 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c }} + gPchInitPpiGuid =3D { 0x511e0280, 0x83ae, 0x4a21, { 0xbd, = 0x57, 0x57, 0xe3, 0xa4, 0x93, 0x12, 0x17 }} + gWdtPpiGuid =3D { 0xF38D1338, 0xAF7A, 0x4FB6, { 0x91, = 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D }} + gPchDmiTcVcMapPpiGuid =3D { 0xed097352, 0x9041, 0x445a, { 0x80, = 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 }} + gPeiSmbusPolicyPpiGuid =3D { 0x63b6e435, 0x32bc, 0x49c6, { 0x81, = 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }} + gPchResetCallbackPpiGuid =3D { 0x17865dc0, 0xb8b, 0x4da8, { 0x8b, = 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d }} + gPchResetEndOfPeiTypeGuid =3D { 0x330d4002, 0xe366, 0x4272, { 0xb5, = 0xdd, 0x41, 0x61, 0x56, 0xb0, 0x5d, 0x20 }} + gPchPeiInitDonePpiGuid =3D { 0x1edcbdf9, 0xffc6, 0x4bd4, { 0x94, = 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 }} + gPchResetPpiGuid =3D { 0x433e0f9f, 0x5ae, 0x410a, { 0xa0, = 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac }} + gPchHdaVerbTablePpiGuid =3D { 0x220307a4, 0x3670, 0x42a5, { 0xaa, = 0x1, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gPchPcieDeviceTablePpiGuid =3D { 0xaf4a1998, 0x4949, 0x4545, { 0x9c, = 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56 }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x2096, 0x4283, { 0x9D, = 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gSaPlatformPolicyPpiGuid =3D { 0x573eaf99, 0xf445, 0x46b5, { 0xa5, = 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 }} + gPeiSmmControlPpiGuid =3D { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, = 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + gPchHsioPtssTablePpiGuid =3D { 0x220307a4, 0x3671, 0x42b5, { 0xaa, = 0x02, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gDirtyWarmResetSignalGuid =3D { 0x24b9a592, 0x4cfc, 0x4c8f, { 0x86, = 0xf4, 0x87, 0x28, 0x2d, 0x7f, 0x9e, 0x9c }} + gDirtyWarmResetGuid =3D { 0xe60fe263, 0xac2b, 0x43d6, { 0xb3, = 0xc7, 0x0d, 0x9d, 0xdc, 0x5a, 0x99, 0x1c }} + gPmcDwrPreMemConfigGuid =3D { 0x1fb7cf2c, 0xfe7c, 0x40f7, { 0x90, = 0xf9, 0x28, 0xdd, 0x63, 0x28, 0xae, 0x1a }} + gPchSpiPpiGuid =3D { 0xdade7ce3, 0x6971, 0x4b75, { 0x82, = 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d }} + gPchHsioChipsetInitSusTblDataPpiGuid =3D { 0x97ed4e5d, 0x01a5, 0x4a3c, {= 0xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }} + gPchPostMemoryConfigurationDonePpi =3D { 0x68607f46, 0xad96, 0x4364, { 0= xb1, 0x83, 0x4e, 0x6d, 0x98, 0xed, 0x79, 0x7b }} +# +# SouthCluster End +# + gFpgaInitPpiGuid =3D { 0x325e1442, 0x9be1, 0x498b, { 0xb0, = 0x07, 0xbf, 0x4c, 0x38, 0xbd, 0xb0, 0xec }} # {325E1442-9BE1-498b-B007-BF4= C38BDB0EC} + gPeiTxtScleanPpiGuid =3D { 0x4d5640e5, 0x2702, 0x4df8, { 0x88, = 0xf4, 0x56, 0x48, 0x86, 0xfc, 0x43, 0xdc }} + gIioSiPolicyPpiGuid =3D { 0xa6231b31, 0xd78c, 0x4a32, { 0x96, = 0x15, 0x56, 0x6c, 0xb6, 0xd1, 0xb1, 0xd7 }} + gIioPolicyPpiGuid =3D { 0x7960448a, 0x39ab, 0x4808, { 0xb0, = 0xf6, 0x5f, 0xe0, 0x9f, 0x81, 0x6d, 0xe0 }} + gIioEarlyInitSignalPpiGuid =3D { 0x0f6539bb, 0x236d, 0x4f80, { 0x8c, = 0x1e, 0x5a, 0x7e, 0x8f, 0x00, 0xd1, 0x30 }} # {0F6539BB-236D-4f80-8C1E-5A7= E8F00D130} + gUpiSiPolicyPpiGuid =3D { 0x87cce352, 0xf86e, 0x4ee8, { 0x89, = 0xee, 0x31, 0xc9, 0x85, 0x7d, 0x61, 0x99 }} + gReferenceCodePolicyPpiGuid =3D { 0x6f39dbf1, 0x853f, 0x4545, { 0xad, = 0xb1, 0x30, 0x15, 0xd9, 0x69, 0x4a, 0xf9 }} # {6f39dbf1-853f-4545-adb1-301= 5d9694af9} + gRasRcPolicyPpiGuid =3D { 0xfbceb643, 0xe18b, 0x4ade, { 0x9d, = 0x14, 0x9f, 0xf0, 0x5c, 0x14, 0xff, 0x5c }} + +# +# Me +# + gAmtStatusCodePpiGuid =3D { 0xca18955b, 0x= 4ee9, 0xd113, { 0xde, 0x06, 0x62, 0xad, 0xc2, 0x7f, 0x23, 0x7e } } + gHeciPpiGuid =3D { 0xd14319e2, 0x= 407a, 0x9580, { 0x8d, 0xe5, 0x51, 0xa8, 0xff, 0xc6, 0xd7, 0xd7 } } + gMbpSensitivePpiGuid =3D { 0xed7c9ce9, 0x= 5912, 0x4807, { 0xec, 0x90, 0x22, 0x18, 0xbc, 0x7b, 0xfc, 0x6c } } + gHeci3IntegratedTouchControllerGuid =3D { 0x3e8d0870, 0x= 271a, 0x4208, { 0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04 } } + gMeDidSentPpiGuid =3D { 0x45dc3106, 0x= ef67, 0x4c71, { 0xb0, 0xf0, 0x97, 0x15, 0x9c, 0x7d, 0xbb, 0x7c } } + + gPeiHeci2PpiGuid =3D { 0xEE0EA811, 0x= FBD9, 0x4777, { 0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74 }} + gPlatformMeHookPpiGuid =3D { 0xe806424f, 0x= d425, 0x4b1a, { 0xbc, 0x26, 0x5f, 0x69, 0x03, 0x89, 0xa1, 0x5a }} + gMeUmaPpiGuid =3D { 0x0100c1c8, 0x= 61d9, 0x498d, { 0xa9, 0xe2, 0x27, 0xe4, 0x92, 0xbe, 0x0e, 0xac }} + gSpsPolicyPpiGuid =3D { 0xcefb6938, 0x= 7fae, 0x4d54, { 0xbb, 0xe3, 0xe6, 0xf2, 0xf8, 0x43, 0x32, 0x72 }} + gMePolicyPpiGuid =3D { 0x1c46d34a, 0x= 4163, 0x02dd, { 0x56, 0x69, 0x2d, 0xa7, 0xca, 0x93, 0xeb, 0xf3 }} + gAmtPolicyPpiGuid =3D { 0x2549016d, 0x= 2b17, 0x4d00, { 0xb5, 0xa4, 0x1d, 0x44, 0x3a, 0x01, 0x38, 0xf8 }} + gSpsHwChangePpiGuid =3D { 0x6b30ce48, 0x= c7c7, 0x4aab, { 0x89, 0x47, 0xd9, 0xcb, 0xbe, 0xac, 0x28, 0x38 }} +# +# IE +# + gPeiIeHeciPpiGuid =3D { 0xaa40440f, 0x= d572, 0x48f9, { 0xb8, 0x24, 0x35, 0xb7, 0x7d, 0xf2, 0x63, 0x32 }} + gPeiIePlatformPolicyPpiGuid =3D { 0x8f685891, 0x= 4e6f, 0x445c, { 0xbb, 0x9e, 0xe5, 0x7a, 0x28, 0xfa, 0x53, 0xa0 }} + +# +# VTD PPIs Begin +# + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0x= f191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } +# +# VTD PPIs End +# + +[Protocols] + gEfiIioUdsProtocolGuid =3D { 0xa7ced760, 0x= c71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb } } + gEfiIioSystemProtocolGuid =3D { 0xddc3080a, 0x= 2740, 0x4ec2, { 0x9a, 0xa5, 0xa0, 0xad, 0xef, 0xd6, 0xff, 0x9c } } + gEfiCrystalRidgeGuid =3D { 0x22b5fc7e, 0x= 4ea8, 0x480a, { 0x91, 0xb0, 0xe6, 0xe9, 0xa8, 0x49, 0x3d, 0x7f } } + gEfiCrystalRidgeSmmGuid =3D { 0x558d5f05, 0x= cd51, 0x48ee, { 0xa3, 0xd2, 0x76, 0xba, 0xa0, 0x7c, 0x8e, 0xa0 } } + gJedecNvdimmSmmProtocolGuid =3D { 0xf47ef644, 0x= 01f5, 0x4ee3, { 0xb0, 0x79, 0x4d, 0x90, 0xf4, 0x7f, 0x35, 0x95 } } + gEfiDcpmmProtocolGuid =3D { 0x25E78B4B, 0x= EEF6, 0x4FDD, { 0x9D, 0xFA, 0x07, 0x88, 0x33, 0x7F, 0x77, 0xC2 } } + gDxeEnhancedSpeedstepProtocolGuid =3D { 0x00e98021, 0x= f4fe, 0x46cc, { 0xab, 0x2d, 0x89, 0x4c, 0x37, 0x3a, 0xfa, 0x01 } } + gNgnRasProtocolGuid =3D { 0x1a2614a0, 0x= 89e7, 0x11e3, { 0x29, 0x90, 0x31, 0xd2, 0x81, 0xfe, 0xb1, 0xdc } } + gEfiRasMpLinkProtocolGuid =3D { 0x8fdc888d, 0x= 2162, 0x4971, { 0x81, 0xc2, 0x35, 0xd3, 0xa1, 0xaa, 0x50, 0x47 } } + gEfiMemRasProtocolGuid =3D { 0xa9685ab6, 0x= 97f1, 0x437e, { 0xb9, 0x0d, 0x45, 0x96, 0xac, 0xe5, 0x02, 0xf9 } } + gEfiNfitTableUpdateProtocolGuid =3D { 0x618c4d8f, 0x= b60c, 0x4da6, { 0xba, 0x3c, 0x80, 0xbe, 0x38, 0xcc, 0xd7, 0xae } } + gAcpiPcatProtocolGuid =3D { 0xb12dc6a0, 0x= 1022, 0x46b6, { 0xb9, 0x95, 0x86, 0x46, 0xad, 0x5e, 0x5e, 0xeb } } + gNfitBindingProtocolGuid =3D { 0x97B4FA0C, 0x= 4D7E, 0xC2D0, { 0x67, 0x8E, 0xFB, 0x92, 0xE9, 0x6D, 0x2C, 0xC2 } } + gCrFwActivateProtocolGuid =3D { 0x67efc0b3, 0x= 3806, 0x42cd, { 0xbd, 0x4a, 0x6a, 0x2c, 0x02, 0xac, 0x63, 0x05 } } + gEfiQuiesceProtocolGuid =3D { 0x20d6e759, 0x= 4c4a, 0x40c0, { 0x95, 0x33, 0x2b, 0xf0, 0x06, 0x68, 0x50, 0xfd } } + gEfiErrorHandlingProtocolGuid =3D { 0x3ba7e14b, 0x= 176d, 0x4b2a, { 0x94, 0x8a, 0xc8, 0x6f, 0xb0, 0x01, 0x94, 0x3c } } + gEfiGlobalNvsAreaProtocolGuid =3D { 0x074e1e48, 0x= 8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } } + gEfiHpIoxAccessGuid =3D { 0x62652b53, 0x= 79d9, 0x4cf2, { 0xb5, 0xaa, 0xad, 0x99, 0x81, 0x0a, 0x7f, 0x17 } } + gEfiCpuHotAddDataProtocolGuid =3D { 0x330be755, 0x= fbed, 0x4f18, { 0xb9, 0xa8, 0x49, 0x58, 0x56, 0xd3, 0xd7, 0xa1 } } + gEfiCpuRasProtocolGuid =3D { 0xf084ff45, 0x= f9fa, 0x4e9e, { 0x8d, 0xff, 0xe2, 0xd7, 0x80, 0xd2, 0x2c, 0xc2 } } + gEfiIioRasProtocolGuid =3D { 0x4c7e45bc, 0x= 8a23, 0x26cd, { 0x94, 0xad, 0x5d, 0x2c, 0x26, 0x3f, 0x25, 0xfe } } + gRasClvAdddcProtocol =3D { 0x20576248, 0x= c01a, 0x439d, { 0x8c, 0xd6, 0x41, 0x8e, 0xaa, 0xbe, 0x0a, 0x29 } } + gRasClvSddcProtocol =3D { 0x5dba82cc, 0x= e80d, 0x4478, { 0xa0, 0x7d, 0x39, 0x4f, 0x36, 0x2d, 0x35, 0x24 } } + gRasClvRankSparingProtocol =3D { 0xe425cf37, 0x= e55b, 0x43d7, { 0xb2, 0xc6, 0xcd, 0xb9, 0xee, 0x8d, 0x25, 0xa5 } } + gRasClvPcieErrHandProtocol =3D { 0xb2bf51e0, 0x= 6543, 0x4acb, { 0xb0, 0x9e, 0xfd, 0x82, 0x6e, 0x1a, 0xf4, 0xc0 } } + gRasClvPatrolScrubProtocol =3D { 0x17bf72a7, 0x= ba65, 0x4837, { 0x86, 0x6d, 0x97, 0x9b, 0x2f, 0x2c, 0x07, 0x5e } } + gEfiCrystalRidgeFlushNearMemoryProtocolGuid =3D { 0xb43cced6, 0x= 4c4a, 0x4588, { 0x90, 0x48, 0xb0, 0xbb, 0x2b, 0x04, 0x01, 0xec } } + gAcpiPlatformProtocolGuid =3D { 0x6dd2a163, 0x= 5247, 0x4a5f, { 0xa3, 0xf2, 0xc1, 0xd8, 0x67, 0x0a, 0x05, 0x8a } } + gSmbiosMemInfoProtocolGuid =3D { 0xAE64455C, 0x= 09D7, 0x4C3B, { 0xA8, 0x58, 0x99, 0x07, 0x3D, 0xFF, 0x6E, 0x01 } } + gDxeKtiProtocolGuid =3D { 0x76c8dfce, 0x= 9908, 0x4fc2, { 0x98, 0x2f, 0x6c, 0x3, 0x2, 0xdc, 0x2f, 0x6c } } + gSmmKtiProtocolGuid =3D { 0x7bc172e, 0x= 2a5c, 0x47b0, { 0xaa, 0xaa, 0xaa, 0xd5, 0x30, 0xb9, 0x5b, 0x4b } } + gSmmEmulationSettingProtocol =3D { 0x93e49ce5, 0x= 789e, 0x4ffe, { 0xb9, 0x3a, 0xa8, 0x09, 0xbb, 0xdd, 0x89, 0xf4 } } + gEfiNvdimmAcpiConfigProtocolGuid =3D { 0x01d1d731, 0x= 7a00, 0x48e4, { 0xb9, 0x38, 0x1a, 0xce, 0x66, 0x5d, 0xed, 0xfb } } + gEfiNvdimmSmbusSmmInterfaceProtocolGuid =3D { 0xf8f2e702, 0x= 6f42, 0x4674, { 0xbe, 0x76, 0x9a, 0xe6, 0x73, 0x4f, 0xc3, 0x3b } } # {f8f2= e702-6f42-4674-be76-9ae6734fc33b} + gEadrProtocolGuid =3D { 0xb03adf09, 0x= 3f07, 0x4d5b, { 0x80, 0x22, 0x6a, 0x21, 0x69, 0x82, 0x2a, 0xf0 } } + gEfiPciMapProtocolGuid =3D { 0xEA63B154, 0x= C1DC, 0x485F, { 0x9D, 0x9A, 0xDC, 0x8B, 0xC0, 0xD1, 0x2A, 0x2B } } + +# +# SouthCluster +# + gPchSpiProtocolGuid =3D { 0xc7d289, 0x1347, 0x4de0,= { 0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a }} + gEfiActiveBiosProtocolGuid =3D { 0xebbe2d1b, 0x1647, 0x4bda,= { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a }} + gEfiSerialGpioProtocolGuid =3D { 0xf52c3858, 0x5ef8, 0x4d41,= { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gWdtProtocolGuid =3D { 0xB42B8D12, 0x2ACB, 0x499a,= { 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x586b, 0x47c1,= { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gEfiPchS3SupportProtocolGuid =3D { 0x2224aee3, 0x8d0b, 0x480a,= { 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 }} + gEfiPchInfoProtocolGuid =3D { 0x984eb4e9, 0x5a95, 0x41de,= { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gEfiSmmSmbusProtocolGuid =3D { 0x72e40094, 0x2ee1, 0x497a,= { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc }} + gEfiSmmIchnDispatchExProtocolGuid =3D { 0x3920405b, 0xc897, 0x44da,= { 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 }} + gEfiSmmIoTrapDispatchProtocolGuid =3D { 0xdb7f536b, 0xede4, 0x4714,= { 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d }} + gPchResetCallbackProtocolGuid =3D { 0x3a3300ab, 0xc929, 0x487d,= { 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 }} + gPchResetProtocolGuid =3D { 0xdb63592c, 0xb8cc, 0x44c8,= { 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a }} + gEfiGlobalNvsAreaProtocolGuid =3D { 0x74e1e48, 0x8132, 0x47a1, = { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x2096, 0x4283,= { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gEfiPchSetTmcSrcClkProtocolGuid =3D { 0xfbaa2549, 0x53d, 0x4012, = { 0x86, 0x6c, 0x7a, 0x86, 0xcc, 0x21, 0xae, 0x21 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x586b, 0x47c1,= { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gPchInfoProtocolGuid =3D { 0x984eb4e9, 0x5a95, 0x41de,= { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gPchNvsAreaProtocolGuid =3D { 0x2E058B2B, 0xEDC1, 0x4431,= { 0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3 }} + gPchSerialIoUartDebugInfoProtocolGuid =3D { 0x2fd2b1bd, 0x0387, 0x4ec6,= { 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6 }} + gExitPmAuthProtocolGuid =3D { 0xd088a413, 0xa70, 0x4217, = { 0xba, 0x55, 0x9a, 0x3c, 0xb6, 0x5c, 0x41, 0xb3 }} + gPchSerialGpioProtocolGuid =3D { 0xf52c3858, 0x5ef8, 0x4d41,= { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gEfiLoadPeImageProtocolGuid =3D { 0x5CB5C776, 0x60D5, 0x45EE,= { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }} + gEfiSmmVariableProtocolGuid =3D { 0xed32d533, 0x99e6, 0x4209,= { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }} + gDxePchPlatformResetPolicyProtocolGuid =3D { 0x45ada968, 0xa8c5, 0x4f30,= { 0xac, 0xd4, 0xf5, 0x13, 0xbc, 0xe5, 0xb0, 0xb3 }} + gDxePchPlatformPolicyProtocolGuid =3D { 0x4b0165a9, 0x61d6, 0x4e23,= { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 }} + gEfiLegacyInterruptProtocolGuid =3D { 0x31ce593d, 0x108a, 0x485d,= { 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe }} + gEfiSmmIchnDispatchProtocolGuid =3D { 0xc50b323e, 0x9075, 0x4f2a,= { 0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc }} + gEfiLegacy8259ProtocolGuid =3D { 0x38321dba, 0x4fe0, 0x4e17,= { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }} + gPlatformEmmcInfoProtocolGuid =3D { 0xf103dd83, 0x3b17, 0x4e1e,= { 0x9b, 0x80, 0x5d, 0xcc, 0x9c, 0x59, 0x0b, 0x2f }} + gPchEmmcTuningProtocolGuid =3D { 0x10fe7e3b, 0xdbe5, 0x4cfa,= { 0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89 }} + gScsEmmcSoftwareTuningProtocolGuid =3D { 0x972215b2, 0x9616, 0x4de4,= { 0xa9, 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54 }} + gPchTcoSmiDispatchProtocolGuid =3D { 0x9E71D609, 0x6D24, 0x47FD,= { 0xB5, 0x72, 0x61, 0x40, 0xF8, 0xD9, 0xC2, 0xA4 }} + gPchPcieSmiDispatchProtocolGuid =3D { 0x3E7D2B56, 0x3F47, 0x42AA,= { 0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB }} + gPchAcpiSmiDispatchProtocolGuid =3D { 0xD52BB262, 0xF022, 0x49EC,= { 0x86, 0xD2, 0x7A, 0x29, 0x3A, 0x7A, 0x05, 0x4B }} + gPchGpioUnlockSmiDispatchProtocolGuid =3D { 0x83339EF7, 0x9392, 0x4716,= { 0x8D, 0x3A, 0xD1, 0xFC, 0x67, 0xCD, 0x55, 0xDB }} + gPchSmiDispatchProtocolGuid =3D { 0xE6A81BBF, 0x873D, 0x47FD,= { 0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93 }} + gEfiSmmIchnDispatch2ProtocolGuid =3D { 0xe0f0cc19, 0x8912, 0x4077,= { 0xbf, 0x8a, 0x6a, 0x5c, 0x27, 0xa, 0x3e, 0x65 }} + gEfiSmmIchnDispatch2ExProtocolGuid =3D { 0x8497455b, 0xb489, 0x4ac7,= { 0xbd, 0x51, 0x78, 0xdf, 0x4e, 0x1f, 0x1a, 0xcd }} + gPchEspiSmiDispatchProtocolGuid =3D { 0xB3C14FF3, 0xBAE8, 0x456C,= { 0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C }} + gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b,= { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} + gPchSataEfiLoadProtocolGuid =3D { 0xaee24780, 0x4511, 0x4f23,= { 0xa0, 0x28, 0xeb, 0x82, 0x4, 0xd4, 0x82, 0x9c }} + gPchsSataEfiLoadProtocolGuid =3D { 0x8580afee, 0x40ad, 0x4f63,= { 0xa5, 0x48, 0x3d, 0x7f, 0x4a, 0x9, 0x86, 0x7d }} + gPchSmmPeriodicTimerControlGuid =3D { 0x6906E93B, 0x603B, 0x4A0F,= { 0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB }} + gIoTrapExDispatchProtocolGuid =3D { 0x5B48E913, 0x707B, 0x4F9D,= { 0xAF, 0x2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D }} + gPchSmmSpiProtocolGuid =3D { 0x56521f06, 0xa62, 0x4822,= { 0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1 }} + gPchThermalLevelsProtocolGuid =3D { 0x813C7793, 0xD430, 0x4114,= { 0x82, 0x6C, 0x8D, 0x19, 0xEF, 0x86, 0x97, 0xF1 }} + gPchPolicyProtocolGuid =3D { 0x543d5c93, 0x6a28, 0x4513,= { 0x85, 0x9a, 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe }} + gPchSmmEadrSxDispatchProtocolGuid =3D { 0x0A97A42A, 0x6929, 0x4DE2,= { 0x91, 0xC1, 0xF2, 0xC0, 0x37, 0xBA, 0xCA, 0xA5 }} + gPchSmmEadrResetDispatchProtocolGuid =3D { 0x5D49C8BA, 0xF3D2, 0x4A3C,= { 0x99, 0x64, 0x64, 0x80, 0x43, 0x12, 0x5A, 0xD8 }} +# +# SouthCluster End +# + gRasClvMirrorFailoverProtocol =3D { 0x66bc00dc, 0x= 8557, 0x4fc1, { 0x9b, 0xec, 0x13, 0x77, 0x60, 0xe2, 0x7e, 0x96 } } + gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0x= c8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 } } + gEfiPciCallbackProtocolGuid =3D { 0x1ca0e202, 0x= fe9e, 0x4776, { 0x9f, 0xaa, 0x57, 0x0c, 0x19, 0x61, 0x7a, 0x06 } } + gSmmPseudoOffestInfoProtocol =3D { 0xB5ABF7DC, 0x= FD44, 0x45C5, { 0xAB, 0x5A, 0x0F, 0xE5, 0x0F, 0xB4, 0x84, 0xF9 } } + gDxePseudoOffestInfoProtocol =3D { 0x07E53E7B, 0x= E480, 0x480D, { 0xB7, 0x4D, 0x21, 0xAE, 0x17, 0x9B, 0x71, 0x78 } } +# +# Me +# + gAlertStandardFormatProtocolGuid =3D { 0x45de9920, 0x= cd54, 0x446a, { 0xa0, 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4 } } + gDxeAmtPolicyGuid =3D { 0x6725e645, 0x= 4a7f, 0x9969, { 0x82, 0xec, 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57 } } + gAmtReadyToBootProtocolGuid =3D { 0xcc9d5c0b, 0x= 9010, 0x45f1, { 0x99, 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77 } } + gHeciProtocolGuid =3D { 0x3c7bc880, 0x= 41f8, 0x4869, { 0xae, 0xfc, 0x87, 0x0a, 0x3e, 0xd2, 0x82, 0x99 } } + gHeciFlowProtocolGuid =3D { 0x1498d127, 0x= 123c, 0x4e52, { 0x84, 0x00, 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e } } + gMebxProtocolGuid =3D { 0x01ab1829, 0x= cecd, 0x4cfa, { 0xa1, 0x8c, 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74 } } + gDxeMePolicyGuid =3D { 0xa0b5dc52, 0x= 4f34, 0x3990, { 0xd4, 0x91, 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42 } } + gDxeSpsPolicyProtocolGuid =3D { 0x1f549fc8, 0x= 14c7, 0x4fd1, { 0xa2, 0xad, 0x42, 0x71, 0xc8, 0x8b, 0x58, 0x12 }} + gMeInfoProtocolGuid =3D { 0x7523c8e4, 0x= 4fbe, 0x9661, { 0x29, 0x96, 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b } } + gPlatformMeHookProtocolGuid =3D { 0xbc52476e, 0x= f67e, 0x4301, { 0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2 } } + gMeNvsAreaProtocolGuid =3D { 0x3bffecfd, 0x= d75f, 0x4975, { 0xb8, 0x88, 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b } } + gMePlatformGetResetTypeGuid =3D { 0xf46dd670, 0x= 36c2, 0x4437, { 0x93, 0xc5, 0x8e, 0x04, 0x65, 0x82, 0xe6, 0xc3 } } + gJhiProtocolGuid =3D { 0xccba3051, 0x= a574, 0x4f9d, { 0x96, 0xf4, 0xec, 0x0d, 0x4a, 0x87, 0xbc, 0x5a } } + gIntegratedTouchHidProtocolGuid =3D { 0x3d0479c1, 0x= 6b19, 0x4191, { 0xb8, 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55 } } + gIntegratedTouchProtocolGuid =3D { 0x2b12e46f, 0x= 3c24, 0x47ff, { 0x8b, 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42 } } + gMeEopDoneProtocolGuid =3D { 0x8d9b3387, 0x= 73db, 0x456f, { 0x88, 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09 } } + gAmtSaveMebxProtocolGuid =3D { 0x86682c04, 0x= ea42, 0x49e5, { 0x96, 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7 } } + + gSmmHeciProtocolGuid =3D { 0x7a305c6c, 0x= 61ae, 0x4bec, { 0xa7, 0xad, 0xec, 0xe3, 0xfb, 0x8f, 0xef, 0xd1 }} + gSmmMeHeci3ProtocolGuid =3D { 0x69735520, 0x= DA83, 0x444A, { 0x93, 0xDC, 0xBD, 0xDD, 0x59, 0xE5, 0x91, 0x82 }} + gActiveManagementProtocolGuid =3D { 0xd25dc167, 0x= eb6a, 0x432d, { 0x65, 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb }} + gMdesStatusCodeProtocolGuid =3D { 0xe5d0875a, 0x= f647, 0x4e16, { 0xbe, 0x4d, 0x95, 0x02, 0x40, 0x29, 0xcc, 0x44 }} + gEfiMeInfoProtocolGuid =3D { 0x11fbfdfb, 0x= 10d2, 0x43e6, { 0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a }} + gEfiAmtWrapperProtocolGuid =3D { 0x919383de, 0x= ebac, 0x4924, { 0x01, 0x94, 0x52, 0x59, 0xe0, 0x0d, 0x65, 0x7a }} + gSpsPolicyProtocolGuid =3D { 0x7316b2ac, 0x= c003, 0x42c8, { 0xb0, 0xf0, 0x88, 0x97, 0x4b, 0x1f, 0x4b, 0xbe }} + gSpsSmmHmrfpoProtocolGuid =3D { 0xeb48a372, 0x= da75, 0x4c5d, { 0xba, 0x00, 0xa7, 0x1e, 0x32, 0xe8, 0xa0, 0x8f }} + gSpsSmmHmrfpoExtProtocolGuid =3D { 0xd34faeb7, 0x= 5d40, 0x4ee1, { 0x8d, 0x04, 0xb6, 0x2a, 0xf9, 0xf0, 0xf7, 0xdf }} + gSpsRasNotifyProtocolGuid =3D { 0xb0aab2cf, 0x= d7ec, 0x4d4c, { 0xa6, 0xce, 0x39, 0x73, 0x8d, 0x0a, 0x29, 0xb4 }} + gIccOverClockingProtocolGuid =3D { 0xe1fc8377, 0x= 25a0, 0x46b9, { 0x82, 0xae, 0x07, 0x6c, 0x73, 0xc0, 0x71, 0xa9 }} + gIccDataProtocolGuid =3D { 0x346b6db3, 0x= 39a3, 0x400e, { 0x81, 0xbd, 0x21, 0x6d, 0xb5, 0x79, 0x74, 0x46 }} + gSpsSmmBiosUpdateProtocolGuid =3D { 0x0141540B, 0x= 6BC3, 0x4B38, { 0xA7, 0xAE, 0xCC, 0x71, 0x84, 0x48, 0xFE, 0x42 }} + gSpsSmmMeStorageProtocolGuid =3D { 0x1b45e3a2, 0x= e498, 0x40f3, { 0x93, 0xb9, 0xb9, 0x5b, 0x7f, 0x2b, 0xf4, 0x2e }} +# +# IE +# + gIeHeciProtocolGuid =3D { 0x03911e52, 0xb39b, 0x4e91, { 0xa5,= 0x53, 0x95, 0x80, 0x3d, 0xc8, 0xac, 0x6a }} +# +# VTD Protocols Begin +# + gEdkiiPlatformVTdPolicyProtocolGuid =3D { 0x3d17e448, 0x= 466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} +# +# VTD Protocols End +# + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x100000= 01 + gPlatformTokenSpaceGuid.PcdMultiPchEnabled |FALSE|BOOLEAN|0x100= 00003 + gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF00= 00007 +#gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF00= 0000F +#gSiPkgTokenSpaceGuid.PcdAmtEnable |FALSE|BOOLEAN|0xF00= 00010 +#gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF00= 00011 +#gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x= 00010055 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. +## +#gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 + + gPlatformTokenSpaceGuid.PcdUseRxTxMultiCastRegisters|FALSE|BOOLEAN|0x100= 00002 + + # PMC Strap Set VDM Feature switch (soft straps update for warm-reset el= imination feature) + gSiPkgTokenSpaceGuid.PcdPmcStrapSetVdmSupported|FALSE|BOOLEAN|0x0001000B + + # Change to TRUE to enable check for sample parts + # If check is enabled, BIOS will not boot on a sample part + gSiPkgTokenSpaceGuid.PcdEnableSamplePartCheck|FALSE|BOOLEAN|0x0001000C + + gSiPkgTokenSpaceGuid.PcdHardwareLocalSemaphores|FALSE|BOOLEAN|0xF0000012 + +### [PcdsFixedAtBuild, PcdsPatchableInModule] +[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic, PcdsDynamicEx] +# +# SouthCluster +# + ## From MdeModulePkg.dec + ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes = to follow ACPI specification. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 + ## Default OEM Table ID for ACPI table creation, it is "EDK2 ". + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|= 0x30001035 + ## Default OEM Revision for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001= 036 + ## Default Creator ID for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037 + ## Default Creator Revision for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x3= 0001038 + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0780|UINT16|0x00010031 + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034 + + ## + ## This PCD specifies the base address of the HPET timer. + ## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xF= ED03000 + ## + gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x000100= 57 + ## + ## This PCD specifies the base address of the IO APIC. + ## The acceptable values are 0xFECxx000. + ## + gSiPkgTokenSpaceGuid.PcdPchIoApicBaseAddress |0xFEC00000|UINT32|0x00010= 058 + + # HSIO +# +# SouthCluster End +# + +# +# VTD PCDs Begin +# + ## Error code for VTd error.

+ # EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
+ # @Prompt Error code for VTd error. + gSiPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 +# +# VTD PCDs End +# + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +# +# SouthCluster +# + gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE|BOOLEAN|0x30000018 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0|UINT8|0x30000019 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0|UINT8|0x30000020 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0|UINT8|0x30000021 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0x88880000|UINT32|0x30000007 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0x88338822|UINT32|0x30000009 + + + ## + ## PCI Express MMIO temporary region length in SEC phase. + ## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, = 0x4000000/64MB + ## + gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT3= 2|0x00200005 + # + # PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined= in SMBIOS, + # values 0-0x7F will be treated as disable FVI reporting. + # FVI structure uses it as SMBIOS OEM type to provide version informatio= n. + # + gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 + + + ## CSM Setup value + gClientCommonModuleTokenSpaceGuid.PcdCsmEnable|TRUE|BOOLEAN|0x30000036 +# +# SouthCluster End +# + + # PcdUseNvdimmFwInterface determines whether memory map code uses Intel = NVDIMM firmware mailbox interface + # to communicate with Intel NVDIMM + gSiPkgTokenSpaceGuid.PcdUseNvdimmFwInterface|TRUE|BOOLEAN|0x30000040 + +# +# VTD PCDs Begin +# + ## The mask is used to control VTd behavior.

+ # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) + # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) + # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. + # BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Pr= otection + # @Prompt The policy for VTd driver behavior. + gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002 + + ## Declares VTd PEI DMA buffer size.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI (InstallPeiMemory), the PMR alignment requirement + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size. + gSiPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|0x00000003 + + ## Declares VTd PEI DMA buffer size for S3.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirem= ent + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size for S3. + gSiPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT32|0x000000= 04 +# +# VTD PCDs End +# + +[PcdsFixedAtBuild] + gPlatformTokenSpaceGuid.PcdUboDev|0x08|UINT8|0x3000000D + gPlatformTokenSpaceGuid.PcdUboFunc|0x02|UINT8|0x3000000E + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC|UINT8|0x3000000F + gPlatformTokenSpaceGuid.PcdSecInFsp|0x0|UINT32|0x30000010 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFD00000|UINT32|= 0x2000000D + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000300000|UINT32|= 0x2000000E + gCpuUncoreTokenSpaceGuid.PcdFlashIcxFlashRegionBase|0x0000000000|UINT32|= 0x20000030 + gCpuUncoreTokenSpaceGuid.PcdFlashIcxFlashRegionSize|0x0000000000|UINT32|= 0x20000031 + gCpuUncoreTokenSpaceGuid.PcdFlashCpxFlashRegionBase|0x0000000000|UINT32|= 0x20000032 + gCpuUncoreTokenSpaceGuid.PcdFlashCpxFlashRegionSize|0x0000000000|UINT32|= 0x20000033 + gCpuUncoreTokenSpaceGuid.PcdFlashOemSecPeiRegionBase|0x0000000000|UINT32= |0x20000040 + gCpuUncoreTokenSpaceGuid.PcdFlashOemSecPeiRegionSize|0x0000000000|UINT32= |0x20000041 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000|UINT32|0x20= 00000F + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000|UINT32|0x20= 000010 + gCpuUncoreTokenSpaceGuid.PcdSecDataCacheRegionPattern|0x5AA55AA5|UINT32|= 0x20000011 + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|0xFFFB0000|UINT3= 2|0x30000004 + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize|0x00010000|UINT3= 2|0x30000005 + ## + ## PCD PcdFlashNvStorageMicrocode2Base and PcdFlashNvStorageMicrocode2Si= ze are + ## added for supporting the second microcode flash region as recovery ba= ckup. + ## Default value 0x0 which means there is no 2nd microcode region. + ## + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocode2Base|0x0|UINT32|0x30= 00000A + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocode2Size|0x0|UINT32|0x30= 00000B + gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|TRUE|BOOLEAN|0x40000001 + gCpuUncoreTokenSpaceGuid.PcdMmioRule19BaseAddress|0xFC000000|UINT32|0x40= 00000F + gSiPkgTokenSpaceGuid.PcdMaxDdrioIpChannels|0x03|UINT8|0x30000006 + gSiPkgTokenSpaceGuid.PcdMaxMcIpChannels|0x03|UINT8|0x30000008 +# +# SouthCluster +# + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x500|UINT16|0x30000003 + gSiPkgTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000005 + gSiPkgTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x30000001 + gSiPkgTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000002 + gEfiCommonPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT3= 2|0x30001033 + gSiPkgTokenSpaceGuid.PcdFspBinaryEnable |FALSE|BOOLEAN|0x30= 000010 + gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012 + gSiPkgTokenSpaceGuid.PcdSermEnable|TRUE|BOOLEAN|0x30000014 + gSiPkgTokenSpaceGuid.PcdSdpsEnable|FALSE|BOOLEAN|0x30000016 + # Added to make ADP specific changes in ServerSiliconPkg + gSiPkgTokenSpaceGuid.PcdAdpPchSupport|FALSE|BOOLEAN|0xF0000050 + + ## + ## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPc= iExpressBaseAddress. + ## This PCD is added for supporting different PCD type in different phas= es. + ## + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0x80000000|UINT64|0x002= 00002 + + ## From MdeModulePkg.dec + ## Progress Code for S3 Suspend end. + # PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OE= M_SPECIFIC | 0x00000001)) =3D 0x03078001 + gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x300= 01033 + + ## TraceHub Configuration + ## PcdTraceHubEnMode: 0 for Disabled, 1 for Internal Debugger, 2 for Hos= t Debugger + + ## TraceHub temporary disabled, until TraceHubInitialize is not working = correctly. Sighting 4929727. + gSiPkgTokenSpaceGuid.PcdTraceHubEnMode|0x00|UINT8|0x30003001 + + ## PcdTraceHubEnFWTrace: 0 for Disabled, 1 for Enabled + gSiPkgTokenSpaceGuid.PcdTraceHubEnFwTrace|0x01|UINT8|0x30003002 + ## PcdTraceHubDest: 0 for Mem, 1 for PTI, 2 for USB3, 3 for BSSB + gSiPkgTokenSpaceGuid.PcdTraceHubDest|0x02|UINT8|0x30003003 + ## PcdTraceHubTempCsrMtbBar: Temporary CSR MTB BAR + gSiPkgTokenSpaceGuid.PcdTraceHubTempCsrMtbBar|0xFE100000|UINT32|0x300030= 04 + + ## + ## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection + ## value of the struct + ## 0x00 EfiGcdAllocateAnySearchBottomUp + ## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp + ## 0x03 EfiGcdAllocateAnySearchTopDown + ## 0x04 EfiGcdAllocateMaxAddressSearchTopDown + ## + ## below value should not using in this situation + ## 0x05 EfiGcdMaxAllocateType : design for max value of struct + ## 0x02 EfiGcdAllocateAddress : design for specification address alloca= te + ## + gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + + ## + ## Temp MEM IO resource + ## + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 |0= x00010053 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 |0= x00010054 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0= x00010055 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize |0x00200000|UINT32|0= x00010056 + + ## + ## 8259 PIC + ## + gSiPkgTokenSpaceGuid.PcdDisable8259Interrupts|TRUE|BOOLEAN|0x30000017 +# +# SouthCluster End +# + +# +# Reference Code Policy default settings +# + gReferenceCodePolicyTokenSpaceGuid.PcdNumaEn |0x01|UINT8|0x0= 0000001 + gReferenceCodePolicyTokenSpaceGuid.PcdUmaBasedClustering |0x00|UINT8|0x0= 001005 + ## + ## PcdUseEmulationInjection indicates if the injection values from emula= tion team + ## should take precedence to be applied in the CSR programming. + ## FALSE: The injection values should not be applied. + ## TRUE : The injection values take precedence to be applied. + ## + gReferenceCodePolicyTokenSpaceGuid.PcdUseEmulationInjection |TRUE|BOOLE= AN|0x0001007 + + # Temperature refresh value select Auto=3D>0/Manula=3D>1 + gSiPkgTokenSpaceGuid.PcdTempRefreshOption |0|UINT8|0x7000000A + + # Temperature refresh value default, Values are in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x19|UINT8|0x7000= 0001 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue |0x53|UINT8|0x7000= 0002 + gSiPkgTokenSpaceGuid.PcdFourxRefreshValue |0x5F|UINT8|0x7000= 0003 + + # Temperature refresh Min Value, Values in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshMinValue |0|UINT8|0x7000= 0004 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshMinValue |0|UINT8|0x7000= 0005 + gSiPkgTokenSpaceGuid.PcdFourxRefreshMinValue |0|UINT8|0x7000= 0006 + + #Temperature refresh Max Value, Calues in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshMaxValue |0xFF|UINT8|0x7= 0000007 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshMaxValue |0xFF|UINT8|0x7= 0000008 + gSiPkgTokenSpaceGuid.PcdFourxRefreshMaxValue |0xFF|UINT8|0x7= 0000009 + + gSiPkgTokenSpaceGuid.PcdDdrInternalClocksOn |0|UINT8|0x7000= 000B + gSiPkgTokenSpaceGuid.PcdDdrForceBiasOn |0|UINT8|0x7000= 000C + + #Temperature Critical temperature value in celcius + gSiPkgTokenSpaceGuid.PcdMaxTCriticalValue |100|UINT8|0x70= 00000F + + #MemTrip default value + gSiPkgTokenSpaceGuid.PcdTempMemTripDefault |101|UINT8|0x70= 000010 + + #Temperature High Value when MemTrip Enabled + gEfiCpRcPkgTokenSpaceGuid.PcdTempHiMemTripEnabled |105|UINT8|0x70= 000011 + #Temperature High Value when MemTrip Disabled + gEfiCpRcPkgTokenSpaceGuid.PcdTempHiMemTripDisabled |100|UINT8|0x70= 000012 +# +# IIO CPU Trace Hub +# + # + # This Pcd for MTB BAR of CPU Trace Hub is set with the same value as fo= r PCH Trace Hub 0xfe100000 + # + gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfe100000|UINT32|0x700000= 0D + + # + # Posted CSR accesses are dynamically enabled in the code where the post= ed method is appropriate. + # + # PcdPostedCsrAccessSupported, if TRUE, exposes the SW mechanisms that s= upport the posted CSR access feature. + # PcdPostedCsrAccessAllowedDefault defines the default setting of the op= tion/knob that allows + # use of the posted CSR access feature. This PCD is only used if the= platform supports + # the posted CSR access feature (that is, if PcdPostedCsrAccessSuppo= rted is TRUE). + # + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |TRUE|BOOLEAN|0= xF0000027 + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessAllowedDefault |TRUE|BOOLEAN|0= xF0000029 + + # + # CPGC global sync control will synchronize CPGC test start across all s= elected memory controllers + # + # PcdCpgcGlobalSyncCtrlSupported, if TRUE, exposes the SW mechanisms tha= t support the feature + # PcdCpgcGlobalSyncCtrlEnableDefault, if TRUE, sets the value of the BIO= S knob to Enable + # + gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported |FALSE|BOOLEAN= |0xF0000030 + gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault |FALSE|BOOLEAN= |0xF0000031 + + gSiPkgTokenSpaceGuid.PcdPeiCoreFv |0x00000000|UI= NT32|0xF0000032 + + gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033 + + # + # Sense Amp Calibration can be trained using HW FSM or SW based algorith= ms + # PcdSenseAmpCalibHwFsmSupported determines if the HW FSM is supported b= y the platform + # + gSiPkgTokenSpaceGuid.PcdSenseAmpCalibHwFsmSupported |FALSE|BOOLEAN= |0xF0000034 + + gSiPkgTokenSpaceGuid.ReservedO |0|UINT8|0xF0000035 + + # PcdCpgcRegCacheAccessSupported, if TRUE, exposes the SW mechanisms tha= t support CPGC register cache access feature. + # PcdCpgcRegCacheAccessAllowedDefault defines the default setting of the= option/knob that allows + # use of CPGC register cache access feature. This PCD is only used i= f the platform supports + # CPGC register cache access feature (that is, if PcdCpgcRegCacheAcc= essSupported is TRUE). + # + gSiPkgTokenSpaceGuid.PcdCpgcRegCacheAccessSupported |TRUE|BOOLEA= N|0xF0000040 + gSiPkgTokenSpaceGuid.PcdCpgcRegCacheAccessAllowedDefault |TRUE|BOOLEA= N|0xF0000041 + + gSiPkgTokenSpaceGuid.ReservedA |FALSE|BOOLEAN|0xF0000036 + + gSiPkgTokenSpaceGuid.ReservedP |FALSE|BOOLEAN|0xF0000037 + + # + #Set the PcdPeiMemoryBaseAddressDefault control whether to limit the mem= ory used by UEFI to below 1GB + #PcdPeiMemoryBaseAddressDefault, if FALSE, the memory used by UEFI will = be limited to below 1GB + # + gSiPkgTokenSpaceGuid.PcdPeiMemoryBaseAddressDefault |TRUE|BOOLEAN|= 0x30000022 + +# +# VTD PCDs Begin +# + + gSiPkgTokenSpaceGuid.PcdVtdSupport|FALSE|BOOLEAN|0x00000006 + +# +# VTD PCDs End +# + +[PcdsDynamicEx] + gReferenceCodePolicyTokenSpaceGuid.PcdEvMode |0x00|UINT8|0x00010= 001 + # ReservedC: The Mailbox Command which it gona to assert. + # 0x00: it will not assert + # 0xFF: it will assert on any error + # Other values: it will assert on the speci= fied command failure + # + gReferenceCodePolicyTokenSpaceGuid.ReservedC|0x0|UINT8|0x00010003 + # + # PcdWarmResetEliminationEn - if TRUE, it indicates SoC supports warm-re= set elimination feature. + # This feature requires Silicon (hardware) support for warm-reset elimin= ation flow to be + # fully functioning. + # + gSiPkgTokenSpaceGuid.PcdWarmResetEliminationEn|FALSE|BOOLEAN|0x0001000A + # + # PcdEmuBiosSkipS3MAccess - TRUE: S3M Flow is skipped; FALSE: S3M Flow i= s not skipped. + # + gSiPkgTokenSpaceGuid.PcdEmuBiosSkipS3MAccess|FALSE|BOOLEAN|0x0001000D + + gSiPkgTokenSpaceGuid.PcdHvmModeEnabled|FALSE|BOOLEAN|0x5000000D + # + # PcdNumaAcpiDataStaticPointer: Saves the static pointer of the NumaAcpi= Data buffer. + # + gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E + +[PcdsDynamic, PcdsDynamicEx] + gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 + gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A + gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D + gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B + +## +## ME +## + gEfiMePkgTokenSpaceGuid.PcdMePlatformResetType|0x00|UINT32|0x50000008 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. +## + gEfiMePkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x50000009 + +## +## RAS +## + gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001 + gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 + +[PcdsFeatureFlag] + ## This PCD used by FPGA drivers to decide to install FPGA features. + gSocketPkgFpgaGuid.PcdSktFpgaActive|FALSE|BOOLEAN|0x1000000E + + gSiPkgTokenSpaceGuid.PcdSimicsEnable |FALSE|BOOLEAN|0xF0= 000022 + gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE|BOOLEAN|0xF0= 000005 + gSiPkgTokenSpaceGuid.PcdCnlPchEnable |TRUE |BOOLEAN|0xF0= 000026 + gEfiMePkgTokenSpaceGuid.PcdHeciEndOfDxeNotify |FALSE|BOOLEAN|0x50= 00000A + gEfiMePkgTokenSpaceGuid.PcdNodeManagerEnable |TRUE |BOOLEAN|0x50= 00000C diff --git a/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec b/Silico= n/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec new file mode 100644 index 0000000000..ae951e0b14 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec @@ -0,0 +1,65 @@ +## @file +# Component description file for the Silicon Reference Code. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D WhitleySiliconPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D 6f1ec317-5d04-456a-8908-6290453d57ac + +[Includes] + Include + Cpu/Include + Library/BaseMemoryCoreLib/Core/Include + Library/BaseMemoryCoreLib/Platform + Pch/SouthClusterLbg + Pch/SouthClusterLbg/Include + Me/MeSps.4/Include + Security/Include + Security/Include/Guid + +[Guids] + gStatusCodeDataTypeExDebugGuid =3D { 0x7859daa2, 0x926e, = 0x4b01, { 0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }} + gEfiCpRcPkgTokenSpaceGuid =3D { 0xfcdd2efc, 0x6ca8, = 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }} + gReferenceCodePolicyTokenSpaceGuid =3D { 0x3268c52f, 0xd3b3, = 0x405d, { 0xb6, 0x91, 0x14, 0x4f, 0xca, 0x42, 0xe4, 0x37 }} # {3268c52f-d3= b3-405d-b691-144fca42e437} + gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0= x4b6b, {0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}} + gSiliconPolicyInitLibInterfaceGuid =3D { 0x058715d2, 0x371f, = 0x486e, { 0x86, 0xf9, 0xbc, 0x7f, 0x89, 0xbc, 0x90, 0x26 }} # {058715d2-37= 1f-486e-86f9-bc7f89bc9026} + gSaveHostToMemoryGuid =3D { 0x9da19038, 0x2085, = 0x486a, { 0xad, 0x53, 0xc4, 0x97, 0xda, 0xaa, 0x20, 0x48 } } + +[Ppis] + gDynamicSiLibraryPpiGuid =3D { 0x4e18e22b, 0x5034, = 0x4512, { 0xb7, 0xe5, 0x0b, 0xf1, 0x9d, 0xe3, 0x59, 0x8c }} + +[Protocols] + gDynamicSiLibraryProtocolGuid =3D { 0xb235fbed, 0x3b25, = 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e }} + gDynamicSiLibrarySmmProtocolGuid =3D { 0x82faf3a3, 0x6226, = 0x48be, {0xb0, 0x4e, 0xc2, 0xfb, 0x0f, 0x72, 0xcf, 0x2f }} + +[PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011 + + gSiPkgTokenSpaceGuid.PcdHvmModeEnabled|FALSE|BOOLEAN|0x5000000D + + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00= 000048 + + gReferenceCodePolicyTokenSpaceGuid.ReservedD|0x0F|UINT8|0x00010002 + + # + # ReservedC: The Mailbox Command which it gona to assert. + # 0x00: it will not assert + # 0xFF: it will assert on any error + # Other values: it will assert on the speci= fied command failure + # + gReferenceCodePolicyTokenSpaceGuid.ReservedC|0x0|UINT8|0x00010003 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x600000= 14 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x60000= 01C + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x60000021 --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77707): https://edk2.groups.io/g/devel/message/77707 Mute This Topic: https://groups.io/mt/84168617/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-