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[192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.2664.1626136920574620140 for ; Mon, 12 Jul 2021 17:42:04 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456230" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456230" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422964" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:55 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 10/17] WhitleyOpenBoardPkg: Add Includes and Libraries Date: Mon, 12 Jul 2021 17:41:24 -0700 Message-Id: <20210713004131.1782-11-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: n7elTEZe6Jqf4UtcheWA7pPjx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136925; bh=FYrrREndofz2Sheil9EM45RBXPgveDhoqnCeM04uCtM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=YIQ+odThgD7PJhulSPeGIgWjnOjiZTj+HOS/zFmST/2EZE2myUW7jdZVcfNGNMqhmc0 853yfFAz4Empl5/xYP2tFtyQNVxpb9OXbF4/iaFrP1ScsPE708S18NS0RMxYHSi8Qu2PC GQvNGBnw5WMdQ/wbi4VG0eIwx5zAXuZLOQ0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136928027100004 Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki --- .../Include/Dsc/CoreDxeInclude.dsc | 135 ++ ...blePerformanceMonitoringInfrastructure.dsc | 40 + .../Include/Dsc/EnableRichDebugMessages.dsc | 50 + .../Include/Fdf/CommonNvStorageFtwWorking.fdf | 20 + .../Include/Fdf/CommonSpiFvHeaderInfo.fdf | 24 + ...anceMonitoringInfrastructurePostMemory.fdf | 14 + ...manceMonitoringInfrastructurePreMemory.fdf | 11 + .../Include/Fdf/NvStorage512K.fdf | 46 + .../Include/GpioInitData.h | 26 + .../Include/Guid/PlatformVariableCommon.h | 33 + .../Include/Guid/SetupVariable.h | 720 ++++++++ .../Include/Guid/UbaCfgHob.h | 74 + .../WhitleyOpenBoardPkg/Include/IoApic.h | 23 + .../Include/Library/MultiPlatSupportLib.h | 67 + .../Include/Library/PeiPlatformHooklib.h | 17 + .../Include/Library/PlatformClocksLib.h | 87 + .../Include/Library/PlatformOpromPolicyLib.h | 83 + .../Library/PlatformSetupVariableSyncLib.h | 60 + .../Include/Library/PlatformVariableHookLib.h | 47 + .../Include/Library/ReadFfsLib.h | 58 + .../Include/Library/SetupLib.h | 134 ++ .../Include/Library/UbaAcpiUpdateLib.h | 38 + .../Include/Library/UbaBoardSioInfoLib.h | 47 + .../Include/Library/UbaClkGenUpdateLib.h | 49 + .../Include/Library/UbaClocksConfigLib.h | 51 + .../Include/Library/UbaGpioInitLib.h | 26 + .../Include/Library/UbaGpioPlatformConfig.h | 259 +++ .../Include/Library/UbaGpioUpdateLib.h | 51 + .../Library/UbaHsioPtssTableConfigLib.h | 52 + .../Include/Library/UbaIioConfigLib.h | 227 +++ .../Library/UbaIioPortBifurcationInitLib.h | 47 + .../Include/Library/UbaOpromUpdateLib.h | 115 ++ .../Include/Library/UbaPcdUpdateLib.h | 44 + .../Include/Library/UbaPchEarlyUpdateLib.h | 63 + .../Library/UbaPcieBifurcationUpdateLib.h | 130 ++ .../Include/Library/UbaPlatLib.h | 25 + .../Include/Library/UbaSlotUpdateLib.h | 124 ++ .../Include/Library/UbaSoftStrapUpdateLib.h | 57 + .../Include/Library/UbaSystemBoardInfoLib.h | 36 + .../Library/UbaSystemConfigUpdateLib.h | 42 + .../Include/Library/UbaUsbOcUpdateLib.h | 51 + .../Include/OnboardNicStructs.h | 98 ++ .../Include/PchSetupVariable.h | 10 + .../Include/PchSetupVariableLbg.h | 372 ++++ .../WhitleyOpenBoardPkg/Include/PlatDevData.h | 183 ++ .../Include/PlatPirqData.h | 36 + .../Include/Ppi/ExReportStatusCodeHandler.h | 38 + .../Include/Ppi/SmbusPolicy.h | 29 + .../Include/Ppi/UbaCfgDb.h | 144 ++ .../Include/Protocol/LegacyBios.h | 1550 +++++++++++++++++ .../Include/Protocol/LegacyBiosPlatform.h | 752 ++++++++ .../Include/Protocol/PciIovPlatform.h | 72 + .../Include/Protocol/PlatformType.h | 48 + .../Include/Protocol/UbaCfgDb.h | 114 ++ .../Include/Protocol/UbaDevsUpdateProtocol.h | 86 + .../Include/Protocol/UbaMakerProtocol.h | 22 + .../WhitleyOpenBoardPkg/Include/SetupTable.h | 25 + .../WhitleyOpenBoardPkg/Include/SioRegs.h | 251 +++ .../WhitleyOpenBoardPkg/Include/SystemBoard.h | 75 + .../WhitleyOpenBoardPkg/Include/UbaKti.h | 29 + .../BoardAcpiLib/DxeBoardAcpiTableLib.c | 37 + .../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 44 + .../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 54 + .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 51 + .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 48 + .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 138 ++ .../Library/BoardInitLib/BoardInitDxeLib.c | 299 ++++ .../Library/BoardInitLib/BoardInitDxeLib.inf | 72 + .../Library/BoardInitLib/BoardInitDxeLib.uni | 29 + .../Library/BoardInitLib/BoardInitPreMemLib.c | 450 +++++ .../BoardInitLib/BoardInitPreMemLib.inf | 66 + .../MultiPlatSupportLib/MultiPlatSupport.h | 48 + .../MultiPlatSupportLib/MultiPlatSupportLib.c | 255 +++ .../MultiPlatSupportLib.inf | 49 + .../FspWrapperHobProcessLib.c | 722 ++++++++ .../PeiFspWrapperHobProcessLib.inf | 99 ++ .../PeiPlatformHookLib/PeiPlatformHooklib.c | 43 + .../PeiPlatformHookLib/PeiPlatformHooklib.inf | 34 + .../Library/PeiReportFvLib/PeiReportFvLib.c | 270 +++ .../Library/PeiReportFvLib/PeiReportFvLib.inf | 65 + .../PeiUbaGpioPlatformConfigLib.c | 518 ++++++ .../Library/PeiUbaPlatLib/PeiUbaPlatLib.inf | 60 + .../PeiUbaPlatLib/PeiUbaUsbOcUpdateLib.c | 61 + .../PeiUbaPlatLib/UbaBoardSioInfoLib.c | 54 + .../PeiUbaPlatLib/UbaClkGenUpdateLib.c | 134 ++ .../PeiUbaPlatLib/UbaClocksConfigLib.c | 59 + .../Library/PeiUbaPlatLib/UbaGpioUpdateLib.c | 68 + .../PeiUbaPlatLib/UbaHsioPtssTableConfigLib.c | 58 + .../PeiUbaPlatLib/UbaIioConfigLibPei.c | 219 +++ .../UbaIioPortBifurcationInitLib.c | 55 + .../Library/PeiUbaPlatLib/UbaPcdUpdateLib.c | 69 + .../PeiUbaPlatLib/UbaPchEarlyUpdateLib.c | 108 ++ .../PeiUbaPlatLib/UbaPchPcieBifurcationLib.c | 57 + .../PeiUbaPlatLib/UbaSlotUpdateLibPei.c | 156 ++ .../PeiUbaPlatLib/UbaSoftStrapUpdateLib.c | 95 + .../PlatformClocksLib/Pei/PlatformClocksLib.c | 347 ++++ .../Pei/PlatformClocksLib.inf | 40 + .../PlatformCmosAccessLib.c | 73 + .../PlatformCmosAccessLib.inf | 45 + .../Library/PlatformHooksLib/PlatformHooks.c | 203 +++ .../PlatformHooksLib/PlatformHooksLib.inf | 28 + .../PlatformOpromPolicyLibNull.c | 88 + .../PlatformOpromPolicyLibNull.inf | 29 + .../PlatformSetupVariableSyncLibNull.c | 81 + .../PlatformSetupVariableSyncLibNull.inf | 28 + .../PlatformVariableHookLibNull.c | 55 + .../PlatformVariableHookLibNull.inf | 24 + .../Library/ReadFfsLib/ReadFfsLib.c | 446 +++++ .../Library/ReadFfsLib/ReadFfsLib.inf | 34 + .../Library/SerialPortLib/Ns16550.h | 46 + .../Library/SerialPortLib/SerialPortLib.c | 1023 +++++++++++ .../Library/SerialPortLib/SerialPortLib.inf | 55 + .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 867 +++++++++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 55 + .../PchPolicyUpdateUsb.c | 152 ++ .../SiliconPolicyUpdateLib.c | 778 +++++++++ .../SiliconPolicyUpdateLib.inf | 64 + .../SiliconPolicyUpdateLibFsp.c | 770 ++++++++ .../SiliconPolicyUpdateLibFsp.inf | 68 + .../SmmSpiFlashCommonLib.inf | 57 + .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 237 +++ .../SpiFlashCommonSmmLib.c | 55 + .../DxeTcg2PhysicalPresenceLib.c | 41 + .../DxeTcg2PhysicalPresenceLib.inf | 29 + .../Library/UbaGpioInitLib/UbaGpioInitLib.c | 145 ++ .../Library/UbaGpioInitLib/UbaGpioInitLib.inf | 46 + 126 files changed, 17890 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeI= nclude.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePe= rformanceMonitoringInfrastructure.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRi= chDebugMessages.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNv= StorageFtwWorking.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSp= iFvHeaderInfo.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePe= rformanceMonitoringInfrastructurePostMemory.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePe= rformanceMonitoringInfrastructurePreMemory.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorag= e512K.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/Platfor= mVariableCommon.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVa= riable.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgH= ob.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Mult= iPlatSupportLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiP= latformHooklib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formClocksLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formOpromPolicyLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formSetupVariableSyncLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formVariableHookLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Read= FfsLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Setu= pLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaA= cpiUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaB= oardSioInfoLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaC= lkGenUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaC= locksConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioInitLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioPlatformConfig.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaH= sioPtssTableConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaI= ioConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaI= ioPortBifurcationInitLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaO= promUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= cdUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= chEarlyUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= cieBifurcationUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= latLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= lotUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= oftStrapUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= ystemBoardInfoLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= ystemConfigUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaU= sbOcUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicSt= ructs.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVari= able.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVari= ableLbg.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReport= StatusCodeHandler.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPol= icy.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Leg= acyBios.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Leg= acyBiosPlatform.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Pci= IovPlatform.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Pla= tformType.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= CfgDb.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= DevsUpdateProtocol.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= MakerProtocol.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeMtOlympusAcpiTableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.uni create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitPreMemLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitPreMemLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupport.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupportLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupportLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrappe= rHobProcessLib/FspWrapperHobProcessLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrappe= rHobProcessLib/PeiFspWrapperHobProcessLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformH= ookLib/PeiPlatformHooklib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformH= ookLib/PeiPlatformHooklib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvL= ib/PeiReportFvLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvL= ib/PeiReportFvLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaGpioPlatformConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaPlatLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaUsbOcUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaBoardSioInfoLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaClkGenUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaClocksConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaGpioUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaHsioPtssTableConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaIioConfigLibPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaIioPortBifurcationInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPcdUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchEarlyUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchPcieBifurcationLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaSlotUpdateLibPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaSoftStrapUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCloc= ksLib/Pei/PlatformClocksLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCloc= ksLib/Pei/PlatformClocksLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmos= AccessLib/PlatformCmosAccessLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmos= AccessLib/PlatformCmosAccessLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHook= sLib/PlatformHooks.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHook= sLib/PlatformHooksLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpro= mPolicyLibNull/PlatformOpromPolicyLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpro= mPolicyLibNull/PlatformOpromPolicyLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetu= pVariableSyncLibNull/PlatformSetupVariableSyncLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetu= pVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVari= ableHookLibNull/PlatformVariableHookLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVari= ableHookLibNull/PlatformVariableHookLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/R= eadFfsLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/R= eadFfsLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/Ns16550.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/SerialPortLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/SerialPortLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrr= Lib/SetCacheMtrrLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrr= Lib/SetCacheMtrrLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/PchPolicyUpdateUsb.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLibFsp.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLibFsp.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SmmSpiFlashCommonLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SpiFlashCommon.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SpiFlashCommonSmmLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2Physical= PresenceLibNull/DxeTcg2PhysicalPresenceLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2Physical= PresenceLibNull/DxeTcg2PhysicalPresenceLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitL= ib/UbaGpioInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitL= ib/UbaGpioInitLib.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.= dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc new file mode 100644 index 0000000000..13f65ff43d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc @@ -0,0 +1,135 @@ +## @file +# Platform description. +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + + # + # Generic EDKII Driver + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf + } + + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!endif +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + #UefiCpuPkg/CpuDxe/CpuDxe.inf + + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + + #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferD= xe.inf + + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + } + SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf +!endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePerforman= ceMonitoringInfrastructure.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include= /Dsc/EnablePerformanceMonitoringInfrastructure.dsc new file mode 100644 index 0000000000..c308e0df4f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePerformanceMonit= oringInfrastructure.dsc @@ -0,0 +1,40 @@ +## @file EnablePerformanceMonitoringInfrastructure.dsc +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdEdkiiFpdtStringRecordEnableOnly|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|100 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries16|100 + gEfiMdeModulePkgTokenSpaceGuid.PcdExtFpdtBootRecordPadSize|0x10000 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + +[LibraryClasses.X64] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + +[LibraryClasses.X64.DXE_CORE] + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.= inf + +[LibraryClasses.X64.SMM_CORE] + PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerform= anceLib.inf + +[Components.IA32] + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerf= ormancePei.inf + +[Components.X64] + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerf= ormanceDxe.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerf= ormanceSmm.inf + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf + +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebug= Messages.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDeb= ugMessages.dsc new file mode 100644 index 0000000000..6a66f2ebbb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessage= s.dsc @@ -0,0 +1,50 @@ +## @file EnableRichDebugMessages.dsc +# This takes care to turn on a higher level of debug messages that produce= s a +# balance between performance and greater levels of detail. +# This also customizes cores to use BaseDebugLibSerialPort for maximum +# messaging. +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# Customize debug messages +# +[PcdsFixedAtBuild] + ## This flag is used to control the built in Debug messages. + # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT4 - Allocate or Free Pool message.
+ # BIT5 - Allocate or Free Page message.
+ # BIT6 - Information message.
+ # BIT7 - Dispatcher message.
+ # BIT8 - Variable message.
+ # BIT10 - Boot Manager message.
+ # BIT12 - BlockIo Driver message.
+ # BIT14 - Network Driver message.
+ # BIT16 - UNDI Driver message + # BIT17 - LoadFile message.
+ # BIT19 - Event message.
+ # BIT20 - Global Coherency Database changes message.
+ # BIT21 - Memory range cachability changes message.
+ # BIT22 - Detailed debug message.
+ # BIT31 - Error message.
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x802A00C7 + +[PcdsPatchableInModule] + # + # This flag is used to control the displayed Debug messages. + # For simplification, we like to ensure both built in and enabled are in= sync + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|gEfiMdePkgTokenSpaceGui= d.PcdFixedDebugPrintErrorLevel + +[LibraryClasses.IA32.PEI_CORE] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + +[LibraryClasses.X64.DXE_CORE] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorage= FtwWorking.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvSto= rageFtwWorking.fdf new file mode 100644 index 0000000000..97c7c2a28f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWork= ing.fdf @@ -0,0 +1,20 @@ +## @file CommonNvStorageFtwWorking.fdf +# FV contents for FTW Working block FV +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHead= erInfo.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHead= erInfo.fdf new file mode 100644 index 0000000000..08f8b95938 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.= fdf @@ -0,0 +1,24 @@ +## @file CommonSpiFvHeaderInfo.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +FvAlignment =3D 16 #FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerforman= ceMonitoringInfrastructurePostMemory.fdf b/Platform/Intel/WhitleyOpenBoardP= kg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf new file mode 100644 index 0000000000..a3576bd7a8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonit= oringInfrastructurePostMemory.fdf @@ -0,0 +1,14 @@ +## @file EnablePerformanceMonitoringInfrastructurePostMemory.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmwar= ePerformanceDxe.inf + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firmwar= ePerformanceSmm.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.= inf + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerforman= ceMonitoringInfrastructurePreMemory.fdf b/Platform/Intel/WhitleyOpenBoardPk= g/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf new file mode 100644 index 0000000000..dbc98f6f1f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonit= oringInfrastructurePreMemory.fdf @@ -0,0 +1,11 @@ +## @file EnablePerformanceMonitoringInfrastructurePreMemory.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwar= ePerformancePei.inf +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.f= df b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf new file mode 100644 index 0000000000..089d9bbf06 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf @@ -0,0 +1,46 @@ +## @file NvStorage512K.fdf +# FV contents for NV storage variable and fault tolerant write usage. +# The size and block layout here must match the actual layout built by the= build tools. +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0= x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 8 Blocks * 0x10000 Bytes / Block + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0= x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98= , 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x3C000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3BFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xBF, 0x03, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h new file mode 100644 index 0000000000..2e25c4b6c5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h @@ -0,0 +1,26 @@ +/** @file + Platform specific information + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "Platform.h" + +#ifndef __GPIO_INIT_DATA_H__ +#define __GPIO_INIT_DATA_H__ + +#include +#include + + +// +// SKX_TODO: Platform Update GPIO table +// +// +// SKX_TODO: Create GPIO tables for LBG platforms (PCH_GPIO_CONFIG type) +// + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariab= leCommon.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariab= leCommon.h new file mode 100644 index 0000000000..aab9856c66 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariableCommo= n.h @@ -0,0 +1,33 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_VARIABLE_COMMON_H_ +#define _PLATFORM_VARIABLE_COMMON_H_ + + +#ifndef PLATFORM_SETUP_VARIABLE_NAME +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup" +#endif + +#define CMOS_CLEAR_EVENT BIT0 +#define CMOS_BAD_CHECKSUM_EVENT BIT1 +#define MFG_MODE_EVENT BIT2 +#define RECOVERY_MODE_EVENT BIT3 +#define LOAD_FAILSAFE_EVENT BIT4 +#define LOAD_CUSTOMIZED_EVENT BIT5 +#define NULL_VARIABLE_EVENT BIT6 + +#define PLATFORM_VARIABLE_HOB_GUID { 0x71e6d4bc, 0x4837, 0x45f1, { 0xa2, 0= xd7, 0x3f, 0x93, 0x8, 0xb1, 0x7e, 0xd7 } } + +extern EFI_GUID gPlatformVariableHobGuid; + +#define LOAD_FAILSAFE_VARIABLE_NAME L"LoadEPSDConfigurationDefaults" +#define LOAD_CUSTOMIZED_VARIABLE_NAME L"LoadSystemConfigurationDefaults" + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..c47f040ca3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h @@ -0,0 +1,720 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SETUP_VARIABLE_H__ +#define __SETUP_VARIABLE_H__ + +// -----------------------------------------------------------------------= ---- +// +// Driver Configuration +// +// -----------------------------------------------------------------------= ---- +// +//Copied from client SetupVariable.h +#ifndef PLATFORM_SETUP_VARIABLE_NAME +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup" +#endif + +#ifndef PCH_SETUP_VARIABLE +#define PCH_SETUP_VARIABLE_NAME L"PchSetup" +#endif + +#define EFI_EPG_GENERIC_VARIABLE_GUID \ + { \ + 0x8302cc54, 0xbb1a, 0x4564, {0x92, 0xdc, 0xae, 0x1a, 0xbb, 0x15, 0x5f,= 0x35} \ + } + +// +// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9} +// +#define SYSTEM_CONFIGURATION_GUID \ + { \ + 0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, = 0xa9} \ + } + +#define PCH_SETUP_GUID \ + { \ + 0x4570b7f1, 0xade8, 0x4943, {0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0= x84} \ + } + +#define FAKE_VARSTORE_GUID \ + { \ + 0xe57d5cb9, 0x148f, 0x444d, {0x9e, 0xcb, 0x9d, 0xf8, 0x65, 0x30, 0xa0,= 0xb4} \ + } + +#define SYSTEM_CONFIGURATION_CONTROL_GUID \ + { \ + 0x8d247131, 0x385e, 0x491f, {0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3,= 0xa6} \ + } + +#define SYSTEM_CONFIGURATION_ICHPCIE_GUID \ + { \ + 0x10e023a7, 0x4ce5, 0x4a6a, {0xa1, 0xbb, 0xbd, 0xd0, 0x8d, 0x16, 0x37,= 0x57} \ + } + +#define SYSTEM_DEFAULT_CONFIGURATION_GUID \ + { \ + 0x99a96812, 0x4730, 0x4290, {0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9,= 0x3b} \ + } + +#define RESERVEMEMFLAG_VARIABLE_GUID \ +{\ + 0xb87aa73f, 0xdcb3, 0x4533, {0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, = 0x40} \ +} + +#define BMC_ENABLE_FLAG_GUID \ +{\ + 0x7bb08ce4, 0x6988, 0x4c59, {0xb5, 0x37, 0xb4, 0xb1, 0xd5, 0xbe, 0xb0, = 0x6e} \ +} + +#define MAX_PCH_PCI_EXPRESS_ROOT_PORTS 8 +#define PASSWORD_MAX_SIZE 16 +#define SHA256_DIGEST_LENGTH 32 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 + +#define FAKE_VARSTORE_ID 0x1234 +#define ME_SETUP_STORAGE_ID 0x1235 +#define ICC_SETUP_ID 0x1236 + +extern EFI_GUID gReserveMemFlagVariableGuid; + +#pragma pack(1) + +typedef struct { + + UINT8 UserPassword[SHA256_DIGEST_LENGTH]; + UINT8 AdminPassword[SHA256_DIGEST_LENGTH]; + UINT8 Access; + + // + // Keyboard + // + UINT8 Numlock; + UINT8 Ps2PortSwap; + + // + // TPM + // + UINT8 TpmEnable; + UINT8 TpmState; + UINT8 MorState; + + // + // XmlCli + // + UINT8 XmlCliSupport; + UINT8 SkipXmlComprs; + UINT8 PublishSetupPgPtr; + UINT32 XmlCLiDramCmosAddr; + + // + // Breakpoints + // + UINT8 ValidationBreakpointType; + UINT16 bsdBreakpoint; + + // + // Power State + // + UINT8 PowerState; + + // + // Wake On Lan + // + UINT8 WakeOnLanS5; + + // + // Boot from Network + // + UINT8 BootNetwork; + + // + // Video + // + UINT8 VideoSelect; + UINT8 EfiWindowsInt10Workaround; + UINT8 UefiOptimizedBootToggle; + + // + // Fan PWM Offset + // + UINT8 FanPwmOffset; + + // + // Benchmark + // + UINT8 ApplicationProfile; + + // + // PCI Minimum Secondary Bus Number + // + UINT8 PCIe_MultiSeg_Support; + + // + UINT8 WakeOnLanSupport; + // + // Enable/disable for PCIe LOM by using GPO44/45 + // NOT PCH LAN + // + UINT8 LomDisableByGpio; + + UINT8 FpkPortConfig[4]; + UINT8 FpkPortConfigPrev[4]; + UINT8 FpkPortPresent[4]; + + // RTC WAKE + // + UINT8 WakeOnRTCS4S5; + UINT8 RTCWakeupTimeHour; + UINT8 RTCWakeupTimeMinute; + UINT8 RTCWakeupTimeSecond; + // PCI_EXPRESS_CONFIG, ROOT PORTS + // + // AJW: these cross the line, but depend on Platform Info + UINT8 PcieClockGatingDisabled ; + UINT8 PcieDmiAspm; + UINT8 PcieSBDE; + UINT8 GbePciePortNum; + UINT8 PciePortConfig1; + UINT8 PciePortConfig2; + UINT8 PciePortConfig3; + UINT8 PciePortConfig4; + UINT8 PciePortConfig5; + + // GBE + UINT8 GbeEnabled; + + // PCH Stepping + UINT8 PchStepping; + + // + // XHCI Wake On USB + // + UINT8 XhciWakeOnUsbEnabled; + + // + // EventLog + // +// +// SKX_TODO: add these for RAS, may be best to find new home for them in a= new setup variable and setup page +// + UINT8 SystemErrorEn; + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + UINT8 RasLogLevel; + UINT8 PoisonEn; + UINT8 ViralEn; + UINT8 CloakDevHideRegistersOs; + UINT8 ClearViralStatus; + UINT8 CloakingEn; + UINT8 UboxToPcuMcaEn; + UINT8 FatalErrSpinLoopEn; + + UINT8 EmcaEn; + UINT8 EmcaIgnOptin; + UINT8 EmcaCsmiEn; + UINT16 EmcaCsmiThreshold; + UINT8 CsmiDynamicDisable; + UINT8 EmcaMsmiEn; + UINT8 ElogCorrErrEn; + UINT8 ElogMemErrEn; + UINT8 ElogProcErrEn; + UINT8 LmceEn; + UINT8 HideWriteDataParityLogs; + UINT8 UboxErrorMask; + + UINT8 WheaSupportEn; + UINT8 WheaLogMemoryEn; + UINT8 WheaLogProcEn; + + UINT8 WheaLogPciEn; + UINT8 AEPErrorInjEn; + UINT8 WheaErrorInjSupportEn; + UINT8 McaBankErrInjEn; + UINT8 WheaErrInjEn; + UINT8 WheaPcieErrInjEn; + UINT8 MeSegErrorInjEn; + UINT8 SgxErrorInjEn; + UINT8 PcieErrInjActionTable; + + UINT8 MemErrEn; + UINT8 CorrMemErrEn; + UINT8 SpareIntSelect; + UINT8 PfdEn; + UINT8 DcpmmEccModeSwitch; + UINT8 FnvErrorEn; + UINT8 FnvErrorLowPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 FnvErrorHighPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 NgnAddressRangeScrub; + UINT8 NgnHostAlertDpa; //Signal Poison or Viral upon receiving = DIMM Physical Address Error + UINT8 NgnHostAlertPatrolScrubUNC; //Signal DDRT interrupt upon receiv= ing Uncorrectable Error for NGN Patrol Scrub + UINT8 ReportAlertSPA; //Include SPA when reporting DDRT a= lert. Only to disable for MCE recovery test. + UINT8 DcpmmUncPoison; // Poison media location for Uncorr= ectable error on Read (via patrol scrubber..) + UINT8 DdrtInternalAlertEn; + + UINT8 IioErrorEn; + UINT8 OsNativeAerSupport; + UINT8 IoMcaEn; + UINT8 IioSev1Pcc; + UINT8 IioErrRegistersClearEn; + UINT8 IioErrorPin0En; + UINT8 IioErrorPin1En; + UINT8 IioErrorPin2En; + UINT8 LerEn; + UINT8 DisableMAerrorLoggingDueToLER; + UINT8 EdpcEn; + UINT8 EdpcInterrupt; + UINT8 EdpcErrCorMsg; + UINT8 PciePtlpEgrBlk; + + UINT8 IioIrpErrorEn; + UINT8 IioMiscErrorEn; + UINT8 IioVtdErrorEn; + UINT8 IioDmaErrorEn; + UINT8 IioDmiErrorEn; + UINT8 IioPcieAddCorrErrorEn; + UINT8 IioPcieAddUnCorrEn; + UINT8 IioPcieAddRcvComWithUr; + UINT8 IioPcieAerSpecCompEn; + UINT8 ItcOtcCaMaEnable; + UINT8 PsfUrEnable; + UINT8 PmsbRouterParityErrEn; + UINT8 PcieErrEn; + UINT8 PcieCorrErrEn; + UINT8 PcieUncorrErrEn; + UINT8 PcieFatalErrEn; + UINT8 PcieCorErrCntr; + UINT16 PcieCorErrThres; + UINT8 PcieCorErrLimitEn; + UINT32 PcieCorErrLimit; + UINT8 PcieAerCorrErrEn; + UINT8 PcieAerAdNfatErrEn; + UINT8 PcieAerNfatErrEn; + UINT8 PcieAerFatErrEn; + UINT8 PcieAerEcrcEn; + UINT8 PcieAerSurpriseLinkDownEn; + UINT8 PcieAerUreEn; + UINT8 McaSpinLoop; + UINT8 IioOOBMode; + +// Endof RAS add + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + + UINT8 McBankWarmBootClearError; + UINT8 ShutdownSuppression; + UINT8 KTIFailoverSmiEn; + + UINT8 irpp0_parityError; + UINT8 irpp0_qtOverflow; + UINT8 irpp0_unexprsp; + UINT8 irpp0_csraccunaligned; + UINT8 irpp0_unceccCs1; + UINT8 irpp0_unceccCs0; + UINT8 irpp0_rcvdpoison; + UINT8 irpp0_crreccCs1; + UINT8 irpp0_crreccCs0; + + UINT8 PropagateSerr; + UINT8 PropagatePerr; + + // + // Boot Options + // + UINT8 serialDebugMsgLvl; + UINT8 serialDebugTrace; + UINT8 serialDebugMsgLvlTrainResults; + UINT8 ResetOnMemMapChange; + UINT8 ForceSetup; + UINT8 BiosGuardEnabled; + UINT8 BiosGuardPlatformSupported; + UINT8 EnableAntiFlashWearout; + UINT8 AntiFlashWearoutSupported; + UINT8 ReservedS1; + + UINT8 Use1GPageTable; + // + // UINT8 QuietBoot; + // + UINT8 FastBoot; + + // PFR { + UINT8 PfrSupported; + UINT8 PfrCpldRotReleaseVersion; + UINT8 PfrCpldRotSvn; + UINT8 PfrPchPfrActiveSvn; + UINT8 PfrPchPfmActiveMajorVersion; + UINT8 PfrPchPfmActiveMinorVersion; + UINT8 PfrBmcPfrActiveSvn; + UINT8 PfrBmcPfmActiveMajorVersion; + UINT8 PfrBmcPfmActiveMinorVersion; + UINT8 PfrPchPfrRecoverySvn; + UINT8 PfrPchPfmRecoveryMajorVersion; + UINT8 PfrPchPfmRecoveryMinorVersion; + UINT8 PfrBmcPfrRecoverySvn; + UINT8 PfrBmcPfmRecoveryMajorVersion; + UINT8 PfrBmcPfmRecoveryMinorVersion; + UINT8 PfrLockStatus; + UINT8 PfrProvisionStatus; + UINT8 PfrPitL1Status; + UINT8 PfrPitL2Status; + UINT8 PfrLock; + UINT8 PfrProvision; + UINT8 PfrUnProvision; + UINT8 PfrPitL1; + UINT8 PfrPitL2; + // PFR } + + // + // Reserve Memory that is hidden from the OS. + // + UINT8 ReserveMem; + UINT64 ReserveStartAddr; + // + // Reserve TAGEC Memory + // + UINT8 TagecMem; + + //Usb Configdata + UINT8 UsbMassDevNum; + UINT8 UsbLegacySupport; + UINT8 UsbEmul6064; + UINT8 UsbMassResetDelay; + UINT8 UsbNonBoot; + UINT8 UsbEmu1; + UINT8 UsbEmu2; + UINT8 UsbEmu3; + UINT8 UsbEmu4; + UINT8 UsbEmu5; + UINT8 UsbEmu6; + UINT8 UsbEmu7; + UINT8 UsbEmu8; + UINT8 UsbEmu9; + UINT8 UsbEmu10; + UINT8 UsbEmu11; + UINT8 UsbEmu12; + UINT8 UsbEmu13; + UINT8 UsbEmu14; + UINT8 UsbEmu15; + UINT8 UsbEmu16; + UINT8 UsbStackSupport; + + // Console Redirection + UINT8 ConsoleRedirection; + UINT8 FlowControl; + UINT64 BaudRate; + UINT8 TerminalType; + UINT8 LegacyOsRedirection; + UINT8 TerminalResolution; + UINT8 DataBits; + UINT8 Parity; + UINT8 StopBits; + +#ifdef EFI_PCI_IOV_SUPPORT + UINT8 SystemPageSize; + UINT8 ARIEnable; + UINT8 ARIForward; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; +#endif + // + // RAS + // + +// +// Network setup entries - start here <><><><><> +// + UINT8 LegacyPxeRom; + UINT8 EfiNetworkSupport; +// +// Network setup entries - end here <><><><><> +// + +// +// SERIALPORT BAUD RATE: Begin +// + UINT32 SerialBaudRate; +// +// SERIALPORT BAUD RATE: END +// + + UINT8 BootAllOptions; + UINT8 SetShellFirst; + UINT8 ShellEntryTime; + + // + // Overclocking related setup variables + // + UINT8 PlatformOCSupport; + UINT8 FilterPll; + UINT8 OverclockingSupport; + + UINT8 CoreMaxOcRatio; + UINT8 CoreVoltageMode; + UINT16 CoreVoltageOverride; + UINT16 CoreVoltageOffset; + UINT8 CoreVoltageOffsetPrefix; + UINT16 CoreExtraTurboVoltage; + + // + // OC related + // + UINT8 MemoryVoltage; + UINT8 MemoryVoltageDefault; + UINT8 tCL; + + // + // CLR Related + // + UINT8 ClrMaxOcRatio; + UINT8 ClrVoltageMode; + UINT16 ClrVoltageOverride; + UINT16 ClrVoltageOffset; + UINT8 ClrVoltageOffsetPrefix; + UINT16 ClrExtraTurboVoltage; + + // + // Uncore Related + // + UINT16 UncoreVoltageOffset; + UINT8 UncoreVoltageOffsetPrefix; + UINT16 IoaVoltageOffset; + UINT8 IoaVoltageOffsetPrefix; + UINT16 IodVoltageOffset; + UINT8 IodVoltageOffsetPrefix; + + // + // SVID and FIVR Related + // + UINT8 SvidEnable; + UINT16 SvidVoltageOverride; + UINT8 FivrFaultsEnable; + UINT8 FivrEfficiencyEnable; + +// +// UBA_START +// + UINT8 SataInterfaceRAIDMode; + UINT8 sSataInterfaceRAIDMode; +// +// UBA_END +// + UINT16 C01MemoryVoltage; + UINT16 C23MemoryVoltage; + + UINT16 CpuVccInVoltage; + + UINT8 VccIoVoltage; + + UINT16 VariablePlatId; + + //XTU 3.0 + + UINT8 FlexRatioOverrideDefault; + UINT8 RatioLimit1Default; + UINT8 RatioLimit2Default; + UINT8 RatioLimit3Default; + UINT8 RatioLimit4Default; + UINT8 OverclockingLockDefault; + UINT8 DdrRefClkDefault; + UINT8 DdrRatioDefault; + UINT8 tCLDefault; + UINT8 tCWLDefault; + UINT16 tFAWDefault; + UINT16 tRASDefault; + UINT16 tRCDefault; + UINT8 tRCDDefault; + UINT16 tREFIDefault; + UINT16 tRFCDefault; + UINT8 tRPDefault; + UINT8 tRPabDefault; + UINT8 tRRDDefault; + UINT8 tRTPDefault; + UINT8 tWRDefault; + UINT8 tWTRDefault; + UINT8 NModeDefault; + UINT8 CoreMaxOcRatioDefault; + UINT8 CoreVoltageModeDefault; + UINT16 CoreVoltageOverrideDefault; + UINT16 CoreVoltageOffsetDefault; + UINT8 CoreVoltageOffsetPrefixDefault; + UINT16 CoreExtraTurboVoltageDefault; + UINT8 GtOcSupportDefault; + UINT8 GtOcFrequencyDefault; + UINT16 GtExtraTurboVoltageDefault; + UINT16 GtOcVoltageDefault; + UINT8 GtVoltageModeDefault; + UINT16 GtVoltageOverrideDefault; + UINT16 GtVoltageOffsetDefault; + UINT8 GtVoltageOffsetPrefixDefault; + UINT8 ClrMaxOcRatioDefault; + UINT8 ClrVoltageModeDefault; + UINT16 ClrVoltageOverrideDefault; + UINT16 ClrVoltageOffsetDefault; + UINT8 ClrVoltageOffsetPrefixDefault; + UINT16 ClrExtraTurboVoltageDefault; + UINT16 UncoreVoltageOffsetDefault; + UINT8 UncoreVoltageOffsetPrefixDefault; + UINT16 IoaVoltageOffsetDefault; + UINT8 IoaVoltageOffsetPrefixDefault; + UINT16 IodVoltageOffsetDefault; + UINT8 IodVoltageOffsetPrefixDefault; + UINT8 SvidEnableDefault; + UINT16 SvidVoltageOverrideDefault; + UINT8 FivrFaultsEnableDefault; + UINT8 FivrEfficiencyEnableDefault; + UINT16 VrCurrentLimitDefault; + UINT8 EnableGvDefault; + UINT8 TurboModeDefault; + UINT8 PowerLimit1TimeDefault; + UINT16 PowerLimit1Default; + UINT16 PowerLimit2Default; + + + UINT8 RatioLimit1; //ratiolimit handling has changed in SKX. knobs might= need to change too. Will have to revisit again. + UINT8 RatioLimit2; + UINT8 RatioLimit3; + UINT8 RatioLimit4; + UINT8 CpuRatio; // need to understand what is the difference between max= nonturboratio and cpuratio. if cpuratiooverride is 0, then cpuratio is same= as maxnonturboratio. add this to platform cpu policy or socketsetup. + UINT8 CpuRatioOverride; + UINT8 IsTurboRatioDefaultsInitalized; // related to initializing all the= vardefault. is this flow needed for HEDT/intended only for clients? no nee= d for set up creation. + + + UINT8 DdrRefClk; //cant find any in purley. new one? + UINT8 PcieRatioDisabled;//need to check if this is applicable to HEDT. a= lso no need to create a setup variable. + UINT8 NMode ; + + UINT16 GtVoltageOffset; //existing but no set up option + UINT16 VrCurrentLimit;//done + //UINT8 SpdProfileSelected; same as XMPMode + UINT8 NModeSupport; + UINT8 WDTSupportforNextOSBoot; // no setup option needed + UINT16 TimeforNextOSBoot; // no setup optiom needed + UINT8 PlatformUnstable; // no set up option needed. this decides if all = the vardefaults are needed. + UINT8 GtVoltageMode; //existing but no set up option + UINT8 DdrRatio; + UINT8 GtOcFrequency; + UINT16 GtExtraTurboVoltage; //existing but no set up option + UINT16 GtVoltageOverride; //existing but no set up option + UINT8 GtVoltageOffsetPrefix; + UINT8 GtOcSupport; + // + // CPU releated + // + UINT8 FlexOverrideEnable; + UINT8 FlexRatioOverride; + UINT8 PowerLimit3Override; + UINT32 PowerLimit3; + UINT8 PowerLimit3Time; + UINT8 PowerLimit3DutyCycle; + UINT8 PowerLimit3Lock; + UINT8 MemoryVoltageOverride; + + // + // ICC Related + // + UINT8 BClkOverride; + UINT8 BclkAdjustable; + UINT8 DmiPegRatio; + UINT8 ReservedS2; + UINT8 ReservedS3; + + UINT8 StorageOpROMSuppression; + UINT8 RsaSupport; + + UINT8 ReservedS4; + UINT8 ReservedS5; + + // + // PCIe Leaky Bucket Feature (requires Gen4 IP) + // + UINT64 ExpectedBer; + UINT32 Gen12TimeWindow; + UINT8 Gen34TimeWindow; + UINT8 Gen12ErrorThreshold; + UINT8 Gen34ErrorThreshold; + UINT8 Gen34ReEqualization; + UINT8 Gen2LinkDegradation; + UINT8 Gen3LinkDegradation; + UINT8 Gen4LinkDegradation; + + // + // Crash Log Feature + // + UINT8 CrashLogFeature; + UINT8 CrashLogOnAllReset; + UINT8 CrashLogClear; + UINT8 CrashLogReArm; + + // + // Error Control + // + UINT8 Ce2LmLoggingEn; + UINT8 KtiFirstCeLatchEn; + UINT8 PatrolScrubErrorReporting; + UINT8 LlcEwbErrorControl; + UINT8 KcsAccessPolicy; + + // + // Platform Deep S5 Feature + // + UINT8 PlatformDeepS5; + UINT8 DeepS5DelayTime; + + UINT8 EnableClockSpreadSpec; + + // + // TCC Mode + // + UINT8 TccMode; +} SYSTEM_CONFIGURATION; + +typedef struct { + UINT8 FakeItem; +} FAKE_VARSTORE; + +#pragma pack() + +#define EFI_HDD_PRESENT 0x01 +#define EFI_HDD_NOT_PRESENT 0x00 +#define EFI_CD_PRESENT 0x02 +#define EFI_CD_NOT_PRESENT 0x00 + +#define EFI_HDD_WARNING_ON 0x01 +#define EFI_CD_WARNING_ON 0x02 +#define EFI_SMART_WARNING_ON 0x04 +#define EFI_HDD_WARNING_OFF 0x00 +#define EFI_CD_WARNING_OFF 0x00 +#define EFI_SMART_WARNING_OFF 0x00 + + +extern EFI_GUID gMainPkgListGuid; +extern EFI_GUID gAdvancedPkgListGuid; +extern EFI_GUID gTpmPkgListGuid; +extern EFI_GUID gSecurityPkgListGuid; +extern EFI_GUID gBootOptionsPkgListGuid; +extern EFI_GUID gServerMgmtPkgListGuid; + + +#ifndef VFRCOMPILE + +extern EFI_GUID gEfiSetupVariableGuid; +extern EFI_GUID gEfiSetupVariableDefaultGuid; +extern EFI_GUID gEfiGlobalVariableControlGuid; + +typedef struct { + UINT8 ProcessController; +} SYSTEM_CONFIGURATION_CONTROL; + +#endif + +#define SYSTEM_PASSWORD_ADMIN 0 +#define SYSTEM_PASSWORD_USER 1 + +#define PASSWORD_ADMIN_NAME L"AdminName" +#define PASSWORD_USER_NAME L"UserName" + +#endif // #ifndef _SETUP_VARIABLE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h b/= Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h new file mode 100644 index 0000000000..b5c8510f8c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h @@ -0,0 +1,74 @@ +/** @file + uba config database head file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_HOB_H_ +#define _UBA_CONFIG_DATABASE_HOB_H_ + + +#define UBA_CONFIG_HOB_SIGNATURE SIGNATURE_32('U', 'B', 'A', 'H') +#define UBA_CONFIG_HOB_VERSION 0x01 + +#define UBA_BOARD_SIGNATURE SIGNATURE_32('S', 'K', 'U', 'D') +#define UBA_BOARD_VERSION 0x01 + +// +// Interface data between PEI & DXE +// Should keep same align +// +#pragma pack (1) + +typedef struct _UBA_CONFIG_HOB_FIELD { + UINT32 Signature; + UINT32 Version; + EFI_GUID ResId; + UINT64 DataOffset; + UINT32 Size; +} UBA_CONFIG_HOB_FIELD; + +typedef struct _UBA_CONFIG_HOB_HEADER { + UINT32 Signature; + UINT32 Version; + EFI_GUID DataGuid; + UINT32 HobLength; + UINT32 BoardId; + EFI_GUID BoardGuid; + CHAR8 BoardName[16]; + UINT32 DataCount; + UBA_CONFIG_HOB_FIELD HobField[1]; +} UBA_CONFIG_HOB_HEADER; + + +typedef struct _UBA_BOARD_NODE { + UINT32 Signature; + UINT32 Version; + LIST_ENTRY DataLinkHead; + + UINT32 BoardId; + EFI_GUID BoardGuid; + CHAR8 BoardName[16]; + UINT32 DataCount; +} UBA_BOARD_NODE; + +typedef struct _UBA_CONFIG_NODE { + UINT32 Signature; + UINT32 Version; + LIST_ENTRY DataLink; + + EFI_HANDLE Handle; + EFI_GUID ResId; + UINT32 Size; + VOID *Data; +} UBA_CONFIG_NODE; + +#pragma pack () + +#define BOARD_NODE_INSTANCE_FROM_THIS(p) CR(p, UBA_BOARD_NODE, DataL= inkHead, UBA_BOARD_SIGNATURE) +#define CONFIG_NODE_INSTANCE_FROM_THIS(p) CR(p, UBA_CONFIG_NODE, Data= Link, UBA_BOARD_SIGNATURE) + +#endif // _UBA_CONFIG_DATABASE_HOB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h b/Platform= /Intel/WhitleyOpenBoardPkg/Include/IoApic.h new file mode 100644 index 0000000000..47d73172bc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h @@ -0,0 +1,23 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IOAPIC_H_ +#define _IOAPIC_H_ + +#define EFI_IO_APIC_INDEX_OFFSET 0x00 +#define EFI_IO_APIC_DATA_OFFSET 0x10 +#define EFI_IO_APIC_IRQ_ASSERTION_OFFSET 0x20 +#define EFI_IO_APIC_EOI_OFFSET 0x40 + +#define EFI_IO_APIC_ID_REGISTER 0x0 +#define EFI_IO_APIC_ID_BITSHIFT 24 +#define EFI_IO_APIC_VER_REGISTER 0x1 +#define EFI_IO_APIC_BOOT_CONFIG_REGISTER 0x3 +#define EFI_IO_APIC_FSB_INT_DELIVERY 0x1 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSu= pportLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSu= pportLib.h new file mode 100644 index 0000000000..6389c393d6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSupportLi= b.h @@ -0,0 +1,67 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MULTI_PLATFORM_SUPPORT_LIB_H_ +#define _MULTI_PLATFORM_SUPPORT_LIB_H_ + +#define MAX_TEMP_BUFFER 0x5000 +//#define MULTI_PLATFORM_DEBUG TRUE + + + + +/*++ +Description: + + This function finds the matched default data and create GUID hob for it. + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateDefaultVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + + + +/** + Gets a vairable store header from FFS inserted by FCE + + Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + + + @return The start address of VARIABLE_STORE_HEADER *. Null if cannot fin= d it + +**/ + +VOID * FindDefaultHobinFfs ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + + + + + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatform= Hooklib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatformH= ooklib.h new file mode 100644 index 0000000000..d94a483f89 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatformHooklib= .h @@ -0,0 +1,17 @@ +/** @file + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ + +EFI_STATUS +BoardInit ( + ); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClo= cksLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClock= sLib.h new file mode 100644 index 0000000000..0dc9c690fe --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClocksLib.h @@ -0,0 +1,87 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PLATFORM_CLOCKS_LIB__ +#define __PLATFORM_CLOCKS_LIB__ + +// +// Known clock generator types +// +typedef enum { + ClockGeneratorCk410, + ClockGeneratorCk420, + ClockGeneratorCk440, + ClockGeneratorCk505, + ClockGeneratorMax +} CLOCK_GENERATOR_TYPE; + +#define CLOCK_GENERATOR_ADDRESS 0xD2 +// +// Clock generator details table +// +typedef struct { + CLOCK_GENERATOR_TYPE ClockType; + UINT8 ClockId; + UINT8 SpreadSpectrumByteOffset; + UINT8 SpreadSpectrumBitOffset; +} CLOCK_GENERATOR_DETAILS; + +// +// An arbitrary maximum length for clock generator buffers +// +#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20 + +// +// CK410 Definitions +// +#define CK410_GENERATOR_ID 0x65 +#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1 +#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 +#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4 +#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2) + +// +// CK420 Definitions +// +#define CK420_GENERATOR_ID 0x11 // IDT ICS932SQ42= 0B +#define CK420_GENERATOR_SPREAD_SPECTRUM_BYTE 1 +#define CK420_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 + +// +// CK440 Definitions +// +#define CK440_GENERATOR_ID 0x12 +#define CK440_GENERATOR_SPREAD_SPECTRUM_BYTE 6 +#define CK440_GENERATOR_SPREAD_SPECTRUM_BIT BIT2 + +// +// CK505 Definitions +// +#define CK505_GENERATOR_ID 0x26 // Silego SLG505Y= C264B +#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4 +#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1) + +#define CLOCK_GENERATOR_SETTINGS_PLATFORMSRP {0xFF, 0x9E, 0x3F, 0x00, 0x00= , 0x0F, 0x08, 0x31, 0x0A, 0x17, 0xFF, 0xFE} +#define CLOCK_GENERATOR_SETTINGS_PLATFORMDVP {0xFF, 0x9E, 0x3F, 0x00, 0x00= , 0x0F, 0x08, 0x31, 0x0A, 0x17} + +EFI_STATUS +ConfigureClockGenerator ( + IN EFI_PEI_SERVICES **PeiServices, + IN CLOCK_GENERATOR_TYPE ClockType, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN OUT UINT8 *ConfigurationTable, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN BOOLEAN SecondarySmbus + ); + +#define PEI_STALL_RESOLUTION 1 + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformOpr= omPolicyLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Platform= OpromPolicyLib.h new file mode 100644 index 0000000000..16ea3d7493 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformOpromPolic= yLib.h @@ -0,0 +1,83 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLAT_OPROM_ +#define _PLAT_OPROM_ +#include + +typedef enum _OPROM_LOAD_POLICY +{ + DONT_LOAD, + EXCLUSIVE_LOAD, + INCLUSIVE_LOAD +} OPROM_LOAD_POLICY; + +/** + Decide if BIOS embdded option roms should be loaded for a certain PCI de= vice. + + @param PciIo PCI device to return the ROM image for. + + @retval TRUE BIOS embedded option roms should not be loaded for th= e PCI device. + @retval FALSE BIOS embedded option roms could be loaded for the PCI= device. +**/ + +BOOLEAN +PlatformOpromLoadDevicePolicy ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ); + +/** + For devices that support multiple option roms like FCoE, PXE, iSCSI etc.= , this function decides if one of these BIOS embdded option roms should be = loaded for a certain PCI device based on platform choices. + + @param PciHandle PCI device to return the ROM image for. + @param TableIndex The index pointing to the option rom in the platf= orm option rom table for the PCI device. + + @retval FALSE The specific BIOS embedded option rom should not = be loaded for the PCI device. + @retval TRUE The specific BIOS embedded option rom could be lo= aded for a certain PCI device. +**/ + +OPROM_LOAD_POLICY +PlatformOpromLoadTypePolicy ( + IN EFI_HANDLE PciHandle, + IN UINTN TableIndex + ); + +/** + Decide if a PCIe device option rom should be dispacthed. + + @param PciHandle PCI device handle. + + @retval FALSE The specific PCIe option rom should not be dispat= ched for the PCI device. + @retval TRUE The specific PCIe option rom could be dispatched = for a certain PCI device. + +**/ + +BOOLEAN +PlatformOpromDispatchPolicy ( + IN EFI_HANDLE DeviceHandle +); + +/** + Enable the legacy console redirection before dispatch the legacy ORPOM o= r disable the legacy console redirection after dispatch + the legacy ORPOM based on setup option and SOL status. + + @param Mode Subfunction. + @param CheckIsAhciRom If the device is legacy Ahci device. + + @retval + +**/ + +VOID +PlatformOpromLegacyCRPolicy ( + IN UINTN Mode, + IN BOOLEAN CheckIsAhciRom +); + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformSet= upVariableSyncLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Pl= atformSetupVariableSyncLib.h new file mode 100644 index 0000000000..02c8411007 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformSetupVaria= bleSyncLib.h @@ -0,0 +1,60 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PLATFORM_SETUP_VAR_SYNC +#define __PLATFORM_SETUP_VAR_SYNC +#include +#include "Uefi/UefiBaseType.h" + +/** + THis function can sync PC/OEM setup variable value to Rp setup variable = before variable service is ready + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, - The input paramter should be VARIABLE_STORE_= HEADER *VarStoreHeader. + Since we don't know whether SECURE_BOOT_ENABLE= is used, we don't know to include which ***VariableFormat.h + So just use VOID* to pass to platform library + IN BOOLEAN CreateHobDataForRpDefaults - whether need to create a hob for= RP setup variable only, + in normal boot case, we should = set this to TRUE to make sure RP setup variable can always sync latest PC v= ariable value + + + + @return The number of Unicode characters. + +**/ +EFI_STATUS SyncSetupVariable ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, + IN BOOLEAN CreateHobDataForRpDefaults +); + + +/*++ +Description: + + This function finds the matched default data and create GUID hob only fo= r RP variable . + This is used to sync Pc variable to RP variable value + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateRPVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformVar= iableHookLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Platfor= mVariableHookLib.h new file mode 100644 index 0000000000..82582bcd45 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformVariableHo= okLib.h @@ -0,0 +1,47 @@ +/** @file + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + + + + +/*++ +Description: + + This function is a hook for PlatformVariableInitPeiEntry + +--*/ +VOID PlatformVariableHookForEntry( + VOID +); + + +/*++ +Description: + + This function allow platform to generate variable hob base on different = event. + +Arguments: + IN VOID *Interface -point to EFI_PEI_READ_ONLY_VARIABL= E2_PPI + IN OUT UINT8 *phobdata, -pont to hob data + IN OUT UINT16 *pDefaultId -pointer to defautlID + +Returns: + TRUE:platform have its own variable hob that need be createn + FALSE:platform don;t need to create variable hob in this case + + +--*/ +BOOLEAN PlatformVariableHookForHobGeneration( + IN VOID *Interface, + IN OUT UINT8 *phobdata, + IN OUT UINT16 *pDefaultId +); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.h new file mode 100644 index 0000000000..ca8a2994c2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.h @@ -0,0 +1,58 @@ +/** @file + Read FFS Library. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __READ_FFS__ +#define __READ_FFS__ +#include +#include + +#define MAX_COMPRESS_ITEM 196 +#define MAX_FFS_BUFFER_SIZE 8*1024 +#define COMPRESS_DUPLICATE 1 +#define COMPRESS_SINGLE 2 + +#pragma pack(1) +typedef struct { + UINT16 Value; + UINT16 Length; + UINT8 Type; + UINT16 Offset; +} COMPRESS_ITEM; + +typedef struct { + UINT32 Signature; + UINT32 Count; + //COMPRESS_ITEM item[Count]; +} COMPRESS_HOBO_DATA; +#pragma pack() + + +BOOLEAN NormalHobToCompressHob(IN OUT VOID* hobAddr,IN OUT UINTN* size); +BOOLEAN CompressHobToNormalHob(IN OUT VOID* hobAddr,OUT UINTN* size); + +//read a FFS from FV. +UINT8* +PreMemReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN BOOLEAN skipheader + ); + +EFI_STATUS +ReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN OUT VOID *FFSData, + OUT UINT32 *FFSSize, + IN BOOLEAN skipheader + ); +EFI_STATUS ValidateCommonFvHeader ( EFI_FIRMWARE_VOLUME_HEADER = *FwVolHeader ); +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h = b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h new file mode 100644 index 0000000000..43eb60e6ca --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h @@ -0,0 +1,134 @@ +/** @file + This library abstracts read/write access for basic type data those value= s may be + stored into the different media. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_LIB_H_ +#define _SETUP_LIB_H_ + +#include + +typedef struct { + EFI_GUID *GuidValue; + CHAR16 *SetupName; + UINTN VariableSize; +} GROUP_INFO; + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by Guid and OptionNu= mber. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] OptionNumber The option number to retrieve a current value = for. + @param[out] DataType A pointer to basic data type of the retrieved = data. + It is optional. It could be NULL. + @param[in, out] Data A pointer to the buffer to be retrieved. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN OUT VOID *Data, + IN OUT UINTN DataSize + ); + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the data specified by Guid and OptionNumber to the val= ue specified by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] OptionNumber The option number to set a current value f= or. + @param[in] Data A pointer to the buffer to set. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +GetEntireConfig ( + IN OUT SETUP_DATA *SetupData + ); + +/** + Set all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +SetEntireConfig ( + IN SETUP_DATA *SetupData + ); + +/** + Get Specified data in the setup + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. +**/ +EFI_STATUS +EFIAPI +GetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN OUT VOID *Variable + ); + +/** + Set Specified data in the setup + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. +**/ +EFI_STATUS +EFIAPI +SetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN VOID *Variable + ); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpdateL= ib.h new file mode 100644 index 0000000000..291f687db3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpdateLib.h @@ -0,0 +1,38 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_ACPI_UPDATE_LIB_H +#define _PLATFORM_ACPI_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_ACPI_FIX_UPDATE_SIGNATURE SIGNATURE_32 ('A', 'C', 'P', '= F') +#define PLATFORM_ACPI_FIX_UPDATE_VERSION 01 + + +// {81129EF8-391D-4f63-AE99-58517EC077E3} +#define PLATFORM_ACPI_FIX_TABLE_GUID \ +{ 0x81129ef8, 0x391d, 0x4f63, { 0xae, 0x99, 0x58, 0x51, 0x7e, 0xc0, 0x77, = 0xe3 } } + +typedef struct { + UINT32 Signature; + UINT32 Version; + + VOID *TablePtr; + +} ACPI_FIX_UPDATE_TABLE; + +EFI_STATUS +PlatformGetAcpiFixTableDataPointer ( + IN VOID **TablePtr +); + +STATIC EFI_GUID gPlatformAcpiFixTableGuid =3D PLATFORM_ACPI_FIX_TABLE_GUI= D; + +#endif //_PLATFORM_ACPI_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSio= InfoLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSioI= nfoLib.h new file mode 100644 index 0000000000..92b50c78dd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSioInfoLib= .h @@ -0,0 +1,47 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_BOARD_SIO_INFO_H_ +#define _UBA_BOARD_SIO_INFO_H_ + +#include + +#define BOARD_SIO_INFO_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'I', 'O') +#define BOARD_SIO_INFO_DATA_VERSION 01 + +// {32C1F731-C2CD-4325-888B-60A0C3DEBB30} +#define PLATFORM_BOARD_SIO_INFO_DATA_GUID \ +{ 0x32c1f731, 0xc2cd, 0x4325, { 0x88, 0x8b, 0x60, 0xa0, 0xc3, 0xde, 0xbb, = 0x30 } } + +// +// board sio information table +// +typedef struct _PEI_BOARD_SIO_INFO{ + // + // Header information + // + INT32 Signature; + INT32 Version; + // + // SIO initialization table + // + UINT8 SioIndexPort; // SIO Index Port va= lue + UINT8 SioDataPort; // SIO Data Port val= ue + SIO_INDEX_DATA *mSioInitTable; // SIO init table + UINT8 NumSioItems; // Number of items i= n the SIO init table. +} PEI_BOARD_SIO_INFO; + +EFI_STATUS +PlatformGetBoardSioInfo ( + OUT PEI_BOARD_SIO_INFO *BoardSioInfoData +); + +STATIC EFI_GUID gPlatformBoardSioInfoDataGuid =3D PLATFORM_BOARD_SIO_INFO= _DATA_GUID; + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUp= dateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUpd= ateLib.h new file mode 100644 index 0000000000..b5f97c9b1e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUpdateLib= .h @@ -0,0 +1,49 @@ +/** @file + UBA ClockGen Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CLOCKGEN_UPDATE_LIB_H +#define _UBA_CLOCKGEN_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_CLOCKGEN_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'C', 'L', '= K') +#define PLATFORM_CLOCKGEN_UPDATE_VERSION 0x01 + +// {CF3845B1-7EB0-44ef-9D67-A80ECE6FED73} +#define PLATFORM_CLOCKGEN_CONFIG_DATA_GUID \ +{ 0xcf3845b1, 0x7eb0, 0x44ef, { 0x9d, 0x67, 0xa8, 0xe, 0xce, 0x6f, 0xed, 0= x73 } } + +#define PLATFORM_NUMBER_OF_CLOCKGEN_DATA 20 +#define PLATFORM_CLOCKGEN_NO_ID 0xFF + +typedef struct { + UINT32 Signature; + UINT32 Version; + + UINTN IdOffset; // Clockgen ID register offset + UINT8 Id; // Clockgen ID + UINTN DataLength; // Number of clockgen data for wri= te + + UINTN SpreadSpectrumByteOffset; + UINT8 SpreadSpectrumValue; + + UINT8 Data[PLATFORM_NUMBER_OF_CLOCKGEN_DATA]; + +} PLATFORM_CLOCKGEN_UPDATE_TABLE; + + +EFI_STATUS +PlatformUpdateClockgen ( + IN BOOLEAN EnableSpreadSpectrum +); + +STATIC EFI_GUID gPlatformClockgenConfigDataGuid =3D PLATFORM_CLOCKGEN_CON= FIG_DATA_GUID; + +#endif //_UBA_CLOCKGEN_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksCo= nfigLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksCon= figLib.h new file mode 100644 index 0000000000..c4114a0d54 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksConfigLib= .h @@ -0,0 +1,51 @@ +/** @file + UBA Clocks Config Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CLOCKS_CONFIG_LIB_H +#define _UBA_CLOCKS_CONFIG_LIB_H + +#include +#include +#include +#include + +#define PLATFORM_CLOCKS_CONFIG_SIGNATURE SIGNATURE_32 ('P', 'C', 'L', 'K') +#define PLATFORM_CLOCKS_CONFIG_VERSION 01 + +// {34F1B964-49C7-4CB6-B9BD-7043B37C90BE} +#define PLATFORM_CLOCKS_CONFIG_DATA_GUID \ +{ 0x34f1b964, 0x49c7, 0x4cb6, { 0xb9, 0xbd, 0x70, 0x43, 0xb3, 0x7c, 0x90, = 0xbe } } + +typedef +EFI_STATUS +(*CLOCKS_CONFIG_CALLBACK) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + CLOCKS_CONFIG_CALLBACK CallUpdate; + +} PLATFORM_CLOCKS_CONFIG_TABLE; + +EFI_STATUS +ConfigurePlatformClock ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi +); + +STATIC EFI_GUID gPlatformClocksConfigDataGuid =3D PLATFORM_CLOCKS_CONFIG_= DATA_GUID; + +#endif //_UBA_CLOCKS_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInit= Lib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInitLib.h new file mode 100644 index 0000000000..d8c692c17d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInitLib.h @@ -0,0 +1,26 @@ +/** @file + UBA GPIO Initializtion Library Header File. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_INIT_LIB_H +#define _UBA_GPIO_INIT_LIB_H + +#include +#include + +// {9282563E-AE17-4E12-B1DC-070F29F37120} +#define PLATFORM_GPIO_INIT_DATA_GUID { 0x9282563e, 0xae17, 0x4e12, { 0x= b1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } + +EFI_STATUS +PlatformInitGpios ( + VOID +); + +extern EFI_GUID gPlatformGpioInitDataGuid; + +#endif //_UBA_GPIO_INIT_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPlat= formConfig.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPl= atformConfig.h new file mode 100644 index 0000000000..e227a75c94 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPlatformCon= fig.h @@ -0,0 +1,259 @@ +/** @file + UBA GPIO Platform Specific functions Library Header File. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_PLATFORM_CONFIG_LIB_H +#define _UBA_GPIO_PLATFORM_CONFIG_LIB_H + +#include +#include +#include + +#define PLATFORM_GPIO_CONFIG_SIGNATURE SIGNATURE_32 ('P', 'G', 'P', 'O') +#define PLATFORM_GPIO_CONFIG_VERSION 01 + + +// {d2c2adab-80c0-4a13-a0f8-adede1a51740} +#define PLATFORM_GPIO_PLATFORM_CONFIG_DATA_GUID \ +{ 0xd2c2adab, 0x80c0, 0x4a13, { 0xa0, 0xf8, 0xad, 0xed, 0xe1, 0xa5, 0x17, = 0x40 } } + +//Use this define to skip the usage of a gpio in PLATFORM_GPIO_CONFIG_TABLE +#define UNUSED_GPIO 0x0 + +typedef struct _PLATFORM_GPIO_CONFIG_TABLE{ + // + // Header information + // + INT32 Signature; + INT32 Version; + + GPIO_INIT_CONFIG GpioMfgPad; + GPIO_PAD ReservedM; + GPIO_PAD RcvJumper; + + // + // ADR pads + // + GPIO_PAD FmAdrTrigger; + GPIO_PAD AdrEnable; + + // + // OemProcMemInit pad + // + GPIO_PAD ForceTo1SConfigModePad; + + // + // Used by PC Platforms + // + GPIO_PAD QATGpio; + + // + // Used by PC platforms. This is the first GPIO pad of the pad series to= indicate Board ID + // + GPIO_PAD BoardID0Gpio; + + // + // Used to indicate proper pin to for WHEA SCI detection + // + GPIO_PAD WheaSciPad; + + // + // Used to generate CPU HP SMI + // + GPIO_PAD CpuHpSmiPad; + + // + // Used to signal FPGA error + // + GPIO_PAD FpgaErrorSingnalPad1; + + // + // Used to signal FPGA error + // + GPIO_PAD FpgaErrorSingnalPad2; + + // Flash Security override + GPIO_PAD FlashSecOverride; +} PLATFORM_GPIO_CONFIG_TABLE; + + +/** + + Reads GPIO pin to get Flash Security Override jumper status + + @param[out] Jumper - The pointer to the jumper output + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFlashSecOvrdVal ( + OUT UINT32 *Jumper +); +/** + + Reads GPIO pin to get recovery jumper status + + @param[out] RcvJumper - The pointer to the Recovery jumper input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetRcvPadVal ( + OUT UINT32 *RcvJumper +); + + +/** + + Reads GPIO pin to get FM ADR trigger pin + + @param[out] FmAdrTrigger - The pointer to the ADR trigger input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFmAdrTriggerPadVal ( + OUT UINT32 *FmAdrTrigger +); + +/** + + Sets GPIO pin to enable ADR on the board + + @param Set[in] - If TRUE means the pas should go 'high', otherwise 'lo= w' + + @retval Status - Success if GPIO set properly + +**/ +EFI_STATUS +GpioSetAdrEnablePadOutVal ( + IN BOOLEAN Set +); + +/** + + Reads GPIO pin to Force to S1 config mode pad + + @param[out] ForceS1ConfigPad - Input value of the Froce S1 Config pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetForcetoS1ConfigModePadVal ( + OUT UINT32 *ForceS1ConfigPad +); + +/** + + Reads GPIO pin related to QAT + + @param[out] QATPad - Input value of the QAT pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetQATPadVal ( + OUT UINT32 *QATPad +); + + +/** + + Get GPIO pin for SCI detection for WHEA RAS functionality + + @param[out] WheaSciPad - Input value of the Whea SCI pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetWheaSciPad ( + OUT UINT32 *WheaSciPad +); + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 1 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad1 ( + OUT UINT32 *FpgaErrorPad +); + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 2 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad2 ( + OUT UINT32 *FpgaErrorPad +); + +/** + + Get GPIO pin for CPU HP SMI detection for RAS functionality + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetCpuHpSmiPad ( + OUT UINT32 *CpuHpSmiPad +); + + +/** + + Reads GPIO pin that is first bit of the Board ID indication word + + @param[out] BoardID0Gpio - Input value of the first Board ID pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId0PadVal ( + OUT UINT32 *BoardID0Gpio +); + + +/** + + Checks whether the MDF jumper has been set + + @param None + + @retval ManufacturingMode - TRUE when MFG jumper is on, FALSE otherwise + +**/ +BOOLEAN +IsManufacturingMode ( + VOID +); + + +STATIC EFI_GUID gPlatformGpioPlatformConfigDataGuid =3D PLATFORM_GPIO_PLA= TFORM_CONFIG_DATA_GUID; + +#endif //_UBA_GPIO_PLATFORM_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpdateL= ib.h new file mode 100644 index 0000000000..72c3766908 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpdateLib.h @@ -0,0 +1,51 @@ +/** @file + UBA GPIO Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_UPDATE_LIB_H +#define _UBA_GPIO_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_GPIO_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'G', 'P', 'O') +#define PLATFORM_GPIO_UPDATE_VERSION 01 + +// {E02C2982-0009-46f6-AF19-DF52BB9742BF} +#define PLATFORM_GPIO_CONFIG_DATA_GUID \ +{ 0xe02c2982, 0x9, 0x46f6, { 0xaf, 0x19, 0xdf, 0x52, 0xbb, 0x97, 0x42, 0xb= f } } + +#define PLATFORM_NUMBER_OF_GPIO_REGISTERS 20 +#define PLATFORM_END_OF_GPIO_LIST 0xFFFFFFFF + +#define GPIO_NO_OR 0 +#define GPIO_NO_AND 0xFFFFFFFF + + +typedef struct { + UINT32 Register; + UINT32 Value; +} GPIO_DATA; + +typedef struct { + UINT32 Signature; + UINT32 Version; + + GPIO_DATA Gpios[PLATFORM_NUMBER_OF_GPIO_REGISTERS]; + +} PLATFORM_GPIO_UPDATE_TABLE; + + +EFI_STATUS +PlatformUpdateGpios ( + VOID +); + +STATIC EFI_GUID gPlatformGpioConfigDataGuid =3D PLATFORM_GPIO_CONFIG_DATA= _GUID; + +#endif //_UBA_GPIO_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHsioPtss= TableConfigLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHs= ioPtssTableConfigLib.h new file mode 100644 index 0000000000..49204ca2b1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHsioPtssTableCo= nfigLib.h @@ -0,0 +1,52 @@ +/** @file + UBA Hsio Ptss Table Config Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H +#define _UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H + +#include +#include +#include +#include +#include +#include + +#define PLATFORM_HSIO_PTSS_TABLE_SIGNATURE SIGNATURE_32 ('P', 'H', 'P', '= T') +#define PLATFORM_HSIO_PTSS_TABLE_VERSION 01 + +// {47EA4CA7-F89A-42E6-89F0-20F4B72BA616} +#define PLATFORM_HSIO_PTSS_TABLE_GUID \ +{ 0x47ea4ca7, 0xf89a, 0x42e6, { 0x89, 0xf0, 0x20, 0xf4, 0xb7, 0x2b, 0xa6, = 0x16 } } + +typedef +VOID +(*HSIO_PTSS_TABLE_CONFIG_CALLBACK) ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy + +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + HSIO_PTSS_TABLE_CONFIG_CALLBACK CallUpdate; + +} PLATFORM_HSIO_PTSS_CONFIG_TABLE; + +EFI_STATUS +InstallPlatformHsioPtssTable ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy +); + +STATIC EFI_GUID gPlatformHsioPtssTableGuid =3D PLATFORM_HSIO_PTSS_TABLE_G= UID; + +#endif //_UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfi= gLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfigLib= .h new file mode 100644 index 0000000000..dc47de6bd7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfigLib.h @@ -0,0 +1,227 @@ +/** @file + UBA IIO Config Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_IIO_CONFIG_LIB_H +#define _UBA_IIO_CONFIG_LIB_H + +#include +#include + +#include + +#define PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'I',= 'O') +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION 01 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_2 02 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_3 03 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_UNSUPPORTED 0x20 + +// {EB35ED63-EACA-4e29-9516-7EDF1F818837} +#define PLATFORM_IIO_CONFIG_DATA_GUID \ +{ 0xeb35ed63, 0xeaca, 0x4e29, { 0x95, 0x16, 0x7e, 0xdf, 0x1f, 0x81, 0x88, = 0x37 } } + +// {3093F83B-5934-473e-8523-24BF297EE684} +#define PLATFORM_IIO_CONFIG_DATA_GUID_1 \ +{ 0x3093f83b, 0x5934, 0x473e, { 0x85, 0x23, 0x24, 0xbf, 0x29, 0x7e, 0xe6, = 0x84 } } + +// {1C5267A4-634B-4bf2-BFF8-9A1164E6D198} +#define PLATFORM_IIO_CONFIG_DATA_GUID_2 \ +{ 0x1c5267a4, 0x634b, 0x4bf2, { 0xbf, 0xf8, 0x9a, 0x11, 0x64, 0xe6, 0xd1, = 0x98 } } + +// {1E486CCA-048E-4702-B28C-0B677201683A} +#define PLATFORM_IIO_CONFIG_DATA_GUID_3 \ +{ 0x1e486cca, 0x48e, 0x4702, { 0xb2, 0x8c, 0xb, 0x67, 0x72, 0x1, 0x68, 0x3= a } } + +// {6FE6C559-4F35-4111-98E1-332A251512F3} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID \ +{ 0x6fe6c559, 0x4f35, 0x4111, { 0x98, 0xe1, 0x33, 0x2a, 0x25, 0x15, 0x12, = 0xf3 } } + +// {0F722F2A-650F-448a-ABB7-04EECD75BB30} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_1 \ +{ 0xf722f2a, 0x650f, 0x448a, { 0xab, 0xb7, 0x4, 0xee, 0xcd, 0x75, 0xbb, 0x= 30 } } + +// {EBD11A00-8C5C-4f71-BB9E-5394032B01F4} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_2 \ +{ 0xebd11a00, 0x8c5c, 0x4f71, { 0xbb, 0x9e, 0x53, 0x94, 0x3, 0x2b, 0x1, 0x= f4 } } + +// {123BD082-3201-465c-B139-0CB8C77208F8} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_3 \ +{ 0x123bd082, 0x3201, 0x465c, { 0xb1, 0x39, 0xc, 0xb8, 0xc7, 0x72, 0x8, 0x= f8 } } + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF +#define SMB_ADDR_MAX 0xFF +#define SMB_DATA_MAX 0xFF +#define NO_BIF_INPUT 0xFF +#define NOT_EXIST 0xFF + +typedef +EFI_STATUS +(*IIO_VAR_UPDATE_CALLBACK) ( + IN IIO_GLOBALS *IioGlobalData +); + +typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} IIO_BIFURCATION_DATA_ENTRY; + +typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY_EX { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card -= use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension car= d - use to dynamically determine PCIe bifurcation + UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to com= municate to different group of devices + UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to sel= ect the channel that will be used to communicate to the different group of = devices. +} IIO_BIFURCATION_DATA_ENTRY_EX; + +typedef struct _PLATFORM_IIO_SLOT_ENTRY { + UINT8 PortIndex; + UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if= slot implemented + BOOLEAN InterLockPresent; + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; + BOOLEAN Hidden; +} IIO_SLOT_CONFIG_DATA_ENTRY; + +typedef struct _PLATFORM_IIO_SLOT_ENTRY_EX { + UINT8 PortIndex; //( {1,2,3,4} =3D {1A,,1B,,1C,1D} ), ( {5,6,= 7,8} =3D {2A,2B,2C,2D} ), ( {9,10,11,12} =3D {3A,3B,3C,3D}),... + UINT16 SlotNumber; // 0xff if slot not implemented , Slot numbe= r if slot implemented + BOOLEAN InterLockPresent; // Yes / No + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; // Yes / No + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; // Yes / No + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled + BOOLEAN Hidden; // deprecate this as it should be purely bas= ed on bifurcation + + BOOLEAN CommonClock; // Yes / No - whether the both side of the = link are in same clock domain or not + BOOLEAN SRIS; // Yes / No - in case of distinct clocking = whether the separate ref. clk supports SSC or not + BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is conne= cted to Uplink port of another chip + BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to b= ifurcate the retimers explicitly + UINT8 RetimerSMBusAddress; // SMBus address to read the retimer status= and bifurcate if required + UINT8 RetimerSMBusChannel; // SMBus Mux channel to read the retimer st= atus and bifurcate if required + UINT8 RetimerWidth; // Retimer width to determine adjacent Reti= mers for the same PCIe slot + UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to comm= unicate to different group of devices + UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to sele= ct the channel that will be used to communicate to the different group of d= evices. + + BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension car= d which are supported in board thro' SMBus address (typically BW5) + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card= - use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension c= ard - use to dynamically determine PCIe bifurcation + BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension c= ard (BW5), or No + UINT8 ExtnCardRetimerSMBusAddress; // SMBus address to read the retime= r status and bifurcate if required + UINT8 ExtnCardRetimerWidth; // use to determine adjacent Retimers to= the x16 PCIe slot on which this Riser is mounted + BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indic= ates slot in which this PCIe extn. Card is mounted + UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled + UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled + + UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercept= ed between the PCIe port and the slot device. Retimer may appear mutually = exclusive. +} IIO_SLOT_CONFIG_DATA_ENTRY_EX; + + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY *IioSlotTablePtr; + UINTN IioSlotTableSize; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE; + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr; + UINTN IioSlotTableSize; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX; + +typedef struct { + UINT8 MuxSmbAddress; + UINT8 MuxSmbChannel; + UINT8 SmbAddress0; + UINT8 SmbAddress1; + UINT8 RegOffset; + UINT8 RegValue; +} MUX_SMB_ADDR; + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_3 { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr; + UINTN IioSlotTableSize; + MUX_SMB_ADDR *RetimerInitTablePtr; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE_3; + +typedef struct { + UINT8 PortHide[8]; +} PCIE_PORT_HIDE_TABLE; + +EFI_STATUS +PlatformIioConfigInit ( + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +); + +EFI_STATUS +PlatformIioConfigInit2 ( + IN UINT8 SkuPersonalityType, + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +); + +EFI_STATUS +PlatformUpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData +); + +EFI_STATUS +PlatformUpdateIioConfig_EX ( + IN IIO_GLOBALS *IioGlobalData +); + +STATIC EFI_GUID gPlatformIioConfigDataGuid =3D PLATFORM_IIO_CONFIG_DATA_G= UID; +STATIC EFI_GUID gPlatformIioConfigDataGuid_1 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_1; +STATIC EFI_GUID gPlatformIioConfigDataGuid_2 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_2; +STATIC EFI_GUID gPlatformIioConfigDataGuid_3 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_3; + +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid =3D PLATFORM_IIO_CONFIG_DAT= A_DXE_GUID; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_1 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_1; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_2 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_2; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_3 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_3; + +#endif //_UBA_IIO_CONFIG_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioPortB= ifurcationInitLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Ub= aIioPortBifurcationInitLib.h new file mode 100644 index 0000000000..874be715f9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioPortBifurcat= ionInitLib.h @@ -0,0 +1,47 @@ +/** @file + UBA Iio Port Bifurcation Init Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_IIO_PORT_BIFURCATION_INIT_LIB_H +#define _UBA_IIO_PORT_BIFURCATION_INIT_LIB_H + +#include +#include +#include +#include + +#define IIO_PORT_BIFURCATION_INIT_SIGNATURE SIGNATURE_32 ('P', 'B', 'I', = 'F') +#define IIO_PORT_BIFURCATION_INIT_VERSION 01 + +// {853E5958-B3D6-4D98-A77C-100BB4ED940B} +#define IIO_PORT_BIFURCATION_INIT_GUID \ +{ 0x853e5958, 0xb3d6, 0x4d98, { 0xa7, 0x7c, 0x10, 0xb, 0xb4, 0xed, 0x94, 0= xb } } + +typedef +VOID +(*IIO_PORT_BIFURCATION_INIT_CALLBACK) ( + IN IIO_GLOBALS *IioGlobalData +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + IIO_PORT_BIFURCATION_INIT_CALLBACK CallUpdate; + +} IIO_PORT_BIFURCATION_INIT_TABLE; + +EFI_STATUS +IioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +); + +STATIC EFI_GUID gIioPortBifurcationInitDataGuid =3D IIO_PORT_BIFURCATION_= INIT_GUID; + +#endif //_UBA_IIO_PORT_BIFURCATION_INIT_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpd= ateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpdat= eLib.h new file mode 100644 index 0000000000..8984a70f9f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpdateLib.h @@ -0,0 +1,115 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_OPTION_ROM_UPDATE_LIB_ +#define _PLATFORM_OPTION_ROM_UPDATE_LIB_ + + +#include +#include + +#include +#include +#include "OnboardNicStructs.h" + +#define PLATFORM_OPTION_ROM_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'B', 'D',= 'S') +#define PLATFORM_OPTION_ROM_UPDATE_VERSION 01 + + +// {371BD79C-DE79-4c5f-AA2B-BC9EBEFA988F} +STATIC EFI_GUID gPlatformOptionRomUpdateConfigDataGuid =3D +{ 0x371bd79c, 0xde79, 0x4c5f, { 0xaa, 0x2b, 0xbc, 0x9e, 0xbe, 0xfa, 0x98, = 0x8f } }; + + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PC_PCI_OPTION_ROM_TABLE; + + +typedef +BOOLEAN +(*PLATFORM_PCIE_ROOT_PORT_CHECK_CALLBACK) ( + IN UINTN Bus, + IN UINT32 PcieSlotOpromBitMap + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_OPTIONROM_TABLE) ( + IN PC_PCI_OPTION_ROM_TABLE **OptionRomTable + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_NIC_SETUP_CONFIG) ( + IN NIC_SETUP_CONFIGURATION_STUCT **NicSetupConfigTable, + IN UINTN *NumOfConfig + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_NIC_CAPABILITY_TABLE) ( + IN NIC_OPTIONROM_CAPBILITY_STRUCT **NicCapabilityTable, + IN UINTN *NumOfNicCapTable + ); + +typedef +EFI_STATUS +(*PLATFORM_SETUP_PCIE_SLOT_NUMBER ) ( + OUT UINT8 *PcieSlotItemCtrl + ); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + + PLATFORM_PCIE_ROOT_PORT_CHECK_CALLBACK CallCheckRootPort; + PLATFORM_GET_OPTIONROM_TABLE GetOptionRomTable; + PLATFORM_GET_NIC_SETUP_CONFIG GetNicSetupConfigTable; + PLATFORM_GET_NIC_CAPABILITY_TABLE GetNicCapabilityTable; + PLATFORM_SETUP_PCIE_SLOT_NUMBER SetupSlotNumber; + +} PLATFORM_OPTION_ROM_UPDATE_DATA; + + +BOOLEAN +PlatformCheckPcieRootPort ( + IN UINTN Bus, + IN UINT32 PcieSlotOpromBitMap +); + +EFI_STATUS +PlatformGetOptionRomTable ( + IN PC_PCI_OPTION_ROM_TABLE **OptionRomTable +); + +EFI_STATUS +PlatformGetNicSetupConfigTable ( + IN NIC_SETUP_CONFIGURATION_STUCT **NicSetupConfigTable, + IN UINTN *NumOfConfig + ); + +EFI_STATUS +PlatformGetNicCapabilityTable ( + IN NIC_OPTIONROM_CAPBILITY_STRUCT **NicCapabilityTable, + IN UINTN *NumOfNicCapTable + ); + +EFI_STATUS +PlatformSetupPcieSlotNumber ( + OUT UINT8 *PcieSlotItemCtrl +); + +#endif //_PLATFORM_OPTION_ROM_UPDATE_LIB_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdat= eLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdateLib= .h new file mode 100644 index 0000000000..23e4c146b7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdateLib.h @@ -0,0 +1,44 @@ +/** @file + UBA PCD Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PCD_UPDATE_LIB_H +#define _UBA_PCD_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_PCD_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'P', 'C', 'D') +#define PLATFORM_PCD_UPDATE_VERSION 01 + +// {D5081573-B3B6-4a1f-9FBC-C3DEDA04CD49} +#define PLATFORM_PCD_CONFIG_DATA_GUID \ +{ 0xd5081573, 0xb3b6, 0x4a1f, { 0x9f, 0xbc, 0xc3, 0xde, 0xda, 0x4, 0xcd, 0= x49 } } + +typedef +EFI_STATUS +(*PCD_UPDATE_CALLBACK) ( + VOID +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + PCD_UPDATE_CALLBACK CallUpdate; + +} PLATFORM_PCD_UPDATE_TABLE; + +EFI_STATUS +PlatformUpdatePcds ( + VOID +); + +STATIC EFI_GUID gPlatformPcdConfigDataGuid =3D PLATFORM_PCD_CONFIG_DATA_G= UID; + +#endif //_UBA_PCD_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarly= UpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarl= yUpdateLib.h new file mode 100644 index 0000000000..f6bcd535cb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarlyUpdateL= ib.h @@ -0,0 +1,63 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_PCH_EARLY_UPDATE_LIB_H +#define _PLATFORM_PCH_EARLY_UPDATE_LIB_H + + +#include +#include + +#include + +#define PLATFORM_PCH_EARLY_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'P', 'C', = 'H') +#define PLATFORM_PCH_EARLY_UPDATE_VERSION 01 + + +// {1763F1D2-6A47-43f8-8279-3765A6929060} +#define PLATFORM_PCH_EARLY_CONFIG_DATA_GUID \ +{ 0x1763f1d2, 0x6a47, 0x43f8, { 0x82, 0x79, 0x37, 0x65, 0xa6, 0x92, 0x90, = 0x60 } } + + +typedef +EFI_STATUS +(*PLATFORM_PCH_LAN_CONFIG) ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +typedef +EFI_STATUS +(*PLATFORM_EARLY_INIT_HOOK) ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + + PLATFORM_PCH_LAN_CONFIG ConfigLan; + PLATFORM_EARLY_INIT_HOOK InitLateHook; + +} PLATFORM_PCH_EARLY_UPDATE_TABLE; + + +EFI_STATUS +PlatformPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +EFI_STATUS +PlatformInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + + +STATIC EFI_GUID gPlatformPchEarlyConfigDataGuid =3D PLATFORM_PCH_EARLY_CO= NFIG_DATA_GUID; + +#endif //_PLATFORM_PCH_EARLY_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcieBifu= rcationUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Uba= PcieBifurcationUpdateLib.h new file mode 100644 index 0000000000..e8a64a7a10 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcieBifurcation= UpdateLib.h @@ -0,0 +1,130 @@ +/** @file + PCH PCIe Bifurcation Update Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PCIE_BIFURCATION_UPDATE_LIB_H +#define _UBA_PCIE_BIFURCATION_UPDATE_LIB_H + +#include +#include +#include + +#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_SIGNATURE SIGNATURE_32 ('P',= 'P', 'C', 'I') +#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_VERSION 01 + +typedef struct { + UINT8 PortIndex; + UINT16 SlotNumber; // 0xff if slot not implemented , Slot numbe= r if slot implemented + BOOLEAN InterLockPresent; // Yes / No + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; // Yes / No + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; // Yes / No + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled + BOOLEAN Hidden; // deprecate this as it should be purely bas= ed on bifurcation + + BOOLEAN CommonClock; // Yes / No - whether the both side of the = link are in same clock domain or not + BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is conne= cted to Uplink port of another chip + BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to b= ifurcate the retimers explicitly + UINT8 RetimerSMBusAddress; // SNBus address to read the retimer status= and bifurcate if required + + BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension car= d which are supported in board thro' SMBus address (typically BW5) + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card= - use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SNBus address for the PCIe extension c= ard - use to dynamically determine PCIe bifurcation + BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension c= ard (BW5), or No + UINT8 ExtnCardRetimerSMBusAddress; // SNBus address to read the retime= r status and bifurcate if required + BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indic= ates slot in which this PCIe extn. Card is mounted + UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled + UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled + + UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercept= ed between the PCIe port and the slot device. Retimer may appear mutually = exclusive. +} PCH_SLOT_CONFIG_DATA_ENTRY_EX; + +// {187576ac-fec1-41bf-91f6-7d1ace7f2bee} +#define PLATFORM_UBA_PCIE_BIFURCATION_GUID \ +{ 0x187576ac, 0xfec1, 0x41bf, { 0x91, 0xf6, 0x7d, 0x1a, 0xce, 0x7f, 0x2b, = 0xee } } + +typedef +EFI_STATUS +(*PCIE_BIFURCATION_UPDATE_CALLBACK) ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +); + +typedef struct _PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE{ + UINT32 Signature; + UINT32 Version; + PCIE_BIFURCATION_UPDATE_CALLBACK CallPcieBifurcationUpdate; +} PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF +#define SMB_ADDR_MAX 0xFF +#define NO_BIF_INPUT 0xFF +#define PORT_0_INDEX 0 +#define PORT_1_INDEX 1 +#define PORT_2_INDEX 2 +#define PORT_3_INDEX 3 +#define PORT_4_INDEX 4 +#define PORT_5_INDEX 5 +#define PORT_6_INDEX 6 +#define PORT_7_INDEX 7 +#define PORT_8_INDEX 8 +#define PORT_9_INDEX 9 +#define PORT_10_INDEX 10 +#define PORT_11_INDEX 11 +#define PORT_12_INDEX 12 +#define PORT_13_INDEX 13 +#define PORT_14_INDEX 14 +#define PORT_15_INDEX 15 +#define PORT_16_INDEX 16 // Added dummy ports(16-27) TODO_FHF +#define PORT_17_INDEX 17 +#define PORT_18_INDEX 18 +#define PORT_19_INDEX 19 +#define PORT_20_INDEX 20 +#define PORT_21_INDEX 21 +#define PORT_22_INDEX 22 +#define PORT_23_INDEX 23 +#define PORT_24_INDEX 24 +#define PORT_25_INDEX 25 +#define PORT_26_INDEX 26 +#define PORT_27_INDEX 27 + +//------------------------------------------------------------------------= ----------- +// PCIE port index for SKX +//------------------------------------------------------------------------= ------------ +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +EFI_STATUS +PlatformGetPchPcieBifurcationConfig ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +); +STATIC EFI_GUID gPlatformUbaPcieBifurcationGuid =3D PLATFORM_UBA_PCIE_BIF= URCATION_GUID; + +#endif //_UBA_PCIE_BIFURCATION_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.h new file mode 100644 index 0000000000..429e63e6ec --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.h @@ -0,0 +1,25 @@ +/** @file + Uba Liarary Definition Header File. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PLAT_LIB_H_ +#define _UBA_PLAT_LIB_H_ + +#include "UbaAcpiUpdateLib.h" +#include "UbaOpromUpdateLib.h" +#include "UbaPchEarlyUpdateLib.h" +#include "UbaClkGenUpdateLib.h" +#include "UbaGpioUpdateLib.h" +#include "UbaPcdUpdateLib.h" +#include "UbaSoftStrapUpdateLib.h" +#include "UbaIioConfigLib.h" +#include "UbaSlotUpdateLib.h" +#include "UbaSystemBoardInfoLib.h" +#include "UbaSystemConfigUpdateLib.h" + +#endif // _UBA_PLAT_LIB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpdateL= ib.h new file mode 100644 index 0000000000..54272ae2d2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpdateLib.h @@ -0,0 +1,124 @@ +/** @file + UBA Slot Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SLOT_UPDATE_LIB_H +#define _UBA_SLOT_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_SLOT_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'S', 'L', 'T') +#define PLATFORM_SLOT_UPDATE_VERSION 01 + +// {BE1CC570-03FC-4a44-8068-5B6E36CAEBB2} +#define PLATFORM_SLOT_DATA_GUID \ +{ 0xbe1cc570, 0x03fc, 0x4a44, { 0x80, 0x68, 0x5b, 0x6e, 0x36, 0xca, 0xeb, = 0xb2 } } + +// {226763AE-972C-4e3c-80D1-73B25E8CBBA3} +#define PLATFORM_SLOT_DATA_GUID2 \ +{ 0x226763ae, 0x972c, 0x4e3c, { 0x80, 0xd1, 0x73, 0xb2, 0x5e, 0x8c, 0xbb, = 0xa3 } }; + +// {56F676D3-24DF-4c77-A336-009DAE693598} +#define PLATFORM_SLOT_DATA_GUID2_1 \ +{ 0x56f676d3, 0x24df, 0x4c77, { 0xa3, 0x36, 0x01, 0x9d, 0xae, 0x69, 0x35, = 0x98 } }; + + +// {B93613E1-48F0-4b32-B3A8-4FEDFC7C1365} +#define PLATFORM_SLOT_DATA_DXE_GUID \ +{ 0xb93613e1, 0x48f0, 0x4b32, { 0xb3, 0xa8, 0x4f, 0xed, 0xfc, 0x7c, 0x13, = 0x65 } } + +// {8185B70E-9A20-4fc4-A1D6-77D54A736518} +#define PLATFORM_SLOT_DATA_DXE_GUID2 \ +{ 0x8185b70e, 0x9a20, 0x4fc4, { 0xa1, 0xd6, 0x77, 0xd5, 0x4a, 0x73, 0x65, = 0x18 } }; + +// {A87C540B-3D69-4c3b-B7F7-6383589C21CE} +#define PLATFORM_SLOT_DATA_DXE_GUID2_1 \ +{ 0xa87c540b, 0x3d69, 0x4c3b, { 0xb7, 0xf7, 0x63, 0x83, 0x58, 0x9c, 0x21, = 0xce } }; + +// {B4CB70B3-558D-4478-84CA-22616034EA16} +#define PLATFORM_PCI_SLOT_IMPLEMENTED_GUID \ +{ 0xb4cb70b3, 0x558d, 0x4478, { 0x84, 0xca, 0x22, 0x61, 0x60, 0x34, 0xea, = 0x16 } }; + +typedef struct _IIO_BROADWAY_ADDRESS_DATA_ENTRY { + UINT8 Socket; + UINT8 IouNumber; + UINT8 BroadwayAddress; // 0xff, no override bifurcation settings. + // 0-2 BW5 card can be present +} IIO_BROADWAY_ADDRESS_DATA_ENTRY; + +typedef +UINT8 +(*PLATFORM_GET_IOU_SETTING) ( + IN UINT8 IOU2Data +); + +typedef +UINT8 +(*PLATFORM_GET_IOU2_SETTING) ( + IN UINT8 SkuPersonalityType, + IN UINT8 IOU2Data +); + +typedef struct _PLATFORM_SLOT_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + IIO_BROADWAY_ADDRESS_DATA_ENTRY *BroadwayTablePtr; + PLATFORM_GET_IOU_SETTING GetIOU2Setting; + UINT8 FlagValue; +} PLATFORM_SLOT_UPDATE_TABLE; + +typedef struct _PLATFORM_SLOT_UPDATE_TABLE2 { + UINT32 Signature; + UINT32 Version; + IIO_BROADWAY_ADDRESS_DATA_ENTRY *BroadwayTablePtr; + PLATFORM_GET_IOU_SETTING GetIOU0Setting; + UINT8 FlagValue; + PLATFORM_GET_IOU2_SETTING GetIOU2Setting; +} PLATFORM_SLOT_UPDATE_TABLE2; + +typedef struct _PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + UINT8 *SlotImplementedTableDataPtr; +} PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE; + +EFI_STATUS +PlatformGetSlotTableData ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU2Setting, + IN OUT UINT8 *FlagValue +); + +EFI_STATUS +PlatformGetSlotTableData2 ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU0Setting, + IN OUT UINT8 *FlagValue, + IN OUT UINT8 *IOU2Setting, + IN UINT8 SkuPersonalityType +); + +EFI_STATUS +PlatformPchGetPciSlotImplementedTableData ( + IN OUT UINT8 **SlotImplementedTable +); + +STATIC EFI_GUID gPlatformSlotDataGuid =3D PLATFORM_SLOT_DATA_GUID; +STATIC EFI_GUID gPlatformSlotDataGuid2 =3D PLATFORM_SLOT_DATA_GUID2; +STATIC EFI_GUID gPlatformSlotDataGuid2_1 =3D PLATFORM_SLOT_DATA_GUID2_1; + + +STATIC EFI_GUID gPlatformSlotDataDxeGuid =3D PLATFORM_SLOT_DATA_DXE_GUID; +STATIC EFI_GUID gPlatformSlotDataDxeGuid2 =3D PLATFORM_SLOT_DATA_DXE_GUID= 2; +STATIC EFI_GUID gPlatformSlotDataDxeGuid2_1 =3D PLATFORM_SLOT_DATA_DXE_GU= ID2_1; + +STATIC EFI_GUID gPlatformPciSlotImplementedGuid =3D PLATFORM_PCI_SLOT_IMP= LEMENTED_GUID; + + +#endif //_UBA_SLOT_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftStra= pUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftSt= rapUpdateLib.h new file mode 100644 index 0000000000..a790b7c55a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftStrapUpdate= Lib.h @@ -0,0 +1,57 @@ +/** @file + UBA PCH Softstrap Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SOFT_STRAP_UPDATE_LIB_H +#define _UBA_SOFT_STRAP_UPDATE_LIB_H + +#include +#include +#include + +#define PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'S', 'T',= 'P') +#define PLATFORM_SOFT_STRAP_UPDATE_VERSION 02 + +// {F06383FE-54BD-4ae1-9C99-1DC83B6A7277} +#define PLATFORM_PCH_SOFTSTRAP_CONFIG_DATA_GUID \ +{ 0xf06383fe, 0x54bd, 0x4ae1, { 0x9c, 0x99, 0x1d, 0xc8, 0x3b, 0x6a, 0x72, = 0x77 } } + +STATIC EFI_GUID gPlatformPchSoftStrapConfigDataGuid =3D PLATFORM_PCH_SOFT= STRAP_CONFIG_DATA_GUID; + +typedef struct _PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY { + UINT8 SoftStrapNumber; + UINT8 BitfieldOffset; + UINT8 BitfieldLength; + UINT32 Value; +} PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY; + +typedef +VOID +(*PLATFORM_SPECIFIC_PCH_SOFTSTRAP_UPDATE) ( + IN UINT8 *FlashDescriptorCopy + ); + +typedef struct { + UINT32 Signature; + UINT32 Version; + PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY *PchSoftStrapTablePtr; + PLATFORM_SPECIFIC_PCH_SOFTSTRAP_UPDATE PchSoftStrapPlatformSpecificUpda= te; +} PLATFORM_PCH_SOFTSTRAP_UPDATE; + + +EFI_STATUS +GetPchSoftSoftStrapTable ( + IN VOID **PchSoftStrapTable + ); + +VOID +PlatformSpecificPchSoftStrapUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ); + +#endif //_UBA_SOFT_STRAP_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemBo= ardInfoLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystem= BoardInfoLib.h new file mode 100644 index 0000000000..e4c980e170 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemBoardInfo= Lib.h @@ -0,0 +1,36 @@ +/** @file + UBA System Board Info Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SYSTEM_BOARD_INFO_LIB_H +#define _UBA_SYSTEM_BOARD_INFO_LIB_H + +#include +#include +#include + +#define SYSTEM_SYSTEM_BOARD_INFO_SIGNATURE SIGNATURE_32 ('I', 'N', 'F', '= O') +#define SYSTEM_SYSTEM_BOARD_INFO_VERSION 01 + +typedef DXE_SYSTEM_BOARD_INFO *(*SYSTEM_BOARD_INFO_CALLBACK) (); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + SYSTEM_BOARD_INFO_CALLBACK CallUpdate; +} SYSTEM_BOARD_INFO_DATA; + +EFI_STATUS +GetSystemBoardInfo ( + IN OUT DXE_SYSTEM_BOARD_INFO **SystemboardInfoTableBuffer + ); + +extern EFI_GUID gSystemBoardInfoConfigDataGuid; + +#endif //_UBA_SYSTEM_BOARD_INFO_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemCo= nfigUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSys= temConfigUpdateLib.h new file mode 100644 index 0000000000..fd8f30daee --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemConfigUpd= ateLib.h @@ -0,0 +1,42 @@ +/** @file + UBA System Config Update Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ +#define _UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ + +#include +#include + +#include + +#define SYSTEM_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('S', 'C', 'O', 'N') +#define SYSTEM_CONFIG_UPDATE_VERSION 01 + +STATIC EFI_GUID gSystemConfigUpdateDataGuid =3D +{ 0x41037136, 0x8834, 0x4F35, { 0xBB, 0x10, 0x28, 0x0, 0x87, 0xAD, 0xB2, 0= x22 } }; + +typedef +VOID +(*IIO_DEFAULT_CONFIG_UPDATE_CALLBACK) ( + IN SYSTEM_CONFIGURATION *Default + ); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + IIO_DEFAULT_CONFIG_UPDATE_CALLBACK CallUpdateIioConfig; +} SYSTEM_CONFIG_UPDATE_DATA; + +EFI_STATUS +UpdateIioDefaultConfig ( + IN SYSTEM_CONFIGURATION *Default + ); + +#endif //_UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpd= ateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpdat= eLib.h new file mode 100644 index 0000000000..96cabc7dd8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpdateLib.h @@ -0,0 +1,51 @@ +/** @file + UBA USB OC Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_USBOC_UPDATE_LIB_H +#define _UBA_USBOC_UPDATE_LIB_H + +#include +#include +#include +#include + +#define PLATFORM_USBOC_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'U', 'S', 'B') +#define PLATFORM_USBOC_UPDATE_VERSION 02 + +// {88238275-5922-46b6-9e35-656df55df44c} +#define PEI_PLATFORM_USBOC_CONFIG_DATA_GUID \ +{ 0x88238275, 0x5922, 0x46f6, { 0x9e, 0x35, 0x65, 0x6d, 0xf5, 0x5d, 0xf4, = 0x4c } } +// {2638009e-3850-4e4b-b05d-042a32dbb9d1} +#define DXE_PLATFORM_USBOC_CONFIG_DATA_GUID \ +{ 0x2638009e, 0x3850, 0x4e4b, { 0xb0, 0x5d, 0x04, 0x2a, 0x32, 0xdb, 0xb9, = 0xd1 } } + +typedef +EFI_STATUS +(*USBOC_UPDATE_CALLBACK) ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +); + +typedef struct _PLATFORM_USBOC_UPDATE_TABLE{ + UINT32 Signature; + UINT32 Version; + USBOC_UPDATE_CALLBACK CallUsbOcUpdate; +} PLATFORM_USBOC_UPDATE_TABLE; + +EFI_STATUS +PlatformGetUsbOcMappings ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +); +STATIC EFI_GUID gPeiPlatformUbaOcConfigDataGuid =3D PEI_PLATFORM_USBOC_CO= NFIG_DATA_GUID; +STATIC EFI_GUID gDxePlatformUbaOcConfigDataGuid =3D DXE_PLATFORM_USBOC_CO= NFIG_DATA_GUID; + +#endif //_UBA_USBOC_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h= b/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h new file mode 100644 index 0000000000..b9f7acdc86 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h @@ -0,0 +1,98 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ONBOARD_NIC_STRUCTS_H +#define _ONBOARD_NIC_STRUCTS_H + +#include + +#pragma pack(1) +typedef struct { + + NIC_TYPE NicType; //Onboard or IO modue? + UINT8 NicIndex; //Nic index in setup page, 1 for Nic = 1, 2 for Nic 2..... + // + //Parent + // + UINT8 RootPortBusNo; //Who is connected to? + UINT8 RootPortDevNo; + UINT8 RootPortFunNo; + + // + //Nic controller for Onboard Nic + // + UINT16 NicVID; //Vendor ID + UINT16 NicDID; //Device ID + UINT8 PortNumbers; //How many ports inside NIC? + UINT8 DescriptionIndex; //Index to Nic description list + + // + //Disable Method for Onboard Nic + // + UINT8 IsGpioCtrl; //Disable by Gpio? + UINT32 GpioForDev; //Ctrl Gpio Pin number for device + UINT8 GpioForDevValue; //what value is used to enable? + + UINT32 PortEnableGPIO[4]; //Ctrl Gpio Pin number for this port + UINT8 PortEnableGPIOValue[4];//what value is used to enable the port + UINT8 IsPchNIC; + +} NIC_SETUP_CONFIGURATION_STUCT; + +typedef struct { + UINT16 NicDID; // Device ID + UINT16 SubDID; // Subsystem ID, if preset to 0xFFFF, th= en negore this field during detection + UINT8 NIC10Gb; // 10Gbe Pxe Seupported + UINT8 PXE_Support; // Pxe supported? + UINT8 iSCSI_Support; // iScsi supported? + UINT8 FCoE_Support; // FCoe supported? + UINT8 InfB_Support; // InfiniBand supported? + UINT8 PchNIC; //PCH integrated NIC? +} NIC_OPTIONROM_CAPBILITY_STRUCT; + +typedef struct { + UINT16 IOM1DID; //Device ID for IOM1 + UINT16 IOM1SubDID; //Subsystem ID for IOM1 + UINT16 IOM2DID; //Device ID for IOM2 + UINT16 IOM2SubDID; //Subsystem ID for IOM2 + UINT16 IOM3DID; //Device ID for IOM3 + UINT16 IOM3SubDID; //Subsystem ID for IOM3 + UINT16 IOM4DID; //Device ID for IOM4 + UINT16 IOM4SubDID; //Subsystem ID for IOM4 +} IOMS_NV_VARIABLE; + +typedef struct { + UINT8 PXE10GPreValue; + UINT8 PXE1GPreValue; + UINT8 Reserved[6]; +} PXE_PREVIOUS_SETTINGS; + +#pragma pack() + +#define NIC_CHARACTER_NUMBER_FOR_VALUE 30 + +#define CPU0_IIO_BUS 0x00 +#define IIO_PCIE_PORT_1A_DEV 0x1 +#define IIO_PCIE_PORT_1A_FUN 0x0 +#define IIO_PCIE_PORT_1B_DEV 0x1 +#define IIO_PCIE_PORT_1B_FUN 0x1 +#define IIO_PCIE_PORT_2A_DEV 0x2 +#define IIO_PCIE_PORT_2A_FUN 0x0 +#define IIO_PCIE_PORT_3A_DEV 0x3 +#define IIO_PCIE_PORT_3A_FUN 0x0 +#define IIO_PCIE_PORT_3C_DEV 0x3 +#define IIO_PCIE_PORT_3C_FUN 0x2 + +#define OB_NIC_POWERVILLE_DID 0x1521 + +#define INTEL_MAC_ADDRESS_REG 0x5400 + +#define VENDOR_ID_MELLANOX 0x15B3 +#define DEVICE_ID_MELLANOX 0x1003 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h = b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h new file mode 100644 index 0000000000..a46ed4d1e1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h @@ -0,0 +1,10 @@ +/** @file + Intermediate header file. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSetupVariableLbg.h" diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg= .h b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg.h new file mode 100644 index 0000000000..f87999a71f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg.h @@ -0,0 +1,372 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_VARIABLE_LBG_H_ +#define _SETUP_VARIABLE_LBG_H_ + +// for PCH_RC_CONFIGURATION +extern EFI_GUID gEfiPchSetupGuid; +#define PCH_SETUP_NAME L"PchSetup" + + +#include +#define HDAUDIO_FEATURES 3 +#define HDAUDIO_PP_MODULES 2 + +#define SATA_MODE_AHCI 0 +#define SATA_MODE_RAID 1 +#define SATA_TEST_MODE_ENABLE 1 + + +/// sSATA max ports for Wellsburg +#define PCH_MAX_SSATA_PORTS 6 + +#pragma pack(1) +typedef struct { + UINT8 Dwr_Enable; + UINT8 Dwr_Stall; + UINT8 Dwr_BmcRootPort; + + UINT8 DwrEn_PMCGBL; + UINT8 DwrEn_MEWDT; + UINT8 DwrEn_IEWDT; + + UINT8 Dwr_MeResetPrepDone; + UINT8 Dwr_IeResetPrepDone; + + // + // PCH_DEVICE_ENABLES + // + UINT8 DeepSxMode; + UINT8 Gp27WakeFromDeepSx; + UINT8 GbeRegionInvalid; + UINT8 LomLanSupported; + UINT8 PchWakeOnLan; + UINT8 PchSlpLanLowDc; + UINT8 PchCrid; + UINT8 PchRtcLock; + UINT8 PchBiosLock; + UINT8 PchAllUnLock; + UINT8 PchThermalUnlock; + UINT8 PchSerm; + + UINT8 Hpet; + UINT8 PchPort80Route; + UINT8 EnableClockSpreadSpec; + UINT8 IchPort80Route; + UINT8 PchSirqMode; + + // + // Usb Config + // + UINT8 PchUsbManualMode; + UINT8 PchGpioLockDown; + UINT8 Usb3PinsTermination; + UINT8 EnableUsb3Pin[10]; + UINT8 PchUsbHsPort[16]; + UINT8 PchUsbSsPort[10]; + UINT8 PchUsbPortDisable; + UINT8 UsbSensorHub; + UINT8 UsbSsicSupport[2]; + UINT8 XhciDisMSICapability; + UINT8 PchUsbPerPortCtl; + UINT8 PchUsb30Port[6]; + UINT8 UsbPrecondition; + UINT8 XhciIdleL1; + UINT8 Btcg; + UINT8 PchUsbDegradeBar; + // + // XHCI OC Map + // + UINT8 XhciOcMapEnabled; + // + // xDCI Config + // + UINT8 PchXdciSupport; + // + // Sata CONFIG + // + UINT8 PchSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 SataInterfaceMode; + UINT8 SataPort[PCH_MAX_SATA_PORTS]; + UINT8 SataHotPlug[PCH_MAX_SATA_PORTS]; + UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS]; + UINT8 SataSpinUp[PCH_MAX_SATA_PORTS]; + UINT8 SataExternal[PCH_MAX_SATA_PORTS]; + UINT8 SataType[PCH_MAX_SATA_PORTS]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SataRaidSrt; + UINT8 SataRaidLoadEfiDriver[PCH_MAX_SATA_CONTROLLERS]; + UINT8 SataRaidOromDelay; + UINT8 SataAlternateId; + UINT8 SataSalp; + UINT8 SataTestMode; + UINT8 PxDevSlp[PCH_MAX_SATA_PORTS]; + UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS]; + UINT16 DitoVal[PCH_MAX_SATA_PORTS]; + UINT8 DmVal[PCH_MAX_SATA_PORTS]; + UINT8 SataTopology[PCH_MAX_SATA_PORTS]; + + // + // sSata CONFIG + // + UINT8 PchsSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 sSataInterfaceMode; + UINT8 sSataPort[PCH_MAX_SSATA_PORTS]; + UINT8 sSataHotPlug[PCH_MAX_SSATA_PORTS]; + UINT8 sSataSpinUp[PCH_MAX_SSATA_PORTS]; + UINT8 sSataExternal[PCH_MAX_SSATA_PORTS]; + UINT8 sPxDevSlp[PCH_MAX_SSATA_PORTS]; + UINT8 sSataType[PCH_MAX_SSATA_PORTS]; + UINT8 sSataRaidR0; + UINT8 sSataRaidR1; + UINT8 sSataRaidR10; + UINT8 sSataRaidR5; + UINT8 sSataRaidIrrt; + UINT8 sSataRaidOub; + UINT8 sSataHddlk; + UINT8 sSataLedl; + UINT8 sSataRaidIooe; + UINT8 sSataRaidSrt; + UINT8 sSataRaidOromDelay; + UINT8 sSataAlternateId; + UINT8 sSataSalp; + UINT8 sSataTestMode; + UINT8 sEnableDitoConfig[PCH_MAX_SSATA_PORTS]; + UINT8 sDmVal[PCH_MAX_SSATA_PORTS]; + UINT8 sDitoVal[PCH_MAX_SSATA_PORTS]; + UINT8 sSataTopology[PCH_MAX_SSATA_PORTS]; + + //PCH THERMAL SENSOR + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + + UINT8 PchDmiExtSync; + UINT8 PcieDmiExtSync; + // AcpiDebug Setup Options + UINT8 PciDelayOptimizationEcr; + UINT8 PchPcieGlobalAspm; + + UINT8 PcieDmiStopAndScreamEnable; + UINT8 DmiLinkDownHangBypass; + UINT8 XTpmLen; + UINT8 PcieRootPort8xhDecode; + UINT8 Pcie8xhDecodePortIndex; + UINT8 PcieRootPortPeerMemoryWriteEnable; + UINT8 PcieComplianceTestMode; + + + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + + UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 PcieRootPortFunctionSwapping; + UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieSwEqOverride; + UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PchPcieUX8MaxPayloadSize; + UINT8 PchPcieUX16MaxPayloadSize; + UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieClockGatingDisabled; + UINT8 PcieUsbGlitchWa; + UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxReadRequestSize; + UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // PCI Bridge Resources + // + UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 MemoryThermalManagement; + UINT8 ExttsViaTsOnBoard; + UINT8 ExttsViaTsOnDimm; + UINT8 FixupPlatformSpecificSoftstraps; + + // + // SMBUS Configuration + // + UINT8 TestSmbusSpdWriteDisable; + + // + // HD-Audio Configuration + // + UINT8 PchHdAudio; + UINT8 PchHdAudioDsp; + UINT8 PchHdAudioPme; + UINT8 PchHdAudioIoBufferOwnership; + UINT8 PchHdAudioIoBufferVoltage; + UINT8 PchHdAudioCodecSelect; + UINT8 PchHdAudioFeature[HDAUDIO_FEATURES]; + UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES]; + + UINT8 DfxHdaVcType; + // + // DMI Configuration + // + UINT8 TestDmiAspmCtrl; + + + // + // + // PCIe LTR Configuration + // + UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS= ]; + UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchSataLtrOverride; + UINT8 PchSataLtrEnable; + UINT16 PchSataSnoopLatencyOverrideValue; + UINT8 PchSataSnoopLatencyOverrideMultiplier; + UINT8 PchSataLtrConfigLock; + + UINT8 PchSSataLtrOverride; + UINT16 PchSSataSnoopLatencyOverrideValue; + UINT8 PchSSataSnoopLatencyOverrideMultiplier; + UINT8 PchSSataLtrEnable; + UINT8 PchSSataLtrConfigLock; + + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + // + // Interrupt Configuration + // + UINT8 PchIoApic24119Entries; + UINT8 ShutdownPolicySelect; + + // + // DPTF SETUP items begin + // + UINT8 EnableDptf; + UINT8 EnablePchDevice; + + // + // Miscellaneous options + // + UINT8 SlpLanLowDc; + UINT8 PchLanK1Off; + UINT8 PchWakeOnWlan; + UINT8 PchWakeOnWlanDeepSx; + UINT8 StateAfterG3; + UINT8 PciePllSsc; + UINT8 FirmwareConfiguration; + UINT8 DciEn; + UINT8 PchDciAutoDetect; + + // Acpi.sd + UINT8 CSNotifyEC; + UINT8 EcLowPowerMode; + + // + // TraceHub Setup Options + // + UINT8 PchTraceHubMode; + UINT32 PchTraceHubMemReg0Size; + UINT32 PchTraceHubMemReg1Size; + UINT8 AetEnableMode; + + // + // PCH P2SB hide and lock options + // + UINT8 PchP2sbDevReveal; + UINT8 PchP2sbUnlock; + + // + // PCH SPI hide and lock options + // + UINT8 ShowSpiController; + UINT8 FlashLockDown; + + // + // PCH PMC DFX options + // + UINT8 PmcReadDisable; + + + // + // ADR Configuration + // + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + UINT8 AdrSysPwrOk; + UINT8 AdrOverClockingWdt; + UINT8 AdrCpuThermalWdt; + UINT8 AdrPmcParityError; + + // + // Audio DSP Configuration + // + UINT8 PchAudioDsp; + UINT8 PchAudioDspD3PowerGating; + UINT8 PchAudioDspAcpiMode; + UINT8 PchAudioDspBluetooth; + UINT8 PchAudioDspAcpiInterruptMode; + + // + // DFX Configuration + // + UINT8 PchEvaMrom0HookEnable; + UINT8 PchEvaMrom1HookEnable; + UINT8 TestMctpBroadcastCycle; + UINT8 PchEvaLockDown; + UINT8 PchTraceHubHide; +} PCH_SETUP; +#pragma pack() + +#endif + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h b/Pla= tform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h new file mode 100644 index 0000000000..0082cf0fa9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h @@ -0,0 +1,183 @@ +/** @file + EFI Platform Device Data Definition Header File. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PLAT_DEVICE_DATA_H_ +#define _EFI_PLAT_DEVICE_DATA_H_ + +#include +#include + +#include +#include + + +typedef struct { + UINT8 Dev; // Device numbers of a chain of br= idges starting at PCI Bus, behind which this device is located. + UINT8 Fun; // Function numbers of a chain of = bridges starting at PCI Bus, behind which this device is located. +} DEVICE_DATA_DEV_PATH; + +typedef struct { + UINT32 UID; // The Root Bridge ID as appears i= n the device path for that bridge. +} DEVICE_DATA_RBRG_PATH; + +typedef struct { + DEVICE_DATA_RBRG_PATH RootBridgePath; // Path to starting PCI Bus from w= hich the SourceBusPath begins. This is used if there are multiple root brid= ges. Each such bridge will originate a lowest level PCI bus. + DEVICE_DATA_DEV_PATH BridgePath[4]; // Pairs of device/function number= s of a chain of bridges starting at PCI Bus, behind which this device is lo= cated. Must terminate with Dev =3D 0xFF. The size of 3 may be bumped up if = there is more bus depth levels than 3 on a particular platform. +} DEVICE_DATA_BUS_PATH; + +// +// Holds live system PCI Root Bridge info. +// +typedef struct { + EFI_HANDLE Handle; // Handle to the PCI dev= ice. + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRbIoProt; // Root Bridge IO protoc= ol. + EFI_DEVICE_PATH_PROTOCOL *DevPath; // Device path to the br= idge. + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources; // Bus/IO/Mem ranges exp= osed via the root bridge. +} DEVICE_DATA_PCI_RBRG; + +// +// Holds live system PCI device info. +// +typedef struct { + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Fun; +} LOCATION; + +typedef struct { + EFI_HANDLE Handle; // Handle to the PCI device. + EFI_PCI_IO_PROTOCOL *PciIoProt; + LOCATION Location; // Bus/Dev/Fun location of this device. + PCI_TYPE_GENERIC ConfSpace; // First 40h bytes of PCI config space for= each device. +} DEVICE_DATA_PCI_DEV; + +// +// Holds live system CPU device info. +// +typedef struct { + UINTN PackageNumber; + UINTN CoreNumber; + UINTN ThreadNumber; + UINT8 Present; + UINT8 Enabled; + UINT8 Stepping; + UINT8 Model; + UINT8 Family; + UINT8 Bsp; + UINT8 Apic; + UINT8 ApicId; + UINT8 ApicVer; + UINT8 Fpu; + UINT8 Mce; + UINT8 Cx8; +} DEVICE_DATA_CPU; + +// +// Platform hardwired data describing all I/O APICs in the system. +// +typedef struct { + UINT8 Enabled; + UINT32 Address; + UINT8 Id; + UINT8 Version; +} DEVICE_DATA_HW_IO_APIC; + +// +// Platform hardwired data describing connection of interrupt sources to l= ocal APICs. +// +typedef struct { + DEVICE_DATA_BUS_PATH SourceBusPath; + UINT8 SourceBusIrq; + UINT8 DestApicId; + UINT8 DestApicIntIn; + UINT8 IntType; + UINT16 Polarity; + UINT16 Trigger; +} DEVICE_DATA_HW_LOCAL_INT; + +// +// Platform hardwired data describing the built-in devices. +// +typedef struct { + DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes ro= ot bridge and P2P bridge chain. + DEVICE_DATA_DEV_PATH DevFun; // Device/function number of the b= uilt-in PCI device being described. 0xff if not applicable e.g., it's an IS= A device. + UINT8 DestApicId; // Destination APIC. + UINT8 DestApicIntIn; // The pin of the destination APIC= the interrupt wire is connected to. + UINT8 IntType; // As defined in the MPS. + UINT16 Polarity; // As defined in the MPS. + UINT16 Trigger; // As defined in the MPS. +} DEVICE_DATA_HW_BUILT_IN; + +// +// Platform hardwired data describing the add-in devices. +// An add-in device is defined here as a pluggable into a PCI slot. +// Thus there must be as many entries as there are slots in the system. +// The devices as defined above may have any complexity (wile complying +// with the PCI spec) including possibly multiple levels of bridges and bu= ses +// possibly with multiple devices possibly with multiple functions. +// The routing of the interrupts from such functions is governed by the +// PCI-to-PCI Bridge Architecture Specification. +// It short it requires that functions rotate mod 4 the interrupt assignme= nts +// (A/B/C/D) with PCI devices of single function devices and that the bus = depth +// does not cause such a rotation. +// +typedef struct { + DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes = root bridge and P2P bridge chain. + UINT8 Dev; // Device number of the slot bei= ng described. + UINT8 DestApicId; // Destination APIC. As defined = in the MPS. + UINT8 DestApicIntIn[4]; // Interrupt pins to destination= APIC, indexes correspond to PCI interrupt pins A/B/C/D. +} DEVICE_DATA_HW_PCI_SLOT; + +// +// Platform hardwired data describing the address space mapping. +// +typedef struct { + DEVICE_DATA_RBRG_PATH RootBridgePath; + UINT8 AddressType; + UINT64 AddressBase; + UINT64 AddressLength; +} DEVICE_DATA_HW_ADDR_SPACE_MAPPING; + +// +// This is the module global containing platform device data. +// +typedef struct { + DEVICE_DATA_HW_LOCAL_INT *LocalIntData; + UINTN LocalIntDataSize; + DEVICE_DATA_HW_ADDR_SPACE_MAPPING *AddrDataMapping; + UINTN AddrDataMappingSize; + + DEVICE_DATA_PCI_RBRG *PciRBridgeInfo; // Info for PCI Root= Bridges in the system. + DEVICE_DATA_PCI_DEV *PciDevInfo; // Info for PCI devi= ces in the system. + UINT8 PciBusNo; // Number of PCI bus= es. Assumes that PCI bus numbers are continous and start from 0. + UINT8 LegacyBusIdx; // Bus number of the= legacy bus like ISA. EISA etc. There could only be one legacy bus. It has = to be the last bus after all the PCI buses. + DEVICE_DATA_CPU *CpuInfo; // Info for all proc= essors. + UINTN CpuMax; +} DEVICE_DATA; + +// +// This is the module global containing platform device data. +// +typedef struct { + DEVICE_DATA_HW_PCI_SLOT *HwPciSlotUpdate; + UINTN HwPciSlotUpdateSize; + DEVICE_DATA_HW_BUILT_IN *HwBuiltInUpdate; + UINTN HwBuiltInUpdateSize; +} DEVICE_UPDATE_DATA; + + +typedef struct _MP_TABLE_CPU_INFO { + UINT8 ApicVersion; + UINT32 CpuSignature; + UINT32 FeatureFlags; +} MP_TABLE_CPU_INFO; + +#endif //_EFI_PLAT_DEVICE_DATA_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h new file mode 100644 index 0000000000..f2fd18bf16 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h @@ -0,0 +1,36 @@ +/** @file + EFI Platform Pirq Data Definition Header File. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PLATF_PIRQ_DATA_H_ +#define _EFI_PLATF_PIRQ_DATA_H_ + +#include + +#define EFI_PIRQ_TABLE_SIGNATURE 0x52495024 +#define EFI_PIRQ_TABLE_VERSION 0x100 + +// +// Common path types. +// +typedef struct { + EFI_LEGACY_PIRQ_TABLE_HEADER PirqTable; +} EFI_LEGACY_PIRQ_TABLE; + +// +// This is the module global containing platform PIRQ data. +// +typedef struct { + EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY *PriorityTable; + UINTN PriorityTableSize; + EFI_LEGACY_PIRQ_TABLE *TableHead; + UINTN TableHeadSize; +} PLATFORM_PIRQ_DATA; + +#endif //_EFI_PLATF_PIRQ_DATA_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatusC= odeHandler.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatu= sCodeHandler.h new file mode 100644 index 0000000000..37c7e19e38 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatusCodeHand= ler.h @@ -0,0 +1,38 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ +#define __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ + + +/** + Registers ExSerialStatusCodeReportWorker as callback function for Report= StatusCode() notification. + + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_EX_RSC_HANDLER_REGISTER)( + IN CONST EFI_PEI_SERVICES **PeiServices +); + +typedef struct _EFI_EX_PEI_RSC_HANDLER_PPI { + EFI_PEI_EX_RSC_HANDLER_REGISTER RegisterExStatusCodeHandler; +} EFI_PEI_EX_RSC_HANDLER_PPI; + +extern EFI_GUID gEfiPeiExStatusCodeHandlerPpiGuid; + +#endif // __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h b= /Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h new file mode 100644 index 0000000000..4b9c8b677f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h @@ -0,0 +1,29 @@ +/** @file + Smbus Policy PPI as defined in EFI 2.0 + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SMBUS_POLICY_PPI_H +#define _PEI_SMBUS_POLICY_PPI_H + +#define PEI_SMBUS_POLICY_PPI_GUID \ + { \ + 0x63b6e435, 0x32bc, 0x49c6, { 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, = 0x6c } \ + } + +typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI; + +typedef struct _PEI_SMBUS_POLICY_PPI { + UINTN BaseAddress; + UINT32 PciAddress; + UINT8 NumRsvdAddress; + UINT8 *RsvdAddress; +} PEI_SMBUS_POLICY_PPI; + +extern EFI_GUID gPeiSmbusPolicyPpiGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h new file mode 100644 index 0000000000..2db2ac8b9a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h @@ -0,0 +1,144 @@ +/** @file + uba central config database PPI + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_PPI_H_ +#define _UBA_CONFIG_DATABASE_PPI_H_ + +// {C1176733-159F-42d5-BCB9-320660B17310} +#define UBA_CONFIG_DATABASE_PPI_GUID \ + { 0xc1176733, 0x159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73,= 0x10 } } + +typedef struct _UBA_CONFIG_DATABASE_PPI UBA_CONFIG_DATABASE_PPI; + +#define UBA_CONFIG_PPI_VERSION 01 +#define UBA_CONFIG_PPI_SIGNATURE SIGNATURE_32('U', 'S', 'K', 'U') + +// +// Functions +// + +/** + Set board's GUID and user friendly name by BoardId. + + If the BoardId is not exist in database, it will create a new platform. + + @param This uba Ppi instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_INIT_BOARD) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN UINT32 BoardId, + IN EFI_GUID *BoardGuid, OPTIONAL + IN CHAR8 *BoardName OPTIONAL + ); + +/** + Get board's GUID and user friendly name by BoardId. + + This is used when you need a BoardGuid to Add/Get platform data + + Core will create a new platform for you if the BoardId is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Ppi instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_GET_BOARD) ( + IN UBA_CONFIG_DATABASE_PPI *This, + OUT UINT32 *BoardId, + OUT EFI_GUID *BoardGuid, OPTIONAL + OUT CHAR8 *BoardName OPTIONAL + ); + +/** + Add configuration data to uba configuration database. + + @param This uba Ppi instance. + @param BoardGuid The GUID for this platform. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_ADD_DATA) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get configuration data from uba configuration database. + + @param This uba Ppi instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_GET_DATA) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + IN OUT UINTN *DataSize + ); + + +// +// Multi Sku config database PPI +// +struct _UBA_CONFIG_DATABASE_PPI { + UINT32 Signature; + UINT32 Version; + + PEI_UBA_CONFIG_INIT_BOARD InitSku; + PEI_UBA_CONFIG_GET_BOARD GetSku; + + PEI_UBA_CONFIG_ADD_DATA AddData; + PEI_UBA_CONFIG_GET_DATA GetData; +}; + +extern EFI_GUID gUbaConfigDatabasePpiGuid; + +#endif // _UBA_CONFIG_DATABASE_PPI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= .h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios.h new file mode 100644 index 0000000000..b0bd90d1cb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios.h @@ -0,0 +1,1550 @@ +/** @file + The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage + under EFI and Legacy OS boot. This file also includes all the related + COMPATIBILIY16 structures and defintions. + + Note: The names for EFI_IA32_REGISTER_SET elements were picked to follow + well known naming conventions. + + Thunk is the code that switches from 32-bit protected environment into t= he 16-bit real-mode + environment. Reverse thunk is the code that does the opposite. + + @copyright + Copyright 2007 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_BIOS_H_ +#define _EFI_LEGACY_BIOS_H_ + +/// +/// +/// +#pragma pack(1) + +typedef UINT8 SERIAL_MODE; +typedef UINT8 PARALLEL_MODE; + +#define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E', '= $') + +/// +/// There is a table located within the traditional BIOS in either the 0xF= 000:xxxx or 0xE000:xxxx +/// physical address range. It is located on a 16-byte boundary and provid= es the physical address of the +/// entry point for the Compatibility16 functions. These functions provide= the platform-specific +/// information that is required by the generic EfiCompatibility code. The= functions are invoked via +/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit= physical +/// entry point. +/// +typedef struct { + /// + /// The string "$EFI" denotes the start of the EfiCompatibility table. B= yte 0 is "I," byte + /// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed = as a DWORD or UINT32. + /// + UINT32 Signature; + + /// + /// The value required such that byte checksum of TableLength equals zer= o. + /// + UINT8 TableChecksum; + + /// + /// The length of this table. + /// + UINT8 TableLength; + + /// + /// The major EFI revision for which this table was generated. + /// + UINT8 EfiMajorRevision; + + /// + /// The minor EFI revision for which this table was generated. + /// + UINT8 EfiMinorRevision; + + /// + /// The major revision of this table. + /// + UINT8 TableMajorRevision; + + /// + /// The minor revision of this table. + /// + UINT8 TableMinorRevision; + + /// + /// Reserved for future usage. + /// + UINT16 Reserved; + + /// + /// The segment of the entry point within the traditional BIOS for Compa= tibility16 functions. + /// + UINT16 Compatibility16CallSegment; + + /// + /// The offset of the entry point within the traditional BIOS for Compat= ibility16 functions. + /// + UINT16 Compatibility16CallOffset; + + /// + /// The segment of the entry point within the traditional BIOS for EfiCo= mpatibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckSegment; + + /// + /// The Offset of the entry point within the traditional BIOS for EfiCom= patibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckOffset; + + /// + /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the = IntelPlatform + ///Innovation Framework for EFI Driver Execution Environment Core Interf= ace Specification (DXE CIS). + /// + UINT32 EfiSystemTable; + + /// + /// The address of an OEM-provided identifier string. The string is null= terminated. + /// + UINT32 OemIdStringPointer; + + /// + /// The 32-bit physical address where ACPI RSD PTR is stored within the = traditional + /// BIOS. The remained of the ACPI tables are located at their EFI addre= sses. The size + /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill= in the ACPI + /// RSD PTR with either the ACPI 1.0b or 2.0 values. + /// + UINT32 AcpiRsdPtrPointer; + + /// + /// The OEM revision number. Usage is undefined but provided for OEM mod= ule usage. + /// + UINT16 OemRevision; + + /// + /// The 32-bit physical address where INT15 E820 data is stored within t= he traditional + /// BIOS. The EfiCompatibility code will fill in the E820Pointer value a= nd copy the + /// data to the indicated area. + /// + UINT32 E820Pointer; + + /// + /// The length of the E820 data and is filled in by the EfiCompatibility= code. + /// + UINT32 E820Length; + + /// + /// The 32-bit physical address where the $PIR table is stored in the tr= aditional BIOS. + /// The EfiCompatibility code will fill in the IrqRoutingTablePointer va= lue and + /// copy the data to the indicated area. + /// + UINT32 IrqRoutingTablePointer; + + /// + /// The length of the $PIR table and is filled in by the EfiCompatibilit= y code. + /// + UINT32 IrqRoutingTableLength; + + /// + /// The 32-bit physical address where the MP table is stored in the trad= itional BIOS. + /// The EfiCompatibility code will fill in the MpTablePtr value and copy= the data + /// to the indicated area. + /// + UINT32 MpTablePtr; + + /// + /// The length of the MP table and is filled in by the EfiCompatibility = code. + /// + UINT32 MpTableLength; + + /// + /// The segment of the OEM-specific INT table/code. + /// + UINT16 OemIntSegment; + + /// + /// The offset of the OEM-specific INT table/code. + /// + UINT16 OemIntOffset; + + /// + /// The segment of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Segment; + + /// + /// The offset of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Offset; + + /// + /// The segment of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Segment; + + /// + /// The offset of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Offset; + + /// + /// The segment of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmSegment; + + /// + /// The offset of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmOffset; + + /// + /// A pointer to a string identifying the independent BIOS vendor. + /// + UINT32 IbvPointer; + + /// + /// This field is NULL for all systems not supporting PCI Express. This = field is the base + /// value of the start of the PCI Express memory-mapped configuration re= gisters and + /// must be filled in prior to EfiCompatibility code issuing the Compati= bility16 function + /// Compatibility16InitializeYourself(). + /// Compatibility16InitializeYourself() is defined in Compatability16 + /// Functions. + /// + UINT32 PciExpressBase; + + /// + /// Maximum PCI bus number assigned. + /// + UINT8 LastPciBus; + + /// + /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If + /// UmaAddress is a valid address in the shadow RAM, it also indicates t= hat the region + /// from 0xC0000 to (UmaAddress - 1) can be used for Option ROM. + /// + UINT32 UmaAddress; + + /// + /// Upper Memory Area size in bytes to be set as Read/Write. If zero, no= UMA region + /// will be set as Read/Write (i.e. all Shadow RAM is set as Read-Only). + /// + UINT32 UmaSize; + + /// + /// Start Address of high memory that can be used for permanent allocati= on. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemoryAddress; + + /// + /// Size of high memory that can be used for permanent allocation in byt= es. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemorySize; +} EFI_COMPATIBILITY16_TABLE; + +/// +/// Functions provided by the CSM binary which communicate between the Efi= Compatibility +/// and Compatability16 code. +/// +/// Inconsistent with the specification here: +/// The member's name started with "Compatibility16" [defined in Intel Fra= mework +/// Compatibility Support Module Specification / 0.97 version] +/// has been changed to "Legacy16" since keeping backward compatible. +/// +typedef enum { + /// + /// Causes the Compatibility16 code to do any internal initialization re= quired. + /// Input: + /// AX =3D Compatibility16InitializeYourself + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE + /// Return: + /// AX =3D Return Status codes + /// + Legacy16InitializeYourself =3D 0x0000, + + /// + /// Causes the Compatibility16 BIOS to perform any drive number translat= ions to match the boot sequence. + /// Input: + /// AX =3D Compatibility16UpdateBbs + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE + /// Return: + /// AX =3D Returned status codes + /// + Legacy16UpdateBbs =3D 0x0001, + + /// + /// Allows the Compatibility16 code to perform any final actions before = booting. The Compatibility16 + /// code is read/write. + /// Input: + /// AX =3D Compatibility16PrepareToBoot + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure + /// Return: + /// AX =3D Returned status codes + /// + Legacy16PrepareToBoot =3D 0x0002, + + /// + /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is= Read/Only. + /// Input: + /// AX =3D Compatibility16Boot + /// Output: + /// AX =3D Returned status codes + /// + Legacy16Boot =3D 0x0003, + + /// + /// Allows the Compatibility16 code to get the last device from which a = boot was attempted. This is + /// stored in CMOS and is the priority number of the last attempted boot= device. + /// Input: + /// AX =3D Compatibility16RetrieveLastBootDevice + /// Output: + /// AX =3D Returned status codes + /// BX =3D Priority number of the boot device. + /// + Legacy16RetrieveLastBootDevice =3D 0x0004, + + /// + /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 af= ter dispatching a legacy OpROM. + /// Input: + /// AX =3D Compatibility16DispatchOprom + /// ES:BX =3D Pointer to EFI_DISPATCH_OPROM_TABLE + /// Output: + /// AX =3D Returned status codes + /// BX =3D Number of non-BBS-compliant devices found. Equals 0 if BBS = compliant. + /// + Legacy16DispatchOprom =3D 0x0005, + + /// + /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified = length and returns the address + /// of that region. + /// Input: + /// AX =3D Compatibility16GetTableAddress + /// BX =3D Allocation region + /// 00 =3D Allocate from either 0xE0000 or 0xF0000 64 KB blocks. + /// Bit 0 =3D 1 Allocate from 0xF0000 64 KB block + /// Bit 1 =3D 1 Allocate from 0xE0000 64 KB block + /// CX =3D Requested length in bytes. + /// DX =3D Required address alignment. Bit mapped. First non-zero bit = from the right is the alignment. + /// Output: + /// AX =3D Returned status codes + /// DS:BX =3D Address of the region + /// + Legacy16GetTableAddress =3D 0x0006, + + /// + /// Enables the EfiCompatibility module to do any nonstandard processing= of keyboard LEDs or state. + /// Input: + /// AX =3D Compatibility16SetKeyboardLeds + /// CL =3D LED status. + /// Bit 0 Scroll Lock 0 =3D Off + /// Bit 1 NumLock + /// Bit 2 Caps Lock + /// Output: + /// AX =3D Returned status codes + /// + Legacy16SetKeyboardLeds =3D 0x0007, + + /// + /// Enables the EfiCompatibility module to install an interrupt handler = for PCI mass media devices that + /// do not have an OpROM associated with them. An example is SATA. + /// Input: + /// AX =3D Compatibility16InstallPciHandler + /// ES:BX =3D Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure + /// Output: + /// AX =3D Returned status codes + /// + Legacy16InstallPciHandler =3D 0x0008 +} EFI_COMPATIBILITY_FUNCTIONS; + + +/// +/// EFI_DISPATCH_OPROM_TABLE +/// +typedef struct { + UINT16 PnPInstallationCheckSegment; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 PnPInstallationCheckOffset; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 OpromSegment; ///< The segment where the OpROM w= as placed. Offset is assumed to be 3. + UINT8 PciBus; ///< The PCI bus. + UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI f= unction. + UINT8 NumberBbsEntries; ///< The number of valid BBS table= entries upon entry and exit. The IBV code may + ///< increase this number, if BBS-= compliant devices also hook INTs in order to force the + ///< OpROM BIOS Setup to be execut= ed. + UINT32 BbsTablePointer; ///< A pointer to the BBS table. + UINT16 RuntimeSegment; ///< The segment where the OpROM c= an be relocated to. If this value is 0x0000, this + ///< means that the relocation of = this run time code is not supported. + ///< Inconsistent with specificati= on here: + ///< The member's name "OpromDesti= nationSegment" [defined in Intel Framework Compatibility Support Module Spe= cification / 0.97 version] + ///< has been changed to "RuntimeS= egment" since keeping backward compatible. + +} EFI_DISPATCH_OPROM_TABLE; + +/// +/// EFI_TO_COMPATIBILITY16_INIT_TABLE +/// +typedef struct { + /// + /// Starting address of memory under 1 MB. The ending address is assumed= to be 640 KB or 0x9FFFF. + /// + UINT32 BiosLessThan1MB; + + /// + /// The starting address of the high memory block. + /// + UINT32 HiPmmMemory; + + /// + /// The length of high memory block. + /// + UINT32 HiPmmMemorySizeInBytes; + + /// + /// The segment of the reverse thunk call code. + /// + UINT16 ReverseThunkCallSegment; + + /// + /// The offset of the reverse thunk call code. + /// + UINT16 ReverseThunkCallOffset; + + /// + /// The number of E820 entries copied to the Compatibility16 BIOS. + /// + UINT32 NumberE820Entries; + + /// + /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory. + /// + UINT32 OsMemoryAbove1Mb; + + /// + /// The start of thunk code in main memory. Memory cannot be used by BIO= S or PMM. + /// + UINT32 ThunkStart; + + /// + /// The size of the thunk code. + /// + UINT32 ThunkSizeInBytes; + + /// + /// Starting address of memory under 1 MB. + /// + UINT32 LowPmmMemory; + + /// + /// The length of low Memory block. + /// + UINT32 LowPmmMemorySizeInBytes; +} EFI_TO_COMPATIBILITY16_INIT_TABLE; + +/// +/// DEVICE_PRODUCER_SERIAL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned = to the serial port. + UINT8 Irq; ///< IRQ assigned to the s= erial port. + SERIAL_MODE Mode; ///< Mode of serial port. = Values are defined below. +} DEVICE_PRODUCER_SERIAL; + +/// +/// DEVICE_PRODUCER_SERIAL's modes. +///@{ +#define DEVICE_SERIAL_MODE_NORMAL 0x00 +#define DEVICE_SERIAL_MODE_IRDA 0x01 +#define DEVICE_SERIAL_MODE_ASK_IR 0x02 +#define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00 +#define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10 +///@) + +/// +/// DEVICE_PRODUCER_PARALLEL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned to= the parallel port. + UINT8 Irq; ///< IRQ assigned to the par= allel port. + UINT8 Dma; ///< DMA assigned to the par= allel port. + PARALLEL_MODE Mode; ///< Mode of the parallel po= rt. Values are defined below. +} DEVICE_PRODUCER_PARALLEL; + +/// +/// DEVICE_PRODUCER_PARALLEL's modes. +///@{ +#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00 +#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01 +#define DEVICE_PARALLEL_MODE_MODE_EPP 0x02 +#define DEVICE_PARALLEL_MODE_MODE_ECP 0x03 +///@} + +/// +/// DEVICE_PRODUCER_FLOPPY +/// +typedef struct { + UINT16 Address; ///< I/O address ass= igned to the floppy. + UINT8 Irq; ///< IRQ assigned to= the floppy. + UINT8 Dma; ///< DMA assigned to= the floppy. + UINT8 NumberOfFloppy; ///< Number of flopp= ies in the system. +} DEVICE_PRODUCER_FLOPPY; + +/// +/// LEGACY_DEVICE_FLAGS +/// +typedef struct { + UINT32 A20Kybd : 1; ///< A20 controller = by keyboard controller. + UINT32 A20Port90 : 1; ///< A20 controlled = by port 0x92. + UINT32 Reserved : 30; ///< Reserved for fu= ture usage. +} LEGACY_DEVICE_FLAGS; + +/// +/// DEVICE_PRODUCER_DATA_HEADER +/// +typedef struct { + DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial p= ort x. Type DEVICE_PRODUCER_SERIAL is defined below. + DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel= port x. Type DEVICE_PRODUCER_PARALLEL is defined below. + DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. = Type DEVICE_PRODUCER_FLOPPY is defined below. + UINT8 MousePresent; ///< Flag to indicate = if mouse is present. + LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boo= lean state information passed to CSM. +} DEVICE_PRODUCER_DATA_HEADER; + +/// +/// ATAPI_IDENTIFY +/// +typedef struct { + UINT16 Raw[256]; ///< Raw data from the I= DE IdentifyDrive command. +} ATAPI_IDENTIFY; + +/// +/// HDD_INFO +/// +typedef struct { + /// + /// Status of IDE device. Values are defined below. There is one HDD_INF= O structure + /// per IDE controller. The IdentifyDrive is per drive. Index 0 is maste= r and index + /// 1 is slave. + /// + UINT16 Status; + + /// + /// PCI bus of IDE controller. + /// + UINT32 Bus; + + /// + /// PCI device of IDE controller. + /// + UINT32 Device; + + /// + /// PCI function of IDE controller. + /// + UINT32 Function; + + /// + /// Command ports base address. + /// + UINT16 CommandBaseAddress; + + /// + /// Control ports base address. + /// + UINT16 ControlBaseAddress; + + /// + /// Bus master address. + /// + UINT16 BusMasterAddress; + + UINT8 HddIrq; + + /// + /// Data that identifies the drive data; one per possible attached drive. + /// + ATAPI_IDENTIFY IdentifyDrive[2]; +} HDD_INFO; + +/// +/// HDD_INFO status bits +/// +#define HDD_PRIMARY 0x01 +#define HDD_SECONDARY 0x02 +#define HDD_MASTER_ATAPI_CDROM 0x04 +#define HDD_SLAVE_ATAPI_CDROM 0x08 +#define HDD_MASTER_IDE 0x20 +#define HDD_SLAVE_IDE 0x40 +#define HDD_MASTER_ATAPI_ZIPDISK 0x10 +#define HDD_SLAVE_ATAPI_ZIPDISK 0x80 + +/// +/// BBS_STATUS_FLAGS;\. +/// +typedef struct { + UINT16 OldPosition : 4; ///< Prior priorit= y. + UINT16 Reserved1 : 4; ///< Reserved for = future use. + UINT16 Enabled : 1; ///< If 0, ignore = this entry. + UINT16 Failed : 1; ///< 0 =3D Not kno= wn if boot failure occurred. + ///< 1 =3D Boot at= tempted failed. + + /// + /// State of media present. + /// 00 =3D No bootable media is present in the device. + /// 01 =3D Unknown if a bootable media present. + /// 10 =3D Media is present and appears bootable. + /// 11 =3D Reserved. + /// + UINT16 MediaPresent : 2; + UINT16 Reserved2 : 4; ///< Reserved for = future use. +} BBS_STATUS_FLAGS; + +/// +/// BBS_TABLE, device type values & boot priority values. +/// +typedef struct { + /// + /// The boot priority for this boot device. Values are defined below. + /// + UINT16 BootPriority; + + /// + /// The PCI bus for this boot device. + /// + UINT32 Bus; + + /// + /// The PCI device for this boot device. + /// + UINT32 Device; + + /// + /// The PCI function for the boot device. + /// + UINT32 Function; + + /// + /// The PCI class for this boot device. + /// + UINT8 Class; + + /// + /// The PCI Subclass for this boot device. + /// + UINT8 SubClass; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringSegment; + + /// + /// BBS device type. BBS device types are defined below. + /// + UINT16 DeviceType; + + /// + /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below. + /// + BBS_STATUS_FLAGS StatusFlags; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerOffset; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerSegment; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringSegment; + + /// + /// Reserved. + /// + UINT32 InitPerReserved; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq13Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq18Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq19Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq40Handler; + UINT8 AssignedDriveNumber; + UINT32 AdditionalIrq41Handler; + UINT32 AdditionalIrq46Handler; + UINT32 IBV1; + UINT32 IBV2; +} BBS_TABLE; + +/// +/// BBS device type values +///@{ +#define BBS_FLOPPY 0x01 +#define BBS_HARDDISK 0x02 +#define BBS_CDROM 0x03 +#define BBS_PCMCIA 0x04 +#define BBS_USB 0x05 +#define BBS_EMBED_NETWORK 0x06 +#define BBS_BEV_DEVICE 0x80 +#define BBS_UNKNOWN 0xff +///@} + +/// +/// BBS boot priority values +///@{ +#define BBS_DO_NOT_BOOT_FROM 0xFFFC +#define BBS_LOWEST_PRIORITY 0xFFFD +#define BBS_UNPRIORITIZED_ENTRY 0xFFFE +#define BBS_IGNORE_ENTRY 0xFFFF +///@} + +/// +/// SMM_ATTRIBUTES +/// +typedef struct { + /// + /// Access mechanism used to generate the soft SMI. Defined types are be= low. The other + /// values are reserved for future usage. + /// + UINT16 Type : 3; + + /// + /// The size of "port" in bits. Defined values are below. + /// + UINT16 PortGranularity : 3; + + /// + /// The size of data in bits. Defined values are below. + /// + UINT16 DataGranularity : 3; + + /// + /// Reserved for future use. + /// + UINT16 Reserved : 7; +} SMM_ATTRIBUTES; + +/// +/// SMM_ATTRIBUTES type values. +///@{ +#define STANDARD_IO 0x00 +#define STANDARD_MEMORY 0x01 +///@} + +/// +/// SMM_ATTRIBUTES port size constants. +///@{ +#define PORT_SIZE_8 0x00 +#define PORT_SIZE_16 0x01 +#define PORT_SIZE_32 0x02 +#define PORT_SIZE_64 0x03 +///@} + +/// +/// SMM_ATTRIBUTES data size constants. +///@{ +#define DATA_SIZE_8 0x00 +#define DATA_SIZE_16 0x01 +#define DATA_SIZE_32 0x02 +#define DATA_SIZE_64 0x03 +///@} + +/// +/// SMM_FUNCTION & relating constants. +/// +typedef struct { + UINT16 Function : 15; + UINT16 Owner : 1; +} SMM_FUNCTION; + +/// +/// SMM_FUNCTION Function constants. +///@{ +#define INT15_D042 0x0000 +#define GET_USB_BOOT_INFO 0x0001 +#define DMI_PNP_50_57 0x0002 +///@} + +/// +/// SMM_FUNCTION Owner constants. +///@{ +#define STANDARD_OWNER 0x0 +#define OEM_OWNER 0x1 +///@} + +/// +/// This structure assumes both port and data sizes are 1. SmmAttribute mu= st be +/// properly to reflect that assumption. +/// +typedef struct { + /// + /// Describes the access mechanism, SmmPort, and SmmData sizes. Type + /// SMM_ATTRIBUTES is defined below. + /// + SMM_ATTRIBUTES SmmAttributes; + + /// + /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below. + /// + SMM_FUNCTION SmmFunction; + + /// + /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmPort; + + /// + /// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmData; +} SMM_ENTRY; + +/// +/// SMM_TABLE +/// +typedef struct { + UINT16 NumSmmEntries; ///< Number of entri= es represented by SmmEntry. + SMM_ENTRY SmmEntry; ///< One entry per f= unction. Type SMM_ENTRY is defined below. +} SMM_TABLE; + +/// +/// UDC_ATTRIBUTES +/// +typedef struct { + /// + /// This bit set indicates that the ServiceAreaData is valid. + /// + UINT8 DirectoryServiceValidity : 1; + + /// + /// This bit set indicates to use the Reserve Area Boot Code Address (RA= CBA) only if + /// DirectoryServiceValidity is 0. + /// + UINT8 RabcaUsedFlag : 1; + + /// + /// This bit set indicates to execute hard disk diagnostics. + /// + UINT8 ExecuteHddDiagnosticsFlag : 1; + + /// + /// Reserved for future use. Set to 0. + /// + UINT8 Reserved : 5; +} UDC_ATTRIBUTES; + +/// +/// UD_TABLE +/// +typedef struct { + /// + /// This field contains the bit-mapped attributes of the PARTIES informa= tion. Type + /// UDC_ATTRIBUTES is defined below. + /// + UDC_ATTRIBUTES Attributes; + + /// + /// This field contains the zero-based device on which the selected + /// ServiceDataArea is present. It is 0 for master and 1 for the slave d= evice. + /// + UINT8 DeviceNumber; + + /// + /// This field contains the zero-based index into the BbsTable for the p= arent device. + /// This index allows the user to reference the parent device informatio= n such as PCI + /// bus, device function. + /// + UINT8 BbsTableEntryNumberForParentDevice; + + /// + /// This field contains the zero-based index into the BbsTable for the b= oot entry. + /// + UINT8 BbsTableEntryNumberForBoot; + + /// + /// This field contains the zero-based index into the BbsTable for the H= DD diagnostics entry. + /// + UINT8 BbsTableEntryNumberForHddDiag; + + /// + /// The raw Beer data. + /// + UINT8 BeerData[128]; + + /// + /// The raw data of selected service area. + /// + UINT8 ServiceAreaData[64]; +} UD_TABLE; + +#define EFI_TO_LEGACY_MAJOR_VERSION 0x02 +#define EFI_TO_LEGACY_MINOR_VERSION 0x00 +#define MAX_IDE_CONTROLLER 8 + +/// +/// EFI_TO_COMPATIBILITY16_BOOT_TABLE +/// +typedef struct { + UINT16 MajorVersion; ///< The= EfiCompatibility major version number. + UINT16 MinorVersion; ///< The= EfiCompatibility minor version number. + UINT32 AcpiTable; ///< The= location of the RSDT ACPI table. < 4G range. + UINT32 SmbiosTable; ///< The= location of the SMBIOS table in EFI memory. < 4G range. + UINT32 SmbiosTableLength; + // + // Legacy SIO state + // + DEVICE_PRODUCER_DATA_HEADER SioData; ///< Sta= ndard traditional device information. + UINT16 DevicePathType; ///< The= default boot type. + UINT16 PciIrqMask; ///< Mas= k of which IRQs have been assigned to PCI. + UINT32 NumberE820Entries; ///< Num= ber of E820 entries. The number can change from the + ///< Com= patibility16InitializeYourself() function. + // + // Controller & Drive Identify[2] per controller information + // + HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Har= d disk drive information, including raw Identify Drive data. + UINT32 NumberBbsEntries; ///< Num= ber of entries in the BBS table + UINT32 BbsTable; ///< A p= ointer to the BBS table. Type BBS_TABLE is defined below. + UINT32 SmmTable; ///< A p= ointer to the SMM table. Type SMM_TABLE is defined below. + UINT32 OsMemoryAbove1Mb; ///< The= amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can + ///< dif= fer from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more + ///< mem= ory may have been discovered. + UINT32 UnconventionalDeviceTable; ///< Inf= ormation to boot off an unconventional device like a PARTIES partition. Type + ///< UD_= TABLE is defined below. +} EFI_TO_COMPATIBILITY16_BOOT_TABLE; + +/// +/// EFI_LEGACY_INSTALL_PCI_HANDLER +/// +typedef struct { + UINT8 PciBus; ///< The PCI bus o= f the device. + UINT8 PciDeviceFun; ///< The PCI devic= e in bits 7:3 and function in bits 2:0. + UINT8 PciSegment; ///< The PCI segme= nt of the device. + UINT8 PciClass; ///< The PCI class= code of the device. + UINT8 PciSubclass; ///< The PCI subcl= ass code of the device. + UINT8 PciInterface; ///< The PCI inter= face code of the device. + // + // Primary section + // + UINT8 PrimaryIrq; ///< The primary d= evice IRQ. + UINT8 PrimaryReserved; ///< Reserved. + UINT16 PrimaryControl; ///< The primary d= evice control I/O base. + UINT16 PrimaryBase; ///< The primary d= evice I/O base. + UINT16 PrimaryBusMaster; ///< The primary d= evice bus master I/O base. + // + // Secondary Section + // + UINT8 SecondaryIrq; ///< The secondary= device IRQ. + UINT8 SecondaryReserved; ///< Reserved. + UINT16 SecondaryControl; ///< The secondary= device control I/O base. + UINT16 SecondaryBase; ///< The secondary= device I/O base. + UINT16 SecondaryBusMaster; ///< The secondary= device bus master I/O base. +} EFI_LEGACY_INSTALL_PCI_HANDLER; + +// +// Restore default pack value +// +#pragma pack() + +#define EFI_LEGACY_BIOS_PROTOCOL_GUID \ + { \ + 0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e,= 0x2d } \ + } + +typedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL; + +/// +/// Flags returned by CheckPciRom(). +/// +#define NO_ROM 0x00 +#define ROM_FOUND 0x01 +#define VALID_LEGACY_ROM 0x02 +#define ROM_WITH_CONFIG 0x04 ///< Not defined in the Framework CSM S= pecification. + +/// +/// The following macros do not appear in the Framework CSM Specification = and +/// are kept for backward compatibility only. They convert 32-bit address= (_Adr) +/// to Segment:Offset 16-bit form. +/// +///@{ +#define EFI_SEGMENT(_Adr) (UINT16) ((UINT16) (((UINTN) (_Adr)) >> 4) &= 0xf000) +#define EFI_OFFSET(_Adr) (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xff= ff) +///@} + +#define CARRY_FLAG 0x01 + +/// +/// EFI_EFLAGS_REG +/// +typedef struct { + UINT32 CF:1; + UINT32 Reserved1:1; + UINT32 PF:1; + UINT32 Reserved2:1; + UINT32 AF:1; + UINT32 Reserved3:1; + UINT32 ZF:1; + UINT32 SF:1; + UINT32 TF:1; + UINT32 IF:1; + UINT32 DF:1; + UINT32 OF:1; + UINT32 IOPL:2; + UINT32 NT:1; + UINT32 Reserved4:2; + UINT32 VM:1; + UINT32 Reserved5:14; +} EFI_EFLAGS_REG; + +/// +/// EFI_DWORD_REGS +/// +typedef struct { + UINT32 EAX; + UINT32 EBX; + UINT32 ECX; + UINT32 EDX; + UINT32 ESI; + UINT32 EDI; + EFI_EFLAGS_REG EFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT32 EBP; + UINT32 ESP; +} EFI_DWORD_REGS; + +/// +/// EFI_FLAGS_REG +/// +typedef struct { + UINT16 CF:1; + UINT16 Reserved1:1; + UINT16 PF:1; + UINT16 Reserved2:1; + UINT16 AF:1; + UINT16 Reserved3:1; + UINT16 ZF:1; + UINT16 SF:1; + UINT16 TF:1; + UINT16 IF:1; + UINT16 DF:1; + UINT16 OF:1; + UINT16 IOPL:2; + UINT16 NT:1; + UINT16 Reserved4:1; +} EFI_FLAGS_REG; + +/// +/// EFI_WORD_REGS +/// +typedef struct { + UINT16 AX; + UINT16 ReservedAX; + UINT16 BX; + UINT16 ReservedBX; + UINT16 CX; + UINT16 ReservedCX; + UINT16 DX; + UINT16 ReservedDX; + UINT16 SI; + UINT16 ReservedSI; + UINT16 DI; + UINT16 ReservedDI; + EFI_FLAGS_REG Flags; + UINT16 ReservedFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT16 BP; + UINT16 ReservedBP; + UINT16 SP; + UINT16 ReservedSP; +} EFI_WORD_REGS; + +/// +/// EFI_BYTE_REGS +/// +typedef struct { + UINT8 AL, AH; + UINT16 ReservedAX; + UINT8 BL, BH; + UINT16 ReservedBX; + UINT8 CL, CH; + UINT16 ReservedCX; + UINT8 DL, DH; + UINT16 ReservedDX; +} EFI_BYTE_REGS; + +/// +/// EFI_IA32_REGISTER_SET +/// +typedef union { + EFI_DWORD_REGS E; + EFI_WORD_REGS X; + EFI_BYTE_REGS H; +} EFI_IA32_REGISTER_SET; + +/** + Thunk to 16-bit real mode and execute a software interrupt with a vector + of BiosInt. Regs will contain the 16-bit register context on entry and + exit. + + @param[in] This The protocol instance pointer. + @param[in] BiosInt The processor interrupt vector to invoke. + @param[in,out] Reg Register contexted passed into (and returned) f= rom thunk to + 16-bit mode. + + @retval TRUE Thunk completed with no BIOS errors in the t= arget code. See Regs for status. + @retval FALSE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_INT86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 BiosInt, + IN OUT EFI_IA32_REGISTER_SET *Regs + ); + +/** + Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the + 16-bit register context on entry and exit. Arguments can be passed on + the Stack argument + + @param[in] This The protocol instance pointer. + @param[in] Segment The segemnt of 16-bit mode call. + @param[in] Offset The offset of 16-bit mdoe call. + @param[in] Reg Register contexted passed into (and returned) fro= m thunk to + 16-bit mode. + @param[in] Stack The caller allocated stack used to pass arguments. + @param[in] StackSize The size of Stack in bytes. + + @retval FALSE Thunk completed with no BIOS errors in the= target code. See Regs for status. @retval = TRUE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_FARCALL86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT16 Segment, + IN UINT16 Offset, + IN EFI_IA32_REGISTER_SET *Regs, + IN VOID *Stack, + IN UINTN StackSize + ); + +/** + Test to see if a legacy PCI ROM exists for this device. Optionally return + the Legacy ROM instance for this PCI device. + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR wi= ll be loaded + @param[out] RomImage Return the legacy PCI ROM for this device. + @param[out] RomSize The size of ROM Image. + @param[out] Flags Indicates if ROM found and if PC-AT. Multiple bi= ts can be set as follows: + - 00 =3D No ROM. + - 01 =3D ROM Found. + - 02 =3D ROM is a valid legacy ROM. + + @retval EFI_SUCCESS The Legacy Option ROM available for this device + @retval EFI_UNSUPPORTED The Legacy Option ROM is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_CHECK_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, OPTIONAL + OUT UINTN *RomSize, OPTIONAL + OUT UINTN *Flags + ); + +/** + Load a legacy PC-AT OPROM on the PciHandle device. Return information + about how many disks were added by the OPROM and the shadow address and + size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C: + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM= BAR will be loaded. + This value is NULL if RomImage is non-NUL= L. This is the normal + case. + @param[in] RomImage A PCI PC-AT ROM image. This argument is n= on-NULL if there is + no hardware associated with the ROM and t= hus no PciHandle, + otherwise is must be NULL. + Example is PXE base code. + @param[out] Flags The type of ROM discovered. Multiple bits= can be set, as follows: + - 00 =3D No ROM. + - 01 =3D ROM found. + - 02 =3D ROM is a valid legacy ROM. + @param[out] DiskStart The disk number of first device hooked by= the ROM. If DiskStart + is the same as DiskEnd no disked were hoo= ked. + @param[out] DiskEnd disk number of the last device hooked by = the ROM. + @param[out] RomShadowAddress Shadow address of PC-AT ROM. + @param[out] RomShadowSize Size of RomShadowAddress in bytes. + + @retval EFI_SUCCESS Thunk completed, see Regs for status. + @retval EFI_INVALID_PARAMETER PciHandle not found + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_INSTALL_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + IN VOID **RomImage, + OUT UINTN *Flags, + OUT UINT8 *DiskStart, OPTIONAL + OUT UINT8 *DiskEnd, OPTIONAL + OUT VOID **RomShadowAddress, OPTIONAL + OUT UINT32 *ShadowedRomSize OPTIONAL + ); + +/** + This function attempts to traditionally boot the specified BootOption. I= f the EFI context has + been compromised, this function will not return. This procedure is not u= sed for loading an EFI-aware + OS off a traditional device. The following actions occur: + - Get EFI SMBIOS data structures, convert them to a traditional format, = and copy to + Compatibility16. + - Get a pointer to ACPI data structures and copy the Compatibility16 RSD= PTR to F0000 block. + - Find the traditional SMI handler from a firmware volume and register t= he traditional SMI + handler with the EFI SMI handler. + - Build onboard IDE information and pass this information to the Compati= bility16 code. + - Make sure all PCI Interrupt Line registers are programmed to match 825= 9. + - Reconfigure SIO devices from EFI mode (polled) into traditional mode (= interrupt driven). + - Shadow all PCI ROMs. + - Set up BDA and EBDA standard areas before the legacy boot. + - Construct the Compatibility16 boot memory map and pass it to the Compa= tibility16 code. + - Invoke the Compatibility16 table function Compatibility16PrepareToBoot= (). This + invocation causes a thunk into the Compatibility16 code, which sets al= l appropriate internal + data structures. The boot device list is a parameter. + - Invoke the Compatibility16 Table function Compatibility16Boot(). This = invocation + causes a thunk into the Compatibility16 code, which does an INT19. + - If the Compatibility16Boot() function returns, then the boot failed in= a graceful + manner--meaning that the EFI code is still valid. An ungraceful boot f= ailure causes a reset because the state + of EFI code is unknown. + + @param[in] This The protocol instance pointer. + @param[in] BootOption The EFI Device Path from BootXXXX variable. + @param[in] LoadOptionSize The size of LoadOption in size. + @param[in] LoadOption LThe oadOption from BootXXXX variable. + + @retval EFI_DEVICE_ERROR Failed to boot from any boot device and me= mory is uncorrupted. Note: This function nor= mally does not returns. It will either boot the = OS or reset the system if memory has been "corrupted" by loading = a boot sector and passing control to it. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN BBS_BBS_DEVICE_PATH *BootOption, + IN UINT32 LoadOptionsSize, + IN VOID *LoadOptions + ); + +/** + This function takes the Leds input parameter and sets/resets the BDA acc= ordingly. + Leds is also passed to Compatibility16 code, in case any special process= ing is required. + This function is normally called from EFI Setup drivers that handle user= -selectable + keyboard options such as boot with NUM LOCK on/off. This function does n= ot + touch the keyboard or keyboard LEDs but only the BDA. + + @param[in] This The protocol instance pointer. + @param[in] Leds The status of current Scroll, Num & Cap lock LEDS: + - Bit 0 is Scroll Lock 0 =3D Not locked. + - Bit 1 is Num Lock. + - Bit 2 is Caps Lock. + + @retval EFI_SUCCESS The BDA was updated successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 Leds + ); + +/** + Retrieve legacy BBS info and assign boot priority. + + @param[in] This The protocol instance pointer. + @param[out] HddCount The number of HDD_INFO structures. + @param[out] HddInfo Onboard IDE controller information. + @param[out] BbsCount The number of BBS_TABLE structures. + @param[in,out] BbsTable Points to List of BBS_TABLE. + + @retval EFI_SUCCESS Tables were returned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_BBS_INFO)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *HddCount, + OUT HDD_INFO **HddInfo, + OUT UINT16 *BbsCount, + IN OUT BBS_TABLE **BbsTable + ); + +/** + Assign drive number to legacy HDD drives prior to booting an EFI + aware OS so the OS can access drives without an EFI driver. + + @param[in] This The protocol instance pointer. + @param[out] BbsCount The number of BBS_TABLE structures + @param[out] BbsTable List of BBS entries + + @retval EFI_SUCCESS Drive numbers assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *BbsCount, + OUT BBS_TABLE **BbsTable + ); + +/** + To boot from an unconventional device like parties and/or execute + HDD diagnostics. + + @param[in] This The protocol instance pointer. + @param[in] Attributes How to interpret the other input parameter= s. + @param[in] BbsEntry The 0-based index into the BbsTable for th= e parent + device. + @param[in] BeerData A pointer to the 128 bytes of ram BEER dat= a. + @param[in] ServiceAreaData A pointer to the 64 bytes of raw Service A= rea data. The + caller must provide a pointer to the speci= fic Service + Area and not the start all Service Areas. + + @retval EFI_INVALID_PARAMETER If error. Does NOT return if no error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UDC_ATTRIBUTES Attributes, + IN UINTN BbsEntry, + IN VOID *BeerData, + IN VOID *ServiceAreaData + ); + +/** + Shadow all legacy16 OPROMs that haven't been shadowed. + Warning: Use this with caution. This routine disconnects all EFI + drivers. If used externally, then the caller must re-connect EFI + drivers. + + @param[in] This The protocol instance pointer. + + @retval EFI_SUCCESS OPROMs were shadowed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This + ); + +/** + Get a region from the LegacyBios for S3 usage. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of required region. + @param[in] Region The region to use. + 00 =3D Either 0xE0000 or 0xF0000 block. + - Bit0 =3D 1 0xF0000 block. + - Bit1 =3D 1 0xE0000 block. + @param[in] Alignment Address alignment. Bit mapped. The fir= st non-zero + bit from right is alignment. + @param[out] LegacyMemoryAddress The Region Assigned + + @retval EFI_SUCCESS The Region was assigned. + @retval EFI_ACCESS_DENIED The function was previously invoked. + @retval Other The Region was not assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN UINTN Region, + IN UINTN Alignment, + OUT VOID **LegacyMemoryAddress + ); + +/** + Get a region from the LegacyBios for Tiano usage. Can only be invoked on= ce. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of data to copy. + @param[in] LegacyMemoryAddress The Legacy Region destination ad= dress. + Note: must be in region assigned= by + LegacyBiosGetLegacyRegion. + @param[in] LegacyMemorySourceAddress The source of the data to copy. + + @retval EFI_SUCCESS The Region assigned. + @retval EFI_ACCESS_DENIED Destination was outside an assigned region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_COPY_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN VOID *LegacyMemoryAddress, + IN VOID *LegacyMemorySourceAddress + ); + +/// +/// Abstracts the traditional BIOS from the rest of EFI. The LegacyBoot() +/// member function allows the BDS to support booting a traditional OS. +/// EFI thunks drivers that make EFI bindings for BIOS INT services use +/// all the other member functions. +/// +struct _EFI_LEGACY_BIOS_PROTOCOL { + /// + /// Performs traditional software INT. See the Int86() function descript= ion. + /// + EFI_LEGACY_BIOS_INT86 Int86; + + /// + /// Performs a far call into Compatibility16 or traditional OpROM code. + /// + EFI_LEGACY_BIOS_FARCALL86 FarCall86; + + /// + /// Checks if a traditional OpROM exists for this device. + /// + EFI_LEGACY_BIOS_CHECK_ROM CheckPciRom; + + /// + /// Loads a traditional OpROM in traditional OpROM address space. + /// + EFI_LEGACY_BIOS_INSTALL_ROM InstallPciRom; + + /// + /// Boots a traditional OS. + /// + EFI_LEGACY_BIOS_BOOT LegacyBoot; + + /// + /// Updates BDA to reflect the current EFI keyboard LED status. + /// + EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS UpdateKeyboardLedStatus; + + /// + /// Allows an external agent, such as BIOS Setup, to get the BBS data. + /// + EFI_LEGACY_BIOS_GET_BBS_INFO GetBbsInfo; + + /// + /// Causes all legacy OpROMs to be shadowed. + /// + EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS ShadowAllLegacyOproms; + + /// + /// Performs all actions prior to boot. Used when booting an EFI-aware OS + /// rather than a legacy OS. + /// + EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI PrepareToBootEfi; + + /// + /// Allows EFI to reserve an area in the 0xE0000 or 0xF0000 block. + /// + EFI_LEGACY_BIOS_GET_LEGACY_REGION GetLegacyRegion; + + /// + /// Allows EFI to copy data to the area specified by GetLegacyRegion. + /// + EFI_LEGACY_BIOS_COPY_LEGACY_REGION CopyLegacyRegion; + + /// + /// Allows the user to boot off an unconventional device such as a PARTI= ES partition. + /// + EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE BootUnconventionalDevice; +}; + +// +// Legacy BIOS needs to access memory in page 0 (0-4095), which is disable= d if +// NULL pointer detection feature is enabled. Following macro can be used = to +// enable/disable page 0 before/after accessing it. +// +#define ACCESS_PAGE0_CODE(statements) \ + do { \ + EFI_STATUS Status_; \ + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc_; \ + \ + Desc_.Attributes =3D 0; \ + Status_ =3D gDS->GetMemorySpaceDescriptor (0, &Desc_); \ + ASSERT_EFI_ERROR (Status_); \ + if ((Desc_.Attributes & EFI_MEMORY_RP) !=3D 0) { \ + Status_ =3D gDS->SetMemorySpaceAttributes ( \ + 0, \ + EFI_PAGES_TO_SIZE(1), \ + Desc_.Attributes & ~(UINT64)EFI_MEMORY_RP \ + ); \ + ASSERT_EFI_ERROR (Status_); \ + } \ + \ + { \ + statements; \ + } \ + \ + if ((Desc_.Attributes & EFI_MEMORY_RP) !=3D 0) { \ + Status_ =3D gDS->SetMemorySpaceAttributes ( \ + 0, \ + EFI_PAGES_TO_SIZE(1), \ + Desc_.Attributes \ + ); \ + ASSERT_EFI_ERROR (Status_); \ + } \ + } while (FALSE) + +extern EFI_GUID gEfiLegacyBiosProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= Platform.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= Platform.h new file mode 100644 index 0000000000..b52ad94c3e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBiosPlatfor= m.h @@ -0,0 +1,752 @@ +/** @file + The EFI Legacy BIOS Patform Protocol is used to mate a Legacy16 + implementation with this EFI code. The EFI driver that produces + the Legacy BIOS protocol is generic and consumes this protocol. + A driver that matches the Legacy16 produces this protocol + + @copyright + Copyright 2007 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_BIOS_PLATFORM_H_ +#define _EFI_LEGACY_BIOS_PLATFORM_H_ + +/// +/// Legacy BIOS Platform depends on HDD_INFO and EFI_COMPATIBILITY16_TABLE= that +/// are defined with the Legacy BIOS Protocol +/// +#include + +#define EFI_LEGACY_BIOS_PLATFORM_PROTOCOL_GUID \ + { \ + 0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x9, 0x7, 0x9c, 0xc, 0x= b4 } \ + } + +typedef struct _EFI_LEGACY_BIOS_PLATFORM_PROTOCOL EFI_LEGACY_BIOS_PLATFORM= _PROTOCOL; + +/** + This enum specifies the Mode param values for GetPlatformInfo() +**/ +typedef enum { + /// + /// This mode is invoked twice. The first invocation has LegacySegment a= nd + /// LegacyOffset set to 0. The mode returns the MP table address in EFI = memory, along with its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the MP table is to be copie= d. The second + /// invocation allows any MP table address fixes to occur in the EFI mem= ory copy of the + /// MP table. The caller, not EfiGetPlatformBinaryMpTable, copies the mo= dified MP + /// table to the allocated region in 0xF0000 or 0xE0000 block after the = second invocation. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to the MP table. + /// + /// TableSize Size in bytes of the MP table. + /// + /// Location Location to place table. 0x00. Either 0xE0000 or 0xF0000 = 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit-mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + // LegacySegment Segment in which EfiCompatibility code will place th= e MP table. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = MP table. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The MP table was returned. + /// + /// EFI_UNSUPPORTED The MP table is not supported on this platform. + /// + EfiGetPlatformBinaryMpTable =3D 0, + /// + /// This mode returns a block of data. The content and usage is IBV or O= EM defined. + /// OEMs or IBVs normally use this function for nonstandard Compatibilit= y16 runtime soft + /// INTs. It is the responsibility of this routine to coalesce multiple = OEM 16 bit functions, if + /// they exist, into one coherent package that is understandable by the = Compatibility16 code. + /// This function is invoked twice. The first invocation has LegacySegme= nt and + /// LegacyOffset set to 0. The function returns the table address in EFI= memory, as well as its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the data (table) is to be c= opied. The second + /// invocation allows any data (table) address fixes to occur in the EFI= memory copy of + /// the table. The caller, not GetOemIntData(), copies the modified data= (table) to the + /// allocated region in 0xF0000 or 0xE0000 block after the second invoca= tion. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to OEM legacy 16 bit code or data. + /// + /// TableSize Size of data. + /// + /// Location Location to place table. 0x00. Either 0xE0000 or 0xF0000 = 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The data was returned successfully. + /// + /// EFI_UNSUPPORTED Oem INT is not supported on this platform. + /// + EfiGetPlatformBinaryOemIntData =3D 1, + /// + /// This mode returns a block of data. The content and usage is IBV defi= ned. OEMs or + /// IBVs normally use this mode for nonstandard Compatibility16 runtime = 16 bit routines. It + /// is the responsibility of this routine to coalesce multiple OEM 16 bi= t functions, if they + /// exist, into one coherent package that is understandable by the Compa= tibility16 code. + /// + /// Example usage: A legacy mobile BIOS that has a pre-existing runtime + /// interface to return the battery status to calling applications. + /// + /// This mode is invoked twice. The first invocation has LegacySegment a= nd + /// LegacyOffset set to 0. The mode returns the table address in EFI mem= ory and its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the table is to be copied. = The second + /// invocation allows any table address fixes to occur in the EFI memory= copy of the table. + /// The caller, not EfiGetPlatformBinaryOem16Data, copies the modified t= able to + /// the allocated region in 0xF0000 or 0xE0000 block after the second in= vocation. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to OEM legacy 16 bit code or data. + /// + /// TableSize Size of data. + /// + /// Location Location to place the table. 0x00. Either 0xE0000 or 0xF0= 000 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The data was returned successfully. + /// + /// EFI_UNSUPPORTED Oem16 is not supported on this platform. + /// + EfiGetPlatformBinaryOem16Data =3D 2, +/// +/// This mode returns a block of data. The content and usage are IBV defin= ed. OEMs or +/// IBVs normally use this mode for nonstandard Compatibility16 runtime 32= bit routines. It +/// is the responsibility of this routine to coalesce multiple OEM 32 bit = functions, if they +/// exist, into one coherent package that is understandable by the Compati= bility16 code. +/// +/// Example usage: A legacy mobile BIOS that has a pre existing runtime +/// interface to return the battery status to calling applications. +/// +/// This mode is invoked twice. The first invocation has LegacySegment and +/// LegacyOffset set to 0. The mode returns the table address in EFI memor= y and its size. +/// +/// The second invocation has LegacySegment and LegacyOffset set to the lo= cation +/// in the 0xF0000 or 0xE0000 block to which the table is to be copied. Th= e second +/// invocation allows any table address fix ups to occur in the EFI memory= copy of the table. +/// The caller, not EfiGetPlatformBinaryOem32Data, copies the modified tab= le to +/// the allocated region in 0xF0000 or 0xE0000 block after the second invo= cation.. +/// +/// Note: There are two generic mechanisms by which this mode can be used. +/// Mechanism 1: This mode returns the data and the Legacy BIOS Protocol c= opies +/// the data into the F0000 or E0000 block in the Compatibility16 code. The +/// EFI_COMPATIBILITY16_TABLE entries Oem32Segment and Oem32Offset can +/// be viewed as two UINT16 entries. +/// Mechanism 2: This mode directly fills in the EFI_COMPATIBILITY16_TABLE= with +/// a pointer to the INT15 E820 region containing the 32 bit code. It retu= rns +/// EFI_UNSUPPORTED. The EFI_COMPATIBILITY16_TABLE entries, +/// Oem32Segment and Oem32Offset, can be viewed as two UINT16 entries or +/// as a single UINT32 entry as determined by the IBV. +/// +/// The function parameters associated with this mode are: +/// +/// TableSize Size of data. +/// +/// Location Location to place the table. 0x00 or 0xE0000 or 0xF0000 64 = KB blocks. +/// Bit 0 =3D 1 0xF0000 64 KB block. +/// Bit 1 =3D 1 0xE0000 64 KB block. +/// Multiple bits can be set. +/// +/// Alignment Bit mapped address alignment granularity. +/// The first nonzero bit from the right is the address granularity. +/// +/// LegacySegment Segment in which EfiCompatibility code will place the = table or data. +/// +/// LegacyOffset Offset in which EfiCompatibility code will place the ta= ble or data. +/// +/// The return values associated with this mode are: +/// EFI_SUCCESS The data was returned successfully. +/// EFI_UNSUPPORTED Oem32 is not supported on this platform. +/// +EfiGetPlatformBinaryOem32Data =3D 3, + /// + /// This mode returns a TPM binary image for the onboard TPM device. + /// + /// The function parameters associated with this mode are: + /// + /// Table TPM binary image for the onboard TPM device. + /// + /// TableSize Size of BinaryImage in bytes. + /// + /// Location Location to place the table. 0x00. Either 0xE0000 or 0xF0= 000 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS BinaryImage is valid. + /// + /// EFI_UNSUPPORTED Mode is not supported on this platform. + /// + /// EFI_NOT_FOUND No BinaryImage was found. + /// + EfiGetPlatformBinaryTpmBinary =3D 4, + /// + /// The mode finds the Compatibility16 Rom Image. + /// + /// The function parameters associated with this mode are: + /// + /// System ROM image for the platform. + /// + /// TableSize Size of Table in bytes. + /// + /// Location Ignored. + /// + /// Alignment Ignored. + /// + /// LegacySegment Ignored. + /// + /// LegacyOffset Ignored. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS ROM image found. + /// + /// EFI_NOT_FOUND ROM not found. + /// + EfiGetPlatformBinarySystemRom =3D 5, + /// + /// This mode returns the Base address of PciExpress memory mapped confi= guration + /// address space. + /// + /// The function parameters associated with this mode are: + /// + /// Table System ROM image for the platform. + /// + /// TableSize Size of Table in bytes. + /// + /// Location Ignored. + /// + /// Alignment Ignored. + /// + /// LegacySegment Ignored. + /// + /// LegacyOffset Ignored. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS Address is valid. + /// + /// EFI_UNSUPPORTED System does not PciExpress. + /// + EfiGetPlatformPciExpressBase =3D 6, + /// + EfiGetPlatformPmmSize =3D 7, + /// + EfiGetPlatformEndOpromShadowAddr =3D 8, + /// +} EFI_GET_PLATFORM_INFO_MODE; + +/** + This enum specifies the Mode param values for GetPlatformHandle(). +**/ +typedef enum { + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the VGA + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all VGA handles found. + /// + /// HandleCount Number of VGA handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformVgaHandle =3D 0, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the IDE + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all IDE handles found. + /// + /// HandleCount Number of IDE handles found. + /// + /// AdditionalData Pointer to HddInfo. + /// Information about all onboard IDE controllers. + /// + EfiGetPlatformIdeHandle =3D 1, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the ISA bus + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all ISA bus handles found. + /// + /// HandleCount Number of ISA bus handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformIsaBusHandle =3D 2, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the USB + /// device used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all USB handles found. + /// + /// HandleCount Number of USB bus handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformUsbHandle =3D 3 +} EFI_GET_PLATFORM_HANDLE_MODE; + +/** + This enum specifies the Mode param values for PlatformHooks(). + Note: Any OEM defined hooks start with 0x8000. +**/ +typedef enum { + /// + /// This mode allows any preprocessing before scanning OpROMs. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle Handle of device OpROM is associated with. + /// + /// ShadowAddress Address where OpROM is shadowed. + /// + /// Compatibility16Table NULL. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookPrepareToScanRom =3D 0, + /// + /// This mode shadows legacy OpROMS that may not have a physical device = associated with + /// them. It returns EFI_SUCCESS if the ROM was shadowed. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle 0. + /// + /// ShadowAddress First free OpROM area, after other OpROMs have bee= n dispatched.. + /// + /// Compatibility16Table Pointer to the Compatability16 Table. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookShadowServiceRoms=3D 1, + /// + /// This mode allows platform to perform any required operation after an= OpROM has + /// completed its initialization. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle Handle of device OpROM is associated with. + /// + /// ShadowAddress Address where OpROM is shadowed. + /// + /// Compatibility16Table NULL. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookAfterRomInit =3D 2 +} EFI_GET_PLATFORM_HOOK_MODE; + +/// +/// This IRQ has not been assigned to PCI. +/// +#define PCI_UNUSED 0x00 +/// +/// This IRQ has been assigned to PCI. +/// +#define PCI_USED 0xFF +/// +/// This IRQ has been used by an SIO legacy device and cannot be used by P= CI. +/// +#define LEGACY_USED 0xFE + +#pragma pack(1) + +typedef struct { + /// + /// IRQ for this entry. + /// + UINT8 Irq; + /// + /// Status of this IRQ. + /// + /// PCI_UNUSED 0x00. This IRQ has not been assigned to PCI. + /// + /// PCI_USED 0xFF. This IRQ has been assigned to PCI. + /// + /// LEGACY_USED 0xFE. This IRQ has been used by an SIO legacy + /// device and cannot be used by PCI. + /// + UINT8 Used; +} EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY; + +// +// Define PIR table structures +// +#define EFI_LEGACY_PIRQ_TABLE_SIGNATURE SIGNATURE_32 ('$', 'P', 'I', 'R') + +typedef struct { + /// + /// $PIR. + /// + UINT32 Signature; + /// + /// 0x00. + /// + UINT8 MinorVersion; + /// + /// 0x01 for table version 1.0. + /// + UINT8 MajorVersion; + /// + /// 0x20 + RoutingTableEntries * 0x10. + /// + UINT16 TableSize; + /// + /// PCI interrupt router bus. + /// + UINT8 Bus; + /// + /// PCI interrupt router device/function. + /// + UINT8 DevFun; + /// + /// If nonzero, bit map of IRQs reserved for PCI. + /// + UINT16 PciOnlyIrq; + /// + /// Vendor ID of a compatible PCI interrupt router. + /// + UINT16 CompatibleVid; + /// + /// Device ID of a compatible PCI interrupt router. + /// + UINT16 CompatibleDid; + /// + /// If nonzero, a value passed directly to the IRQ miniport's Initialize= function. + /// + UINT32 Miniport; + /// + /// Reserved for future usage. + /// + UINT8 Reserved[11]; + /// + /// This byte plus the sum of all other bytes in the LocalPirqTable equa= l 0x00. + /// + UINT8 Checksum; +} EFI_LEGACY_PIRQ_TABLE_HEADER; + + +typedef struct { + /// + /// If nonzero, a value assigned by the IBV. + /// + UINT8 Pirq; + /// + /// If nonzero, the IRQs that can be assigned to this device. + /// + UINT16 IrqMask; +} EFI_LEGACY_PIRQ_ENTRY; + +typedef struct { + /// + /// PCI bus of the entry. + /// + UINT8 Bus; + /// + /// PCI device of this entry. + /// + UINT8 Device; + /// + /// An IBV value and IRQ mask for PIRQ pins A through D. + /// + EFI_LEGACY_PIRQ_ENTRY PirqEntry[4]; + /// + /// If nonzero, the slot number assigned by the board manufacturer. + /// + UINT8 Slot; + /// + /// Reserved for future use. + /// + UINT8 Reserved; +} EFI_LEGACY_IRQ_ROUTING_ENTRY; + +#pragma pack() + + +/** + Finds the binary data or other platform information. + + @param This The protocol instance pointer. + @param Mode Specifies what data to return. See See EFI= _GET_PLATFORM_INFO_MODE enum. + @param Table Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param TableSize Mode specific. See EFI_GET_PLATFORM_INFO= _MODE enum. + @param Location Mode specific. See EFI_GET_PLATFORM_INFO= _MODE enum. + @param Alignment Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param LegacySegment Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param LegacyOffset Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + + @retval EFI_SUCCESS Data returned successfully. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + @retval EFI_NOT_FOUND Binary image or table not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_INFO)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_INFO_MODE Mode, + OUT VOID **Table, + OUT UINTN *TableSize, + OUT UINTN *Location, + OUT UINTN *Alignment, + IN UINT16 LegacySegment, + IN UINT16 LegacyOffset + ); + +/** + Returns a buffer of handles for the requested subfunction. + + @param This The protocol instance pointer. + @param Mode Specifies what handle to return. See EFI_G= ET_PLATFORM_HANDLE_MODE enum. + @param Type Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param HandleBuffer Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param HandleCount Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param AdditionalData Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + + @retval EFI_SUCCESS Handle is valid. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + @retval EFI_NOT_FOUND Handle is not known. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_HANDLE)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_HANDLE_MODE Mode, + IN UINT16 Type, + OUT EFI_HANDLE **HandleBuffer, + OUT UINTN *HandleCount, + IN VOID **AdditionalData OPTIONAL + ); + +/** + Load and initialize the Legacy BIOS SMM handler. + + @param This The protocol instance pointer. + @param EfiToLegacy16BootTable A pointer to Legacy16 boot table. + + @retval EFI_SUCCESS SMM code loaded. + @retval EFI_DEVICE_ERROR SMM code failed to load + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_SMM_INIT)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN VOID *EfiToLegacy16BootTable + ); + +/** + Allows platform to perform any required action after a LegacyBios operat= ion. + Invokes the specific sub function specified by Mode. + + @param This The protocol instance pointer. + @param Mode Specifies what handle to return. See EFI_G= ET_PLATFORM_HOOK_MODE enum. + @param Type Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param DeviceHandle Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param ShadowAddress Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param Compatibility16Table Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param AdditionalData Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + + @retval EFI_SUCCESS The operation performed successfully. Mode= specific. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_HOOKS)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_HOOK_MODE Mode, + IN UINT16 Type, + IN EFI_HANDLE DeviceHandle, OPTIONAL + IN OUT UINTN *ShadowAddress, OPTIONAL + IN EFI_COMPATIBILITY16_TABLE *Compatibility16Table, OPTIONAL + OUT VOID **AdditionalData OPTIONAL + ); + +/** + Returns information associated with PCI IRQ routing. + This function returns the following information associated with PCI IRQ = routing: + * An IRQ routing table and number of entries in the table. + * The $PIR table and its size. + * A list of PCI IRQs and the priority order to assign them. + + @param This The protocol instance pointer. + @param RoutingTable The pointer to PCI IRQ Routing table. + This location is the $PIR table minus th= e header. + @param RoutingTableEntries The number of entries in table. + @param LocalPirqTable $PIR table. + @param PirqTableSize $PIR table size. + @param LocalIrqPriorityTable A list of interrupts in priority order t= o assign. + @param IrqPriorityTableEntries The number of entries in the priority ta= ble. + + @retval EFI_SUCCESS Data was successfully returned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_ROUTING_TABLE)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + OUT VOID **RoutingTable, + OUT UINTN *RoutingTableEntries, + OUT VOID **LocalPirqTable, OPTIONAL + OUT UINTN *PirqTableSize, OPTIONAL + OUT VOID **LocalIrqPriorityTable, OPTIONAL + OUT UINTN *IrqPriorityTableEntries OPTIONAL + ); + +/** + Translates the given PIRQ accounting for bridge. + This function translates the given PIRQ back through all buses, if requi= red, + and returns the true PIRQ and associated IRQ. + + @param This The protocol instance pointer. + @param PciBus The PCI bus number for this device. + @param PciDevice The PCI device number for this device. + @param PciFunction The PCI function number for this device. + @param Pirq Input is PIRQ reported by device, and outp= ut is true PIRQ. + @param PciIrq The IRQ already assigned to the PIRQ, or t= he IRQ to be + assigned to the PIRQ. + + @retval EFI_SUCCESS The PIRQ was translated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_TRANSLATE_PIRQ)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN UINTN PciBus, + IN UINTN PciDevice, + IN UINTN PciFunction, + IN OUT UINT8 *Pirq, + OUT UINT8 *PciIrq + ); + +/** + Attempt to legacy boot the BootOption. If the EFI contexted has been + compromised this function will not return. + + @param This The protocol instance pointer. + @param BbsDevicePath The EFI Device Path from BootXXXX variabl= e. + @param BbsTable The Internal BBS table. + @param LoadOptionSize The size of LoadOption in size. + @param LoadOption The LoadOption from BootXXXX variable + @param EfiToLegacy16BootTable A pointer to BootTable structure + + @retval EFI_SUCCESS Ready to boot. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_PREPARE_TO_BOOT)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN BBS_BBS_DEVICE_PATH *BbsDevicePath, + IN VOID *BbsTable, + IN UINT32 LoadOptionsSize, + IN VOID *LoadOptions, + IN VOID *EfiToLegacy16BootTable + ); + +/** + This protocol abstracts the platform portion of the traditional BIOS. +**/ +struct _EFI_LEGACY_BIOS_PLATFORM_PROTOCOL { + /// + /// Gets binary data or other platform information. + /// + EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_INFO GetPlatformInfo; + /// + /// Returns a buffer of all handles matching the requested subfunction. + /// + EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_HANDLE GetPlatformHandle; + /// + /// Loads and initializes the traditional BIOS SMM handler. + EFI_LEGACY_BIOS_PLATFORM_SMM_INIT SmmInit; + /// + /// Allows platform to perform any required actions after a LegacyBios = operation. + /// + EFI_LEGACY_BIOS_PLATFORM_HOOKS PlatformHooks; + /// + /// Gets $PIR table. + EFI_LEGACY_BIOS_PLATFORM_GET_ROUTING_TABLE GetRoutingTable; + /// + /// Translates the given PIRQ to the final value after traversing any P= CI bridges. + /// + EFI_LEGACY_BIOS_PLATFORM_TRANSLATE_PIRQ TranslatePirq; + /// + /// Final platform function before the system attempts to boot to a tra= ditional OS. + /// + EFI_LEGACY_BIOS_PLATFORM_PREPARE_TO_BOOT PrepareToBoot; +}; + +extern EFI_GUID gEfiLegacyBiosPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlat= form.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlatform= .h new file mode 100644 index 0000000000..77423481ce --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h @@ -0,0 +1,72 @@ +/** @file + This file declares PCI IOV platform protocols. + + @copyright + Copyright 2005 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_IOV_PLATFORM_H_ +#define _PCI_IOV_PLATFORM_H_ + + +// +// Protocol for GUID. +// + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL EFI_PCI_IOV_PLATFORM_PROTOCO= L; + +typedef UINT32 EFI_PCI_IOV_PLATFORM_POLICY; + +#define EFI_PCI_IOV_POLICY_ARI 0x0001 +#define EFI_PCI_IOV_POLICY_SRIOV 0x0002 +#define EFI_PCI_IOV_POLICY_MRIOV 0x0004 + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +/** + + The GetPlatformPolicy() function retrieves the platform policy regardi= ng PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +; + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL { + EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE GetSystemLowes= tPageSize; + EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY GetPlatformPol= icy; +} EFI_PCI_IOV_PLATFORM_PROTOCOL; + +extern EFI_GUID gEfiPciIovPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformTy= pe.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformType.h new file mode 100644 index 0000000000..6fdfea0fde --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformType.h @@ -0,0 +1,48 @@ +/** @file + This file defines platform policies for Platform Type. + + @copyright + Copyright 1996 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_TYPE_H_ +#define _PLATFORM_TYPE_H_ + +#include + +typedef struct _EFI_PLATFORM_TYPE_PROTOCOL { + UINT8 SystemUuid[16]; // 16 bytes + UINT32 Signature; // "$PIT" 0x54495024 + UINT32 Size; // Size of the table + UINT16 Revision; // Revision of the table + UINT16 Type; // Platform Type + UINT32 CpuType; // Cpu Type + UINT8 CpuStepping; // Cpu Stepping + UINT32 TypeRevisionId; // Board Revision ID + UINT16 IioSku; + UINT16 IioRevision; + UINT16 PchSku; + UINT16 PchRevision; + UINT16 PchType; // Retrive PCH SKU type = installed + BOOLEAN ExtendedInfoValid; // If TRUE then below fi= elds are Valid + UINT8 Checksum; // Checksum minus System= Uuid is valid in DXE only. + UINT64 TypeStringPtr; + UINT64 IioStringPtr; + UINT64 PchStringPtr; + EFI_PLATFORM_PCI_DATA PciData; + EFI_PLATFORM_CPU_DATA CpuData; + EFI_PLATFORM_MEM_DATA MemData; + EFI_PLATFORM_SYS_DATA SysData; + EFI_PLATFORM_PCH_DATA PchData; + UINT8 IioRiserId; + UINT8 BoardId; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 Emulation; // 100b =3D Simics +} EFI_PLATFORM_TYPE_PROTOCOL; + +extern EFI_GUID gEfiPlatformTypeProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h= b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h new file mode 100644 index 0000000000..658188e467 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h @@ -0,0 +1,114 @@ +/** @file + uba central config database Protocol + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_H_ +#define _UBA_CONFIG_DATABASE_H_ + +// {E03E0D46-5263-4845-B0A4-58D57B3177E2} +#define UBA_CONFIG_DATABASE_PROTOCOL_GUID \ + { 0xe03e0d46, 0x5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77= , 0xe2 } } + + +typedef struct _UBA_CONFIG_DATABASE_PROTOCOL UBA_CONFIG_DATABASE_PROTOCOL; + +#define UBA_CONFIG_PROTOCOL_SIGNATURE SIGNATURE_32('M', 'S', 'K', 'P') +#define UBA_CONFIG_PROTOCOL_VERSION 0x01 + +/** + Get platform's GUID and user friendly name by PlatformType. + + This is used when you need a PlatformId to Add/Get platform data + + Core will create a new platform for you if the PlatformType is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Protocol instance. + @param PlatformType The platform type, same define as Platform= .h. + @param PlatformId The GUID for this platform. + @param PlatformName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_GET_PLATFORM) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + OUT UINT32 *PlatformType, + OUT EFI_GUID *PlatformId, + OUT CHAR8 *PlatformName + ); + +/** + Add configuration data to uba configuration database. + + @param This uba Protocol instance. + @param PlatformId The GUID for this platform. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_ADD_DATA) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get configuration data from uba configuration database. + + @param This uba Protocol instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_GET_DATA) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + OUT UINTN *DataSize + ); + + +// +// UbaConfigDatabaseProtocol +// +struct _UBA_CONFIG_DATABASE_PROTOCOL { + UINT32 Signature; + UINT32 Version; + + UBA_CONFIG_GET_PLATFORM GetSku; + UBA_CONFIG_ADD_DATA AddData; + UBA_CONFIG_GET_DATA GetData; +}; + +extern EFI_GUID gUbaConfigDatabaseProtocolGuid; + +#endif // __UBA_CONFIG_DATABASE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevsUpd= ateProtocol.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevs= UpdateProtocol.h new file mode 100644 index 0000000000..ee7fabc719 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevsUpdateProt= ocol.h @@ -0,0 +1,86 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLT_DEVS_UPDATE_H_ +#define _PLT_DEVS_UPDATE_H_ + +// {1E22C6FA-B39E-419a-A071-D60B672B21C8} +#define EFI_PLT_DEVS_UPDATE_GUID \ + { \ + 0x1e22c6fa, 0xb39e, 0x419a, { 0xa0, 0x71, 0xd6, 0xb, 0x67, 0x2b, 0x21, = 0xc8 }\ + } + +#define PORTNUMMAX 8 + +typedef struct _EFI_PLT_DEVS_UPDATE_PROTOCOL EFI_PLT_DEVS_UPDATE_PROTOCOL; + +typedef enum { + NET_PXE_1GB =3D 0, + NET_PXE_10GB =3D 1, + NET_ISCSI =3D 2, + NET_FCOE =3D 3, + NET_INFINITBADN =3D 4 +} OPROM_FILE_TYPE; + +typedef enum { + HIDDEN =3D 0, + ONBOARD_NIC =3D 1, + IO_MODULE_NIC =3D 2, +} NIC_TYPE; + +typedef enum { + UNDEF =3D 0, + ETHERNET =3D 1, + INFIBAND =3D 2 +} NIC_SUB_TYPE; + +#define DFT_MAC_SIZE 0x20 +#define DFT_GUID_SIZE 0x64 + +#define PXE1GBit 0x1 +#define PXE10GBit 0x2 +#define FcoeBit 0x4 +#define iSCSIBit 0x8 + +#pragma pack(1) +typedef struct _PLAT_NIC_SETUP_INFO{ + NIC_TYPE NicType; //Onboard or IO module + NIC_SUB_TYPE NicSubType; //Ethernect or Infinitband c= ontroller + UINT8 NicIndex; //Onboard Nic1,2,3 or IOM 1,= 2,3 per setup option + UINT8 RootPortBusNo; //Root Bridge Bus No + UINT8 RootPortDevNo; //Root Bridge device No + UINT8 RootPortFunNo; //Root Bridge Function No + UINT16 NicVID; //Nic Vendor ID + UINT16 NicDID; //Nic Device ID + UINT16 SubDID; //Nic Subsystem ID + UINT8 PortNumbers; //Ports numbder after detect= ion + CHAR8 NicDescription[64]; //Nic description defined in= Eps + EFI_MAC_ADDRESS PortMacAddress[PORTNUMMAX]; + EFI_GUID InfinitbandGuid; + UINT8 OpROMCapMap; + UINT8 IsPchNIC; +}PLAT_NIC_SETUP_INFO; +#pragma pack() + +typedef EFI_STATUS (*PLATFORM_HKS_GET_EMBEDED_OPTIONROM) (IN EFI_PLT_DEVS_= UPDATE_PROTOCOL *This, IN EFI_HANDLE PciHandle,OPROM_FILE_TYPE OpRomType); +typedef EFI_STATUS (*PLATFORM_HKS_DISPATCH_OPTIONROM) (IN EFI_PLT_DEVS_UPD= ATE_PROTOCOL *This, IN EFI_HANDLE PciHandle); +typedef EFI_STATUS (*PLATFORM_HKS_BDS_UPDATE_MAC) (IN EFI_PLT_DEVS_UPDATE_= PROTOCOL *This); +typedef EFI_STATUS (*PLATFORM_HKS_ON_ENTER_SETUP) (IN EFI_PLT_DEVS_UPDATE_= PROTOCOL *This, OUT PLAT_NIC_SETUP_INFO **NicInfo, OUT UINT8 *NicNum); + +typedef struct _EFI_PLT_DEVS_UPDATE_PROTOCOL { + PLATFORM_HKS_GET_EMBEDED_OPTIONROM PlatformHooksOnGettingEmbed= OpRom; + PLATFORM_HKS_DISPATCH_OPTIONROM PlatformHooksOnDispatchOpRo= m; + PLATFORM_HKS_BDS_UPDATE_MAC PlatformHooksBdsUpdateMac; + PLATFORM_HKS_ON_ENTER_SETUP PlatformHooksGetNicInfo; +} EFI_PLT_DEVS_UPDATE_PROTOCOL; + +extern EFI_GUID gEfiPlatformDevsUpdateProtocolGuid; +extern EFI_GUID gEfiVMDDriverProtocolGuid; +extern EFI_GUID gEfiHfiPcieGen3ProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerPr= otocol.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerProt= ocol.h new file mode 100644 index 0000000000..31ad158860 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerProtocol.h @@ -0,0 +1,22 @@ +/** @file + GUID variable for multi-boards support in DXE phase. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __UBA_MAKER_PROTOCOL_H__ +#define __UBA_MAKER_PROTOCOL_H__ + + +extern EFI_GUID gEfiPlatformTypeNeonCityEPRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeHedtCRBProtocolGuid; +extern EFI_GUID gEfiPlatformTypeLightningRidgeEXRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid; +extern EFI_GUID gEfiPlatformTypeWilsonCityRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeWilsonCityModularProtocolGuid; +extern EFI_GUID gEfiPlatformTypeIsoscelesPeakProtocolGuid; + +#endif // #ifndef __UBA_MAKER_PROTOCOL_H__ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h b/Plat= form/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h new file mode 100644 index 0000000000..c3a8e931d5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h @@ -0,0 +1,25 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_TABLE_H_ +#define _SETUP_TABLE_H_ +#include +#include + +#include +#include +#include + +typedef struct { + SOCKET_CONFIGURATION SocketConfig; + SYSTEM_CONFIGURATION SystemConfig; + PCH_SETUP PchSetup; + MEM_BOOT_HEALTH_CONFIG MemBootHealthConfig; +} SETUP_DATA; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h b/Platfor= m/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..6f848d536d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,251 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +typedef struct { + UINT8 Index; + UINT8 Value; +} SIO_INDEX_DATA; + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +// +// COM (Serial) Port Base address +// +#define SIO_BASE_COM1 0x3F8 +#define SIO_BASE_COM2 0x2F8 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define PRIMARY_INTERRUPT_SELECT 0x70 +#define INTERRUPT_TYPE 0x71 + +// +//ASPEED AST2500 register +// +#define ASPEED2500_SIO_INDEX_PORT 0x2E +#define ASPEED2500_SIO_DATA_PORT (ASPEED2500_SIO_INDEX_PORT+1) + +#define ASPEED2500_SIO_UART1 0x02 +#define ASPEED2500_SIO_UART2 0x03 +#define ASPEED2500_SIO_SMI 0x0D +#define ASPEED2500_SIO_MAILBOX 0x0E + +#define SCU7C 0x1e6e207c + +#define ASPEED2500_SIO_UNLOCK 0xA5 +#define ASPEED2500_SIO_LOCK 0xAA + +// +// Port address for PILOT-IV +// +#define PILOTIV_CHIP_ID 0x03 +#define PILOTIV_SIO_INDEX_PORT 0x2E +#define PILOTIV_SIO_DATA_PORT (PILOTIV_SIO_INDEX_PORT+1) + +#define PILOTIV_SIO_UNLOCK 0x5A +#define PILOTIV_SIO_LOCK 0xA5 +#define PILOTIV_UNLOCK 0x5A +#define PILOTIV_LOCK 0xA5 + +#define PILOTIV_SIO_PSR 0x00 +#define PILOTIV_SIO_COM2 0x01 +#define PILOTIV_SIO_COM1 0x02 +#define PILOTIV_SIO_SWCP 0x03 +#define PILOTIV_SIO_GPIO 0x04 +#define PILOTIV_SIO_WDT 0x05 + +#define PILOTIV_SIO_KCS3 0x08 +#define PILOTIV_SIO_KCS4 0x09 +#define PILOTIV_SIO_KCS5 0x0A +#define PILOTIV_SIO_BT 0x0B +#define PILOTIV_SIO_SMIC 0x0C +#define PILOTIV_SIO_MAILBOX 0x0D +#define PILOTIV_SIO_RTC 0x0E +#define PILOTIV_SIO_SPI 0x0F +#define PILOTIV_SIO_TAP 0x10 + +// +// Register for Pilot IV +// +#define PILOTIV_CHIP_ID_REG 0x20 +#define PILOTIV_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PILOTIV_ACTIVATE ACTIVATE +#define PILOTIV_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PILOTIV_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PILOTIV_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1 +#define PILOTIV_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1 +#define PILOTIV_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT + + +// +// Port address for PC8374 +// +#define PC8374_CHIP_ID 0xF1 +#define PC8374_SIO_INDEX_PORT 0x02E +#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1) + +// +// Logical device in PC8374 +// +#define PC8374_SIO_FLOPPY 0x00 +#define PC8374_SIO_PARA 0x01 +#define PC8374_SIO_COM2 0x02 +#define PC8374_SIO_COM1 0x03 +#define PC8374_SIO_MOUSE 0x05 +#define PC8374_SIO_KYBD 0x06 +#define PC8374_SIO_GPIO 0x07 + +// +// Registers specific for PC8374 +// +#define PC8374_CLOCK_SELECT 0x2D +#define PC8374_CLOCK_CONFIG 0x29 + +// +// Registers for PC8374 +// +#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PC8374_ACTIVATE ACTIVATE +#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT +#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0 +#define PC8374_CHIP_ID_REG 0x20 + +#define PC87427_SERVERIO_CNF2 0x22 + + + +// +// Port address for NCT5104D +// +#define NCT5104D_SIO_INDEX_PORT 0x4E +#define NCT5104D_SIO_DATA_PORT (NCT5104D_SIO_INDEX_PORT+1) + +// +// Registers for NCT5104D +// +#define NCT5104D_CHIP_ID_REG 0x20 +#define NCT5104D_CHIP_ID 0xC4 +#define NCT5104D_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define NCT5104D_ACTIVATE ACTIVATE +#define NCT5104D_SIO_UARTA 2 +#define NCT5104D_SIO_COM1 3 +#define NCT5104D_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define NCT5104D_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define NCT5104D_WAKEUP_ON_IRQ_EN 0x70 +#define NCT5104D_ENTER_THE_EXTENDED_FUNCTION_MODE 0x87 +#define NCT5104D_EXIT_THE_EXTENDED_FUNCTION_MODE 0xAA +// +// Port address for W83527 +// +#define W83527_SIO_INDEX_PORT 0x02E +#define W83527_SIO_DATA_PORT (W83527_SIO_INDEX_PORT+1) + +// +// Logical device in W83527 +// +#define W83527_SIO_KYBD 0x05 +#define W83527_SIO_WDTO 0x08 +#define W83527_SIO_GPIO 0x09 +#define W83527_SIO_ACPI 0x0A +#define W83527_SIO_HWM 0x0B +#define W83527_SIO_PCEI 0x0C + +// +// Registers for W83527 +// +#define W83527_EXT_MODE_START 0x87 +#define W83527_EXT_MODE_STOP 0xAA +#define W83527_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define W83527_ACTIVATE_REG 0x30 +#define W83527_ACTIVATE ACTIVATE +#define W83527_CHIP_ID_REG 0x20 +#define W83527_CHIP_ID 0xB0 +#define W83527_CLOCK_REG 0x24 +#define W83527_KBC_BASE1_HI_ADDR_REG 0x60 +#define W83527_KBC_BASE1_LO_ADDR_REG 0x61 +#define W83527_KBC_BASE2_HI_ADDR_REG 0x62 +#define W83527_KBC_BASE2_LO_ADDR_REG 0x63 +#define W83527_KBC_BASE1_HI_ADDR 0x00 +#define W83527_KBC_BASE1_LO_ADDR 0x60 +#define W83527_KBC_BASE2_HI_ADDR 0x00 +#define W83527_KBC_BASE2_LO_ADDR 0x64 +#define W83527_KBC_KB_IRQ_REG 0x70 +#define W83527_KBC_KB_IRQ 0x01 +#define W83527_KBC_MS_IRQ_REG 0x72 +#define W83527_KBC_MS_IRQ 0x0C +#define W83527_KBC_CFG_REG 0xF0 +#define W83527_KBC_CFG 0x83 +#define W83527_KBC_CLOCK 0x01 +#define W83527_EXT_MODE_START 0x87 +#define W83527_EXT_MODE_END 0xAA + + +// +// Select Clock for W83527, 0 / 1 for 24MHz / 48MHz +// +#define W83527_CLOCK_BIT 0x06 +#define W83527_CLOCK 0x01 + +// +// Initialize Key Board Controller +// +#define W83527_KeyBoard 1 + + +// +// Pilot II Mailbox Data Register definitions +// +#define MBDAT00_OFFSET 0x00 +#define MBDAT01_OFFSET 0x01 +#define MBDAT02_OFFSET 0x02 +#define MBDAT03_OFFSET 0x03 +#define MBDAT04_OFFSET 0x04 +#define MBDAT05_OFFSET 0x05 +#define MBDAT06_OFFSET 0x06 +#define MBDAT07_OFFSET 0x07 +#define MBDAT08_OFFSET 0x08 +#define MBDAT09_OFFSET 0x09 +#define MBDAT10_OFFSET 0x0A +#define MBDAT11_OFFSET 0x0B +#define MBDAT12_OFFSET 0x0C +#define MBDAT13_OFFSET 0x0D +#define MBDAT14_OFFSET 0x0E +#define MBDAT15_OFFSET 0x0F +#define MBST0_OFFSET 0x10 +#define MBST1_OFFSET 0x11 + +// +// If both are there, use the default one +// + +#define ASPEED_EXIST BIT4 +#define NCT5104D_EXIST BIT3 +#define W83527_EXIST BIT2 +#define PC8374_EXIST BIT1 +#define PILOTIV_EXIST BIT0 +#define DEFAULT_SIO PILOTIV_EXIST +#define DEFAULT_KDB PC8374_EXIST + +#define IPMI_DEFAULT_SMM_IO_BASE 0xca2 +#define PILOTIV_SWC_BASE_ADDRESS 0xA00 +#define PILOTIV_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80 +#define PILOTIV_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84 +#define PILOTIV_GPE1_BLK_BASE_ADDRESS 0x0A86 +#define PILOTIV_KCS3_DATA_BASE_ADDRESS 0x0CA4 +#define PILOTIV_KCS3_CMD_BASE_ADDRESS 0x0CA5 +#define PILOTIV_KCS4_DATA_BASE_ADDRESS 0x0CA2 +#define PILOTIV_KCS4_CMD_BASE_ADDRESS 0x0CA3 +#define PILOTIV_MAILBOX_BASE_ADDRESS 0x0600 +#define PILOTIV_MAILBOX_MASK 0xFFE0 +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h b/Pla= tform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h new file mode 100644 index 0000000000..fda7ccf523 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h @@ -0,0 +1,75 @@ +/** @file + This protocol is EFI compatible. + + @copyright + Copyright 2005 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SYSTEM_BOARD_H_ +#define _DXE_SYSTEM_BOARD_H_ + +#include +#include +#include + +#define PCI_DEVICE_NUMBER_IMC0_CH_0 0x08 +#define PCI_FUNCTION_NUMBER_IMC0_CH_0 0 +#define PCI_DEVICE_ID_IMC0_CH_0 0x2014 +#define BIOSGUARD_SUPPORT_ENABLED BIT0 +#define OC_SUPPORT_ENABLED BIT1 + +#ifndef __AML_OFFSET_TABLE_H +#define __AML_OFFSET_TABLE_H + +typedef struct { + char *Pathname; /* Full pathname (from root) to= the object */ + unsigned short ParentOpcode; /* AML opcode for the parent ob= ject */ + unsigned long NamesegOffset; /* Offset of last nameseg in th= e parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (= as applicable) */ +} AML_OFFSET_TABLE_ENTRY; +#endif + +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ + { \ + 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00 } \ + } + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + +// +// System board information table +// +typedef struct { + // + // Pci option ROM data + // + PCI_OPTION_ROM_TABLE *PciOptionRomTable; + + // + // System CPU data + // + UINT32 CpuSocketCount; + + // + // System device and irq routing data + // + DEVICE_DATA *DeviceData; + PLATFORM_PIRQ_DATA *SystemPirqData; +} DXE_SYSTEM_BOARD_INFO; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h b/Platform= /Intel/WhitleyOpenBoardPkg/Include/UbaKti.h new file mode 100644 index 0000000000..c7802d6451 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h @@ -0,0 +1,29 @@ +/** @file + UBA KTI header file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#ifndef _UBA_KTI_H_ +#define _UBA_KTI_H_ + +#define PLATFORM_KTIEP_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'K', 'T', 'I') +#define PLATFORM_KTIEP_UPDATE_VERSION 01 + +typedef struct _PLATFORM_KTI_EPARAM_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + ALL_LANES_EPARAM_LINK_INFO *AllLanesEparamTablePtr; + UINT32 SizeOfAllLanesEparamTable; + PER_LANE_EPARAM_LINK_INFO *PerLaneEparamTablePtr; + UINT32 SizeOfPerLaneEparamTable; +} PLATFORM_KTI_EPARAM_UPDATE_TABLE; +#endif //_UBA_KTI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/= DxeBoardAcpiTableLib.c new file mode 100644 index 0000000000..dfa0c994dc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.c @@ -0,0 +1,37 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + MtOlympusBoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLi= b/DxeBoardAcpiTableLib.inf new file mode 100644 index 0000000000..3186c6c91e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.inf @@ -0,0 +1,44 @@ +### @file +# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxeBoardAcpiTableLib + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiTableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + PcdLib +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeMtOlympusAcpiTableLib.c + DxeBoardAcpiTableLib.c + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeMtO= lympusAcpiTableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpi= Lib/DxeMtOlympusAcpiTableLib.c new file mode 100644 index 0000000000..09b917083c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeMtOlympusA= cpiTableLib.c @@ -0,0 +1,54 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM *mGlobalNvsArea; + +VOID +MtOlympusUpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + +} + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) { + MtOlympusUpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoa= rdAcpiEnableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..09a6b00877 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.c @@ -0,0 +1,51 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoa= rdAcpiEnableLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiL= ib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..fcbc94cc50 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.inf @@ -0,0 +1,48 @@ +### @file +# Platform Hook Library instance +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmBoardAcpiEnableLib + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + UefiBootServicesTableLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + +[Protocols] + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmSil= iconAcpiEnableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiL= ib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..2b8a35c7e8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmSiliconAcp= iEnableLib.c @@ -0,0 +1,138 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 SmiEn; + UINT16 Pm1En; + UINT16 Pm1Cnt; + UINT16 PchPmBase; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Init Power Management I/O Base aka ACPI Base + // + PchPmBase =3D DynamicSiLibraryProtocol->PmcGetAcpiBase (); + + SmiEn =3D IoRead32 (PchPmBase + R_ACPI_IO_SMI_EN); + + // + // Disable SW SMI Timer and legacy USB + // + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB | = B_ACPI_IO_SMI_EN_LEGACY_USB2); + + // + // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when SLP_TYP is = written + // + SmiEn |=3D B_ACPI_IO_SMI_EN_ON_SLP_EN ; + IoWrite32 (PchPmBase + R_ACPI_IO_SMI_EN, SmiEn); + + // + // Disable PM sources except power button + // + Pm1En =3D B_ACPI_IO_PM1_EN_PWRBTN; + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_EN, Pm1En); + + // + // Enable SCI + // + Pm1Cnt =3D IoRead16 (PchPmBase + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 Pm1Cnt; + UINT16 PchPmBase; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Init Power Management I/O Base aka ACPI Base + // + PchPmBase =3D DynamicSiLibraryProtocol->PmcGetAcpiBase (); + + Pm1Cnt =3D IoRead16 (PchPmBase + R_ACPI_IO_PM1_CNT); + + // + // Disable SCI + // + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN; + + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Board= InitDxeLib.c new file mode 100644 index 0000000000..d31c9292a6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.c @@ -0,0 +1,299 @@ +/** @file +Library for Board Init. + +@copyright +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +IIO_UDS *mIioUds; + +/** + Connects Root Bridge +**/ +VOID +ConnectRootBridge ( + BOOLEAN Recursive + ); + + +VOID +ProgramDPRregs ( + VOID +); + +/** + A hook for board-specific initialization after PCI enumeration. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterPciEnumeration ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ReadyToBoot event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitReadyToBoot ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ExitBootServices event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitEndOfFirmware ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + This function will retrieve the DPR data from HOBs produced by MRC + and will use it to program the DPR registers in IIO and in PCH + + @param VOID + @retval VOID + +**/ +VOID +ProgramDprRegs ( + VOID + ) +{ + return; +} + +/** + Function to set the WPE bit of the BIOS Info Flags MSR to enable Anti-Fl= ash wearout + protection within BIOS Guard before booting to the OS + + @param[in] EFI_EVENT Event + @param[in] VOID *Context + + @retval None + +**/ +VOID +EFIAPI +EnableAntiFlashWearout ( + EFI_EVENT Event, + VOID *Context + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices =3D NULL; + SYSTEM_CONFIGURATION SetupData; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + CopyMem (&SetupData, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CONFIGURATION)); + + // + // First check if Anti-flash wearout feature is supported by platform an= d Setup variable is enabled + // + if (SetupData.AntiFlashWearoutSupported =3D=3D TRUE && SetupData.EnableA= ntiFlashWearout) { + Status =3D gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **) &MpServices + ); + ASSERT_EFI_ERROR(Status); + + // + // Set WPE on BSP, then all other APs + // + DynamicSiLibraryProtocol->SetBiosInfoFlagWpe(); + + MpServices->StartupAllAPs ( + MpServices, + (EFI_AP_PROCEDURE) DynamicSiLibraryProtocol->SetBiosIn= foFlagWpe, + FALSE, + NULL, + 0, + NULL, + NULL + ); + } +} + +/** + Before console after trusted console event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Even= t. +**/ +VOID +BdsBoardBeforeConsoleAfterTrustedConsoleCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *Interface; + + DEBUG ((DEBUG_INFO, "Board gBdsEventBeforeConsoleBeforeEndOfDxeGuid call= back starts\n")); + // + // make sure root bridge is already connected before EndOfDxe. + // Try to locate gEfiPciEnumerationCompleteProtocolGuid to see if PciBus= scan already executed. + // + Status =3D gBS->LocateProtocol ( + &gEfiPciEnumerationCompleteProtocolGuid, + NULL, + &Interface + ); + if (EFI_ERROR (Status)) { + ConnectRootBridge (FALSE); + } +} + +EFI_STATUS +EFIAPI +BoardNotificationInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + UINT32 BspCpuidSignature; + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *UdsHobPtr; + EFI_BOOT_MODE BootMode; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GU= ID; + EFI_EVENT BeforeConsoleAfterTrustedConsoleEvent; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG((DEBUG_INFO, "PlatformEarlyDxeEntry \n")); + + // + // Get the IIO_UDS data HOB + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT(GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + UdsHobPtr =3D GET_GUID_HOB_DATA(GuidHob); + // + // Allocate Memory Pool buffer for IIO_UDS data + // + Status =3D gBS->AllocatePool ( EfiBootServicesData, sizeof (IIO_UDS), (V= OID **) &mIioUds ); + ASSERT_EFI_ERROR (Status); + // + // Initialize the Memory Pool buffer with the data from the Hand-Off-Blo= ck + // + CopyMem(mIioUds, UdsHobPtr, sizeof(IIO_UDS)); + + // + // Get the boot mode that we are currently in + // + BootMode =3D GetBootModeHob(); + + // + // Program DPR registers with the range from Memory Init + // + ProgramDprRegs (); + + // + // Program the GenProtRange registers for BIOS Guard + // + DynamicSiLibraryProtocol->ProgramGenProtRangeRegs (mIioUds); + + // + // Program the IMR registers for ME IMR region + // + DynamicSiLibraryProtocol->ProgramImrRegs (mIioUds); + + // + // Program the IMR2 registers for CPM & nCPM IMR region + // + DynamicSiLibraryProtocol->ProgramImr2Regs (mIioUds); + + // + // Get BSP CPU ID + // Shift out the stepping + // + AsmCpuid (0x01, &RegEax, &RegEbx, &RegEcx, &RegEdx); + BspCpuidSignature =3D (RegEax >> 4) & 0x0000FFFF; + if ( (BspCpuidSignature =3D=3D CPU_FAMILY_SKX) && (BootMode !=3D BOOT_ON= _FLASH_UPDATE)) { + // + // Register event to set WPE bit in Bios Info Flags MSR to enable Anti= Flash wearout + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + EnableAntiFlashWearout, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + } + + // + // Create BeforeConsoleAfterTrustedConsole event callback + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + BdsBoardBeforeConsoleAfterTrustedConsoleCallback, + NULL, + &gBdsEventBeforeConsoleAfterTrustedConsoleGuid, + &BeforeConsoleAfterTrustedConsoleEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Boa= rdInitDxeLib.inf new file mode 100644 index 0000000000..219512566c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.inf @@ -0,0 +1,72 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitDxeLib + FILE_GUID =3D DDD75880-C38A-4D6B-B84E-FAC1122560BF + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + CONSTRUCTOR =3D BoardNotificationInit + +[Sources] + BoardInitDxeLib.c + BoardInitDxeLib.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + IoLib + PcdLib + HobLib + UefiLib + BaseMemoryLib + HiiLib + UefiBootManagerLib + BoardBdsHookLib + +[Guids] + gEfiPlatformTxtDeviceMemoryGuid + gEfiDprRegsProgrammedGuid + gEfiSetupVariableGuid + gEfiEndOfDxeEventGroupGuid + gEfiEventExitBootServicesGuid + gImr2BaseAddressHobGuid + gBdsEventBeforeConsoleAfterTrustedConsoleGuid + +[Protocols] + gEfiMpServiceProtocolGuid + gEfiPciEnumerationCompleteProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Pcd] + gPlatformTokenSpaceGuid.PcdImr0Enable + gPlatformTokenSpaceGuid.PcdImr0Base + gPlatformTokenSpaceGuid.PcdImr0Mask + gPlatformTokenSpaceGuid.PcdImr0Rac + gPlatformTokenSpaceGuid.PcdImr0Wac + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderLoad + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderStart + gStructPcdTokenSpaceGuid.PcdSetup + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.uni b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Boa= rdInitDxeLib.uni new file mode 100644 index 0000000000..05fcfa3439 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.uni @@ -0,0 +1,29 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +//**/ + +/=3D# + +#langdef en-US "English" +#langdef fr-FR "Fran=C3=A7ais" + +#string STR_BOOT_PROMPT #language en-US "\n\n" + " Press [Enter= ] to directly boot.\n" + " Press [F2] = to enter setup and select boot options.\n" + " Press [F7] = to show boot menu options.\n\n" + " Copyright (c= ) 2006 - 2021, Intel Corporation.\n" + #language fr-FR "\n\n" + " Press [Enter= ] to directly boot.\n" + " Press [F2] = to enter setup and select boot options.\n" + " Press [F7] = to show boot menu options.\n\n" + " Copyright (c= ) 2006 - 2021, Intel Corporation.\n" +#string STR_START_BOOT_OPTION #language en-US "Start boot option" + #language fr-FR "l'option de botte= de D=C3=A9but" +#string STR_MFG_MODE_PROMPT #language en-US "\n\n\n" + " !!!Booting i= n Manufacturing Mode!!!\n" diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitPreMemLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Bo= ardInitPreMemLib.c new file mode 100644 index 0000000000..5c186ce862 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitPreM= emLib.c @@ -0,0 +1,450 @@ +/** @file + Platform Hook Library instances + +@copyright +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfigurati= on, + IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCo= reConfig, + IN SOCKET_IIO_CONFIGURATION *SocketIioConfig + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +VOID +EarlyPlatformPchInit ( + VOID + ) +{ + UINT16 Data16; + UINT8 Data8; + UINTN LpcBaseAddress; + UINT8 TcoRebootHappened; + UINTN SpiBaseAddress; + UINTN P2sbBase; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - Start\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + SpiBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + + // + // Program bar + // + P2sbBase =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + + MmioWrite32 (P2sbBase + R_P2SB_CFG_SBREG_BAR, PCH_PCR_BASE_ADDRESS); + MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + // + // LPC I/O Configuration + // + DynamicSiLibraryPpi->PchLpcIoDecodeRangesSet ( + (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) | + (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) | + (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) + ); + + DynamicSiLibraryPpi->PchLpcIoEnableDecodingSet ( + B_LPC_CFG_IOE_ME2 | + B_LPC_CFG_IOE_SE | + B_LPC_CFG_IOE_ME1 | + B_LPC_CFG_IOE_KE | + B_LPC_CFG_IOE_HGE | + B_LPC_CFG_IOE_LGE | + B_LPC_CFG_IOE_FDE | + B_LPC_CFG_IOE_PPE | + B_LPC_CFG_IOE_CBE | + B_LPC_CFG_IOE_CAE + ); + // + // Enable the upper 128-byte bank of RTC RAM + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_RTC_HOST, R_RTC_PCR_CONF, (U= INT32)~0, B_RTC_PCR_CONF_UCMOS_EN); + + // + // Disable the Watchdog timer expiration from causing a system reset + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT3= 2)~0, B_ITSS_PCR_GIC_AME); + // + // Halt the TCO timer + // + Data16 =3D IoRead16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT); + Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT; + IoWrite16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT, Data16); + + // + // Read the Second TO status bit + // + Data8 =3D IoRead8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS); + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECON= D_TO) { + TcoRebootHappened =3D 1; + DEBUG ((EFI_D_INFO, "EarlyPlatformPchInit - TCO Second TO status bit i= s set. This might be a TCO reboot\n")); + } else { + TcoRebootHappened =3D 0; + } + + // + // Clear the Second TO status bit + // + Data8 |=3D (UINT8) B_TCO_IO_TCO2_STS_SECOND_TO; + Data8 &=3D (UINT8) ~B_TCO_IO_TCO2_STS_INTRD_DET; + IoWrite8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS, Data8); + + // + // Disable SERR NMI and IOCHK# NMI in port 61 + // + Data8 =3D IoRead8 (R_PCH_IO_NMI_SC); + Data8 |=3D (B_PCH_IO_NMI_SC_PCI_SERR_EN | B_PCH_IO_NMI_SC_IOCHK_NMI_EN); + IoWrite8 (R_PCH_IO_NMI_SC, Data8); + + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT3= 2)~B_ITSS_PCR_GIC_AME, 0); + + // + // Clear EISS bit to allow for SPI use + // + MmioAnd8 (SpiBaseAddress + R_SPI_CFG_BC, (UINT8)~B_SPI_CFG_BC_EISS); + + // + // Enable LPC decode at 0xCA0 for BMC + // + DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IPMI_DEFAULT_SMM_IO_BASE & 0x= FF0), 0x10); + DEBUG ((EFI_D_INFO, "[IPMI_DEBUG]: PchLpcGenIoRangeSet 0x%x!\n", IPMI_DE= FAULT_SMM_IO_BASE)); + + DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - End\n")); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + SYSTEM_CONFIGURATION SysSetupData; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreSetupData; + SOCKET_IIO_CONFIGURATION SocketIioSetupData; + PCH_SETUP PchSetupData; + UINT16 ABase; + UINT16 Pm1Sts =3D 0; + UINT32 Pm1Cnt; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Get Setup Data + // + + ZeroMem (&SysSetupData, sizeof(SYSTEM_CONFIGURATION)); + ZeroMem (&SocketProcessorCoreSetupData, sizeof(SOCKET_PROCESSORCORE_CONF= IGURATION)); + ZeroMem (&SocketIioSetupData, sizeof(SOCKET_IIO_CONFIGURATION)); + ZeroMem (&PchSetupData, sizeof(PCH_SETUP)); + + CopyMem (&PchSetupData, PcdGetPtr(PcdPchSetup), sizeof(PCH_SETUP)); + CopyMem (&SysSetupData, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CONFIGURATION= )); + CopyMem (&SocketProcessorCoreSetupData, PcdGetPtr(PcdSocketProcessorCore= Config), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION)); + CopyMem (&SocketIioSetupData, PcdGetPtr(PcdSocketIioConfig), sizeof(SOCK= ET_IIO_CONFIGURATION)); + // + // Configure GPIO + // + Status =3D BoardInit (); + + EarlyPlatformPchInit (); + + /// + /// Set what state (S0/S5) to go to when power is re-applied after a pow= er failure (G3 state) + /// + DynamicSiLibraryPpi->PmcSetPlatformStateAfterPowerFailure (PchSetupData.= StateAfterG3); + + // + // Check PWR FLR + // + if (DynamicSiLibraryPpi->PmcIsPowerFailureDetected ()) { + DynamicSiLibraryPpi->PmcClearPowerFailureStatus (); + } + ///---------------------------------------------------------------------= ------------- + /// + /// Clear PWR_BTN_STS if set. BIOS should check the WAK_STS bit in PM1_S= TS[15] (PCH register ABASE+00h) before memory + /// initialization to determine if ME has reset the system while the Hos= t was in a sleep state. + /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is t= aken by overwriting + /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit. + /// + ABase =3D DynamicSiLibraryPpi->PmcGetAcpiBase (); + + Pm1Sts =3D IoRead16 (ABase + R_ACPI_IO_PM1_STS); + if ((Pm1Sts & B_ACPI_IO_PM1_STS_PWRBTN) =3D=3D B_ACPI_IO_PM1_STS_PWRBTN)= { + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN); + } + + if ((Pm1Sts & B_ACPI_IO_PM1_STS_WAK) =3D=3D 0) { + Pm1Cnt =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D V_ACPI_IO_PM1_CNT_S5; + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + // + // Update Platform Info + // + UpdatePlatformInfo (&SysSetupData,&SocketProcessorCoreSetupData,&SocketI= ioSetupData); + + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT16 Pm1Cnt; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Check if user wants to turn off in PEI phase + // + if (BootMode !=3D BOOT_ON_S3_RESUME) { + DynamicSiLibraryPpi->CheckPowerOffNow (); + } else { + Pm1Cnt =3D IoRead16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT); + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SLP_TYP; + IoWrite16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + + Initialize POC register by Variable. + + @param *SystemConfiguration - Pointer to SystemConfiguration variables. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfigurati= on, + IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCo= reConfig, + IN SOCKET_IIO_CONFIGURATION *SocketIioConfig + ) +{ + EFI_PLATFORM_INFO *PlatformInfo; + EFI_HOB_GUID_TYPE *GuidHob; + // + // Update the PCIE base and 32/64bit PCI resource support + // + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + PlatformInfo->SysData.SysIoApicEnable =3D PCH_IOAPIC; +#if MAX_SOCKET <=3D 4 + if (SocketIioConfig->DevPresIoApicIio[0]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC00_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[1]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC01_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[2]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC02_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[3]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC03_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[4]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC04_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[5]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC05_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[6]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC06_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[7]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC07_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[8]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC08_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[9]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC09_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[10]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC10_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[11]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC11_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[12]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC12_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[13]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC13_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[14]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC14_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[15]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC15_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[16]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC16_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[17]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC17_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[18]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC18_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[19]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC19_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[20]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC20_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[21]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC21_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[22]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC22_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[23]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC23_IOAPIC); + } +#else + // Enable all 32 IOxAPIC + PlatformInfo->SysData.SysIoApicEnable =3D 0xFFFFFFFF; +#endif + // + // Check to make sure TsegSize is in range, if not use default. + // + if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) { + SocketProcessorCoreConfig->TsegSize =3D MAX_PROCESSOR_TSEG; // if out = of range make default 64M + } + PlatformInfo->MemData.MemTsegSize =3D (0x400000 << SocketProcessorCoreC= onfig->TsegSize); + PlatformInfo->MemData.MemIedSize =3D PcdGet32 (PcdCpuIEDRamSize); + + // + // Minimum SMM range in TSEG should be larger than 3M + // + ASSERT (PlatformInfo->MemData.MemTsegSize - PlatformInfo->MemData.MemIed= Size >=3D 0x300000); + + return EFI_SUCCESS; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitPreMemLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/= BoardInitPreMemLib.inf new file mode 100644 index 0000000000..3e1f966f32 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitPreM= emLib.inf @@ -0,0 +1,66 @@ +## @file +# Component information file for PEI Board Init Pre-Mem Library +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitPreMemLib + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + PeiServicesLib + PeimEntryPoint + PciLib + PeiServicesTablePointerLib + PciExpressLib + BaseCryptLib + CmosAccessLib + PeiPlatformHookLib + ReportStatusCodeLib + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + HobLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + BoardInitPreMemLib.c + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gEfiPlatformInfoGuid + +[Pcd] + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdPchSetup + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupport.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatS= upportLib/MultiPlatSupport.h new file mode 100644 index 0000000000..76cea4cb38 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupport.h @@ -0,0 +1,48 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MULTI_PLATFORM_SUPPORT_H_ +#define _MULTI_PLATFORM_SUPPORT_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gDefaultDataFileGuid; +extern EFI_GUID gEfiVariableGuid; +extern EFI_GUID gEfiAuthenticatedVariableGuid; + +typedef struct { + UINT16 DefaultId; + UINT8 BoardId; +} DEFAULT_INFO; + +typedef struct { + // + // HeaderSize includes HeaderSize fields and DefaultInfo arrays + // + UINT16 HeaderSize; + // + // DefaultInfo arrays those have the same default setting. + // + DEFAULT_INFO DefaultInfo[1]; + // + // Default data is stored as variable storage. + // VARIABLE_STORE_HEADER VarStorageHeader; + // +} DEFAULT_DATA; + + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupportLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPl= atSupportLib/MultiPlatSupportLib.c new file mode 100644 index 0000000000..9f0af4b3e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupportLib.c @@ -0,0 +1,255 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +//notes +//1: security variable and non-security variable may have different implem= entation +//2. BP core variable sync may need update this module +//3 different generation need to sync base on RP variable and Generation v= ariable +// this library to use a lightweight get variable service to patch variabl= e hob before PEI variable service is ready + + + + + + +/** + Gets a vairable store header from FFS inserted by FCE + + Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + + + @return The start address of VARIABLE_STORE_HEADER *. Null if cannot fin= d it + +**/ + +VOID * FindDefaultHobinFfs ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ) +{ + EFI_PEI_SERVICES **PeiServices; + UINTN FvInstance; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_FFS_FILE_HEADER *FfsHeader; + UINT32 FileSize; + EFI_COMMON_SECTION_HEADER *Section; + UINT32 SectionLength; + BOOLEAN DefaultFileIsFound; + DEFAULT_DATA *DefaultData; + DEFAULT_INFO *DefaultInfo; + VARIABLE_STORE_HEADER *VarStoreHeader; + UINT32 FFSSize =3D 0; + + + + // + // Get PeiService pointer + // + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + + // + // Find the FFS file that stores all default data. + // + DefaultFileIsFound =3D FALSE; + FvInstance =3D 0; + FfsHeader =3D NULL; + while (((*PeiServices)->FfsFindNextVolume (PeiServices, FvInstance, &FvH= eader) =3D=3D EFI_SUCCESS) && + (!DefaultFileIsFound)) { + FfsHeader =3D NULL; + while ((*PeiServices)->FfsFindNextFile (PeiServices, EFI_FV_FILETYPE_F= REEFORM, FvHeader, &FfsHeader) =3D=3D EFI_SUCCESS) { + if (CompareGuid ((EFI_GUID *) FfsHeader, &gDefaultDataFileGuid)) { + DefaultFileIsFound =3D TRUE; + break; + } + } + FvInstance ++; + } + + // + // FFS file is not found. + // + if (!DefaultFileIsFound) { + + if(PcdGet32(PcdFailSafeVarFfsSize)!=3D0 ){ + //try to search other FVS + FfsHeader =3D (EFI_FFS_FILE_HEADER *) AllocatePool(PcdGet32(PcdFailS= afeVarFfsSize) ); + if(FfsHeader =3D=3D NULL) { + return NULL; + } + if(EFI_SUCCESS !=3D ReadFFSFile( (EFI_FIRMWARE_VOLUME_HEADER *) PcdG= et32(PcdFailSafeVarFvBase), gDefaultDataFileGuid, 0, FfsHeader, &FFSSize, F= ALSE)) { + return NULL; + } + ASSERT(PcdGet32(PcdFailSafeVarFfsSize) Size) & 0x00FFFFFF; + while (((UINTN) Section < (UINTN) FfsHeader + FileSize) && (VarStoreHead= er =3D=3D NULL)) { + DefaultData =3D (DEFAULT_DATA *) (Section + 1); + DefaultInfo =3D &(DefaultData->DefaultInfo[0]); + while ((UINTN) DefaultInfo < (UINTN) DefaultData + DefaultData->Header= Size) { + if (DefaultInfo->DefaultId =3D=3D DefaultId && DefaultInfo->BoardId = =3D=3D BoardId) { + VarStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINT8 *) DefaultDat= a + DefaultData->HeaderSize); + break; + } + DefaultInfo ++; + } + // + // Size is 24 bits wide so mask upper 8 bits. + // SectionLength is adjusted it is 4 byte aligned. + // Go to the next section + // + SectionLength =3D *(UINT32 *)Section->Size & 0x00FFFFFF; + SectionLength =3D (SectionLength + 3) & (~3); + ASSERT (SectionLength !=3D 0); + Section =3D (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLe= ngth); + } + + return VarStoreHeader; + +} + + +/** + This function searches the first instance of a HOB from the starting HOB= pointer. + Such HOB should satisfy two conditions: + its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to = the input Guid. + If there does not exist such HOB from the starting HOB pointer, it will = return NULL. + Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_S= IZE () + to extract the data section and its size info respectively. + In contrast with macro GET_NEXT_HOB(), this function does not skip the s= tarting HOB pointer + unconditionally: it returns HobStart back if HobStart itself meets the r= equirement; + caller is required to use GET_NEXT_HOB() if it wishes to skip current Ho= bStart. + If Guid is NULL, then ASSERT(). + If HobStart is NULL, then ASSERT(). + + @param Guid The GUID to match with in the HOB list. + @param HobStart A pointer to a Guid. + + @return The next instance of the matched GUID HOB from the starting HOB. + +**/ +VOID * +InternalGetNextGuidHob ( + IN CONST EFI_GUID *Guid, + IN CONST VOID *HobStart + ) +{ + EFI_PEI_HOB_POINTERS GuidHob; + + GuidHob.Raw =3D (UINT8 *) HobStart; + while (!END_OF_HOB_LIST (GuidHob)) { + if (GuidHob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION && Comp= areGuid (Guid, &GuidHob.Guid->Name)) { + break; + } + GuidHob.Raw =3D GET_NEXT_HOB (GuidHob); + } + return GuidHob.Raw; +} + +EFI_STATUS +CreateDefaultVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ) +/*++ +Description: + + This function finds the matched default data and create GUID hob for it. + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ +{ + VARIABLE_STORE_HEADER *VarStoreHeader; + VARIABLE_STORE_HEADER *VarStoreHeaderHob; + UINT8 *VarHobPtr; + UINT8 *VarPtr; + UINT32 VarDataOffset; + UINT32 VarHobDataOffset; + EFI_PEI_SERVICES **PeiServices; + + // + // Get PeiService pointer + // + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + + VarStoreHeader =3D (VARIABLE_STORE_HEADER*)FindDefaultHobinFfs( DefaultI= d, BoardId); + + // + // Matched default data is not found. + // + if (VarStoreHeader =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + // + // Create HOB to store defautl data so that Variable driver can use it. + // Allocate more data for header alignment. + // + VarStoreHeaderHob =3D (VARIABLE_STORE_HEADER *) BuildGuidHob (&VarStoreH= eader->Signature, VarStoreHeader->Size + HEADER_ALIGNMENT - 1); + if (VarStoreHeaderHob =3D=3D NULL) { + // + // No enough hob resource. + // + return EFI_OUT_OF_RESOURCES; + } + + // + // Copy variable storage header. + // + CopyMem (VarStoreHeaderHob, VarStoreHeader, sizeof (VARIABLE_STORE_HEADE= R)); + // + // Copy variable data. + // + VarPtr =3D (UINT8 *) HEADER_ALIGN ((UINTN) (VarStoreHeader + 1= )); + VarDataOffset =3D (UINT32) ((UINTN) VarPtr - (UINTN) VarStoreHeader); + VarHobPtr =3D (UINT8 *) HEADER_ALIGN ((UINTN) (VarStoreHeaderHob = + 1)); + VarHobDataOffset =3D (UINT32) ((UINTN) VarHobPtr - (UINTN) VarStoreHeade= rHob); + CopyMem (VarHobPtr, VarPtr, VarStoreHeader->Size - VarDataOffset); + // + // Update variable size. + // + VarStoreHeaderHob->Size =3D VarStoreHeader->Size - VarDataOffset + VarHo= bDataOffset; + + // SyncSetupVariable(PeiServices,VarStoreHeaderHob,FALSE); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupportLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Multi= PlatSupportLib/MultiPlatSupportLib.inf new file mode 100644 index 0000000000..ea8d853314 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupportLib.inf @@ -0,0 +1,49 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +#--*/ +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D MultiPlatSupportLib + FILE_GUID =3D EA5EEAF9-2EB4-4fbf-BB28-5B3A605B8665 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MultiPlatSupportLib|PEIM PEI_CORE + +[Sources] + MultiPlatSupportLib.c + + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PeiServicesTablePointerLib + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + IoLib + PciLib + PcdLib + ReadFfsLib + MemoryAllocationLib + +[Guids] + gDefaultDataFileGuid ## CONSUMES ## File + +[Pcd] + gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize + gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPro= cessLib/FspWrapperHobProcessLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Libr= ary/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c new file mode 100644 index 0000000000..19dc82d7a7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib= /FspWrapperHobProcessLib.c @@ -0,0 +1,722 @@ +/** @file + Provide FSP wrapper hob process related function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Additional pages are used by DXE memory manager. +// It should be consistent between RetrieveRequiredMemorySize() and GetPei= MemSize() +// +#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE) + +EFI_GUID mCpuVarDataHobGuid =3D {0x71dd88db, 0x1722, 0x48af, {0x96, 0x5b, = 0x5e, 0x15, 0xaf, 0xfe, 0x86, 0x56}}; +/** + Get the mem size in memory type infromation table. + + @param[in] PeiServices PEI Services table. + + @return the mem size in memory type infromation table. +**/ +UINT64 +GetMemorySizeInMemoryTypeInformation ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + EFI_MEMORY_TYPE_INFORMATION *MemoryData; + UINT8 Index; + UINTN TempPageNum; + + MemoryData =3D NULL; + Status =3D (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES**)Pei= Services, (VOID **) &Hob.Raw); + ASSERT_EFI_ERROR (Status); + + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION && + CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) { + MemoryData =3D (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EF= I_HOB_GENERIC_HEADER) + sizeof (EFI_GUID)); + break; + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + if (MemoryData =3D=3D NULL) { + return 0; + } + + TempPageNum =3D 0; + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= { + // + // Accumulate default memory size requirements + // + TempPageNum +=3D MemoryData[Index].NumberOfPages; + } + + return TempPageNum * EFI_PAGE_SIZE; +} + +/** + Get the mem size need to be reserved in PEI phase. + + @param[in] PeiServices PEI Services table. + + @return the mem size need to be reserved in PEI phase. +**/ +UINT64 +RetrieveRequiredMemorySize ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + UINT64 Size; + + Size =3D GetMemorySizeInMemoryTypeInformation (PeiServices); + return Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +/** + Get the mem size need to be consumed and reserved in PEI phase. + + @param[in] PeiServices PEI Services table. + @param[in] BootMode Current boot mode. + + @return the mem size need to be consumed and reserved in PEI phase. +**/ +UINT64 +GetPeiMemSize ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 BootMode + ) +{ + UINT64 Size; + UINT64 MinSize; + + if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + return PcdGet32 (PcdPeiRecoveryMinMemSize); + } + + Size =3D GetMemorySizeInMemoryTypeInformation (PeiServices); + + MinSize =3D PcdGet32 (PcdPeiMinMemSize); + + return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +VOID +TransferHobData ( + VOID *HobStart, + EFI_GUID *InfoGuid, + UINT8 *Info + ) +{ + VOID *GuidHob; + VOID *Data; + UINTN DataSize; + VOID *Hob; + + GuidHob =3D GetNextGuidHob (InfoGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find %a\n", Info)); + return; + } + + Data =3D GET_GUID_HOB_DATA (GuidHob); + DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + Hob =3D BuildGuidDataHob ( + InfoGuid, + Data, + DataSize + ); + DEBUG ((DEBUG_INFO, "Create %a Hob at %x\n", Info, Hob)); +} + +VOID +CopyHobData ( + VOID *HobStart, + EFI_GUID *InfoGuid, + UINT8 *Info + ) +{ + VOID *GuidHob; + VOID *Data; + VOID *OrgGuidHob; + VOID *OrgData; + UINTN DataSize; + UINTN OrgDataSize; + + GuidHob =3D GetNextGuidHob (InfoGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find %a\n", Info)); + return; + } + + Data =3D GET_GUID_HOB_DATA (GuidHob); + DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + + OrgGuidHob =3D GetFirstGuidHob (InfoGuid); + if (OrgGuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Copy Hob Can't Find org %a\n", Info)); + } + + OrgData =3D GET_GUID_HOB_DATA (OrgGuidHob); + OrgDataSize =3D GET_GUID_HOB_DATA_SIZE (OrgGuidHob); + if (OrgDataSize !=3D DataSize) { + DEBUG ((EFI_D_ERROR, "%a Hob Size Don't Match Between FSP and BootLoad= er. FSP:%x vs BootLoader:%x\n", OrgDataSize, DataSize)); + ASSERT (FALSE); + } + CopyMem (OrgData, Data, DataSize); + + DEBUG ((EFI_D_ERROR, "CopyHobData %a Hob from %x to %x, Size: %x\n", Inf= o, Data, OrgData, DataSize)); +} + + +VOID +TransferPcd ( + VOID * HobStart + ) +{ + VOID *GuidHob; + EFI_PHYSICAL_ADDRESS *HobBuffer; + + GuidHob =3D GetNextGuidHob (&gSaveHostToMemoryGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find gSaveHostToMemoryGuid\n"= )); + return; + } + + HobBuffer =3D (EFI_PHYSICAL_ADDRESS*) GET_GUID_HOB_DATA (GuidHob); + PcdSet64S (PcdSyshostMemoryAddress, (UINTN) HobBuffer[0]); + PcdSet64S (PcdMemMapHostMemoryAddress, (UINTN) HobBuffer[1]); + DEBUG ((DEBUG_INFO, "TransferPcd Set PcdSyshostMemoryAddress %x\n", (UIN= TN) HobBuffer[0])); + DEBUG ((DEBUG_INFO, "TransferPcd Set PcdMemMapHostMemoryAddress %x\n", (= UINTN) HobBuffer[1])); +} + + +/** + Post FSP-M HOB process for Memory Resource Descriptor. + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + + @return If platform process the FSP hob list successfully. +**/ +EFI_STATUS +EFIAPI +PostFspmHobProcess ( + IN VOID *FspHobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 PeiMemSize; + EFI_PHYSICAL_ADDRESS PeiMemBase; + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_PEI_CAPSULE_PPI *Capsule; + VOID *CapsuleBuffer; + UINTN CapsuleBufferLength; + UINT64 RequiredMemSize; + UINT64 ResourceLength; + EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D (EFI_PEI_SERVICES **) GetPeiServicesTablePointer (); + + PeiServicesGetBootMode (&BootMode); + + PeiMemBase =3D 0; + PeiMemSize =3D 0; + RequiredMemSize =3D 0; + ResourceLength =3D 0; + + // + // Parse the hob list from fsp + // Report all the resource hob except MMIO and IO resource Hob's + // + if (BootMode !=3D BOOT_ON_S3_RESUME) { + PeiMemSize =3D GetPeiMemSize (PeiServices, BootMode); + RequiredMemSize =3D RetrieveRequiredMemorySize (PeiServices); + Hob.Raw =3D (UINT8*)(UINTN) FspHobList; + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); + + // + // Find the largest available system Memory and use it for PeiMemory + // + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.= Raw)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength <=3D BASE_4GB) + && (Hob.ResourceDescriptor->PhysicalStart >=3D PeiMemBase) + && (Hob.ResourceDescriptor->ResourceLength >=3D PeiMemSize)) { + PeiMemBase =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Reso= urceDescriptor->ResourceLength - PeiMemSize; + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + } + + CopyHobData (FspHobList, &gSystemInfoVarHobGuid, (UINT8*) "gSystemInfoVa= rHobGuid"); + CopyHobData (FspHobList, &gIioSiPolicyHobGuid, (UINT8*) "gIioSiPolicyHob= Guid"); + TransferPcd (FspHobList); + + Hob.Raw =3D (UINT8 *)(UINTN) FspHobList; + + // + // Skip the MMIO and IO reource map from the FSP Hob list + // + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Ra= w)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_IO) || (= Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMORY_MAPPED_IO))= { + Hob.Raw =3D GET_NEXT_HOB (Hob); + continue; + } + ResourceLength =3D Hob.ResourceDescriptor->ResourceLength; + DEBUG ((DEBUG_INFO, "Resource start %lx resource length %lx resource t= ype %d\n", Hob.ResourceDescriptor->PhysicalStart, Hob.ResourceDescriptor->R= esourceLength, Hob.ResourceDescriptor->ResourceType)); + if (BootMode !=3D BOOT_ON_S3_RESUME) { + // + // If the system memory found in FSP Hob is determined for PeiMemory= . Split the Resource descriptor Hob + // + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart <=3D PeiMemBase) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength >=3D PeiMemBase + PeiMemSize) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength <=3D BASE_4GB)) { + if ((CompareGuid (&Hob.ResourceDescriptor->Owner, &gZeroGuid))) { + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + PeiMemBase, + PeiMemSize + ); + } else { + BuildResourceDescriptorWithOwnerHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + PeiMemBase, + PeiMemSize, + &Hob.ResourceDescriptor->Owner + ); + } + ResourceLength =3D (Hob.ResourceDescriptor->ResourceLength) - (Pei= MemSize); + } + } + + // + // Report the resource hob + // + if ((CompareGuid (&Hob.ResourceDescriptor->Owner, &gZeroGuid))) { + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + ResourceLength + ); + } else { + BuildResourceDescriptorWithOwnerHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + ResourceLength, + &Hob.ResourceDescriptor->Owner + ); + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // @todo: It is a W/A for SetMemorySpaceAttribute issue in PchSpi and Pc= hReset drivers. + // We need to modify it instead of hard code here. Due to Install= EfiMemory is using hard code to + // describe memory resource, we have to hard code in here. Once I= nstallEfiMemory is merged, we should + // be able to remove this. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFFA00000, + 0x80000 + ); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFE000000, + 0x10000 + ); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFE010000, + 0x1000 + ); + + // + // Capsule mode + // + Capsule =3D NULL; + CapsuleBuffer =3D NULL; + CapsuleBufferLength =3D 0; + if (BootMode =3D=3D BOOT_ON_FLASH_UPDATE) { + Status =3D PeiServicesLocatePpi ( + &gEfiPeiCapsulePpiGuid, + 0, + NULL, + (VOID **) &Capsule + ); + ASSERT_EFI_ERROR (Status); + + if (Status =3D=3D EFI_SUCCESS) { + Status =3D PeiServicesGetHobList ((void**)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = Hob.Raw)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDes= criptor->ResourceLength <=3D BASE_4GB) + && (Hob.ResourceDescriptor->PhysicalStart >=3D BASE_1MB) + && (Hob.ResourceDescriptor->PhysicalStart !=3D PeiMemBase) + && (Hob.ResourceDescriptor->ResourceLength >=3D CapsuleBuff= erLength)) { + CapsuleBufferLength =3D (UINTN)Hob.ResourceDescriptor->Resour= ceLength; + CapsuleBuffer =3D (VOID*)(UINTN)Hob.ResourceDescriptor->Physi= calStart; + + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // Call the Capsule PPI Coalesce function to coalesce the capsule = data. + // + Status =3D Capsule->Coalesce (PeiServices, &CapsuleBuffer, &Capsul= eBufferLength); + } + } + + DEBUG ((DEBUG_INFO, "FSP wrapper PeiMemBase : 0x%08x\n", PeiMemBa= se)); + DEBUG ((DEBUG_INFO, "FSP wrapper PeiMemSize : 0x%08x\n", PeiMemSi= ze)); + DEBUG ((DEBUG_INFO, "FSP wrapper RequiredMemSize : 0x%08x\n", Required= MemSize)); + + // + // Install efi memory + // + Status =3D PeiServicesInstallPeiMemory ( + PeiMemBase, + PeiMemSize - RequiredMemSize + ); + ASSERT_EFI_ERROR (Status); + + if (Capsule !=3D NULL) { + Status =3D Capsule->CreateState ((EFI_PEI_SERVICES **) PeiServices, = CapsuleBuffer, CapsuleBufferLength); + } + + + // + // Create a memory allocation HOB at fixed location for MP Services PPI = AP wait loop. + // Report memory region used by FSP. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdFspCpuPeiApWakeupBufferAddr), + EFI_PAGE_SIZE, + EfiBootServicesData + ); + + return EFI_SUCCESS; +} + +/** + Process FSP HOB list + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + +**/ +VOID +ProcessFspHobList ( + IN VOID *FspHobList + ) +{ + UINT8 PhysicalAddressBits; + UINT32 RegEax; + EFI_PEI_HOB_POINTERS FspHob; + + FspHob.Raw =3D FspHobList; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8) RegEax; + } else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob (PhysicalAddressBits, 16); + + // + // Add all the HOBs from FSP binary to FSP wrapper + // + while (!END_OF_HOB_LIST (FspHob)) { + if (FspHob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + // + // Skip FSP binary creates PcdDataBaseHobGuid + // + if (!CompareGuid(&FspHob.Guid->Name, &gPcdDataBaseHobGuid)) { + BuildGuidDataHob ( + &FspHob.Guid->Name, + GET_GUID_HOB_DATA (FspHob), + GET_GUID_HOB_DATA_SIZE (FspHob) + ); + } + } + FspHob.Raw =3D GET_NEXT_HOB (FspHob); + } +} + +VOID +CheckFspGraphicsDeviceInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_INFO_HOB *FspGraphicsInfo =3D NULL; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *FspGraphicsDeviceInfo =3D NULL; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GraphicsDeviceInfo; + + Status =3D PeiServicesGetHobList ((VOID**) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsInfoHobGuid, Hob.Raw))= !=3D NULL) { + FspGraphicsInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + } + if (FspGraphicsInfo =3D=3D NULL) { + return ; + } + + Status =3D PeiServicesGetHobList ((VOID**) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsDeviceInfoHobGuid, Hob= .Raw)) !=3D NULL) { + FspGraphicsDeviceInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + } + if (FspGraphicsDeviceInfo !=3D NULL) { + return ; + } + + // + // FSP only publish FspGraphicsInfo, but no FspGraphicsDeviceInfo. + // + // Workaround: Need publish FspGraphicsDeviceInfo, because Intel Graphic= s BarIndex is 1. + // + GraphicsDeviceInfo.VendorId =3D MAX_UINT16; + GraphicsDeviceInfo.DeviceId =3D MAX_UINT16; + GraphicsDeviceInfo.SubsystemVendorId =3D MAX_UINT16; + GraphicsDeviceInfo.SubsystemId =3D MAX_UINT16; + GraphicsDeviceInfo.RevisionId =3D MAX_UINT8; + GraphicsDeviceInfo.BarIndex =3D 1; + BuildGuidDataHob ( + &gEfiGraphicsDeviceInfoHobGuid, + &GraphicsDeviceInfo, + sizeof(GraphicsDeviceInfo) + ); + + return ; +} + +/** + Dump FSP HOB list + +**/ +VOID +DumpFspHobList ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + DEBUG ((DEBUG_INFO, "FSP Extended GUID HOB: {%g}\n", &(Hob.Guid->= Name))); + } + if ((Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) && + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMORY_RE= SERVED)) { + DEBUG ((DEBUG_INFO, "FSP Reserved Resource HOB: %016lX ~ %016lX\n", \ + Hob.ResourceDescriptor->PhysicalStart, Hob.ResourceDescripto= r->PhysicalStart \ + + Hob.ResourceDescriptor->ResourceLength)); + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } +} + +/** + Dump FSP memory resource + +**/ +VOID +DumpFspMemoryResource ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "\nFSP Memory Resource\n")); + DEBUG ((DEBUG_INFO, " Resource Range Type Attribute= Owner\n")); + DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"= )); + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Ra= w)) !=3D NULL) { + if (!CompareGuid (&(Hob.ResourceDescriptor->Owner), &gZeroGuid)) { + DEBUG ((DEBUG_INFO, "%016lx-%016lx %4x %016x %g\n", + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescript= or->ResourceLength, + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + &(Hob.ResourceDescriptor->Owner) + )); + } else { + DEBUG ((DEBUG_INFO, "%016lx-%016lx %4x %016x \n", + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescript= or->ResourceLength, + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute + )); + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Dump FSP memory resource + +**/ +VOID +DumpFspGraphicsInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_INFO_HOB *FspGraphicsInfo =3D NULL; + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsInfoHobGuid, Hob.Raw))= !=3D NULL) { + FspGraphicsInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + if (FspGraphicsInfo !=3D NULL) { + DEBUG((DEBUG_INFO, "\nGraphicsInfo\n")); + DEBUG((DEBUG_INFO, " |-> FrameBufferBase : 0x%016lx\n", FspGraphics= Info->FrameBufferBase)); + DEBUG((DEBUG_INFO, " |-> FrameBufferSize : 0x%016lx\n", FspGraphics= Info->FrameBufferSize)); + DEBUG((DEBUG_INFO, " |-> GraphicsMode\n")); + DEBUG((DEBUG_INFO, " |-> Version : 0x%08x\n", FspGra= phicsInfo->GraphicsMode.Version)); + DEBUG((DEBUG_INFO, " |-> HorizontalResolution : %d\n", FspGraphic= sInfo->GraphicsMode.HorizontalResolution)); + DEBUG((DEBUG_INFO, " |-> VerticalResolution : %d\n", FspGraphic= sInfo->GraphicsMode.VerticalResolution)); + DEBUG((DEBUG_INFO, " |-> PixelFormat : %d\n", FspGraphic= sInfo->GraphicsMode.PixelFormat)); + DEBUG((DEBUG_INFO, " |-> PixelInformation : %d|%d|%d|%d\n", + FspGraphicsInfo->GraphicsMode.PixelInformation.RedMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.GreenMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.BlueMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.ReservedMask + )); + DEBUG((DEBUG_INFO, " |-> PixelsPerScanLine : %d\n", FspGraphic= sInfo->GraphicsMode.PixelsPerScanLine)); + DEBUG((DEBUG_INFO, "\n")); + } else { + DEBUG((DEBUG_INFO, "\nNo GraphicsInfo\n")); + } + } +} + +VOID +DumpFspGraphicsDeviceInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *FspGraphicsDeviceInfo =3D NULL; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsDeviceInfoHobGuid, Hob= .Raw)) !=3D NULL) { + FspGraphicsDeviceInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + if (FspGraphicsDeviceInfo !=3D NULL) { + DEBUG((DEBUG_INFO, "\nGraphicsDeviceInfo\n")); + DEBUG((DEBUG_INFO, " |-> VendorId : 0x%04x\n", FspGraphics= DeviceInfo->VendorId)); + DEBUG((DEBUG_INFO, " |-> DeviceId : 0x%04x\n", FspGraphics= DeviceInfo->DeviceId)); + DEBUG((DEBUG_INFO, " |-> SubsystemVendorId : 0x%04x\n", FspGraphics= DeviceInfo->SubsystemVendorId)); + DEBUG((DEBUG_INFO, " |-> SubsystemId : 0x%04x\n", FspGraphics= DeviceInfo->SubsystemId)); + DEBUG((DEBUG_INFO, " |-> RevisionId : 0x%02x\n", FspGraphics= DeviceInfo->RevisionId)); + DEBUG((DEBUG_INFO, " |-> BarIndex : 0x%02x\n", FspGraphics= DeviceInfo->BarIndex)); + DEBUG((DEBUG_INFO, "\n")); + } else { + DEBUG((DEBUG_INFO, "\nNo GraphicsDeviceInfo\n")); + } + } +} + +EFI_PEI_PPI_DESCRIPTOR mSiliconInitializedDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEdkiiSiliconInitializedPpiGuid, + NULL +}; + +/** + Post FSP-S HOB process (not Memory Resource Descriptor). + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + + @return If platform process the FSP hob list successfully. +**/ +EFI_STATUS +EFIAPI +PostFspsHobProcess ( + IN VOID *FspHobList + ) +{ + EFI_STATUS Status; + + // + // Only in FSP API mode the wrapper has to build hobs basing on FSP outp= ut data. + // + ASSERT (FspHobList !=3D NULL); + ProcessFspHobList (FspHobList); + CheckFspGraphicsDeviceInfoHob (); + DEBUG_CODE_BEGIN (); + DumpFspGraphicsInfoHob (); + DumpFspGraphicsDeviceInfoHob (); + DumpFspHobList (); + DumpFspMemoryResource (); + DEBUG_CODE_END (); + + Status =3D PeiServicesInstallPpi (&mSiliconInitializedDesc); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPro= cessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf new file mode 100644 index 0000000000..f1dcc32147 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib= /PeiFspWrapperHobProcessLib.inf @@ -0,0 +1,99 @@ +## @file +# Provide FSP wrapper hob process related function. +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiFspWrapperHobProcessLib + FILE_GUID =3D C7B7070B-E5A8-4b86-9110-BDCA1095F496 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspWrapperHobProcessLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperHobProcessLib.c + + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + HobLib + DebugLib + FspWrapperPlatformLib + PeiServicesLib + PeiServicesTablePointerLib + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + gMinPlatformPkgTokenSpaceGuid.PcdFspCpuPeiApWakeupBufferAddr + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress + gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress + +[Guids] + gFspReservedMemoryResourceHobGuid ## CONSUMES ## H= OB + gEfiMemoryTypeInformationGuid ## CONSUMES ## G= UID + gPcdDataBaseHobGuid + gZeroGuid + gEfiGraphicsInfoHobGuid + gEfiGraphicsDeviceInfoHobGuid + gCsrPseudoOffsetTableGuid + gReferenceCodePolicyHobGuid + gSaveHostToMemoryGuid + gEfiMemoryMapGuid + gRasRcPolicyHobGuid + gRasRcConfigHobGuid + gEfiSmmPeiSmramMemoryReserveGuid + gEfiAcpiVariableGuid + gEfiCpuPolicyDataHobGuid + gSystemInfoVarHobGuid + gIioSiPolicyHobGuid + +[Ppis] + gEfiPeiCapsulePpiGuid ## CONSUMES + gEdkiiSiliconInitializedPpiGuid ## PRODUCES diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/= PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatfo= rmHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..9adbfee4a1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/PeiPlat= formHooklib.c @@ -0,0 +1,43 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +/** + Configure GPIO + + @param[in] PlatformInfo +**/ +VOID +GpioInit ( +) +{ + EFI_STATUS Status; + Status =3D PlatformInitGpios(); +} + + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + ) +{ + + GpioInit(); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/= PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlat= formHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..4b40fbd9ad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/PeiPlat= formHooklib.inf @@ -0,0 +1,34 @@ +## @file +# +# @copyright +# Copyright 1999 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D AD901798-B0DA-4b20-B90C-283F886E76D0 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[Sources] + PeiPlatformHooklib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + DebugLib + UbaGpioInitLib + +[Pcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/Pe= iReportFvLib.c new file mode 100644 index 0000000000..f0230642d2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.c @@ -0,0 +1,270 @@ +/** @file PeiReportFvLib.c + Source code file for Report Firmware Volume (FV) library + + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +ReportPreMemFv ( + VOID + ) +{ + UINTN Index =3D 0; + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; + EFI_BOOT_MODE BootMode =3D BOOT_WITH_FULL_CONFIG= URATION; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + DEBUG_CODE ( + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, &Ppi); + if (!EFI_ERROR (Status)) { + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength)); + } + } + ); + + // + // FvBspPreMemory and FvPreMemory are required for all stages. + // + + DEBUG ((DEBUG_INFO, "Install FlashFvBspPreMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvBspPreMemoryBase), PcdGet32 (PcdFlashFvBspPreMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvBspPreMem= oryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvBspPreMemoryBase), + PcdGet32 (PcdFlashFvBspPreMemorySize), + NULL, + NULL, + 0 + ); + + DEBUG ((DEBUG_INFO, "Install FlashFvPreMemory - 0x%x, 0x%x\n", PcdGet32 = (PcdFlashFvPreMemoryBase), PcdGet32 (PcdFlashFvPreMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvPreMemory= Base))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPreMemoryBase), + PcdGet32 (PcdFlashFvPreMemorySize), + NULL, + NULL, + 0 + ); + + // + // In API mode, do not publish FSP FV. + // + if (!PcdGetBool (PcdFspWrapperBootMode)) { + // + // FvFspT may be required for all stages + // + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (Pc= dFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspTBas= e))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase), + PcdGet32 (PcdFlashFvFspTSize), + NULL, + NULL, + 0 + ); + + // + // FvFspM required for stage 2 and above + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspMB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspMBase), + PcdGet32 (PcdFlashFvFspMSize), + NULL, + NULL, + 0 + ); + } + } + + // + // FvOprom may be required for most stages + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + DEBUG ((DEBUG_INFO, "Install PcdFlashFvOprom - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvOpromBase), PcdGet32 (PcdFlashFvOpromSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvOpromBa= se))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOpromBase), + PcdGet32 (PcdFlashFvOpromSize), + NULL, + NULL, + 0 + ); + } + + // + // FvAdvanced not needed until stage 6 + // + if (PcdGet8 (PcdBootStage) >=3D 6) { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvancedPreMemory - 0x%x, 0x%x\n",= PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), PcdGet32 (PcdFlashFvAdvancedPr= eMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvAdvance= dPreMemoryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), + PcdGet32 (PcdFlashFvAdvancedPreMemorySize), + NULL, + NULL, + 0 + ); + } +} + +VOID +ReportPostMemFv ( + VOID + ) +{ + UINTN Index =3D 0; + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; + + DEBUG_CODE ( + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, &Ppi); + if (!EFI_ERROR (Status)) { + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength)); + } + } + ); + + // + // FvFspS, FvPostMemory, and FvBsp may be required for completing stage 2 + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + // + // In API mode, do not publish FSP FV. + // + if (!PcdGetBool (PcdFspWrapperBootMode)) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspSB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspSBase), + PcdGet32 (PcdFlashFvFspSSize), + NULL, + NULL, + 0 + ); + } + + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvPostMem= oryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase), + PcdGet32 (PcdFlashFvPostMemorySize), + NULL, + NULL, + 0 + ); + + DEBUG ((DEBUG_INFO, "Install FlashFvBsp - 0x%x, 0x%x\n", PcdGet32 (Pcd= FlashFvBspBase), PcdGet32 (PcdFlashFvBspSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvBspBase= ))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvBspBase), + PcdGet32 (PcdFlashFvBspSize), + NULL, + NULL, + 0 + ); + } + + // + // FvUefiBoot required for completing stage 3 + // + if (PcdGet8 (PcdBootStage) >=3D 3) { + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvUefiBoo= tBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase), + PcdGet32 (PcdFlashFvUefiBootSize), + NULL, + NULL, + 0 + ); + } + + // + // FvOsBoot required for completing stage 4 + // + if (PcdGet8 (PcdBootStage) >=3D 4) { + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvOsBootB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase), + PcdGet32 (PcdFlashFvOsBootSize), + NULL, + NULL, + 0 + ); + } + + // + // FvSecurity required for completing stage 5 + // + if (PcdGet8 (PcdBootStage) >=3D 5) { + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvSecurit= yBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase), + PcdGet32 (PcdFlashFvSecuritySize), + NULL, + NULL, + 0 + ); + } + + // + // FvAdvanced required for completing stage 6 + // + if (PcdGet8 (PcdBootStage) >=3D 6) { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvAdvance= dBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase), + PcdGet32 (PcdFlashFvAdvancedSize), + NULL, + NULL, + 0 + ); + } + + // + // Report resource related HOB for flash FV to reserve space in GCD and = memory map + // + + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize) + ); + + BuildMemoryAllocationHob ( + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + EfiMemoryMappedIO + ); +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/= PeiReportFvLib.inf new file mode 100644 index 0000000000..b02fac49cf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.inf @@ -0,0 +1,65 @@ +### @file +# Component information file for the Report Firmware Volume (FV) library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiReportFvLib + FILE_GUID =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D9 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D ReportFvLib + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Sources] + PeiReportFvLib.c + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSU= MES + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase ## CONSU= MES + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset ## CONSU= MES \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aGpioPlatformConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUb= aPlatLib/PeiUbaGpioPlatformConfigLib.c new file mode 100644 index 0000000000..6711de4fad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaGpioPl= atformConfigLib.c @@ -0,0 +1,518 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// UBA and GPIO headers +// +#include +#include + + +/** + +Function gets pointers to the UBA data installed by the right RP package + +@param[out] GpioParams The pointer to the platform GPIO parameters + + +@retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +PlatformGetGpioPlatformMappings ( + IN OUT PLATFORM_GPIO_CONFIG_TABLE *GpioParams + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi (&gUbaConfigDatabasePpiGuid, 0, NULL, &U= baConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + TableSize =3D sizeof(PLATFORM_GPIO_CONFIG_TABLE); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioPlatformConfigDataGuid, + GpioParams, + &TableSize + ); + + return Status; +} + +/** + + Reads GPIO pin to get Flash Security Override jumper status + + @param[out] Jumper - The pointer to the jumper output + + @retval Status - Success if GPIO's are read properly + Jumper - 0x0 if an error happened, otherwise the jumperl value + +**/ +EFI_STATUS +GpioGetFlashSecOvrdVal ( + OUT UINT32 *Jumper + ) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + *Jumper =3D 0x0; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FlashSecOverride =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fl= ashSecOverride, Jumper); + return Status; +} + +/** + + Reads GPIO pin to get recovery jumper status + + @param[out] RcvJumper - The pointer to the Recovery jumper input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetRcvPadVal ( + OUT UINT32 *RcvJumper +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.RcvJumper =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Rc= vJumper, RcvJumper); + return Status; +} + + +/** + + Reads GPIO pin to get FM ADR trigger pin + + @param[out] FmAdrTrigger - The pointer to the ADR trigger input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFmAdrTriggerPadVal ( + OUT UINT32 *FmAdrTrigger +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FmAdrTrigger =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fm= AdrTrigger, FmAdrTrigger); + return Status; +} + + +/** + + Sets GPIO pin to enable ADR on the board + + @param Set[in] - If TRUE means the pas should go 'high', otherwise 'lo= w' + + @retval Status - Success if GPIO set properly + +**/ +EFI_STATUS +GpioSetAdrEnablePadOutVal ( + IN BOOLEAN Set +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR(Status)) { + return Status; + } + + if (GpioPlatformConfig.AdrEnable =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + if (Set) { + Status =3D DynamicSiLibraryPpi->GpioSetOutputValue (GpioPlatformConfig= .AdrEnable, GpioOutHigh); + } + else { + Status =3D DynamicSiLibraryPpi->GpioSetOutputValue (GpioPlatformConfig= .AdrEnable, GpioOutLow); + } + return Status; +} + +/** + + Reads GPIO pin to Force to S1 config mode pad + + @param[out] ForceS1ConfigPad - Input value of the Froce S1 Config pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetForcetoS1ConfigModePadVal ( + OUT UINT32 *ForceS1ConfigPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.ForceTo1SConfigModePad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fo= rceTo1SConfigModePad, ForceS1ConfigPad); + return Status; +} + +/** + + Reads GPIO pin related to QAT + + @param[out] QATPad - Input value of the QAT pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetQATPadVal ( + OUT UINT32 *QATPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.QATGpio =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.QA= TGpio, QATPad); + return Status; + +} + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 1 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad1 ( + OUT UINT32 *FpgaErrorPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FpgaErrorSingnalPad1 =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *FpgaErrorPad =3D (UINT32) GpioPlatformConfig.FpgaErrorSingnalPad1; + return EFI_SUCCESS; + +} + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 2 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad2 ( + OUT UINT32 *FpgaErrorPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FpgaErrorSingnalPad2 =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *FpgaErrorPad =3D (UINT32) GpioPlatformConfig.FpgaErrorSingnalPad2; + return Status; + +} + + +/** + + Get GPIO pin for CPU HP SMI detection for RAS functionality + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetCpuHpSmiPad ( + OUT UINT32 *CpuHpSmiPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.CpuHpSmiPad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *CpuHpSmiPad =3D (UINT32) GpioPlatformConfig.CpuHpSmiPad; + return Status; + +} + + +/** + + Reads GPIO pin that is first bit of the Board ID indication word + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId0PadVal ( + OUT UINT32 *BoardID0Gpio +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.BoardID0Gpio =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Bo= ardID0Gpio, BoardID0Gpio); + return Status; + +} + +/** + + Sets GPIO's used for Boot Mode + + @param None + + @retval Status - Success if GPIO's are configured + +**/ +EFI_STATUS +GpioConfigForMFGMode ( + VOID + ) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.GpioMfgPad.GpioPad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + DEBUG ((EFI_D_INFO, "Start ConfigureGpio() for BootMode Detection.\n")); + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GpioPlatformConfig.Gpi= oMfgPad.GpioPad, &GpioPlatformConfig.GpioMfgPad.GpioConfig); + + ASSERT_EFI_ERROR (Status); + DEBUG ((EFI_D_INFO, "End ConfigureGpio() for BootMode Detection.\n")); + return Status; +} + +/** + + Checks whether the MDF jumper has been set + + @param None + + @retval ManufacturingMode - TRUE when MFG jumper is on, FALSE otherwise + +**/ +BOOLEAN +IsManufacturingMode ( + VOID +) +{ + + BOOLEAN ManufacturingMode =3D TRUE; + + EFI_STATUS Status; + UINT32 GpiValue; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + ASSERT_EFI_ERROR (Status); + + if (GpioPlatformConfig.GpioMfgPad.GpioPad =3D=3D UNUSED_GPIO) { + return FALSE; + } + + Status =3D GpioConfigForMFGMode (); + ASSERT_EFI_ERROR (Status); + + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Gp= ioMfgPad.GpioPad, &GpiValue); + + ASSERT_EFI_ERROR (Status); + + if (!GpiValue) { + ManufacturingMode =3D FALSE; + } + return ManufacturingMode; + +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aPlatLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Pei= UbaPlatLib.inf new file mode 100644 index 0000000000..5e911ba790 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaPlatLi= b.inf @@ -0,0 +1,60 @@ +## @file +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiUbaPlatLib + FILE_GUID =3D EBD8C6DC-8439-47f1-9B31-91464088F135 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D UbaPlatLib|PEIM PEI_CORE + +[sources] + UbaPchEarlyUpdateLib.c + UbaClkGenUpdateLib.c + UbaGpioUpdateLib.c + UbaPcdUpdateLib.c + UbaSoftStrapUpdateLib.c + UbaIioConfigLibPei.c + UbaSlotUpdateLibPei.c + UbaBoardSioInfoLib.c + UbaClocksConfigLib.c + UbaIioPortBifurcationInitLib.c + UbaPchPcieBifurcationLib.c + UbaHsioPtssTableConfigLib.c + PeiUbaUsbOcUpdateLib.c + PeiUbaGpioPlatformConfigLib.c + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + PeimEntryPoint + PeiServicesTablePointerLib + IoLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## ALWAYS_CONSUMES + +[Depex] + gUbaConfigDatabasePpiGuid AND + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aUsbOcUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaUsbOcUpdateLib.c new file mode 100644 index 0000000000..6dbf9eb7eb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaUsbOcU= pdateLib.c @@ -0,0 +1,61 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetUsbOcMappings ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_USBOC_UPDATE_TABLE UsbOcUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(UsbOcUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &UsbOcUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (UsbOcUpdateTable.Signature =3D=3D PLATFORM_USBOC_UPDATE_SIGNATUR= E); + ASSERT (UsbOcUpdateTable.Version =3D=3D PLATFORM_USBOC_UPDATE_VERSION); + + UsbOcUpdateTable.CallUsbOcUpdate( Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaBo= ardSioInfoLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaBoardSioInfoLib.c new file mode 100644 index 0000000000..86c2a6ff4e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaBoardSioI= nfoLib.c @@ -0,0 +1,54 @@ +/** @file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetBoardSioInfo ( + OUT PEI_BOARD_SIO_INFO *BoardSioInfoData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PEI_BOARD_SIO_INFO); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformBoardSioInfoDataGuid, + BoardSioInfoData, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (BoardSioInfoData -> Signature =3D=3D BOARD_SIO_INFO_DATA_SIGNATU= RE); + ASSERT (BoardSioInfoData -> Version =3D=3D BOARD_SIO_INFO_DATA_VERSION); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaCl= kGenUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaClkGenUpdateLib.c new file mode 100644 index 0000000000..c0eb5df07a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaClkGenUpd= ateLib.c @@ -0,0 +1,134 @@ +/** @file + UbaClkGenUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#define CLOCK_GENERATOR_ADDRESS 0xD2 + +EFI_STATUS +PlatformUpdateClockgen ( + IN BOOLEAN EnableSpreadSpectrum +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_CLOCKGEN_UPDATE_TABLE ClockgenTable; + UINTN TableSize =3D 0; + + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 Buffer[PLATFORM_NUMBER_OF_CLOCKGEN= _DATA]; + UINTN Length =3D 0; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_PEI_SMBUS2_PPI *SmbusPpi =3D NULL; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiSmbus2PpiGuid, + 0, + NULL, + &SmbusPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Read the clock generator + // + SlaveAddress.SmbusDeviceAddress =3D CLOCK_GENERATOR_ADDRESS >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + do { + + TableSize =3D sizeof(ClockgenTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformClockgenConfigDataGuid, + &ClockgenTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (ClockgenTable.Signature =3D=3D PLATFORM_CLOCKGEN_UPDATE_SIGNAT= URE); + ASSERT (ClockgenTable.Version =3D=3D PLATFORM_CLOCKGEN_UPDATE_VERSION); + + if (ClockgenTable.Id !=3D PLATFORM_CLOCKGEN_NO_ID) { + if (ClockgenTable.Id !=3D Buffer[ClockgenTable.IdOffset]) { + continue; + } + } + + if (EnableSpreadSpectrum) { + ClockgenTable.Data[ClockgenTable.SpreadSpectrumByteOffset] =3D Clock= genTable.SpreadSpectrumValue; + } + + // + // Program clock generator + // + Command =3D 0; + Length =3D ClockgenTable.DataLength; + + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusWriteBlock, + FALSE, + &Length, //&ConfigurationTableLength, + &ClockgenTable.Data //ConfigurationTable + ); + if (EFI_ERROR(Status)) { + return Status; + } else { + break; + } + }while (!EFI_ERROR(Status)); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaCl= ocksConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaClocksConfigLib.c new file mode 100644 index 0000000000..dd7873522c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaClocksCon= figLib.c @@ -0,0 +1,59 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +ConfigurePlatformClock ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_CLOCKS_CONFIG_TABLE PlatformClocksConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PlatformClocksConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformClocksConfigDataGuid, + &PlatformClocksConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PlatformClocksConfigTable.Signature =3D=3D PLATFORM_CLOCKS_CONFI= G_SIGNATURE); + ASSERT (PlatformClocksConfigTable.Version =3D=3D PLATFORM_CLOCKS_CONFIG_= VERSION); + + Status =3D PlatformClocksConfigTable.CallUpdate(PeiServices, NotifyDescr= iptor, SmbusPpi); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaGp= ioUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Ub= aGpioUpdateLib.c new file mode 100644 index 0000000000..164302ba7b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaGpioUpdat= eLib.c @@ -0,0 +1,68 @@ +/** @file + UbaGpioUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +PlatformUpdateGpios ( + VOID +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_GPIO_UPDATE_TABLE GpioTable; + UINTN TableSize; + UINTN Index; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(GpioTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioConfigDataGuid, + &GpioTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (GpioTable.Signature =3D=3D PLATFORM_GPIO_UPDATE_SIGNATURE); + ASSERT (GpioTable.Version =3D=3D PLATFORM_GPIO_UPDATE_VERSION); + + for (Index =3D 0; GpioTable.Gpios[Index].Register !=3D PLATFORM_END_OF_G= PIO_LIST; Index++) { + + IoWrite32 (GpioTable.Gpios[Index].Register, GpioTable.Gpios[Index].Val= ue); + } + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaHs= ioPtssTableConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaP= latLib/UbaHsioPtssTableConfigLib.c new file mode 100644 index 0000000000..35f67a013a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaHsioPtssT= ableConfigLib.c @@ -0,0 +1,58 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +InstallPlatformHsioPtssTable ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy + +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_HSIO_PTSS_CONFIG_TABLE PlatformHsioPtssConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PlatformHsioPtssConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformHsioPtssTableGuid, + &PlatformHsioPtssConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PlatformHsioPtssConfigTable.Signature =3D=3D PLATFORM_HSIO_PTSS_= TABLE_SIGNATURE); + ASSERT (PlatformHsioPtssConfigTable.Version =3D=3D PLATFORM_HSIO_PTSS_TA= BLE_VERSION); + + PlatformHsioPtssConfigTable.CallUpdate( PchSetup, PchPolicy ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIi= oConfigLibPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaIioConfigLibPei.c new file mode 100644 index 0000000000..e4ac30a962 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIioConfig= LibPei.c @@ -0,0 +1,219 @@ +/** @file + PeiUbaIioConfigLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformIioConfigInit ( + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + *BifurcationTable =3D IioConfigTable.IioBifurcationTablePtr; + *BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize/= sizeof(IIO_BIFURCATION_DATA_ENTRY)); + + *SlotTable =3D IioConfigTable.IioSlotTablePtr; + *SlotEntries =3D (UINT8)(IioConfigTable.IioSlotTableSize/sizeof(IIO_SLOT= _CONFIG_DATA_ENTRY)); + + return Status; +} + +EFI_STATUS +PlatformIioConfigInit2 ( + IN UINT8 SkuPersonalityType, + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + if (SkuPersonalityType =3D=3D 1) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 2) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 3) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + &IioConfigTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + *BifurcationTable =3D IioConfigTable.IioBifurcationTablePtr; + *BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize/= sizeof(IIO_BIFURCATION_DATA_ENTRY)); + + *SlotTable =3D IioConfigTable.IioSlotTablePtr; + *SlotEntries =3D (UINT8)(IioConfigTable.IioSlotTableSize/sizeof(IIO_SLOT= _CONFIG_DATA_ENTRY)); + + return Status; +} + +EFI_STATUS +PlatformUpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + Status =3D IioConfigTable.CallUpdate (IioGlobalData); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +EFI_STATUS +PlatformUpdateIioConfig_EX ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + + Status =3D IioConfigTable.CallUpdate (IioGlobalData); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIi= oPortBifurcationInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiU= baPlatLib/UbaIioPortBifurcationInitLib.c new file mode 100644 index 0000000000..41416adef1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIioPortBi= furcationInitLib.c @@ -0,0 +1,55 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +IioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + IIO_PORT_BIFURCATION_INIT_TABLE IioPortBifurcationInitTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioPortBifurcationInitTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gIioPortBifurcationInitDataGuid, + &IioPortBifurcationInitTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioPortBifurcationInitTable.Signature =3D=3D IIO_PORT_BIFURCATIO= N_INIT_SIGNATURE); + ASSERT (IioPortBifurcationInitTable.Version =3D=3D IIO_PORT_BIFURCATION_= INIT_VERSION); + + IioPortBifurcationInitTable.CallUpdate(IioGlobalData); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= dUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Uba= PcdUpdateLib.c new file mode 100644 index 0000000000..ce822faa2d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPcdUpdate= Lib.c @@ -0,0 +1,69 @@ +/** @file + UbaPcdUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + Function updates Platform Configuration Data (PCD) in Unified Board Abst= raction (UBA) + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS PCDs successfuly intialized + @return EFI_ERROR An error ocurs during PCDs initialization + +**/ +EFI_STATUS +PlatformUpdatePcds ( + VOID + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCD_UPDATE_TABLE PcdUpdateTable; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Size =3D sizeof(PcdUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &PcdUpdateTable, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + ASSERT (PcdUpdateTable.Signature =3D=3D PLATFORM_PCD_UPDATE_SIGNATURE); + ASSERT (PcdUpdateTable.Version =3D=3D PLATFORM_PCD_UPDATE_VERSION); + + Status =3D PcdUpdateTable.CallUpdate (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= hEarlyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchEarlyUpdateLib.c new file mode 100644 index 0000000000..dc7a044729 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPchEarlyU= pdateLib.c @@ -0,0 +1,108 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +PlatformPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_EARLY_UPDATE_TABLE PchEarlyUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PchEarlyUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &PchEarlyUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchEarlyUpdateTable.Signature =3D=3D PLATFORM_PCH_EARLY_UPDATE_S= IGNATURE); + ASSERT (PchEarlyUpdateTable.Version =3D=3D PLATFORM_PCH_EARLY_UPDATE_VER= SION); + + Status =3D PchEarlyUpdateTable.ConfigLan (SystemConfig); + + return Status; +} + +EFI_STATUS +PlatformInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_EARLY_UPDATE_TABLE PchEarlyUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PchEarlyUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &PchEarlyUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchEarlyUpdateTable.Signature =3D=3D PLATFORM_PCH_EARLY_UPDATE_S= IGNATURE); + ASSERT (PchEarlyUpdateTable.Version =3D=3D PLATFORM_PCH_EARLY_UPDATE_VER= SION); + + if (PchEarlyUpdateTable.InitLateHook =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + Status =3D PchEarlyUpdateTable.InitLateHook (SystemConfig); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= hPcieBifurcationLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPl= atLib/UbaPchPcieBifurcationLib.c new file mode 100644 index 0000000000..53c913aa54 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPchPcieBi= furcationLib.c @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetPchPcieBifurcationConfig ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE BifurcationUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(BifurcationUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformUbaPcieBifurcationGuid, + &BifurcationUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (BifurcationUpdateTable.Signature =3D=3D PLATFORM_PCH_PCIE_BIFURC= ATION_UPDATE_SIGNATURE); + ASSERT (BifurcationUpdateTable.Version =3D=3D PLATFORM_PCH_PCIE_BIFURCAT= ION_UPDATE_VERSION); + + BifurcationUpdateTable.CallPcieBifurcationUpdate(PchPcieBifurcationConfi= g, PchSlotConfig); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSl= otUpdateLibPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib= /UbaSlotUpdateLibPei.c new file mode 100644 index 0000000000..55ada7b3aa --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSlotUpdat= eLibPei.c @@ -0,0 +1,156 @@ +/** @file + UbaSlotUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetSlotTableData ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU2Setting, + IN OUT UINT8 *FlagValue +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_SLOT_UPDATE_TABLE IioSlotTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioSlotTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &IioSlotTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioSlotTable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (IioSlotTable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *BroadwayTable =3D IioSlotTable.BroadwayTablePtr; + *IOU2Setting =3D IioSlotTable.GetIOU2Setting (*IOU2Setting); + *FlagValue =3D IioSlotTable.FlagValue; + + return Status; +} + +EFI_STATUS +PlatformGetSlotTableData2 ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU0Setting, + IN OUT UINT8 *FlagValue, + IN OUT UINT8 *IOU2Setting, + IN UINT8 SkuPersonalityType +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_SLOT_UPDATE_TABLE2 IioSlotTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioSlotTable); + if ((SkuPersonalityType =3D=3D 1) || (SkuPersonalityType =3D=3D 3)) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2_1, + &IioSlotTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &IioSlotTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioSlotTable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (IioSlotTable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *BroadwayTable =3D IioSlotTable.BroadwayTablePtr; + *IOU0Setting =3D IioSlotTable.GetIOU0Setting (*IOU0Setting); + *FlagValue =3D IioSlotTable.FlagValue; + *IOU2Setting =3D IioSlotTable.GetIOU2Setting (SkuPersonalityType, *IOU= 2Setting); + + return Status; +} + +EFI_STATUS +PlatformPchGetPciSlotImplementedTableData ( + IN OUT UINT8 **SlotImplementedTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE SITable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + (VOID **)&UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(SITable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &SITable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (SITable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (SITable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *SlotImplementedTable =3D SITable.SlotImplementedTableDataPtr; + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSo= ftStrapUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatL= ib/UbaSoftStrapUpdateLib.c new file mode 100644 index 0000000000..a4042d2b37 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSoftStrap= UpdateLib.c @@ -0,0 +1,95 @@ +/** @file + UbaSoftStrapUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +EFI_STATUS +GetPchSoftSoftStrapTable ( + IN VOID **PchSoftStrapTable + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_SOFTSTRAP_UPDATE PchSoftStrapUpdate; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Size =3D sizeof(PchSoftStrapUpdate); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &PchSoftStrapUpdate, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchSoftStrapUpdate.Signature =3D=3D PLATFORM_SOFT_STRAP_UPDATE_S= IGNATURE); + ASSERT (PchSoftStrapUpdate.Version =3D=3D PLATFORM_SOFT_STRAP_UPDATE_VER= SION); + + *PchSoftStrapTable =3D PchSoftStrapUpdate.PchSoftStrapTablePtr; + + return Status; +} + +VOID +PlatformSpecificPchSoftStrapUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_SOFTSTRAP_UPDATE PchSoftStrapUpdate; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return; + } + + Size =3D sizeof(PchSoftStrapUpdate); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &PchSoftStrapUpdate, + &Size + ); + if (EFI_ERROR(Status)) { + return; + } + + ASSERT (PchSoftStrapUpdate.Signature =3D=3D PLATFORM_SOFT_STRAP_UPDATE_S= IGNATURE); + ASSERT (PchSoftStrapUpdate.Version =3D=3D PLATFORM_SOFT_STRAP_UPDATE_VER= SION); + + PchSoftStrapUpdate.PchSoftStrapPlatformSpecificUpdate (FlashDescriptorCo= py); +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/P= ei/PlatformClocksLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Platfor= mClocksLib/Pei/PlatformClocksLib.c new file mode 100644 index 0000000000..3cd48be906 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/Pei/Plat= formClocksLib.c @@ -0,0 +1,347 @@ +/** @file + Platform Clocks Lib file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SMBUS_RETRIES 10 + + +EFI_STATUS +ConfigureClockGeneratorOnSecondarySmbus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_SMBUS2_PPI *SmbusPpi, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN OUT UINT8 *ConfigurationTable + ); + +/** + + Configure the clock generator using the SMBUS PPI services. + + This function performs a block write, and dumps debug information. + + @param PeiServices - General purpose services available to= every PEIM. + @param ClockType - Clock generator's model name. + @param ClockAddress - SMBUS address of clock generator. + @param ConfigurationTableLength - Length of configuration table. + @param ConfigurationTable - Pointer of configuration table. + + @retval EFI_SUCCESS - Operation success. + +**/ +EFI_STATUS +ConfigureClockGenerator ( + IN EFI_PEI_SERVICES **PeiServices, + IN CLOCK_GENERATOR_TYPE ClockType, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN OUT UINT8 *ConfigurationTable, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN UINT8 SecondarySmbus + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH= ]; + UINTN Length; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_PEI_SMBUS2_PPI *SmbusPpi; + UINT8 SmbErrorsCounter; + + // + // Locate SmBus Ppi + // + Status =3D (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiSmbus2PpiGuid, + 0, + NULL, + &SmbusPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Verify input arguments + // + ASSERT (ConfigurationTableLength >=3D 8); + ASSERT (ConfigurationTableLength <=3D MAX_CLOCK_GENERATOR_BUFFER_LENGTH); + ASSERT (ClockType < ClockGeneratorMax); + ASSERT (ConfigurationTable !=3D NULL); + + // + // Init some local vars + // + SlaveAddress.SmbusDeviceAddress =3D ClockAddress >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + + if (SecondarySmbus =3D=3D TRUE) { + + return (ConfigureClockGeneratorOnSecondarySmbus(PeiServices, + SmbusPpi, + ClockAddress, + ConfigurationTableLength, + EnableSpreadSpectrum, + mSupportedClockGeneratorT, + ConfigurationTable + )); + } else { + // + // Not LightningRidge + // Read the clock generator on the primary SMBus + // + + SmbErrorsCounter =3D 0; + + do + { + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + if(Status !=3D EFI_SUCCESS) + { + DEBUG ((EFI_D_ERROR, "SMBUS reading error\n")); + + } + + SmbErrorsCounter ++; + } + while ((Status !=3D EFI_SUCCESS) && (SmbErrorsCounter < MAX_SMBUS_RETR= IES)); + + // + // Sanity check that the requested clock type is present in our suppor= ted clocks table + // + DEBUG ((DEBUG_INFO, "Expected Clock Generator ID is %x, populated %x\n= ", mSupportedClockGeneratorT->ClockId, Buffer[7])); + + if (EnableSpreadSpectrum) { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] |=3D mSu= pportedClockGeneratorT->SpreadSpectrumBitOffset; + + if (ClockType =3D=3D ClockGeneratorCk420) { + + // Ensure that the clock chip is operating in normal mode. + // + Buffer[10] &=3D ~BIT7; + } + } else { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] &=3D ~(m= SupportedClockGeneratorT->SpreadSpectrumBitOffset); + } + +#ifdef EFI_DEBUG + { + UINT8 i; + DEBUG ((DEBUG_INFO, "SlaveAddress.SmbusDeviceAddress %x: Size =3D%x\= n", SlaveAddress.SmbusDeviceAddress, Length)); + for (i =3D 0; i < ConfigurationTableLength; i++) { + DEBUG ((DEBUG_INFO, "Default Clock Generator Byte %d: %x\n", i, Bu= ffer[i])); + } + } +#endif + + // + // Program clock generator, using the platform default values + // + + SmbErrorsCounter =3D 0; + do + { + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusWriteBlock, + FALSE, + &Length, // &ConfigurationTableLength, + Buffer //ConfigurationTable + ); + // ASSERT_EFI_ERROR (Status); + + + if(Status !=3D EFI_SUCCESS) + { + DEBUG ((EFI_D_ERROR, "SMBUS writing error\n")); + } + + SmbErrorsCounter ++; + } + while ((Status !=3D EFI_SUCCESS) && (SmbErrorsCounter < MAX_SMBUS_RETRI= ES)); + + // + // Dump contents after write + // +#ifdef EFI_DEBUG + { + UINT8 i; + SlaveAddress.SmbusDeviceAddress =3D ClockAddress >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + + for (i =3D 0; i < ConfigurationTableLength; i++) { + DEBUG ((DEBUG_INFO, "Clock Generator Byte %d: %x\n", i, Buffer[i])= ); + } + } +#endif + + return EFI_SUCCESS; + } // else () +} + + +/** + + Configure clock generator on Kahuna + Clock gen is on a secondary SMBus + + @param IN EFI_PEI_SERVICES **PeiServices - Pointer to PEI Servic= es table + @param IN EFI_PEI_SMBUS2_PPI *SmbusPpi - Pointer to SMBUs services= PPI + @param IN UINT8 ClockAddress - SMBus address of clock= gen + @param IN UINT8 *Buffer - Pointer to buffer containin= g byte stream to send to clock gen + @param IN UINTN Length - Number of bytes in buffer + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The function cannot continue due to le= ngth is out of bound. + +**/ +EFI_STATUS +ConfigureClockGeneratorOnSecondarySmbus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_SMBUS2_PPI *SmbusPpi, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN OUT UINT8 *ConfigurationTable + ) +{ + EFI_PEI_STALL_PPI *StallPpi; + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_SMBUS_DEVICE_COMMAND SmbusCommand; + UINTN SmbusLength; + UINT8 SmbusData[MAX_CLOCK_GENERATOR_BUFFER_LENGTH]; + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH]; + UINT8 Length; + + ZeroMem (Buffer, sizeof(Buffer)); + + if (ConfigurationTableLength > MAX_CLOCK_GENERATOR_BUFFER_LENGTH) { + return EFI_INVALID_PARAMETER; + } + + // + // Locate Stall PPI + // + Status =3D (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiStallPpiGuid, + 0, + NULL, + &StallPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Get length of payload to send to clock gen + // + Length =3D (UINT8) ConfigurationTableLength; + + // + // Copy the default clock generator data into Buffer + // + CopyMem ((VOID*)Buffer, ConfigurationTable, Length); + + // + // Set spread spectrum bit in Buffer or clear it? + // + if (EnableSpreadSpectrum) { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] |=3D mSupp= ortedClockGeneratorT->SpreadSpectrumBitOffset; + + if (mSupportedClockGeneratorT->ClockType =3D=3D ClockGeneratorCk420) { + + // + // Ensure that the clock chip is operating in normal mode. + // + Buffer[10] &=3D ~BIT7; + } + } else { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] &=3D ~(mSu= pportedClockGeneratorT->SpreadSpectrumBitOffset); + } + + // + // Now encapsulate the data for a Write Block command to the clock gen + // as the payload in a Write Block command to the SMBus bridge + // + // Segment address =3D 0xF2, this becomes slave address + // Slave address (clock gen) =3D ClockAddress, this becomes slave command + // + SlaveAddress.SmbusDeviceAddress =3D (0xF2 >> 1); + SmbusCommand =3D ClockAddress; + + // + // Set byte index in clock gen to start with, always 0 + // + SmbusData[0] =3D 0; + + // + // Set byte count clock gen wants to see + // + SmbusData[1] =3D (UINT8) Length; + + // + // Payload byte count for SMBus bridge + // + SmbusLength =3D Length + 2; + if (SmbusLength > MAX_CLOCK_GENERATOR_BUFFER_LENGTH) { + return EFI_INVALID_PARAMETER; + } + + // + // Copy the clock gen data to the SMBus buffer + // + CopyMem ((VOID *)(((UINT8*)SmbusData) + 2), (VOID *)Buffer, Length); + + // + // Use EfiSmbusWriteBlock to communicate with clock gen + // + Status =3D SmbusPpi->Execute( SmbusPpi, + SlaveAddress, + SmbusCommand, + EfiSmbusWriteBlock, + FALSE, + &SmbusLength, + &SmbusData ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/P= ei/PlatformClocksLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Platf= ormClocksLib/Pei/PlatformClocksLib.inf new file mode 100644 index 0000000000..cbb5d53d98 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/Pei/Plat= formClocksLib.inf @@ -0,0 +1,40 @@ +## @file +# +# @copyright +# Copyright 2013 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformClocksLib + FILE_GUID =3D 09C4033A-CCD5-45BE-8846-BC7E4536489D + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformClocksLib | PEIM + +[Sources] + PlatformClocksLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib + HobLib + +[Protocols] + +[Guids] + +[Ppis] + gEfiPeiSmbus2PpiGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessL= ib/PlatformCmosAccessLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Pla= tformCmosAccessLib/PlatformCmosAccessLib.c new file mode 100644 index 0000000000..2169b3fadd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessLib/Plat= formCmosAccessLib.c @@ -0,0 +1,73 @@ +/** @file + Platform CMOS Access Library. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Return the platform CMOS entries. + + @param [out] EnryCount Number of platform CMOS entries. + + @return Platform CMOS entries. +**/ +CMOS_ENTRY * +EFIAPI +PlatformCmosGetEntry ( + OUT UINTN *EntryCount + ) +{ + + *EntryCount =3D 0; + return NULL; +} + + +/** + Return the NMI enable status. +**/ + +BOOLEAN +EFIAPI +PlatformCmosGetNmiState ( + VOID + ) +{ + volatile UINT32 Data32; + BOOLEAN Nmi; + Data32 =3D 0; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + // + // Preserve NMI bit setting + // + + if ((DynamicSiLibraryPpi->ReadNmiEn ())& B_PCH_IO_NMI_EN_NMI_EN) { + Nmi =3D TRUE; + } + else + Nmi =3D FALSE; + + return Nmi; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessL= ib/PlatformCmosAccessLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/P= latformCmosAccessLib/PlatformCmosAccessLib.inf new file mode 100644 index 0000000000..c3d7532409 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessLib/Plat= formCmosAccessLib.inf @@ -0,0 +1,45 @@ +## @file +# Library producing CMOS access functionalities are relevant to platform. +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformCmosAccessLib + FILE_GUID =3D f4d9e039-d8c9-4981-a504-7e91715efbc5 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformCmosAccessLib | PEIM + +[Sources] + PlatformCmosAccessLib.c + +[LibraryClasses] + DebugLib + IoLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + BoardModulePkg/BoardModulePkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/Pl= atformHooks.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib= /PlatformHooks.c new file mode 100644 index 0000000000..fa695358bf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/PlatformH= ooks.c @@ -0,0 +1,203 @@ +/** @file + Platform Hooks file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +UINT8 +IsSimPlatform (VOID) +{ + return 0; +} + +/** + + Read Aspeed AHB register. + + @param RegIndex: register index of Aspeed. + + @retval value of register. + +**/ +UINT32 +ReadAHBDword ( + UINT32 RegIndex + ) +{ + UINT8 bValue; + UINT32 rdValue =3D 0; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, ASPEED2500_SIO_SMI); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0x30); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, 1); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf8); + bValue =3D IoRead8(ASPEED2500_SIO_DATA_PORT); + bValue &=3D 0xfc; + bValue |=3D 2; // 4 byte window. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, bValue); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf0); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf1); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf2); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf3); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); + + // trigger read + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xfe); + IoRead8 (ASPEED2500_SIO_DATA_PORT); + + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf4); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf5); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf6); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf7); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + + + return rdValue; + +} + +/** + * Checks for the presence of ASPEED SIO + * @return TRUE if its present. FALSE if not. + */ +BOOLEAN +IsAspeedPresent ( + VOID + ) +{ + BOOLEAN PresenceStatus =3D FALSE; + UINT32 DeviceID; + + // + //ASPEED AST2500/AST2600 + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (ASPEED2500_SIO_DATA_PORT, ASPEED2500_SIO_UART1); + if (IoRead8 (ASPEED2500_SIO_DATA_PORT) =3D=3D ASPEED2500_SIO_UART1) { + // + //right now, maybe it is ASPEED. to detect the device ID. + // + DeviceID =3D ReadAHBDword (SCU7C); + // + //There is a Aspeed card need to support as well. it's type is AST2500 A= 1 EVB. + // + //AST2300-A0 0x01000003 + //AST2300-A1 0x01010303 + //AST1300-A1 0x01010003 + //AST1050-A1 0x01010203 + //AST2400-A0 0x02000303 + //AST2400-A1 0x02010303 + //AST1400-A1 0x02010103 + //AST1250-A1 0x02010303 + //AST2500-A0 0x04000303 + //AST2510-A0 0x04000103 + //AST2520-A0 0x04000203 + //AST2530-A0 0x04000403 + //AST2500-A1 0x04010303 + //AST2510-A1 0x04010103 + //AST2520-A1 0x04010203 + //AST2530-A1 0x04010403 + // + if ((DeviceID & 0xff0000ff) =3D=3D 0x04000003) { + PresenceStatus =3D TRUE; + } + } + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_LOCK); + return PresenceStatus; +} + +/** + * Checks for the presence of Nuvoton SIO + * @return TRUE if its present. FALSE if not. + */ +BOOLEAN +IsNuvotonPresent ( + VOID + ) +{ + BOOLEAN PresenceStatus =3D FALSE; + + // + // Nuvoton NCT5104D + // + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_ENTER_THE_EXTENDED_FUNCTION_= MODE); + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_ENTER_THE_EXTENDED_FUNCTION_= MODE); + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_CHIP_ID_REG); + if (IoRead8 (NCT5104D_SIO_DATA_PORT) =3D=3D NCT5104D_CHIP_ID) { + PresenceStatus =3D TRUE; + } + return PresenceStatus; +} + +/** + * Checks for the presence of the following SIO: + * -ASPEED AST2500 + * -Nuvoton NCT5104D + * + * @return An UINT32 with the corresponding bit set for each SIO. + * -ASPEED_EXIST BIT4 + * -NCT5104D_EXIST BIT3 + * -PC8374_EXIST BIT1 + * -PILOTIV_EXIST BIT0 + */ +UINT32 +IsSioExist ( + VOID + ) +{ + UINT32 SioExit =3D 0; + + if (IsAspeedPresent ()) { + SioExit |=3D ASPEED_EXIST; + } + + if (IsNuvotonPresent ()) { + SioExit |=3D NCT5104D_EXIST; + } + + DEBUG((DEBUG_INFO, "[SIO] Current system SIO exist bit:%x \n", SioExit)); + + return SioExit; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/Pl= atformHooksLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHoo= ksLib/PlatformHooksLib.inf new file mode 100644 index 0000000000..c1b18c4511 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/PlatformH= ooksLib.inf @@ -0,0 +1,28 @@ +## @file +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformHooksLib + FILE_GUID =3D 44497B44-55D0-48b2-8BF8-DDC633C52BF6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformHooksLib + +[Sources] + PlatformHooks.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PciLib + BaseLib + PciSegmentLib + BaseMemoryLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicy= LibNull/PlatformOpromPolicyLibNull.c b/Platform/Intel/WhitleyOpenBoardPkg/L= ibrary/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.c new file mode 100644 index 0000000000..fc466c1bda --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicyLibNull= /PlatformOpromPolicyLibNull.c @@ -0,0 +1,88 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Decide if BIOS embdded option roms should be loaded for a certain PCI de= vice. + + @param PciIo PCI device to return the ROM image for. + + @retval TRUE BIOS embedded option roms should not be run for the P= CI device. + @retval FALSE BIOS embedded option roms could be run for the PCI de= vice. +**/ + +BOOLEAN +PlatformOpromLoadDevicePolicy ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + return TRUE; +} + +/** + For devices that support multiple option roms like FCoE, PXE, iSCSI etc.= , this function decides if one of these BIOS embdded option roms should be = loaded for a certain PCI device based on platform choices. + + @param PciHandle PCI device to return the ROM image for. + @param TableIndex The index pointing to the option rom in the platf= orm option rom table for the PCI device. + + @retval FALSE The specific BIOS embedded option rom should not = be run for the PCI device. + @retval TRUE The specific BIOS embedded option rom could be ru= n for a certain PCI device. +**/ + +OPROM_LOAD_POLICY +PlatformOpromLoadTypePolicy ( + IN EFI_HANDLE PciHandle, + IN UINTN TableIndex + ) +{ + return INCLUSIVE_LOAD; +} + +/** + Decide if a PCIe device option rom should be dispacthed. + + @param PciHandle PCI device handle. + + @retval FALSE The specific PCIe option rom should not be dispat= ched for the PCI device. + @retval TRUE The specific PCIe option rom could be dispatched = for a certain PCI device. + +**/ + +BOOLEAN +PlatformOpromDispatchPolicy ( + IN EFI_HANDLE DeviceHandle +) +{ + return TRUE; +} + + +/** + Enable the legacy console redirection before dispatch the legacy ORPOM o= r disable the legacy console redirection after dispatch + the legacy ORPOM based on setup option and SOL status. + + @param Mode Subfunction. + @param CheckIsAhciRom If the device is legacy Ahci device. + + @retval + +**/ + +VOID +PlatformOpromLegacyCRPolicy ( + IN UINTN Mode, + IN BOOLEAN CheckIsAhciRom +) +{ + + return; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicy= LibNull/PlatformOpromPolicyLibNull.inf b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf new file mode 100644 index 0000000000..7b2f88cb32 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicyLibNull= /PlatformOpromPolicyLibNull.inf @@ -0,0 +1,29 @@ +## @file +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformOpromPolicyLib + FILE_GUID =3D 9FFE7727-A322-4957-BC66-76E25D85A069 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformOpromPolicyLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + PlatformOpromPolicyLibNull.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariab= leSyncLibNull/PlatformSetupVariableSyncLibNull.c b/Platform/Intel/WhitleyOp= enBoardPkg/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSy= ncLibNull.c new file mode 100644 index 0000000000..abe4f2872e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariableSyncL= ibNull/PlatformSetupVariableSyncLibNull.c @@ -0,0 +1,81 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + + +/*++ + Description: + + This function will parse the variable hob and find three vairables: + RP variable + PC common variable + PC generation variable + This is used to sync Pc variable to RP variable value + + Arguments: + PeiServices - PeiServices + Header - VARIABLE_STORE_HEADER + CreateHobDataForRpDefaults - will create a hob for RP defaults, + this is used in normal post case, + cannot be used in specicfic hob event + + + Returns: + + EFI_SUCCESS - Sync to RP variable Success + Other -Sync to RP variable Failure + + + --*/ + +EFI_STATUS SyncSetupVariable ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, + IN BOOLEAN CreateHobDataForRpDefaults +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + + + return Status; + +} + + + +/*++ +Description: + + This function finds the matched default data and create GUID hob only fo= r RP variable . + This is used to sync Pc variable to RP variable value + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateRPVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ){ + EFI_STATUS Status =3D EFI_SUCCESS; + + return Status; + + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariab= leSyncLibNull/PlatformSetupVariableSyncLibNull.inf b/Platform/Intel/Whitley= OpenBoardPkg/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariable= SyncLibNull.inf new file mode 100644 index 0000000000..a65305b1ea --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariableSyncL= ibNull/PlatformSetupVariableSyncLibNull.inf @@ -0,0 +1,28 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformSetupVariableSyncLibNull + FILE_GUID =3D 260C4506-F632-4210-ABB8-6951C2D27AD1 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSetupVariableSyncLibNull|PEIM= PEI_CORE + +[Sources] + PlatformSetupVariableSyncLibNull.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + HobLib + PeiServicesTablePointerLib + PeiServicesLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHoo= kLibNull/PlatformVariableHookLibNull.c b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.c new file mode 100644 index 0000000000..dd1ec54051 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHookLibNul= l/PlatformVariableHookLibNull.c @@ -0,0 +1,55 @@ +/** @file + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + + + + +/*++ +Description: + + This function is a hook for PlatformVariableInitPeiEntry + +--*/ +VOID PlatformVariableHookForEntry( + VOID +){ + + +} + + +/*++ +Description: + + This function allow platform to generate variable hob base on different = event. + +Arguments: + IN VOID *Interface -point to EFI_PEI_READ_ONLY_VARIABL= E2_PPI + IN OUT UINT8 *phobdata, -pont to hob data + IN OUT UINT16 *pDefaultId -pointer to defautlID + +Returns: + TRUE:platform have its own variable hob that need be createn + FALSE:platform don;t need to create variable hob in this case + + +--*/ +BOOLEAN PlatformVariableHookForHobGeneration( + IN VOID *Interface, + IN OUT UINT8 *phobdata, + IN OUT UINT16 *pDefaultId +){ + + + + return FALSE; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHoo= kLibNull/PlatformVariableHookLibNull.inf b/Platform/Intel/WhitleyOpenBoardP= kg/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf new file mode 100644 index 0000000000..0b2c5ca795 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHookLibNul= l/PlatformVariableHookLibNull.inf @@ -0,0 +1,24 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVariableHookLibNull + FILE_GUID =3D 8DAB8601-7FE8-4a1d-A314-09F7D3789C5A + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformVariableHookLibNull +[sources] + PlatformVariableHookLibNull.c + +[LibraryClasses] + BaseLib + IoLib + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsL= ib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.c new file mode 100644 index 0000000000..d12c253846 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.c @@ -0,0 +1,446 @@ +/** @file + Read FFS Library + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// +//EFI_FIRMWARE_FILE_SYSTEM3_GUID indicates support for FFS_ATTRIB_LARGE_SI= ZE +//And thus support for files 16MB or larger. +// +UINT8 * +PreMemReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN BOOLEAN skipheader + ) +/*++ + +Routine Description: + + Read FFS file from specified FV in PreMem phase + +Arguments: + + FwVolHeader - FV Base Address + + FFSGuid - FFS to find & Read + + FFSDataSize - Data size to read.If this value equal 0, will read the w= hole FFS size + + skipheader - TRUE: skip to read the ffs and first section header,read= from data directly, for one data section only ffs + FALSE:read from header + +Returns: + + None + +--*/ +{ + EFI_FFS_FILE_HEADER *ffsHdr; + UINT64 FvSize; + UINT32 FileOccupiedSize; + UINT32 FFSDataOffset; + EFI_FIRMWARE_VOLUME_EXT_HEADER *FwVolExtHeader; + UINT32 FFSSize =3D 0; + + FvSize =3D 0; + FFSDataOffset =3D 0; + if (FwVolHeader->ExtHeaderOffset !=3D 0) { + // + // Searching for files starts on an 8 byte aligned boundary after the = end of the Extended Header if it exists. + // + FwVolExtHeader =3D (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINTN)FwVolHea= der + FwVolHeader->ExtHeaderOffset ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ((UINT8 *) FwVolExtHeader + FwVolEx= tHeader->ExtHeaderSize); + } else { + ffsHdr =3D (EFI_FFS_FILE_HEADER*)(((UINT8 *) FwVolHeader)+ FwVolHeade= r->HeaderLength); + } + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + + if(FwVolHeader->FvLength =3D=3D 0xFFFFFFFFFFFFFFFF) return NULL; + + FvSize =3D (UINTN)ffsHdr-(UINTN)FwVolHeader; + while((FvSize < FwVolHeader->FvLength)&&((UINTN)ffsHdr <((UINTN)FwVolHea= der+ (UINTN)FwVolHeader->FvLength))){ + if(CompareGuid (&ffsHdr->Name, &FFSGuid)) break; + + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + + FvSize+=3D FileOccupiedSize; + ffsHdr =3D (EFI_FFS_FILE_HEADER *)((UINT8 *)ffsHdr + FileOccupiedSize= ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + } + + if (FvSize < FwVolHeader->FvLength) { + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + FFSSize =3D FileOccupiedSize; + + if(FFSDataSize =3D=3D 0) + FFSDataSize=3D FFSSize; + + if(skipheader){ + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER2) + sizeof(EFI_COMMON= _SECTION_HEADER2); + } else { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_= SECTION_HEADER); + } + if(FFSDataSize =3D=3D 0) { + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER2) - siz= eof(EFI_COMMON_SECTION_HEADER2); + } else { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER) - size= of(EFI_COMMON_SECTION_HEADER); + } + } + } + } + + return (UINT8 *)ffsHdr + FFSDataOffset; +} + +EFI_STATUS +ReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN OUT VOID *FFSData, + OUT UINT32 *FFSSize, + IN BOOLEAN skipheader + ) +/*++ + +Routine Description: + + Read FFS file from FV + +Arguments: + + FwVolHeader - FV Base Address + + FFSGuid - FFS to find & Read + + FFSDataSize - Data size to read.If this value equal 0, will read the w= hole FFS size + + FFSData - Pointer to buffer for read. + + FFSSize - FFS file size FYI for caller. + + skipheader - TRUE: skip to read the ffs and first section header,read fr= om data directly, for one data section only ffs + FALSE:read from header + +Returns: + + None + +--*/ +{ + EFI_FFS_FILE_HEADER *ffsHdr; + UINT64 FvSize; + UINT32 FileOccupiedSize; + UINT32 FFSDataOffset; + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME_EXT_HEADER *FwVolExtHeader; + + Status =3D EFI_NOT_FOUND; + *FFSSize =3D 0; + FvSize =3D 0; + FFSDataOffset =3D 0; + if (FwVolHeader->ExtHeaderOffset !=3D 0) { + // + // Searching for files starts on an 8 byte aligned boundary after the = end of the Extended Header if it exists. + // + FwVolExtHeader =3D (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINTN)FwVolHea= der + FwVolHeader->ExtHeaderOffset ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ((UINT8 *) FwVolExtHeader + FwVolEx= tHeader->ExtHeaderSize); + } else { + ffsHdr =3D (EFI_FFS_FILE_HEADER*)(((UINT8 *) FwVolHeader)+ FwVolHeade= r->HeaderLength); + } + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + + if(FwVolHeader->FvLength =3D=3D 0xFFFFFFFFFFFFFFFF) { + return EFI_VOLUME_CORRUPTED; + } + + FvSize =3D (UINTN)ffsHdr-(UINTN)FwVolHeader; + while((FvSize < FwVolHeader->FvLength)&&((UINTN)ffsHdr <((UINTN)FwVolHea= der+ (UINTN)FwVolHeader->FvLength))){ + if(CompareGuid (&ffsHdr->Name, &FFSGuid)){ + Status =3D EFI_SUCCESS; + break; + } + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + + FvSize+=3D FileOccupiedSize; + ffsHdr =3D (EFI_FFS_FILE_HEADER *)((UINT8 *)ffsHdr + FileOccupiedSize= ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + } + + if (FvSize < FwVolHeader->FvLength) { + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + *FFSSize =3D FileOccupiedSize; + + if(FFSDataSize =3D=3D 0) { + FFSDataSize=3D *FFSSize; + } + + if(skipheader){ + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER2) + sizeof(EFI_COMMON_S= ECTION_HEADER2); + } else { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_SE= CTION_HEADER); + } + if(FFSDataSize =3D=3D 0) { + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER2) - sizeo= f(EFI_COMMON_SECTION_HEADER2); + } else { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER) - sizeof= (EFI_COMMON_SECTION_HEADER); + } + } + } + + CopyMem(FFSData,(UINT8*)ffsHdr + FFSDataOffset,FFSDataSize); + } + return Status; +} + +BOOLEAN +NormalHobToCompressHob(IN OUT VOID* hobAddr,IN OUT UINTN* size) +{ + UINTN i,j,k; + COMPRESS_HOBO_DATA CompressHob; + COMPRESS_ITEM Hobitem[MAX_COMPRESS_ITEM]; + UINT16 TempBuffer[MAX_FFS_BUFFER_SIZE/4]; + UINTN offset=3D0; + UINTN RemainSize =3D 0; + + CompressHob.Signature =3D 0x5A45524F; + CompressHob.Count =3D0; + j=3D0; + i=3D0; + RemainSize =3D (*size % 2) + 2; + if(MAX_COMPRESS_ITEM*sizeof(COMPRESS_ITEM)+MAX_FFS_BUFFER_SIZE/4+sizeof(= COMPRESS_HOBO_DATA) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + if((*size) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + ZeroMem(TempBuffer,MAX_FFS_BUFFER_SIZE/2); + + while(i < (*size - RemainSize)){ + + if(j>=3DMAX_COMPRESS_ITEM) { + return FALSE; + } + + //search for duplicate array + if(*(UINT16*)((UINTN)hobAddr+i)=3D=3D*(UINT16*)((UINTN)hobAddr+i+2) ){ + + for(k=3D2;(i+k)<(*size- RemainSize);k+=3D2 ){ + if(*(UINT16*)((UINTN)hobAddr+i)!=3D*(UINT16*)((UINTN)hobAddr+i+k)= ){ + break; + } + } + + if(i+k>=3D *size - (*size % 2)) { + k -=3D2; + } + + Hobitem[j].Value =3D *(UINT16*)((UINTN)hobAddr+i); + Hobitem[j].Length =3D(UINT16) k; + Hobitem[j].Type =3D COMPRESS_DUPLICATE; + Hobitem[j].Offset =3D 0; + j++; + CompressHob.Count =3D(UINT32)j; + i+=3Dk; + + } + else{//single array + for(k=3D2;i+k+2 <=3D (*size- RemainSize);k+=3D2){ + if(offset >=3D MAX_FFS_BUFFER_SIZE/4) { + return FALSE; + } + TempBuffer[offset]=3D *(UINT16*)((UINTN)hobAddr+i+k-2); + offset +=3D1; + if(*(UINT16*)((UINTN)hobAddr+i+k)=3D=3D*(UINT16*)((UINTN)hobAddr+i+= k+2)){ + k +=3D 2; + break; + } + + } + + + Hobitem[j].Length =3D (UINT16) k - 2; + Hobitem[j].Type =3D COMPRESS_SINGLE; + Hobitem[j].Offset =3D (UINT16)(offset - (Hobitem[j].Length/2) ); + Hobitem[j].Value =3D0; + j++; + CompressHob.Count =3D(UINT32)j; + i+=3Dk - 2; + + } + + } + + if(j>=3DMAX_COMPRESS_ITEM) { + //not worth to compress + return FALSE; + } + + //process last one + CopyMem((UINT8*)(&TempBuffer[offset]), (UINT8*)((UINTN)hobAddr + *size -= RemainSize), RemainSize); + Hobitem[j].Length =3D (UINT16)RemainSize; + Hobitem[j].Type =3D COMPRESS_SINGLE; + Hobitem[j].Offset =3D (UINT16)offset; + Hobitem[j].Value =3D0; + j++; + CompressHob.Count =3D(UINT32)j; + + CopyMem(hobAddr,(VOID*)&CompressHob,sizeof(COMPRESS_HOBO_DATA)); + offset =3D sizeof(COMPRESS_HOBO_DATA); + for(i=3D0; i < CompressHob.Count;i++){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),(UINT8*)&Hobitem[i],sizeof(COM= PRESS_ITEM)); + offset +=3D sizeof(COMPRESS_ITEM); + if(Hobitem[i].Type =3D=3D COMPRESS_SINGLE){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),&TempBuffer[Hobitem[i].Offse= t],Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + } + } + + *size =3D offset; + + return TRUE; +} + +BOOLEAN +CompressHobToNormalHob(IN OUT VOID* hobAddr,OUT UINTN* size) +{ + UINTN i; + COMPRESS_HOBO_DATA CompressHob ; + COMPRESS_ITEM Hobitem[MAX_COMPRESS_ITEM]; + UINTN offset=3D0; + UINT16 TempBuffer[MAX_FFS_BUFFER_SIZE/4]; + + CopyMem((VOID*)&CompressHob,hobAddr,sizeof(COMPRESS_HOBO_DATA)); + + if(CompressHob.Signature !=3D 0x5A45524F) { + return FALSE; + } + + if(CompressHob.Count>MAX_COMPRESS_ITEM) { + //not worth to compress + return FALSE; + } + + if(*size > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + if(MAX_COMPRESS_ITEM*sizeof(COMPRESS_ITEM)+MAX_FFS_BUFFER_SIZE/4+sizeof(= COMPRESS_HOBO_DATA) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + offset =3D sizeof(COMPRESS_HOBO_DATA); + for(i=3D0; i < CompressHob.Count;i++){ + CopyMem((VOID*)&Hobitem[i],(UINT8*)((UINTN)hobAddr+offset),sizeof(COMP= RESS_ITEM)); + offset +=3D sizeof(COMPRESS_ITEM); + if(Hobitem[i].Type =3D=3D COMPRESS_SINGLE){ + CopyMem(&TempBuffer[Hobitem[i].Offset],(UINT8*)((UINTN)hobAddr+offse= t),Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + } + } + + offset =3D0; + for(i=3D0; i < CompressHob.Count;i++){ + if(Hobitem[i].Type =3D=3DCOMPRESS_DUPLICATE){ + SetMem16((VOID*)((UINTN)hobAddr+offset),Hobitem[i].Length,Hobitem[i].= Value); + offset +=3D Hobitem[i].Length; + } + else if(Hobitem[i].Type =3D=3DCOMPRESS_SINGLE){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),&TempBuffer[Hobitem[i].Offset= ],Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + + } + + } + + *size =3D offset; + + return TRUE; +} + +EFI_STATUS +ValidateCommonFvHeader ( + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ) +/*++ + +Routine Description: + Check the integrity of firmware volume header + +Arguments: + FwVolHeader - A pointer to a firmware volume header + +Returns: + EFI_SUCCESS - The firmware volume is consistent + EFI_NOT_FOUND - The firmware volume has corrupted. So it is not = an FV + +--*/ +{ + UINT16 *Ptr; + UINT16 HeaderLength; + UINT16 Checksum; + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) || + (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength =3D=3D ((UINTN) -1)) || + ((FwVolHeader->HeaderLength & 0x01) !=3D 0) + ) { + return EFI_NOT_FOUND; + } + // + // Verify the header checksum + // + HeaderLength =3D (UINT16) (FwVolHeader->HeaderLength / 2); + Ptr =3D (UINT16 *) FwVolHeader; + Checksum =3D 0; + while (HeaderLength > 0) { + Checksum =3D Checksum + (*Ptr); + Ptr++; + HeaderLength--; + } + + if (Checksum !=3D 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsL= ib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.i= nf new file mode 100644 index 0000000000..94f2cdbb5f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.inf @@ -0,0 +1,34 @@ +## @file +# Read FFS library +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ReadFfsLib + FILE_GUID =3D CD5BD27A-A122-41DE-B277-A258284BF35C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ReadFfslib + +[Sources] + ReadFfsLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + +[Pcd] + +[Protocols] + +[Guids] + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns165= 50.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns16550.h new file mode 100644 index 0000000000..77a1bdd849 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns16550.h @@ -0,0 +1,46 @@ +/** @file + Header file of NS16550 hardware definition. + + @copyright + Copyright 6550 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __NS16550_H_ +#define __NS16550_H_ + +// +// --------------------------------------------- +// UART Register Offsets +// --------------------------------------------- +// +#define BAUD_LOW_OFFSET 0x00 +#define BAUD_HIGH_OFFSET 0x01 +#define IER_OFFSET 0x01 +#define LCR_SHADOW_OFFSET 0x01 +#define FCR_SHADOW_OFFSET 0x02 +#define IR_CONTROL_OFFSET 0x02 +#define FCR_OFFSET 0x02 +#define EIR_OFFSET 0x02 +#define BSR_OFFSET 0x03 +#define LCR_OFFSET 0x03 +#define MCR_OFFSET 0x04 +#define LSR_OFFSET 0x05 +#define MSR_OFFSET 0x06 + +// +// --------------------------------------------- +// UART Register Bit Defines +// --------------------------------------------- +// +#define LSR_TXRDY 0x20 +#define LSR_RXDA 0x01 +#define DLAB 0x01 + +#define UART_DATA 8 +#define UART_STOP 1 +#define UART_PARITY 0 +#define UART_BREAK_SET 0 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.c new file mode 100644 index 0000000000..28be8147c2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/SerialPortLi= b.c @@ -0,0 +1,1023 @@ +/** @file + Serial I/O Port library functions with no library constructor/destructor + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "Ns16550.h" +#include +#include +#include +#include +#include +#include + +// +// PCH I/O Port Defines +// +#define R_PCH_IOPORT_PCI_INDEX 0xCF8 +#define R_PCH_IOPORT_PCI_DATA 0xCFC + +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11= ) | (((Bus) & 0xFF) << 16) | (1 << 31)) + +#define PCH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(DEFAULT_PCI_BUS_NUMBER_PC= H, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, Offset) + +// +// PCI Defintions. +// +#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01 + +#define B_UART_FCR_FIFOE BIT0 +#define B_UART_FCR_FIFO64 BIT5 +#define R_UART_LCR 3 +#define R_UART_LSR 5 +#define B_UART_LSR_RXRDY BIT0 +#define R_UART_MCR 4 +#define B_UART_MCR_RTS BIT1 +#define B_UART_MCR_DTRC BIT0 +#define R_UART_MSR 6 +#define B_UART_MSR_CTS BIT4 +#define B_UART_MSR_DSR BIT5 +#define B_UART_MSR_RI BIT6 +#define B_UART_MSR_DCD BIT7 +#define B_UART_LSR_RXRDY BIT0 +#define B_UART_LSR_TXRDY BIT5 +#define B_UART_LSR_TEMT BIT6 +#define R_UART_BAUD_LOW 0 +#define R_UART_BAUD_HIGH 1 +#define B_UART_LCR_DLAB BIT7 + +// +// COM definitions +// +#define COM1_BASE 0x3f8 +#define COM2_BASE 0x2f8 + +UINT32 +IsSioExist ( + VOID + ); + +typedef struct { + UINT8 Index; + UINT8 Data; +} SIO_REG_TABLE; + + +STATIC SIO_REG_TABLE mASPEED2500Table [] =3D { + { REG_LOGICAL_DEVICE, ASPEED2500_SIO_UART1 }, + { ACTIVATE, 0x01 }, + { PRIMARY_INTERRUPT_SELECT, 0x04 }, // COMA IRQ routing + { INTERRUPT_TYPE, 0x01 }, // COMA Interrupt Type + { REG_LOGICAL_DEVICE, ASPEED2500_SIO_UART2 }, + { ACTIVATE, 0x01 }, + { PRIMARY_INTERRUPT_SELECT, 0x03 }, // COMB IRQ routing + { INTERRUPT_TYPE, 0x01 } // COMB Interrupt Type +}; + +UINT8 gData =3D 8; +UINT8 gStop =3D 1; +UINT8 gParity =3D 0; +UINT8 gBreakSet =3D 0; + +// +// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo +// +typedef struct { + UINT8 Device; + UINT8 Function; + UINT16 PowerManagementStatusAndControlRegister; +} PCI_UART_DEVICE_INFO; + +/** + + Check if Serial Port is enabled or not. + + @param none + + @retval TRUE Serial Port was enabled. + @retval FALSE Serial Port was disabled. + +**/ +BOOLEAN +EFIAPI +IsSerialPortEnabled ( +) +{ + return TRUE; +} + +UINT8 +SerialPortReadRegister ( + UINTN Base, + UINTN Offset + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } else { + return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } +} + +UINT8 +SerialPortWriteRegister ( + UINTN Base, + UINTN Offset, + UINT8 Value + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),= Value); + } else { + return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), V= alue); + } +} + +/** + Update the value of an 32-bit PCI configuration register in a PCI device= . If the + PCI Configuration register specified by PciAddress is already programmed= with a + non-zero value, then return the current value. Otherwise update the PCI= configuration + register specified by PciAddress with the value specified by Value and r= eturn the + value programmed into the PCI configuration register. All values must b= e masked + using the bitmask specified by Mask. + + @param PciAddress PCI Library address of the PCI Configuration registe= r to update. + @param Value The value to program into the PCI Configuration Regi= ster. + @param Mask Bitmask of the bits to check and update in the PCI c= onfiguration register. + + @return The Secondary bus number that is actually programed into the PC= I to PCI Bridge device. + +**/ +UINT32 +SerialPortLibUpdatePciRegister32 ( + UINTN PciAddress, + UINT32 Value, + UINT32 Mask + ) +{ + UINT32 CurrentValue; + + CurrentValue =3D PciRead32 (PciAddress) & Mask; + if (CurrentValue !=3D 0) { + return CurrentValue; + } + return PciWrite32 (PciAddress, Value & Mask); +} + +/** + Retrieve the I/O or MMIO base address register for the PCI UART device. + + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO i= n PCI UART + Device if they are not already enabled. + + @return The base address register of the UART device. + +**/ +UINTN +GetSerialRegisterBase ( + VOID + ) +{ + UINTN PciLibAddress; + UINTN BusNumber; + UINTN SubordinateBusNumber; + UINT32 ParentIoBase; + UINT32 ParentIoLimit; + UINT16 ParentMemoryBase; + UINT16 ParentMemoryLimit; + UINT32 IoBase; + UINT32 IoLimit; + UINT16 MemoryBase; + UINT16 MemoryLimit; + UINTN SerialRegisterBase; + UINTN BarIndex; + UINT32 RegisterBaseMask; + PCI_UART_DEVICE_INFO *DeviceInfo; + + // + // Get PCI Device Info + // + DeviceInfo =3D (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInf= o); + + // + // If PCI Device Info is empty, then assume fixed address UART and retur= n PcdSerialRegisterBase + // + if (DeviceInfo->Device =3D=3D 0xff) { + return (UINTN)PcdGet64 (PcdSerialRegisterBase); + } + + // + // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB + // + ParentMemoryBase =3D 0 >> 16; + ParentMemoryLimit =3D 0xfff00000 >> 16; + ParentIoBase =3D 0 >> 12; + ParentIoLimit =3D 0xf000 >> 12; + + // + // Enable I/O and MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber =3D 0; (DeviceInfo + 1)->Device !=3D 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Devi= ceInfo->Function, 0); + + // + // Retrieve and verify the bus numbers in the PCI to PCI Bridge + // + BusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDAR= Y_BUS_REGISTER_OFFSET); + SubordinateBusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDIN= ATE_BUS_REGISTER_OFFSET); + if (BusNumber =3D=3D 0 || BusNumber > SubordinateBusNumber) { + return 0; + } + + // + // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI= Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + MemoryLimit =3D PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Br= idge.MemoryLimit)) & 0xfff0; + MemoryBase =3D PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Br= idge.MemoryBase)) & 0xfff0; + + // + // If PCI Bridge MMIO window is disabled, then return 0 + // + if (MemoryLimit < MemoryBase) { + return 0; + } + + // + // If PCI Bridge MMIO window is not in the address range decoded by = the parent PCI Bridge, then return 0 + // + if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit = || MemoryLimit > ParentMemoryLimit) { + return 0; + } + ParentMemoryBase =3D MemoryBase; + ParentMemoryLimit =3D MemoryLimit; + } else { + IoLimit =3D PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoLimit)); + if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) =3D=3D 0) { + IoLimit =3D IoLimit >> 4; + } else { + IoLimit =3D (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bri= dge.IoLimitUpper16)) << 4) | (IoLimit >> 4); + } + IoBase =3D PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase)); + if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) =3D=3D 0) { + IoBase =3D IoBase >> 4; + } else { + IoBase =3D (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Brid= ge.IoBaseUpper16)) << 4) | (IoBase >> 4); + } + + // + // If PCI Bridge I/O window is disabled, then return 0 + // + if (IoLimit < IoBase) { + return 0; + } + + // + // If PCI Bridge I/O window is not in the address range decoded by t= he parent PCI Bridge, then return 0 + // + if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > Par= entIoLimit) { + return 0; + } + ParentIoBase =3D IoBase; + ParentIoLimit =3D IoLimit; + } + } + + // + // Compute PCI Lib Address to PCI UART + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Device= Info->Function, 0); + + // + // Find the first IO or MMIO BAR + // + RegisterBaseMask =3D 0xFFFFFFF0; + for (BarIndex =3D 0; BarIndex < PCI_MAX_BAR; BarIndex ++) { + SerialRegisterBase =3D PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_= OFFSET + BarIndex * 4); + if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) =3D= =3D 0)) { + // + // MMIO BAR is found + // + RegisterBaseMask =3D 0xFFFFFFF0; + break; + } + + if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != =3D 0)) { + // + // IO BAR is found + // + RegisterBaseMask =3D 0xFFFFFFF8; + break; + } + } + + // + // MMIO or IO BAR is not found. + // + if (BarIndex =3D=3D PCI_MAX_BAR) { + return 0; + } + + // + // Program UART BAR + // + SerialRegisterBase =3D SerialPortLibUpdatePciRegister32 ( + PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarI= ndex * 4, + (UINT32)PcdGet64 (PcdSerialRegisterBase), + RegisterBaseMask + ); + + // + // Verify that the UART BAR is in the address range decoded by the paren= t PCI Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((Seri= alRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) { + return 0; + } + } else { + if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >= > 12) > ParentIoLimit) { + return 0; + } + } + + // + // Enable I/O and MMIO in PCI UART Device if they are not already enabled + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI= _COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specified + // + if (DeviceInfo->PowerManagementStatusAndControlRegister !=3D 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndCo= ntrolRegister) & (BIT0 | BIT1)) !=3D 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndContro= lRegister, (UINT16)~(BIT0 | BIT1)); + // + // If PCI UART was not in D0, then make sure FIFOs are enabled, but = do not reset FIFOs + // + SerialPortWriteRegister (SerialRegisterBase, FCR_OFFSET, (UINT8)(Pcd= Get8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); + } + } + + // + // Get PCI Device Info + // + DeviceInfo =3D (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInf= o); + + // + // Enable I/O or MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber =3D 0; (DeviceInfo + 1)->Device !=3D 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Devi= ceInfo->Function, 0); + + // + // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_P= CI_COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specifi= ed + // + if (DeviceInfo->PowerManagementStatusAndControlRegister !=3D 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAnd= ControlRegister) & (BIT0 | BIT1)) !=3D 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndCont= rolRegister, (UINT16)~(BIT0 | BIT1)); + } + } + + BusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGIS= TER_OFFSET); + } + + return SerialRegisterBase; +} + + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +InitializeSio ( + VOID + ) +{ + + UINT32 SioExist; + UINT32 SioEnable; + UINT32 Index; + UINT32 Decode; + UINT32 Enable; + UINT32 SpiConfigValue; + + // + // Enable LPC decode + // Set COMA/COMB base + // + Decode =3D ((V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) | (V_LPC_CFG= _IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB)); + SpiConfigValue =3D MmioRead32 (PCH_PCR_ADDRESS (PID_ESPISPI, R_PCH_PCR_S= PI_CONF_VALUE)); + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + Enable =3D ( B_LPC_CFG_IOE_ME2 | B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_ME1= \ + | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE); + } else { + Enable =3D ( B_LPC_CFG_IOE_ME2 | B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_ME1= \ + | B_LPC_CFG_IOE_KE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE); + } + IoWrite32 (R_PCH_IOPORT_PCI_INDEX, (UINT32) (PCH_LPC_CF8_ADDR (R_LPC_CFG= _IOD))); + + IoWrite32 (R_PCH_IOPORT_PCI_DATA, Decode | (Enable << 16)); + + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_LPCIOD), (UINT16)Dec= ode); + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_LPCIOE), (UINT16)Ena= ble); + + SioExist =3D IsSioExist(); + + if ((SioExist & (PILOTIV_EXIST | PC8374_EXIST)) =3D=3D (PILOTIV_EXIST | = PC8374_EXIST) ) { + // + // Both are there, we use DEFAULT_SIO as debug port anyway + // + if (DEFAULT_SIO =3D=3D PILOTIV_EXIST) { + SioEnable =3D PILOTIV_EXIST; + } else { + SioEnable =3D PC8374_EXIST; + } + } else { + SioEnable =3D SioExist; + } + + // + // ASPEED AST2500/AST2600 UART init. + // + if (SioEnable =3D=3D ASPEED_EXIST) { + // + // Unlock SIO + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + + // + // COM1 & COM2 + // + for (Index =3D 0; Index < sizeof (mASPEED2500Table)/sizeof (SIO_REG_TA= BLE); Index++) { + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, mASPEED2500Table[Index].Index); + IoWrite8 (ASPEED2500_SIO_DATA_PORT, mASPEED2500Table[Index].Data); + } + + // + // Lock SIO + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_LOCK); + } +} + +/** + + Initialize Serial Port + + The Baud Rate Divisor registers are programmed and the LCR + is used to configure the communications format. Hard coded + UART config comes from globals in DebugSerialPlatform lib. + + @param None + + @retval None + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINTN Divisor; + UINT8 OutputData; + UINT8 Data; + UINT16 ComBase; + + ComBase =3D (UINT16)PcdGet64 (PcdSerialRegisterBase); + InitializeSio(); + // + // Some init is done by the platform status code initialization. + // + // + // Map 5..8 to 0..3 + // + Data =3D (UINT8) (gData - (UINT8) 5); + + // + // Calculate divisor for baud generator + // + Divisor =3D 115200 / PcdGet32(PcdSerialBaudRate); + + // + // Set communications format + // + OutputData =3D (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3= ) | ((gStop << 2) | Data)))); + IoWrite8 (ComBase + LCR_OFFSET, OutputData); + + // + // Configure baud rate + // + IoWrite8 (ComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (ComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); + + // + // Switch back to bank 0 + // + OutputData =3D (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << = 3) | ((gStop << 2) | Data)))); + IoWrite8 (ComBase + LCR_OFFSET, OutputData); + + return RETURN_SUCCESS; +} + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes writed to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + UINT8 Data; + + if ((IsSerialPortEnabled() =3D=3D FALSE) || (NULL =3D=3D Buffer)) { + return 0; + } + + Result =3D NumberOfBytes; + + while (NumberOfBytes--) { + // + // Wait for the serail port to be ready. + // + do { + Data =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OF= FSET); + } while ((Data & LSR_TXRDY) =3D=3D 0); + IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++); + } + + return Result; +} + + +/* + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed. + @retval !0 Actual number of bytes raed to serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + UINT8 Data; + + if ((IsSerialPortEnabled() =3D=3D FALSE) || (NULL =3D=3D Buffer)) { + return 0; + } + + Result =3D NumberOfBytes; + + while (NumberOfBytes--) { + // + // Wait for the serail port to be ready. + // + do { + Data =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OF= FSET); + } while ((Data & LSR_RXDA) =3D=3D 0); + + *Buffer++ =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase)); + } + + return Result; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN SerialRegisterBase; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return FALSE; + } + + // + // Read the serial port status + // + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LS= R_RXRDY) !=3D 0) { + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Clear RTS to prevent peer from sending data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Ser= ialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS)); + } + return TRUE; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Set RTS to let the peer send some data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Seria= lPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS)); + } + + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the seria= l device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Mcr; + + // + // First determine the parameter is invalid. + // + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_= READY | + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) !=3D 0) { + return RETURN_UNSUPPORTED; + } + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + // + // Read the Modem Control Register. + // + Mcr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + Mcr &=3D (~(B_UART_MCR_DTRC | B_UART_MCR_RTS)); + + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) =3D=3D EFI_SERIAL_DATA_TE= RMINAL_READY) { + Mcr |=3D B_UART_MCR_DTRC; + } + + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) =3D=3D EFI_SERIAL_REQUEST_TO_= SEND) { + Mcr |=3D B_UART_MCR_RTS; + } + + // + // Write the Modem Control Register. + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr); + + return RETURN_SUCCESS; + +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial= device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Msr; + UINT8 Mcr; + UINT8 Lsr; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + *Control =3D 0; + + // + // Read the Modem Status Register. + // + Msr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MSR); + + if ((Msr & B_UART_MSR_CTS) =3D=3D B_UART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((Msr & B_UART_MSR_DSR) =3D=3D B_UART_MSR_DSR) { + *Control |=3D EFI_SERIAL_DATA_SET_READY; + } + + if ((Msr & B_UART_MSR_RI) =3D=3D B_UART_MSR_RI) { + *Control |=3D EFI_SERIAL_RING_INDICATE; + } + + if ((Msr & B_UART_MSR_DCD) =3D=3D B_UART_MSR_DCD) { + *Control |=3D EFI_SERIAL_CARRIER_DETECT; + } + + // + // Read the Modem Control Register. + // + Mcr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + + if ((Mcr & B_UART_MCR_DTRC) =3D=3D B_UART_MCR_DTRC) { + *Control |=3D EFI_SERIAL_DATA_TERMINAL_READY; + } + + if ((Mcr & B_UART_MCR_RTS) =3D=3D B_UART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + // + // Read the Line Status Register. + // + Lsr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_LSR); + + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) =3D=3D (B_UART_LSR_TEMT= | B_UART_LSR_TXRDY)) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((Lsr & B_UART_LSR_RXRDY) =3D=3D 0) { + *Control |=3D EFI_SERIAL_INPUT_BUFFER_EMPTY; + } + + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + serial interface. A ReceiveFifoDepth value of = 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in microseconds. + This timeout applies to both the transmit and = receive side of the + interface. A Timeout value of 0 will use the d= evice's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A Parity value of + DefaultParity will use the device's default pa= rity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. A DataBits + vaule of 0 will use the device's default data = bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. A StopBits + value of DefaultStopBits will use the device's= default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + UINTN SerialRegisterBase; + UINT32 SerialBaudRate; + UINTN Divisor; + UINT8 Lcr; + UINT8 LcrData; + UINT8 LcrParity; + UINT8 LcrStop; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + // + // Check for default settings and fill in actual values. + // + if (*BaudRate =3D=3D 0) { + *BaudRate =3D PcdGet32 (PcdSerialBaudRate); + } + SerialBaudRate =3D (UINT32) *BaudRate; + + if (*DataBits =3D=3D 0) { + LcrData =3D (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3); + *DataBits =3D LcrData + 5; + } else { + if ((*DataBits < 5) || (*DataBits > 8)) { + return RETURN_INVALID_PARAMETER; + } + // + // Map 5..8 to 0..3 + // + LcrData =3D (UINT8) (*DataBits - (UINT8) 5); + } + + if (*Parity =3D=3D DefaultParity) { + LcrParity =3D (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7); + switch (LcrParity) { + case 0: + *Parity =3D NoParity; + break; + + case 3: + *Parity =3D EvenParity; + break; + + case 1: + *Parity =3D OddParity; + break; + + case 7: + *Parity =3D SpaceParity; + break; + + case 5: + *Parity =3D MarkParity; + break; + + default: + break; + } + } else { + switch (*Parity) { + case NoParity: + LcrParity =3D 0; + break; + + case EvenParity: + LcrParity =3D 3; + break; + + case OddParity: + LcrParity =3D 1; + break; + + case SpaceParity: + LcrParity =3D 7; + break; + + case MarkParity: + LcrParity =3D 5; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + if (*StopBits =3D=3D DefaultStopBits) { + LcrStop =3D (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1); + switch (LcrStop) { + case 0: + *StopBits =3D OneStopBit; + break; + + case 1: + if (*DataBits =3D=3D 5) { + *StopBits =3D OneFiveStopBits; + } else { + *StopBits =3D TwoStopBits; + } + break; + + default: + break; + } + } else { + switch (*StopBits) { + case OneStopBit: + LcrStop =3D 0; + break; + + case OneFiveStopBits: + case TwoStopBits: + LcrStop =3D 1; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + // + // Calculate divisor for baud generator + // Ref_Clk_Rate / Baud_Rate / 16 + // + Divisor =3D PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16); + if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >=3D SerialB= audRate * 8) { + Divisor++; + } + + // + // Configure baud rate + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB= ); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (= Divisor >> 8)); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (D= ivisor & 0xff)); + + // + // Clear DLAB and configure Data Bits, Parity, and Stop Bits. + // Strip reserved bits from line control value + // + Lcr =3D (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData); + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & = 0x3F)); + + return RETURN_SUCCESS; + +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ser= ialPortLib.inf new file mode 100644 index 0000000000..df308e412e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/SerialPortLi= b.inf @@ -0,0 +1,55 @@ +## @file +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SerialPortLib + FILE_GUID =3D 15B26F43-A389-4bae-BDE3-4BB0719B7D4F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + EDK_RELEASE_VERSION =3D 0x00020000 + UEFI_SPECIFICATION_VERSION =3D 0x00020000 + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[Sources.common] + SerialPortLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + PcdLib + PciLib + IoLib + DebugLib + PlatformHooksLib + +[FixedPcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMET= IMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSU= MES + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/Set= CacheMtrrLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib= /SetCacheMtrrLib.c new file mode 100644 index 0000000000..b67dafd366 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/SetCacheMt= rrLib.c @@ -0,0 +1,867 @@ +/** @file + SetCacheMtrr library functions. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#define EFI_MAX_ADDRESS 0xFFFFFFFF + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance + /// + MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set + /// until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); + DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); + + /// + /// Assume size of main memory is multiple of 256MB + /// + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; + MemoryBase =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB + /// + if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer + /// + MtrrSetAllMtrrs (&MtrrSetting); + + return ; +} + +/** + + This function finds the start address and size of control or Block windo= w region in the system. + + @param Host - pointer to sysHost structure on stack + @param Memtype - Type of the memory range + @param RangeSize - pointer to the variable to store the StartAddress + @param RangeSize - pointer to the variable to store RangeSize + + @retval EFI_SUCCESS - success + EFI_NOT_FOUND - Region not found. + +**/ +EFI_STATUS +GetMemoryRegionRange( + struct SystemMemoryMapHob *systemMemoryMap, + UINT16 Memtype, + EFI_PHYSICAL_ADDRESS *StartAddress, + EFI_PHYSICAL_ADDRESS *RangeSize) +{ + UINT8 Index; + EFI_STATUS Status =3D EFI_NOT_FOUND; + UINT8 Socket =3D 0; + EFI_PHYSICAL_ADDRESS Limit =3D 0; + + *RangeSize =3D 0; + *StartAddress =3D 0; + + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + if (systemMemoryMap->Socket[Socket].SAD[0].Enable =3D=3D 0) { + continue; + } + + for (Index =3D 0; Index < MAX_SAD_RULES; Index++) { + if (systemMemoryMap->Socket[Socket].SAD[Index].Enable =3D=3D 0) { + continue; + } + if (systemMemoryMap->Socket[Socket].SAD[Index].type =3D=3D Memtype) { + if ((*StartAddress =3D=3D 0) && (Index > 0)) { + //Store the start address for the specified range in bytes + *StartAddress =3D (EFI_PHYSICAL_ADDRESS)MultU64x32 ((UINT64)syst= emMemoryMap->Socket[Socket].SAD[Index-1].Limit, CONVERT_64MB_TO_BYTE); + } + + if (MultU64x32((UINT64)systemMemoryMap->Socket[Socket].SAD[Index].= Limit, CONVERT_64MB_TO_BYTE) > Limit) { + //Store/Update the end address for the specified range in bytes = if greater than previous limit + Limit =3D (EFI_PHYSICAL_ADDRESS)MultU64x32 ((UINT64)systemMemory= Map->Socket[Socket].SAD[Index].Limit, CONVERT_64MB_TO_BYTE); + } + } + } + } + + if (Limit !=3D 0) { + *RangeSize =3D Limit - *StartAddress; + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + + MP programming MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN at socket level. + + @param PeiServices - Ptr of EFI_PEI_SERVICES ptr + @param mPeiMpServices - Ptr of EFI_PEI_MP_SERVICES_PPI + + @retval EFI_SUCCESS - Programming done + @retval EFI_UNSUPPORTED - Not support this platform + +**/ +EFI_STATUS +PkgMpEnableMcaOnCacheableMmio( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *mPeiMpServices +) +{ + UINT16 PackageDoneBitmap; + UINTN NumberOfProcessors; + UINTN NumberEnabledProcessors; + UINTN Index; + UINT8 TotalSockets =3D 0; + EFI_PROCESSOR_INFORMATION ProcInfo; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (!DynamicSiLibraryPpi->IsCpuAndRevision (CPU_SKX, REV_ALL) && !Dynami= cSiLibraryPpi->IsCpuAndRevision (CPU_CLX, REV_ALL) && !DynamicSiLibraryPpi-= >IsCpuAndRevision (CPU_CPX, REV_ALL)) { + return EFI_UNSUPPORTED; + } + + PackageDoneBitmap =3D 0; + mPeiMpServices->GetNumberOfProcessors( + PeiServices, + mPeiMpServices, + &NumberOfProcessors, + &NumberEnabledProcessors + ); + + // + // Find total number of sockets present on the board + // + for (Index =3D 0; Index < MAX_SOCKET; Index++) { + if (DynamicSiLibraryPpi->SocketPresent (Index)) { + TotalSockets++; + } + } + + // + // Loop through all the enabled processors and find one thread per socke= t present + // to write the MSR. Remote sockets need to use StartupThisAP. + // + for (Index =3D 0; Index < NumberOfProcessors; Index++) { + mPeiMpServices->GetProcessorInfo( + PeiServices, + mPeiMpServices, + Index, + &ProcInfo + ); + + if (!(PackageDoneBitmap & (1 << ProcInfo.Location.Package)) && (ProcIn= fo.StatusFlag & PROCESSOR_ENABLED_BIT)) { + + PackageDoneBitmap |=3D (1 << ProcInfo.Location.Package); + TotalSockets--; + + if (ProcInfo.StatusFlag & PROCESSOR_AS_BSP_BIT) { + DynamicSiLibraryPpi->EnableMcaOnCacheableMmio(); + } else { + Status =3D mPeiMpServices->StartupThisAP ( + PeiServices, + mPeiMpServices, + (EFI_AP_PROCEDURE)DynamicSiLibraryPpi->EnableMcaOnCa= cheableMmio, + Index, + 0, + NULL + ); + } + + // + // All sockets are programmed, skip checking rest of threads + // + if (TotalSockets =3D=3D 0) { + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + + Function to set all MTRRs on the current thread to the MTRR set passed i= n. + + @param MtrrSettings - Pointer to MTRR Settings to use + + @retval None + +**/ +VOID +SetAllMtrrs( + VOID *MtrrSettings +) +{ + MtrrSetAllMtrrs((MTRR_SETTINGS*)MtrrSettings); +} + +/** + + Function that analyzes memory length passed in to see if there is an + appropriate address to perform a more efficient top down coverage of + the memory range. At this address bit, it is more efficient to overshoot + memory range with WB cache type and cover the gap with UC cache type. + + @param MemoryLength - Memory length of entire memory region + + @retval Zero - No efficient top down approaches found. More = efficient + to cover memory range conventional way (bottom= up). + PwrOfTwo Value - PowerOfTwo bit where the top down approach is = most efficient + +**/ +UINT64 +FindTopDownPowerOfTwo ( + IN UINT64 MemoryLength + ) +{ + UINT8 Index; + BOOLEAN FoundOne =3D FALSE; + UINT8 ZeroCount =3D 0; + UINT8 OnesCount =3D 0; + UINT64 TopDownBit =3D 0; + UINT8 MtrrSavings =3D 0; + + for (Index =3D 0; Index < 64; Index++){ + if (MemoryLength & LShiftU64(1, Index)) { + OnesCount++; + FoundOne =3D TRUE; + } else { + // + // If there are more 1's than 0's plus 2 between least significant b= it set + // and current bit under test, then top down approach is more effici= ent. + // Continue to loop through memory length to look for more efficienc= ies + // and compare them against previous efficiencies found to pick best= power of two. + // + if (((ZeroCount + 2) < OnesCount) && ((OnesCount - (ZeroCount + 2)) = > MtrrSavings)) { + TopDownBit =3D LShiftU64(1, (Index - 1)); + MtrrSavings =3D OnesCount - (ZeroCount + 2); + } + if (FoundOne) { + ZeroCount++; + } + } + } + + // + // MtrrLib can handle this case efficiently + // + if (TopDownBit =3D=3D GetPowerOfTwo64(MemoryLength)) { + TopDownBit =3D 0; + } + + return TopDownBit; +} + +/** + + Recalculate the memory length to prevent MTRR out of resource error. + + @param MemoryLength - Memory Length that we want to truncate + + @retval UINT64 - New truncated memory length + +**/ +UINT64 +MemLengthRecalculation ( + IN UINT64 MemoryLength + ) +{ + UINT8 BitIndex; + + for (BitIndex =3D 0;BitIndex < 64; BitIndex++) { + if ((RShiftU64(MemoryLength, BitIndex) & 1) =3D=3D 1) { + // + // Clear lowest power of two bit found + // + MemoryLength &=3D ~LShiftU64(1, BitIndex); + break; + } + } + return MemoryLength; +} + +/** + + Sets the uncached part of upper memory as reserved to prevent OS from us= ing. + The uncached region will always be at the top of high memory. + + @param OriginalMemoryLength - Original top of memory value + @param NewMemoryLength - New memory range used for successful pr= ogramming + + @retval None + +**/ +VOID +ReserveUncachedMemory ( + IN UINT64 OriginalMemoryLength, + IN UINT64 NewMemoryLength + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceHob; + VOID *HobStart; + UINT64 TempLength; + + HobStart =3D GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + // + // Scan resource descriptor hobs to set our required range attribute as = tested + // + for (Hob.Raw =3D HobStart; !END_OF_HOB_LIST(Hob); Hob.Raw =3D GET_NEXT_H= OB(Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + ResourceHob =3D Hob.ResourceDescriptor; + if ((ResourceHob->PhysicalStart >=3D NewMemoryLength) && + ((ResourceHob->PhysicalStart + ResourceHob->ResourceLength) <=3D O= riginalMemoryLength)) { + // + // Range is completely included in the uncached area, mark as test= ed + // + ResourceHob->ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } else if ((ResourceHob->PhysicalStart < NewMemoryLength) && + (ResourceHob->PhysicalStart + ResourceHob->ResourceLength > NewMem= oryLength)) { + // + // Shrink previous HOB to base of uncached region, create new hob = to cover uncached space + // + TempLength =3D ResourceHob->ResourceLength; + ResourceHob->ResourceLength =3D NewMemoryLength - ResourceHob->Phy= sicalStart; + BuildResourceDescriptorHob( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ), + ResourceHob->PhysicalStart + ResourceHob->ResourceLength, + TempLength - ResourceHob->ResourceLength + ); + if ((ResourceHob->PhysicalStart + ResourceHob->ResourceLength + + (TempLength - ResourceHob->ResourceLength)) =3D=3D OriginalMemor= yLength) { + break; + } + } + if (ResourceHob->PhysicalStart + ResourceHob->ResourceLength =3D=3D = OriginalMemoryLength) { + break; + } + } + } + + HobStart =3D GetFirstHob (EFI_HOB_TYPE_MEMORY_ALLOCATION); + // + // Scan memory allocation hobs to make sure this range is free + // + for (Hob.Raw =3D HobStart; !END_OF_HOB_LIST(Hob); Hob.Raw =3D GET_NEXT_H= OB(Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_MEMORY_ALLOCATION) { + if ((Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress > NewMe= moryLength) && + (OriginalMemoryLength > Hob.MemoryAllocation->AllocDescriptor.Memo= ryBaseAddress)) { + // + // If hob range is above the range we want to reserve, set limit t= o that base. + // + OriginalMemoryLength =3D Hob.MemoryAllocation->AllocDescriptor.Mem= oryBaseAddress; + } else if ((Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress + + Hob.MemoryAllocation->AllocDescriptor.MemoryLength - 1) > NewMemor= yLength) { + // + // If there is a range allocated that starts below but comes into = the reserved range, + // adjust the base so it starts above previous allocation + // + NewMemoryLength =3D Hob.MemoryAllocation->AllocDescriptor.MemoryBa= seAddress + + Hob.MemoryAllocation->AllocDescriptor.MemoryLength; + } + } + } + + // + // Create hob to reserve the memory + // + if (NewMemoryLength < OriginalMemoryLength) { + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)NewMemoryLength, + OriginalMemoryLength - NewMemoryLength, + EfiReservedMemoryType + ); + } +} + +/** + Update MTRR setting in EndOfPei phase. + This function will clear temporary memory (CAR) phase MTRR settings + and configure MTRR to cover permanent memory. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 LowUncableBase; + UINT64 MemoryBase; + UINT64 TempQword; + UINT64 MemoryLength; + UINT64 TempMemoryLength; + UINT64 OriginalMemoryLength; + UINT64 TopDownBit; + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_INFO *PlatformInfo; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *IioUds; + MTRR_SETTINGS MtrrSettings; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GUID; + EFI_PEI_MP_SERVICES_PPI *mPeiMpServices =3D NULL; + EFI_BOOT_MODE BootMode; + CONST EFI_PEI_SERVICES ** PeiServices; + + + PeiServices =3D GetPeiServicesTablePointer(); + BootMode =3D GetBootModeHob(); + if (BootMode !=3D BOOT_ON_S3_RESUME) { + // + // Get required HOBs to be used to generate MTRR programming + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + if (GuidHob =3D=3D NULL) { + ASSERT(GuidHob !=3D NULL); + return EFI_NOT_FOUND; + } + IioUds =3D GET_GUID_HOB_DATA (GuidHob); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT(GuidHob !=3D NULL); + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + // + // Calculate the low uncacheable base address + // + if (IioUds->PlatformData.PciExpressBase < IioUds->PlatformData.PlatGlo= balMmio32Base) { + LowUncableBase =3D IioUds->PlatformData.PciExpressBase; + } else { + LowUncableBase =3D IioUds->PlatformData.PlatGlobalMmio32Base; + } + + LowUncableBase &=3D (0x0FFF00000); + + // + // Reset all Mtrrs to 0 including fixed MTRR and variable MTRR + // + ZeroMem(&MtrrSettings, sizeof(MTRR_SETTINGS)); + + // + // Set fixed cache for memory range below 1MB + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + 0, + 0xA0000, + EFI_CACHE_WRITEBACK + ); + ASSERT_EFI_ERROR(Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + 0xA0000, + 0x60000, + EFI_CACHE_UNCACHEABLE + ); + ASSERT_EFI_ERROR(Status); + + // + // Base set to 1mb due to MtrrLib programming method + // + MemoryBase =3D BASE_1MB; + MemoryLength =3D LowUncableBase; + + Status =3D (*PeiServices)->GetHobList (PeiServices, &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYST= EM_MEMORY) || + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMO= RY_MAPPED_IO && + (Hob.ResourceDescriptor->ResourceAttribute & EFI_RESOURCE_ATTR= IBUTE_WRITE_BACK_CACHEABLE)) || + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMO= RY_RESERVED && + (Hob.ResourceDescriptor->ResourceAttribute & EFI_RESOURCE_ATT= RIBUTE_WRITE_BACK_CACHEABLE))) { + if (Hob.ResourceDescriptor->PhysicalStart > EFI_MAX_ADDRESS) { + TempQword =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Reso= urceDescriptor->ResourceLength; + if (TempQword > MemoryLength) { + MemoryLength =3D TempQword; + } + } + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + TempMemoryLength =3D MemoryLength; + OriginalMemoryLength =3D MemoryLength; + + DEBUG((DEBUG_ERROR, "Total Memory size: 0x%lx\n", MemoryLength)); + + Status =3D EFI_SUCCESS; + // + // Loop will continue until MTRR programming is successfully done. + // All regions reserved in this loop are considered essential regions + // If any of them fail to fit, memory is truncated by lowest power of + // two until all regions fit into the programming + // + do { + if (Status =3D=3D RETURN_OUT_OF_RESOURCES){ + // + // Ran out of MTRRs: lower top of high memory by lowest power of t= wo bit and retry + // + MemoryLength =3D MemLengthRecalculation (TempMemoryLength); + DEBUG((DEBUG_ERROR, "MTRR: %r, attempting: 0x%lx\n", Status, Memor= yLength)); + // + // Restore the MemoryBase to its original value, save MemoryLength + // + MemoryBase =3D BASE_1MB; + TempMemoryLength =3D MemoryLength; + ZeroMem(&(MtrrSettings.Variables), sizeof(MTRR_VARIABLE_SETTINGS)); + } + + TopDownBit =3D FindTopDownPowerOfTwo(MemoryLength); + + // + // If TopDownBit has a value, then we found a more efficient address= length + // to use a top down approach. We will walk through the full addres= s length to + // program MTRRs individually. BASE_1MB fixups are due to MtrrLib p= rogram method. + // + if(TopDownBit){ + DEBUG((DEBUG_INFO, "Efficient Top Down Power of Two =3D %lx\n\n", = TopDownBit)); + while (MemoryLength !=3D 0) { + if (GetPowerOfTwo64(MemoryLength) =3D=3D TopDownBit) { + // + // Overshoot address with WB and cover remaining gap with UC + // + TempQword =3D MemoryLength; + MemoryLength =3D LShiftU64(GetPowerOfTwo64 (MemoryLength), 1); + + if(MemoryBase =3D=3D BASE_1MB) { + MemoryLength -=3D BASE_1MB; + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + if(MemoryBase =3D=3D BASE_1MB) { + MemoryBase =3D 0; + MemoryLength +=3D BASE_1MB; + } + + MemoryBase +=3D TempQword; + MemoryLength -=3D TempQword; + + // + // Program UC region gap between top of memory and WB MTRR + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength, + EFI_CACHE_UNCACHEABLE + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + MemoryLength =3D 0; + } else { + // + // Grow next power of two upwards and adjust base and length + // + TempQword =3D GetPowerOfTwo64(MemoryLength); + MemoryLength -=3D TempQword; + + if(MemoryBase =3D=3D BASE_1MB) { + TempQword -=3D BASE_1MB; + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + TempQword, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + MemoryBase +=3D TempQword; + } + } + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + } else { + // + // Create a WB region for the entire memory region + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength - BASE_1MB, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + } + + // + // Punch UC hole for lower MMIO region + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + LowUncableBase, + EFI_MAX_ADDRESS - LowUncableBase + 1, + EFI_CACHE_UNCACHEABLE + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + + } while (Status =3D=3D RETURN_OUT_OF_RESOURCES); + // + // Assert if there was an error other than resource issue + // + ASSERT_EFI_ERROR (Status); + + // + // Set PSMI Trace Region to uncached + // + if (PlatformInfo->MemData.PsmiUcTraceRegionSize !=3D 0) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + PlatformInfo->MemData.PsmiUcTraceRegionBase, + PlatformInfo->MemData.PsmiUcTraceRegionSize, + EFI_CACHE_UNCACHEABLE + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "PSMI- Could not set Trace Region MemType to U= C\n")); + } + } + + // + // Set the calculated MTRR settings for the BSP + // + MtrrSetAllMtrrs (&MtrrSettings); + + // + // Need to mark the uncached memory as reserved + // + if (OriginalMemoryLength > TempMemoryLength) { + DEBUG((DEBUG_ERROR, "New TOHM: 0x%lx, Previous: 0x%lx\n", TempMemory= Length, OriginalMemoryLength)); + ReserveUncachedMemory (OriginalMemoryLength, TempMemoryLength); + } + } + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiMpServicesPpiGuid, + 0, + NULL, + &mPeiMpServices + ); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + if(!EFI_ERROR(Status)){ + // + // Sync all AP MTRRs with BSP + // + Status =3D mPeiMpServices->StartupAllAPs ( + PeiServices, + mPeiMpServices, + (EFI_AP_PROCEDURE)SetAllMtrrs, + FALSE, + 0, + (VOID*)&MtrrSettings + ); + } + } + + PkgMpEnableMcaOnCacheableMmio (PeiServices, mPeiMpServices); + + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/Set= CacheMtrrLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrL= ib/SetCacheMtrrLib.inf new file mode 100644 index 0000000000..6f21d1ea72 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/SetCacheMt= rrLib.inf @@ -0,0 +1,55 @@ +## @file +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 7E5407A1-0058-4617-AAEC-ACB0F74B4A1F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib|PEIM + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + HobLib + MtrrLib + PeiServicesLib + BaseMemoryLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + gEfiPlatformInfoGuid ## CONSUMES + +[Ppis] + gEfiPeiMpServicesPpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/PchPolicyUpdateUsb.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Silic= onPolicyUpdateLib/PchPolicyUpdateUsb.c new file mode 100644 index 0000000000..c4c5d9aaba --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Pch= PolicyUpdateUsb.c @@ -0,0 +1,152 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// EDK and EDKII have different GUID formats +// +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ) +/*++ + +Routine Description: + + This function performs PCH USB Platform Policy initialzation + +Arguments: + PchUsbConfig Pointer to PCH_USB_CONFIG data buffer + SetupVariables Pointer to Setup variable + PlatformType PlatformType specified + PlatformFlavor PlatformFlavor specified + BoardType BoardType specified + +Returns: + +--*/ +{ + UINTN PortIndex; +#ifdef TESTMENU_FLAG + UINT8 Index; +#endif + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + PchUsbConfig->UsbPrecondition =3D PchRcVariables->UsbPrecondition; + + for (PortIndex =3D 0; PortIndex < DynamicSiLibraryPpi->GetPchXhciMaxUs= b2PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbHsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D FALSE; + } + } + for (PortIndex =3D 0; PortIndex < DynamicSiLibraryPpi->GetPchXhciMaxUs= b3PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbSsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D FALSE; + } + } + + for (PortIndex =3D 0; PortIndex < PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS; Po= rtIndex++) { + PchUsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Petxiset); + PchUsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Txiset); + PchUsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Predeemp); + PchUsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Pehalfbit); + } + + // + // xDCI (USB device) related settings from setup variable + // + if(PchRcVariables->PchXdciSupport =3D=3D 1) { + PchUsbConfig->XdciConfig.Enable=3D TRUE; + } else { + PchUsbConfig->XdciConfig.Enable=3D FALSE; + } + +#ifdef TESTMENU_FLAG + // + // Need to clear UsbEPTypeLockPolicy[8] and UsbEPTypeLockPolicy[16] sinc= e this is not assign in the setup + // + PchRcVariables->UsbEPTypeLockPolicy[8] =3D 0; + SetupPchRcVariablesVariables->UsbEPTypeLockPolicy[16] =3D 0; + + // + // Update USB EP Type Lock Policy Settings + // + for (Index =3D 0; Index < 24; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicy |=3D (UI= NT32) (PchRcVariables->UsbEPTypeLockPolicy[Index] << Index); + } + + for (Index =3D 0; Index < 16; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicyPortContr= ol1 |=3D (UINT32) (PchRcVariables->RootPortPolicyControl[Index] << Index *= 2); + } + + for (Index =3D 16; Index < 20; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicyPortContr= ol2 |=3D (UINT32) (PchRcVariables->RootPortPolicyControl[Index] << (Index = - 16) * 2); + } + + // + // Remark: Can be disabled only for debugging process!!! + // + PchUsbConfig->TstMnuControllerEnabled =3D PchRcVariables->XhciEnabled; + // + // SSIC debug mode + // + PchUsbConfig->TstMnuSsicHalt =3D PchRcVariables->XhciSsicHalt; +#endif + // + // XHCI USB Over Current Pins disabled, update it based on setup option. + // + PchUsbConfig->XhciOcMapEnabled =3D PchRcVariables->XhciOcMapEnabled; + + // + // XHCI Wake On USB configured based on user input through setup option + // + PchUsbConfig->XhciWakeOnUsb =3D SetupVariables->XhciWakeOnUsbEnabled; + // + // XHCI option to disable MSIs + // + PchUsbConfig->XhciDisMSICapability =3D PchRcVariables->XhciDisMSICapabil= ity; + + // + // Platform Board programming per the layout of each port. + // + // OC Map for USB2 Ports + for (PortIndex=3D0;PortIndexPortUsb20[PortIndex].OverCurrentPin =3D (UINT8)((USB_OVE= RCURRENT_PIN *)Usb20OverCurrentMappings)[PortIndex]; + } + + // OC Map for USB3 Ports + for (PortIndex=3D0;PortIndexPortUsb30[PortIndex].OverCurrentPin =3D (UINT8)((USB_OVE= RCURRENT_PIN *)Usb30OverCurrentMappings)[PortIndex]; + } + +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/S= iliconPolicyUpdateLib/SiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..25a27eee39 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.c @@ -0,0 +1,778 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialz= ation. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +STATIC +EFI_STATUS +InstallPcieDeviceTable ( + IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable + ) +{ + EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc; + EFI_STATUS Status; + + DeviceTablePpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (size= of (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (DeviceTablePpiDesc !=3D NULL); + + if (DeviceTablePpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + DeviceTablePpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_D= ESCRIPTOR_TERMINATE_LIST; + DeviceTablePpiDesc->Guid =3D &gPchPcieDeviceTablePpiGuid; + DeviceTablePpiDesc->Ppi =3D DeviceTable; + + Status =3D PeiServicesInstallPpi (DeviceTablePpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the d= river + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 BmcRootPort; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + USB_OVERCURRENT_PIN *Usb20OverCurrentMappings =3D NULL; + USB_OVERCURRENT_PIN *Usb30OverCurrentMappings =3D NULL; + USB2_PHY_PARAMETERS *Usb20AfeParams =3D NULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_SETUP *PchRcVariables; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + SetupVariables =3D PcdGetPtr(PcdSetup); + PchRcVariables =3D PcdGetPtr(PcdPchSetup); + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route =3D PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable =3D TRUE; + PchPolicy->LanConfig.K1OffEnable =3D PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable =3D FALSE; + } + + PchPolicy->SataConfig.Enable =3D PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable =3D PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable =3D TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun =3D FALSE; + PchPolicy->PchConfig.Crid =3D PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm =3D PchRcVariables->PchSerm; + + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + PchPolicy->SmbusConfig.SmbusIoBase =3D PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode =3D PchRcVariables->SataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode =3D=3D TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D PchRcVariables-= >SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug =3D PchRcVa= riables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp =3D PchRcVa= riables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External =3D PchRcVa= riables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].InterlockSw =3D PchRcVa= riables->SataMechanicalSw[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp =3D PchRcVa= riables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcVa= riables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal =3D PchRcVa= riables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal =3D PchRcVa= riables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive =3D PchRcVa= riables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId =3D PchRcVariables->SataAlte= rnateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataRa= idLoadEfiDriver[0]; + } + PchPolicy->SataConfig.Rst.Raid0 =3D PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 =3D PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 =3D PchRcVariables->SataRaidR1= 0; + PchPolicy->SataConfig.Rst.Raid5 =3D PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt =3D PchRcVariables->SataRaidIr= rt; + PchPolicy->SataConfig.Rst.OromUiBanner =3D PchRcVariables->SataRaidOu= b; + PchPolicy->SataConfig.Rst.HddUnlock =3D PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate =3D PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly =3D PchRcVariables->SataRaidIo= oe; + PchPolicy->SataConfig.Rst.SmartStorage =3D PchRcVariables->SataRaidSr= t; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchRcVariables->SataRaidOr= omDelay; + + PchPolicy->SataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->SataConfig.SalpSupport =3D PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode =3D PchRcVariables->SataTestMode; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata =3D=3D TRUE) && (PchRcVariables->SataInte= rfaceMode =3D=3D PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = =3D PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode =3D PchRcVariables->sSataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxsSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode =3D=3D TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D PchRcVariables= ->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug =3D PchRcV= ariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp =3D PchRcV= ariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External =3D PchRcV= ariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp =3D PchRcV= ariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcV= ariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal =3D PchRcV= ariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal =3D PchRcV= ariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive =3D PchRcV= ariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId =3D PchRcVariables->sSataAl= ternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataR= aidLoadEfiDriver[1]; + } + PchPolicy->sSataConfig.Rst.Raid0 =3D PchRcVariables->sSataRaid= R0; + PchPolicy->sSataConfig.Rst.Raid1 =3D PchRcVariables->sSataRaid= R1; + PchPolicy->sSataConfig.Rst.Raid10 =3D PchRcVariables->sSataRaid= R10; + PchPolicy->sSataConfig.Rst.Raid5 =3D PchRcVariables->sSataRaid= R5; + PchPolicy->sSataConfig.Rst.Irrt =3D PchRcVariables->sSataRaid= Irrt; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D PchRcVariables->sSataRaid= Oub; + PchPolicy->sSataConfig.Rst.HddUnlock =3D PchRcVariables->sSataHddl= k; + PchPolicy->sSataConfig.Rst.LedLocate =3D PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D PchRcVariables->sSataRaid= Iooe; + PchPolicy->sSataConfig.Rst.SmartStorage =3D PchRcVariables->sSataRaid= Srt; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchRcVariables->sSataRaid= OromDelay; + + PchPolicy->sSataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->sSataConfig.SalpSupport =3D PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode =3D PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm !=3D PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm !=3D 0xFF) { + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm =3D FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =3D%x\n", PchPolicy->D= miConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating =3D SetupVariables= ->PcieClockGatingDisabled; + PchPolicy->PcieConfig.EnablePort8xhDecode =3D PchRcVariables->= PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex =3D PchRcVariables->= Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite =3D PchRcVariables->= PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode =3D PchRcVariables->= PcieComplianceTestMode; + + /// + /// Temporary WA: Force Link speed on BMC board to GEN1 + /// TODO: remove this WA together with Purley platforms support + /// + BmcRootPort =3D PcdGet8 (PcdOemSkuBmcPciePortNumber); + if ((BmcRootPort !=3D 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables-= >PcieRootPortSpeed))) { + DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRo= otPort)); + PchRcVariables->PcieRootPortSpeed[BmcRootPort] =3D 1; + } + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = =3D PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = =3D (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = =3D PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = =3D PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = =3D PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = =3D PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = =3D PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = =3D PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = =3D PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = =3D PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = =3D PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = =3D PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = =3D PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = =3D PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = =3D PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = =3D PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = =3D PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = =3D PchRcVariables->PcieRootPortEqPh3Method[Index]; + PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = =3D TRUE; + } + PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = =3D FALSE; + + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D PchRcVariables->Pc= ieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D PchRcVariables->Pc= ieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm =3D PchRcVariable= s->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp =3D PchRcVariable= s->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = =3D PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = =3D PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = =3D PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = =3D PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = =3D PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF= (SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = =3D VTdSupport; + if (DynamicSiLibraryPpi->X2ApicIdDetect (NULL)) { + PchPolicy->PcieConfig.VTdSupport =3D TRUE; + } + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable =3D PchRcVariables->PchHdA= udio; + PchPolicy->HdAudioConfig.DspEnable =3D FALSE; + PchPolicy->HdAudioConfig.Pme =3D PchRcVariables->PchHdA= udioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership =3D PchRcVariables->PchHdA= udioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage =3D PchRcVariables->PchHdA= udioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect =3D TRUE; //iDisp is perm= anently disabled + for(Index =3D 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |=3D (UINT32)(PchRcVariables->= PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index =3D 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |=3D (UINT32)(PchRcVariables-= >PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType =3D PchRcVariables->DfxHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock =3D PchRcVariables->PchRtcLoc= k; + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.GpioLockDown =3D PchRcVariables->PchGpioLo= ckDown; + PchPolicy->LockDownConfig.TcoLock =3D TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock =3D TRUE; + PchPolicy->P2sbConfig.PsfUnlock =3D TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock =3D FALSE; + PchPolicy->P2sbConfig.PsfUnlock =3D FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal =3D PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + + PchPolicy->PmConfig.PmcReadDisable =3D TRUE; + + if (PchRcVariables->PchAdrEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn =3D PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel =3D PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset =3D PchRcVariables->AdrHost= PartitionReset; + } + if (PchRcVariables->AdrTimerEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn =3D PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal !=3D ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal =3D PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal !=3D ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal =3D PchRcVariables->AdrMultiplie= rVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement !=3D FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard !=3D FALSE) || (PchRcVariables->= ExttsViaTsOnDimm !=3D FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pi= nSelection =3D 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pi= nSelection =3D 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable =3D FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D PchRcVariables->PchIoApic2= 4119Entries; + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_IOAPIC; + PchPolicy->IoApicConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_IOAP= IC; + PchPolicy->IoApicConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_IO= APIC; + + PchPolicy->HpetConfig.BdfValid =3D 1; + PchPolicy->HpetConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_HPET; + PchPolicy->HpetConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_HPET; + PchPolicy->HpetConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_HPET= 0; + + PchPolicy->PchInterruptConfig.ShutdownPolicySelect =3D PchRcVaria= bles->ShutdownPolicySelect; + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol =3D PchRcVaria= bles->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D PchRcVaria= bles->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable =3D PchRcVaria= bles->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable =3D PchRcVaria= bles->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx =3D PchRcVaria= bles->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc =3D PchRcVaria= bles->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D PchRcVaria= bles->PciePllSsc; + PchPolicy->PmConfig.Dwr_BmcRootPort =3D PchRcVaria= bles->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL =3D PchRcVaria= bles->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT =3D PchRcVaria= bles->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT =3D PchRcVaria= bles->DwrEn_IEWDT; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec =3D PchRcVariables->EnableCl= ockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + if (PchRcVariables->ThermalDeviceEnable =3D=3D PchThermalDeviceAuto) { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceEnabl= edPci; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchRcVariables->Therm= alDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = =3D TRUE; + + /// + ///Set PCHHOT# to 85C. + /// + PchPolicy->ThermalConfig.PchHotLevel =3D 0x10E; + + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn =3D DCI_DISABLE; + PchPolicy->DciConfig.DciAutoDetect =3D DCI_DISABLE; + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + if (PchRcVariables->PchSirqMode =3D=3D 0) { + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode =3D PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass =3D PchRcVariables->DmiLinkDo= wnHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D PchRcVariables->PcieDmiS= topAndScreamEnable; + + // + // Update Pch Usb Config + // + PlatformGetUsbOcMappings ( + (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings, + (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings, + (USB2_PHY_PARAMETERS **) &Usb20AfeParams + ); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + + // + // Install PCIe device override table + // + InstallPcieDeviceTable (mPcieDeviceTable); + + // + // Initialize PTSS board specyfic HSIO settings + // + InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy); + + + PchPolicy->PchTraceHubConfig.PchTraceHubHide =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library= /SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..5c9d1a5a06 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.inf @@ -0,0 +1,64 @@ +## @file +# Module Infomation file +# +# @copyright +# Copyright 2011 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLib.c + PchPolicyUpdateUsb.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + HobLib + IoLib + PcdLib + UbaPlatLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + +[Guids] + gEfiAcpiVariableGuid + +[Ppis] + gPchPcieDeviceTablePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLibFsp.c b/Platform/Intel/WhitleyOpenBoardPkg/Librar= y/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c new file mode 100644 index 0000000000..f9fa6dfe64 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.c @@ -0,0 +1,770 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialz= ation. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +STATIC +EFI_STATUS +InstallPcieDeviceTable ( + IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable + ) +{ + EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc; + EFI_STATUS Status; + + DeviceTablePpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (size= of (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (DeviceTablePpiDesc !=3D NULL); + + if (DeviceTablePpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + DeviceTablePpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_D= ESCRIPTOR_TERMINATE_LIST; + DeviceTablePpiDesc->Guid =3D &gPchPcieDeviceTablePpiGuid; + DeviceTablePpiDesc->Ppi =3D DeviceTable; + + Status =3D PeiServicesInstallPpi (DeviceTablePpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the d= river + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 BmcRootPort; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + USB_OVERCURRENT_PIN *Usb20OverCurrentMappings=3DNULL; + USB_OVERCURRENT_PIN *Usb30OverCurrentMappings=3DNULL; + USB2_PHY_PARAMETERS *Usb20AfeParams =3D NULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_SETUP *PchRcVariables; + FSPM_UPD *FspmUpd; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + FspmUpd =3D (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress); + ASSERT (FspmUpd !=3D NULL); + SetupVariables =3D PcdGetPtr(PcdSetup); + PchRcVariables =3D PcdGetPtr(PcdPchSetup); + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route =3D PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable =3D TRUE; + PchPolicy->LanConfig.K1OffEnable =3D PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable =3D FALSE; + } + + PchPolicy->SataConfig.Enable =3D PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable =3D PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable =3D TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun =3D FALSE; + PchPolicy->PchConfig.Crid =3D PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm =3D PchRcVariables->PchSerm; + + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + PchPolicy->SmbusConfig.SmbusIoBase =3D PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode =3D PchRcVariables->SataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode =3D=3D TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D PchRcVariables-= >SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug =3D PchRcVa= riables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp =3D PchRcVa= riables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External =3D PchRcVa= riables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp =3D PchRcVa= riables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcVa= riables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal =3D PchRcVa= riables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal =3D PchRcVa= riables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive =3D PchRcVa= riables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId =3D PchRcVariables->SataAlte= rnateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataRa= idLoadEfiDriver[0]; + } + PchPolicy->SataConfig.Rst.Raid0 =3D PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 =3D PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 =3D PchRcVariables->SataRaidR1= 0; + PchPolicy->SataConfig.Rst.Raid5 =3D PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt =3D PchRcVariables->SataRaidIr= rt; + PchPolicy->SataConfig.Rst.OromUiBanner =3D PchRcVariables->SataRaidOu= b; + PchPolicy->SataConfig.Rst.HddUnlock =3D PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate =3D PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly =3D PchRcVariables->SataRaidIo= oe; + PchPolicy->SataConfig.Rst.SmartStorage =3D PchRcVariables->SataRaidSr= t; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchRcVariables->SataRaidOr= omDelay; + + PchPolicy->SataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->SataConfig.SalpSupport =3D PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode =3D PchRcVariables->SataTestMode; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata =3D=3D TRUE) && (PchRcVariables->SataInte= rfaceMode =3D=3D PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = =3D PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode =3D PchRcVariables->sSataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxsSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode =3D=3D TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D PchRcVariables= ->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug =3D PchRcV= ariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp =3D PchRcV= ariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External =3D PchRcV= ariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp =3D PchRcV= ariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcV= ariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal =3D PchRcV= ariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal =3D PchRcV= ariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive =3D PchRcV= ariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId =3D PchRcVariables->sSataAl= ternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataR= aidLoadEfiDriver[0];; + } + PchPolicy->sSataConfig.Rst.Raid0 =3D PchRcVariables->sSataRaid= R0; + PchPolicy->sSataConfig.Rst.Raid1 =3D PchRcVariables->sSataRaid= R1; + PchPolicy->sSataConfig.Rst.Raid10 =3D PchRcVariables->sSataRaid= R10; + PchPolicy->sSataConfig.Rst.Raid5 =3D PchRcVariables->sSataRaid= R5; + PchPolicy->sSataConfig.Rst.Irrt =3D PchRcVariables->sSataRaid= Irrt; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D PchRcVariables->sSataRaid= Oub; + PchPolicy->sSataConfig.Rst.HddUnlock =3D PchRcVariables->sSataHddl= k; + PchPolicy->sSataConfig.Rst.LedLocate =3D PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D PchRcVariables->sSataRaid= Iooe; + PchPolicy->sSataConfig.Rst.SmartStorage =3D PchRcVariables->sSataRaid= Srt; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchRcVariables->sSataRaid= OromDelay; + + PchPolicy->sSataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->sSataConfig.SalpSupport =3D PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode =3D PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm !=3D PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm !=3D 0xFF) { + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm =3D FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =3D%x\n", PchPolicy->D= miConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating =3D SetupVariables= ->PcieClockGatingDisabled; + PchPolicy->PcieConfig.EnablePort8xhDecode =3D PchRcVariables->= PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex =3D PchRcVariables->= Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite =3D PchRcVariables->= PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode =3D PchRcVariables->= PcieComplianceTestMode; + + /// + /// Temporary WA: Force Link speed on BMC board to GEN1 + /// TODO: remove this WA together with Purley platforms support + /// + BmcRootPort =3D PcdGet8(PcdOemSkuBmcPciePortNumber); + if ((BmcRootPort !=3D 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables-= >PcieRootPortSpeed))) { + DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRo= otPort)); + PchRcVariables->PcieRootPortSpeed[BmcRootPort] =3D 1; + } + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = =3D PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = =3D (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = =3D PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = =3D PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = =3D PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = =3D PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = =3D PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = =3D PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = =3D PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = =3D PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = =3D PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = =3D PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = =3D PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = =3D PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = =3D PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = =3D PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = =3D PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = =3D PchRcVariables->PcieRootPortEqPh3Method[Index]; + PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = =3D TRUE; + } + PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = =3D FALSE; + + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D PchRcVariables->Pc= ieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D PchRcVariables->Pc= ieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm =3D PchRcVariable= s->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp =3D PchRcVariable= s->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = =3D PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = =3D PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = =3D PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = =3D PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = =3D PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF= (SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = =3D VTdSupport; + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable =3D PchRcVariables->PchHdA= udio; + PchPolicy->HdAudioConfig.DspEnable =3D FALSE; + PchPolicy->HdAudioConfig.Pme =3D PchRcVariables->PchHdA= udioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership =3D PchRcVariables->PchHdA= udioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage =3D PchRcVariables->PchHdA= udioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect =3D TRUE; //iDisp is perm= anently disabled + for(Index =3D 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |=3D (UINT32)(PchRcVariables->= PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index =3D 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |=3D (UINT32)(PchRcVariables-= >PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType =3D PchRcVariables->DfxHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock =3D PchRcVariables->PchRtcL= ock; + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.GpioLockDown =3D PchRcVariables->PchGpio= LockDown; + PchPolicy->LockDownConfig.TcoLock =3D TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock =3D TRUE; + PchPolicy->P2sbConfig.PsfUnlock =3D TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock =3D FALSE; + PchPolicy->P2sbConfig.PsfUnlock =3D FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal =3D PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + + PchPolicy->PmConfig.PmcReadDisable =3D TRUE; + + if (PchRcVariables->PchAdrEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn =3D PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel =3D PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset =3D PchRcVariables->AdrHost= PartitionReset; + } + if (PchRcVariables->AdrTimerEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn =3D PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal !=3D ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal =3D PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal !=3D ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal =3D PchRcVariables->AdrMultiplie= rVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement !=3D FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard !=3D FALSE) || (PchRcVariables->= ExttsViaTsOnDimm !=3D FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pi= nSelection =3D 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pi= nSelection =3D 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable =3D FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D PchRcVariables->PchIoApic2= 4119Entries; + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_IOAPIC; + PchPolicy->IoApicConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_IOAP= IC; + PchPolicy->IoApicConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_IO= APIC; + + + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol =3D PchRcVaria= bles->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D PchRcVaria= bles->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable =3D PchRcVaria= bles->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable =3D PchRcVaria= bles->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx =3D PchRcVaria= bles->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc =3D PchRcVaria= bles->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D PchRcVaria= bles->PciePllSsc; + PchPolicy->PmConfig.Dwr_BmcRootPort =3D PchRcVaria= bles->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL =3D PchRcVaria= bles->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT =3D PchRcVaria= bles->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT =3D PchRcVaria= bles->DwrEn_IEWDT; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec =3D PchRcVariables->EnableCl= ockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + if (PchRcVariables->ThermalDeviceEnable =3D=3D PchThermalDeviceAuto) { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceEnabl= edPci; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchRcVariables->Therm= alDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = =3D TRUE; + + // + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn =3D DCI_DISABLE; + PchPolicy->DciConfig.DciAutoDetect =3D DCI_DISABLE; + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + if (PchRcVariables->PchSirqMode =3D=3D 0) { + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode =3D PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass =3D PchRcVariables->DmiLinkDo= wnHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D PchRcVariables->PcieDmiS= topAndScreamEnable; + + // + // Update Pch Usb Config + // + PlatformGetUsbOcMappings ( + (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings, + (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings, + (USB2_PHY_PARAMETERS **) &Usb20AfeParams + ); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + + // + // Install PCIe device override table + // + InstallPcieDeviceTable (mPcieDeviceTable); + + // + // Initialize PTSS board specyfic HSIO settings + // + InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy); + + + PchPolicy->PchTraceHubConfig.PchTraceHubHide =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLibFsp.inf b/Platform/Intel/WhitleyOpenBoardPkg/Libr= ary/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..344374a85f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.inf @@ -0,0 +1,68 @@ +## @file +# Module Infomation file +# +# @copyright +# Copyright 2011 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLibFsp.c + PchPolicyUpdateUsb.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec + +[LibraryClasses] + HobLib + IoLib + PcdLib + UbaPlatLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES + +[Guids] + gEfiAcpiVariableGuid + +[Ppis] + gPchPcieDeviceTablePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Smm= SpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..a5bcb5e2f2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSp= iFlashCommonLib.inf @@ -0,0 +1,57 @@ +## @file +# SMM Library instance of Spi Flash Common Library Class +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + PciLib + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + gDynamicSiLibrarySmmProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid AND + gEfiSmmSwDispatch2ProtocolGuid AND + gDynamicSiLibrarySmmProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SpiFlashCommon.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlash= CommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..d28b453580 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFl= ashCommon.c @@ -0,0 +1,237 @@ +/** @file + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces + for module use. + + @copyright + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// FlashAreaBaseAddress and Size for boottime and runtime usage. +// +UINTN mFlashAreaBaseAddress =3D 0; +UINTN mFlashAreaSize =3D 0; + +/** + This function enable SPI.MSE(Memory Space Enable) Bit1 if it is disabled. + in some cases, the SPI.MSE will be disabled. For example, it is disabled= under PCI bus initialization. + + @param None. + + @retval None. + +**/ +VOID +SpiMemorySpaceCheckandEnable( + VOID + ) +{ + UINTN SpiMemAddress; + UINT32 SpiCmdData; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_SMM_PROTOCOL *DynamicSiLibrarySmmProtocol =3D NULL; + + Status =3D gSmst->SmmLocateProtocol (&gDynamicSiLibrarySmmProtocolGuid, = NULL, &DynamicSiLibrarySmmProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + SpiMemAddress =3D DynamicSiLibrarySmmProtocol->MmPciBase ( DEFAULT_PCI_B= US_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI); + + SpiCmdData =3D MmioRead32 (SpiMemAddress + PCI_COMMAND_OFFSET); + + if (!(SpiCmdData & BIT1)) { //Bit1: Memory Space Enable + SpiCmdData |=3D BIT1; + MmioWrite32(SpiMemAddress + PCI_COMMAND_OFFSET, SpiCmdData); + } + +} + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + SpiMemorySpaceCheckandEnable(); + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + SpiMemorySpaceCheckandEnable(); + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SpiFlashCommonSmmLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSp= iFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..de0b762f00 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFl= ashCommonSmmLib.c @@ -0,0 +1,55 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mFlashAreaBaseAddress; +extern UINTN mFlashAreaSize; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mFlashAreaBaseAddress =3D (UINTN)PcdGet32 (PcdFlashAreaBaseAddress); + mFlashAreaSize =3D (UINTN)PcdGet32 (PcdFlashAreaSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenc= eLibNull/DxeTcg2PhysicalPresenceLib.c b/Platform/Intel/WhitleyOpenBoardPkg/= Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.c new file mode 100644 index 0000000000..7eb37e232e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenceLibNul= l/DxeTcg2PhysicalPresenceLib.c @@ -0,0 +1,41 @@ +/** @file + NULL Tcg2PhysicalPresenceLib library instance + + @copyright + Copyright (c) 2018, Red Hat, Inc. + Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Check if the pending TPM request needs user input to confirm. + + The TPM request may come from OS. This API will check if TPM request exi= sts and need user + input to confirmation. + + @retval TRUE TPM needs input to confirm user physical presence. + @retval FALSE TPM doesn't need input to confirm user physical p= resence. + +**/ +BOOLEAN +EFIAPI +Tcg2PhysicalPresenceLibNeedUserConfirm ( + VOID + ) +{ + return FALSE; +} + +VOID +EFIAPI +Tcg2PhysicalPresenceLibProcessRequest ( + IN TPM2B_AUTH *PlatformAuth OPTIONAL + ) +{ + // + // do nothing + // +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenc= eLibNull/DxeTcg2PhysicalPresenceLib.inf b/Platform/Intel/WhitleyOpenBoardPk= g/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf new file mode 100644 index 0000000000..618917d2ff --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenceLibNul= l/DxeTcg2PhysicalPresenceLib.inf @@ -0,0 +1,29 @@ +## @file +# NULL Tcg2PhysicalPresenceLib library instance +# +# Under SecurityPkg, the corresponding library instance will check and +# execute TPM 2.0 request from OS or BIOS; the request may ask for user +# confirmation before execution. This Null instance implements a no-op +# Tcg2PhysicalPresenceLibProcessRequest(), without user interaction. +# +# @copyright +# Copyright (C) 2018, Red Hat, Inc. +# Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeTcg2PhysicalPresenceLibNull + FILE_GUID =3D 2A6BA243-DC22-42D8-9C3D-AE3728DC7AFA + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D Tcg2PhysicalPresenceLib|DXE_DRIVER DX= E_RUNTIME_DRIVER UEFI_APPLICATION UEFI_DRIVER + +[Sources] + DxeTcg2PhysicalPresenceLib.c + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaG= pioInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/Ub= aGpioInitLib.c new file mode 100644 index 0000000000..3fdcf2e18f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaGpioInit= Lib.c @@ -0,0 +1,145 @@ +/** @file + UbaGpioInitLib implementation. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static GPIO_INIT_CONFIG meSPIConfig[] =3D +{ + { GPIO_SKL_H_GPP_A0, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLo= ck } },//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + { GPIO_SKL_H_GPP_A1, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_1_LAD_0_ESPI_IO_0 + { GPIO_SKL_H_GPP_A2, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_2_LAD_1_ESPI_IO_1 + { GPIO_SKL_H_GPP_A3, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_3_LAD_2_ESPI_IO_2 + { GPIO_SKL_H_GPP_A4, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_4_LAD_3_ESPI_IO_3 + { GPIO_SKL_H_GPP_A5, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfi= gLock } },//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + { GPIO_SKL_H_GPP_A6, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigL= ock } },//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + { GPIO_SKL_H_GPP_A7, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLo= ck } },//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + { GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfi= gLock } },//GPP_A_8_FM_LPC_CLKRUN_N + { GPIO_SKL_H_GPP_A9, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K, GpioPadConfi= gLock } },//GPP_A_9_CLK_24M_66M_LPC0_ESPI + { GPIO_SKL_H_GPP_A10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigL= ock } },//GPP_A_10_TP_PCH_GPP_A_10 + { GPIO_SKL_H_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock= } },//GPP_A_11_FM_LPC_PME_N + { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone = } },//GPP_A_12_IRQ_PCH_SCI_WHEA_N + { GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLoc= k | GpioOutputStateLock } },//GPP_A_13_FM_EUP_LOT6_N + { GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfig= Lock } },//GPP_A_14_ESPI_RESET_N + { GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock= } },//GPP_A_15_SUSACK_N + { GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock |= GpioOutputStateLock } },// CLK_48MHZ_PCH [GPP_A_16_CLKOUT_LPC_2] +}; + + +VOID +UpdateeSPIConfiguration ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress +) +{ + UINT32 Index1; + UINT32 Index2; + + for(Index1 =3D 0; Index1 < sizeof (meSPIConfig)/sizeof (GPIO_INIT_CONFIG= ); Index1++) { + for (Index2 =3D 0; Index2 < NumberOfItems; Index2++) { + if (meSPIConfig[Index1].GpioPad =3D=3D (GpioInitTableAddress+Index2)= ->GpioPad){ + (GpioInitTableAddress + Index2)->GpioConfig =3D meSPIConfig[Index1= ].GpioConfig; + } + } + } +} + +EFI_STATUS +PlatformInitGpios ( + VOID +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + GPIO_INIT_CONFIG *GpioTable; + UINTN TableSize; + UINT32 SpiConfigValue; + GPIO_INIT_CONFIG *mPchGpioInitData =3D NULL; + VOID *HobPtr; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gUbaConfigDatabasePpiGuid, 0, NULL, &U= baConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + TableSize =3D PcdGet32(PcdOemSku_GPIO_TABLE_SIZE); + DEBUG ((DEBUG_INFO, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", Table= Size, (TableSize/sizeof (GPIO_INIT_CONFIG)) )); + Status =3D PeiServicesAllocatePool (TableSize, &GpioTable); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + GpioTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + SpiConfigValue =3D 0; + DynamicSiLibraryPpi->PchPcrRead32ByPchId (PCH_LEGACY_ID, PID_ESPISPI, R_= PCH_PCR_SPI_CONF_VALUE, &SpiConfigValue); + DEBUG((DEBUG_INFO, "SPI Config Value =3D %x; ", SpiConfigValue)); + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + DEBUG((DEBUG_INFO, "eSPI Mode\n")); + } else { + DEBUG((DEBUG_INFO, "LPC Mode\n")); + } + + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + mPchGpioInitData =3D AllocateZeroPool((UINTN)TableSize); + if (mPchGpioInitData !=3D NULL){ + CopyMem(mPchGpioInitData, GpioTable, TableSize); + UpdateeSPIConfiguration((UINT32)(TableSize / sizeof(GPIO_INIT_CONFIG= )), mPchGpioInitData); + } else { + DEBUG ((DEBUG_ERROR, "\n*** ERROR!!!! AllocateZeroPool returned NULL= pointer when trying to allocate buffer for 'mPchGpioInitData'!!!! ***\n")); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return Status; + } + } else { + // Point to LPC config values + mPchGpioInitData =3D GpioTable; + } + + DEBUG ((DEBUG_INFO, "UBA: Start ConfigureGpio().\n")); + Status =3D DynamicSiLibraryPpi->GpioConfigurePadsByPchId (PCH_LEGACY_ID,= TableSize/sizeof (GPIO_INIT_CONFIG), mPchGpioInitData); + DEBUG ((DEBUG_INFO, "UBA: ConfigureGpio() end.\n")); + + HobPtr =3D BuildGuidDataHob ( + &gPlatformGpioConfigGuid, + mPchGpioInitData, + TableSize + ); + if (HobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PlatformInitGpios(): ERROR: BuildGuidDataHob fai= led!\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaG= pioInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/= UbaGpioInitLib.inf new file mode 100644 index 0000000000..cfcd4790e5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaGpioInit= Lib.inf @@ -0,0 +1,46 @@ +## @file +# +# @copyright +# Copyright 2016 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UbaGpioInitLib + FILE_GUID =3D C3597C66-784E-4215-BF24-71D8C7B5E3BE + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D UbaGpioInitLib|PEIM PEI_CORE + +[sources] + UbaGpioInitLib.c + +[LibraryClasses] + DebugLib + MemoryAllocationLib + PeiServicesLib + PcdLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioConfigGuid + gPlatformGpioInitDataGuid + +[Depex] + gUbaConfigDatabasePpiGuid AND + gDynamicSiLibraryPpiGuid --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77714): https://edk2.groups.io/g/devel/message/77714 Mute This Topic: https://groups.io/mt/84168627/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-