From nobody Thu May 2 16:20:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77707+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77707+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136910; cv=none; d=zohomail.com; s=zohoarc; b=hK4OcJfDB+3WlTqvG4Fv/EMGx6enkrLy8Ue7y1wx04mxfKp0wkJT6jBXhBVsJYsQZ9P+TkdwmCbbZh6csq/+H4kxTFHz6hGY1Cinl2bddmNWeUKuxreUTCTzjPEPcVrdYwUh7LhDgyhDJXGo9bvNEnzYUlT2J4XSe0aP7azxcqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626136910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=gLhO3VN1cQV3vRXqbyLWsqtSvTH18MbzafyfetD/MkA=; b=HetnMecKILkCxQ+bZXoaOEBXUXeXv28R5kMswaY3ikLUqNlWaGLYd9+I7NlCso9o/XPVUPDs033+Up6BZA7+VSa5H4kl4HNLeVmBQML2mBkwCnKrxhwIEKjjEsHIQy3Qt5C5aV2sHw2k8FbJJY5AXyH/uf/eLYuHu7AywfCD8sQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77707+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626136910727811.708670548502; Mon, 12 Jul 2021 17:41:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kNTRYY1788612xqEU7XyIIo4; Mon, 12 Jul 2021 17:41:50 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.2663.1626136909548654023 for ; Mon, 12 Jul 2021 17:41:49 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723112" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723112" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:45 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422913" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:45 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 01/17] WhitleySiliconPkg: Add DEC and DSC files Date: Mon, 12 Jul 2021 17:41:15 -0700 Message-Id: <20210713004131.1782-2-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: yptMIxrocelo4PVKMDjnX7r5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136910; bh=eJIDC2e603g/F2NarkkHYPbrComMtTvfUL9+jVdHSTI=; h=Cc:Date:From:Reply-To:Subject:To; b=ILPEJm4Y6gBLPaJmv0I3GlVP6sFIayjRtXjQ+fxS5bB70bYNJCWE/peKXMeYuiwv/HW 7uuExjHSbByRwpYcii78mlBkFc0e+vASv/4fbXOKFfzbGyr7inOt6kqhwiKYXqoHrYN5L SgjB+3DB8S3Ou7sUTQNvD7LaLPNaHkg8vpc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136912690100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 541 +++++++++ .../WhitleySiliconPkg/MrcCommonConfig.dsc | 71 ++ .../Product/Whitley/SiliconPkg10nmPcds.dsc | 99 ++ .../Intel/WhitleySiliconPkg/SiliconPkg.dec | 1004 +++++++++++++++++ .../WhitleySiliconPkg/WhitleySiliconPkg.dec | 65 ++ 5 files changed, 1780 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc create mode 100644 Silicon/Intel/WhitleySiliconPkg/Product/Whitley/Silicon= Pkg10nmPcds.dsc create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/Wh= itleySiliconPkg/CpRcPkg.dec new file mode 100644 index 0000000000..91eace9aa0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -0,0 +1,541 @@ +## @file +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D CpRcPkg + PACKAGE_GUID =3D 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + # + # Over time these will be removed as definitions are moved + # out of BaseMemoryCoreLib and into the standard Include directory + # + + Library/BaseMemoryCoreLib/Core + Library/BaseMemoryCoreLib/Core/Include + Library/BaseMemoryCoreLib/Platform + +[Guids] + + ## Include/Guid/MemBootHealthGuid.h + gMemBootHealthGuid =3D { 0xACD56900, 0xDEFC, 0x4127, { 0xDE= , 0x12, 0x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F }} + + ## Include/Guid/CpRcPkgTokenSpace.h + gEfiCpRcPkgTokenSpaceGuid =3D { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d= , 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }} + gSystemInfoVarHobGuid =3D { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92= , 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }} + gReferenceCodePolicyHobGuid =3D { 0x5AC718A1, 0xFBA0, 0x4F5F, { 0xAF= , 0x9F, 0x20, 0x4A, 0x1A, 0xF6, 0x15, 0x32 }} + + ## Include/SystemInfoVar.h + gEfiSysInfoVarNvramDataGuid =3D { 0x0E5AD476, 0xE47D, 0x4E50, { 0xAE= , 0x9D, 0x38, 0xDF, 0xE2, 0x71, 0x67, 0x96 }} + gStatusCodeDataTypeExDebugGuid =3D { 0x7859daa2, 0x926e, 0x4b01, { 0x85= , 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }} + gDebugDataGuid =3D { 0xED585D92, 0x8F3D, 0x43E3, { 0xB7= , 0x8D, 0xD1, 0xB8, 0xF9, 0x05, 0x7F, 0xCE }} + gPerfStatsGuid =3D { 0x83f6e752, 0xd9ae, 0x48eb, { 0xab= , 0xd4, 0xb5, 0xe9, 0x84, 0x63, 0x60, 0x68 }} + + ## Include/Guid/RcSimGlobalDataHob.h + gEfiRcSimGlobalDataHobGuid =3D { 0x25a4a61a, 0x5a6d, 0x429e, { 0x99= , 0x2b, 0xbe, 0xeb, 0x8a, 0xbd, 0xd8, 0x40 }} + + # OnBoardSPD library + gOnBoardSpdTableGuid =3D { 0xe15c5c55, 0x09ec, 0x4a95, { 0xa3= , 0x5a, 0x1e, 0x72, 0xa3, 0x2c, 0x4f, 0x0f }} + gSpdTableHobGuid =3D { 0x429E8B23, 0xB8B1, 0x4208, { 0x96= , 0xAA, 0x51, 0x5A, 0x11, 0x62, 0x80, 0x40 }} + + ## Include/Guid/FspInfo.h + gFspInfoHobGuid =3D { 0x4a7bd124, 0xcbea, 0x4b3b, { 0x95= , 0x86, 0x11, 0xe6, 0x68, 0xe9, 0xbc, 0xdd }} + + gEfiMemoryConfigDataGuid =3D { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c= , 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }} + + gMemRasS3DataVariableGuid =3D { 0xe626f9ca, 0xfd71, 0x458c, { 0xb9= , 0x26, 0xbf, 0x40, 0x80, 0x62, 0x42, 0xa9 }} + + gStaticPointerSmmSizeGuid =3D { 0xd0ee5959, 0xbae6, 0x4709, { 0xaa= , 0x2b, 0x55, 0xbe, 0x90, 0x57, 0x65, 0x6d }} + + # Enhanced Warning Log (EWL) BDAT schema Guid + gEwlBdatSchemaGuid =3D { 0xbffe532f, 0xca3b, 0x416c, { 0xa0= , 0xf6, 0xff, 0xe4, 0xe7, 0x1e, 0x3a, 0xd }} + + # Memory SPD Raw data BDAT schema Guid + gSpdBdatSchemaGuid =3D { 0x1b19f809, 0x1d91, 0x4f00, { 0xa3= , 0xf3, 0x7a, 0x67, 0x66, 0x6, 0xd3, 0xb1 }} + + # Memory SPD Raw data version ID Guid + gSpdVersion1Guid =3D { 0x46f60b90, 0x9c94, 0x43ca, { 0xa7= , 0x7c, 0x9, 0xb8, 0x48, 0x99, 0x93, 0x48 }} + + # Memory SPD data variable + gSpdVariableGuid =3D { 0x1f5d405b, 0x9b66, 0x4336, { 0x85= , 0xe9, 0x52, 0xb4, 0xee, 0x6a, 0xca, 0x51 }} + + # Memory training data BDAT schema Guid + gMemTrainingDataBdatSchemaGuid =3D { 0x27aab341, 0x5ef9, 0x4383, { 0xae= , 0x4d, 0x9, 0x12, 0x41, 0xb2, 0xfa, 0xc }} + + # Memory training data version ID Guid + gMemTrainingDataVersion1Guid =3D { 0x37e839b5, 0x4357, 0x47d9, { 0xa1= , 0x3f, 0x6f, 0x9a, 0x43, 0x33, 0xfb, 0xc4 }} + + # Memory training data HOB Guid + gMemTrainingDataHobGuid =3D { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86= , 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }} + + # + # Guid for the BiosId file, used only for RcSim + # + gRcSimBiosIdFileGuid =3D { 0xf0c51ad5, 0x44f0, 0x4622, { 0x95= , 0x15, 0xe2, 0x7, 0x71, 0xf0, 0xe0, 0xf2 }} + gSystemTopologyGuid =3D { 0x743e5992, 0xf2a0, 0x4c9f, { 0xa5= , 0xf5, 0x3b, 0x24, 0xad, 0xe8, 0x7f, 0x4d }} + +[PPIs] + ## Include/Ppi/MemorySetupPolicyPpi.h + gMemoryPolicyPpiGuid =3D { 0x731b6dbc, 0x18ac, 0x4cc3, { 0x9= e, 0xe2, 0x9e, 0x5f, 0x33, 0x39, 0x68, 0x81 }} + +[PcdsFeatureFlag] + ## Indicate whether USRA can support S3 + gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012 + + ## Use this feature PCD to support Single PCIe segment with static MMCFG= Base + gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014 + + ## enable/disable USRA trace. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016 + + ## enable/disable Quiesce feature. + gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017 + + ## Enable / disable CTE build feature. + gEfiCpRcPkgTokenSpaceGuid.PcdCteBuild|FALSE|BOOLEAN|0x0000001C + + ## Enable / disable COSIM build feature. + gEfiCpRcPkgTokenSpaceGuid.PcdCosimBuild|FALSE|BOOLEAN|0x0000001D + + ## Enable / disable DDRT2 buffer build + gEfiCpRcPkgTokenSpaceGuid.PcdDdrt2BufferlessBuild|FALSE|BOOLEAN|0x000000= 4F + + # Backside Rank Margin Tool + gEfiCpRcPkgTokenSpaceGuid.EnableBacksideRmt|FALSE|BOOLEAN|0x0000001F + # Backside Command Rank Margin Tool + gEfiCpRcPkgTokenSpaceGuid.EnableBacksideCmdRmt|FALSE|BOOLEAN|0x00000030 + # RMT Pattern Length + gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthCmd|32767|UINT32|0x00000031 + gEfiCpRcPkgTokenSpaceGuid.RmtPatternLengthExtCmdCtlVref|32767|UINT32|0x0= 0000032 + gEfiCpRcPkgTokenSpaceGuid.PcdEnableNgnBcomMargining|FALSE|BOOLEAN|0x0000= 0033 + #Enable per bit margining + gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|TRUE|BOOLEAN|0x00000034 + ## Enable / disable MRS STACKING in the CPGC + gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdr|FALSE|BOOLEAN|0x00000037 + gEfiCpRcPkgTokenSpaceGuid.MrsStackingDdrt|FALSE|BOOLEAN|0x00000038 + gEfiCpRcPkgTokenSpaceGuid.MrsStackingNvdimm|FALSE|BOOLEAN|0x00000039 + # Use this PCD to control if separate CWL_adj calculation for 14nm and 1= 0nm + gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|FALSE|BOOLEAN|0x0000003B + + ## Enable / disable USRA register filter. For Sim and SMM. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterFilterEnable|TRUE|BOOLEAN|0x000= 0002D + ## Enable / disable USRA register log. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraRegisterLogEnable|TRUE|BOOLEAN|0x000000= 2E + + ## Enable / disable override of debug levels during MRC call table execu= tion + gEfiCpRcPkgTokenSpaceGuid.PcdDebugLevelsOverride|TRUE|BOOLEAN|0x00000050 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved1|TRUE|BOOLEAN|0x00000051 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved2|FALSE|BOOLEAN|0x0000011c + gEfiCpRcPkgTokenSpaceGuid.PcdReserved3|FALSE|BOOLEAN|0x0000011d + gEfiCpRcPkgTokenSpaceGuid.PcdReserved4|FALSE|BOOLEAN|0x0000011e + + gEfiCpRcPkgTokenSpaceGuid.Reserved15|FALSE|BOOLEAN|0x00000052 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved5|TRUE|BOOLEAN|0x00000053 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved6|FALSE|BOOLEAN|0x00000054 + + #Enable\Disable Mem Boot Health Feature + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|TRUE|BOOLEAN|= 0x00000055 + #Control Opportunistic Self Refresh(OSR) feature. + #PCD hides\shows the OSR Setup knob based on setting + #default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshSupported|FALSE|BOO= LEAN|0x00000115 + + gEfiCpRcPkgTokenSpaceGuid.PcdDprSizeFeatureSupport|FALSE|BOOLEAN|0x00000= 056 + + #SecurityPolicy + gSecurityPolicyDataGuid.PcdCoSignEnable|FALSE|BOOLEAN|0xE000002F + +[PcdsFixedAtBuild] + # + # MRC build time configuration PCD's + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE|BOOLEAN|0x00000100 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|FALSE|BOOLEAN|0x00= 000101 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE|BOOLEAN|0x00000102 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE|BOOLEAN|0= x00000103 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE|BOOLEAN|0x00000104 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE|BOOLEAN|0x00000= 105 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE|BOOLEAN|0= x00000106 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE|BOOLEAN|0x000001= 07 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE|BOOLEAN|0x0= 0000113 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSpdDecodeLibTrace|FALSE|BOOLEAN|0x0= 0000114 + + #PCD controls Setup default for OSR + #Default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdOpportunisticSelfRefreshDefault|0|UINT8|0x0= 0000116 + #PCD controls Setup default for DDRT Self Refresh + #Default disabled + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSrefDefault|0|UINT8|0x00000117 + + # + # Dimm support + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE|BOOLEAN|0x00000108 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE|BOOLEAN|0x00000109 + + # + # SVID support + # + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidSupported|TRUE|BOOLEAN|0x8000010A + + # + # Miscellaneous MRC options + # + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE|BOOLEAN|0x= 00000110 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE|BOOLEAN|0x00000112 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|FALSE|BOOLEAN|0x00000111 + + ## Indicates the size of each PCIE segment + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010 + gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013 + ## Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018 + ## Maximum number of sockets supported for this firmware build. + # This PCD should be used sparingly. Dynamic allocation of data and + # dynamic control flows are preferred over using this PCD for static + # data allocation and control. + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019 + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|0x22|UINT32|0x0000001A + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|0x2|UINT32|0x0000001B + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutBaseClock|0x0000001C= |UINT32|0x00000022 + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutThreshold|0x0000000C= |UINT32|0x00000023 + gEfiCpRcPkgTokenSpaceGuid.PcdReadPendingQueueTimeoutCreditLimit|0x000000= 20|UINT32|0x00000024 + ## Enable / Disable USRA trace configuration by IO port + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortEnable|FALSE|BOOL= EAN|0x00000025 + ## Set the specific IO port for trace configuration low byte + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortLow|0x81|UINT8|0x= 00000026 + ## Set the specific IO port for trace configuration high byte + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationPortHigh|0x82|UINT8|0= x00000027 + + ## PcdUsraTraceConfigurationValue is used to control the USRA trace beha= vior, and the defination shown as below. + # When PcdUsraTraceConfigurationPortEnable is TRUE, this configuration v= alue can be overridden by configuration IO port. + # When PcdUsraTraceConfigurationPortEnable is FALSE, the value can be ov= erridden via the interface SetUsraTraceConfiguration(). + # Bit 0 - Bit 3 : USRA trace Signature,it should always be 0101B. + # Bit 4: Set indicates USRA trace message's format is long m= ode. + # Bit 5: Set indicates get address operation is traced. + # Bit 6: Set indicates modify operation is traced. + # Bit 7: Set indicates write operation is traced. + # Bit 8: Set indicates read operation is traced. + # Bit 9: Set indicates PCIE access is traced. + # Bit 10: Set indicates CSR access is traced. + # Bit 11 - Bit14: Reserved for future uses. + # Bit 15: Set indicates dumps the content of CpuCsrAccessVar = before dumping the register access trace information. + # @Prompt USRA trace configuration settings. + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceConfigurationValue|0x07F5|UINT16|0= x00000028 + ## Default value to USRA trace start at earlier stage, this value can be= overridden by the interface UsraTraceStart() + ## and UsraTraceEnd(). + gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceStartAtEarlierStage|FALSE|BOOLEAN|= 0x00000029 + ## Indicates whether it needs to clear temp bus assignment in PCIE commo= n init library + gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE|BOOLEAN|0x00000= 02A + + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion|{0, 0, 0, 0}|RC_VERSION|0x0000001= 5 { + + RcVersion.h + + WhitleySiliconPkg/CpRcPkg.dec + } + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x0033 + + # + # MRC DEFAULT SETTINGS + # + + # PCD NAME | = VALUE| TYPE| PCD NUM. + ## Default Enable / Disable Legacy RMT Feature + gEfiCpRcPkgTokenSpaceGuid.PcdLegacyRmtEnable | = 1| UINT8|0x0000001E + + + # + # Enforce memory POR configurations + # 0 (ENFORCE_POR_EN) - Enforce memory POR + # 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal + # 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations + # + gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | = 0| UINT8|0x00000040 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE= |BOOLEAN|0x0000003A + + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | = FALSE|BOOLEAN|0x00000060 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastColdBootDefault | = TRUE|BOOLEAN|0x00000061 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault | = TRUE|BOOLEAN|0x00000062 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault | = 0xFF| UINT8|0x00000063 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault | = 0xFF| UINT8|0x00000064 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault | = 0x0| UINT8|0x00000065 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | = 0x2| UINT8|0x00000066 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | = FALSE|BOOLEAN|0x00000067 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | = 0x6| UINT8|0x00000068 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOO= LEAN|0x00000069 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | = TRUE| UINT8|0x0000006A + + + #Setup string for Mem boot health check + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHea= lthConfig"| VOID*|0x00000070 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | = FALSE|BOOLEAN|0x00000071 + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | = FALSE|BOOLEAN|0x00000072 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2= | UINT8|0x0000011F + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE= |BOOLEAN|0x00000120 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | = FALSE|BOOLEAN|0x00000075 + #option to choose Mem Boot Health configuration type. 00=3D>Auto (Use de= faults), 01=3D>Manual (Override defaults with setup option), 02=3D>Disable = (Disable feature) + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | = 00| UINT8|0x00000076 + + # The below values are setup\standard\build defaults. Can be overridden = in platform specific dsc + ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS STARTS########= ############################# + #Left edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayLeftEdge | = 5| UINT8|0x00000077 + #Right edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxDqDelayRightEdge | = 5| UINT8|0x00000078 + #Left edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefLeftEdge | = 5| UINT8|0x00000079 + #Right edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningTxVrefRightEdge | = 5| UINT8|0x0000007A + #Left edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayLeftEdge | = 5| UINT8|0x0000007B + #Right edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxDqsDelayRightEdge | = 5| UINT8|0x0000007C + #Left edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefLeftEdge | = 5| UINT8|0x0000007D + #Right edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdWarningRxVrefRightEdge | = 5| UINT8|0x0000007E + ###################MEM BOOT HEALTH CONFIG WARNING OFFSETS ENDS##########= ############################# + + ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS STARTS#######= ############################# + #Left edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayLeftEdge | = 2| UINT8|0x0000007F + #Right edge offset for TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxDqDelayRightEdge | = 2| UINT8|0x00000080 + #Left edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefLeftEdge | = 2| UINT8|0x00000081 + #Right edge offset for TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalTxVrefRightEdge | = 2| UINT8|0x00000082 + #Left edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayLeftEdge | = 2| UINT8|0x00000083 + #Right edge offset for RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxDqsDelayRightEdge | = 2| UINT8|0x00000084 + #Left edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefLeftEdge | = 2| UINT8|0x00000085 + #Right edge offset for RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdCriticalRxVrefRightEdge | = 2| UINT8|0x00000086 + ###################MEM BOOT HEALTH CONFIG CRITICAL OFFSETS ENDS#########= ############################# + + # Option to enable/disable RMT minimum margin test + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumMarginCheckDefault | = 1| UINT8|0x00000124 + + # Define the default minimum margin thresholds for RMT margin check + # The minimum margin thresholds are applied to both margin directions. + # Rx timing: RxDqsDelay + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxTimingMargin | = 3| UINT8|0x00000125 + # Rx voltage: RxVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumRxVoltageMargin | = 3| UINT8|0x00000126 + # Tx timing: TxDqDelay + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxTimingMargin | = 3| UINT8|0x00000127 + # Tx voltage: TxVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumTxVoltageMargin | = 3| UINT8|0x00000128 + # Cmd timing: CmdAll + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdTimingMargin | = 5| UINT8|0x00000129 + # Cmd voltage: CmdVref + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCmdVoltageMargin | = 5| UINT8|0x00000130 + # Ctl timing: CtlAll + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | = 5| UINT8|0x00000131 + + #Reset on Critical Margin failure to perform Memory Training from scratch + gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | = 1| UINT8|0x00000087 + + #Enable Debug message inside MarginTest + #BIT0 for API Debug messages + #BIT1 for Log messages + #BIT2 for Error messages + #BIT3 for Function trace messages + gEfiCpRcPkgTokenSpaceGuid.PcdEvDebugMsg | = 0| UINT8|0x00000088 + + #Non-Configurable...Number of Signals to test. + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootSignalsToTest | = 4| UINT8|0x00000089 + + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved14| FALSE|BOOLEAN|0= x0000008B + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations | = FALSE|BOOLEAN|0x0000008C + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt| = FALSE|BOOLEAN|0x0000008D + # + # Default SMBUS Speed - see SMB_CLOCK_FREQUENCY + # 0 - SMB_CLK_100K - 100 Khz + # 1 - SMB_CLK_400K - 400 Khz + # 2 - SMB_CLK_700K - 700 Khz + # 3 - SMB_CLK_1M - 1 Mhz + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault | = 0x1| UINT8|0x0000008E + + # + # Throttling mid on temp lo + # 0 - Disabled + # 1 - Enabled + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcThrottlingMidOnTempLo | = 0| UINT8|0x0000008F + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault | = 0x1| UINT8|0x00000090 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCtleTrainingEnable | = TRUE|BOOLEAN|0x00000091 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcImodeTrainingEnable | = TRUE|BOOLEAN|0x00000092 + + + #CLTT settings + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault | = 82| UINT8|0x00000093 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault | = 83| UINT8|0x00000094 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault | = 85| UINT8|0x00000095 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault | = 83| UINT8|0x00000096 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault | = 83| UINT8|0x00000097 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault | = 93| UINT8|0x00000098 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault | = 95| UINT8|0x00000099 + + # + # Allowed debug level at build time configuration + # See RcDebugLib.h for mapping details + # + gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugAllowedLevelsMask | = 0xC7F0190B| UINT32|0x0000009A + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTcoCompTrainingEnable | = FALSE|BOOLEAN|0x0000009B + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault | = 0x1| UINT8|0x0000009C + gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault | = 1| UINT8|0x0000009D + + # + # Enforce memory population POR configurations. + # 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce memory = population POR. + # 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported memo= ry populations. + # 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated memo= ry populations. + gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePopulationPorDefault | = 1| UINT8|0x0000009E + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable | = TRUE|BOOLEAN|0x0000009F + + # + # Legacy ADR flow + # 0 (LEGACY_ADR_MODE_DISABLE) - Pcode driven ADR flow + # 1 (LEGACY_ADR_MODE_ENABLE) - Legacy ADR flow + # + gEfiCpRcPkgTokenSpaceGuid.PcdLegacyAdrDefault | = 0| UINT8|0x000000A0 + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault | = 0x1| UINT8|0x000000A1 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPxcDefault | = 0x1| UINT8|0x000000A2 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdjcDefault | = 0x1| UINT8|0x000000A3 + + # + # Default debug level at build time configuration + # + gEfiCpRcPkgTokenSpaceGuid.PcdRcDebugBuildTimeDefault | = 0x8000190B| UINT32|0x000000A9 + + gEfiCpRcPkgTokenSpaceGuid.PcdRmtMarginInCaCsTm | = TRUE|BOOLEAN|0x000000AC + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault | = 0| UINT8|0x000000AE + + #Only enable for 14nm, not a feature for 10nm and above + # 0 =3D Disable + # 1 =3D TA Floor + # 2 =3D Receive Enable Average + # 3 =3D Receive Enable Average part 1 only + gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption | = 0|UINT8|0x000000A4 + + # + # Timers detinitions for priority promotions + # + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim | = 0x100| UINT16|0x000000A5 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim | = 0x100| UINT16|0x000000A6 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim | = 0x100| UINT16|0x000000A7 + + #Mrc memory default frequency + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDdrFrequencyDefault | = 0x0| UINT8|0x000000A8 + + #MRC Panic Watermark default + # 0 =3D Auto, 1 =3D High, 2 =3D Low + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPanicWatermarkDefault | = 0x0| UINT8|0x000000AA + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved15 | = 0x2| UINT8|0x000000AB + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved16 | = 0x0| UINT8|0x000000AD + + # Additional Buffer Delay for Roundtrip + gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk | = 4| UINT8|0x000000AF + + # Option to enable / disable MCR Support + gEfiCpRcPkgTokenSpaceGuid.PcdMcrSupport | = FALSE|BOOLEAN|0x000000B0 + + # Option to store SPD raw data to BDAT + gEfiCpRcPkgTokenSpaceGuid.SaveSpdToBdat | = TRUE|BOOLEAN|0x00000121 + # Option to store training data to BDAT + gEfiCpRcPkgTokenSpaceGuid.SaveMrcTrainingDataToBdat | = TRUE|BOOLEAN|0x00000122 + + + gEfiCpRcPkgTokenSpaceGuid.PcdVendorMemtestEnable | = TRUE|BOOLEAN|0x00000123 + +[PcdsDynamicEx] + ## | = MMCFG Table Header | = Segment 0 | = Segment 1 | = Segment 2 |= Segment 3 = | Segment 4 = | Segment 5 = | Segment 6 = | Segment 7 = | + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011 + + gEfiCpRcPkgTokenSpaceGuid.PcdSimStaticPointerTableMapPtr|{0x0}|VOID*|0x8= 0000012 + +############### SVID Mapping ################################## + #The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, = and 0x16. + #Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (= VR ID's 0x10 and 0x12). + #Those are typically shared such that MC0/MC2 share the same DDR VR (as = they are on the same side of the CPU) + #and MC1/MC3 share the other. Depending on motherboard layout and other = design constraints, this could change + #This information is per platform basis and can be obtained from platfor= m schematics. + #Need to map this token for MC to SVID based on platform. + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap|{0}|MEM_SVID_MAP|0x80000014 { + + Library/MemVrSvidMapLib.h + + WhitleySiliconPkg/WhitleySiliconPkg.dec + } +############### SVID Mapping ################################## + + # IMON SVID VR address + # Fill with IMON SVID Address + # End the list with 0xFF (IMON_ADDR_LIST_END) + # Assumption, all socket repeat same address + #BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + #BIT 0:3 =3D> SVID ADDRESS + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr|{0xFF}|VCC_IMON|0x0000008A { + + ImonVrSvid.h + + WhitleySiliconPkg/WhitleySiliconPkg.dec + } + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32= |0x00000020 + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x000000= 21 + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035 + gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000= 036 + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x0= 0000118 +## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor + gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C + gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D + +[PcdsDynamic, PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00= 000048 + gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0= x00000049 + gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A + gEfiCpRcPkgTokenSpaceGuid.PcdLtMemSize|0x00500000|UINT32|0x0000004B + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable|FALSE|BOOLEAN|0x0000004C + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size|0x0|UINT64|0x0000004D + + # + # PCD for storing sizeof (SysHost) in PEI for later comparision in DXE + # + + gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize|0x00000000|UINT32|0x00= 00004E diff --git a/Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc b/Silicon/= Intel/WhitleySiliconPkg/MrcCommonConfig.dsc new file mode 100644 index 0000000000..be22c51e44 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc @@ -0,0 +1,71 @@ +## @file +# Memory Reference Code configuration file. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# This file is for common defintions for all MRC build targets. +# This is not for platform specific defintions +# + +[PcdsFixedAtBuild] + +# +# MRC Debug configuration options +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugTurnarounds|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPerformanceStats|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSenseAmp|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDisplayPerformanceValues|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLateCmdClk|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugPowerTraining|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugLrdimmExtraMessages|FALSE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcBeginEndDebugHooks|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcDebugSwizzleInspection|FALSE + +# +# Dimm support +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcQrDimmSupport|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcSoDimmSupport|TRUE + +# +# Miscellaneous MRC options +# + +gEfiCpRcPkgTokenSpaceGuid.PcdMrcPurleyBiosHeaderOverride|TRUE +gEfiCpRcPkgTokenSpaceGuid.PcdMrcXmpSupport|TRUE + +[PcdsFixedAtBuild.IA32] + +gEfiCpRcPkgTokenSpaceGuid.PcdReserved7|TRUE + +[BuildOptions] + +# +# Size of NvramData structure, per socket +# + DEFINE NUMBER_OF_SUB_CHANNELS =3D -D SUB_CH=3D1 + + DEFINE NUMBER_OF_MAX_RANK_DIMM =3D -D MAX_RANK_DIMM=3D4 + DEFINE NUMBER_OF_MAX_RANK_CH =3D -D MAX_RANK_CH=3D8 + +*_*_*_CC_FLAGS =3D $(NUMBER_OF_SUB_CHANNELS) $(NUMBER_OF_MAX_RANK_DIMM) $= (NUMBER_OF_MAX_RANK_CH) + +# +# Always define IA32 for PEI, undefine for DXE and SMM +# + +*_*_IA32_CC_FLAGS =3D -D IA32 +*_*_X64_CC_FLAGS =3D -U IA32 + + + + + diff --git a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nm= Pcds.dsc b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPc= ds.dsc new file mode 100644 index 0000000000..4402540f91 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc @@ -0,0 +1,99 @@ +## @file +# Pcd definitions for 14nm & 10nm wave1 & 10nm wave2 CPU. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# PCD definitions section - list of all PCD definitions needed by this Pla= tform. +# +##########################################################################= ###### +[PcdsFixedAtBuild] + + # Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010 + + ## Socket count used to indicate maximum number of CPU sockets supported= by the platform. + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount|$(MAX_CORE) + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount|$(MAX_THREAD) + + ## Indicates whether it needs to clear temp bus assignment in PCIE commo= n init library + gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE + + # Default SMBUS speed for Whitley is 700Khz - see SMB_CLOCK_FREQUENCY de= finition + gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault|0x2 + +!if (($(CPUTARGET) =3D=3D "ICX")) + # Overrides specific to ICX-SP + gEfiCpRcPkgTokenSpaceGuid.PcdDimmIsolationDefault |0 + + # Enable LRDIMM DB DFE for ICX + PMem + gEfiCpRcPkgTokenSpaceGuid.PcdMrcLrdimmDbDfeDefault |1 + + # Additional Buffer Delay for Roundtrip + gEfiCpRcPkgTokenSpaceGuid.PcdRoundTripBufferDelayDclk |8 +!endif + + # Memory health check default + # 00=3D>Auto (Use defaults), 01=3D>Manual (Override defaults with setup = option), 02=3D>Disable (Disable feature) +!if (($(CPUTARGET) =3D=3D "ICX")) + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck|2 +!endif + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault|TRUE + + # + # Override MRC default values for SKX, defaults are all set + # for 10nm + # + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE + + gEfiCpRcPkgTokenSpaceGuid.PcdMrcBdatDefault|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcWritePreambleTclkDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcReadPreambleTclkDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcRxDfeDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcOdtDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault|TRUE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault|0x0 + + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoSingleRefreshDefault|82 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshDefault|82 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiSingleRefreshDefault|100 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidSingleRefreshAepDefault|83 + + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempLoDoubleRefreshDefault|84 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempMidDoubleRefreshDefault|93 + gEfiCpRcPkgTokenSpaceGuid.PcdClttTempHiDoubleRefreshDefault|100 + +!else + gEfiCpRcPkgTokenSpaceGuid.PcdMrcMcRonDefault|0x0 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcDramRonDefault|0x0 +!if ($(CPUTARGET) =3D=3D "ICX") + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosLowTimerLim| 0x290 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosMedTimerLim|0x290 + gEfiCpRcPkgTokenSpaceGuid.PcdMrcQosHighTimerLim|0x290 +!endif +!endif + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12|1 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13|FALSE + +# +# Enable DDR4 and DDRT turnaround timing optimization for all Whitley +# platforms +# + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizations|TRUE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcTurnaroundOptimizationsDdrt|TRUE + + # + # enable NVDIMM support + # + gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|TRUE \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel= /WhitleySiliconPkg/SiliconPkg.dec new file mode 100644 index 0000000000..d7039f65c4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec @@ -0,0 +1,1004 @@ +## @file +# Platform Package +# Cross Platform Modules for Tiano +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D ServerSiliconPkg + PACKAGE_GUID =3D DD44D851-9A3E-46E8-A2Ef-D794D014ECC1 + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + Security/Include + Pch/SouthClusterLbg + Pch/SouthClusterLbg/Include + + Cpu/Include + +[Guids] + gMrcThermalHobGuid =3D { 0xca8d15fb, 0x= 8776, 0x4eab, { 0xa8, 0xb8, 0xec, 0x2c, 0x32, 0xcf, 0x2a, 0x9b } } + gEfiPlatformInfoGuid =3D { 0x1e2acc41, 0x= e26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } } + gCpuUncoreTokenSpaceGuid =3D { 0x9044434c, 0x= 40e8, 0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 } } + gProcessorProducerGuid =3D { 0x1bf06aea, 0x= 5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } } + gEfiCpuHtCapableGuid =3D { 0x0d1b9c8e, 0x= f77b, 0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 } } + gEfiMemoryConfigDataHobGuid =3D { 0x1de25879, 0x= 6e2a, 0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 } } + gEfiMemorySetupGuid =3D { 0x3eeff35f, 0x= 147c, 0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 } } + gEfiMemoryMapGuid =3D { 0xf8870015, 0x= 6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } } + gEfiMemoryMapDataHobBdatGuid =3D { 0x3417b225, 0x= 916a, 0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 } } + gEfiMpstNodeDataGuid =3D { 0x418bc604, 0x= f15e, 0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 0x88 } } + gReadyForLockProtocolGuid =3D { 0x8d6f1add, 0x= 45a5, 0x45a8, { 0x8b, 0xb8, 0x0c, 0x3a, 0x95, 0x31, 0x48, 0xfa } } + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + gEfiSocketIioVariableGuid =3D { 0xdd84017e, 0x= 7f52, 0x48f9, { 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0x0d, 0xbe, 0x27 } } + gEfiSocketCommonRcVariableGuid =3D { 0x4402ca38, 0x= 808f, 0x4279, { 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f } } + gEfiSocketMpLinkVariableGuid =3D { 0x2b9b22de, 0x= 2ad4, 0x4abc, { 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c } } + gEfiSocketPciResourceDataGuid =3D { 0xca3ff937, 0x= d646, 0x4936, { 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 } } + gEfiSocketMemoryVariableGuid =3D { 0x98cf19ed, 0x= 4109, 0x4681, { 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 } } + gEfiSocketPowermanagementVarGuid =3D { 0xA1047342, 0x= BDBA, 0x4DAE, { 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 } } + gEfiSocketProcessorCoreVarGuid =3D { 0x07013588, 0x= C789, 0x4E12, { 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C } } + gPrevBootErrSrcHobGuid =3D { 0x5138b5c5, 0x= 9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } } + gSocketPkgListGuid =3D { 0x5c0083db, 0x= 3f7d, 0x4b20, { 0xac, 0x9b, 0x73, 0xfc, 0x65, 0x1b, 0x25, 0x03 } } + gEfiReservedMemoryDataGuid =3D { 0xb5535bba, 0x= c858, 0x4302, { 0x8B, 0xcd, 0xd9, 0x3a, 0x70, 0x72, 0x2f, 0x8c } } + gEfiVolatileMemModeVariableGuid =3D { 0x0633a0f1, 0x= 78fe, 0x4139, { 0xb8, 0x78, 0x00, 0x45, 0xe8, 0x1c, 0xb8, 0xab } } + gSignalBeforeEnterSetupGuid =3D { 0xd9f1669a, 0x= f505, 0x48bd, { 0xa8, 0x92, 0x94, 0xb7, 0xca, 0x90, 0x30, 0x31 } } + gEfiQpiRcParmGuid =3D { 0x8149fbb8, 0x= a2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d } } + gAddressBasedMirrorGuid =3D { 0x7b9be2e0, 0x= e28a, 0x4197, { 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } } + gEfiPprVariableGuid =3D { 0x6a159d4f, 0x= 6e6b, 0x4523, { 0xae, 0xb5, 0xf7, 0xaf, 0x1c, 0x44, 0x4b, 0x0f } } + gRasStateVariableGuid =3D { 0x9189541f, 0x= ac0c, 0x4368, { 0x90, 0x62, 0x70, 0xe1, 0x95, 0x7c, 0x34, 0x45 } } + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } + gEfiCpuPolicyDataHobGuid =3D { 0x8d1faf2d, 0x= 08d6, 0x4c05, { 0x8b, 0xd3, 0x3b, 0x6c, 0x0f, 0x0f, 0xff, 0x1a } } + gEfiPsmiPolicyDataHobGuid =3D { 0x42ed3781, 0x= 019a, 0x28ae, { 0x16, 0x3b, 0x9a, 0x50, 0x07, 0x0f, 0x93, 0x6b } } + gPsmiInitDataGuid =3D { 0x63f37a26, 0x= 9764, 0x86aa, { 0x91, 0x85, 0xe1, 0x90, 0xab, 0x56, 0x63, 0x49 } } + gEfiKtiHostInDataHobGuid =3D { 0x3c1526ff, 0x= d33e, 0x4ba8, { 0x97, 0x0d, 0x4b, 0x9f, 0x28, 0x92, 0x50, 0xa5 } } + gEfiKtiHostOutDataHobGuid =3D { 0x7080648f, 0x= 430e, 0x430c, { 0xbc, 0x7a, 0x66, 0x25, 0xd4, 0x58, 0x3b, 0x74 } } + gEfiKtiHostNvramDataHobGuid =3D { 0xac45d3d6, 0x= a36e, 0x43a6, { 0xad, 0x17, 0x0a, 0x45, 0xbb, 0x47, 0xbe, 0xd6 } } + gReferenceCodePolicyTokenSpaceGuid =3D { 0x3268c52f, 0x= d3b3, 0x405d, { 0xb6, 0x91, 0x14, 0x4f, 0xca, 0x42, 0xe4, 0x37 } } # {3268= c52f-d3b3-405d-b691-144fca42e437} + gEfiMktmekeyGuid =3D { 0xca3ff937, 0x= d649, 0x4936, { 0x90, 0xe8, 0x2b, 0x95, 0x06, 0x49, 0xb3, 0x82 } } + gSecurityMemMapHobGuid =3D { 0xeec2c166, 0x= fc41, 0x4506, { 0xbc, 0xd6, 0xf0, 0x19, 0x9e, 0x22, 0x9f, 0xa3 } } + gCxlNodeHobGuid =3D { 0xdd8ae009, 0x= da5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } } + gSgxUefiFwKeyBlobsVariableGuid =3D { 0x60F76511, 0x= DD87, 0x466D, { 0x91, 0xA6, 0x3C, 0x18, 0x00, 0xFA, 0xDC, 0x6F } } + gSgxUefiFwKeyBlobsWithIntegrityVariableGuid =3D { 0x582cc492, 0x= 51ee, 0x46db, { 0x8d, 0x34, 0xd8, 0x7c, 0x8e, 0x9a, 0x10, 0x83 } } + gSgxUefiFwRegistrationStateVariableGuid =3D { 0x2C65F1A3, 0x= 5DD5, 0x4A41, { 0xA5, 0xC1, 0xF6, 0x93, 0x7F, 0x77, 0x85, 0xE5 } } + gSgxUefiFwPlatformManifestVariableGuid =3D { 0x06141EE2, 0x= 7CDD, 0x4FDF, { 0xA4, 0x52, 0xAE, 0x7D, 0x20, 0x42, 0x6E, 0x2D } } + gSgxRegistrationConfigVariableGuid =3D { 0x18b3bc81, 0x= e210, 0x42b9, { 0x9e, 0xc8, 0x2c, 0x5a, 0x7d, 0x4d, 0x89, 0xb6 } } + gSgxRegistrationServerRequestVariableGuid =3D { 0x304E0796, 0x= D515, 0x4698, { 0xAC, 0x6E, 0xE7, 0x6C, 0xB1, 0xA7, 0x1C, 0x28 } } + gSgxRegistrationPackageInfoVariableGuid =3D { 0xAC406DEB, 0x= AB92, 0x42D6, { 0xAF, 0xF7, 0x0D, 0x78, 0xE0, 0x82, 0x6C, 0x68 } } + gSgxRegistrationPackageInfoWithIntegrityVariableGuid =3D { 0x4d5e9417, 0= x46f4, 0x4704, { 0xb2, 0x1f, 0xc7, 0xc6, 0x72, 0x13, 0xa0, 0xda } } + gSgxRegistrationServerResponseVariableGuid =3D { 0x89589C7B, 0x= B2D9, 0x4FC9, { 0xBC, 0xDA, 0x46, 0x3b, 0x98, 0x3B, 0x2F, 0xB7 } } + gSgxRegistrationStatusVariableGuid =3D { 0xF236C5DC, 0x= A491, 0x4BBE, { 0xBC, 0xDD, 0x88, 0x88, 0x57, 0x70, 0xDF, 0x45 } } + gSgxRegistrationServerInfoGuid =3D { 0x83E12F21, 0x= 1A6B, 0xA142, { 0xA7, 0xA9, 0xDA, 0x3A, 0xB6, 0xB7, 0xBD, 0x02 } } + gSgxUefiRegistrationConfigVariableGuid =3D { 0x8d4ca9e8, 0x= 44c3, 0x43e5, { 0x93, 0x5e, 0xb6, 0xcc, 0x8f, 0xc5, 0x56, 0x65 } } + gSgxUefiRegistrationServerRequestVariableGuid =3D { 0xcd24952f, 0x= 8175, 0x4797, { 0x8e, 0x7d, 0xd8, 0x4b, 0x15, 0x6a, 0x82, 0x77 } } + gSgxUefiRegistrationServerResponseVariableGuid =3D { 0x35d93155, 0x= 79dc, 0x4b5e, { 0xb6, 0xdf, 0x8e, 0xfe, 0x17, 0x93, 0xa1, 0x5e } } + gSgxUefiRegistrationStatusVariableGuid =3D { 0xcf24d5e9, 0x= 51e3, 0x45b4, { 0x8f, 0xe2, 0x2f, 0x34, 0x5c, 0x5f, 0x76, 0x6b } } + gSgxLegacyRegistrationSoftwareGuardStatusVariableGuid =3D { 0x9cb2e73f, = 0x7325, 0x40f4, { 0xa4, 0x84, 0x65, 0x9b, 0xb3, 0x44, 0xc3, 0xcd } } + gSgxLegacyRegistrationEpcBiosVariableGuid =3D { 0xc60aa7f6, 0x= e8d6, 0x4956, { 0x8b, 0xa1, 0xfe, 0x26, 0x29, 0x8f, 0x5e, 0x87 } } + gSgxLegacyRegistrationEpcSwVariableGuid =3D { 0xd69a279b, 0x= 58eb, 0x45d1, { 0xa1, 0x48, 0x77, 0x1b, 0xb9, 0xeb, 0x52, 0x51 } } + gVtdConfigGuid =3D { 0x03e5cf63, 0x= bebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54, 0x61, 0x20, 0xf1, 0xc5 } } + gPpmBeforeBiosInitDoneGuid =3D { 0x0fce4563, 0x= bebb, 0x4041, { 0xa7, 0xd7, 0xbe, 0xf4, 0x61, 0x20, 0xf1, 0xc5 } } + gPbspTearDownNemAddressHobGuid =3D { 0x2e45be97, 0x= ddc2, 0x4d47, { 0x8f, 0x3b, 0x74, 0x1d, 0x50, 0xdf, 0x20, 0x98 } } + gKtiAdaptationTableGuid =3D { 0x204012d3, 0x= 584d, 0x4325, { 0xae, 0x9e, 0xd7, 0x4d, 0xd8, 0x18, 0x6a, 0xd1 } } + +# +# +# +# RAS +# + gEfiRasHostGuid =3D { 0x8149fbb8, 0x= a2cf, 0x4234, { 0xb5, 0x06, 0xb7, 0x62, 0x55, 0xf7, 0xa3, 0x6d } } + gEfiRasClvTesterGuid =3D { 0x9bd36f4f, 0x= 08dc, 0x4eab, { 0x86, 0x37, 0x2b, 0xc1, 0xbd, 0x5e, 0x0d, 0x95 } } + gRasRcPolicyHobGuid =3D { 0x279ED988, 0x= BFEA, 0x43B4, { 0xB3, 0x79, 0xCE, 0x61, 0xAB, 0xDA, 0xC0, 0xB7 } } + gRasRcConfigHobGuid =3D { 0x437872EF, 0x= 2792, 0x47E6, { 0x97, 0xCA, 0xD3, 0xD8, 0xFF, 0xC7, 0x39, 0xA4 } } + gRasGlobalDataVariableGuid =3D { 0xcb4afa36, 0x= 42bf, 0x400b, { 0x8b, 0x8f, 0x57, 0x39, 0x41, 0xa2, 0x9f, 0x4e } } + +## +## Common +## + gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0= x5f, 0x8f, 0xd7, 0x65, 0x4e}} + +# +# Security +# + gSecurityPolicyDataGuid =3D { 0x1781F59B, 0x71FA, 0x4FB1, { 0xB0,= 0x7A, 0x5C, 0x5E, 0xE2, 0xDF, 0x98, 0x14 }} + gSgxInitDataHobGuid =3D { 0x4EF0BEDC, 0xC5C1, 0x4E69, { 0x82,= 0x18, 0x7D, 0xBE, 0x8A, 0x60, 0x68, 0x8C }} + gSgxPreMemInitHobGuid =3D { 0x9A9E2225, 0xE026, 0x4BFF, { 0x99,= 0x17, 0xF1, 0x23, 0xE1, 0xD4, 0x3A, 0xD5 }} + gTmePreMemInitHobGuid =3D { 0x84495ab7, 0xf97f, 0x4502, { 0x93,= 0x12, 0xf7, 0xf4, 0xab, 0x91, 0x09, 0x6e }} + gMktmeInitDataGuid =3D { 0x52eff441, 0x3a19, 0x4d59, { 0x8c,= 0x05, 0x6f, 0x2d, 0x5b, 0x2f, 0xa6, 0xed }} + gTdxDataHobGuid =3D { 0x05885d44, 0x9588, 0x428e, { 0x9e,= 0xb0, 0x1c, 0xa7, 0xe5, 0x4c, 0xa9, 0x6b }} + gSecurityIpInterdependenceGuid =3D { 0x9abadd78, 0xf5b5, 0x4c8e, { 0xa9,= 0x52, 0x3a, 0x83, 0xbe, 0x90, 0x7a, 0x1a }} + +# +# SouthCluster +# + gPchInfoHobGuid =3D { 0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD= 0, 0x36, 0x5F, 0xD6, 0x3E }} + gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0= x97, 0x38, 0x59, 0xd8 }} + gSiPreMemConfigGuid =3D {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, = 0x25, 0x88, 0xbe, 0xfd, 0xc6}} + gSiPolicyHobGuid =3D {0x4ee8c3b9, 0x47a7, 0x4c8a, {0xbb, 0x60, 0x6d, 0= x90, 0xbf, 0x62, 0x10, 0x3c}} + gSiPreMemPolicyHobGuid =3D {0x9142b7e1, 0x411d, 0x475a, {0xab, 0xfc, 0xf= 7, 0x89, 0xb8, 0x2c, 0x24, 0xc8}} + gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x4= 3, 0x66, 0x99, 0xcb, 0xe4, 0x5b}} + gPchIpInfoHobGuid =3D { 0x69247df8, 0x1ecf, 0x4b11, { 0xba, 0xb4, 0x= 28, 0x5a, 0x77, 0xaf, 0x61, 0x11 }} + + gSetupVariableGuid =3D { 0xEC87D643, 0xEBA4, 0x4BB5, = { 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }} + + gChipsetInitHobGuid =3D {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83,= 0x35, 0xfc, 0xc8, 0xd1, 0xc4}} + + gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xE= B, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} + gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x= 36, 0x61, 0xC6, 0x71, 0x3C, 0x5A}} + gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88= , 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}} + gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, 0x= 1a, 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}} + gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1,= 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} + gHpetPreMemConfigGuid =3D {0x7C75C0F1, 0xA20F, 0x42EB, {0x83, 0xDE, 0x= E8, 0x58, 0xAB, 0x81, 0xC5, 0xDC}} + gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0= x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}} + gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC= 6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}} + gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36= , 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}} + gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C= , 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}} + gHsioPreMemConfigGuid =3D {0xbc9e5787, 0x3ddb, 0x4916, {0x8c, 0xcc, 0x= 82, 0xb8, 0x9, 0x43, 0xe2, 0xf0}} + gDmiPreMemConfigGuid =3D {0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA= 3, 0xCF, 0x53, 0xE6, 0xC1, 0x8A}} + gFiaMuxPreMemConfigGuid =3D {0x65667495, 0xA0DF, 0x4481, {0x8D, 0x36, 0x= 01, 0x01, 0x06, 0x98, 0xFD, 0x81}} + gFiaOverrideStatusHobGuid =3D {0x618D94C1, 0x0EDE, 0x4EE3, {0x98, 0x4F, = 0xB2, 0x07, 0x6B, 0x05, 0x50, 0xFB}} + gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0x= CA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} + gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33,= 0xDE, 0x10, 0x6D, 0x94, 0x84}} + gPcieRpDxeConfigGuid =3D {0x475530EA, 0xBD72, 0x416F, {0x98, 0x9F,0x48= , 0x70, 0x5F, 0x14, 0x4E, 0xD9}} + gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0x= C5, 0x9C, 0x54, 0x07, 0xC4}} + gsSataConfigGuid =3D {0xe447c420, 0x3a8e, 0x4d9b, {0x84, 0xe5, 0x4d, 0= x73, 0x77, 0x69, 0xb8, 0xc6}} + gHsiosSataPreMemConfigGuid =3D {0xc4877b20, 0x3098, 0x4952, {0xb8, 0x0= 1, 0x21,0x8a, 0x27, 0xca, 0x75, 0x91}} + gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, = 0x68, 0xBA, 0x87, 0x3E, 0x6C}} + gCio2ConfigGuid =3D {0xFBC4C192, 0x789D, 0x4038, {0x90, 0xE1, 0x5E, 0x= 6D, 0xFD, 0x52, 0xAF, 0x8A}} + gDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x4= 2, 0x9C, 0x4F, 0x17, 0xBD}} + gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA= 3, 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}} + gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2,= 0xBF, 0x4E, 0x91, 0xC3, 0x4C}} + gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0x= E7, 0x7A, 0xA1, 0x4E, 0x87, 0x76}} + gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x5= 8, 0xEA, 0xAC, 0x5E, 0x29, 0x78}} + gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5= D, 0xB8, 0x1C, 0x57, 0x40}} + gLanConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1= A, 0x59, 0x2B, 0x14, 0x2F}} + gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70= , 0xC4, 0x85, 0xFB, 0xA8, 0x0D}} + gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0x= D3, 0xD3, 0x85, 0xFF, 0x07}} + gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1= , 0x0D, 0xF9, 0xE3, 0xA7}} + gSdCardConfigGuid =3D {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x= 93, 0xF5, 0x90, 0x50, 0x27}} + gEmmcConfigGuid =3D {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C= , 0x68, 0xA4, 0xB2, 0x1D}} + gUfsConfigGuid =3D {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51,= 0x2F, 0x2F, 0x8F, 0xA7}} + gEmmcDxeConfigGuid =3D {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE, 0= xF9, 0x0C, 0xB0, 0xC8, 0x18}} + gPort61ConfigGuid =3D {0x59913475, 0x1960, 0x4099, {0x80, 0xEC, 0xAF, = 0xC7, 0xCF, 0x5F, 0x9F, 0xAC}} + gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x5= 4, 0x20, 0x94, 0x05, 0xD0}} + gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA= , 0x09, 0xE5, 0x78, 0x3A, 0xDB}} + gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x7= 3, 0x8C, 0xD2, 0x23, 0x10, 0x96}} + gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x4= 0, 0x26, 0xCA, 0x34, 0x57}} + gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46,= 0x11, 0xF9, 0x23, 0x9E, 0xAE}} + gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xF= B, 0xB7, 0x66, 0x8B, 0xDE}} + gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xA= A, 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}} + gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE= , 0x5F, 0x4C, 0x8D, 0xF5}} + gWatchDogConfigGuid =3D {0x940EC076, 0x04AF, 0x45DA, {0xAF, 0xFA, 0x6A= , 0xEF, 0xDB, 0x2B, 0x86, 0x55}} + gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0x= F7, 0x5C, 0x4B, 0xE1, 0xE3}} + gHsuartConfigGuid =3D {0xEA329E4E, 0x1725, 0x43E0, {0xBA, 0x69, 0x67, 0= xA3, 0x76, 0x73, 0x45, 0x16}} + gHsioPcieConfigFIAWM20Guid =3D {0x92cd256c, 0xdd71, 0x4707, {0xad, 0x7= a, 0x87, 0xb3, 0xfd, 0x70, 0x08, 0x94}} + gAdrConfigGuid =3D {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xC= F, 0x97, 0x39, 0x0C, 0x65}} + gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6= , 0x56, 0x10, 0xF9, 0x86}} + gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69,= 0x43, 0xF3, 0x38, 0x31, 0x4D}} + gScsInfoHobGuid =3D {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA= , 0xE2, 0x99, 0x78, 0xB2}} + gUsb2PhyConfigGuid =3D {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC,= 0x68, 0x2D, 0xAE, 0xD3, 0xF2}} + gUsb3HsioConfigGuid =3D {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69= , 0xF9, 0xB1, 0xAC, 0x40, 0xD5}} + gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE= , 0x5F, 0x4C, 0x8D, 0xF5}} + gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC1, = 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }} + gRcPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0x= d0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gSataControllerDriverGuid =3D { 0xbb929da9, 0x68f7, 0x4035, { 0xb2, 0x2c= , 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 }} + gPchInitVariableGuid =3D { 0xe6c2f70a, 0xb604, 0x4877, { 0x85, 0xba, 0xd= e, 0xec, 0x89, 0xe1, 0x17, 0xeb }} + gPchS3ImageGuid =3D { 0x271dd6f2, 0x54cb, 0x45e6, { 0x85, 0x85, 0x8c, 0x= 92, 0x3c, 0x1a, 0xc7, 0x6 }} + gEfiSmbusArpMapGuid =3D { 0x707be83e, 0x0bf6, 0x40a5, { 0xbe, 0x64, 0x34= , 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }} + mPchSataRsteProtocolGuid =3D { 0x3ea94650, 0xfc5b, 0x11e1, {0xa2, 0x1f, = 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}} + mPchSataRstProtocolGuid =3D { 0xfc5f2e00, 0xfc68, 0x11e1, {0xa2, 0x1f, 0= x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}} + gPchInitPeiVariableGuid =3D { 0xa31b27a4, 0xcae6, 0x48ff, {0x8c, 0x5a, 0= x29, 0x42, 0x21, 0xe6, 0xf3, 0x89 }} + gChipsetInitInfoHobGuid =3D { 0xc1392859, 0x1f65, 0x446e, {0xb3, 0xf5, 0= x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4}} + gPchOemSmmGuid =3D { 0xc0cfaf36, 0x4296, 0x40ba, {0xa9, 0xf1, 0x77, 0x10= , 0x9b, 0x91, 0xce, 0x19}} + gPchPowerCycleResetGuid =3D { 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd= , 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 }} + gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x= 18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} + gPchGlobalResetWithEcGuid =3D { 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x= 3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 }} +#S3 add + gPchS3CodeInLockBoxGuid =3D { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4,= 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}} + gPchS3ContextInLockBoxGuid =3D { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f= , 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}} +#S3 add +# gMeBiosExtensionSetupGuid =3D { 0x1bad711c, 0xd451, 0x4241, { 0xb1= , 0xf3, 0x85, 0x37, 0x81, 0x2e, 0xc, 0x70 } } // SERVER_BIOS_FLAG +# gAmtForcePushPetPolicyGuid =3D { 0xacc8e1e4, 0x9f9f, 0x4e40, { 0xa5= , 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 } } // SERVER_BIOS_FLAG + gEfiAcpiVariableGuid =3D { 0xaf9ffd67, 0xec10, 0x488a, { 0x9d, 0= xfc, 0x6c, 0xbf, 0x5e, 0xe2, 0x2c, 0x2e }} + gEfiCommonPkgTokenSpaceGuid =3D { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0= xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }} + gPchPolicyHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0= x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} + gPchChipsetInitHobGuid =3D { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0= xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }} + gWdtHobGuid =3D { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0= xb7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }} + gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gPchPsfErrorHobGuid =3D { 0x9ee875f4, 0xa463, 0x4b29, { 0x88, 0= x79, 0x11, 0x2a, 0x4d, 0x05, 0x47, 0x7f }} + gHdAudioPreMemConfigGuid =3D { 0xD38F1E2B, 0x21B3, 0x43D1, { 0x9F, 0= xA8, 0xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88 }} + gIshPreMemConfigGuid =3D { 0x7C24E649, 0xC1F0, 0x4CF9, { 0x87, 0= x96, 0xE7, 0xA0, 0xEE, 0x34, 0x43, 0xF8 }} + + gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0= xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }} + +## +## PreMem Performance +## + gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, = 0x3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}} + gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, = 0x29, 0x0B, 0x38, 0xC5, 0x32, 0x25}} + gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, = 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}} + gPlatformGpioConfigGuid =3D {0xd66acbe3, 0x3293, 0x4ba1, {0xb0, 0x0b, = 0xb3, 0x8f, 0x64, 0x8d, 0x8d, 0x5e}} +# SouthCluster End +# + + gSocketPkgFpgaGuid =3D { 0x624b948f, 0x= 6eba, 0x4dfd, { 0x9d, 0xda, 0x10, 0xb0, 0x07, 0x3a, 0x37, 0x35 } } # {624B= 948F-6EBA-4DFD-9DDA-10B0073A3735} + gFpgaSocketVariableGuid =3D { 0x75839b0b, 0x= 0a99, 0x4233, { 0x8a, 0xa4, 0x38, 0x66, 0xf6, 0xce, 0xf4, 0xb3 } } # {7583= 9B0B-0A99-4233-8AA4-3866F6CEF4B3} + gFpgaSocketPkgListGuid =3D { 0xa3922b1a, 0x= 35e4, 0x4132, { 0x9c, 0xed, 0x91, 0xd3, 0x8d, 0x71, 0x71, 0xd8 } } # {A392= 2B1A-35E4-4132-9CED-91D38D7171D8} + gFpgaFormSetGuid =3D { 0x22819110, 0x= 7F6F, 0x4852, { 0xB4, 0xBB, 0x13, 0xA7, 0x70, 0x14, 0x9B, 0x0C } } # {2281= 9110-7F6F-4852-B4BB-13A770149B0C} + gFpgaSocketHobGuid =3D { 0xd759c710, 0x= 49ea, 0x4d26, { 0x9f, 0x7c, 0xde, 0x10, 0x64, 0x87, 0x6e, 0x2f } } # {D759= C710-49EA-4D26-9F7C-DE1064876E2F} + gFpgaSocketBbsGbeGuid =3D { 0x28b225ef, 0x= e6b1, 0x4dc0, { 0x8d, 0x4d, 0x49, 0xef, 0xc8, 0x57, 0xcc, 0xdf } } # {28B2= 25EF-E6B1-4dc0-8D4D-49EFC857CCDF} + gFpgaSocketBbsPcieGuid =3D { 0xe4d662cd, 0x= 7ccb, 0x4cb5, { 0xae, 0xce, 0x4e, 0xea, 0x39, 0x8f, 0xf8, 0xe4 } } # {E4D6= 62CD-7CCB-4cb5-AECE-4EEA398FF8E4} + gFpgaSocketN4PeGuid =3D { 0x78d87f9a, 0x= 321e, 0x4a07, { 0x87, 0x5f, 0x8d, 0x83, 0xa3, 0xd0, 0x6e, 0x59 } } # {78D8= 7F9A-321E-4a07-875F-8D83A3D06E59} + gFpgaErrorRecordGuid =3D { 0x09fdcb1e, 0x= e08b, 0x4b64, { 0x89, 0x0c, 0x70, 0xe3, 0x17, 0x4b, 0xe0, 0x7a } } + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } + gEfiAfterPlatformLocksEventGuid =3D { 0x1c5fdaf2, 0x= 9fb3, 0x431b, { 0x8e, 0xcd, 0xb7, 0xd3, 0x5c, 0xbe, 0xfa, 0xe9 } } + gEfiPlatformTxtDeviceMemoryGuid =3D { 0x73d1d476, 0x= a7c9, 0x4efd, { 0x8f, 0x8b, 0xd5, 0x32, 0xef, 0x38, 0x17, 0x08 } } + gEmulationHobGuid =3D { 0xbea8d1f4, 0x= c2fd, 0x4d74, { 0xbd, 0xf2, 0xb7, 0xb5, 0x40, 0x34, 0xd7, 0xc0 } } # {BEA8= D1F4-C2FD-4d74-BDF2-B7B54034D7C0} + gEmulationDfxVariableGuid =3D { 0x41266ead, 0x= 701c, 0x461f, { 0xa6, 0xb1, 0x42, 0xcd, 0x38, 0x7d, 0x1a, 0x6e } } # {41266= EAD-701C-461f-A6B1-42CD387D1A6E} + gEmulationFormSetGuid =3D { 0x52b3b56e, 0x= e716, 0x455f, { 0xa5, 0xe3, 0xb3, 0x14, 0xf1, 0x8e, 0x6c, 0x5d } } # {52B3= B56E-E716-455f-A5E3-B314F18E6C5D} + gCsrPseudoOffsetTableGuid =3D { 0x5921E6F4, 0x= D672, 0x45CA, { 0xBF, 0xF1, 0x34, 0x47, 0xA4, 0x1E, 0x21, 0x4A } } + gEfiKtiEparamInfoGuid =3D { 0xaac08905, 0x= 6700, 0x48aa, { 0xb8, 0x8c, 0xca, 0x1e, 0x53, 0xc5, 0x5d, 0xa0 } } # {AAC0= 8905-6700-48aa-B88C-CA1E53C55DA0} + gIioSiPolicyHobGuid =3D { 0x353bb17b, 0x= 74ac, 0x4895, { 0xb4, 0x61, 0x2c, 0x8c, 0x97, 0x68, 0x30, 0xe6 } } + gIioPcieConfigGuid =3D { 0x5cd68841, 0x= 16c0, 0x4f8e, { 0xba, 0xb, 0x94, 0x7c, 0xa3, 0x47, 0xb7, 0xa0 } } + gPeiPciMmioResMapHobGuid =3D { 0xd8c98608, 0x= 40c4, 0x4ba6, { 0x85, 0x04, 0x1d, 0x23, 0xf2, 0xa5, 0x4b, 0x4e } } # {d8c9= 8608-40c4-4ba6-8504-1d23f2a54b4e} + gImr2BaseAddressHobGuid =3D { 0xea9184fe, 0x= 3bec, 0x436d, { 0x92, 0x14, 0x3f, 0x8c, 0xb5, 0x64, 0xdf, 0xfe } } # {EA91= 84FE-3BEC-436d-9214-3F8CB564DFFE} + +## +## DMA Protection Event GUID +## + gEfiDmaProtectionDisablingEventGroupGuid =3D { 0x05e32339, 0x= 92d4, 0x440e, { 0xb3, 0xb3, 0x9c, 0x9c, 0xbe, 0x79, 0xd3, 0x7f } } # {05E3= 2339-92D4-440e-B3B3-9C9CBE79D37F} + + +## +## Me +## + gAmtForcePushPetPolicyGuid =3D { 0xacc8e1e4, 0x= 9f9f, 0x4e40, { 0xa5, 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 } } + gAmtForcePushPetVariableGuid =3D { 0xd7ac94af, 0x= a498, 0x45ec, { 0xbf, 0xa2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b } } + gMeBiosExtensionSetupGuid =3D { 0xaf013532, 0x= c828, 0x4fbd, { 0x20, 0xae, 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e } } + gMePlatformReadyToBootGuid =3D { 0x03fdf171, 0x= 1d67, 0x4ace, { 0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74 } } + gMeSsdtAcpiTableStorageGuid =3D { 0x9a8f82d5, 0x= 39b1, 0x48da, { 0x92, 0xdc, 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6 } } + gAmtPetQueueHobGuid =3D { 0xca0801d3, 0x= afb1, 0x4dec, { 0x9b, 0x65, 0x93, 0x65, 0xec, 0xc7, 0x93, 0x6b } } + gAmtForcePushPetHobGuid =3D { 0x4efa0db6, 0x= 26dc, 0x4bb1, { 0xa7, 0x6f, 0x14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c } } + gMeDataHobGuid =3D { 0x1e94f097, 0x= 5acd, 0x4089, { 0xb2, 0xe3, 0xb9, 0xa5, 0xc8, 0x79, 0xa7, 0x0c } } + gPciImrHobGuid =3D { 0x49b1eac3, 0x= 0cd6, 0x451e, { 0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35, 0x86 } } + gTpm2AcpiTableStorageGuid =3D { 0x7d279373, 0x= eecc, 0x4d4f, { 0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a } } + gMeBiosPayloadHobGuid =3D { 0x992c52c8, 0x= bc01, 0x4ecd, { 0x20, 0xbf, 0xf9, 0x57, 0x16, 0x0e, 0x9e, 0xf7 } } + gEfiTouchPanelGuid =3D { 0x91b1d27b, 0x= e126, 0x48d1, { 0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8, 0x83, 0x62 } } + gMeFwHobGuid =3D { 0x52885e62, 0x= 4c4d, 0x9546, { 0x2d, 0xba, 0x2a, 0x84, 0x89, 0xee, 0xa8, 0xa3 } } + gMePeiPreMemConfigGuid =3D { 0x67ed113b, 0x= d4ab, 0x43f5, { 0x9c, 0x3c, 0x35, 0x44, 0x15, 0xaa, 0x47, 0x5c } } + gMePeiConfigGuid =3D { 0x9bad5628, 0x= 657b, 0x48e3, { 0xb1, 0x11, 0xc3, 0xb9, 0xeb, 0xea, 0xee, 0x17 } } + gMeDxeConfigGuid =3D { 0xad08bacc, 0x= 4906, 0x4d9b, { 0xbe, 0xd1, 0x81, 0xa5, 0x2c, 0x13, 0xdb, 0xf8 } } + gAmtPeiConfigGuid =3D { 0x7254546a, 0x= ace3, 0x4a32, { 0x9a, 0xc2, 0xf0, 0xcc, 0x28, 0x4e, 0x1e, 0x4d } } + gAmtDxeConfigGuid =3D { 0x3f12ab6b, 0x= b04d, 0x4824, { 0xbf, 0xb6, 0x3e, 0xe7, 0x5d, 0x02, 0x0b, 0x84 } } + gIvmProtocolGuid =3D { 0x3C4852D6, 0x= D47B, 0x4F46, { 0xB0, 0x5E, 0xB5, 0xED, 0xC1, 0xAA, 0x44, 0x0E } } + gSdmProtocolGuid =3D { 0xDBA4D603, 0x= D7ED, 0x4931, { 0x88, 0x23, 0x17, 0xAD, 0x58, 0x57, 0x05, 0xD5 } } + gRtmProtocolGuid =3D { 0x5565A099, 0x= 7FE2, 0x45C1, { 0xA2, 0x2B, 0xD7, 0xE9, 0xDF, 0xEA, 0x9A, 0x2E } } + gSvmProtocolGuid =3D { 0xF47ACC04, 0x= D94B, 0x49CA, { 0x87, 0xA6, 0x7F, 0x7D, 0xC0, 0x3F, 0xBA, 0xF3 } } + gMeEopDoneHobGuid =3D { 0x247323af, 0x= c8f1, 0x4b8c, { 0x90, 0x87, 0xaa, 0x4b, 0xa7, 0xb7, 0x6d, 0x6a } } + gMePreMemPolicyHobGuid =3D { 0xe6de74a5, 0x= 021b, 0x4f78, { 0xa3, 0xcd, 0x34, 0xd6, 0x7e, 0xe4, 0x82, 0xbf } } + gMePolicyHobGuid =3D { 0x0341cf17, 0x= bc8f, 0x4a20, { 0xac, 0x28, 0x6c, 0x3c, 0x32, 0x4c, 0xd4, 0x17 } } + gAmtPolicyHobGuid =3D { 0x703eb2cd, 0x= 5ca8, 0x4233, { 0x9d, 0xa3, 0x0d, 0x2d, 0x57, 0xe6, 0x73, 0x34 } } + gAmtMebxDataGuid =3D { 0x912e1538, 0x= 371d, 0x4ea6, { 0xa8, 0x41, 0xd7, 0x6a, 0x08, 0x93, 0x3a, 0x70 } } + + gEfiMeRcVariableGuid =3D { 0x2b26358d, 0x= f899, 0x41c4, { 0x9b, 0xc2, 0x82, 0xa3, 0x38, 0xb9, 0x93, 0xd8 }} + gSpsInfoHobGuid =3D { 0x489d2a71, 0x= ba4a, 0x444c, { 0x9f, 0xe2, 0xa6, 0xb7, 0xe5, 0xcd, 0x78, 0x47 }} + gEfiSpsAcpiTableLocatorGuid =3D { 0x4896840D, 0x= 46BB, 0x412B, { 0xA3, 0x0A, 0xA6, 0x2A, 0xBF, 0xB3, 0x68, 0x2F }} + gIccGuid =3D { 0x64192dca, 0x= d034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 }} + gEfiMePkgTokenSpaceGuid =3D { 0x731d14ec, 0x= 7f7c, 0x4403, { 0x8c, 0x02, 0x96, 0xac, 0x8c, 0x33, 0x5c, 0x2b }} + gConsoleLockGuid =3D { 0x368cda0d, 0x= cf31, 0x4b9b, { 0x8c, 0xf6, 0xe7, 0xd1, 0xbf, 0xff, 0x15, 0x7e }} + gMeInfoSetupGuid =3D { 0x78259433, 0x= 7b6d, 0x4db3, { 0x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d }} + gMeSetupVariableGuid =3D { 0x5432122d, 0x= d034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 }} + gMeTypeHobGuid =3D { 0xc0bc8ed5, 0x= 078c, 0x49c7, { 0x9c, 0xf9, 0xf8, 0x73, 0xff, 0xe5, 0x50, 0x81 }} + gAmtConsoleVariableGuid =3D { 0xd9aaf1e5, 0x= cd14, 0x4312, { 0x9c, 0xa4, 0x85, 0xc3, 0x0a, 0xde, 0x43, 0xe8 }} + gMeUefiFwHealthStatusHobGuid =3D { 0xa9bac5d8, 0x= 27a9, 0x4a32, { 0x9c, 0xda, 0xd3, 0xfb, 0x9d, 0x93, 0xac, 0x65 }} + gMeUmaInfoHobGuid =3D { 0xf70269e6, 0x= c201, 0x4d18, { 0xb7, 0x4d, 0xb8, 0x32, 0x1e, 0x3a, 0xff, 0xdc }} + + gSpsPeiConfigGuid =3D { 0x027be940, 0x= bd58, 0x48f4, { 0x80, 0x19, 0x34, 0xc5, 0xee, 0x79, 0xb8, 0xda }} + gSpsDxeConfigGuid =3D { 0xf9373326, 0x= da54, 0x4e31, { 0x9a, 0x08, 0x06, 0x7d, 0xcb, 0x06, 0x16, 0xbd }} + gSpsPolicyHobGuid =3D { 0xc87d4e27, 0x= 8023, 0x4a7e, { 0x8e, 0xc3, 0xa6, 0x3e, 0x3e, 0xb2, 0x94, 0xdc }} + gSpsSmmWatchdogGuid =3D { 0xf7ec1c4b, 0x= 1683, 0x403b, { 0xa8, 0x76, 0xfd, 0x3b, 0x13, 0x0f, 0x1b, 0x55 }} + +## +## IE +## + gEfiIeRcVariableGuid =3D { 0xd8b85944, 0x= 13b2, 0x41f9, { 0x85, 0xc6, 0xa0, 0xb1, 0x33, 0x78, 0x3e, 0x40 }} + gIeHobGuid =3D { 0x081077fa, 0x= 577d, 0x43b8, { 0xa8, 0xac, 0x9e, 0x0d, 0x31, 0x65, 0xf4, 0xee }} + + gUboxIpInterfaceCpuGuid =3D { 0xfedb4f83, 0x= 3be3, 0x44b2, { 0x8d, 0x29, 0x72, 0xad, 0xd0, 0xb6, 0x3c, 0x18 }} + gUboxIpInterfacePcieGen4Guid =3D { 0x32c49b21, 0x= d303, 0x4cfe, { 0xb7, 0xf5, 0xa1, 0x5f, 0x8f, 0x65, 0xff, 0x6e }} + + gKtiIpInterfaceCpuGuid =3D { 0xCC75DACB, 0x= A115, 0x4FAD, { 0xA7, 0xC6, 0x63, 0x0D, 0xC9, 0xA3, 0x62, 0xB7 }} + gKtiIpInterfacePcieGen4Guid =3D { 0xe899d31e, 0x= aff8, 0x49cb, { 0x8c, 0x1d, 0x58, 0x94, 0x3b, 0x3a, 0x59, 0x72 }} + + gPcuIpInterfaceCpuGuid =3D { 0x86b9e6bc, 0x= acb0, 0x44cd, { 0xa4, 0xb0, 0xda, 0x8d, 0x7d, 0xba, 0xb9, 0xcc }} + gPcuIpInterfacePcieGen4Guid =3D { 0x82682b43, 0x= eedb, 0x49e8, { 0xa2, 0x30, 0xfa, 0x15, 0x36, 0x52, 0x6a, 0x2a }} + + gIioIpInterfaceCpuGuid =3D { 0x96e629a1, 0x= 4f87, 0x434c, { 0xac, 0xa3, 0xef, 0x27, 0xca, 0x1a, 0x5f, 0x5a }} + gIioIpInterfacePcieGen4Guid =3D { 0x0c343cae, 0x= 84f7, 0x4062, { 0xa5, 0x17, 0x1d, 0x5f, 0xdb, 0xc8, 0x5c, 0xa5 }} + + gChaIpInterfaceCpuGuid =3D { 0xaa83b114, 0x= b7c9, 0x4cfa, { 0xb9, 0x8e, 0x8d, 0x7a, 0x26, 0xbb, 0x8c, 0x69 }} + gChaIpInterfacePcieGen4Guid =3D { 0xe2e90cf1, 0x= 214c, 0x469d, { 0xb5, 0xcf, 0xc7, 0xb4, 0x86, 0x7f, 0xf1, 0xf8 }} + + gM2UPcieIpInterfaceCpuGuid =3D { 0x793a789f, 0x= 9764, 0x48fd, { 0xb8, 0xc9, 0xac, 0xdd, 0xfa, 0x5b, 0x4e, 0x26 }} + gM2UPcieIpInterfacePcieGen4Guid =3D { 0x5032faf9, 0x= 6c56, 0x4941, { 0x94, 0x4d, 0x1f, 0xe7, 0x63, 0xe6, 0xab, 0x5f }} + + gKtiSimHelpInterfaceCpuGuid =3D { 0xf2231017, 0x= dad7, 0x4697, { 0xaa, 0xb7, 0xd8, 0x2c, 0x48, 0x4f, 0xe5, 0x7f }} + gKtiSimHelpInterfacePcieGen4Guid =3D { 0x429d26f3, 0x= 8a2d, 0x4fba, { 0xbf, 0x12, 0x8d, 0x9d, 0xe4, 0xef, 0xf9, 0x6d }} + + gPcuMailBoxIpInterfaceCpuGuid =3D { 0x52ee6a0d, 0x= 2c64, 0x4865, { 0xa8, 0xf5, 0x2c, 0x75, 0x81, 0xf7, 0xf9, 0x2a }} + gPcuMailBoxIpInterfacePcieGen4Guid =3D { 0xb096b416, 0x= 520a, 0x42f0, { 0xa4, 0xb3, 0x53, 0x1d, 0x7d, 0xd5, 0x06, 0xc5 }} + gChipsetLockDoneGuid =3D { 0x76FAEB39, 0x= 0DDA, 0x4979, { 0xBE, 0x7B, 0x47, 0x41, 0x05, 0x05, 0x17, 0x81 }} + + gFpgaIpInterfaceGuid =3D { 0x69FC448A, 0x= 28FC, 0x40E3, { 0xAB, 0x2A, 0x70, 0x22, 0xC4, 0x36, 0xCF, 0xED }} + gMsmIpInterfaceCpuGuid =3D { 0x6ebabfae, 0x= cfd2, 0x4fac, { 0x96, 0xa6, 0x8b, 0x2c, 0x0f, 0xc3, 0x08, 0xbd }} + gSpkIpInterfaceCpuGuid =3D { 0x3edf7f6d, 0x= 2061, 0x4941, { 0xb6, 0x31, 0xdd, 0x40, 0xa0, 0xba, 0xcb, 0xad }} + gBiosDoneGuid =3D { 0xaf4c5733, 0x= f4c3, 0x48ba, { 0xa7, 0x48, 0x87, 0x3e, 0x8c, 0xee, 0xd2, 0xf4 }} + +# +# VTD HOB GUIDs Begin +# + ## HOB GUID to get memory information after MRC is done. The hob data wi= ll be used to set the PMR ranges + gVtdPmrInfoDataHobGuid =3D {0x6fb61645, 0xf= 168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } +# +# VTD HOB GUIDs End +# + +[Ppis] + +## +## MdeModulePkg +## +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0= x54, 0xd2, 0xe1, 0x32, 0x3d}} +gPeiSmmAccessPpiGuid =3D {0x268f33a9, 0xcccd, 0x48be, {0x88, 0x17, 0x86,= 0x05, 0x3a, 0xc3, 0x2e, 0xd6}} +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7= , 0x43, 0x05, 0xce, 0x74, 0xc5}} + + gPeiBaseMemoryTestPpiGuid =3D { 0xb6ec423c, 0x= 21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 }} + gPeiPlatformMemorySizePpiGuid =3D { 0x9a7ef41e, 0x= c140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 }} + gEfiPeiMpServicesPpiGuid =3D { 0xee16160a, 0x= e8be, 0x47a6, { 0x82, 0x0a, 0xc6, 0x90, 0x0d, 0xb0, 0x25, 0x0a }} + gSgxInitPpiGuid =3D { 0xD8163BA4, 0x= EFA8, 0x411E, { 0xA0, 0x32, 0x05, 0x0D, 0x56, 0xE9, 0xAF, 0x74 }} + + gEndOfSiInitPpiGuid =3D { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E= , 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} + gMeBeforeDidSentPpiGuid =3D {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5, 0x= 5e, 0xf6, 0xcd, 0x6e, 0x4c, 0x87}} + +## +## Common +## + gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0= x84, 0x8c, 0x5e, 0x86, 0x70}} + gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x9= 7, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} + gPeiOemIioHooksPpiGuid =3D { 0x5265657a, 0xbfac, 0x468e, { 0xae,= 0x81, 0xc, 0x40, 0x7a, 0x1, 0xec, 0x37 }} + +# +# KTI RC +# + gEfiAfterKtiRcGuid =3D { 0x6f079b18, 0x0591, 0x4554, { 0xbb, = 0x8a, 0xfb, 0x95, 0xb1, 0xa5, 0x3f, 0x6b }} + +# +# Security +# + gSecurityAppSgx3v0PpiGuid =3D { 0x4358eeb8, 0xbebf, 0x4f33, { = 0xb5, 0xe7, 0x3b, 0xcb, 0x75, 0xb7, 0xc2, 0x1c }} + gSecurityFruCpuFeatureSgx3v0PpiGuid =3D { 0xa56c1a20, 0x9011, 0x4e1c, { = 0x8d, 0x8a, 0x31, 0xff, 0x0b, 0xdf, 0x6c, 0x7d }} + +# +# SouthCluster +# + gPchPmcXramOffsetDataPpiGuid =3D { 0xc1392859, 0x1f65, 0x446e, { 0xa3, = 0xf6, 0x85, 0x36, 0xfc, 0xc7, 0xd1, 0xc4 }} + gPchPlatformPolicyPpiGuid =3D { 0xdfe2b897, 0xe8e, 0x4926, { 0xbc, = 0x69, 0xe5, 0xed, 0xd3, 0xf9, 0x38, 0xe1 }} + gPchIpInfoPpiGuid =3D { 0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, = 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d, 0xa5 }} + gPeiUsbControllerPpiGuid =3D { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, = 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }} + gPchUsbPolicyPpiGuid =3D { 0xc02b0573, 0x2b4e, 0x4a31, { 0xa3, = 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c }} + gPchInitPpiGuid =3D { 0x511e0280, 0x83ae, 0x4a21, { 0xbd, = 0x57, 0x57, 0xe3, 0xa4, 0x93, 0x12, 0x17 }} + gWdtPpiGuid =3D { 0xF38D1338, 0xAF7A, 0x4FB6, { 0x91, = 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D }} + gPchDmiTcVcMapPpiGuid =3D { 0xed097352, 0x9041, 0x445a, { 0x80, = 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 }} + gPeiSmbusPolicyPpiGuid =3D { 0x63b6e435, 0x32bc, 0x49c6, { 0x81, = 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }} + gPchResetCallbackPpiGuid =3D { 0x17865dc0, 0xb8b, 0x4da8, { 0x8b, = 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d }} + gPchResetEndOfPeiTypeGuid =3D { 0x330d4002, 0xe366, 0x4272, { 0xb5, = 0xdd, 0x41, 0x61, 0x56, 0xb0, 0x5d, 0x20 }} + gPchPeiInitDonePpiGuid =3D { 0x1edcbdf9, 0xffc6, 0x4bd4, { 0x94, = 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 }} + gPchResetPpiGuid =3D { 0x433e0f9f, 0x5ae, 0x410a, { 0xa0, = 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac }} + gPchHdaVerbTablePpiGuid =3D { 0x220307a4, 0x3670, 0x42a5, { 0xaa, = 0x1, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gPchPcieDeviceTablePpiGuid =3D { 0xaf4a1998, 0x4949, 0x4545, { 0x9c, = 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56 }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x2096, 0x4283, { 0x9D, = 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gSaPlatformPolicyPpiGuid =3D { 0x573eaf99, 0xf445, 0x46b5, { 0xa5, = 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 }} + gPeiSmmControlPpiGuid =3D { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, = 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + gPchHsioPtssTablePpiGuid =3D { 0x220307a4, 0x3671, 0x42b5, { 0xaa, = 0x02, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }} + gDirtyWarmResetSignalGuid =3D { 0x24b9a592, 0x4cfc, 0x4c8f, { 0x86, = 0xf4, 0x87, 0x28, 0x2d, 0x7f, 0x9e, 0x9c }} + gDirtyWarmResetGuid =3D { 0xe60fe263, 0xac2b, 0x43d6, { 0xb3, = 0xc7, 0x0d, 0x9d, 0xdc, 0x5a, 0x99, 0x1c }} + gPmcDwrPreMemConfigGuid =3D { 0x1fb7cf2c, 0xfe7c, 0x40f7, { 0x90, = 0xf9, 0x28, 0xdd, 0x63, 0x28, 0xae, 0x1a }} + gPchSpiPpiGuid =3D { 0xdade7ce3, 0x6971, 0x4b75, { 0x82, = 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d }} + gPchHsioChipsetInitSusTblDataPpiGuid =3D { 0x97ed4e5d, 0x01a5, 0x4a3c, {= 0xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }} + gPchPostMemoryConfigurationDonePpi =3D { 0x68607f46, 0xad96, 0x4364, { 0= xb1, 0x83, 0x4e, 0x6d, 0x98, 0xed, 0x79, 0x7b }} +# +# SouthCluster End +# + gFpgaInitPpiGuid =3D { 0x325e1442, 0x9be1, 0x498b, { 0xb0, = 0x07, 0xbf, 0x4c, 0x38, 0xbd, 0xb0, 0xec }} # {325E1442-9BE1-498b-B007-BF4= C38BDB0EC} + gPeiTxtScleanPpiGuid =3D { 0x4d5640e5, 0x2702, 0x4df8, { 0x88, = 0xf4, 0x56, 0x48, 0x86, 0xfc, 0x43, 0xdc }} + gIioSiPolicyPpiGuid =3D { 0xa6231b31, 0xd78c, 0x4a32, { 0x96, = 0x15, 0x56, 0x6c, 0xb6, 0xd1, 0xb1, 0xd7 }} + gIioPolicyPpiGuid =3D { 0x7960448a, 0x39ab, 0x4808, { 0xb0, = 0xf6, 0x5f, 0xe0, 0x9f, 0x81, 0x6d, 0xe0 }} + gIioEarlyInitSignalPpiGuid =3D { 0x0f6539bb, 0x236d, 0x4f80, { 0x8c, = 0x1e, 0x5a, 0x7e, 0x8f, 0x00, 0xd1, 0x30 }} # {0F6539BB-236D-4f80-8C1E-5A7= E8F00D130} + gUpiSiPolicyPpiGuid =3D { 0x87cce352, 0xf86e, 0x4ee8, { 0x89, = 0xee, 0x31, 0xc9, 0x85, 0x7d, 0x61, 0x99 }} + gReferenceCodePolicyPpiGuid =3D { 0x6f39dbf1, 0x853f, 0x4545, { 0xad, = 0xb1, 0x30, 0x15, 0xd9, 0x69, 0x4a, 0xf9 }} # {6f39dbf1-853f-4545-adb1-301= 5d9694af9} + gRasRcPolicyPpiGuid =3D { 0xfbceb643, 0xe18b, 0x4ade, { 0x9d, = 0x14, 0x9f, 0xf0, 0x5c, 0x14, 0xff, 0x5c }} + +# +# Me +# + gAmtStatusCodePpiGuid =3D { 0xca18955b, 0x= 4ee9, 0xd113, { 0xde, 0x06, 0x62, 0xad, 0xc2, 0x7f, 0x23, 0x7e } } + gHeciPpiGuid =3D { 0xd14319e2, 0x= 407a, 0x9580, { 0x8d, 0xe5, 0x51, 0xa8, 0xff, 0xc6, 0xd7, 0xd7 } } + gMbpSensitivePpiGuid =3D { 0xed7c9ce9, 0x= 5912, 0x4807, { 0xec, 0x90, 0x22, 0x18, 0xbc, 0x7b, 0xfc, 0x6c } } + gHeci3IntegratedTouchControllerGuid =3D { 0x3e8d0870, 0x= 271a, 0x4208, { 0x8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04 } } + gMeDidSentPpiGuid =3D { 0x45dc3106, 0x= ef67, 0x4c71, { 0xb0, 0xf0, 0x97, 0x15, 0x9c, 0x7d, 0xbb, 0x7c } } + + gPeiHeci2PpiGuid =3D { 0xEE0EA811, 0x= FBD9, 0x4777, { 0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74 }} + gPlatformMeHookPpiGuid =3D { 0xe806424f, 0x= d425, 0x4b1a, { 0xbc, 0x26, 0x5f, 0x69, 0x03, 0x89, 0xa1, 0x5a }} + gMeUmaPpiGuid =3D { 0x0100c1c8, 0x= 61d9, 0x498d, { 0xa9, 0xe2, 0x27, 0xe4, 0x92, 0xbe, 0x0e, 0xac }} + gSpsPolicyPpiGuid =3D { 0xcefb6938, 0x= 7fae, 0x4d54, { 0xbb, 0xe3, 0xe6, 0xf2, 0xf8, 0x43, 0x32, 0x72 }} + gMePolicyPpiGuid =3D { 0x1c46d34a, 0x= 4163, 0x02dd, { 0x56, 0x69, 0x2d, 0xa7, 0xca, 0x93, 0xeb, 0xf3 }} + gAmtPolicyPpiGuid =3D { 0x2549016d, 0x= 2b17, 0x4d00, { 0xb5, 0xa4, 0x1d, 0x44, 0x3a, 0x01, 0x38, 0xf8 }} + gSpsHwChangePpiGuid =3D { 0x6b30ce48, 0x= c7c7, 0x4aab, { 0x89, 0x47, 0xd9, 0xcb, 0xbe, 0xac, 0x28, 0x38 }} +# +# IE +# + gPeiIeHeciPpiGuid =3D { 0xaa40440f, 0x= d572, 0x48f9, { 0xb8, 0x24, 0x35, 0xb7, 0x7d, 0xf2, 0x63, 0x32 }} + gPeiIePlatformPolicyPpiGuid =3D { 0x8f685891, 0x= 4e6f, 0x445c, { 0xbb, 0x9e, 0xe5, 0x7a, 0x28, 0xfa, 0x53, 0xa0 }} + +# +# VTD PPIs Begin +# + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0x= f191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } +# +# VTD PPIs End +# + +[Protocols] + gEfiIioUdsProtocolGuid =3D { 0xa7ced760, 0x= c71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb } } + gEfiIioSystemProtocolGuid =3D { 0xddc3080a, 0x= 2740, 0x4ec2, { 0x9a, 0xa5, 0xa0, 0xad, 0xef, 0xd6, 0xff, 0x9c } } + gEfiCrystalRidgeGuid =3D { 0x22b5fc7e, 0x= 4ea8, 0x480a, { 0x91, 0xb0, 0xe6, 0xe9, 0xa8, 0x49, 0x3d, 0x7f } } + gEfiCrystalRidgeSmmGuid =3D { 0x558d5f05, 0x= cd51, 0x48ee, { 0xa3, 0xd2, 0x76, 0xba, 0xa0, 0x7c, 0x8e, 0xa0 } } + gJedecNvdimmSmmProtocolGuid =3D { 0xf47ef644, 0x= 01f5, 0x4ee3, { 0xb0, 0x79, 0x4d, 0x90, 0xf4, 0x7f, 0x35, 0x95 } } + gEfiDcpmmProtocolGuid =3D { 0x25E78B4B, 0x= EEF6, 0x4FDD, { 0x9D, 0xFA, 0x07, 0x88, 0x33, 0x7F, 0x77, 0xC2 } } + gDxeEnhancedSpeedstepProtocolGuid =3D { 0x00e98021, 0x= f4fe, 0x46cc, { 0xab, 0x2d, 0x89, 0x4c, 0x37, 0x3a, 0xfa, 0x01 } } + gNgnRasProtocolGuid =3D { 0x1a2614a0, 0x= 89e7, 0x11e3, { 0x29, 0x90, 0x31, 0xd2, 0x81, 0xfe, 0xb1, 0xdc } } + gEfiRasMpLinkProtocolGuid =3D { 0x8fdc888d, 0x= 2162, 0x4971, { 0x81, 0xc2, 0x35, 0xd3, 0xa1, 0xaa, 0x50, 0x47 } } + gEfiMemRasProtocolGuid =3D { 0xa9685ab6, 0x= 97f1, 0x437e, { 0xb9, 0x0d, 0x45, 0x96, 0xac, 0xe5, 0x02, 0xf9 } } + gEfiNfitTableUpdateProtocolGuid =3D { 0x618c4d8f, 0x= b60c, 0x4da6, { 0xba, 0x3c, 0x80, 0xbe, 0x38, 0xcc, 0xd7, 0xae } } + gAcpiPcatProtocolGuid =3D { 0xb12dc6a0, 0x= 1022, 0x46b6, { 0xb9, 0x95, 0x86, 0x46, 0xad, 0x5e, 0x5e, 0xeb } } + gNfitBindingProtocolGuid =3D { 0x97B4FA0C, 0x= 4D7E, 0xC2D0, { 0x67, 0x8E, 0xFB, 0x92, 0xE9, 0x6D, 0x2C, 0xC2 } } + gCrFwActivateProtocolGuid =3D { 0x67efc0b3, 0x= 3806, 0x42cd, { 0xbd, 0x4a, 0x6a, 0x2c, 0x02, 0xac, 0x63, 0x05 } } + gEfiQuiesceProtocolGuid =3D { 0x20d6e759, 0x= 4c4a, 0x40c0, { 0x95, 0x33, 0x2b, 0xf0, 0x06, 0x68, 0x50, 0xfd } } + gEfiErrorHandlingProtocolGuid =3D { 0x3ba7e14b, 0x= 176d, 0x4b2a, { 0x94, 0x8a, 0xc8, 0x6f, 0xb0, 0x01, 0x94, 0x3c } } + gEfiGlobalNvsAreaProtocolGuid =3D { 0x074e1e48, 0x= 8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } } + gEfiHpIoxAccessGuid =3D { 0x62652b53, 0x= 79d9, 0x4cf2, { 0xb5, 0xaa, 0xad, 0x99, 0x81, 0x0a, 0x7f, 0x17 } } + gEfiCpuHotAddDataProtocolGuid =3D { 0x330be755, 0x= fbed, 0x4f18, { 0xb9, 0xa8, 0x49, 0x58, 0x56, 0xd3, 0xd7, 0xa1 } } + gEfiCpuRasProtocolGuid =3D { 0xf084ff45, 0x= f9fa, 0x4e9e, { 0x8d, 0xff, 0xe2, 0xd7, 0x80, 0xd2, 0x2c, 0xc2 } } + gEfiIioRasProtocolGuid =3D { 0x4c7e45bc, 0x= 8a23, 0x26cd, { 0x94, 0xad, 0x5d, 0x2c, 0x26, 0x3f, 0x25, 0xfe } } + gRasClvAdddcProtocol =3D { 0x20576248, 0x= c01a, 0x439d, { 0x8c, 0xd6, 0x41, 0x8e, 0xaa, 0xbe, 0x0a, 0x29 } } + gRasClvSddcProtocol =3D { 0x5dba82cc, 0x= e80d, 0x4478, { 0xa0, 0x7d, 0x39, 0x4f, 0x36, 0x2d, 0x35, 0x24 } } + gRasClvRankSparingProtocol =3D { 0xe425cf37, 0x= e55b, 0x43d7, { 0xb2, 0xc6, 0xcd, 0xb9, 0xee, 0x8d, 0x25, 0xa5 } } + gRasClvPcieErrHandProtocol =3D { 0xb2bf51e0, 0x= 6543, 0x4acb, { 0xb0, 0x9e, 0xfd, 0x82, 0x6e, 0x1a, 0xf4, 0xc0 } } + gRasClvPatrolScrubProtocol =3D { 0x17bf72a7, 0x= ba65, 0x4837, { 0x86, 0x6d, 0x97, 0x9b, 0x2f, 0x2c, 0x07, 0x5e } } + gEfiCrystalRidgeFlushNearMemoryProtocolGuid =3D { 0xb43cced6, 0x= 4c4a, 0x4588, { 0x90, 0x48, 0xb0, 0xbb, 0x2b, 0x04, 0x01, 0xec } } + gAcpiPlatformProtocolGuid =3D { 0x6dd2a163, 0x= 5247, 0x4a5f, { 0xa3, 0xf2, 0xc1, 0xd8, 0x67, 0x0a, 0x05, 0x8a } } + gSmbiosMemInfoProtocolGuid =3D { 0xAE64455C, 0x= 09D7, 0x4C3B, { 0xA8, 0x58, 0x99, 0x07, 0x3D, 0xFF, 0x6E, 0x01 } } + gDxeKtiProtocolGuid =3D { 0x76c8dfce, 0x= 9908, 0x4fc2, { 0x98, 0x2f, 0x6c, 0x3, 0x2, 0xdc, 0x2f, 0x6c } } + gSmmKtiProtocolGuid =3D { 0x7bc172e, 0x= 2a5c, 0x47b0, { 0xaa, 0xaa, 0xaa, 0xd5, 0x30, 0xb9, 0x5b, 0x4b } } + gSmmEmulationSettingProtocol =3D { 0x93e49ce5, 0x= 789e, 0x4ffe, { 0xb9, 0x3a, 0xa8, 0x09, 0xbb, 0xdd, 0x89, 0xf4 } } + gEfiNvdimmAcpiConfigProtocolGuid =3D { 0x01d1d731, 0x= 7a00, 0x48e4, { 0xb9, 0x38, 0x1a, 0xce, 0x66, 0x5d, 0xed, 0xfb } } + gEfiNvdimmSmbusSmmInterfaceProtocolGuid =3D { 0xf8f2e702, 0x= 6f42, 0x4674, { 0xbe, 0x76, 0x9a, 0xe6, 0x73, 0x4f, 0xc3, 0x3b } } # {f8f2= e702-6f42-4674-be76-9ae6734fc33b} + gEadrProtocolGuid =3D { 0xb03adf09, 0x= 3f07, 0x4d5b, { 0x80, 0x22, 0x6a, 0x21, 0x69, 0x82, 0x2a, 0xf0 } } + gEfiPciMapProtocolGuid =3D { 0xEA63B154, 0x= C1DC, 0x485F, { 0x9D, 0x9A, 0xDC, 0x8B, 0xC0, 0xD1, 0x2A, 0x2B } } + +# +# SouthCluster +# + gPchSpiProtocolGuid =3D { 0xc7d289, 0x1347, 0x4de0,= { 0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a }} + gEfiActiveBiosProtocolGuid =3D { 0xebbe2d1b, 0x1647, 0x4bda,= { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a }} + gEfiSerialGpioProtocolGuid =3D { 0xf52c3858, 0x5ef8, 0x4d41,= { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gWdtProtocolGuid =3D { 0xB42B8D12, 0x2ACB, 0x499a,= { 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x586b, 0x47c1,= { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gEfiPchS3SupportProtocolGuid =3D { 0x2224aee3, 0x8d0b, 0x480a,= { 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 }} + gEfiPchInfoProtocolGuid =3D { 0x984eb4e9, 0x5a95, 0x41de,= { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gEfiSmmSmbusProtocolGuid =3D { 0x72e40094, 0x2ee1, 0x497a,= { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc }} + gEfiSmmIchnDispatchExProtocolGuid =3D { 0x3920405b, 0xc897, 0x44da,= { 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 }} + gEfiSmmIoTrapDispatchProtocolGuid =3D { 0xdb7f536b, 0xede4, 0x4714,= { 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d }} + gPchResetCallbackProtocolGuid =3D { 0x3a3300ab, 0xc929, 0x487d,= { 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 }} + gPchResetProtocolGuid =3D { 0xdb63592c, 0xb8cc, 0x44c8,= { 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a }} + gEfiGlobalNvsAreaProtocolGuid =3D { 0x74e1e48, 0x8132, 0x47a1, = { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }} + gPchSmmIoTrapControlGuid =3D { 0x514D2AFD, 0x2096, 0x4283,= { 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }} + gEfiPchSetTmcSrcClkProtocolGuid =3D { 0xfbaa2549, 0x53d, 0x4012, = { 0x86, 0x6c, 0x7a, 0x86, 0xcc, 0x21, 0xae, 0x21 }} + gPchPlatformPolicyProtocolGuid =3D { 0x782ee5ae, 0x586b, 0x47c1,= { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }} + gPchInfoProtocolGuid =3D { 0x984eb4e9, 0x5a95, 0x41de,= { 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 }} + gPchNvsAreaProtocolGuid =3D { 0x2E058B2B, 0xEDC1, 0x4431,= { 0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3 }} + gPchSerialIoUartDebugInfoProtocolGuid =3D { 0x2fd2b1bd, 0x0387, 0x4ec6,= { 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6 }} + gExitPmAuthProtocolGuid =3D { 0xd088a413, 0xa70, 0x4217, = { 0xba, 0x55, 0x9a, 0x3c, 0xb6, 0x5c, 0x41, 0xb3 }} + gPchSerialGpioProtocolGuid =3D { 0xf52c3858, 0x5ef8, 0x4d41,= { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }} + gEfiLoadPeImageProtocolGuid =3D { 0x5CB5C776, 0x60D5, 0x45EE,= { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }} + gEfiSmmVariableProtocolGuid =3D { 0xed32d533, 0x99e6, 0x4209,= { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }} + gDxePchPlatformResetPolicyProtocolGuid =3D { 0x45ada968, 0xa8c5, 0x4f30,= { 0xac, 0xd4, 0xf5, 0x13, 0xbc, 0xe5, 0xb0, 0xb3 }} + gDxePchPlatformPolicyProtocolGuid =3D { 0x4b0165a9, 0x61d6, 0x4e23,= { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 }} + gEfiLegacyInterruptProtocolGuid =3D { 0x31ce593d, 0x108a, 0x485d,= { 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe }} + gEfiSmmIchnDispatchProtocolGuid =3D { 0xc50b323e, 0x9075, 0x4f2a,= { 0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc }} + gEfiLegacy8259ProtocolGuid =3D { 0x38321dba, 0x4fe0, 0x4e17,= { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }} + gPlatformEmmcInfoProtocolGuid =3D { 0xf103dd83, 0x3b17, 0x4e1e,= { 0x9b, 0x80, 0x5d, 0xcc, 0x9c, 0x59, 0x0b, 0x2f }} + gPchEmmcTuningProtocolGuid =3D { 0x10fe7e3b, 0xdbe5, 0x4cfa,= { 0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89 }} + gScsEmmcSoftwareTuningProtocolGuid =3D { 0x972215b2, 0x9616, 0x4de4,= { 0xa9, 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54 }} + gPchTcoSmiDispatchProtocolGuid =3D { 0x9E71D609, 0x6D24, 0x47FD,= { 0xB5, 0x72, 0x61, 0x40, 0xF8, 0xD9, 0xC2, 0xA4 }} + gPchPcieSmiDispatchProtocolGuid =3D { 0x3E7D2B56, 0x3F47, 0x42AA,= { 0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB }} + gPchAcpiSmiDispatchProtocolGuid =3D { 0xD52BB262, 0xF022, 0x49EC,= { 0x86, 0xD2, 0x7A, 0x29, 0x3A, 0x7A, 0x05, 0x4B }} + gPchGpioUnlockSmiDispatchProtocolGuid =3D { 0x83339EF7, 0x9392, 0x4716,= { 0x8D, 0x3A, 0xD1, 0xFC, 0x67, 0xCD, 0x55, 0xDB }} + gPchSmiDispatchProtocolGuid =3D { 0xE6A81BBF, 0x873D, 0x47FD,= { 0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93 }} + gEfiSmmIchnDispatch2ProtocolGuid =3D { 0xe0f0cc19, 0x8912, 0x4077,= { 0xbf, 0x8a, 0x6a, 0x5c, 0x27, 0xa, 0x3e, 0x65 }} + gEfiSmmIchnDispatch2ExProtocolGuid =3D { 0x8497455b, 0xb489, 0x4ac7,= { 0xbd, 0x51, 0x78, 0xdf, 0x4e, 0x1f, 0x1a, 0xcd }} + gPchEspiSmiDispatchProtocolGuid =3D { 0xB3C14FF3, 0xBAE8, 0x456C,= { 0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C }} + gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b,= { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} + gPchSataEfiLoadProtocolGuid =3D { 0xaee24780, 0x4511, 0x4f23,= { 0xa0, 0x28, 0xeb, 0x82, 0x4, 0xd4, 0x82, 0x9c }} + gPchsSataEfiLoadProtocolGuid =3D { 0x8580afee, 0x40ad, 0x4f63,= { 0xa5, 0x48, 0x3d, 0x7f, 0x4a, 0x9, 0x86, 0x7d }} + gPchSmmPeriodicTimerControlGuid =3D { 0x6906E93B, 0x603B, 0x4A0F,= { 0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB }} + gIoTrapExDispatchProtocolGuid =3D { 0x5B48E913, 0x707B, 0x4F9D,= { 0xAF, 0x2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D }} + gPchSmmSpiProtocolGuid =3D { 0x56521f06, 0xa62, 0x4822,= { 0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1 }} + gPchThermalLevelsProtocolGuid =3D { 0x813C7793, 0xD430, 0x4114,= { 0x82, 0x6C, 0x8D, 0x19, 0xEF, 0x86, 0x97, 0xF1 }} + gPchPolicyProtocolGuid =3D { 0x543d5c93, 0x6a28, 0x4513,= { 0x85, 0x9a, 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe }} + gPchSmmEadrSxDispatchProtocolGuid =3D { 0x0A97A42A, 0x6929, 0x4DE2,= { 0x91, 0xC1, 0xF2, 0xC0, 0x37, 0xBA, 0xCA, 0xA5 }} + gPchSmmEadrResetDispatchProtocolGuid =3D { 0x5D49C8BA, 0xF3D2, 0x4A3C,= { 0x99, 0x64, 0x64, 0x80, 0x43, 0x12, 0x5A, 0xD8 }} +# +# SouthCluster End +# + gRasClvMirrorFailoverProtocol =3D { 0x66bc00dc, 0x= 8557, 0x4fc1, { 0x9b, 0xec, 0x13, 0x77, 0x60, 0xe2, 0x7e, 0x96 } } + gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0x= c8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 } } + gEfiPciCallbackProtocolGuid =3D { 0x1ca0e202, 0x= fe9e, 0x4776, { 0x9f, 0xaa, 0x57, 0x0c, 0x19, 0x61, 0x7a, 0x06 } } + gSmmPseudoOffestInfoProtocol =3D { 0xB5ABF7DC, 0x= FD44, 0x45C5, { 0xAB, 0x5A, 0x0F, 0xE5, 0x0F, 0xB4, 0x84, 0xF9 } } + gDxePseudoOffestInfoProtocol =3D { 0x07E53E7B, 0x= E480, 0x480D, { 0xB7, 0x4D, 0x21, 0xAE, 0x17, 0x9B, 0x71, 0x78 } } +# +# Me +# + gAlertStandardFormatProtocolGuid =3D { 0x45de9920, 0x= cd54, 0x446a, { 0xa0, 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4 } } + gDxeAmtPolicyGuid =3D { 0x6725e645, 0x= 4a7f, 0x9969, { 0x82, 0xec, 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57 } } + gAmtReadyToBootProtocolGuid =3D { 0xcc9d5c0b, 0x= 9010, 0x45f1, { 0x99, 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77 } } + gHeciProtocolGuid =3D { 0x3c7bc880, 0x= 41f8, 0x4869, { 0xae, 0xfc, 0x87, 0x0a, 0x3e, 0xd2, 0x82, 0x99 } } + gHeciFlowProtocolGuid =3D { 0x1498d127, 0x= 123c, 0x4e52, { 0x84, 0x00, 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e } } + gMebxProtocolGuid =3D { 0x01ab1829, 0x= cecd, 0x4cfa, { 0xa1, 0x8c, 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74 } } + gDxeMePolicyGuid =3D { 0xa0b5dc52, 0x= 4f34, 0x3990, { 0xd4, 0x91, 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42 } } + gDxeSpsPolicyProtocolGuid =3D { 0x1f549fc8, 0x= 14c7, 0x4fd1, { 0xa2, 0xad, 0x42, 0x71, 0xc8, 0x8b, 0x58, 0x12 }} + gMeInfoProtocolGuid =3D { 0x7523c8e4, 0x= 4fbe, 0x9661, { 0x29, 0x96, 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b } } + gPlatformMeHookProtocolGuid =3D { 0xbc52476e, 0x= f67e, 0x4301, { 0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2 } } + gMeNvsAreaProtocolGuid =3D { 0x3bffecfd, 0x= d75f, 0x4975, { 0xb8, 0x88, 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b } } + gMePlatformGetResetTypeGuid =3D { 0xf46dd670, 0x= 36c2, 0x4437, { 0x93, 0xc5, 0x8e, 0x04, 0x65, 0x82, 0xe6, 0xc3 } } + gJhiProtocolGuid =3D { 0xccba3051, 0x= a574, 0x4f9d, { 0x96, 0xf4, 0xec, 0x0d, 0x4a, 0x87, 0xbc, 0x5a } } + gIntegratedTouchHidProtocolGuid =3D { 0x3d0479c1, 0x= 6b19, 0x4191, { 0xb8, 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55 } } + gIntegratedTouchProtocolGuid =3D { 0x2b12e46f, 0x= 3c24, 0x47ff, { 0x8b, 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42 } } + gMeEopDoneProtocolGuid =3D { 0x8d9b3387, 0x= 73db, 0x456f, { 0x88, 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09 } } + gAmtSaveMebxProtocolGuid =3D { 0x86682c04, 0x= ea42, 0x49e5, { 0x96, 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7 } } + + gSmmHeciProtocolGuid =3D { 0x7a305c6c, 0x= 61ae, 0x4bec, { 0xa7, 0xad, 0xec, 0xe3, 0xfb, 0x8f, 0xef, 0xd1 }} + gSmmMeHeci3ProtocolGuid =3D { 0x69735520, 0x= DA83, 0x444A, { 0x93, 0xDC, 0xBD, 0xDD, 0x59, 0xE5, 0x91, 0x82 }} + gActiveManagementProtocolGuid =3D { 0xd25dc167, 0x= eb6a, 0x432d, { 0x65, 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb }} + gMdesStatusCodeProtocolGuid =3D { 0xe5d0875a, 0x= f647, 0x4e16, { 0xbe, 0x4d, 0x95, 0x02, 0x40, 0x29, 0xcc, 0x44 }} + gEfiMeInfoProtocolGuid =3D { 0x11fbfdfb, 0x= 10d2, 0x43e6, { 0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a }} + gEfiAmtWrapperProtocolGuid =3D { 0x919383de, 0x= ebac, 0x4924, { 0x01, 0x94, 0x52, 0x59, 0xe0, 0x0d, 0x65, 0x7a }} + gSpsPolicyProtocolGuid =3D { 0x7316b2ac, 0x= c003, 0x42c8, { 0xb0, 0xf0, 0x88, 0x97, 0x4b, 0x1f, 0x4b, 0xbe }} + gSpsSmmHmrfpoProtocolGuid =3D { 0xeb48a372, 0x= da75, 0x4c5d, { 0xba, 0x00, 0xa7, 0x1e, 0x32, 0xe8, 0xa0, 0x8f }} + gSpsSmmHmrfpoExtProtocolGuid =3D { 0xd34faeb7, 0x= 5d40, 0x4ee1, { 0x8d, 0x04, 0xb6, 0x2a, 0xf9, 0xf0, 0xf7, 0xdf }} + gSpsRasNotifyProtocolGuid =3D { 0xb0aab2cf, 0x= d7ec, 0x4d4c, { 0xa6, 0xce, 0x39, 0x73, 0x8d, 0x0a, 0x29, 0xb4 }} + gIccOverClockingProtocolGuid =3D { 0xe1fc8377, 0x= 25a0, 0x46b9, { 0x82, 0xae, 0x07, 0x6c, 0x73, 0xc0, 0x71, 0xa9 }} + gIccDataProtocolGuid =3D { 0x346b6db3, 0x= 39a3, 0x400e, { 0x81, 0xbd, 0x21, 0x6d, 0xb5, 0x79, 0x74, 0x46 }} + gSpsSmmBiosUpdateProtocolGuid =3D { 0x0141540B, 0x= 6BC3, 0x4B38, { 0xA7, 0xAE, 0xCC, 0x71, 0x84, 0x48, 0xFE, 0x42 }} + gSpsSmmMeStorageProtocolGuid =3D { 0x1b45e3a2, 0x= e498, 0x40f3, { 0x93, 0xb9, 0xb9, 0x5b, 0x7f, 0x2b, 0xf4, 0x2e }} +# +# IE +# + gIeHeciProtocolGuid =3D { 0x03911e52, 0xb39b, 0x4e91, { 0xa5,= 0x53, 0x95, 0x80, 0x3d, 0xc8, 0xac, 0x6a }} +# +# VTD Protocols Begin +# + gEdkiiPlatformVTdPolicyProtocolGuid =3D { 0x3d17e448, 0x= 466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} +# +# VTD Protocols End +# + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x100000= 01 + gPlatformTokenSpaceGuid.PcdMultiPchEnabled |FALSE|BOOLEAN|0x100= 00003 + gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF00= 00007 +#gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF00= 0000F +#gSiPkgTokenSpaceGuid.PcdAmtEnable |FALSE|BOOLEAN|0xF00= 00010 +#gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF00= 00011 +#gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x= 00010055 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. +## +#gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 + + gPlatformTokenSpaceGuid.PcdUseRxTxMultiCastRegisters|FALSE|BOOLEAN|0x100= 00002 + + # PMC Strap Set VDM Feature switch (soft straps update for warm-reset el= imination feature) + gSiPkgTokenSpaceGuid.PcdPmcStrapSetVdmSupported|FALSE|BOOLEAN|0x0001000B + + # Change to TRUE to enable check for sample parts + # If check is enabled, BIOS will not boot on a sample part + gSiPkgTokenSpaceGuid.PcdEnableSamplePartCheck|FALSE|BOOLEAN|0x0001000C + + gSiPkgTokenSpaceGuid.PcdHardwareLocalSemaphores|FALSE|BOOLEAN|0xF0000012 + +### [PcdsFixedAtBuild, PcdsPatchableInModule] +[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic, PcdsDynamicEx] +# +# SouthCluster +# + ## From MdeModulePkg.dec + ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes = to follow ACPI specification. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 + ## Default OEM Table ID for ACPI table creation, it is "EDK2 ". + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|= 0x30001035 + ## Default OEM Revision for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001= 036 + ## Default Creator ID for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037 + ## Default Creator Revision for ACPI table creation. + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x3= 0001038 + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0780|UINT16|0x00010031 + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034 + + ## + ## This PCD specifies the base address of the HPET timer. + ## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xF= ED03000 + ## + gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x000100= 57 + ## + ## This PCD specifies the base address of the IO APIC. + ## The acceptable values are 0xFECxx000. + ## + gSiPkgTokenSpaceGuid.PcdPchIoApicBaseAddress |0xFEC00000|UINT32|0x00010= 058 + + # HSIO +# +# SouthCluster End +# + +# +# VTD PCDs Begin +# + ## Error code for VTd error.

+ # EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
+ # @Prompt Error code for VTd error. + gSiPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 +# +# VTD PCDs End +# + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +# +# SouthCluster +# + gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE|BOOLEAN|0x30000018 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0|UINT8|0x30000019 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0|UINT8|0x30000020 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0|UINT8|0x30000021 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0x88880000|UINT32|0x30000007 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0x88338822|UINT32|0x30000009 + + + ## + ## PCI Express MMIO temporary region length in SEC phase. + ## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, = 0x4000000/64MB + ## + gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT3= 2|0x00200005 + # + # PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined= in SMBIOS, + # values 0-0x7F will be treated as disable FVI reporting. + # FVI structure uses it as SMBIOS OEM type to provide version informatio= n. + # + gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 + + + ## CSM Setup value + gClientCommonModuleTokenSpaceGuid.PcdCsmEnable|TRUE|BOOLEAN|0x30000036 +# +# SouthCluster End +# + + # PcdUseNvdimmFwInterface determines whether memory map code uses Intel = NVDIMM firmware mailbox interface + # to communicate with Intel NVDIMM + gSiPkgTokenSpaceGuid.PcdUseNvdimmFwInterface|TRUE|BOOLEAN|0x30000040 + +# +# VTD PCDs Begin +# + ## The mask is used to control VTd behavior.

+ # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) + # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) + # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. + # BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Pr= otection + # @Prompt The policy for VTd driver behavior. + gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002 + + ## Declares VTd PEI DMA buffer size.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI (InstallPeiMemory), the PMR alignment requirement + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size. + gSiPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|0x00000003 + + ## Declares VTd PEI DMA buffer size for S3.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirem= ent + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size for S3. + gSiPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT32|0x000000= 04 +# +# VTD PCDs End +# + +[PcdsFixedAtBuild] + gPlatformTokenSpaceGuid.PcdUboDev|0x08|UINT8|0x3000000D + gPlatformTokenSpaceGuid.PcdUboFunc|0x02|UINT8|0x3000000E + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC|UINT8|0x3000000F + gPlatformTokenSpaceGuid.PcdSecInFsp|0x0|UINT32|0x30000010 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFD00000|UINT32|= 0x2000000D + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000300000|UINT32|= 0x2000000E + gCpuUncoreTokenSpaceGuid.PcdFlashIcxFlashRegionBase|0x0000000000|UINT32|= 0x20000030 + gCpuUncoreTokenSpaceGuid.PcdFlashIcxFlashRegionSize|0x0000000000|UINT32|= 0x20000031 + gCpuUncoreTokenSpaceGuid.PcdFlashCpxFlashRegionBase|0x0000000000|UINT32|= 0x20000032 + gCpuUncoreTokenSpaceGuid.PcdFlashCpxFlashRegionSize|0x0000000000|UINT32|= 0x20000033 + gCpuUncoreTokenSpaceGuid.PcdFlashOemSecPeiRegionBase|0x0000000000|UINT32= |0x20000040 + gCpuUncoreTokenSpaceGuid.PcdFlashOemSecPeiRegionSize|0x0000000000|UINT32= |0x20000041 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000|UINT32|0x20= 00000F + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000|UINT32|0x20= 000010 + gCpuUncoreTokenSpaceGuid.PcdSecDataCacheRegionPattern|0x5AA55AA5|UINT32|= 0x20000011 + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|0xFFFB0000|UINT3= 2|0x30000004 + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize|0x00010000|UINT3= 2|0x30000005 + ## + ## PCD PcdFlashNvStorageMicrocode2Base and PcdFlashNvStorageMicrocode2Si= ze are + ## added for supporting the second microcode flash region as recovery ba= ckup. + ## Default value 0x0 which means there is no 2nd microcode region. + ## + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocode2Base|0x0|UINT32|0x30= 00000A + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocode2Size|0x0|UINT32|0x30= 00000B + gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|TRUE|BOOLEAN|0x40000001 + gCpuUncoreTokenSpaceGuid.PcdMmioRule19BaseAddress|0xFC000000|UINT32|0x40= 00000F + gSiPkgTokenSpaceGuid.PcdMaxDdrioIpChannels|0x03|UINT8|0x30000006 + gSiPkgTokenSpaceGuid.PcdMaxMcIpChannels|0x03|UINT8|0x30000008 +# +# SouthCluster +# + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x500|UINT16|0x30000003 + gSiPkgTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000005 + gSiPkgTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x30000001 + gSiPkgTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000002 + gEfiCommonPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT3= 2|0x30001033 + gSiPkgTokenSpaceGuid.PcdFspBinaryEnable |FALSE|BOOLEAN|0x30= 000010 + gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012 + gSiPkgTokenSpaceGuid.PcdSermEnable|TRUE|BOOLEAN|0x30000014 + gSiPkgTokenSpaceGuid.PcdSdpsEnable|FALSE|BOOLEAN|0x30000016 + # Added to make ADP specific changes in ServerSiliconPkg + gSiPkgTokenSpaceGuid.PcdAdpPchSupport|FALSE|BOOLEAN|0xF0000050 + + ## + ## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPc= iExpressBaseAddress. + ## This PCD is added for supporting different PCD type in different phas= es. + ## + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0x80000000|UINT64|0x002= 00002 + + ## From MdeModulePkg.dec + ## Progress Code for S3 Suspend end. + # PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OE= M_SPECIFIC | 0x00000001)) =3D 0x03078001 + gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x300= 01033 + + ## TraceHub Configuration + ## PcdTraceHubEnMode: 0 for Disabled, 1 for Internal Debugger, 2 for Hos= t Debugger + + ## TraceHub temporary disabled, until TraceHubInitialize is not working = correctly. Sighting 4929727. + gSiPkgTokenSpaceGuid.PcdTraceHubEnMode|0x00|UINT8|0x30003001 + + ## PcdTraceHubEnFWTrace: 0 for Disabled, 1 for Enabled + gSiPkgTokenSpaceGuid.PcdTraceHubEnFwTrace|0x01|UINT8|0x30003002 + ## PcdTraceHubDest: 0 for Mem, 1 for PTI, 2 for USB3, 3 for BSSB + gSiPkgTokenSpaceGuid.PcdTraceHubDest|0x02|UINT8|0x30003003 + ## PcdTraceHubTempCsrMtbBar: Temporary CSR MTB BAR + gSiPkgTokenSpaceGuid.PcdTraceHubTempCsrMtbBar|0xFE100000|UINT32|0x300030= 04 + + ## + ## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection + ## value of the struct + ## 0x00 EfiGcdAllocateAnySearchBottomUp + ## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp + ## 0x03 EfiGcdAllocateAnySearchTopDown + ## 0x04 EfiGcdAllocateMaxAddressSearchTopDown + ## + ## below value should not using in this situation + ## 0x05 EfiGcdMaxAllocateType : design for max value of struct + ## 0x02 EfiGcdAllocateAddress : design for specification address alloca= te + ## + gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + + ## + ## Temp MEM IO resource + ## + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 |0= x00010053 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 |0= x00010054 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0= x00010055 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize |0x00200000|UINT32|0= x00010056 + + ## + ## 8259 PIC + ## + gSiPkgTokenSpaceGuid.PcdDisable8259Interrupts|TRUE|BOOLEAN|0x30000017 +# +# SouthCluster End +# + +# +# Reference Code Policy default settings +# + gReferenceCodePolicyTokenSpaceGuid.PcdNumaEn |0x01|UINT8|0x0= 0000001 + gReferenceCodePolicyTokenSpaceGuid.PcdUmaBasedClustering |0x00|UINT8|0x0= 001005 + ## + ## PcdUseEmulationInjection indicates if the injection values from emula= tion team + ## should take precedence to be applied in the CSR programming. + ## FALSE: The injection values should not be applied. + ## TRUE : The injection values take precedence to be applied. + ## + gReferenceCodePolicyTokenSpaceGuid.PcdUseEmulationInjection |TRUE|BOOLE= AN|0x0001007 + + # Temperature refresh value select Auto=3D>0/Manula=3D>1 + gSiPkgTokenSpaceGuid.PcdTempRefreshOption |0|UINT8|0x7000000A + + # Temperature refresh value default, Values are in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x19|UINT8|0x7000= 0001 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue |0x53|UINT8|0x7000= 0002 + gSiPkgTokenSpaceGuid.PcdFourxRefreshValue |0x5F|UINT8|0x7000= 0003 + + # Temperature refresh Min Value, Values in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshMinValue |0|UINT8|0x7000= 0004 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshMinValue |0|UINT8|0x7000= 0005 + gSiPkgTokenSpaceGuid.PcdFourxRefreshMinValue |0|UINT8|0x7000= 0006 + + #Temperature refresh Max Value, Calues in Celcius + gSiPkgTokenSpaceGuid.PcdHalfxRefreshMaxValue |0xFF|UINT8|0x7= 0000007 + gSiPkgTokenSpaceGuid.PcdTwoxRefreshMaxValue |0xFF|UINT8|0x7= 0000008 + gSiPkgTokenSpaceGuid.PcdFourxRefreshMaxValue |0xFF|UINT8|0x7= 0000009 + + gSiPkgTokenSpaceGuid.PcdDdrInternalClocksOn |0|UINT8|0x7000= 000B + gSiPkgTokenSpaceGuid.PcdDdrForceBiasOn |0|UINT8|0x7000= 000C + + #Temperature Critical temperature value in celcius + gSiPkgTokenSpaceGuid.PcdMaxTCriticalValue |100|UINT8|0x70= 00000F + + #MemTrip default value + gSiPkgTokenSpaceGuid.PcdTempMemTripDefault |101|UINT8|0x70= 000010 + + #Temperature High Value when MemTrip Enabled + gEfiCpRcPkgTokenSpaceGuid.PcdTempHiMemTripEnabled |105|UINT8|0x70= 000011 + #Temperature High Value when MemTrip Disabled + gEfiCpRcPkgTokenSpaceGuid.PcdTempHiMemTripDisabled |100|UINT8|0x70= 000012 +# +# IIO CPU Trace Hub +# + # + # This Pcd for MTB BAR of CPU Trace Hub is set with the same value as fo= r PCH Trace Hub 0xfe100000 + # + gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfe100000|UINT32|0x700000= 0D + + # + # Posted CSR accesses are dynamically enabled in the code where the post= ed method is appropriate. + # + # PcdPostedCsrAccessSupported, if TRUE, exposes the SW mechanisms that s= upport the posted CSR access feature. + # PcdPostedCsrAccessAllowedDefault defines the default setting of the op= tion/knob that allows + # use of the posted CSR access feature. This PCD is only used if the= platform supports + # the posted CSR access feature (that is, if PcdPostedCsrAccessSuppo= rted is TRUE). + # + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |TRUE|BOOLEAN|0= xF0000027 + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessAllowedDefault |TRUE|BOOLEAN|0= xF0000029 + + # + # CPGC global sync control will synchronize CPGC test start across all s= elected memory controllers + # + # PcdCpgcGlobalSyncCtrlSupported, if TRUE, exposes the SW mechanisms tha= t support the feature + # PcdCpgcGlobalSyncCtrlEnableDefault, if TRUE, sets the value of the BIO= S knob to Enable + # + gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported |FALSE|BOOLEAN= |0xF0000030 + gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault |FALSE|BOOLEAN= |0xF0000031 + + gSiPkgTokenSpaceGuid.PcdPeiCoreFv |0x00000000|UI= NT32|0xF0000032 + + gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033 + + # + # Sense Amp Calibration can be trained using HW FSM or SW based algorith= ms + # PcdSenseAmpCalibHwFsmSupported determines if the HW FSM is supported b= y the platform + # + gSiPkgTokenSpaceGuid.PcdSenseAmpCalibHwFsmSupported |FALSE|BOOLEAN= |0xF0000034 + + gSiPkgTokenSpaceGuid.ReservedO |0|UINT8|0xF0000035 + + # PcdCpgcRegCacheAccessSupported, if TRUE, exposes the SW mechanisms tha= t support CPGC register cache access feature. + # PcdCpgcRegCacheAccessAllowedDefault defines the default setting of the= option/knob that allows + # use of CPGC register cache access feature. This PCD is only used i= f the platform supports + # CPGC register cache access feature (that is, if PcdCpgcRegCacheAcc= essSupported is TRUE). + # + gSiPkgTokenSpaceGuid.PcdCpgcRegCacheAccessSupported |TRUE|BOOLEA= N|0xF0000040 + gSiPkgTokenSpaceGuid.PcdCpgcRegCacheAccessAllowedDefault |TRUE|BOOLEA= N|0xF0000041 + + gSiPkgTokenSpaceGuid.ReservedA |FALSE|BOOLEAN|0xF0000036 + + gSiPkgTokenSpaceGuid.ReservedP |FALSE|BOOLEAN|0xF0000037 + + # + #Set the PcdPeiMemoryBaseAddressDefault control whether to limit the mem= ory used by UEFI to below 1GB + #PcdPeiMemoryBaseAddressDefault, if FALSE, the memory used by UEFI will = be limited to below 1GB + # + gSiPkgTokenSpaceGuid.PcdPeiMemoryBaseAddressDefault |TRUE|BOOLEAN|= 0x30000022 + +# +# VTD PCDs Begin +# + + gSiPkgTokenSpaceGuid.PcdVtdSupport|FALSE|BOOLEAN|0x00000006 + +# +# VTD PCDs End +# + +[PcdsDynamicEx] + gReferenceCodePolicyTokenSpaceGuid.PcdEvMode |0x00|UINT8|0x00010= 001 + # ReservedC: The Mailbox Command which it gona to assert. + # 0x00: it will not assert + # 0xFF: it will assert on any error + # Other values: it will assert on the speci= fied command failure + # + gReferenceCodePolicyTokenSpaceGuid.ReservedC|0x0|UINT8|0x00010003 + # + # PcdWarmResetEliminationEn - if TRUE, it indicates SoC supports warm-re= set elimination feature. + # This feature requires Silicon (hardware) support for warm-reset elimin= ation flow to be + # fully functioning. + # + gSiPkgTokenSpaceGuid.PcdWarmResetEliminationEn|FALSE|BOOLEAN|0x0001000A + # + # PcdEmuBiosSkipS3MAccess - TRUE: S3M Flow is skipped; FALSE: S3M Flow i= s not skipped. + # + gSiPkgTokenSpaceGuid.PcdEmuBiosSkipS3MAccess|FALSE|BOOLEAN|0x0001000D + + gSiPkgTokenSpaceGuid.PcdHvmModeEnabled|FALSE|BOOLEAN|0x5000000D + # + # PcdNumaAcpiDataStaticPointer: Saves the static pointer of the NumaAcpi= Data buffer. + # + gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E + +[PcdsDynamic, PcdsDynamicEx] + gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 + gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A + gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D + gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B + +## +## ME +## + gEfiMePkgTokenSpaceGuid.PcdMePlatformResetType|0x00|UINT32|0x50000008 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. +## + gEfiMePkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x50000009 + +## +## RAS +## + gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001 + gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 + +[PcdsFeatureFlag] + ## This PCD used by FPGA drivers to decide to install FPGA features. + gSocketPkgFpgaGuid.PcdSktFpgaActive|FALSE|BOOLEAN|0x1000000E + + gSiPkgTokenSpaceGuid.PcdSimicsEnable |FALSE|BOOLEAN|0xF0= 000022 + gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE|BOOLEAN|0xF0= 000005 + gSiPkgTokenSpaceGuid.PcdCnlPchEnable |TRUE |BOOLEAN|0xF0= 000026 + gEfiMePkgTokenSpaceGuid.PcdHeciEndOfDxeNotify |FALSE|BOOLEAN|0x50= 00000A + gEfiMePkgTokenSpaceGuid.PcdNodeManagerEnable |TRUE |BOOLEAN|0x50= 00000C diff --git a/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec b/Silico= n/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec new file mode 100644 index 0000000000..ae951e0b14 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec @@ -0,0 +1,65 @@ +## @file +# Component description file for the Silicon Reference Code. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D WhitleySiliconPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D 6f1ec317-5d04-456a-8908-6290453d57ac + +[Includes] + Include + Cpu/Include + Library/BaseMemoryCoreLib/Core/Include + Library/BaseMemoryCoreLib/Platform + Pch/SouthClusterLbg + Pch/SouthClusterLbg/Include + Me/MeSps.4/Include + Security/Include + Security/Include/Guid + +[Guids] + gStatusCodeDataTypeExDebugGuid =3D { 0x7859daa2, 0x926e, = 0x4b01, { 0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, 0xd2 }} + gEfiCpRcPkgTokenSpaceGuid =3D { 0xfcdd2efc, 0x6ca8, = 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }} + gReferenceCodePolicyTokenSpaceGuid =3D { 0x3268c52f, 0xd3b3, = 0x405d, { 0xb6, 0x91, 0x14, 0x4f, 0xca, 0x42, 0xe4, 0x37 }} # {3268c52f-d3= b3-405d-b691-144fca42e437} + gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0= x4b6b, {0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}} + gSiliconPolicyInitLibInterfaceGuid =3D { 0x058715d2, 0x371f, = 0x486e, { 0x86, 0xf9, 0xbc, 0x7f, 0x89, 0xbc, 0x90, 0x26 }} # {058715d2-37= 1f-486e-86f9-bc7f89bc9026} + gSaveHostToMemoryGuid =3D { 0x9da19038, 0x2085, = 0x486a, { 0xad, 0x53, 0xc4, 0x97, 0xda, 0xaa, 0x20, 0x48 } } + +[Ppis] + gDynamicSiLibraryPpiGuid =3D { 0x4e18e22b, 0x5034, = 0x4512, { 0xb7, 0xe5, 0x0b, 0xf1, 0x9d, 0xe3, 0x59, 0x8c }} + +[Protocols] + gDynamicSiLibraryProtocolGuid =3D { 0xb235fbed, 0x3b25, = 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b, 0x7e }} + gDynamicSiLibrarySmmProtocolGuid =3D { 0x82faf3a3, 0x6226, = 0x48be, {0xb0, 0x4e, 0xc2, 0xfb, 0x0f, 0x72, 0xcf, 0x2f }} + +[PcdsDynamicEx] + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011 + + gSiPkgTokenSpaceGuid.PcdHvmModeEnabled|FALSE|BOOLEAN|0x5000000D + + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00= 000048 + + gReferenceCodePolicyTokenSpaceGuid.ReservedD|0x0F|UINT8|0x00010002 + + # + # ReservedC: The Mailbox Command which it gona to assert. + # 0x00: it will not assert + # 0xFF: it will assert on any error + # Other values: it will assert on the speci= fied command failure + # + gReferenceCodePolicyTokenSpaceGuid.ReservedC|0x0|UINT8|0x00010003 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x600000= 14 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x60000= 01C + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x60000021 --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 02/17] WhitleySiliconPkg: Add Includes and Libraries Date: Mon, 12 Jul 2021 17:41:16 -0700 Message-Id: <20210713004131.1782-3-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: sklQEObv5oRDB27x5UyftvdLx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136915; bh=ddpdaXuQwCbDWsbp/YBTWm3qDJFhKejx34GqvtT2cA0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=TInOexRpurg0hezg80tFHi2aFI34KIt4XFHry6j9wXzg5H2YShmI7qPquRoMfb+a9IC ki9O1fmV1d5w7as6xf79rVzUK6OO7XFEInqUrsLSNDmdb1pAWozHf9AuRf1ZLrL72PEqU IQ3J4p5kYqGyf8wYtKFmG9BDfazQX7L4esg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136917146100001 Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Include/BackCompatible.h | 19 + .../Include/ConfigBlock/TraceHubConfig.h | 65 + .../Include/ConfigBlock/Usb2PhyConfig.h | 63 + .../Include/ConfigBlock/UsbConfig.h | 85 + .../WhitleySiliconPkg/Include/Cpu/CpuIds.h | 18 + .../Include/CpuAndRevisionDefines.h | 283 +++ .../Include/EmulationConfiguration.h | 22 + .../Intel/WhitleySiliconPkg/Include/Fpga.h | 17 + .../WhitleySiliconPkg/Include/GpioConfig.h | 288 +++ .../Include/Guid/EmulationDfxVariable.h | 25 + .../Include/Guid/FpgaSocketVariable.h | 39 + .../Include/Guid/MemBootHealthGuid.h | 71 + .../Include/Guid/MemoryMapData.h | 197 ++ .../Include/Guid/PartialMirrorGuid.h | 61 + .../Include/Guid/PlatformInfo.h | 150 ++ .../Guid/SiliconPolicyInitLibInterface.h | 78 + .../Include/Guid/SocketCommonRcVariable.h | 57 + .../Include/Guid/SocketIioVariable.h | 444 ++++ .../Include/Guid/SocketMemoryVariable.h | 477 ++++ .../Include/Guid/SocketMpLinkVariable.h | 320 +++ .../Include/Guid/SocketPciResourceData.h | 60 + .../Guid/SocketPowermanagementVariable.h | 300 +++ .../Guid/SocketProcessorCoreVariable.h | 143 ++ .../Include/Guid/SocketVariable.h | 36 + .../Include/Guid/StatusCodeDataTypeExDebug.h | 50 + .../WhitleySiliconPkg/Include/IioConfig.h | 398 ++++ .../Include/IioPlatformData.h | 204 ++ .../Intel/WhitleySiliconPkg/Include/IioRegs.h | 179 ++ .../Include/IioSetupDefinitions.h | 60 + .../Include/IioUniversalData.h | 166 ++ .../WhitleySiliconPkg/Include/ImonVrSvid.h | 26 + .../Include/KtiSetupDefinitions.h | 22 + .../Include/Library/CompressedVariableLib.h | 35 + .../Library/EmulationConfigurationLib.h | 34 + .../Include/Library/MemTypeLib.h | 32 + .../Include/Library/MemVrSvidMapLib.h | 66 + .../Include/Library/PchInfoLib.h | 22 + .../Include/Library/PlatformHooksLib.h | 17 + .../Include/Library/SemaphoreLib.h | 326 +++ .../Intel/WhitleySiliconPkg/Include/MaxCore.h | 20 + .../WhitleySiliconPkg/Include/MaxSocket.h | 20 + .../WhitleySiliconPkg/Include/MaxThread.h | 20 + .../WhitleySiliconPkg/Include/MemCommon.h | 41 + .../Include/Memory/Ddr4SpdRegisters.h | 38 + .../Include/Memory/ProcSmbChipCommon.h | 28 + .../WhitleySiliconPkg/Include/Platform.h | 266 +++ .../Include/PlatformInfoTypes.h | 106 + .../Include/Ppi/DynamicSiLibraryPpi.h | 474 ++++ .../Include/Ppi/MemoryPolicyPpi.h | 2112 +++++++++++++++++ .../Include/Ppi/RasImcS3Data.h | 53 + .../Include/Ppi/UpiPolicyPpi.h | 39 + .../Protocol/DynamicSiLibraryProtocol.h | 252 ++ .../Protocol/DynamicSiLibrarySmmProtocol.h | 60 + .../Include/Protocol/GlobalNvsArea.h | 212 ++ .../Include/Protocol/IioUds.h | 47 + .../Include/Protocol/PciCallback.h | 85 + .../WhitleySiliconPkg/Include/RcVersion.h | 23 + .../Include/ScratchpadList.h | 49 + .../Include/SiliconUpdUpdate.h | 53 + .../WhitleySiliconPkg/Include/SystemInfoVar.h | 93 + .../Include/UncoreCommonIncludes.h | 111 + .../WhitleySiliconPkg/Include/Upi/KtiDisc.h | 36 + .../WhitleySiliconPkg/Include/Upi/KtiHost.h | 304 +++ .../WhitleySiliconPkg/Include/Upi/KtiSi.h | 32 + .../Include/UsraAccessType.h | 291 +++ .../Core/Include/DataTypes.h | 36 + .../BaseMemoryCoreLib/Core/Include/MemHost.h | 1051 ++++++++ .../Core/Include/MemHostChipCommon.h | 190 ++ .../BaseMemoryCoreLib/Core/Include/MemRegs.h | 25 + .../Core/Include/MrcCommonTypes.h | 28 + .../Core/Include/NGNDimmPlatformCfgData.h | 22 + .../BaseMemoryCoreLib/Core/Include/SysHost.h | 193 ++ .../Core/Include/SysHostChipCommon.h | 101 + .../BaseMemoryCoreLib/Platform/MemDefaults.h | 28 + .../BaseMemoryCoreLib/Platform/PlatformHost.h | 35 + .../FspWrapperPlatformLib.c | 243 ++ .../FspWrapperPlatformLib.inf | 71 + .../Library/SetupLib/PeiSetupLib.c | 259 ++ .../Library/SetupLib/PeiSetupLib.inf | 55 + .../Library/SetupLib/SetupLib.c | 253 ++ .../Library/SetupLib/SetupLib.inf | 59 + .../Library/SetupLib/SetupLibNull.c | 159 ++ .../Library/SetupLib/SetupLibNull.inf | 46 + .../SiliconPolicyInitLibShim.c | 104 + .../SiliconPolicyInitLibShim.inf | 38 + .../SiliconWorkaroundLibNull.c | 38 + .../SiliconWorkaroundLibNull.inf | 50 + 87 files changed, 12904 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Tra= ceHubConfig.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb= 2PhyConfig.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb= Config.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionD= efines.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfig= uration.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationD= fxVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocket= Variable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHea= lthGuid.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapD= ata.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMir= rorGuid.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformIn= fo.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPol= icyInitLibInterface.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketComm= onRcVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioV= ariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemo= ryVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLi= nkVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciR= esourceData.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowe= rmanagementVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProc= essorCoreVariable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVari= able.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCode= DataTypeExDebug.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData= .h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinit= ions.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalDat= a.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinit= ions.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/Compres= sedVariableLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/Emulati= onConfigurationLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemType= Lib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSv= idMapLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfo= Lib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/Platfor= mHooksLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/Semapho= reLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdR= egisters.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbC= hipCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Platform.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTyp= es.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLi= braryPpi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolic= yPpi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Dat= a.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPp= i.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/Dynami= cSiLibraryProtocol.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/Dynami= cSiLibrarySmmProtocol.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/Global= NvsArea.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds= .h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCal= lback.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdat= e.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonInc= ludes.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/DataTypes.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/MemHost.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/MemHostChipCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/MemRegs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/MrcCommonTypes.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/NGNDimmPlatformCfgData.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/SysHost.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Core/Include/SysHostChipCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Platform/MemDefaults.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreL= ib/Platform/PlatformHost.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatf= ormLib/FspWrapperPlatformLib.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatf= ormLib/FspWrapperPlatformLib.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSet= upLib.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSet= upLib.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupL= ib.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupL= ib.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupL= ibNull.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupL= ibNull.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyIn= itLibShim/SiliconPolicyInitLibShim.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyIn= itLibShim/SiliconPolicyInitLibShim.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkarou= ndLibNull/SiliconWorkaroundLibNull.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkarou= ndLibNull/SiliconWorkaroundLibNull.inf diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h b/Sil= icon/Intel/WhitleySiliconPkg/Include/BackCompatible.h new file mode 100644 index 0000000000..0e9fbde11f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h @@ -0,0 +1,19 @@ +/** @file + Back Compatiable temp header file + + @copyright + Copyright 2007 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __BACK_COMPATIABLE_H__ +#define __BACK_COMPATIABLE_H__ + +#define R_ACPI_LV2 0x14 + +#define R_IOPORT_CMOS_UPPER_INDEX 0x72 +#define R_IOPORT_CMOS_UPPER_DATA 0x73 + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubCo= nfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig= .h new file mode 100644 index 0000000000..11b9367e9a --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h @@ -0,0 +1,65 @@ +/** @file + PCH Trace Hub policy + +@copyright + Copyright 2015 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _TRACEHUB_CONFIG_H_ +#define _TRACEHUB_CONFIG_H_ + +#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1 +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPchTraceHubPreMemConfigGuid; + +/// +/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation +/// +typedef enum { + TraceHubModeDisabled =3D 0, + TraceHubModeTargetDebugger =3D 1, + TraceHubModeHostDebugger =3D 2, + TraceHubModeMax +} TRACE_HUB_ENABLE_MODE; + +/// +/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size +/// +typedef enum { + TraceBufferNone =3D 0, + TraceBuffer1M =3D SIZE_1MB, + TraceBuffer8M =3D SIZE_8MB, + TraceBuffer64M =3D SIZE_64MB, + TraceBuffer128M =3D SIZE_128MB, + TraceBuffer256M =3D SIZE_256MB, + TraceBuffer512M =3D SIZE_512MB +} TRACE_BUFFER_SIZE; + +#pragma pack (push,1) + +/// +/// TRACE_HUB_CONFIG block describes TraceHub settings. +/// +typedef struct { + /** + Trace hub mode. Default is disabled. + Target Debugger mode refers to debug tool running on target device itsel= f and it works as a conventional PCI device; + Host Debugger mode refers to SUT debugged via probe on host, configured = as ACPI device with PCI configuration sapce hidden. + 0 =3D Disable; 1 =3D Target Debugger mode; 2 =3D Host Debugger mo= de + Refer to TRACE_HUB_ENABLE_MODE + **/ + UINT32 EnableMode; + /** + Trace hub memory buffer region size policy. + The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB= , 3:64MB, 4:128MB, 5:256MB, 6:512MB. + Refer to TRACE_BUFFER_SIZE. + **/ + UINT32 MemReg0Size; + UINT32 MemReg1Size; +} TRACE_HUB_CONFIG; + +#pragma pack (pop) + +#endif // _TRACEHUB_CONFIG_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyCon= fig.h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h new file mode 100644 index 0000000000..1db4d54a39 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h @@ -0,0 +1,63 @@ +/** @file + USB2 PHY configuration policy + +@copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _USB2_PHY_CONFIG_H_ +#define _USB2_PHY_CONFIG_H_ + +#define USB2_PHY_CONFIG_REVISION 1 +extern EFI_GUID gUsb2PhyConfigGuid; + +#pragma pack (push,1) + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port electrical parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} USB2_PHY_PARAMETERS; + +#pragma pack (pop) + +#endif // _USB2_PHY_CONFIG_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.= h b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..8bb60137df --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,85 @@ +/** @file + Common USB policy shared between PCH and CPU + Contains general features settings for xHCI and xDCI + +@copyright + Copyright 2017 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _USB_CONFIG_H_ +#define _USB_CONFIG_H_ + +#define USB_CONFIG_REVISION 1 +extern EFI_GUID gUsbConfigGuid; + +#define MAX_USB2_PORTS 16 +#define MAX_USB3_PORTS 10 + +#pragma pack (push,1) + +#define PCH_USB_OC_PINS_MAX 8 ///< Maximal possible number of USB Over C= urrent pins + +/// +/// Overcurrent pins, the values match the setting of EDS, please refer to= EDS for more details +/// +typedef enum { + UsbOverCurrentPin0 =3D 0, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin6, + UsbOverCurrentPin7, + UsbOverCurrentPinMax, + UsbOverCurrentPinSkip =3D 0xFF +} USB_OVERCURRENT_PIN; + +/** + This structure configures per USB2.0 port settings like enabling and ove= rcurrent protection +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT32 OverCurrentPin : 8; + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 23; ///< Reserved bits +} USB2_PORT_CONFIG; + +/** + This structure configures per USB3.x port settings like enabling and ove= rcurrent protection +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT32 OverCurrentPin : 8; + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 23; ///< Reserved bits +} USB3_PORT_CONFIG; + + +/** + The XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be ena= bled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} XDCI_CONFIG; + +#pragma pack (pop) + +#endif // _USB_CONFIG_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h b/Silicon= /Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h new file mode 100644 index 0000000000..0cb9cb6df5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h @@ -0,0 +1,18 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPUID_REGS_H_ +#define _CPUID_REGS_H_ + +#define CPU_FAMILY_SKX 0x5065 // Skylake/CascadeLake CPU +#define CPU_FAMILY_ICX 0x606A // IceLake CPU +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITEBACK 6 + +#define APICID_MASK_BIT14_8 0x7F //current Si support programmable APIC= ID up to 15bits +#endif //_CPUID_REGS_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.= h b/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h new file mode 100644 index 0000000000..f94a5b3d68 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h @@ -0,0 +1,283 @@ +/** @file + Defines for CPU and Revision library. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_AND_REVISION_DEFINES_H_// #ifndef _CPU_AND_REVISION_LIB_H_ +#define _CPU_AND_REVISION_DEFINES_H_ + +// CPU types +#define CPU_SKX 0 // Skylake: Mainstream Xeon =E2=80= =93 14nm +#define CPU_CLX 1 // CascadeLake: Mainstream Xeon =E2=80= =93 14nm +#define CPU_CPX 2 // CooperLake: Mainstream Xeon =E2=80= =93 14nm +#define CPU_ICXSP 4 // Icelake-SP: Mainstream Xeon =E2=80= =93 10nm Wave 1 +#define CPU_MAX 0xFF // MAX CPU limit + + +// CPU Physical chop types +#define CPU_CHOP_TYPE_LCC 0 +#define CPU_CHOP_TYPE_MCC 1 +#define CPU_CHOP_TYPE_HCC 2 +#define CPU_CHOP_TYPE_XCC 3 + +#define MINOR_REV_MASK 0x000F +#define MINOR_REV_BIT_WIDTH 4 +#define MAJOR_REV_MASK 0xFFF0 + +#define MAJOR_REV_A (0x01 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_B (0x02 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_C (0x03 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_D (0x04 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_E (0x05 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_F (0x06 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_G (0x07 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_H (0x08 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_I (0x09 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_J (0x0A << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_K (0x0B << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_L (0x0C << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_M (0x0D << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_N (0x0E << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_O (0x0F << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_P (0x10 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_Q (0x11 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_R (0x12 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_S (0x13 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_T (0x14 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_U (0x15 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_V (0x16 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_W (0x17 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_X (0x18 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_Y (0x19 << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_Z (0x1A << (MINOR_REV_BIT_WIDTH)) +#define MAJOR_REV_ALL (0x1F << (MINOR_REV_BIT_WIDTH)) + +#define MINOR_REV_0 0 +#define MINOR_REV_1 1 +#define MINOR_REV_2 2 +#define MINOR_REV_3 3 +#define MINOR_REV_4 4 +#define MINOR_REV_5 5 +#define MINOR_REV_6 6 +#define MINOR_REV_7 7 +#define MINOR_REV_8 8 +#define MINOR_REV_ALL 0xF + +// +// Revision defines - Generic for all Cpu Types +// If new revisions are needed, follow same pattern +// +#define REV_A0 (MAJOR_REV_A | MINOR_REV_0) +#define REV_A1 (MAJOR_REV_A | MINOR_REV_1) +#define REV_A2 (MAJOR_REV_A | MINOR_REV_2) +#define REV_A3 (MAJOR_REV_A | MINOR_REV_3) +#define REV_A4 (MAJOR_REV_A | MINOR_REV_4) +#define REV_A5 (MAJOR_REV_A | MINOR_REV_5) +#define REV_AX (MAJOR_REV_A | MINOR_REV_ALL) + +#define REV_B0 (MAJOR_REV_B | MINOR_REV_0) +#define REV_B1 (MAJOR_REV_B | MINOR_REV_1) +#define REV_B2 (MAJOR_REV_B | MINOR_REV_2) +#define REV_B3 (MAJOR_REV_B | MINOR_REV_3) +#define REV_B4 (MAJOR_REV_B | MINOR_REV_4) +#define REV_B5 (MAJOR_REV_B | MINOR_REV_5) +#define REV_BX (MAJOR_REV_B | MINOR_REV_ALL) + +#define REV_C0 (MAJOR_REV_C | MINOR_REV_0) +#define REV_C1 (MAJOR_REV_C | MINOR_REV_1) +#define REV_C2 (MAJOR_REV_C | MINOR_REV_2) +#define REV_C3 (MAJOR_REV_C | MINOR_REV_3) +#define REV_C4 (MAJOR_REV_C | MINOR_REV_4) +#define REV_C5 (MAJOR_REV_C | MINOR_REV_5) +#define REV_CX (MAJOR_REV_C | MINOR_REV_ALL) + +#define REV_D0 (MAJOR_REV_D | MINOR_REV_0) +#define REV_D1 (MAJOR_REV_D | MINOR_REV_1) +#define REV_D2 (MAJOR_REV_D | MINOR_REV_2) +#define REV_D3 (MAJOR_REV_D | MINOR_REV_3) +#define REV_D4 (MAJOR_REV_D | MINOR_REV_4) +#define REV_D5 (MAJOR_REV_D | MINOR_REV_5) +#define REV_DX (MAJOR_REV_D | MINOR_REV_ALL) + +#define REV_E0 (MAJOR_REV_E | MINOR_REV_0) +#define REV_E1 (MAJOR_REV_E | MINOR_REV_1) +#define REV_E2 (MAJOR_REV_E | MINOR_REV_2) +#define REV_E3 (MAJOR_REV_E | MINOR_REV_3) +#define REV_E4 (MAJOR_REV_E | MINOR_REV_4) +#define REV_E5 (MAJOR_REV_E | MINOR_REV_5) +#define REV_EX (MAJOR_REV_E | MINOR_REV_ALL) + +#define REV_F0 (MAJOR_REV_F | MINOR_REV_0) +#define REV_F1 (MAJOR_REV_F | MINOR_REV_1) +#define REV_F2 (MAJOR_REV_F | MINOR_REV_2) +#define REV_F3 (MAJOR_REV_F | MINOR_REV_3) +#define REV_F4 (MAJOR_REV_F | MINOR_REV_4) +#define REV_F5 (MAJOR_REV_F | MINOR_REV_5) +#define REV_FX (MAJOR_REV_F | MINOR_REV_ALL) + +#define REV_G0 (MAJOR_REV_G | MINOR_REV_0) +#define REV_G1 (MAJOR_REV_G | MINOR_REV_1) +#define REV_G2 (MAJOR_REV_G | MINOR_REV_2) +#define REV_G3 (MAJOR_REV_G | MINOR_REV_3) +#define REV_G4 (MAJOR_REV_G | MINOR_REV_4) +#define REV_G5 (MAJOR_REV_G | MINOR_REV_5) +#define REV_GX (MAJOR_REV_G | MINOR_REV_ALL) + +#define REV_H0 (MAJOR_REV_H | MINOR_REV_0) +#define REV_H1 (MAJOR_REV_H | MINOR_REV_1) +#define REV_H2 (MAJOR_REV_H | MINOR_REV_2) +#define REV_H3 (MAJOR_REV_H | MINOR_REV_3) +#define REV_H4 (MAJOR_REV_H | MINOR_REV_4) +#define REV_H5 (MAJOR_REV_H | MINOR_REV_5) +#define REV_HX (MAJOR_REV_H | MINOR_REV_ALL) + +#define REV_I0 (MAJOR_REV_I | MINOR_REV_0) +#define REV_I1 (MAJOR_REV_I | MINOR_REV_1) +#define REV_I2 (MAJOR_REV_I | MINOR_REV_2) +#define REV_I3 (MAJOR_REV_I | MINOR_REV_3) +#define REV_I4 (MAJOR_REV_I | MINOR_REV_4) +#define REV_I5 (MAJOR_REV_I | MINOR_REV_5) +#define REV_IX (MAJOR_REV_I | MINOR_REV_ALL) + +#define REV_J0 (MAJOR_REV_J | MINOR_REV_0) +#define REV_J1 (MAJOR_REV_J | MINOR_REV_1) +#define REV_J2 (MAJOR_REV_J | MINOR_REV_2) +#define REV_J3 (MAJOR_REV_J | MINOR_REV_3) +#define REV_J4 (MAJOR_REV_J | MINOR_REV_4) +#define REV_J5 (MAJOR_REV_J | MINOR_REV_5) +#define REV_JX (MAJOR_REV_J | MINOR_REV_ALL) + +#define REV_K0 (MAJOR_REV_K | MINOR_REV_0) +#define REV_K1 (MAJOR_REV_K | MINOR_REV_1) +#define REV_K2 (MAJOR_REV_K | MINOR_REV_2) +#define REV_K3 (MAJOR_REV_K | MINOR_REV_3) +#define REV_K4 (MAJOR_REV_K | MINOR_REV_4) +#define REV_K5 (MAJOR_REV_K | MINOR_REV_5) +#define REV_KX (MAJOR_REV_K | MINOR_REV_ALL) + +#define REV_L0 (MAJOR_REV_L | MINOR_REV_0) +#define REV_L1 (MAJOR_REV_L | MINOR_REV_1) +#define REV_L2 (MAJOR_REV_L | MINOR_REV_2) +#define REV_L3 (MAJOR_REV_L | MINOR_REV_3) +#define REV_L4 (MAJOR_REV_L | MINOR_REV_4) +#define REV_L5 (MAJOR_REV_L | MINOR_REV_5) +#define REV_LX (MAJOR_REV_L | MINOR_REV_ALL) + +#define REV_M0 (MAJOR_REV_M | MINOR_REV_0) +#define REV_M1 (MAJOR_REV_M | MINOR_REV_1) +#define REV_M2 (MAJOR_REV_M | MINOR_REV_2) +#define REV_M3 (MAJOR_REV_M | MINOR_REV_3) +#define REV_M4 (MAJOR_REV_M | MINOR_REV_4) +#define REV_M5 (MAJOR_REV_M | MINOR_REV_5) +#define REV_MX (MAJOR_REV_M | MINOR_REV_ALL) + +#define REV_N0 (MAJOR_REV_N | MINOR_REV_0) +#define REV_N1 (MAJOR_REV_N | MINOR_REV_1) +#define REV_N2 (MAJOR_REV_N | MINOR_REV_2) +#define REV_N3 (MAJOR_REV_N | MINOR_REV_3) +#define REV_N4 (MAJOR_REV_N | MINOR_REV_4) +#define REV_N5 (MAJOR_REV_N | MINOR_REV_5) +#define REV_NX (MAJOR_REV_N | MINOR_REV_ALL) + +#define REV_O0 (MAJOR_REV_O | MINOR_REV_0) +#define REV_O1 (MAJOR_REV_O | MINOR_REV_1) +#define REV_O2 (MAJOR_REV_O | MINOR_REV_2) +#define REV_O3 (MAJOR_REV_O | MINOR_REV_3) +#define REV_O4 (MAJOR_REV_O | MINOR_REV_4) +#define REV_O5 (MAJOR_REV_O | MINOR_REV_5) +#define REV_OX (MAJOR_REV_O | MINOR_REV_ALL) + +#define REV_P0 (MAJOR_REV_P | MINOR_REV_0) +#define REV_P1 (MAJOR_REV_P | MINOR_REV_1) +#define REV_P2 (MAJOR_REV_P | MINOR_REV_2) +#define REV_P3 (MAJOR_REV_P | MINOR_REV_3) +#define REV_P4 (MAJOR_REV_P | MINOR_REV_4) +#define REV_P5 (MAJOR_REV_P | MINOR_REV_5) +#define REV_PX (MAJOR_REV_P | MINOR_REV_ALL) + +#define REV_Q0 (MAJOR_REV_Q | MINOR_REV_0) +#define REV_Q1 (MAJOR_REV_Q | MINOR_REV_1) +#define REV_Q2 (MAJOR_REV_Q | MINOR_REV_2) +#define REV_Q3 (MAJOR_REV_Q | MINOR_REV_3) +#define REV_Q4 (MAJOR_REV_Q | MINOR_REV_4) +#define REV_Q5 (MAJOR_REV_Q | MINOR_REV_5) +#define REV_QX (MAJOR_REV_Q | MINOR_REV_ALL) + +#define REV_R0 (MAJOR_REV_R | MINOR_REV_0) +#define REV_R1 (MAJOR_REV_R | MINOR_REV_1) +#define REV_R2 (MAJOR_REV_R | MINOR_REV_2) +#define REV_R3 (MAJOR_REV_R | MINOR_REV_3) +#define REV_R4 (MAJOR_REV_R | MINOR_REV_4) +#define REV_R5 (MAJOR_REV_R | MINOR_REV_5) +#define REV_RX (MAJOR_REV_R | MINOR_REV_ALL) + +#define REV_S0 (MAJOR_REV_S | MINOR_REV_0) +#define REV_S1 (MAJOR_REV_S | MINOR_REV_1) +#define REV_S2 (MAJOR_REV_S | MINOR_REV_2) +#define REV_S3 (MAJOR_REV_S | MINOR_REV_3) +#define REV_S4 (MAJOR_REV_S | MINOR_REV_4) +#define REV_S5 (MAJOR_REV_S | MINOR_REV_5) +#define REV_SX (MAJOR_REV_S | MINOR_REV_ALL) + +#define REV_T0 (MAJOR_REV_T | MINOR_REV_0) +#define REV_T1 (MAJOR_REV_T | MINOR_REV_1) +#define REV_T2 (MAJOR_REV_T | MINOR_REV_2) +#define REV_T3 (MAJOR_REV_T | MINOR_REV_3) +#define REV_T4 (MAJOR_REV_T | MINOR_REV_4) +#define REV_T5 (MAJOR_REV_T | MINOR_REV_5) +#define REV_TX (MAJOR_REV_T | MINOR_REV_ALL) + +#define REV_U0 (MAJOR_REV_U | MINOR_REV_0) +#define REV_U1 (MAJOR_REV_U | MINOR_REV_1) +#define REV_U2 (MAJOR_REV_U | MINOR_REV_2) +#define REV_U3 (MAJOR_REV_U | MINOR_REV_3) +#define REV_U4 (MAJOR_REV_U | MINOR_REV_4) +#define REV_U5 (MAJOR_REV_U | MINOR_REV_5) +#define REV_UX (MAJOR_REV_U | MINOR_REV_ALL) + +#define REV_V0 (MAJOR_REV_V | MINOR_REV_0) +#define REV_V1 (MAJOR_REV_V | MINOR_REV_1) +#define REV_V2 (MAJOR_REV_V | MINOR_REV_2) +#define REV_V3 (MAJOR_REV_V | MINOR_REV_3) +#define REV_V4 (MAJOR_REV_V | MINOR_REV_4) +#define REV_V5 (MAJOR_REV_V | MINOR_REV_5) +#define REV_VX (MAJOR_REV_V | MINOR_REV_ALL) + +#define REV_W0 (MAJOR_REV_W | MINOR_REV_0) +#define REV_W1 (MAJOR_REV_W | MINOR_REV_1) +#define REV_W2 (MAJOR_REV_W | MINOR_REV_2) +#define REV_W3 (MAJOR_REV_W | MINOR_REV_3) +#define REV_W4 (MAJOR_REV_W | MINOR_REV_4) +#define REV_W5 (MAJOR_REV_W | MINOR_REV_5) +#define REV_WX (MAJOR_REV_W | MINOR_REV_ALL) + +#define REV_X0 (MAJOR_REV_X | MINOR_REV_0) +#define REV_X1 (MAJOR_REV_X | MINOR_REV_1) +#define REV_X2 (MAJOR_REV_X | MINOR_REV_2) +#define REV_X3 (MAJOR_REV_X | MINOR_REV_3) +#define REV_X4 (MAJOR_REV_X | MINOR_REV_4) +#define REV_X5 (MAJOR_REV_X | MINOR_REV_5) +#define REV_XX (MAJOR_REV_X | MINOR_REV_ALL) + +#define REV_Y0 (MAJOR_REV_Y | MINOR_REV_0) +#define REV_Y1 (MAJOR_REV_Y | MINOR_REV_1) +#define REV_Y2 (MAJOR_REV_Y | MINOR_REV_2) +#define REV_Y3 (MAJOR_REV_Y | MINOR_REV_3) +#define REV_Y4 (MAJOR_REV_Y | MINOR_REV_4) +#define REV_Y5 (MAJOR_REV_Y | MINOR_REV_5) +#define REV_YX (MAJOR_REV_Y | MINOR_REV_ALL) + +#define REV_Z0 (MAJOR_REV_Z | MINOR_REV_0) +#define REV_Z1 (MAJOR_REV_Z | MINOR_REV_1) +#define REV_Z2 (MAJOR_REV_Z | MINOR_REV_2) +#define REV_Z3 (MAJOR_REV_Z | MINOR_REV_3) +#define REV_Z4 (MAJOR_REV_Z | MINOR_REV_4) +#define REV_Z5 (MAJOR_REV_Z | MINOR_REV_5) +#define REV_ZX (MAJOR_REV_Z | MINOR_REV_ALL) + +#define REV_ALL (MAJOR_REV_ALL | MINOR_REV_ALL) +#endif \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration= .h b/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h new file mode 100644 index 0000000000..c15ec034ec --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h @@ -0,0 +1,22 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EMULATION_CONFIGURATION_H_ +#define _EMULATION_CONFIGURATION_H_ + +// +// Emulation Setting Values +// +#define EMULATION_AUTO 0 +#define EMULATION_DISABLE 1 +#define EMULATION_ENABLE 2 + +#endif // _EMULATION_CONFIGURATION_H_ + + + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h b/Silicon/Intel= /WhitleySiliconPkg/Include/Fpga.h new file mode 100644 index 0000000000..758b6f845d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h @@ -0,0 +1,17 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FPGA_DATA_H_ +#define _FPGA_DATA_H_ + +// Max Sockets for FPGA's, for all arrays, index loops,... +// Note: all bit mask arrays are defined as "UINT8", so if this increases +// Those will have to be refactored to hold the new data. +#define FPGA_MAX_SOCKET MAX_SOCKET + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h b/Silicon= /Intel/WhitleySiliconPkg/Include/GpioConfig.h new file mode 100644 index 0000000000..700e629d3c --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h @@ -0,0 +1,288 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig and Host Software Pad Ownership are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 4; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, both In w= ith inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 5; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting i= s applicable only if GPIO is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 8; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 4; + + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 7; + + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 3; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 27; ///< Reserved bits for future extension + UINT32 RsvdBits1; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault =3D 0x0 +} GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio =3D 0x1, + GpioPadModeNative1 =3D 0x3, + GpioPadModeNative2 =3D 0x5, + GpioPadModeNative3 =3D 0x7, + GpioPadModeNative4 =3D 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi =3D 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio =3D 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault =3D 0x0, ///< Leave pad direction setti= ng unmodified + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both output a= nd input + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both output a= nd input with inversion + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input with in= version + GpioDirOut =3D 0x5, ///< Set pad for output only + GpioDirNone =3D 0x7 ///< Disable both output and i= nput +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault =3D 0x0, ///< Leave output value unmodified + GpioOutLow =3D 0x1, ///< Set output to low + GpioOutHigh =3D 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC= /SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to= GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing = unmodified + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inter= rupt generation + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered (= type of edge depends on input inversion) + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigge= red +} GPIO_INT_CONFIG; + +#define GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source +#define GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) w= hich will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + + + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmodi= fied + /// + /// LBG configuration + /// + GpioResetPwrGood =3D 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (P= adRstCfg =3D 00b =3D "Powergood") + GpioResetDeep =3D 0x0B, ///< Deep GPIO Reset (PadRstCfg =3D = 01b =3D "Deep GPIO Reset") + GpioResetNormal =3D 0x0D, ///< GPIO Reset (PadRstCfg =3D 10b = =3D "GPIO Reset" ) + GpioResetResume =3D 0x0F, ///< GPP: Reserved; GPD: RSMRST; (Pa= dRstCfg =3D 11b =3D "Resume Reset") + + /// + /// New GPIO reset configuration options + /// + /** + Resume Reset (RSMRST) + GPP: PadRstCfg =3D 00b =3D "Powergood" + GPD: PadRstCfg =3D 11b =3D "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset =3D 0x01, + /** + Host Deep Reset + PadRstCfg =3D 01b =3D "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset =3D 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg =3D 10b =3D "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset =3D 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg =3D 00b =3D "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset =3D 0x07 +} GPIO_RESET_CONFIG; + + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with GpioTol= erance1v8. +/// +typedef enum { + GpioTermDefault =3D 0x0, ///< Leave termination setting unmo= dified + GpioTermNone =3D 0x1, ///< none + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative =3D 0x1F, ///< Native function controls pads = termination + GpioNoTolerance1v8 =3D (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 =3D (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value +#define GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for = GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault =3D 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock =3D 0x3, ///< Lock Pad Configuration + GpioOutputStateLock =3D 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future exten= sions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and= native usage). +/// The override takes place at the internal pad state directly from b= uffer and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default =3D 0x0, ///< Use default input override value + GpioRxRaw1Dis =3D 0x1, ///< Don't override input + GpioRxRaw1En =3D 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVaria= ble.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h new file mode 100644 index 0000000000..2b7d4cc86d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h @@ -0,0 +1,25 @@ +/** @file + Data format for Emulation + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __EMULATION_DFX_VARIABLE_H__ +#define __EMULATION_DFX_VARIABLE_H__ + +#pragma pack(1) +typedef struct { + UINT8 DfxUbiosGeneration; + UINT8 DfxHybridSystemLevelEmulation; + UINT8 DfxPmMsrTrace; +} EMULATION_DFX_CONFIGURATION; +#pragma pack() + +extern EFI_GUID gEmulationDfxVariableGuid; +#define EMULATION_DFX_CONFIGURATION_NAME L"EmulationDfxConfig" + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariabl= e.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h new file mode 100644 index 0000000000..96e9f6d428 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h @@ -0,0 +1,39 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FPGA_SOCKET_CONFIGURATION_DATA_H__ +#define __FPGA_SOCKET_CONFIGURATION_DATA_H__ + +#include + +extern EFI_GUID gFpgaSocketVariableGuid; +#define FPGA_SOCKET_CONFIGURATION_NAME L"FpgaSocketConfig" + +#pragma pack(1) + +typedef struct { + + // User Bitmap to enable the FPGA socket. + UINT8 FpgaSetupEnabled; + + // for each socket enabled, use this Bit stream GUID Index + // Note: variable is Index+ 1 for unused default to be 0 + UINT8 FpgaSocketGuid[FPGA_MAX_SOCKET]; + // FPGA Temperature Threshold 1/2: Max value clamped at 100 C; + // i.e. if the SW tries to write value greater than 100 C, HW will autom= atically default to 100 C. + UINT8 FpgaThermalTH1[FPGA_MAX_SOCKET]; + UINT8 FpgaThermalTH2[FPGA_MAX_SOCKET]; + + // FPGA reserved data + UINT8 FpgaReserved[14]; +} FPGA_SOCKET_CONFIGURATION; +#pragma pack() + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h new file mode 100644 index 0000000000..5b760117f7 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h @@ -0,0 +1,71 @@ +/** @file + MemBootHealthGuid.h + + Header for using Structured PCD in MemBootHealth + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_BOOT_HEALTH_GUID_H_ +#define _MEM_BOOT_HEALTH_GUID_H_ + +// Enable Mem boot health check feature +#define MEM_BOOT_HEALTH_ENABLE 1 +// Disable Mem boot health check feature +#define MEM_BOOT_HEALTH_DISABLE 0 + +// Mem Boot Health check option +// Option to choose Mem Boot Health configuration type. +// 00=3D>Auto (Use defaults) +#define MEM_BOOT_HEALTH_CONFIG_AUTO 0 +// 01=3D>Manual(Override defaults with setup option) +#define MEM_BOOT_HEALTH_CONFIG_MANUAL 1 +// 02=3D>Disable (Disable feature) +#define MEM_BOOT_HEALTH_CONFIG_DISABLE 2 + +#define ENABLE_REBOOT_ON_CRITICAL_FAILURE 1 +#define DISABLE_REBOOT_ON_CRITICAL_FAILURE 0 + +#pragma pack(1) +typedef struct { + + // + // Memory Boot Health Check + // + UINT8 MemBootHealthVisible; // 0 =3D> Hide Memory b= oot health check option, 1 =3D> Enable the option in setup + + UINT8 MemBootHealthCheck; // 0=3D>Auto, 1=3D>Manua= l and 2=3D>Disabled Memory Boot Health Check + + UINT8 ResetOnCriticalError; // 0 =3D> Dont reboot on= critical error, 1 =3D Reboot on critical error + // + // Memory Boot Health check parameters + // + UINT8 WarningTxDqDelayLeftEdge; + UINT8 WarningTxDqDelayRightEdge; + UINT8 WarningTxVrefLeftEdge; + UINT8 WarningTxVrefRightEdge; + UINT8 WarningRxDqsDelayLeftEdge; + UINT8 WarningRxDqsDelayRightEdge; + UINT8 WarningRxVrefLeftEdge; + UINT8 WarningRxVrefRightEdge; + + UINT8 CriticalTxDqDelayLeftEdge; + UINT8 CriticalTxDqDelayRightEdge; + UINT8 CriticalTxVrefLeftEdge; + UINT8 CriticalTxVrefRightEdge; + UINT8 CriticalRxDqsDelayLeftEdge; + UINT8 CriticalRxDqsDelayRightEdge; + UINT8 CriticalRxVrefLeftEdge; + UINT8 CriticalRxVrefRightEdge; +} MEM_BOOT_HEALTH_CONFIG; +#pragma pack() + +#define MEM_BOOT_HEALTH_GUID { 0xACD56900, 0xDEFC, 0x4127, { 0xDE, 0x12, 0= x32, 0xA0, 0xD2, 0x69, 0x46, 0x2F } } + +#define MEM_BOOT_HEALTH_SETUP_STR L"MemBootHealthConfig" + +extern EFI_GUID gMemBootHealthGuid; +#endif // _MEM_BOOT_HEALTH_GUID_H_ \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b= /Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..1512b90881 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h @@ -0,0 +1,197 @@ +/** @file + GUID used for Memory Map Data entries in the HOB list. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_MAP_DATA_H_ +#define _MEMORY_MAP_DATA_H_ + +#include "SysHost.h" +#include "PartialMirrorGuid.h" + +#define RESERVED_2 2 +#define RESERVED_4 4 + +// +// System Memory Map HOB information +// + +#pragma pack(1) +struct RankDevice { + UINT8 enabled; // 0 =3D disabled, 1 =3D enabled + UINT8 logicalRank; // Logical Rank number (0 - 7) + UINT16 rankSize; // Units of 64 MB +}; + +struct PersisentDpaMap +{ + UINT32 perRegionDPAOffset; + UINT32 SPALimit; +}; + +typedef struct DimmDevice { + UINT8 Present; + BOOLEAN Enabled; + UINT8 DcpmmPresent; // 1 - This is a DCPMM + UINT8 X4Present; + UINT8 NumRanks; + UINT8 keyByte; + UINT8 actKeyByte2; // Actual module type reported by SPD + UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device wi= dth + UINT8 dimmTs; // Thermal sensor data. + UINT16 VolCap; // Volatile capacity (AEP DIMM only) + UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only) + UINT16 DimmSize; + UINT32 NVmemSize; + UINT16 SPDMMfgId; // Module Mfg Id from SPD + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT32 perRegionDPA; // DPA of PMEM that Nfit needs + struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DP= A map + UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number + UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number + UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS= TYPE 17 + struct firmwareRev FirmwareVersion; // Firmware revision + struct RankDevice rankList[MAX_RANK_DIMM]; + UINT16 InterfaceFormatCode; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT16 FisVersion; // Firmware Interface Specification version + UINT8 DimmSku; // Dimm SKU info + UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM + UINT16 manufacturingDate; // Date the NVDIMM was manufactured + INT32 commonTck; + UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy = source; 2: no backup energy source + BOOLEAN NvDimmNPresent; ///< JEDEC NVDIMM-N Type Memory Present + UINT16 SPDRegVen; ///< Register Vendor ID in SPD + UINT8 CidBitMap; // SubRankPer CS for DIMM device +} MEMMAP_DIMM_DEVICE_INFO_STRUCT; + +struct ChannelDevice { + UINT8 Enabled; = // 0 =3D channel disabled, 1 =3D channel enabled + UINT8 Features; = // Bit mask of features to enable or disable + UINT8 MaxDimm; = // Number of DIMM + UINT8 NumRanks; = // Number of ranks on this channel + UINT8 chFailed; + UINT8 ngnChFailed; + UINT8 SpareLogicalRank[MAX_SPARE_RANK]; = // Logical rank, selected as Spare + UINT8 SparePhysicalRank[MAX_SPARE_RANK]; = // Physical rank, selected as spare + UINT16 SpareRankSize[MAX_SPARE_RANK]; = // spare rank size + UINT8 EnabledLogicalRanks; // Bitmap of Lo= gical ranks that are enabled + MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; +}; + +struct memcontroller { + UINT32 MemSize; +}; + +typedef struct socket { + UINT8 SocketEnabled; + UINT16 IioStackBitmap; + BOOLEAN Reserved[RESERVED_4]; + UINT8 imcEnabled[MAX_IMC]; + UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][MC_MAX_NODE]; /= / SAD interleave list + UINT8 SktSkuValid; // Whether Socket SKU= value is valid from PCU + UINT32 SktSkuLimit; // SKU limit value fr= om PCU + UINT32 SktTotMemMapSPA; // Total memory mappe= d to SPA + UINT32 SktPmemMapSpa; // Total persistent m= emory mapped to SPA + UINT32 SktMemSize2LM; // Total memory exclu= ded from Limit + SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; /= / SAD table + struct memcontroller imc[MAX_IMC]; + struct ChannelDevice ChannelInfo[MAX_CH]; +} MEMMAP_SOCKET; + +typedef struct SystemMemoryMapElement { + UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1= : 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ct= rl region + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ON= LY IN NUMA + UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on so= cket then ImcInterBitmap and ChInterBitmap are identical in all sockets + UINT8 ImcInterBitmap; // IMC interleave bitmap for this memory + UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are i= nterleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 = & 0 are interleaved + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks +} SYSTEM_MEMORY_MAP_ELEMENT; + +typedef struct SystemMemoryMapHob { + // + // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4= clusters. + // All2All/Quad/Hemi modes can be considered as having only one cluster = (i.e SNC1). + // + UINT8 TotalClusters; + + MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data st= ructure + UINT32 lowMemBase; // Mem base in 64MB unit= s for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB unit= s for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB unit= s for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB unit= s for above 4GB mem. + UINT32 memSize; // Total physical memory= size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - = Lockstep + UINT8 volMemMode; // 0 - 1LM, 1 - 2LM + UINT8 CacheMemType; // 0 - DDR$DDRT + UINT8 DdrtIntlvGranularity; // 1 - 256B, 2 - 4KB + UINT16 DramType; + UINT8 SmbMode[MAX_SOCKET][MAX_SMB_INSTANCE]; // Stores type of smbus = mode: 0 - I2C mode, 1 - I3C mode + UINT8 DdrVoltage; + UINT8 DcpmmPresent; // If at least one DCPMM P= resent (used by Nfit), then this should get set + BOOLEAN EkvPresent; // Set if EKV controller= on system + BOOLEAN BwvPresent; // Set if BWV controller= on system + UINT8 XMPProfilesSup; + UINT16 Reserved1[MAX_SOCKET]; + UINT32 Reserved2; + UINT32 Reserved3; + UINT16 Reserved4; + UINT16 Reserved5; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are en= abled + UINT16 ExRasModesEnabled; // Extended RAS modes th= at are enabled + UINT8 sncEnabled; // 0 - SNC disabled for = this configuration, 1 - SNC enabled for this configuration + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map = Elements + SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_= SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; + struct memSetup MemSetup; + MEM_RESERVED_1 Reserved142; + MEMMAP_SOCKET Socket[MAX_SOCKET]; + struct memTiming profileMemTime[2]; + + UINT32 Reserved6; + UINT8 Reserved7[RESERVED_2]; + EFI_GUID Reserved8[RESERVED_2]; + UINT8 Reserved9; + RASMEMORYINFO RasMeminfo; + UINT8 LatchSystemShutdownState; + BOOLEAN IsWpqFlushSupported; + UINT8 EadrSupport; + UINT8 EadrCacheFlushMode; + UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCK= ET * MAX_DCPMM_CH + HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH]; + UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memo= ry reserved for 2LM cache (64MB granularity) + BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for In= tel PMEM Modules + UINT16 BiosFisVersion; // Firmware Interfa= ce Specification version currently supported by BIOS + UINT16 MaxAveragePowerLimit; // Max Power limit = in mW used for averaged power ( Valid range ends at 15000mW) + UINT16 MinAveragePowerLimit; // Min Power limit = in mW used for averaged power ( Valid range starts from 10000mW) + UINT16 CurrAveragePowerLimit; // Current Power li= mit in mW used for average power + UINT16 MaxMbbPowerLimit; // Max MBB power li= mit ( Valid range ends at 18000mW). + UINT16 MinMbbPowerLimit; // Min MBB power li= mit ( Valid range starts from 15000mW). + UINT16 CurrMbbPowerLimit; // Current Power li= mit in mW used for MBB power + UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average = Power Time Constant + UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average = Power Time Constant + UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Aver= age Power Time Constant + UINT32 MmiohBase; // MMIOH base in 64= MB granularity + UINT8 MaxSadRules; // Maximum SAD entr= ies supported by silicon (24 for 14nm silicon, 16 for 10nm silicon) + UINT8 NumberofChaDramClusters; // Number of CHA DR= AM decoder clusters + UINT8 VirtualNumaEnable; // Enable or Disabl= e Virtual NUMA + UINT8 VirtualNumOfCluster; // Number of Virtua= l NUMA nodes in each physical NUMA node (Socket or SNC cluster) + BOOLEAN NumaEnable; // Information if N= UMA is enabled or not +} SYSTEM_MEMORY_MAP_HOB; + +#pragma pack() + +#endif // _MEMORY_MAP_DATA_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h new file mode 100644 index 0000000000..17fb93a163 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h @@ -0,0 +1,61 @@ +/** @file + GUID used for ADDRESS_RANGE_MIRROR_VARIABLE. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PARTIAL_MIRROR_GUID_H_ +#define _PARTIAL_MIRROR_GUID_H_ + +#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, {= 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } } + +#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent" +#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest" +#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VAR= IABLE_DATA) +#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE= | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS) +#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1 +#define MIRROR_STATUS_SUCCESS 0 +#define MIRROR_STATUS_MIRROR_INCAPABLE 1 +#define MIRROR_STATUS_VERSION_MISMATCH 2 +#define MIRROR_STATUS_INVALID_REQUEST 3 +#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4 +#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5 + +extern EFI_GUID gAddressBasedMirrorGuid; + +#pragma pack(1) + +typedef struct { +// +// MirroredAmountAbove4GB is the amount of available memory above 4GB that= needs to be mirrored +// measured in basis point (hundredths of percent e.g. 12.75% =3D 1275). +// In a multi-socket system, platform is required to distribute the mirror= ed memory ranges such that the +// amount mirrored is approximately proportional to the amount of memory = on each NUMA node. E.g. on +// a two node machine with 64GB on node 0 and 32GB on node 1, a request fo= r 12GB of mirrored memory +// should be allocated with 8GB of mirror on node 0 and 4GB on node 1. +// +// For example, if the total memory in the system is 48GB and 12GB of memo= ry above the 4GB addresses needs to be mirrored then the amount would be: +// Total Memory =3D 48 GB +// Total Memory above 4GB =3D 44 GB +// Percentage =3D 8/44 * 100 =3D 18.18% =3D 1818 basis points +// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB= on socket 1, +// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to m= aintain the requested 18%. +// This ensures that OS has an adequate amount of mirrored memory on each = NUMA domain. +// + UINT8 MirrorVersion; + BOOLEAN MirrorMemoryBelow4GB; + UINT16 MirroredAmountAbove4GB; + UINT8 MirrorStatus; +} ADDRESS_RANGE_MIRROR_VARIABLE_DATA; + +typedef struct { + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType; + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType; +} RASMEMORYINFO; +#pragma pack() + + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h b/= Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h new file mode 100644 index 0000000000..2bce1aa905 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h @@ -0,0 +1,150 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_H_ +#define _PLATFORM_INFO_H_ + +#include + +extern EFI_GUID gEfiPlatformInfoGuid; + +#pragma pack(1) + +typedef struct { + UINT32 ReservedPci; +} EFI_PLATFORM_PCI_DATA; + +typedef struct { + UINT32 ReservedCpu; +} EFI_PLATFORM_CPU_DATA; + +typedef struct { + UINT64 SysIoApicEnable; + UINT8 SysSioExist; + UINT8 IsocEn; // Isoc Enabled + UINT8 MeSegEn; // Me Seg Enabled. + UINT8 DmiVc1; // 0 - Disable, 1 - Enable + UINT8 SocketConfig; + UINT8 DmiVcm; // 0 - Disable, 1 - Enable + UINT8 DmiReserved; // for alignment +} EFI_PLATFORM_SYS_DATA; + +typedef struct { + UINT32 BiosGuardPhysBase; + UINT32 BiosGuardMemSize; + UINT32 MemTsegSize; + UINT32 MemIedSize; + +#ifdef LT_FLAG + UINT32 MemLtMemSize; // Below TSEG, contains (high to low: (Heap, S= initMem, reserved)3M, LtDevMemNonDMA 2M) + UINT32 MemDprMemSize; // 6M DPR contained in LtMem + UINT32 MemLtMemAddress; +#endif // #ifdef LT_FLAG + + UINT64 PsmiUcTraceRegionBase; + UINT64 PsmiUcTraceRegionSize; +} EFI_PLATFORM_MEM_DATA; + +typedef struct { + UINT8 PchPciePortCfg1; // PCIE Port Configuration Strap 1 + UINT8 PchPciePortCfg2; // PCIE Port Configuration Strap 2 + UINT8 PchPciePortCfg3; // PCIE Port Configuration Strap 3 + UINT8 PchPciePortCfg4; // PCIE Port Configuration Strap 4 + UINT8 PchPciePortCfg5; // PCIE Port Configuration Strap 5 + UINT8 PchPcieSBDE; + UINT8 LomLanSupported; // Indicates if PCH LAN on board is supported= or not + UINT8 GbePciePortNum; // Indicates the PCIe port qhen PCH LAN on bo= ard is connnected. + UINT8 GbeRegionInvalid; + BOOLEAN GbeEnabled; // Indicates if the GBE is SS disabled + UINT8 PchStepping; +} EFI_PLATFORM_PCH_DATA; + +// +// Platform Deep Sleep Feature +// +typedef struct { + UINT8 PlatformDeepS5; + UINT8 DeepS5DelayTime; +} EFI_PLATFORM_DEEPS5_DATA; + +typedef struct { + UINT8 EnableClockSpreadSpec; +} EFI_PLATFORM_EXTERNAL_CLOCK; + +/// +/// Enumeration of possible Wilson City interposer types +/// +typedef enum { + InterposerUnknown =3D 0, ///< Type is unknown and should be retrieved= from the Platform HOB + InterposerA, ///< Interposer Type A + InterposerB, ///< Interposer Type B + InterposerMax ///< Maximum number of members of this enum +} INTERPOSER_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 MappedMcId[MAX_IMC]; +} INTERPOSER; + +typedef struct { + INTERPOSER Interposer[InterposerMax]; +} INTERPOSER_MAP; +#pragma pack() + +// +// This HOB definition must be consistent with what is created in the +// PlatformInfo protocol definition. This way the information in the +// HOB can be directly copied upon the protocol and only the strings +// will need to be updated. +// +typedef struct _EFI_PLATFORM_INFO { + UINT8 SystemUuid[16]; // 16 bytes + CHAR8 SerialNumber[64]; // 64 bytes + UINT32 Signature; // "$PIT" 0x54495024 + UINT32 Size; // Size of the table + UINT16 Revision; // Revision of the t= able + UINT16 Type; // Platform Type + UINT32 CpuType; // Cpu Type + UINT8 CpuStepping; // Cpu Stepping + UINT32 TypeRevisionId; // Board Revision ID + UINT8 BoardId; // Board ID + UINT16 IioSku; + UINT16 IioRevision; + UINT16 PchSku; + UINT8 PchRevision; + UINT8 PchType; // Retrive PCH SKU t= ype installed + UINT8 MaxNumOfPchs; // Maximum Number of= installed PCHs + BOOLEAN ExtendedInfoValid; // If TRUE then belo= w fields are Valid + UINT8 Checksum; // Checksum minus Sy= stemUuid is valid in DXE only. + UINT64 TypeStringPtr; + UINT64 IioStringPtr; + UINT64 PchStringPtr; + EFI_PLATFORM_PCI_DATA PciData; + EFI_PLATFORM_CPU_DATA CpuData; + EFI_PLATFORM_MEM_DATA MemData; + EFI_PLATFORM_SYS_DATA SysData; + EFI_PLATFORM_PCH_DATA PchData; + UINT8 IioRiserId; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 PlatformCapabilities; // Platform capabili= tes describes platform is 2-socket modular board, 4S or 8S + // + // Wilson City Interposer Type + // + INTERPOSER_TYPE InterposerType[MAX_SOCKET]; = // 0 - Unknown, 1 - InterposerA, 2 - InterposerB + UINT32 QATDis; = // 0 - QAT Enabled; 1 - Disabled + UINT32 QATSel; + UINT8 MemoryTopology[MAX_SOCKET][MAX_IMC*MAX_MC_CH= ]; // Specifies the memory topology per socket-per channel + UINT8 MemoryConnectorType[MAX_SOCKET][MAX_IMC*MAX_= MC_CH]; // Specifies the memory connector type per socket-per channel, type= EFI_MEMORY_DIMM_CONNECTOR_TYPE + EFI_PLATFORM_DEEPS5_DATA DeepS5Data; + EFI_PLATFORM_EXTERNAL_CLOCK ExternalClock; +} EFI_PLATFORM_INFO; + +#pragma pack() + +#endif // #ifndef _PLATFORM_INFO_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInit= LibInterface.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicy= InitLibInterface.h new file mode 100644 index 0000000000..57037c96dd --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInte= rface.h @@ -0,0 +1,78 @@ +/** @file + This provides a versatile abstraction for the SiliconPolicyInitLib libra= ry interface. + + This defines the typedef necessary for PPI and protocol use. + This defines structs for PPI and protocol production and consumption. + There is a single GUID defining both PPI and protocol. + +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SILICON_POLICY_INIT_LIB_INTERFACE_H_ +#define _SILICON_POLICY_INIT_LIB_INTERFACE_H_ + +#include + +// +// All interface declarations should refer to the SiliconPolicyInitLib for= description of functionality +// + +typedef +VOID * +(EFIAPI *PEI_SILICON_POLICY_INIT_PRE_MEM) ( + IN OUT VOID *Policy OPTIONAL + ); + +typedef +RETURN_STATUS +(EFIAPI *PEI_SILICON_POLICY_DONE_PRE_MEM) ( + IN VOID *Policy + ); + +typedef +VOID * +(EFIAPI *PEI_SILICON_POLICY_INIT_POST_MEM) ( + IN OUT VOID *Policy OPTIONAL + ); + +typedef +RETURN_STATUS +(EFIAPI *PEI_SILICON_POLICY_DONE_POST_MEM) ( + IN VOID *Policy + ); + +typedef +VOID * +(EFIAPI *PEI_SILICON_POLICY_INIT_LATE) ( + IN OUT VOID *Policy OPTIONAL + ); + +typedef +RETURN_STATUS +(EFIAPI *PEI_SILICON_POLICY_DONE_LATE) ( + IN VOID *Policy + ); + +// +// PPI structure declaration +// +typedef struct { + PEI_SILICON_POLICY_INIT_PRE_MEM SiliconPolicyInitPreMem; + PEI_SILICON_POLICY_DONE_PRE_MEM SiliconPolicyDonePreMem; + PEI_SILICON_POLICY_INIT_POST_MEM SiliconPolicyInitPostMem; + PEI_SILICON_POLICY_DONE_POST_MEM SiliconPolicyDonePostMem; +} SILICON_POLICY_INIT_LIB_PPI; + +// +// Protocol structure declaration +// +typedef struct { + PEI_SILICON_POLICY_INIT_LATE SiliconPolicyInitLate; + PEI_SILICON_POLICY_DONE_LATE SiliconPolicyDoneLate; +} SILICON_POLICY_INIT_LIB_PROTOCOL; + +extern EFI_GUID gSiliconPolicyInitLibInterfaceGuid; + +#endif // _SILICON_POLICY_INIT_LIB_INTERFACE_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVar= iable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariab= le.h new file mode 100644 index 0000000000..8bc88cd97c --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h @@ -0,0 +1,57 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__ +#define __SOCKET_COMMONRC_CONFIG_DATA_H__ + + +#include + +extern EFI_GUID gEfiSocketCommonRcVariableGuid; +#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig" + +#define UMABASEDCLUSTERING_DISABLED 0 +#define UMABASEDCLUSTERING_HEMISPHERE 2 +#define UMABASEDCLUSTERING_QUADRANT 4 + +#pragma pack(1) +typedef struct { + // + // Common Section of RC + // + UINT32 MmiohBase; + UINT16 MmiohSize; + UINT8 MmcfgBase; + UINT8 MmcfgSize; + UINT8 IsocEn; + UINT8 NumaEn; + UINT8 UmaBasedClustering; + UINT8 MirrorMode; + UINT8 CpuType; + UINT8 CpuChop; + UINT8 X2ApicForceEn; + UINT8 SystemRasType; + UINT8 NumCpus; + UINT8 ReservedS6; + UINT8 ReservedS7[MAX_B2P_MAILBOX_GROUPS]; + UINT8 OcCap; + UINT8 IssMaxLevel; + UINT8 DcpmmEnable; + UINT8 ReservedS8; + UINT8 HbmSku; + UINT8 PbfCapableSystem; + UINT8 DcuRtlWaEn; + UINT8 SstCpCapableSystem; + UINT8 VirtualNumaEnable; +} SOCKET_COMMONRC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h new file mode 100644 index 0000000000..7df44e93c3 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h @@ -0,0 +1,444 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SOCKET_IIO_VARIABLE_H_ +#define _SOCKET_IIO_VARIABLE_H_ + +#include + +extern EFI_GUID gEfiSocketIioVariableGuid; +#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig" + +/* + These vars are not used anywhere - it is left here for reference as this= is used in comments below. + Number must be used directly because of VFR compiler... + + #ifndef MAX_STACKS_PER_SOCKET_VAR + #define MAX_STACKS_PER_SOCKET_VAR 6 + #define MAX_PORTS_PER_SOCKET_VAR 21 + #endif + #endif +*/ + +#if MAX_SOCKET =3D=3D 1 + #define TOTAL_VMD_STACKS_VAR 6 // MAX_STACKS_PER_SOCK= ET_VAR * MAX_SOCKET + + #define TOTAL_NTB_PORTS_VAR 5 // NUMBER_NTB_PORTS_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_IOU_VAR 5 // MAX_IOU_PER_SOCKET = * MAX_SOCKET + #define TOTAL_VMD_PCH_ROOTPORTS_VAR 20 // MAX_PCH_ROOTPORTS *= MAX_SOCKET + #define TOTAL_RETIMERS_VAR 12 // MAX_SOCKET * MAX_ST= ACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related) + + #define TOTAL_NPK_VAR 1 // NUMBER_TRACE_HUB_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_PORTS_VAR 21 // MAX_PORTS_PER_SOCKE= T_VAR * MAX_SOCKET + #define TOTAL_VMD_PORTS_VAR 24 // MAX_PORTS_PER_STACK= * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET + #define TOTAL_DSA_VAR 1 // 1_DSA_PER_SOCKET * = MAX_SOCKET + #define TOTAL_IAX_VAR 1 // 1_IAX_PER_SOCKET * = MAX_SOCKET + #define TOTAL_CPM_VAR 1 // 1_CPM_PER_SOCKET * = MAX_SOCKET + #define TOTAL_HQM_VAR 1 // 1_HQM_PER_SOCKET * = MAX_SOCKET + +#endif + +#if MAX_SOCKET =3D=3D 4 + #define TOTAL_VMD_STACKS_VAR 24 // MAX_STACKS_PER_SOCK= ET_VAR * MAX_SOCKET + #define TOTAL_NTB_PORTS_VAR 20 // NUMBER_NTB_PORTS_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_IOU_VAR 20 // MAX_IOU_PER_SOCKET = * MAX_SOCKET + #define TOTAL_VMD_PCH_ROOTPORTS_VAR 80 // MAX_PCH_ROOTPORTS *= MAX_SOCKET + #define TOTAL_RETIMERS_VAR 48 // MAX_SOCKET * MAX_ST= ACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related) + #define TOTAL_NPK_VAR 4 // NUMBER_TRACE_HUB_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_PORTS_VAR 84 // MAX_PORTS_PER_SOCKE= T_VAR * MAX_SOCKET + #define TOTAL_VMD_PORTS_VAR 96 // MAX_PORTS_PER_STACK= * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET + #define TOTAL_DSA_VAR 4 // 1_DSA_PER_SOCKET * = MAX_SOCKET + #define TOTAL_IAX_VAR 4 // 1_IAX_PER_SOCKET * = MAX_SOCKET + #define TOTAL_CPM_VAR 4 // 1_CPM_PER_SOCKET * = MAX_SOCKET + #define TOTAL_HQM_VAR 4 // 1_HQM_PER_SOCKET * = MAX_SOCKET +#endif + +#if MAX_SOCKET =3D=3D 2 + #define TOTAL_VMD_STACKS_VAR 12 // MAX_STACKS_PER_SOCK= ET_VAR * MAX_SOCKET + #define TOTAL_NTB_PORTS_VAR 10 // NUMBER_NTB_PORTS_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_IOU_VAR 10 // MAX_IOU_PER_SOCKET = * MAX_SOCKET + #define TOTAL_VMD_PCH_ROOTPORTS_VAR 40 // MAX_PCH_ROOTPORTS *= MAX_SOCKET + #define TOTAL_RETIMERS_VAR 24 // MAX_SOCKET * MAX_ST= ACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related) + #define TOTAL_NPK_VAR 2 // NUMBER_TRACE_HUB_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_PORTS_VAR 42 // MAX_PORTS_PER_SOCKE= T_VAR * MAX_SOCKET + #define TOTAL_VMD_PORTS_VAR 48 // MAX_PORTS_PER_STACK= * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET + #define TOTAL_DSA_VAR 2 // 1_DSA_PER_SOCKET * = MAX_SOCKET + #define TOTAL_IAX_VAR 2 // 1_IAX_PER_SOCKET * = MAX_SOCKET + #define TOTAL_CPM_VAR 2 // 1_CPM_PER_SOCKET * = MAX_SOCKET + #define TOTAL_HQM_VAR 2 // 1_HQM_PER_SOCKET * = MAX_SOCKET +#endif + +#if MAX_SOCKET > 4 + #define TOTAL_VMD_PCH_ROOTPORTS_VAR 160 // MAX_PCH_ROOTPORTS *= MAX_SOCKET + #define TOTAL_NTB_PORTS_VAR 40 // NUMBER_NTB_PORTS_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_IOU_VAR 40 // MAX_IOU_PER_SOCKET = * MAX_SOCKET + #define TOTAL_VMD_STACKS_VAR 48 // MAX_STACKS_PER_SOCK= ET_VAR * MAX_SOCKET + #define TOTAL_RETIMERS_VAR 96 // MAX_SOCKET * MAX_ST= ACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related) + #define TOTAL_NPK_VAR 8 // NUMBER_TRACE_HUB_PE= R_SOCKET * MAX_SOCKET + #define TOTAL_PORTS_VAR 168 // MAX_PORTS_PER_SOCKE= T_VAR * MAX_SOCKET + #define TOTAL_VMD_PORTS_VAR 192 // MAX_PORTS_PER_STACK= * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET + #define TOTAL_DSA_VAR MAX_SOCKET // 1_DSA_PER_SOCKET * = MAX_SOCKET + #define TOTAL_IAX_VAR MAX_SOCKET // 1_IAX_PER_SOCKET * = MAX_SOCKET + #define TOTAL_CPM_VAR MAX_SOCKET // 1_CPM_PER_SOCKET * = MAX_SOCKET + #define TOTAL_HQM_VAR MAX_SOCKET // 1_HQM_PER_SOCKET * = MAX_SOCKET +#endif + +#pragma pack(1) + +typedef struct { + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VTd Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VTdSupport; + UINT8 DmaCtrlOptIn; + UINT8 InterruptRemap; + UINT8 PostedInterrupt; + UINT8 ATS; + UINT8 CoherencySupport; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIE Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + // Vars used to configure (disable/greyout) parts of setup menu + UINT8 IioPresent[MAX_SOCKET]; + UINT8 IioStackPresent[TOTAL_IIO_STACKS]; // based on sysInfo data + UINT8 PchPresentOnStack[MAX_SOCKET]; // stub for multiPCH + UINT8 RetimerPresent[TOTAL_RETIMERS_VAR]; // retimer detected in sta= ck + + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 PcieHotPlugOnPort[TOTAL_PORTS_VAR]; + UINT8 SLOTHPSUP[TOTAL_PORTS_VAR]; // Hot Plug surprise suppo= rted - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; + UINT8 ConfigIOU1[MAX_SOCKET]; + UINT8 ConfigIOU2[MAX_SOCKET]; + UINT8 ConfigIOU3[MAX_SOCKET]; + UINT8 ConfigIOU4[MAX_SOCKET]; + UINT8 ConfigIOU5[MAX_SOCKET]; + UINT8 ConfigIOU6[MAX_SOCKET]; + UINT8 ConfigIOU7[MAX_SOCKET]; + UINT8 PcieSubSystemMode[TOTAL_IOU_VAR]; + UINT8 CompletionTimeoutGlobal; + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; + UINT8 StopAndScream; + UINT8 SnoopResponseHoldOff; + // + // PCIE capability + // + UINT8 PCIe_LTR; + UINT8 PcieExtendedTagField; + UINT8 Pcie10bitTag; + UINT8 PCIe_AtomicOpReq; + UINT8 PcieMaxReadRequestSize; + UINT8 PciePtm; + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + // mixc PCIE configuration + UINT8 PcieLinkDis[TOTAL_PORTS_VAR]; // On Setup + UINT8 PcieAspm[TOTAL_PORTS_VAR]; // On Setup + UINT8 PcieCommonClock[TOTAL_PORTS_VAR]; // On Setup + UINT8 PcieMaxPayload[TOTAL_PORTS_VAR]; // On Setup PRD + UINT8 PcieDState[TOTAL_PORTS_VAR]; // On Setup + UINT8 PcieL1Latency[TOTAL_PORTS_VAR]; // On Setup + UINT8 MsiEn[TOTAL_PORTS_VAR]; // On Setup + UINT8 ExtendedSync[TOTAL_PORTS_VAR]; // On Setup + UINT8 PciePortEnable[TOTAL_PORTS_VAR]; // On Setup + UINT8 IODC[TOTAL_PORTS_VAR]; // On Setup + UINT8 MctpEn[TOTAL_PORTS_VAR]; // On Setup + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[TOTAL_PORTS_VAR]; //on Setup + UINT8 ComplianceMode[TOTAL_PORTS_VAR]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[TOTAL_PORTS_VAR]; // On Setup + UINT8 DeEmphasis[TOTAL_PORTS_VAR]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[TOTAL_PORTS_VAR]; // On Setup + UINT8 MSIFATEN[TOTAL_PORTS_VAR]; //On Setup. + UINT8 MSINFATEN[TOTAL_PORTS_VAR]; //On Setup. + UINT8 MSICOREN[TOTAL_PORTS_VAR]; //On Setup. + UINT8 ACPIPMEn[TOTAL_PORTS_VAR]; //On Setup + UINT8 P2PRdDis[TOTAL_PORTS_VAR]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[TOTAL_PORTS_VAR]; //On Setup + UINT8 ACPIHP[TOTAL_PORTS_VAR]; //On Setup + UINT8 ACPIPM[TOTAL_PORTS_VAR]; //On Setup + UINT8 SRIS[TOTAL_PORTS_VAR]; //On Setup + UINT8 TXEQ[TOTAL_PORTS_VAR]; //On Setup + UINT8 SERRE[TOTAL_PORTS_VAR]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[TOTAL_PORTS_VAR]; // Unsupported Req= uest per-port option + + // + // PCIE Link Training Ctrl + // + + + // + // North Peak (NPK) + // + + UINT8 NorthTraceHubMode[TOTAL_NPK_VAR]; + UINT32 NorthTraceHubMemReg0Size[TOTAL_NPK_VAR]; + UINT32 NorthTraceHubMemReg1Size[TOTAL_NPK_VAR]; + + // + // Sierra Peak (SPK) + // + UINT8 SierraPeakMemBufferSize[MAX_SOCKET]; + + // + // MMIO poison enabling per stack + // + UINT8 PoisonMmioReadEn[TOTAL_IIO_STACKS]; // on setup +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Crystal Beach 3 Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + UINT8 CbDmaMultiCastEnable; // CbDmaMu= ltiCastEnable test enable + + UINT8 DsaEn[TOTAL_DSA_VAR]; // on setup + UINT8 IaxEn[TOTAL_IAX_VAR]; // on setup + UINT8 CpmEn[TOTAL_CPM_VAR]; // on setup + UINT8 HqmEn[TOTAL_HQM_VAR]; // on setup + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D MISC IOH Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[TOTAL_PORTS_VAR]; // Hide any of the DMI o= r PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; + // Hide IOAPIC Device= 5, Function 4 + UINT8 PCUF6Hide; // Hide Device PCU Devic= e 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K gra= nularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 Xppdef; + UINT8 Pci64BitResourceAllocation; + UINT8 PcieBiosTrainEnable; // Used as a work around= for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test = enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + + + UINT8 HidePEXPMenu[TOTAL_PORTS_VAR]; // to suppress /displa= y the PCIe port menu + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D NTB Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 NtbPpd[TOTAL_NTB_PORTS_VAR]; //on setup opti= on + UINT8 NtbBarSizeOverride[TOTAL_NTB_PORTS_VAR]; //on setup opti= on + UINT8 NtbSplitBar[TOTAL_NTB_PORTS_VAR]; //on setup option + UINT8 NtbBarSizeImBar1[TOTAL_NTB_PORTS_VAR]; //on setup opti= on + UINT8 NtbBarSizeImBar2[TOTAL_NTB_PORTS_VAR]; //on setup opti= on + UINT8 NtbBarSizeImBar2_0[TOTAL_NTB_PORTS_VAR]; //on setup o= ption + UINT8 NtbBarSizeImBar2_1[TOTAL_NTB_PORTS_VAR]; //on setup o= ption + UINT8 NtbBarSizeEmBarSZ1[TOTAL_NTB_PORTS_VAR]; //on setup op= tion + UINT8 NtbBarSizeEmBarSZ2[TOTAL_NTB_PORTS_VAR]; //on setup op= tion + UINT8 NtbBarSizeEmBarSZ2_0[TOTAL_NTB_PORTS_VAR]; //on setup= option + UINT8 NtbBarSizeEmBarSZ2_1[TOTAL_NTB_PORTS_VAR]; //on setup= option + UINT8 NtbXlinkCtlOverride[TOTAL_NTB_PORTS_VAR]; //on setup opti= on + + UINT8 NtbLinkBiosTrainEn; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VMD Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VMDEnabled[TOTAL_VMD_STACKS_VAR]; // indicates i= f VMD is enabled on given stack + UINT8 VMDPortEnable[TOTAL_VMD_PORTS_VAR]; // indicated i= f VMD is enabled on given port is enabled + UINT8 VMDPchPortAllowed[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates i= f VMD CAN BE enabled on given PCH Rp + UINT8 VMDPchPortEnable[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates i= f VMD IS enabled on given PCH Rp + UINT8 VMDHotPlugEnable[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDCfgBarSz[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDCfgBarAttr[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDMemBarSz1[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDMemBar1Attr[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDMemBarSz2[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDMemBar2Attr[TOTAL_VMD_STACKS_VAR]; + UINT8 VMDDirectAssign[TOTAL_VMD_STACKS_VAR]; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIe SSD Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + + UINT8 PcieAICEnabled[TOTAL_VMD_STACKS_VAR]; + UINT8 PcieAICPortEnable[TOTAL_PORTS_VAR]; + UINT8 PcieAICHotPlugEnable[TOTAL_VMD_STACKS_VAR]; + + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Retimers Related Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + + UINT32 RetimerGlParmReg0Override[TOTAL_RETIMERS_VAR]; + UINT32 RetimerPseudoPort0Reg2Override[TOTAL_RETIMERS_VAR]; + UINT32 RetimerPseudoPort1Reg2Override[TOTAL_RETIMERS_VAR]; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= PCI-E Port Clock Gating Related Setup Options =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 PciePortClkGateEnable[TOTAL_PORTS_VAR]; // Indicate= s Clock gating for this PCIe port is enabled or not + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIe Global Related Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 PcieLowLatencyRetimersEnabled; + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup + UINT8 PcieEnqCmdSupport; //On setup + UINT16 DelayBeforePCIeLinkTraining; //On Setup +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Reserved Setup Options =3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 ReservedS9; + UINT8 ReservedS10; + UINT8 ReservedS11; // On Setup + UINT8 ReservedS12; // On Setup + UINT8 ReservedS13; // On Setup + UINT8 ReservedS14; // On Setup + UINT8 ReservedS15; // On Setup + UINT8 ReservedS16; // On Setup + UINT8 ReservedS17; // On Setup + UINT8 ReservedS18; // On Setup + UINT8 ReservedS19; // On Setup + UINT8 ReservedS20; // On Setup + UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup + + UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS25[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS26[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS27[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS28[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS29[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS30[TOTAL_PORTS_VAR]; //On Setup + + UINT8 ReservedS31[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS32[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS33[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS34[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS35[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS36[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS37[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS38[TOTAL_PORTS_VAR]; //On Setup + + UINT8 ReservedS39[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS40[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS41[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS42[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS43[TOTAL_PORTS_VAR]; //On Setup + + + UINT8 ReservedS44[TOTAL_PORTS_VAR]; + UINT8 ReservedS45[TOTAL_PORTS_VAR]; //On Setup + UINT8 ReservedS46; //On Setup + + UINT8 ReservedS47; //On Setup + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO = Global Performance Tuner Related Setup Options =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 PerformanceTuningMode; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PC= I-E Data Link Feature Exchange Enable =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 PcieDataLinkFeatureExchangeEnable[TOTAL_PORTS_VAR]; //On Setup + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = Variables added post Beta =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 PcieTxRxDetPoll[TOTAL_PORTS_VAR]; + UINT8 EcrcGenEn[TOTAL_PORTS_VAR]; //On Setup + UINT8 EcrcChkEn[TOTAL_PORTS_VAR]; //On Setup + UINT8 ControlIommu; + UINT32 VtdDisabledBitmask[MAX_SOCKET]; + UINT8 X2ApicOptOut; + UINT8 SkipRetimersDetection; + + UINT8 VtdPciAcsCtlWaEn; // Enables override of ACSCTL on PCI= e root ports for VTd + UINT8 VtdPciAcsCtlBit0; + UINT8 VtdPciAcsCtlBit1; + UINT8 VtdPciAcsCtlBit2; + UINT8 VtdPciAcsCtlBit3; + UINT8 VtdPciAcsCtlBit4; +} SOCKET_IIO_CONFIGURATION; +#pragma pack() + +#endif // _SOCKET_IIO_VARIABLE_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVaria= ble.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h new file mode 100644 index 0000000000..533489fafc --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h @@ -0,0 +1,477 @@ +/** @file + Data format for Ioh Memory Config Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__ +#define __SOCKET_MEMORY_CONFIG_DATA_H__ + + +#include +#include + +extern EFI_GUID gEfiSocketMemoryVariableGuid; +#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig" + +#pragma pack(1) +typedef struct { + UINT8 ReservedS48; + UINT8 MemoryHotPlugBase; + UINT8 MemoryHotPlugLen; + UINT8 Srat; + UINT8 SratMemoryHotPlug; + UINT8 SratCpuHotPlug; + UINT8 PagePolicy; + UINT8 PatrolScrub; + UINT8 PatrolScrubDuration; + UINT8 TempRefreshOption; + UINT8 HalfxRefreshValue; + UINT8 TwoxRefreshValue; + UINT8 FourxRefreshValue; + UINT8 NsddcEn; + UINT8 EsddcEn; + UINT8 ColumnCorrectionDisable; + UINT8 SaiPolicyGroupWaBiosW; + UINT8 PatrolScrubAddrMode; + UINT8 partialmirrorsad0; + UINT8 PartialMirrorUefi; + UINT16 PartialMirrorUefiPercent; + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array = of sizes of different partial mirrors + UINT8 ImmediateFailoverAction; + UINT8 PlusOneEn; + UINT8 MemCeFloodPolicy; + UINT16 spareErrTh; + UINT8 TriggerSWErrThEn; + UINT16 SpareSwErrTh; + UINT16 timeWindow; + UINT8 DieSparing; + UINT8 PclsEn; + UINT8 ADDDCEn; + UINT8 DcpmmEccModeSwitch; + UINT8 AdddcErrInjEn; + UINT8 leakyBktTimeWindow; + UINT8 leakyBktLo; + UINT8 leakyBktHi; + UINT16 leakyBktHour; + UINT8 leakyBktMinute; + UINT8 CmdNormalization; + UINT8 LrDimmBacksideVrefEn; + UINT8 CmdVrefEnable; + UINT8 DramRonEn; + UINT8 McRonEn; + UINT8 RxCtleTrnEn; + UINT8 RxOdtEn; + UINT8 LrDimmWrVrefEn; + UINT8 LrDimmRdVrefEn; + UINT8 LrDimmTxDqCentering; + UINT8 LrDimmRxDqCentering; + UINT8 txEqCalibration; + UINT8 CmdTxEqCalibration; + UINT8 RxDfe; + UINT8 TxRiseFallSlewRate; + UINT8 iModeTraining; + UINT8 TcoCompTraining; + UINT8 RoundTripLatency; + UINT8 DutyCycleTraining; + UINT8 PxcTraining; + UINT8 DdjcTraining; + UINT8 refreshMode; + UINT8 dllResetTestLoops; + UINT8 DdrMemoryType; + UINT8 HwMemTest; + UINT16 MemTestLoops; + UINT8 TrainingResultOffsetFunctionEnable; + UINT16 OffsetTxDq; + UINT16 OffsetRxDq; + UINT16 OffsetTxVref; + UINT16 OffsetRxVref; + UINT16 OffsetCmdAll; + UINT16 OffsetCmdVref; + UINT16 OffsetCtlAll; + UINT32 AdvMemTestOptions; + UINT8 AdvMemTestResetList; + UINT8 AdvMemTestCondition; + UINT16 AdvMemTestCondVdd; + UINT8 AdvMemTestCondTwr; + UINT16 AdvMemTestCondTrefi; + UINT32 AdvMemTestCondPause; + UINT8 EccSupport; + UINT8 EccEnable; + UINT8 ReservedS49; + UINT8 ReservedS50; + UINT8 ReservedS51; + UINT8 ReservedS52; + UINT16 ReservedS53; + UINT16 ReservedS54; + UINT16 ReservedS55; + UINT16 ReservedS56; + UINT16 ReservedS57; + UINT8 ReservedS58; + UINT16 ReservedS59; + UINT8 ReservedS60; + UINT16 ReservedS61; + UINT8 ReservedS62; + UINT8 ReservedS63; + UINT16 ReservedS64; + UINT16 ReservedS65; + UINT8 ReservedS66; + UINT8 ReservedS67; + UINT8 ReservedS68; + UINT8 ReservedS69; + UINT8 ReservedS70; + UINT8 ReservedS71; + UINT8 ReservedS72; + UINT8 ReservedS73; + UINT8 ReservedS74[16]; //[MAX_SOCKET * MAX_IMC] =3D= [8] + UINT8 volMemMode; + UINT8 CacheMemType; //Only valid if volMemMode is 2LM + UINT8 DdrCacheSize; + UINT8 PmemCaching; + UINT8 ReservedS75; + UINT8 memInterleaveGran1LM; + UINT8 ReservedS76; + UINT8 ReservedS77; + UINT8 ReservedS78; + UINT8 ReservedS79; + UINT8 ReservedS80; + UINT8 CkeProgramming; + UINT8 SrefProgramming; + UINT8 PkgcSrefEn; + UINT8 CkeIdleTimer; + UINT8 ApdEn; + UINT8 PpdEn; + UINT8 DdrtCkeEn; + UINT8 OppSrefEn; + UINT8 OppSrefVisible; //Setup variable to hide Oppo= rtunistic Self Refresh Knob + UINT8 DdrtSrefEn; + UINT8 DataDllOff; + UINT8 MdllOffEn; + UINT8 CkMode; + UINT8 MemTestOnColdFastBoot; + UINT8 AttemptFastBoot; + UINT8 AttemptFastBootCold; + UINT8 bdatEn; + UINT8 ScrambleEnDDRT; + UINT8 ScrambleEn; // for ddr4 + UINT8 allowCorrectableError; + UINT8 allowCorrectableMemTestError; + UINT16 ScrambleSeedLow; + UINT16 ScrambleSeedHigh; + UINT8 CustomRefreshRateEn; + UINT8 CustomRefreshRate; + UINT8 readVrefCenter; + UINT8 wrVrefCenter; + UINT8 haltOnMemErr; + UINT8 thermalthrottlingsupport; + UINT8 MemTripReporting; + UINT8 OffPkgMemToThermTrip; + UINT8 OffPkgMemToMemTrip; + UINT8 InPkgMemToThermTrip; + UINT8 InPkgMemToMemTrip; + UINT8 DimmTempStatValue; + UINT8 XMPProfilesSup; + UINT8 XMPMode; + UINT8 tCAS; + UINT8 tRP; + UINT8 tRCD; + UINT8 tRAS; + UINT8 tWR; + UINT16 tRFC; + UINT8 tRRD; + UINT8 tRRD_L; + UINT8 tRTP; + UINT8 tWTR; + UINT8 tFAW; + UINT8 tCWL; + UINT8 tRC; + UINT8 commandTiming; + UINT16 tREFI; + UINT8 DdrFreqLimit; + UINT16 Vdd; + UINT8 lrdimmModuleDelay; + UINT32 rmtPatternLength; + UINT32 rmtPatternLengthExt; + UINT8 RecEnDelayAverage; + UINT8 check_pm_sts; + UINT8 check_platform_detect; + UINT8 MemPwrSave; + UINT8 ElectricalThrottlingMode; + UINT8 MultiThreaded; + UINT8 promoteMrcWarnings; + UINT8 promoteWarnings; + UINT8 oppReadInWmm; + UINT16 normOppInterval; + UINT8 ReservedS81[96]; //[MAX_SETUP_SOCKET * MAX_SETUP= _IMC * MAX_SETUP_MC_CH] =3D [8 * 4 * 3 =3D 96] + UINT8 mdllSden; + UINT8 memhotSupport; + UINT8 MemHotIn; + UINT8 MemHotOut; + UINT8 MemHotOuputAssertThreshold; + UINT8 ADREn; + UINT8 RankMargin; + UINT8 EnableBacksideRMT; + UINT8 EnableBacksideCMDRMT; + UINT8 EnableNgnBcomMargining; + UINT8 ReservedS82; + UINT8 RankSparing; + UINT8 multiSparingRanks; + UINT8 ReservedS83; + UINT8 dimmIsolation; + UINT8 smbSpeed; + UINT8 SmbSpdAccess; + UINT8 SpdPrintEn; + UINT16 SpdPrintLength; + UINT8 EnforcePOR; + UINT8 pda; + UINT8 turnaroundOpt; + UINT8 turnaroundOptDdrt; + UINT8 oneRankTimingMode; + UINT8 eyeDiagram; + UINT8 NvmdimmPerfConfig; + UINT8 ReservedS84; + UINT8 ReservedS85; + UINT8 ReservedS86; + UINT8 ReservedS87; + UINT8 ReservedS88; + UINT8 ReservedS89; + UINT8 ReservedS90; + UINT8 ReservedS91; + UINT8 ReservedS92; + UINT8 ReservedS93; + UINT8 ReservedS94; + UINT8 ReservedS95; + UINT8 ReservedS96; + UINT8 ReservedS97; + UINT8 ReservedS98; + UINT8 ReservedS99; + UINT8 ReservedS100; + UINT8 ReservedS101; + UINT8 ReservedS102; + UINT8 ReservedS103; + UINT8 ReservedS104; + UINT8 DramRaplPwrLimitLockCsr; + UINT8 DramRaplEnable; + UINT8 BwLimitTfOvrd; + UINT8 perbitmargin; + UINT8 DramRaplExtendedRange; + UINT8 CmsEnableDramPm; + UINT8 logParsing; + UINT8 WritePreamble; + UINT8 ReadPreamble; + UINT8 WrCRC; + UINT8 AepOnSystem; + UINT8 EkvOnSystem; // 0 =3D> Do not suppress power m= anagement policy for BWV, 1 =3D> suppress power management policy for BWV. + UINT8 BwvOnSystem; // 0 =3D> Do not suppress power m= anagement policy for EKV, 1 =3D> suppress power management policy for EKV. + // NGN options + UINT8 LockNgnCsr; + UINT8 NgnCmdTime; + UINT8 NgnEccCorr; + UINT8 NgnEccWrChk; + UINT8 NgnEccRdChk; + UINT8 NgnEccExitCorr; + UINT8 NgnDebugLock; + UINT8 NgnArsPublish; + UINT8 RmtOnColdFastBoot; + UINT8 LegacyRmt; + UINT8 mrcRepeatTest; + UINT8 ReservedS105; + UINT8 ReservedS106; + UINT8 ReservedS107; + UINT8 staggerref; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT32 memFlowsExt2; + UINT32 memFlowsExt3; + UINT8 Blockgnt2cmd1cyc; + UINT8 TrefiPerChannel; + UINT8 TrefiNumofRank; + UINT16 TrefiDelay; + UINT8 Disddrtopprd; + UINT16 Reserved; + UINT8 setSecureEraseAllDIMMs; + UINT8 setSecureEraseSktCh[64]; // [MAX_SOCKET * MAX_I= MC * MAX_MC_CH] + UINT8 SetSecureEraseSktChHob[64]; // [MAX_SOCKET * MAX= _IMC * MAX_MC_CH] + UINT8 AppDirectMemoryHole; + UINT8 LatchSystemShutdownState; + UINT8 ExtendedType17; + // + // PPR related + // + UINT8 pprType; + UINT8 pprErrInjTest; + // CR QoS Configuration Profiles + UINT8 FastGoConfig; + UINT8 ReservedS108; + UINT8 LegacyADRModeEn; + UINT8 MinNormalMemSize; + UINT8 ADRDataSaveMode; + UINT8 eraseArmNVDIMMS; + UINT8 restoreNVDIMMS; + UINT8 interNVDIMMS; + UINT8 imcBclk; + UINT8 spdCrcCheck; + UINT8 ReservedS109; + UINT8 SETUP_REMOVE_SanitizeOverwriteNvmDimm; // remov= ed + UINT8 EliminateDirectoryInFarMemory; + UINT8 NvmdimmPowerCyclePolicy; + + //CMI Init option + UINT8 CmiInitOption; + // + // Cmd setup hold percent offset for 2n timing + // + UINT8 cmdSetupPercentOffset; + UINT8 ShortStroke2GB; + UINT8 NvDimmEnergyPolicy; //Energy Policy Manageme= nt + UINT8 ReservedS110; + UINT8 ReservedS111; + UINT8 ReservedS112; + UINT8 ReservedS113; + UINT8 DisableDirForAppDirect; + UINT8 NvmMediaStatusException; + UINT8 NvmQos; + UINT8 ReservedS114; + UINT8 ReservedS115; + UINT8 ReservedS116; + + // + // FIS 2.x + // + UINT16 DcpmmAveragePowerLimit; // Power limit in= mW used for averaged power ( Valid range starts from 10000mW). + UINT8 DcpmmAveragePowerTimeConstant; // Value used = as a base time window for power usage measurements Turbo Mode Support(in mS= ec). + UINT32 DcpmmMbbAveragePowerTimeConstant; // Value used = as a base time window for power usage measurements Memory Bandwidth Boost S= upport(in mSec). + UINT8 DcpmmMbbFeature; // Allows enab= ling and disabling the feature (Turbo Mode State/Memory Bandwidth Boost). + UINT16 DcpmmMbbMaxPowerLimit; // Power limit= in mW used for limiting the Turbo Mode/Memory Bandwidth Boost + // power consu= mption (Valid range starts from 15000mW). + + UINT8 ReservedS117; + UINT8 ReservedS118; + UINT8 ReservedS119; + + UINT8 ReservedS120; + UINT8 LsxImplementation; + UINT8 FactoryResetClear; + UINT8 EadrSupport; + UINT32 NvdimmSmbusMaxAccessTime; + UINT32 NvdimmSmbusReleaseDelay; + UINT8 NfitPublishMailboxStructs; + + // + // fADR setup option + // + UINT8 FadrSupport; + + // + // Biased 2-way near memory cache support options + // + UINT8 EnableTwoWayNmCache; // Enable or disab= le biased 2-way near memory cache. + UINT16 NonPreferredWayMask; // A 10-bit mask t= o control the bias counter ratio. + UINT8 PreferredReadFirst; // Reads are issue= d to the non-preferred or preferred way first. + + // + // Boot-time fast zero memory setup option + // + UINT8 FastZeroMemSupport; // Enable or disab= le boot-time fast zero memory support. + + // + // XOR decoder options + // + UINT8 ReservedS121; + UINT8 ReservedS122; + UINT8 ReservedS123; + UINT8 ReservedS124; + UINT8 ReservedS125; + UINT8 ReservedS126; + UINT8 ReservedS127; + + UINT8 ReservedS128; + UINT8 ReservedS129; + + UINT8 ReservedS130; + UINT16 ReservedS131; + UINT8 ReservedS132; + UINT8 ReservedS133; + UINT8 ReservedS134; + UINT8 ReservedS135; + UINT8 DcpmmApiVersion200OnSystem; // 0 =3D> Suppress= DcpmmAveragePowerTimeConstant, 1 =3D> Do not suppress DcpmmAveragePowerTim= eConstant. + UINT8 DcpmmApiVersion201OnSystem; // 0 =3D> Suppress= DcpmmAveragePowerTimeConstant, 1 =3D> Do not suppress DcpmmAveragePowerTim= eConstant. + UINT8 DcpmmApiVersion200OrGreaterOnSystem; + UINT8 ReservedS136; + UINT8 EnforcePopulationPor; + + // + // DFE Path Finding + // + UINT8 EnableTapSweep; + + UINT8 DfeGainBias; + + UINT8 Tap1Start; + UINT8 Tap1End; + UINT8 Tap1Size; + + UINT8 Tap2Start; + UINT8 Tap2End; + UINT8 Tap2Size; + + UINT8 Tap3Start; + UINT8 Tap3End; + UINT8 Tap3Size; + + UINT8 Tap4Start; + UINT8 Tap4End; + UINT8 Tap4Size; + + UINT8 TrainingCompOptions; // Memory Training= Comp Options Values. + + UINT8 PeriodicRcomp; // Memory Periodic= Rcomp Auto/Enable/Disable. + UINT8 PeriodicRcompInterval; // Memory Periodic= Rcomp Interval. + + UINT8 ReservedS137; + + UINT8 AepNotSupportedException; + + UINT8 ReservedS138; + + UINT8 ReservedS139; + UINT8 PanicWm; + + UINT16 OffsetRecEn; + + UINT8 EadrCacheFlushMode; + UINT8 ReservedS140; + UINT8 ReservedS141; + UINT8 ReservedS142; + UINT8 ReservedS143; + + UINT8 ReservedS144; + UINT8 ReservedS145; + UINT8 LrdimmDbDfeTraining; + + UINT8 ReservedS146; + UINT8 ReservedS147; + UINT8 ReservedS148; + UINT8 AdvMemTestRetryAfterRepair; + UINT8 AdvMemTestPpr; + UINT8 AdvMemTestRankListNumEntries; + UINT32 AdvMemTestRankList[ADV_MT_LIST_LIMIT]; + + UINT32 SmartTestKey; + UINT8 SetMemTested; + + // + // RMT minimum margin check + // + UINT8 RmtMinimumMarginCheck; + + UINT8 ReservedS149; +} SOCKET_MEMORY_CONFIGURATION; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVaria= ble.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h new file mode 100644 index 0000000000..d279066b68 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h @@ -0,0 +1,320 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__ +#define __SOCKET_MP_LINK_CONFIG_DATA_H__ + +#include + +extern EFI_GUID gEfiSocketMpLinkVariableGuid; +#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig" + +#pragma pack(1) +typedef struct { + // SKXTODO: rename to Kti when removing HSX code + UINT8 QpiSetupNvVariableStartTag; // This must be the very first one o= f the whole KTI Setup NV variable! + + // + // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options + // The variables are used as a communication vehicle from the PciHostBri= dge DXE driver to an OEM hook + // which updates the KTI resource map + // + // + // KTI Host structure inputs + // + UINT8 BusRatio[MAX_SOCKET]; + UINT8 D2KCreditConfig; // 1 - Min, 2 - Med (Default), 3- Max + UINT8 SnoopThrottleConfig; // 0 - Disabled, 1 - Min, 2 - Med (Default)= , 3- Max + UINT8 SnoopAllCores; // 0 - Disabled, 1 - Enabled, 2 - Auto + UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range;= valid values are 0-3; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; = valid values are 0-3; 0 is default. + UINT8 P2pRelaxedOrdering; // 1 - Enable; 0 - Disable + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - In= fo Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOL= OGY_PRECEDENCE is default + UINT8 Degrade4SPreference; // 4S1LFullConnect topology is default; ano= ther option is 4S2LRing topology. + + // + // Phy/Link Layer Options + // + UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow = Speed; 1- Full Speed + UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104= GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (de= fault) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable + UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode + UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S To= pology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default) + UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (defaul= t), 0x00 - min + UINT8 SncEn; // 0 - Disable (default), 1 - Enable + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default= ), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALL= OC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default) + UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default)= ; 0 - Disable + UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default)= ; 0 - Disable + UINT8 XptRemotePrefetchEn; // XPT Remote Prefetch : 1 - Enable (D= efault); 0 - Disable + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disabl= e, 1 - Enable, 2- Auto (default) + UINT8 IrqThreshold; // KTI IRQ Threshold setting + UINT8 TorThresLoctoremNorm; // TOR threshold - Loctorem threshold n= ormal + UINT8 TorThresLoctoremEmpty; // TOR threshold - Loctorem threshold e= mpty + UINT8 MbeBwCal; // 0 - Linear, 1 - Biased, 2 - Legacy, = 3 - AUTO (default =3D Linear) + UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - En= able; 2 - AUTO (default) + UINT8 StaleAtoSOptEn; // HA A to S directory optimization + UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - En= able, 0 - Disable + UINT8 SplitLock; // Setting this bit removes the Ubox PC= U handshake during stopreq and startreq only + // for splitlocks: - Enable, 0 - Disable + UINT8 KtiAdaptationEn; // 0 - Disable, 1 - Enable + UINT8 KtiAdaptationSpeed; // Use KTI_LINK_SPEED definition; MAX_K= TI_LINK_SPEED - Auto (i.e BIOS choosen speed) + + UINT8 ReservedS150; + UINT8 ReservedS151; + UINT8 ReservedS152; + UINT8 ReservedS153; + UINT8 ReservedS154; + UINT8 ReservedS155; + UINT8 ReservedS156; + UINT8 ReservedS157; + UINT8 ReservedS158; + UINT8 ReservedS159; + UINT8 ReservedS160; + UINT8 ReservedS161; + UINT8 ReservedS162; + UINT8 ReservedS163; + UINT8 ReservedS164; + UINT8 ReservedS165; + UINT8 ReservedS166; + UINT8 ReservedS167; + UINT8 ReservedS168; + UINT8 ReservedS169; + UINT8 ReservedS170; + UINT8 ReservedS171; + UINT8 ReservedS172; + UINT8 ReservedS173; + UINT8 ReservedS174; + UINT8 ReservedS175; + UINT8 ReservedS176; + UINT8 ReservedS177; + UINT8 ReservedS178; + + UINT8 ReservedS179; + UINT8 ReservedS180; + UINT8 ReservedS181; + UINT8 ReservedS182; + UINT8 ReservedS183; + UINT8 ReservedS184; + UINT8 ReservedS185; + UINT32 ReservedS186; + + UINT8 ReservedS187; + UINT8 ReservedS188; + +#define UPICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##K= tiLinkVnaOverride; + + UINT8 KtiCpuPerPortStartTag; + UPICPUPRTVARIABLE (UINT8 Cpu0P0) + UPICPUPRTVARIABLE (UINT8 Cpu0P1) + UPICPUPRTVARIABLE (UINT8 Cpu0P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu0P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu0P4) + UPICPUPRTVARIABLE (UINT8 Cpu0P5) +#endif +#if MAX_SOCKET > 1 + UPICPUPRTVARIABLE (UINT8 Cpu1P0) + UPICPUPRTVARIABLE (UINT8 Cpu1P1) + UPICPUPRTVARIABLE (UINT8 Cpu1P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu1P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu1P4) + UPICPUPRTVARIABLE (UINT8 Cpu1P5) +#endif +#endif +#if MAX_SOCKET > 2 + UPICPUPRTVARIABLE (UINT8 Cpu2P0) + UPICPUPRTVARIABLE (UINT8 Cpu2P1) + UPICPUPRTVARIABLE (UINT8 Cpu2P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu2P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu2P4) + UPICPUPRTVARIABLE (UINT8 Cpu2P5) +#endif +#endif +#if MAX_SOCKET > 3 + UPICPUPRTVARIABLE (UINT8 Cpu3P0) + UPICPUPRTVARIABLE (UINT8 Cpu3P1) + UPICPUPRTVARIABLE (UINT8 Cpu3P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu3P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu3P4) + UPICPUPRTVARIABLE (UINT8 Cpu3P5) +#endif +#endif +#if (MAX_SOCKET > 4) + UPICPUPRTVARIABLE (UINT8 Cpu4P0) + UPICPUPRTVARIABLE (UINT8 Cpu4P1) + UPICPUPRTVARIABLE (UINT8 Cpu4P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu4P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu4P4) + UPICPUPRTVARIABLE (UINT8 Cpu4P5) +#endif +#endif +#if (MAX_SOCKET > 5) + UPICPUPRTVARIABLE (UINT8 Cpu5P0) + UPICPUPRTVARIABLE (UINT8 Cpu5P1) + UPICPUPRTVARIABLE (UINT8 Cpu5P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu5P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu5P4) + UPICPUPRTVARIABLE (UINT8 Cpu5P5) +#endif +#endif +#if (MAX_SOCKET > 6) + UPICPUPRTVARIABLE (UINT8 Cpu6P0) + UPICPUPRTVARIABLE (UINT8 Cpu6P1) + UPICPUPRTVARIABLE (UINT8 Cpu6P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu6P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu6P4) + UPICPUPRTVARIABLE (UINT8 Cpu6P5) +#endif +#endif +#if (MAX_SOCKET > 7) + UPICPUPRTVARIABLE (UINT8 Cpu7P0) + UPICPUPRTVARIABLE (UINT8 Cpu7P1) + UPICPUPRTVARIABLE (UINT8 Cpu7P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTVARIABLE (UINT8 Cpu7P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTVARIABLE (UINT8 Cpu7P4) + UPICPUPRTVARIABLE (UINT8 Cpu7P5) +#endif +#endif + +#define UPICPUPRTDFXVARIABLE(x) x##ReservedS189;x##ReservedS190;x##R= eservedS191;x##ReservedS246; + + UINT8 DfxKtiCpuPerPortStartTag; + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu0P5) +#endif +#if MAX_SOCKET > 1 + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu1P5) +#endif +#endif +#if MAX_SOCKET > 2 + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu2P5) +#endif +#endif +#if MAX_SOCKET > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu3P5) +#endif +#endif +#if MAX_SOCKET > 4 + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu4P5) +#endif +#endif +#if MAX_SOCKET > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu5P5) +#endif +#endif +#if MAX_SOCKET > 6 + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu6P5) +#endif +#endif +#if MAX_SOCKET > 7 + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P0) + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P1) + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P2) +#if MAX_KTI_PORTS > 3 + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P3) +#endif +#if MAX_KTI_PORTS > 5 + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P4) + UPICPUPRTDFXVARIABLE (UINT8 Cpu7P5) +#endif +#endif + + UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the wh= ole KTI Setup NV variable +} SOCKET_MP_LINK_CONFIGURATION; + +#pragma pack() + +#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResource= Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData= .h new file mode 100644 index 0000000000..567a44e73f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h @@ -0,0 +1,60 @@ +/** @file + UEFI variables used by DXE to pass PCI resource reconfiguration request = to PEI. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_ +#define _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_ + +extern EFI_GUID gEfiSocketPciResourceDataGuid; + +/** + * PCI MMIO and IO resource reconfiguration request structure. + **/ +#define SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SystemPciResourceCon= figData" + +typedef struct { + UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-= bit mmio regions) + UINT64 Limit; ///< Limit (last valid) address of a range +} PCIE_BASE_LIMIT; + +typedef struct { + PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to = entity + PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for en= tity + PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO reg= ion for entity +} PCI_BASE_LIMITS; + +typedef struct { + PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of= all PCIe resources for the socket + PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of= all PCIe resources for each stack of the socket +} SOCKET_PCI_BASE_LIMITS; + +typedef struct { + // + // Save basic system configuration parameters along with the resource ma= p to detect a change. + // Remember low and high I/O memory range when saving recource configura= tion. It is used to verify + // whether system memory map changed. Remember also stacks configured wh= en creating the map. + // If anything changed reset the system PCI resource configuration. + // + UINT64 MmioHBase; + UINT64 MmioHLimit; + UINT32 MmioLBase; + UINT32 MmioLLimit; + UINT16 IoBase; + UINT16 IoLimit; + UINT16 StackPresentBitmap[MAX_SOCKET]; + // + // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options + // The variables are used as a communication vehicle from the PciHostBri= dge DXE driver to an OEM hook + // which updates the KTI resource map. + // + SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of= all PCIe resources for each socket +} SYSTEM_PCI_BASE_LIMITS; + + +#endif // _SOCKET_PCI_RESOURCE_CONFIG_DATA_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanage= mentVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowerma= nagementVariable.h new file mode 100644 index 0000000000..460e6e300b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVar= iable.h @@ -0,0 +1,300 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ +#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ + + +#include + +extern EFI_GUID gEfiSocketPowermanagementVarGuid; +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementC= onfig" + +#define NUM_CST_LAT_MSR 3 + +#pragma pack(1) + +typedef struct { + UINT8 WFRWAEnable; + UINT8 UncoreFreqScaling; + UINT8 InputUncoreFreq; + UINT8 ProcessorEistSupport; // Gates EIST based on CPUID E= CX[7] + UINT8 ProcessorEistEnable; // EIST or GV3 setup option + UINT8 GpssTimer; // Global P-state Selection ti= mer setup option + + // Intel Speed Select (ISS) + UINT8 IssTdpLevel; + UINT8 DynamicIss; + + // Config TDP + UINT8 ConfigTdpLevel; + UINT8 ConfigTdpLock; + + // Individual controls for ACPI sleep states + // ** These can be overridden by AcpiSleepState because these knobs are = not available to CRB ** + // + UINT8 AcpiS3Enable; + UINT8 AcpiS4Enable; + + // + //HWPM starts + // + UINT8 ProcessorHWPMEnable; + UINT8 ProcessorHWPMInterrupt; + UINT8 ProcessorEPPEnable; + UINT8 ProcessorEppProfile; + UINT8 ProcessorAPSrocketing; + UINT8 ProcessorScalability; + UINT8 ProcessorRaplPrioritization; + UINT8 ProcessorOutofBandAlternateEPB; + // + //HWPM ends + // + UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select op= tion + UINT8 BootPState; // Boot Performance Mode + + // + // Active PBF (Prioritized Base Frequency) + // + UINT8 ProcessorActivePbf; + // + // Configure PBF High Priority Cores + // + UINT8 ProcessorConfigurePbf; + + // + // Processor Control + // + UINT8 TurboMode; + UINT8 EnableXe; + + //OverClocking + UINT8 HideOverclockingLock; + UINT8 OverclockingLock; + UINT8 AvxSupport; + + UINT8 AvxLicensePreGrant; + UINT8 AvxIccpLevel; + + UINT8 TurboRatioLimitRatio[8]; + UINT8 TurboRatioLimitCores[8]; + + UINT8 C2C3TT; + UINT8 DynamicL1; // Enabling Dynamic L1 + UINT8 ProcessorCcxEnable; // Enabling CPU C states of pr= ocessor + UINT8 PackageCState; // Package C-State Limit + UINT8 EnableLowerLatencyMode; // Enable Lower Latency Mode f= or register accesses + UINT8 C3Enable; // Enable/Disable NHM C3(ACPI = C2) report to OS + UINT8 C6Enable; // Enable/Disable NHM C6(ACPI = C3) report to OS + UINT8 ProcessorC1eEnable; // Enabling C1E state of proce= ssor + UINT8 OSCx; // ACPI C States + UINT8 C1AutoDemotion; // Enabling C1 auto demotion + UINT8 C1AutoUnDemotion; // Enabling C1 auto un-demotion + UINT8 MonitorMWait; // Enabling IO MWAIT + + UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Valid + UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Multiplier + UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENC= Y_CONTROL_x.Value + + UINT8 TStateEnable; // T states enable? + UINT8 OnDieThermalThrottling; // Throtte ratio + UINT8 ProchotLock; + UINT8 EnableProcHot; + UINT8 EnableThermalMonitor; + UINT8 ThermalMonitorStatusFilter; + UINT8 ThermalMonitorStatusFilterTimeWindow; + UINT8 ProchotResponse; + UINT8 EETurboDisable; + UINT8 SapmctlValCtl; + UINT8 PwrPerfTuning; + UINT8 AltEngPerfBIAS; + UINT8 PwrPerfSwitch; + UINT8 WorkLdConfig; + UINT16 EngAvgTimeWdw1; + + UINT8 ProchotResponseRatio; + UINT8 TCCActivationOffset; + + UINT8 P0TtlTimeLow1; + UINT8 P0TtlTimeHigh1; + + UINT8 PkgCLatNeg; + UINT8 LTRSwInput; + UINT8 SAPMControl; + UINT8 CurrentConfig; + UINT8 PriPlnCurCfgValCtl; + UINT8 Psi3Code; + UINT16 CurrentLimit; + + UINT8 Psi3Thshld; + UINT8 Psi2Code; + UINT8 Psi2Thshld; + UINT8 Psi1Code; + UINT8 Psi1Thshld; + + //Power Management Setup options + UINT8 PkgCstEntryValCtl; + UINT8 NativeAspmEnable; + + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + UINT8 PpcccLock; + + UINT8 SnpLatVld; + UINT8 SnpLatOvrd; + UINT8 SnpLatMult; + UINT16 SnpLatVal; + UINT16 NonSnpLatVld; + UINT8 NonSnpLatOvrd; + UINT8 NonSnpLatMult; + UINT16 NonSnpLatVal; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + UINT8 EepLOverride; + UINT8 EepLOverrideEn; + UINT8 ITurboOvrdEn; + UINT8 CstDemotOvrdEN; + UINT8 TrboDemotOvrdEn; + UINT8 UncrPerfPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 ImcApmOvrdEn; // unused + UINT8 IomApmOvrdEn; + UINT8 KtiApmOvrdEn; + UINT8 PerfPLmtThshld; + + // SAPMCTL_CFG (CSR 1:30:1:0xB0) + UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0] + UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1] + UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2] + UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3] + UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4] + UINT8 Kti45PkgcClkGateDis[MAX_SOCKET]; //Bit[5] + UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16] + UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17] + UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18] + UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22] + UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23] + UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6] + UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7] + UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19] + UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20] + UINT8 Kti45pllOffEna[MAX_SOCKET]; //Bit[21] + UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30]; + UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31]; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) + UINT8 PerfPLimitClip; + UINT8 PerfPLimitEn; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >=3D HSX C stepping + UINT8 PerfPlimitDifferential; + UINT8 PerfPLimitClipC; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90) + UINT8 Kti0In[MAX_SOCKET]; + UINT8 Kti1In[MAX_SOCKET]; + UINT8 Kti2In[MAX_SOCKET]; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c) + UINT8 PcieIio0In[MAX_SOCKET]; + UINT8 PcieIio1In[MAX_SOCKET]; + UINT8 PcieIio2In[MAX_SOCKET]; + UINT8 PcieIio3In[MAX_SOCKET]; + UINT8 PcieIio4In[MAX_SOCKET]; + UINT8 PcieIio5In[MAX_SOCKET]; + + // WRITE_PKGC_SA_PS_CRITERIA (B2P) + UINT8 EnablePkgcCriteria; + UINT8 PkgCCriteriaLogicalIpType[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaKti[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaRlink[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaFxr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMcddr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHbm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaIio[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHqm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaNac[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaTip[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMdfs[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHcx[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaDino[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeIio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoKti[MAX_SOCKET]; + UINT8 EnableLinkInL1Kti[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoRlink[MAX_SOCKET]; + UINT8 EnableLinkInL1Rlink[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoFxr[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMcddr[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHbm[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoIio[MAX_SOCKET]; + UINT8 EnableLinkInL1Iio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHqm[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoNac[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoTip[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMdfs[MAX_SOCKET]; + UINT8 AllowLpStateMdfs[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHcx[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoDino[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskDino[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskDino[MAX_SOCKET]; + + UINT8 FastRaplDutyCycle; + UINT8 TurboPowerLimitLock; + UINT8 TurboPowerLimitCsrLock; + UINT8 PowerLimit1En; + UINT16 PowerLimit1Power; + UINT16 PowerLimit1Time; + UINT8 PowerLimit2En; + UINT16 PowerLimit2Power; + UINT16 PowerLimit2Time; + + UINT8 PmaxDetector; + UINT8 PmaxAutoAdjustment; + UINT8 PmaxLoadLine; + UINT8 PmaxSign; + UINT8 PmaxOffset; + UINT8 PmaxOffsetNegative; + UINT8 PmaxTriggerSetup; + + //XTU 3.0 + + UINT8 MaxEfficiencyRatio[MAX_SOCKET]; + UINT8 MaxNonTurboRatio[MAX_SOCKET]; + + UINT8 VccSAandVccIOdisable; + // Software LTR Override Control + UINT8 SwLtrOvrdCtl; + UINT8 EnhancedPmaxDetector; + UINT8 PcodeWdogTimerEn; + + UINT8 RunCpuPpmInPei; + + UINT8 UncoreFreqRaplLimit; +} SOCKET_POWERMANAGEMENT_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCo= reVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessor= CoreVariable.h new file mode 100644 index 0000000000..52ab370ce7 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVaria= ble.h @@ -0,0 +1,143 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ +#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ + +#include + +extern EFI_GUID gEfiSocketProcessorCoreVarGuid; +#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfi= g" + +#pragma pack(1) + +typedef struct { + + UINT8 CpuidMaxValue; + + UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL] + UINT8 ProcessorVmxEnable; // Enabling VMX + UINT8 ProcessorSmxEnable; // Enabling SMX (TXT LT) + UINT8 ProcessorLtsxEnable; // Enabling TXT (TXT LT-SX) + UINT8 ThreeStrikeTimer; // Disable 3strike timer + UINT8 FastStringEnable; // Fast String + UINT8 MachineCheckEnable; // Machine Check + UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch + UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch + UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher + UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher + UINT8 DCUModeSelection; // DCU Mode Selection + UINT8 ProcessorX2apic; // Enable Processor XAPIC + UINT8 BspSelection; // Select BSP + UINT8 IedTraceSize; // IED trace size + UINT8 TsegSize; // TSEG size + UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio + UINT8 CheckCpuBist; // check and disable BIST fail= e core or ignore + UINT8 CoreFailover; // Enable spare core(s) in pla= ce of core(s) that fail BIST + UINT64 ReservedS192; + UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Co= re Ratio Multiplier + UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode = Processor Core Ratio Multiplier Enable + UINT8 ForcePhysicalModeEnable; // Force physical destionation= mode + UINT8 LlcPrefetchEnable; // LLC Prefetch + UINT8 CpuMtoIWa; // MtoI Workaround; + UINT8 ProcessorVirtualWireMode; + + UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control + UINT8 ProcessorMsrPkgCstConfigControlLock; // MSR PKG_CST_CONFIG_CONTR= OL lock + UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR + UINT8 AesEnable; + UINT8 PpinControl; // PPIN Control MSR + UINT8 LockChipset; // Lock Chipset + UINT8 BiosAcmErrorReset; // Disable LT-SX and reset sys= tem when BIOS ACM error occurs + UINT8 AcmType; // 0x80 =3D debug signed ACM; = 0x40 =3D NPW production signed ACM; 0x00 =3D PW production signed ACM + + // SecurityPolicy Stalagmite + #include + + UINT8 SkipStopPbet; // Skip StopPbet + + UINT64 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket + + // IOT/OCLA configs +#ifndef OCLA_TOR_ENTRY_MAX + #define OCLA_TOR_ENTRY_MIN 0 + #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Iso= ch on/off + #define OCLA_TOR_ENTRY_DEFAULT 1 + #define OCLA_WAY_MIN 0 + #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 = can be reserved for OCLA + #define OCLA_WAY_DEFAULT 1 +#endif + UINT8 IotEn[MAX_SOCKET]; + UINT8 OclaMaxTorEntry[MAX_SOCKET]; + UINT8 OclaMinWay[MAX_SOCKET]; + UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO= _LLC_WAYS bitmask. + UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:= 0] bitmask. - Only Bits[10:0] are used + UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:= 16] bitmask. - Only Bits[10:0] are used + + UINT8 PCIeDownStreamPECIWrite; + + // + // SMM Blocked and SMM Delayed + // + UINT8 SmmBlockedDelayed; + + // + // eSMM Save State Mode + // + UINT8 eSmmSaveState; + + UINT8 PeciInTrustControlBit; //On Setup + UINT8 PeciAgtLegacyTrustBit; + UINT8 PeciAgtSmbusTrustBit; + UINT8 PeciAgtIeTrustBit; + UINT8 PeciAgtGenericTrustBit; + UINT8 PeciAgtEspiTrustBit; + UINT8 Poison; + UINT8 Viral; + UINT8 EVMode; + UINT8 SmbusErrorRecovery; + UINT8 CpuL1NextPagePrefetcherDisable; + UINT8 CpuPaLimit; + UINT8 RdtCatOpportunisticTuning; + UINT8 CpuDbpEnable; // Enable/Disable DBP-F + UINT8 GlobalPsmiEnable; + UINT8 PsmiTrace[MAX_SOCKET]; + UINT8 PsmiHandlerSize[MAX_SOCKET]; + UINT8 PsmiTraceRegion0[MAX_SOCKET]; + UINT8 PsmiTraceBufferSizeRegion0[MAX_SOCKET]; + UINT8 PsmiTraceMemTypeRegion0[MAX_SOCKET]; + UINT8 PsmiTraceRegion1[MAX_SOCKET]; + UINT8 PsmiTraceBufferSizeRegion1[MAX_SOCKET]; + UINT8 PsmiTraceMemTypeRegion1[MAX_SOCKET]; + UINT8 PsmiTraceRegion2[MAX_SOCKET]; + UINT8 PsmiTraceBufferSizeRegion2[MAX_SOCKET]; + UINT8 PsmiTraceMemTypeRegion2[MAX_SOCKET]; + UINT8 PsmiTraceRegion3[MAX_SOCKET]; + UINT8 PsmiTraceBufferSizeRegion3[MAX_SOCKET]; + UINT8 PsmiTraceMemTypeRegion3[MAX_SOCKET]; + UINT8 PsmiTraceRegion4[MAX_SOCKET]; + UINT8 PsmiTraceBufferSizeRegion4[MAX_SOCKET]; + UINT8 PsmiTraceMemTypeRegion4[MAX_SOCKET]; + UINT8 L2RfoPrefetchDisable; // L2 RFO Prefetch + UINT8 AmpPrefetchEnable; + UINT8 TscResetEnable; + UINT8 AcExceptionOnSplitLockEnable; + // FuSa (SAF) Start + UINT8 SafSupport; + UINT8 EnableSaf; + // FuSa (SAF) End + UINT8 CFRS3mEnable; + UINT8 CFRS3mManualCommit; + UINT8 CFRPucodeEnable; + UINT8 CFRPucodeManualCommit; + UINT8 CpuCrashLogGprs; +} SOCKET_PROCESSORCORE_CONFIGURATION; +#pragma pack() + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h = b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h new file mode 100644 index 0000000000..49de34bcb2 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h @@ -0,0 +1,36 @@ +/** @file + Data format for Socket Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SOCKET_CONFIG_DATA_H__ +#define __SOCKET_CONFIG_DATA_H__ + +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) + +typedef struct { + SOCKET_IIO_CONFIGURATION IioConfig; + SOCKET_COMMONRC_CONFIGURATION CommonRcConfig; + SOCKET_MP_LINK_CONFIGURATION UpiConfig; + SOCKET_MEMORY_CONFIGURATION MemoryConfig; + SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration; +} SOCKET_CONFIGURATION; + + + +#pragma pack() +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTyp= eExDebug.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTyp= eExDebug.h new file mode 100644 index 0000000000..369732921e --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebu= g.h @@ -0,0 +1,50 @@ +/** @file + GUID and structure used for debug status code policy. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_ +#define _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_ + +#define STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID \ + { 0x7859daa2, 0x926e, 0x4b01,{0x85, 0x86, 0xc6, 0x2d, 0x45, 0x64, 0x21, = 0xd2} } + +#define MAX_EX_DEBUG_SIZE 0x200 // Inherited from PEI status code max +#define MAX_EX_DEBUG_STR_LEN (MAX_EX_DEBUG_SIZE - sizeof(EX_DEBUG_INFO)) + +typedef +CHAR8 * +(EFIAPI *PROCESS_BUFFER) ( + IN VOID *ProcessDataPtr, + IN CHAR8 *Buffer, + IN OUT UINTN *BufferSize + ); + +typedef +VOID * +(EFIAPI *PRINT_SYNC_ACQUIRE) ( + VOID + ); + +typedef +VOID * +(EFIAPI *PRINT_SYNC_RELEASE) ( + VOID + ); + +typedef struct { + PROCESS_BUFFER ProcessBuffer; // Buffer processing functi= on + VOID *ProcessDataPtr; // Data needed for proces= sing + PRINT_SYNC_ACQUIRE PrintSyncAcquire; // Acquire sync function + PRINT_SYNC_RELEASE PrintSyncRelease; // Release sync function + UINT32 DebugStringLen; + CHAR8 *DebugString; // Provided debug string +} EX_DEBUG_INFO; + +extern EFI_GUID gStatusCodeDataTypeExDebugGuid; + +#endif // _STATUS_CODE_DATA_TYPE_EX_DEBUG_GUID_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/= Intel/WhitleySiliconPkg/Include/IioConfig.h new file mode 100644 index 0000000000..df11dda735 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h @@ -0,0 +1,398 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIO_CONFIG_H +#define _IIO_CONFIG_H +#include + +#pragma pack(1) //to align members on byte boundary +/** +The Silicon Policy allows the platform code to publish a set of configurat= ion +information that the RC drivers will use to configure the silicon hardware. +**/ +typedef struct { + UINT8 ReservedAJ[MAX_TOTAL_PORTS]; + UINT8 ReservedAK[MAX_TOTAL_PORTS]; + UINT8 ReservedAL[MAX_TOTAL_PORTS]; + UINT8 ReservedAM[MAX_TOTAL_PORTS]; + UINT8 ReservedAN[MAX_TOTAL_PORTS]; + UINT8 ReservedAO[MAX_TOTAL_PORTS]; + UINT8 ReservedAP[MAX_TOTAL_PORTS]; + UINT8 ReservedAQ[MAX_TOTAL_PORTS]; + UINT8 ReservedAR[MAX_TOTAL_PORTS]; + UINT8 ReservedAS[MAX_TOTAL_PORTS]; + UINT8 ReservedAT[MAX_TOTAL_PORTS]; + UINT8 ReservedAU[MAX_TOTAL_PORTS]; + UINT8 ReservedAV[MAX_TOTAL_PORTS]; + UINT8 ReservedAW[MAX_TOTAL_PORTS]; + UINT8 ReservedAX[MAX_TOTAL_PORTS]; + UINT8 ReservedAY[MAX_TOTAL_PORTS]; + UINT8 ReservedE[MAX_TOTAL_PORTS]; + UINT8 ReservedF[MAX_TOTAL_PORTS]; + UINT8 ReservedG[MAX_TOTAL_PORTS]; + UINT8 ReservedAZ[MAX_TOTAL_PORTS]; + UINT8 ReservedBA[MAX_TOTAL_PORTS]; + + UINT8 PciePortClkGateEnable[MAX_TOTAL_PORTS]; + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; + UINT8 PciePortEnable[MAX_TOTAL_PORTS]; + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; + UINT8 PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup + UINT8 PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; + UINT8 PciePtm; + UINT8 PcieHotPlugEnable; + UINT8 PCIe_LTR; + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; +} IIO_PCIE_CONFIG_DATA; + +typedef struct _IIO_RETIMER_DATA { + UINT8 RetimerPresent; // eq. 0 =3D> there is no retime= r data + UINT32 GlParamReg0; // current value of Global Param= . Reg. 0 + UINT32 GlParamReg1; // current value of Global Param= . Reg. 1 + UINT32 PseudoPort0Reg2; // current value of Pseudo Port0= Reg. 2 + UINT32 PseudoPort1Reg2; // current value of Pseudo Port1= Reg. 2 + UINT32 GlParmReg0Override; // value to write to Global Para= m. Reg. 0 + UINT32 PseudoPort0Reg2Override; // value to write to Pseudo Port= 0 Reg. 2 + UINT32 PseudoPort1Reg2Override; // value to write to Pseudo Port= 1 Reg. 2 +} IIO_RETIMER_DATA; + +typedef struct { +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VTd Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VTdSupport; + UINT8 DmaCtrlOptIn; + UINT8 InterruptRemap; + UINT8 PostedInterrupt; + UINT8 ATS; + UINT8 CoherencySupport; + UINT8 VtdAcsWa; + UINT8 VtdPciAcsCtl; // Value to set in PCIe ACSCTL r= egister if reqeusted + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCIE Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Elec= tromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B= 17) + UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot= Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot = Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Powe= r Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Atte= ntion Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL = Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) + UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Powe= r Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) + UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Atte= ntion Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indi= cate if Port will PcieSSD capable. + + UINT8 PcieHotPlugOnPort[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // m= anual override of hotplug for port + + // General PCIE Configuration + UINT8 PcieSubSystemMode[MAX_SOCKET][MAX_IOU_PER_SOCKET]; //on Setup + + UINT8 CompletionTimeoutGlobal; + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; + UINT8 StopAndScream; + UINT8 SnoopResponseHoldOff; + // + // PCIE capability + // + UINT8 PcieExtendedTagField; + UINT8 Pcie10bitTag; + UINT8 PCIe_AtomicOpReq; + UINT8 PcieMaxReadRequestSize; + + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + // + // VPP Control + // + BOOLEAN VppEnabled[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 = -- Disable, 01 -- Enable //no setup option defined- aj + UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -= - Port 0, 01 -- Port 1 //no setup option defined- aj + UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-0= 7 for SMBUS address of Vpp //no setup option defined- aj + + // + // Mux and channel for segment + // + UINT8 MuxAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // SMB= US address of MUX //no setup option defined + UINT8 ChannelID[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- = channel 0, 01 -- channel 1 //no setup option defined + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE RAS (Errors) + // + UINT8 Serr; + UINT8 Perr; + UINT8 IioErrorEn; + UINT8 LerEn; + UINT8 WheaPcieErrInjEn; + + // + // PciePll + // + UINT8 PciePllSsc; //On Setup + + // + // PCIE Link Training Ctrl + // + UINT16 DelayBeforePCIeLinkTraining; //On Setup + + // + // Retimers related config + // + IIO_RETIMER_DATA Retimer[MAX_SOCKET][MAX_IIO_STACK][MAX_RETIMERS_PER_S= TACK]; + BOOLEAN SkipRetimersDetection; // Skip detection of retimers in UBA = code + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Crystal Beach 3 Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + UINT8 CbDmaMultiCastEnable; // MultiCa= stEnable test enable + + UINT8 DsaEn[NUM_DSA*MAX_SOCKET]; = // on setup + UINT8 IaxEn[NUM_IAX*MAX_SOCKET]; = // on setup + UINT8 CpmEn[NUM_CPM*MAX_SOCKET]; = // on setup + UINT8 HqmEn[NUM_HQM*MAX_SOCKET]; = // on setup + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D MISC IOH Setup Options =3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of = the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 PCUF6Hide; // Hide Device PCU Devic= e 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K gra= nularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 PcieBiosTrainEnable; // Used as a work around= for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test = enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + UINT8 MctpEn[MAX_TOTAL_PORTS]; // Enable/Disable MCTP f= or each Root Port + + UINT8 LegacyVgaSoc; + UINT8 LegacyVgaStack; + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /displa= y the PCIe port menu + + BOOLEAN PoisonMmioReadEn[MAX_SOCKET][MAX_IIO_STACK]; // on setup + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D NTB Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 NtbPpd[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeOverride[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbSplitBar[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeImBar1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeImBar2[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeImBar2_0[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeImBar2_1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeEmBarSZ1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeEmBarSZ2[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeEmBarSZ2_0[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbBarSizeEmBarSZ2_1[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + UINT8 NtbXlinkCtlOverride[MAX_SOCKET*NUMBER_NTB_PORTS_PER_SOCKET]; = //on setup option + + UINT8 NtbLinkBiosTrainEn; = // on setup option +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D VMD Related Setup Options =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 VMDEnabled[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDPortEnable[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; + UINT8 VMDHotPlugEnable[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDCfgBarSz[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDCfgBarAttr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDMemBarSz1[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDMemBar1Attr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDMemBarSz2[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDMemBar2Attr[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + UINT8 VMDPchPortEnable[MAX_SOCKET][MAX_VMD_ROOTPORTS_PER_PCH]; + UINT8 VMDDirectAssign[MAX_SOCKET][MAX_VMD_STACKS_PER_SOCKET]; + + /** + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PcieSSD Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + **/ + UINT8 PcieAICEnabled[MAX_SOCKET*MAX_STACKS_PER_SOCKET]; = // Indicate if PCIE AIC Device will be connected behind an specif= ic IOUx + UINT8 PcieAICPortEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; + UINT8 PcieAICHotPlugEnable[MAX_SOCKET*MAX_STACKS_PER_SOCKET]; + + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Gen3 Related Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + //PCIE Global Option + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + BOOLEAN PcieLowLatencyRetimersEnabled; + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 GlobalPme2AckTOCtrl; //on Setup + + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup + UINT8 PcieEnqCmdSupport; //On setup +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IOAPIC Related Setup Options =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Security Related Setup Options =3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 LockChipset; + UINT8 PeciInTrustControlBit; + UINT8 PeciAgtLegacyTrustBit; + UINT8 PeciAgtSmbusTrustBit; + UINT8 PeciAgtIeTrustBit; + UINT8 PeciAgtGenericTrustBit; + UINT8 PeciAgtEspiTrustBit; + UINT8 ProcessorX2apic; + UINT8 ProcessorMsrLockControl; + UINT8 Xppdef; + UINT8 Pci64BitResourceAllocation; + UINT8 Imr2SupportEnable; +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Reserved Setup Options =3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 ReservedQ; // On Setup + UINT8 ReservedR; + UINT8 ReservedS; // On Setup + UINT8 ReservedT; // On Setup + UINT8 ReservedU; // On Setup + UINT8 ReservedV; // On Setup + UINT8 ReservedW; // On Setup + UINT8 ReservedX; // On Setup + UINT8 ReservedY; // On Setup + UINT8 ReservedZ; // On Setup + UINT8 ReservedAA; // On Setup + UINT8 ReservedAB; // On Setup + + UINT32 ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_RE= GS_PER_STACK]; + UINT32 ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_= PER_STACK]; + + UINT8 ReservedAE[MAX_TOTAL_PORTS]; // On Setup + + UINT8 ReservedAF[MAX_TOTAL_PORTS]; + UINT8 ReservedAG[MAX_TOTAL_PORTS]; // On Setup + BOOLEAN ReservedAH; // On Setup + + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO = Global Performance Tuner Related Setup Options =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 PerformanceTuningMode; + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PCI-= E Data Link Feature Exchange Enable =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + UINT8 PcieDataLinkFeatureExchangeEnable[MAX_TOTAL_PORTS]; //On Setup + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO = Trace Hub struct for setup options =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + TRACE_HUB_CONFIG CpuTraceHubConfig[MAX_SOCKET][NUMBER_TRACE_HUB_PER_S= OCKET]; + + UINT8 SLOTIMP[MAX_TOTAL_PORTS]; + UINT8 SLOTSPLS[MAX_TOTAL_PORTS]; + UINT8 SLOTSPLV[MAX_TOTAL_PORTS]; + UINT16 SLOTPSP[MAX_TOTAL_PORTS]; + UINT8 ConfigIOU[MAX_SOCKET][MAX_IOU_PER_SOCKET]; // 00-x4x4x4x= 4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + + UINT8 EOI[MAX_TOTAL_PORTS]; + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; + UINT8 MSICOREN[MAX_TOTAL_PORTS]; + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; + UINT8 DISL0STx[MAX_TOTAL_PORTS]; + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; + UINT8 ACPIHP[MAX_TOTAL_PORTS]; + UINT8 ACPIPM[MAX_TOTAL_PORTS]; + UINT8 SRIS[MAX_TOTAL_PORTS]; + UINT8 TXEQ[MAX_TOTAL_PORTS]; + UINT8 EcrcGenEn[MAX_TOTAL_PORTS]; + UINT8 EcrcChkEn[MAX_TOTAL_PORTS]; + UINT8 SERRE[MAX_TOTAL_PORTS]; + + // + // Sierra Peak (SPK) + // + UINT8 SierraPeakMemBufferSize[MAX_SOCKET]; // on setup + IIO_PCIE_CONFIG_DATA IioPcieConfig; + + UINT32 VtdDisabledBitmask[MAX_SOCKET]; +} IIO_CONFIG; +#pragma pack() + +#endif // _IIO_CONFIG_H diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h b/Si= licon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h new file mode 100644 index 0000000000..088cc471f4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h @@ -0,0 +1,204 @@ +/** @file + This file provides required platform data structure for IOH. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIO_PLATFORM_DATA_H_ +#define _IIO_PLATFORM_DATA_H_ + +#include +#include +#include + +typedef enum { + DmiTypeVc0, + DmiTypeVc1, + DmiTypeVcm, + MaxDmiVcType +} DMI_VC_TYPE; + +typedef enum { + DmiTypeTc0, + DmiTypeTc1, + DmiTypeTc2, + DmiTypeTc3, + DmiTypeTc4, + DmiTypeTc5, + DmiTypeTc6, + DmiTypeTc7, + MaxDmiTcType +}DMI_TC_TYPE; + +#pragma pack(1) + +typedef union { + struct { + UINT32 Value; + UINT32 ValueHigh; + } Address32bit; + UINT64 Address64bit; +} IIO_PTR_ADDRESS; + +/* + * Following are the data structure defined to support multiple CBDMA type= s on a system + */ + +typedef struct { + UINT32 NoSnoopSupported : 1; + UINT32 RelaxOrderSupported : 1; +} CB_CONFIG_CAPABILITY; + +typedef struct { + UINT8 CB_VER; + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT8 MaxNoChannels; + CB_CONFIG_CAPABILITY CBConfigCap; +} CBDMA_CONTROLLER; + +typedef struct { + CBDMA_CONTROLLER CbDmaDevice; +} DMA_HOST; + +// <<<< end of CBDMA data structures >>>> + +typedef struct { + UINT8 LinkWidth; + UINT8 LinkSpeed; +} IIO_DMI_DATA; + +typedef struct { + UINT8 SystemRasType; + BOOLEAN IsocEnable; + UINT8 EVMode; + UINT32 meRequestedSize; + UINT32 ieRequestedSize; + UINT8 DmiVc[MaxDmiVcType]; + UINT8 DmiVcId[MaxDmiVcType]; + UINT8 DmiTc[MaxDmiTcType]; + UINT8 PlatformType; + UINT8 IOxAPICCallbackBootEvent; + UINT8 RasOperation; + UINT8 SocketUnderOnline; + UINT8 CompletedReadyToBootEventServices; + UINT8 SocketPresent[MaxIIO]; + UINT8 SocketBaseBusNumber[MaxIIO]; + UINT8 SocketLimitBusNumber[MaxIIO]; + UINT32 StackPresentBitmap[MaxIIO]; + UINT64_STRUCT SegMmcfgBase[MaxIIO]; + UINT8 SegmentSocket[MaxIIO]; + UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT32 SocketStackMmiolBase[MaxIIO][MAX_IIO_STACK]; + UINT32 SocketStackMmiolLimit[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 SocketUncoreBusNumber[MaxIIO][MAX_UNCORE_STACK]; // 10nm o= nly + UINT32 PchIoApicBase; + UINT32 PciResourceMem32Base[MaxIIO]; + UINT32 PciResourceMem32Limit[MaxIIO]; + UINT8 Pci64BitResourceAllocation; + UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK]; + UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK]; + UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK]; + UINT32 RcBaseAddress; + UINT64 PciExpressBase; + UINT32 PmBase[MaxIIO]; + UINT32 PchSegRegBaseAddress[MaxIIO]; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT8 Emulation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 StackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 StackId[MaxIIO][MAX_IIO_STACK]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT8 IODC; + UINT8 MultiPch; + UINT8 FpgaActive[MaxIIO]; + UINT32 TraceHubMemBase; + UINT8 DmiSocketMap; + IIO_DMI_DATA DmiSocketData[MAX_SOCKET]; + UINT64 PciTrainingStartTime; // time in microseconds +} IIO_V_DATA; + +typedef struct { + UINT8 Device; + UINT8 Function; +} IIO_PORT_INFO; + +typedef struct { + UINT8 Valid; + UINT8 IioUplinkPortIndex; //defines platform spe= cific uplink port index (if any else FF) + IIO_PORT_INFO UplinkPortInfo; +} IIO_UPLINK_PORT_INFO; + +typedef struct _INTEL_IIO_PORT_INFO { + UINT8 Device; + UINT8 Function; + UINT8 Reserved137; + UINT8 Reserved138; + UINT8 Reserved139; + UINT8 Reserved140; + UINT8 Reserved141; + UINT8 SuperClusterPort; + UINT8 NtbDevice; + UINT8 NtbFunction; +} INTEL_IIO_PORT_INFO; + +typedef struct _INTEL_DMI_PCIE_INFO { + INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} INTEL_DMI_PCIE_INFO; + +typedef struct _INTEL_IIO_PRELINK_DATA { + INTEL_DMI_PCIE_INFO PcieInfo; + IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO]; +} INTEL_IIO_PRELINK_DATA; + +typedef struct { + UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 MaxPXPMap[MaxIIO * NUMBER_PORTS_PER_SOCKET]; // Max= link width + BOOLEAN LaneReversedPXPMap[MaxIIO][MAX_IOU_PER_SOCKET]; + UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 RetimerConnectCount[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + IIO_PTR_ADDRESS PtrAddress; + IIO_PTR_ADDRESS PtrPcieTopology; + UINT64 McastRsvdMemory; + DMA_HOST DMAhost[MaxIIO]; + UINT8 resetRequired; + UINT8 MaxPciePortNumberPerSocket[MaxIIO]; + + // + // IsSocketSmbEnabled and TimeoutOnVppOccured are needed only as a WA fo= r SMB issue in socket + // + BOOLEAN IsSocketSmbEnabled[MaxIIO]; // contains TRUE if socket sm= b controller was enabled for given IIO (socket) + BOOLEAN TimeoutOnVppOccurred[MaxIIO]; // contains TRUE if there wa= s a timeout after VPP programming +} IIO_OUT_DATA; + +typedef struct { + IIO_V_DATA IioVData; + INTEL_IIO_PRELINK_DATA PreLinkData; + IIO_OUT_DATA IioOutData; +} IIO_VAR; + +typedef struct { + IIO_CONFIG SetupData; + IIO_VAR IioVar; +} IIO_GLOBALS; + +#pragma pack() + +#endif //_IIO_PLATFORM_DATA_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/In= tel/WhitleySiliconPkg/Include/IioRegs.h new file mode 100644 index 0000000000..98f759be81 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h @@ -0,0 +1,179 @@ +/** @file + + @copyright + Copyright 2010 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIO_REGS_H_ +#define _IIO_REGS_H_ + +#include + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D General Definitions =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ +//------------------------------------------------------------------------= ----------- +// PCIE port index for SKX +//------------------------------------------------------------------------= ------------ +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +//------------------------------------------------------------------------= ----------- +// Number's ports per stack definitions for 10nm +//------------------------------------------------------------------------= ------------ + +// STACK0 for: ICX-SP +#define NUMBER_PORTS_PER_STACK0_10NM 1 + +// NON-STACK0 for: ICX-SP +#define NUMBER_PORTS_PER_NON_STACK0_10NM 4 + +#define MAX_UNCORE_STACK 2 // MAX_LOGIC_IIO_STACK - MAX= _IIO_STACK + +#define MaxIIO MAX_SOCKET + +#define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKE= T. Note: this covers up to 8S. +#define MAX_TOTAL_PORTS (MAX_SOCKET * NUMBER_PORTS_PER_SOCKE= T) //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 =3D S4_= S7 as optimal + + #define NUM_IAX 1 //number of IAX per Socket + #define NUM_DSA 1 //number of DSA per Socket + #define NUM_CPM 1 //number of CPM per Socket + #define NUM_HQM 1 //number of HQM per Socket + +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. = Not reflect architecture but only sysHost structure! + +#define NUMBER_NTB_PORTS_PER_SOCKET 5 + +#ifndef MAX_STACKS_PER_SOCKET + #define MAX_STACKS_PER_SOCKET 6 + #define MAX_IIO_PORTS_PER_STACK NUMBER_PORTS_PER_NON_STACK0_10NM +#endif + +#define MAX_IOU_PER_SOCKET 5 // Max IOU number per socket f= or all silicon generation, SKX, ICX + +#define MAX_VMD_ROOTPORTS_PER_PCH 20 // Max number of rootports in = PCH +#define MAX_VMD_STACKS_PER_SOCKET 6 // Max number of stacks per so= cket supported by VMD + +#define MAX_RETIMERS_PER_STACK 2 // Max number of retime= rs per pcie controller (ICX-SP) + +#ifndef NELEMENTS +#define NELEMENTS(Array) (sizeof(Array)/sizeof((Array)[0])) +#endif + + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO Root Port Definitions =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ +// Max BDFs definitions +#define MAX_FUNC_NUM 8 +#define MAX_DEV_NUM 32 +#define MAX_BUS_NUM 256 + +#define PORT_0_INDEX 0 +#define PORT_A_INDEX 1 +#define PORT_B_INDEX 2 +#define PORT_C_INDEX 3 +#define PORT_D_INDEX 4 +#define PORT_E_INDEX 5 +#define PORT_F_INDEX 6 +#define PORT_G_INDEX 7 +#define PORT_H_INDEX 8 + +//------------------------------------------------------------------------= ----------- +// Port Index definition for SKX +//------------------------------------------------------------------------= ------------ +#define PCIE_PORT_2_DEV 0x02 +// IOU0 +#define PORT_1A_INDEX 1 +#define PORT_1B_INDEX 2 +#define PORT_1C_INDEX 3 +#define PORT_1D_INDEX 4 +// IOU1 +#define PORT_2A_INDEX 5 +#define PORT_2B_INDEX 6 +#define PORT_2C_INDEX 7 +#define PORT_2D_INDEX 8 +// IOU2 +#define PORT_3A_INDEX 9 +#define PORT_3B_INDEX 10 +#define PORT_3C_INDEX 11 +#define PORT_3D_INDEX 12 +//MCP0 +#define PORT_4A_INDEX 13 +#define PORT_4B_INDEX 14 +#define PORT_4C_INDEX 15 +#define PORT_4D_INDEX 16 +//MCP1 +#define PORT_5A_INDEX 17 +#define PORT_5B_INDEX 18 +#define PORT_5C_INDEX 19 +#define PORT_5D_INDEX 20 + +//------------------------------------------------------------------------= ----------- +// Port Index definition for ICX-SP +//------------------------------------------------------------------------= ------------ + +// IOU0 +#define PORT_1A_INDEX_1 1 +#define PORT_1B_INDEX_1 2 +#define PORT_1C_INDEX_1 3 +#define PORT_1D_INDEX_1 4 +// IOU1 +#define PORT_2A_INDEX_2 5 +#define PORT_2B_INDEX_2 6 +#define PORT_2C_INDEX_2 7 +#define PORT_2D_INDEX_2 8 +// IOU2 +#define PORT_3A_INDEX_3 9 +#define PORT_3B_INDEX_3 10 +#define PORT_3C_INDEX_3 11 +#define PORT_3D_INDEX_3 12 +// IOU3 +#define PORT_4A_INDEX_4 13 +#define PORT_4B_INDEX_4 14 +#define PORT_4C_INDEX_4 15 +#define PORT_4D_INDEX_4 16 +// IOU4 +#define PORT_5A_INDEX_5 17 +#define PORT_5B_INDEX_5 18 +#define PORT_5C_INDEX_5 19 +#define PORT_5D_INDEX_5 20 + +// +// Port Config Mode +// +#define REGULAR_PCIE_OWNERSHIP 0 +#define VMD_OWNERSHIP 3 +#define PCIEAIC_OCL_OWNERSHIP 4 + +#define NUMBER_TRACE_HUB_PER_SOCKET 1 + +// +// 8 stacks per each socket: +// - 6 IIO stacks (used only on 14nm systems - 10nm doesn't hide per-IP) +// - 2 uncore stacks (used only for 10nm systems - 14nm doesn't have suc= h stacks) +// +#define NUM_DEVHIDE_REGS_PER_STACK 8 // devHide 32-bit r= egister for each function on stack +#define NUM_DEVHIDE_UNCORE_STACKS 2 // number of uncore= stacks in setup structure +#define NUM_DEVHIDE_IIO_STACKS 6 // number of IIO st= acks ins etup structure + +#if MaxIIO > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 512 // MAX_DEVHIDE_RE= GS_PER_SOCKET * MaxIIO +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 256 // MAX_DEVHIDE_RE= GS_PER_SOCKET * MaxIIO +#endif + +#endif //_IIO_REGS_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h = b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h new file mode 100644 index 0000000000..55496e60d4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h @@ -0,0 +1,60 @@ +/** @file + Definitions shared with HFR/VFR files. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOSETUPDEFINITIONS_H_ +#define _IIOSETUPDEFINITIONS_H_ + +//------------------------------------------------------------------------= ----------- +// Number of ports per socket for CPUs +//------------------------------------------------------------------------= ------------ +#define NUMBER_PORTS_PER_SOCKET_ICX 21 +#define NUMBER_PORTS_PER_SOCKET_SKX 21 +#define NUMBER_PORTS_PER_SOCKET_CPX 13 + +//------------------------------------------------------------------------= ----------- +// General NUMBER_PORTS_PER_SOCKET definition +//------------------------------------------------------------------------= ------------ +#define NUMBER_PORTS_PER_SOCKET NUMBER_PORTS_PER_SOCKET_SKX + +/** +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Equates common for Set= up options (.vfr/.hfr) and source files (.c/.h) =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +**/ + +#define IIO_BIFURCATE_xxxxxxxx 0xFE +#define IIO_BIFURCATE_x4x4x4x4 0x0 +#define IIO_BIFURCATE_x4x4xxx8 0x1 +#define IIO_BIFURCATE_xxx8x4x4 0x2 +#define IIO_BIFURCATE_xxx8xxx8 0x3 +#define IIO_BIFURCATE_xxxxxx16 0x4 +#define IIO_BIFURCATE_x2x2x4x8 0x5 +#define IIO_BIFURCATE_x4x2x2x8 0x6 +#define IIO_BIFURCATE_x8x2x2x4 0x7 +#define IIO_BIFURCATE_x8x4x2x2 0x8 +#define IIO_BIFURCATE_x2x2x4x4x4 0x9 +#define IIO_BIFURCATE_x4x2x2x4x4 0xA +#define IIO_BIFURCATE_x4x4x2x2x4 0xB +#define IIO_BIFURCATE_x4x4x4x2x2 0xC +#define IIO_BIFURCATE_x2x2x2x2x8 0xD +#define IIO_BIFURCATE_x8x2x2x2x2 0xE +#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF +#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10 +#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11 +#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12 +#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13 +#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14 +#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15 +#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16 +#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17 +#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18 +#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 +#define IIO_BIFURCATE_AUTO 0xFF + +#endif /* _IIOSETUPDEFINITIONS_H_ */ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h new file mode 100644 index 0000000000..32fc4a2978 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h @@ -0,0 +1,166 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIO_UNIVERSAL_DATA_ +#define _IIO_UNIVERSAL_DATA_ + +#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53= , 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } } +#include "SysHost.h" +#include "IioPlatformData.h" +#include "UncoreCommonIncludes.h" +#include + +//------------------------------------------------------------------------= --------------// +// Structure definitions for Universal Data Store (UDS) +//------------------------------------------------------------------------= --------------// +#define UINT64 unsigned long long + +#pragma pack(1) + + +typedef struct { + UINT8 Valid; // TRUE, if the link is valid (= i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - II= O) + UINT8 PeerPort; // Port of the peer socket +}QPI_PEER_DATA; + +typedef struct { + UINT8 Valid; + UINT32 MmioBar[TYPE_MAX_MMIO_BAR]; + UINT8 PcieSegment; + UINT64_STRUCT SegMmcfgBase; + UINT16 stackPresentBitmap; + UINT16 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList[MAX_CHA_MAP]; + UINT32 SocId; + QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 Mmio32Base; // Base of low MMIO confi= gured for this stack in memory map + UINT32 Mmio32Limit; // Limit of low MMIO conf= igured for this stack in memory map + UINT64 Mmio64Base; // Base of high MMIO conf= igured for this stack in memory map + UINT64 Mmio64Limit; // Limit of high MMIO con= figured for this stack in memory map + UINT32 PciResourceMem32Base; // Base of low MMIO resou= rce available for PCI devices + UINT32 PciResourceMem32Limit; // Limit of low MMIO reso= urce available for PCI devices + UINT64 PciResourceMem64Base; // Base of high MMIO reso= urce available for PCI devices + UINT64 PciResourceMem64Limit; // Limit of high MMIO res= ource available for PCI devices + UINT32 VtdBarAddress; + UINT32 Mmio32MinSize; // Minimum required size = of MMIO32 resource needed for this stack +} STACK_RES; + +typedef struct { + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (= 0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 Mmio32Base; // Base of low MMIO confi= gured for this socket in memory map + UINT32 Mmio32Limit; // Limit of low MMIO conf= igured for this socket in memory map + UINT64 Mmio64Base; // Base of high MMIO conf= igured for this socket in memory map + UINT64 Mmio64Limit; // Limit of high MMIO con= figured for this socket in memory map + STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; + UINT32 RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmio32Base; // Global Mmiol base + UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit + UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [= 43:0] + UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit = [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info pe= r CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info pe= r IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[MAX_SOCKET]; // This data arr= ay is valid only for SBSP, not for non-SBSP CPUs. for CpuSv + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; //5370389 + UINT32 UboxMmioSize; + UINT32 MaxAddressBits; +} PLATFORM_DATA; + +typedef struct { + UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI= Link speed (Slow/Full speed mode) + UINT8 CurrentUpiLinkFrequency; // Current requested = UPI Link frequency (in GT) + UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disab= led, 1 - Enabled for PM X2APIC + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kt= i link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range r= equested by ME FW, in MB + UINT32 ieRequestedSize; // Size of the memory range r= equested by IE FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; = // 1,..4. Total number of CPU packages installed and detected (1..4)by QP= I RC + UINT16 tolmLimit; + UINT32 tohmLimit; + RC_VERSION RcVersion; + BOOLEAN MsrTraceEnable; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD s= upport + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT16 LlcSizeReg; + UINT8 chEnabled[MAX_SOCKET][MAX_CH]; + UINT8 memNode[MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 ReservedBC; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + UINT32 OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h b/Silicon= /Intel/WhitleySiliconPkg/Include/ImonVrSvid.h new file mode 100644 index 0000000000..75b73113ac --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h @@ -0,0 +1,26 @@ +/** @file + + ImonVrSvid.h + + API Header for IMON VR PCD Structure + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IMON_VR_SVID_H_ +#define _IMON_VR_SVID_H_ + +//Maximum IMON COUNT +#define MAX_IMON_COUNT 16 + +//End of List +#define IMON_ADDR_LIST_END 0xFF + +typedef struct { + UINT8 VrSvid[MAX_IMON_COUNT]; +} VCC_IMON; + +#endif //_IMON_VR_SVID_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h = b/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h new file mode 100644 index 0000000000..bea4f72ce9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h @@ -0,0 +1,22 @@ +/** @file + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _kti_setup_definitions_h +#define _kti_setup_definitions_h + +// +// Link speed +// +// +// ICX KTI Speed options +// +#define SPEED_REC_96GT 0 +#define SPEED_REC_104GT 1 +#define SPEED_REC_112GT 2 + +#endif // _kti_setup_definitions_h diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVari= ableLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVaria= bleLib.h new file mode 100644 index 0000000000..0a212840e4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib= .h @@ -0,0 +1,35 @@ +/** @file + Interface header file for the Compressed Variable library class. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _COMPRESSED_VARIABLE_LIB_H_ +#define _COMPRESSED_VARIABLE_LIB_H_ + +#include + +/** + Retrieve data from a HOB(s), then compress and save the data. + + @param[in] HobGuid GUID of the HOB to save. + @param[in] VariableName Name of the variable to save as. + @param[in] VariableGuid GUID of the variable to save as. + + @retval EFI_SUCCESS The variable was saved successfully. + @retval !EFI_SUCCESS Failure. + +**/ + +EFI_STATUS +EFIAPI +SaveVariableFromHob ( + IN EFI_GUID HobGuid, + IN CHAR16 *VariableName, + IN EFI_GUID VariableGuid + ); + +#endif // #ifndef _COMPRESSED_VARIABLE_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfi= gurationLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationCo= nfigurationLib.h new file mode 100644 index 0000000000..be12385348 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfiguratio= nLib.h @@ -0,0 +1,34 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EMULATION_CONFIGURATION_LIB_H_ +#define _EMULATION_CONFIGURATION_LIB_H_ + +#include + +#pragma pack(1) + +typedef struct { + UINT8 UbiosGenerationSetting; // indicate if uB= IOS generation is enable or not in setup menu + UINT8 HybridSystemLevelEmulationSetting; // indicate if HS= LE is enable or not in setup menu + UINT8 UbiosOutputMode; // indicate if we= should output register writes to the serial port + UINT32 LoopBackLabelNumber; // used to create= ASM reads for emulation + UINT8 FnvAccessValue; // indicate if FN= V access enable or not + UINT8 MsrTraceEnable; // indicate if Mr= s Trace is enable or not in setup menu + UINT8 MsrTraceOutputMode; // indicate if Mr= s Trace Asm Output Mode +} EMULATION_SETTING; + +#pragma pack() + +#define ASM_OUTPUT_ENABLE BIT0 // flag to indica= te ASM output is enabled + +#define FNV_ACCESS_DISABLE 0 // flag to indica= te FNV access is disabled + +#define MSR_OUTPUT_DISABLE 0 // flag to indica= te Mrs Trace Asm Output is disabled + +#endif // _EMULATION_CONFIGURATION_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h b= /Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h new file mode 100644 index 0000000000..d5cf1c01d0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h @@ -0,0 +1,32 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMTYPELIB_H_ +#define _MEMTYPELIB_H_ + +typedef enum { + MemTypeNone =3D 0, + MemType1lmDdr, + MemType1lmAppDirect, + MemType1lmAppDirectReserved, + MemType1lmCtrl, + MemType1lmHbm, + MemTypeNxm, + MemType2lmDdrCacheMemoryMode, + MemType2lmDdrWbCacheAppDirect, + MemType2lmHbmCacheDdr, + MemType2lmHbmCacheMemoryMode, + MemTypeCxlAccVolatileMem, + MemTypeCxlAccPersistentMem, + MemTypeFpga, + MemTypeCxlExpVolatileMem, + MemTypeCxlExpPersistentMem, + MemTypeMax +} MEM_TYPE; + +#endif // _MEMTYPELIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLi= b.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h new file mode 100644 index 0000000000..8eae5c64df --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h @@ -0,0 +1,66 @@ +/** @file + + MemVrSvidMapLib.h + + API Header for VrSvid Mapping + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_VR_SVID_MAP_LIB_H_ +#define _MEM_VR_SVID_MAP_LIB_H_ + +#define MAX_SVID_MC 16 +#define MAX_SVID_SOCKET 16 + +typedef struct { + UINT8 Mc[MAX_SVID_MC]; // Store SVID for Socket\MC Pair +} SVID_SOCKET; + +typedef struct { + SVID_SOCKET Socket[MAX_SVID_SOCKET]; +} MEM_SVID_MAP; + + +/** + Get SVID Mapping from Socket and MCID + + @param[in] Socket - Socket Id - 0 based + @param[in] McId - Memory controller 0 based + @param[in] SvidValue - SVID Value + + @retval EFI_SUCCESS - Value found + @retval EFI_NOT_FOUND - Value not found + +**/ +EFI_STATUS +EFIAPI +GetSvidMap ( + IN UINT8 Socket, + IN UINT8 McId, + IN UINT8 *SvidValue + ); + +/** + Set SVID Mapping for given Socket and MCID + + @param[in] Socket - Socket Id - 0 based + @param[in] McId - Memory controller 0 based + @param[in] SvidValue - SVID Value + + @retval EFI_SUCCESS - Value set successfully + @retval EFI_NOT_FOUND - Value not set + +**/ +EFI_STATUS +EFIAPI +SetSvidMap ( + IN UINT8 Socket, + IN UINT8 McId, + IN UINT8 SvidValue + ); + +#endif //_MEM_VR_SVID_MAP_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h b= /Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..adda16bdc2 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h @@ -0,0 +1,22 @@ +/** @file + Header file for PchInfoLib. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include + +typedef enum { + PchH =3D 1, + PchLp, + PchMini, + PchUnknownSeries +} PCH_SERIES; + +#endif // _PCH_INFO_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksL= ib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h new file mode 100644 index 0000000000..1f31ffed74 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h @@ -0,0 +1,17 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +UINT32 +IsSioExist ( + VOID + ); + +VOID +InitializeSio ( + VOID + ); diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h= b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h new file mode 100644 index 0000000000..0287e98b4d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h @@ -0,0 +1,326 @@ +/** @file + The Semaphore Library API provides the necessary functions to acquire/re= lease + the global or a socket's semaphore. + + This API is designed to allow a calling agent to acquire a global (the S= BSP) + semaphore or a socket's semaphore. It also provides functionality to re= lease + the semaphore and check if ownership has been obtained. If a semaphore = is + desired, an agent should first attempt to acquire it, then check if it h= as + ownership. If ownership has not been obtained, the agent must wait until + ownership has been obtained before proceeding. Once the desired task is= complete + the semaphore must be released. Semaphores should be used for when ensu= ring + exclusive access to resoruces among CPU sockets is necessary. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SEMAPHORE_LIB_H_ +#define _SEMAPHORE_LIB_H_ + +#include + +/// +/// Used to identify which System Sempahore is being accessed. There are +/// currently two System Semaphores available for use (0 and 1). +/// +typedef enum { + SystemSemaphore0, ///< Semaphore 0 - Used for SPD/SMBus access + SystemSemaphore1, ///< Semaphore 1 - Used for Debug print + SystemSemaphoreMax +} SYSTEM_SEMAPHORE_NUMBER; + +/// +/// Used to identify which Local Sempahore is being accessed. There are +/// currently two Local Semaphores available for use (0 and 1). +/// +typedef enum { + LocalSemaphore0, + LocalSemaphore1, + LocalSemaphoreMax +} LOCAL_SEMAPHORE_NUMBER; + +#define DO_NOT_ADD_TO_QUEUE FALSE +#define ADD_TO_QUEUE TRUE + +/** + Acquire a global (BSP) semaphore for the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &Q= Num); + while (!Owned) { + Owned =3D IsGlobalSemaphoreOwned (SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseGlobalSemaphore (SystemSemaphore0); + ...... + + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + @param[in] AddToQueue - specifices whether to add the requesting + socket to the queue (TRUE or FALSE) + @param[out] QueueNumber - assigned place in line of semaphore requ= est, + if adding to queue + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +AcquireGlobalSemaphore ( + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber, + IN BOOLEAN AddToQueue, + OUT UINT32 *QueueNumber OPTIONAL + ); + +/** + Checks if a global (BSP) semaphore is owned by the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &Q= Num); + while (!Owned) { + Owned =3D IsGlobalSemaphoreOwned (SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseGlobalSemaphore (SystemSemaphore0); + ...... + + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + @param[in] QueueNumber - assigned place in line of semaphore requ= est + that was returned by AcquireGlobalSemaph= ore + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +IsGlobalSemaphoreOwned ( + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber, + IN UINT32 QueueNumber + ); + +/** + Release a global (BSP) semaphore owned by the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireGlobalSemaphore (SystemSemaphore0, ADD_TO_QUEUE, &Q= Num); + while (!Owned) { + Owned =3D IsGlobalSemaphoreOwned (SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseGlobalSemaphore (SystemSemaphore0); + ...... + + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + + @retval EFI_SUCCESS - successfully released semaphore + @retval EFI_DEVICE_ERROR - error releasing semaphore +**/ +EFI_STATUS +EFIAPI +ReleaseGlobalSemaphore ( + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber + ); + + +/** + Acquire a socket semaphore for the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_Q= UEUE, &QNum); + while (!Owned) { + Owned =3D IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseSocketSemaphore (Socket, SystemSemaphore0); + ...... + + @param[in] Socket - Socket where the semaphore is located + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + @param[in] AddToQueue - specifices whether to add the requesting + socket to the queue (TRUE or FALSE) + @param[out] QueueNumber - assigned place in line of semaphore requ= est, + if adding to queue + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +AcquireSocketSemaphore ( + IN UINT8 Socket, + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber, + IN BOOLEAN AddToQueue, + OUT UINT32 *QueueNumber OPTIONAL + ); + +/** + Checks if a socket semaphore is owned by the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_Q= UEUE, &QNum); + while (!Owned) { + Owned =3D IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseSocketSemaphore (Socket, SystemSemaphore0); + ...... + + @param[in] Socket - Socket where the semaphore is located + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + @param[in] QueueNumber - assigned place in line of semaphore requ= est + that was returned by AcquireSocketSemaph= ore + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +IsSocketSemaphoreOwned ( + IN UINT8 Socket, + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber, + IN UINT32 QueueNumber + ); + +/** + Release a socket semaphore owned by the calling socket. + + Used for ensuring exclusive access to resources among CPU sockets. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireSocketSemaphore (Socket, SystemSemaphore0, ADD_TO_Q= UEUE, &QNum); + while (!Owned) { + Owned =3D IsSocketSemaphoreOwned (Socket, SystemSemaphore0, QNum)); + } + DoSomething (); + ReleaseSocketSemaphore (Socket, SystemSemaphore0); + ...... + + @param[in] Socket - Socket to release semaphore + @param[in] SemaphoreNumber - SYSTEMSEMAPHORE register number (0 or 1) + + @retval EFI_SUCCESS - successfully released semaphore + @retval EFI_DEVICE_ERROR - error releasing semaphore +**/ +EFI_STATUS +EFIAPI +ReleaseSocketSemaphore ( + IN UINT8 Socket, + IN SYSTEM_SEMAPHORE_NUMBER SemaphoreNumber + ); + +/** + Acquire a local semaphore for the calling thread. + + Used for ensuring exclusive access to resources among CPU threads. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNu= m); + while (!Owned) { + Owned =3D IsLocalSemaphoreOwned (LocalSemaphore0, QNum)); + } + DoSomething (); + ReleaseLocalSemaphore (LocalSemaphore0); + ...... + + @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1) + @param[in] AddToQueue - specifices whether to add the requesting + thread to the queue (TRUE or FALSE) + @param[out] QueueNumber - assigned place in line of semaphore requ= est, + if adding to queue + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +AcquireLocalSemaphore ( + IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber, + IN BOOLEAN AddToQueue, + OUT UINT32 *QueueNumber OPTIONAL + ); + +/** + Checks if a local semaphore is owned by the calling thread. + + Used for ensuring exclusive access to resources among CPU threads. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNu= m); + while (!Owned) { + Owned =3D IsLocalSemaphoreOwned (LocalSemaphore0, QNum)); + } + DoSomething (); + ReleaseLocalSemaphore (LocalSemaphore0); + ...... + + @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1) + @param[in] QueueNumber - assigned place in line of semaphore requ= est + that was returned by AcquireLocalSemapho= re + + @retval TRUE - successfully acquired semaphore + @retval FALSE - semaphore not acquired +**/ +BOOLEAN +EFIAPI +IsLocalSemaphoreOwned ( + IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber, + IN UINT32 QueueNumber + ); + +/** + Release a local semaphore owned by the calling thread. + + Used for ensuring exclusive access to resources among CPU threads. + + IMPORTANT: + The functions must be called in the sequence below: + ...... + Owned =3D AcquireLocalSemaphore (LocalSemaphore0, ADD_TO_QUEUE, &QNu= m); + while (!Owned) { + Owned =3D IsLocalSemaphoreOwned (LocalSemaphore0, QNum)); + } + DoSomething (); + ReleaseLocalSemaphore (LocalSemaphore0); + ...... + + @param[in] SemaphoreNumber - LOCALSEMAPHORE register number (0 or 1) + + @retval EFI_SUCCESS - successfully released semaphore + @retval EFI_INVALID_PARAMETER - semaphore number is out of range + @retval EFI_DEVICE_ERROR - error releasing semaphore +**/ +EFI_STATUS +EFIAPI +ReleaseLocalSemaphore ( + IN LOCAL_SEMAPHORE_NUMBER SemaphoreNumber + ); + +#endif // _SEMAPHORE_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h b/Silicon/In= tel/WhitleySiliconPkg/Include/MaxCore.h new file mode 100644 index 0000000000..6cde7ac633 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h @@ -0,0 +1,20 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// This defines the maximum number of cores supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_CORE +#define MAX_CORE (FixedPcdGet32 (PcdMaxCpuCoreCount)) +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h b/Silicon/= Intel/WhitleySiliconPkg/Include/MaxSocket.h new file mode 100644 index 0000000000..06f2e54db3 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h @@ -0,0 +1,20 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// This defines the maximum number of sockets supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h b/Silicon/= Intel/WhitleySiliconPkg/Include/MaxThread.h new file mode 100644 index 0000000000..3240fc7166 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h @@ -0,0 +1,20 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// This defines the maximum number of threads supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_THREAD +#define MAX_THREAD (FixedPcdGet32 (PcdMaxCpuThreadCount)) +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h b/Silicon/= Intel/WhitleySiliconPkg/Include/MemCommon.h new file mode 100644 index 0000000000..6958b1431b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h @@ -0,0 +1,41 @@ +/** @file + Mem common Hearder File + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __MEM_COMMON_H__ +#define __MEM_COMMON_H__ + +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channel= s per socket + +typedef enum { + ReservedMemSs, + Ddr4MemSs =3D 1, + Ddr5MemSs =3D 2, + LpDdr4MemSs =3D 3, + LpDdr5MemSs =3D 4, + Hbm2MemSs =3D 5, + MrcMstMax, + MrcMstDelim =3D MAX_INT32 +} MRC_MST; + +typedef enum { + TYPE_SCF_BAR =3D 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + +#endif //#ifndef __MEM_COMMON_H__ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegister= s.h b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h new file mode 100644 index 0000000000..0b002311fb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h @@ -0,0 +1,38 @@ +/** @file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DDR4_SPD_REGS_H_ +#define _DDR4_SPD_REGS_H_ + +// +// DDR4 SPD Spec 4.0 Register Definitions +// + +/* Byte 132 (0x084) (Registered): RDIMM Thermal Heat Spreader Solution */ + +#define SPD_RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_REG 0x0084 + +typedef union { + struct { + UINT8 heat_spreader_thermal_characteristics : 7; + /* Bits[0:6] + Heat Spreader Thermal Characteristics + 0 =3D Undefined + All other settings to be defined + */ + UINT8 heat_spreader_solution : 1; + /* Bits[7] + Heat Spreader Solution + 0 =3D Heat spreader solution is not incorpo= rated onto this assembly + 1 =3D Heat spreader solution is incorporate= d onto this assembly + */ + } Bits; + UINT8 Data; +} RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_STRUCT; + +#endif // #ifndef _DDR4_SPD_REGS_H_ \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipComm= on.h b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h new file mode 100644 index 0000000000..ae47ef2034 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h @@ -0,0 +1,28 @@ +/** @file + ProcSmbChipCommon.h + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PROC_SMB_CHIP_COMMON_H_ +#define _PROC_SMB_CHIP_COMMON_H_ + +#include + +// +// Available SMBus clock periods to be programmed. +// +typedef enum { + SmbClk100K =3D SMB_CLK_100K, // 100 Khz in I2C mode; 4Mhz in I3C mode + SmbClk400K =3D SMB_CLK_400K, // 400 Khz in I2C mode; 6Mhz in I3C mode + SmbClk700K =3D SMB_CLK_700K, // 700 Khz in I2C mode; 8Mhz in I3C mode + SmbClk1M =3D SMB_CLK_1M, // 1 Mhz in I2C mode; 10Mhz in I3C mode + SmbClkPeriodMax +} SMB_CLOCK_FREQUENCY; + +#define MAX_SMB_INSTANCE 2 // Maximum number of SMBUS Instances + +#endif // _PROC_SMB_CHIP_COMMON_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h b/Silicon/I= ntel/WhitleySiliconPkg/Include/Platform.h new file mode 100644 index 0000000000..b8ed188f16 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Platform.h @@ -0,0 +1,266 @@ +/** @file + Platform specific information + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +// +// Assigning default ID and base addresses here, these definitions are use= d by ACPI tables +// + +#define PCH_IOAPIC (UINT64)BIT0 +#define PCH_IOAPIC_ID 0x08 +#define PCH_IOAPIC_ADDRESS 0xFEC00000 // This must get range = from Legacy IIO +#define PCH_INTERRUPT_BASE 0 + +#define PC00_IOAPIC (UINT64)BIT1 //Because PCH_IOAPIC= gets the first bit, these bit values will be 1+PC number. +#define PC00_IOAPIC_ID 0x09 +#define PC00_INTERRUPT_BASE 24 + +#define PC01_IOAPIC (UINT64)BIT2 +#define PC01_IOAPIC_ID 0x0A +#define PC01_INTERRUPT_BASE 32 + +#define PC02_IOAPIC (UINT64)BIT3 +#define PC02_IOAPIC_ID 0x0B +#define PC02_INTERRUPT_BASE 40 + +#define PC03_IOAPIC (UINT64)BIT4 +#define PC03_IOAPIC_ID 0x0C +#define PC03_INTERRUPT_BASE 48 + +#define PC04_IOAPIC (UINT64)BIT5 +#define PC04_IOAPIC_ID 0x0D +#define PC04_INTERRUPT_BASE 56 + +#define PC05_IOAPIC (UINT64)BIT6 +#define PC05_IOAPIC_ID 0x0E +#define PC05_INTERRUPT_BASE 64 + +#define PC06_IOAPIC (UINT64)BIT7 +#define PC06_IOAPIC_ID 0x0F +#define PC06_INTERRUPT_BASE 72 + +#define PC07_IOAPIC (UINT64)BIT8 +#define PC07_IOAPIC_ID 0x10 +#define PC07_INTERRUPT_BASE 80 + +#define PC08_IOAPIC (UINT64)BIT9 +#define PC08_IOAPIC_ID 0x11 +#define PC08_INTERRUPT_BASE 88 + +#define PC09_IOAPIC (UINT64)BIT10 +#define PC09_IOAPIC_ID 0x12 +#define PC09_INTERRUPT_BASE 96 + +#define PC10_IOAPIC (UINT64)BIT11 +#define PC10_IOAPIC_ID 0x13 +#define PC10_INTERRUPT_BASE 104 + +#define PC11_IOAPIC (UINT64)BIT12 +#define PC11_IOAPIC_ID 0x14 +#define PC11_INTERRUPT_BASE 112 + +#define PC12_IOAPIC (UINT64)BIT13 +#define PC12_IOAPIC_ID 0x15 +#define PC12_INTERRUPT_BASE 120 + +#define PC13_IOAPIC (UINT64)BIT14 +#define PC13_IOAPIC_ID 0x16 +#define PC13_INTERRUPT_BASE 128 + +#define PC14_IOAPIC (UINT64)BIT15 +#define PC14_IOAPIC_ID 0x17 +#define PC14_INTERRUPT_BASE 136 + +#define PC15_IOAPIC (UINT64)BIT16 +#define PC15_IOAPIC_ID 0x18 +#define PC15_INTERRUPT_BASE 144 + +#define PC16_IOAPIC (UINT64)BIT17 +#define PC16_IOAPIC_ID 0x19 +#define PC16_INTERRUPT_BASE 152 + +#define PC17_IOAPIC (UINT64)BIT18 +#define PC17_IOAPIC_ID 0x1A +#define PC17_INTERRUPT_BASE 160 + +#define PC18_IOAPIC (UINT64)BIT19 +#define PC18_IOAPIC_ID 0x1B +#define PC18_INTERRUPT_BASE 168 + +#define PC19_IOAPIC (UINT64)BIT20 +#define PC19_IOAPIC_ID 0x1C +#define PC19_INTERRUPT_BASE 176 + +#define PC20_IOAPIC (UINT64)BIT21 +#define PC20_IOAPIC_ID 0x1D +#define PC20_INTERRUPT_BASE 184 + +#define PC21_IOAPIC (UINT64)BIT22 +#define PC21_IOAPIC_ID 0x1E +#define PC21_INTERRUPT_BASE 192 + +#define PC22_IOAPIC (UINT64)BIT23 +#define PC22_IOAPIC_ID 0x1F +#define PC22_INTERRUPT_BASE 200 + +#define PC23_IOAPIC (UINT64)BIT24 +#define PC23_IOAPIC_ID 0x20 +#define PC23_INTERRUPT_BASE 208 + +#define PC24_IOAPIC (UINT64)BIT25 +#define PC24_IOAPIC_ID 0x21 +#define PC24_INTERRUPT_BASE 216 + +#define PC25_IOAPIC (UINT64)BIT26 +#define PC25_IOAPIC_ID 0x22 +#define PC25_INTERRUPT_BASE 224 + +#define PC26_IOAPIC (UINT64)BIT27 +#define PC26_IOAPIC_ID 0x23 +#define PC26_INTERRUPT_BASE 232 + +#define PC27_IOAPIC (UINT64)BIT28 +#define PC27_IOAPIC_ID 0x24 +#define PC27_INTERRUPT_BASE 240 + +#define PC28_IOAPIC (UINT64)BIT29 +#define PC28_IOAPIC_ID 0x25 +#define PC28_INTERRUPT_BASE 248 + +#define PC29_IOAPIC (UINT64)BIT30 +#define PC29_IOAPIC_ID 0x26 +#define PC29_INTERRUPT_BASE 256 + +#define PC30_IOAPIC (UINT64)BIT31 +#define PC30_IOAPIC_ID 0x27 +#define PC30_INTERRUPT_BASE 264 + +#define PC31_IOAPIC (UINT64)BIT32 +#define PC31_IOAPIC_ID 0x28 +#define PC31_INTERRUPT_BASE 272 + +#define PC32_IOAPIC (UINT64)BIT33 +#define PC32_IOAPIC_ID 0x29 +#define PC32_INTERRUPT_BASE 280 + +#define PC33_IOAPIC (UINT64)BIT34 +#define PC33_IOAPIC_ID 0x2A +#define PC33_INTERRUPT_BASE 288 + +#define PC34_IOAPIC (UINT64)BIT35 +#define PC34_IOAPIC_ID 0x2B +#define PC34_INTERRUPT_BASE 296 + +#define PC35_IOAPIC (UINT64)BIT36 +#define PC35_IOAPIC_ID 0x2C +#define PC35_INTERRUPT_BASE 304 + +#define PC36_IOAPIC (UINT64)BIT37 +#define PC36_IOAPIC_ID 0x2D +#define PC36_INTERRUPT_BASE 312 + +#define PC37_IOAPIC (UINT64)BIT38 +#define PC37_IOAPIC_ID 0x2E +#define PC37_INTERRUPT_BASE 320 + +#define PC38_IOAPIC (UINT64)BIT39 +#define PC38_IOAPIC_ID 0x2F +#define PC38_INTERRUPT_BASE 328 + +#define PC39_IOAPIC (UINT64)BIT40 +#define PC39_IOAPIC_ID 0x30 +#define PC39_INTERRUPT_BASE 336 + +#define PC40_IOAPIC (UINT64)BIT41 +#define PC40_IOAPIC_ID 0x31 +#define PC40_INTERRUPT_BASE 344 + +#define PC41_IOAPIC (UINT64)BIT42 +#define PC41_IOAPIC_ID 0x32 +#define PC41_INTERRUPT_BASE 352 + +#define PC42_IOAPIC (UINT64)BIT43 +#define PC42_IOAPIC_ID 0x33 +#define PC42_INTERRUPT_BASE 360 + +#define PC43_IOAPIC (UINT64)BIT44 +#define PC43_IOAPIC_ID 0x34 +#define PC43_INTERRUPT_BASE 368 + +#define PC44_IOAPIC (UINT64)BIT45 +#define PC44_IOAPIC_ID 0x35 +#define PC44_INTERRUPT_BASE 376 + +#define PC45_IOAPIC (UINT64)BIT46 +#define PC45_IOAPIC_ID 0x36 +#define PC45_INTERRUPT_BASE 384 + +#define PC46_IOAPIC (UINT64)BIT47 +#define PC46_IOAPIC_ID 0x37 +#define PC46_INTERRUPT_BASE 392 + +#define PC47_IOAPIC (UINT64)BIT48 +#define PC47_IOAPIC_ID 0x38 +#define PC47_INTERRUPT_BASE 400 + +// +// Define platform base +// Note: All the PCH devices must get Legacy IO resources within first 16KB +// since KTI RC allcoates range 0-16KB for the legacy IIO. +// +#define PCH_ACPI_BASE_ADDRESS PcdGet16 (PcdAcpiBaseAddress) = // ACPI Power Management I/O Register Base Address + +#define PCH_TCO_BASE_ADDRESS PcdGet16 (PcdTcoBaseAddress) + +#define SIO_GPIO_BASE_ADDRESS 0x0800 + +// +// SMBUS Data +// +#define PCH_SMBUS_BASE_ADDRESS 0x0780 + +// +// CMOS usage +// + +// Second bank +// +#define CMOS_PLATFORM_ID_LO 0x18 // Second bank CMO= S location of Platform ID +#define CMOS_PLATFORM_ID_HI 0x19 // + +#define PCI_BUS_NUMBER_PCH_HPET 0x0 +#define PCI_DEVICE_NUMBER_PCH_HPET 0x1F + +#define PCI_FUNCTION_NUMBER_PCH_HPET0 0x00 + +#define PCI_BUS_NUMBER_PCH_IOAPIC 0x00 +#define PCI_DEVICE_NUMBER_PCH_IOAPIC 0x1E + +#define PCI_FUNCTION_NUMBER_PCH_IOAPIC 0x0 + +// +// AHCI port offset values +// +#define EFI_AHCI_PORT_START 0x0100 +#define EFI_AHCI_PORT_REG_WIDTH 0x0080 +#define EFI_AHCI_PORT_CLB 0x0000 +#define EFI_AHCI_PORT_CLBU 0x0004 +#define EFI_AHCI_PORT_FB 0x0008 +#define EFI_AHCI_PORT_FBU 0x000C +#define EFI_AHCI_PORT_IS 0x0010 +#define EFI_AHCI_PORT_IE 0x0014 +#define EFI_AHCI_PORT_CMD 0x0018 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h new file mode 100644 index 0000000000..ca91434663 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -0,0 +1,106 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_TYPES_H_ +#define _PLATFORM_INFO_TYPES_H_ + +// +// DIMM Connector type +// +typedef enum { + DimmConnectorPth =3D 0x00, // Through hole connector + DimmConnectorSmt, // Surface mount connector + DimmConnectorMemoryDown, // Platform soldered DRAMs + DimmConnectorIgnore, // Ignore connector type + DimmConnectorMax +} EFI_MEMORY_DIMM_CONNECTOR_TYPE; + +// +// Platform types - used with EFI_PLATFORM_INFO BoardId +// +typedef enum { + StartOfEfiPlatformTypeEnum =3D 0x00, + //For PPO + TypeNeonCityEPRP, + TypeWolfPass, + TypeTennesseePass, + TypeHedtCRB, + TypeLightningRidgeEXRP, + TypeLightningRidgeEX8S1N, + TypeBarkPeak, + TypeYubaCityRP, + TypeRidgeport, + //End PPO + TypeWilsonCityRP, + TypeWilsonCityModular, + TypeCoyotePass, + TypeIdaville, + TypeMoroCityRP, + TypeBrightonCityRp, + TypeJacobsville, + TypeSnrSvp, + TypeSnrSvpSodimm, + TypeJacobsvilleMDV, + TypeFrostCreekRP, + TypeVictoriaCanyonRP, + TypeArcherCityRP, + TypeNeonCityEPECB, + TypeIsoscelesPeak, + TypeWilsonPointRP, + TypeWilsonPointModular, + TypeBretonSound, + TypeWilsonCityPPV, + TypeCooperCityRP, + TypeWilsonCitySMT, + TypeSnrSvpSodimmB, + TypeArcherCityModular, + TypeArcherCityEVB, + TypeArcherCityXPV, + TypeBigPineKey, + TypeExperWorkStationRP, + EndOfEfiPlatformTypeEnum +} EFI_PLATFORM_TYPE; + +#define TypePlatformUnknown 0xFF +#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 +#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 +#define TypePlatformDefault TypeWilsonPointRP + +// +// CPU type: Standard (no MCP), -F, etc +// +typedef enum { + CPU_TYPE_STD, + CPU_TYPE_F, + CPU_TYPE_P, + CPU_TYPE_MAX +} CPU_TYPE; + +#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD) +#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F) +#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P) + +typedef enum { + DaisyChainTopology =3D 0x00, + InvSlotsDaisyChainTopology, + TTopology +} EFI_MEMORY_TOPOLOGY_TYPE; + +// +// Values for SocketConfig +// + +#define SOCKET_UNDEFINED 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 +#define SOCKET_1S 3 +#define SOCKET_1SWS 4 +#define SOCKET_8S 5 +#define SOCKET_2S 6 + +#endif // #ifndef _PLATFORM_INFO_TYPES_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPp= i.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h new file mode 100644 index 0000000000..c6915582c6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h @@ -0,0 +1,474 @@ +/** @file + UBS silicon access PPI + + This PPI abstracts all UBA silicon accesses + + @copyright + Copyright 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DYNAMIC_SI_LIBARY_PPI_H_ +#define _DYNAMIC_SI_LIBARY_PPI_H_ + +// {C1176733-159F-42d5-BCB9-320660B17310} +#define DYNAMIC_SI_LIBARY_PPI_GUID \ + { 0x4e18e22b, 0x5034, 0x4512, { 0xb7, 0xe5, 0x0b, 0xf1, 0x9d, 0xe3, 0x59= , 0x8c } } + +#define UBA_ACCESS_PPI_VERSION 01 +#define UBA_ACCESS_PPI_SIGNATURE SIGNATURE_32('D', 'S', 'L', 'P') + +#include +#include +#include +#include +#include + +// +// Functions +// + +typedef +EFI_STATUS +(EFIAPI *PEI_GET_GPIO_INPUT_VALUE) ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_SET_GPIO_OUTPUT_VALUE) ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_GPIO_SET_PAD) ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +typedef +UINT16 +(EFIAPI *PEI_GET_PCH_DEVICE_ID) ( + VOID + ); + +typedef +PCH_SERIES +(EFIAPI *PEI_GET_PCH_SERIES) ( + VOID + ); + +typedef +PCH_STEPPING +(EFIAPI *PEI_GET_PCH_STEPPING) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IS_PCH_GBE_REGION_VALID) ( + VOID + ); + +typedef +UINT32 +(EFIAPI *PEI_GET_PCH_GBE_PORT_NUMBER) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IS_PCH_GBE_PRESENT) ( + VOID + ); + +typedef +VOID +(EFIAPI *PEI_PchDisableGbe) ( + VOID + ); + +typedef +VOID +(EFIAPI *PEI_PchDisableGbeByPchId) ( + IN UINT8 PchId + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_GpioConfigurePadsByPchId) ( + IN UINT8 PchId, + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_GpioGetInputValueByPchId) ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PeiGetCurrenClockingMode) ( + OUT CLOCKING_MODES *ClockingMode + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_GetPchPcieRpDevFunByPchId) ( + IN UINT8 PchId, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IsSimicsEnvironment) ( + VOID + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPchMaxSataPortNum) ( + VOID + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPchMaxsSataPortNum) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_GpioSetPadConfigByPchId) ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPchMaxPciePortNum) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchGetSataLaneNumByPchId) ( + IN UINT8 PchId, + UINT32 SataLaneIndex, + UINT8 *LaneNum + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchGetPcieLaneNumByPchId) ( + IN UINT8 PchId, + UINT32 PcieLaneIndex, + UINT8 *LaneNum + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchGetsSataLaneNumByPchId) ( + IN UINT8 PchId, + UINT32 SataLaneIndex, + UINT8 *LaneNum + ); + +typedef +UINTN +(EFIAPI *PEI_MmPciBase) ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function + ); + +typedef +BOOLEAN +(EFIAPI *PEI_HybridSystemLevelEmulationEnabled) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IioIsSocketPresent) ( + IN UINT8 IioIndex + ); + +typedef +UINT8 +(EFIAPI *PEI_GetMaxPortNumPerSocket) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IsVMDEnabledForPort) ( + IN UINT8 IioIndex, + IN UINT8 PortIndex + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IioAreLanesAssignedToPort) ( + IN IIO_GLOBALS *IioGlobalData, + IN UINT8 IioIndex, + IN UINT8 PortIndex + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPortIndexbyStack) ( + IN UINT8 StackIndex, + IN UINT8 PortIndex + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IsDmiStack) ( + IN UINT8 Stack + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IsCpuAndRevision) ( + IN UINT8 CpuType, + IN UINT16 Revision + ); + +typedef +UINT8 +(EFIAPI *PEI_GetMaxStackNumPerSocket) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_IioIsStackPresent) ( + IN UINT8 IioIndex, + IN UINT8 StackIndex + ); + +typedef +UINT8 +(EFIAPI *PEI_GetMaxPortNumPerStack) ( + IN UINT8 Stack + ); + +// +// From KtiApi.h +// +typedef +BOOLEAN +(EFIAPI *PEI_SocketPresent) ( + IN UINT32 SocId + ); + +/** + Get SVID Mapping from Socket and MCID + + @param[in] Socket - Socket Id - 0 based + @param[in] McId - Memory controller 0 based + @param[in] SvidValue - SVID Value + + @retval EFI_SUCCESS - Value found + @retval EFI_NOT_FOUND - Value not found + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_GetSvidMap) ( + IN UINT8 Socket, + IN UINT8 McId, + IN UINT8 *SvidValue + ); + +typedef +UINT16 +(EFIAPI *PEI_PmcGetAcpiBase) ( + VOID + ); + +typedef +UINT16 +(EFIAPI *PEI_PmcGetAcpiBaseByPchId) ( + IN UINT8 PchId + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchLpcIoDecodeRangesSet) ( + IN UINT16 LpcIoDecodeRanges + ); + +typedef +VOID +(EFIAPI *PEI_CheckPowerOffNow) ( + VOID + ); + +typedef +VOID +(EFIAPI *PEI_PmcSetPlatformStateAfterPowerFailure) ( + IN UINT8 PowerStateAfterG3 + ); + +typedef +VOID +(EFIAPI *PEI_PmcClearPowerFailureStatus) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_PmcIsPowerFailureDetected) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchLpcGenIoRangeSet) ( + IN UINT16 Address, + IN UINTN Length + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchLpcIoEnableDecodingSet) ( + IN UINT16 LpcIoEnableDecoding + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchPcrAndThenOr32) ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_PchPcrRead32ByPchId) ( + IN UINT8 PchId, + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +typedef +UINT8 +(EFIAPI *PEI_ReadNmiEn) ( + VOID + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPchXhciMaxUsb2PortNum) ( + VOID + ); + +typedef +UINT8 +(EFIAPI *PEI_GetPchXhciMaxUsb3PortNum) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_PchIsGbeAvailable) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_EnableMcaOnCacheableMmio) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *PEI_X2ApicIdDetect) ( + IN VOID *Host + ); + +// +// Abstracting silicon functional implementations from OpenBoardPkg code +// +typedef struct { + UINT32 Signature; + UINT32 Version; + + PEI_GET_GPIO_INPUT_VALUE GpioGetInputValue; + PEI_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue; + PEI_GPIO_SET_PAD GpioSetPadConfig; + + PEI_GET_PCH_DEVICE_ID GetPchLpcDeviceId; + PEI_GET_PCH_SERIES GetPchSeries; + PEI_GET_PCH_STEPPING PchStepping; + PEI_IS_PCH_GBE_REGION_VALID PchIsGbeRegionValid; + PEI_GET_PCH_GBE_PORT_NUMBER PchGetGbePortNumber; + PEI_IS_PCH_GBE_PRESENT PchIsGbePresent; + + PEI_PchDisableGbeByPchId PchDisableGbeByPchId; + PEI_GpioConfigurePadsByPchId GpioConfigurePadsByPchId; + PEI_GpioSetPadConfigByPchId GpioSetPadConfigByPchId; + PEI_GpioGetInputValueByPchId GpioGetInputValueByPchId; + PEI_PeiGetCurrenClockingMode PeiGetCurrenClockingMode; + PEI_GetPchPcieRpDevFunByPchId GetPchPcieRpDevFunByPchId; + PEI_IsSimicsEnvironment IsSimicsEnvironment; + PEI_GetPchMaxSataPortNum GetPchMaxSataPortNum; + PEI_GetPchMaxsSataPortNum GetPchMaxsSataPortNum; + PEI_GetPchMaxPciePortNum GetPchMaxPciePortNum; + PEI_PchGetSataLaneNumByPchId PchGetSataLaneNumByPchId; + PEI_PchGetsSataLaneNumByPchId PchGetsSataLaneNumByPchId; + PEI_PchGetPcieLaneNumByPchId PchGetPcieLaneNumByPchId; + PEI_MmPciBase MmPciBase; + PEI_HybridSystemLevelEmulationEnabled HybridSystemLevelEmulationEnab= led; + PEI_IioIsSocketPresent IioIsSocketPresent; + PEI_GetMaxPortNumPerSocket GetMaxPortNumPerSocket; + PEI_IsVMDEnabledForPort IsVMDEnabledForPort; + PEI_IioAreLanesAssignedToPort IioAreLanesAssignedToPort; + PEI_GetPortIndexbyStack GetPortIndexbyStack; + PEI_IsDmiStack IsDmiStack; + PEI_IsCpuAndRevision IsCpuAndRevision; + PEI_PchDisableGbe PchDisableGbe; + PEI_GetMaxStackNumPerSocket GetMaxStackNumPerSocket; + PEI_IioIsStackPresent IioIsStackPresent; + PEI_GetMaxPortNumPerStack GetMaxPortNumPerStack; + PEI_SocketPresent SocketPresent; + PEI_GetSvidMap GetSvidMap; + + PEI_PmcGetAcpiBase PmcGetAcpiBase; + PEI_PmcGetAcpiBaseByPchId PmcGetAcpiBaseByPchId; + PEI_PchLpcIoDecodeRangesSet PchLpcIoDecodeRangesSet; + PEI_CheckPowerOffNow CheckPowerOffNow; + PEI_PmcSetPlatformStateAfterPowerFailure PmcSetPlatformStateAfterPowerF= ailure; + PEI_PmcClearPowerFailureStatus PmcClearPowerFailureStatus; + PEI_PmcIsPowerFailureDetected PmcIsPowerFailureDetected; + PEI_PchLpcGenIoRangeSet PchLpcGenIoRangeSet; + PEI_PchLpcIoEnableDecodingSet PchLpcIoEnableDecodingSet; + PEI_PchPcrAndThenOr32 PchPcrAndThenOr32; + PEI_PchPcrRead32ByPchId PchPcrRead32ByPchId; + PEI_ReadNmiEn ReadNmiEn; + + PEI_GetPchXhciMaxUsb2PortNum GetPchXhciMaxUsb2PortNum; + PEI_GetPchXhciMaxUsb3PortNum GetPchXhciMaxUsb3PortNum; + PEI_PchIsGbeAvailable PchIsGbeAvailable; + PEI_EnableMcaOnCacheableMmio EnableMcaOnCacheableMmio; + PEI_X2ApicIdDetect X2ApicIdDetect; +} DYNAMIC_SI_LIBARY_PPI; + +extern EFI_GUID gDynamicSiLibraryPpiGuid; + +#endif // _DYNAMIC_SI_LIBARY_PPI_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h = b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h new file mode 100644 index 0000000000..6c5ca06bc1 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h @@ -0,0 +1,2112 @@ +/** @file + Header file defining MEMORY_POLICY_PPI, which is for platform code to se= t platform + specific configurations of memory reference code. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_POLICY_PPI_H_ +#define _MEMORY_POLICY_PPI_H_ + +#include +#include +#include +#include +#include + + +/// +/// Number of group of BIOS-to-Pcode Mailbox command. +// +#define MAX_B2P_MAILBOX_GROUPS 32 + +#pragma pack(push, 1) + +/// +/// Memory Timings Settings. +// +struct memTiming { + + /// + /// @brief + /// Column Latency. + /// @details + /// Column Latency (CL) time is the number of clock cycles needed to acc= ess a + /// certain column of data in RAM. It's also known as CAS (column address + /// strobe) time. + // + UINT8 nCL; + + /// + /// @brief + /// Row Precharge. + /// @details + /// RP (row precharge) time is the number of clock cycles needed to term= inate + /// access to an open row of memory, and open access to the next row. + // + UINT8 nRP; + + /// + /// @brief + /// RAS to CAS Delay. + /// @details + /// RAS to CAS Delay (RCD) is the number of clock cycles delay required + /// between an active command row address strobe (RAS) and a CAS. It is + /// the time required between the memory controller asserting a row addr= ess, + /// and then asserting a column address during the subsequent read or wr= ite + /// command. RCD stands for row address to column address delay time. + // + UINT8 nRCD; + + /// + /// @brief + /// Row to Row Delay. + /// @details + /// Active to Active Delay, Row to Row Delay or RAS to RAS Delay. The am= ount of + /// cycles that taken to activate the next bank of memory. + // + UINT8 nRRD; + UINT8 nRRD_L; + + /// + /// @brief + /// Write to Read Delay. + /// @details + /// Write to Read Delay. The amount of cycles required between a valid w= rite + /// command and the next read command. + // + UINT8 nWTR; + + /// + /// @brief + /// Row Active Strobe. + /// @details + /// Row Active Strobe (RAS) time is the minimum number of clock cycles n= eeded + /// to access a certain row of data in RAM between the data request and = the + /// precharge command. It's known as active to precharge delay. + // + UINT8 nRAS; + + /// + /// @brief + /// Read To Precharge delay. + /// @details + /// The number of clocks between a read command to a row pre-charge comm= and. + // + UINT8 nRTP; + + /// + /// @brief + /// Write Recovery time. + /// @details + /// The amount of cycles that are required between a valid + /// write operation and precharge, to make sure that data is written pro= perly. + /// + UINT8 nWR; + + /// + /// @brief + /// Four Activate Window. + /// @details + /// Four Activate Window, which specifies the time window in wich four a= ctivates + /// are allowed on the same rank. + // + UINT8 nFAW; + + /// + /// CAS (WRITE) latency (CWL). + // + UINT8 nCWL; + + /// + /// @brief + /// Row Cycle. + /// @details + /// Row Cycle time, the minimum time in cycles taken for a row to comple= te a full + /// cycle, which typically can be calculated by nRC =3D nRAS + nRP. + // + UINT8 nRC; + + /// + /// @brief + /// Command Rate. + /// @details + /// Command Rate / Command per Clock (1T/2T) is the delay between a memo= ry chip + /// is selected and the first active command can be issued. + // + UINT8 nCMDRate; + + /// + /// The limit of DDR frequency ratio, based on base clock frequency. + // + UINT8 ddrFreqLimit; + + /// + /// Vdd for DRAM core. + // + UINT16 vdd; + + /// + /// XMP Memory Controller Voltage Level. + // + UINT8 ucVolt; + + /// + /// Bits map to indicate if a CAS in a CAS list is supported. + // + UINT64 casSup; + + /// + /// Refresh Interval. + // + UINT16 tREFI; + + /// + /// @brief + /// Refresh to Activate Delay. + /// @details + /// Refresh to Activate Delay or Refresh Cycle Time. The number of clock= s from + /// a Refresh command to the first Activate command. + // + UINT16 nRFC; + + /// + /// Frequency of DDR. + // + UINT16 ddrFreq; +}; + +typedef struct ReservedS193 { + + UINT8 ReservedS69; + + UINT8 ReservedS70; + + UINT8 ReservedS68; + + UINT8 ReservedS67; + + UINT8 ReservedS71; + + UINT8 ReservedS74[MAX_SOCKET * MAX_IMC]; + + UINT8 ReservedS194[MAX_SOCKET]; + + UINT8 ReservedS77; + + UINT8 ReservedS48; + + UINT32 ReservedS195; + + UINT8 ReservedS196; + + UINT8 ReservedS107; + + UINT8 ReservedS105; + + UINT8 ReservedS75; + + UINT8 ReservedS108; + + UINT8 ReservedS73; + + UINT8 ReservedS197; + + + UINT8 ReservedS49; + + UINT8 ReservedS50; + + UINT8 ReservedS51; + + UINT8 ReservedS52; + + UINT16 ReservedS53; + + UINT16 ReservedS54; + + UINT16 ReservedS55; + + UINT16 ReservedS56; + + UINT16 ReservedS57; + + UINT8 ReservedS58; + + UINT16 ReservedS59; + + UINT8 ReservedS60; + + UINT16 ReservedS61; + + UINT8 ReservedS62; + + UINT8 ReservedS63; + + UINT16 ReservedS64; + + UINT16 ReservedS65; + + UINT8 ReservedS66; + + UINT8 ReservedS198 : 1, + ReservedS199 : 1, + ReservedS200 : 1, + ReservedS119 : 1, + ReservedS201 : 4; + UINT8 ReservedS120; + + BOOLEAN ReservedS128; // Posted CSR access metho= d is available when this is TRUE + + BOOLEAN ReservedS130; + + UINT16 ReservedS131; + + BOOLEAN ReservedS111; + + BOOLEAN ReservedS202; + + UINT8 ReservedS203; + + BOOLEAN ReservedS204; + + BOOLEAN ReservedS205; + + BOOLEAN ReservedS206; + + UINT8 ReservedS121; + + UINT8 ReservedS122; + + UINT8 ReservedS123; + + UINT8 ReservedS124; + + UINT8 ReservedS125; + + UINT8 ReservedS126; + + UINT8 ReservedS127; + + BOOLEAN ReservedS137; + + UINT8 SenseAmpCalibHwSwOption; + + BOOLEAN ReservedS129; + + UINT8 ReservedS207 :4, + ReservedS208 :1, + ReservedS209 :1, + ReservedS210 :2; + + UINT8 ReservedS143; + + UINT8 ReservedS144; + + UINT8 ReservedS145; + + UINT8 ReservedS211 :4, + ReservedS212 :1, + ReservedS213 :3; + + UINT8 ReservedS148; + + + UINT8 ReservedS149; + +} RESERVED_S193; + +/// +/// DIMM enable/disable information +// +struct ddrDimmSetup { + + /// + /// Setting for each DIMM to be mapped out. + // + UINT8 mapOut[MAX_RANK_DIMM]; +}; + +/// +/// Channel setup structure declaration +// +struct ddrChannelSetup { + UINT8 enabled; /// Channel enable switch. + UINT8 numDimmSlots; /// Number of DIMM slots per cha= nnel. + UINT8 batterybacked; /// ADR Battery backed or not. + UINT8 rankmask; /// Rank mask. 0 =3D disable; 1 = =3D enable. + struct ddrDimmSetup dimmList[MAX_DIMM]; /// DIMM enable/disable informat= ion. +}; + +/// +/// PPR DRAM Address. +// +typedef struct { + UINT8 dimm; + UINT8 rank; + UINT8 subRank; + UINT32 nibbleMask; + UINT8 bank; + UINT32 row; +} PPR_ADDR; + +/// +/// PPR Address, buffer to hold DRAM Address that need to be repaired.
+// +typedef struct { + UINT8 pprAddrStatus; + UINT8 socket; + UINT8 mc; + UINT8 ch; + PPR_ADDR pprAddr; +} PPR_ADDR_MRC_SETUP; + + +/// +/// Socket setup structure declaration. +// +struct ddrSocketSetup { + + /// + /// iMC enable/disable switch. + // + UINT8 enabled; + + /// + /// Bit-mapped options per socket. + // + UINT8 options; + + /// + /// Platform configuration for each channel. + // + struct ddrChannelSetup ddrCh[MAX_CH]; + + /// + /// Enable/Disable memory controller. + // + UINT8 imcEnabled[MAX_IMC]; +}; + +/// +/// Define AdvMemTest Rank List item +/// The input format is defined as follows: +/// Rank number in bits[3:0] +/// DIMM number in bits[7:4] +/// Channel number in the MC in bits[11:8] +/// MC number in bits[15:12] +/// Socket number in bits [19:16] +/// bits [31:20] are reserved +/// For example: +/// To test MC 0, CH 1, DIMM 0, RANK 0 on Socket 0, you need to enter a v= alue of 0x100 +/// To test MC 1, CH 0, DIMM 0, RANK 0 on Socket 0, you need to enter a v= alue of 0x1000 +// +typedef union { + struct { + UINT32 Rank: 4; + UINT32 Dimm: 4; + UINT32 Channel: 4; + UINT32 Mc: 4; + UINT32 Socket: 4; + UINT32 rsvd: 12; + } Bits; + UINT32 Data; +} AdvMemTestRankData; + +/// +/// Host memory setup structure declaration. +// +struct memSetup { + + /// + /// @brief + /// Flags for enabling (1)/disabling(0) MRC features.
+ /// @details + /// TEMPHIGH_EN BIT0, enables support for 95 degree DI= MMs.
+ /// ATTEMPT_FAST_BOOT_COLD BIT1.
+ /// PDWN_SR_CKE_MODE BIT2, enables CKE to be tri-stated dur= ing + /// register clock off power down se= lf-refresh.
+ /// OPP_SELF_REF_EN BIT3, enables the opportunistic self r= efresh mechanism.
+ /// MDLL_SHUT_DOWN_EN BIT4, enables MDLL shutdown.
+ /// PAGE_POLICY BIT5, Clear for open page, set for clo= sed page. Open page + /// has better performance and power= usage in general. + /// Close page may benefit some appl= ications with poor
+ /// locality.
+ /// ALLOW2XREF_EN BIT6, enables 2X refresh if needed for= extended operating + /// temperature range (95degrees) If= TEMPHIGH_EN is also + /// set, setting this bit will resul= t in 2X refresh timing + /// for the IMC refresh control regi= ster.
+ /// MULTI_THREAD_MRC_EN BIT7, enables multithreaded MRC. This = reduces boot time for + /// systems with multiple processor = sockets.
+ /// ADAPTIVE_PAGE_EN BIT8, enables adaptive page mode. The = memory controller will + /// dynamically determine how long t= o keep pages open
+ /// to improve performance.
+ /// CMD_CLK_TRAINING_EN BIT9, enables command to clock trainin= g step.
+ /// SCRAMBLE_EN BIT10, set to enable data scrambling. = This should always be + /// enabled except for debug purpos= es.
+ /// SCRAMBLE_EN_DDRT BIT11, set to enable data scrambling. = This should always be + /// enabled except for debug purpos= es.
+ /// DISPLAY_EYE_EN BIT12,
+ /// DDR_RESET_LOOP BIT13, enables infinite channel reset = loop without retries + /// for gathering of margin data. + /// NUMA_AWARE BIT14, enables configuring memory inte= rleaving appropriately + /// for NUMA aware OS.
+ /// DISABLE_WMM_OPP_READ BIT15, disables issuing read commands = opportunistically during WMM.
+ /// RMT_COLD_FAST_BOOT BIT16.
+ /// ECC_CHECK_EN BIT17, enables ECC checking.
+ /// ECC_MIX_EN BIT18, enables ECC in a system with mi= xed ECC and non-ECC memory in a + /// channel by disabling ECC when t= his configuration is detected.
+ /// DISABLE_ECC_SUPPORT BIT19, disables ECC check.
+ /// CA_PARITY_EN BIT20,
+ /// PER_NIBBLE_EYE_EN BIT22. + /// RAS_TO_INDP_EN BIT23, switches from lockstep or mirro= r mode to independenct channel + /// mode when memory is present on = channel 2 and this is enabled.
+ /// MARGIN_RANKS_EN BIT25, enables the rank margin tool. + /// MEM_OVERRIDE_EN BIT26, enables use of inputMemTime inp= uts as hard overrides.
+ /// DRAMDLL_OFF_PD_EN BIT27,
+ /// MEMORY_TEST_EN BIT28, enables execution of MemTest if= on cold boot
+ /// MEMORY_TEST_COLD_FAST_BOOT_EN BIT29, enables the memory test when go= ing through a cold fast boot + /// path
+ /// ATTEMPT_FAST_BOOT BIT30, attempts to take a fast boot pa= th if the NVRAM structure is good + /// and the memory config hasn't ch= anged. For example, on a warm boot, + /// this will take the "fast warm" = path through MRC which attempts + /// to make it as close as possible= to the S3 path.
+ /// SW_MEMORY_TEST_EN BIT31.
+ // + UINT32 options; + + /// + /// @brief + /// Flags for enabling (1)/disabling(0) MRC features.
+ /// @details + /// PD_CRC_CHECK BIT0
+ /// SET_MEM_TESTED_EN BIT1
+ /// AVAILABLE BIT2
+ /// TURNAROUND_OPT_EN_DDRT BIT3
+ /// PDA_EN BIT5
+ /// TURNAROUND_OPT_EN BIT6
+ /// AVAILABLE BIT7
+ /// ALLOW_CORRECTABLE_ERROR BIT8
+ /// ALLOW_CORRECTABLE_MEM_TEST_ERROR BIT9
+ /// AVAILABLE BIT10
+ /// AVAILABLE BIT11
+ /// AVAILABLE BIT12
+ /// PER_BIT_MARGINS BIT13
+ /// DUTY_CYCLE_EN BIT14
+ /// LRDIMM_BACKSIDE_VREF_EN BIT15
+ /// AVAILABLE BIT16
+ /// DRAM_RX_EQ_EN BIT17
+ /// AVAILABLE BIT18
+ /// AVAILABLE BIT19
+ /// AVAILABLE BIT20
+ /// OPTIONS_EXT_RESERVED1 BIT21
+ /// AVAILABLE BIT22
+ /// WR_CRC BIT23
+ /// OPTIONS_EXT_RESERVED2 BIT24
+ /// AVAILABLE BIT25
+ /// AVAILABLE BIT26
+ /// AVAILABLE BIT27
+ /// AVAILABLE BIT28
+ /// DIMM_ISOLATION_EN BIT29
+ /// AVAILABLE BIT30
+ // + UINT32 optionsExt; + + /// + /// @brief + /// NGN Flags. + /// @details + /// NGN_CMD_TIME BIT1
+ /// NGN_DEBUG_LOCK BIT6
+ /// NGN_ARS_ON_BOOT BIT7
+ /// NGN_ARS_PUBLISH BIT9
+ /// NGN_ECC_EXIT_CORR BIT10
+ /// NGN_ECC_CORR BIT11
+ /// NGN_ECC_WR_CHK BIT12
+ /// NGN_ECC_RD_CHK BIT13
+ // + UINT32 optionsNgn; + + + /// + /// @brief + /// PDA behavior for x16 devices.
+ /// @details + /// 0 - will disable PDA operation when a x16 device is detected.
+ /// 1 - will not modify PDA Mode.
+ // + UINT8 PdaModeX16; + + /// + /// @brief + /// IMC BCLK frequency.
+ /// @details + /// 0 - Auto, MRC code determine the value.
+ /// 1 - 100MHz.
+ /// 2 - 133MHz.
+ // + UINT8 imcBclk; + + /// + /// @brief + /// Enforce memory POR configurations.
+ /// @details + /// 0 (ENFORCE_POR_EN) - Enforce memory POR.
+ /// 1 (ENFORCE_STRETCH_EN) - Enforce memory frequency stretch goal. + /// 2 (ENFORCE_POR_DIS) - Do not enforce POR configurations.
+ // + UINT8 enforcePOR; + + /// + /// @brief + /// DDR Frequency Limit. + /// @details + /// Forces a DDR frequency slower than the common tCK detected via SPD.<= BR> + /// A DDR frequency faster than the common frequency is a config error.<= BR> + /// Options are 0=3DAUTO, 1=3DDDR_800, 3=3DDDR_1066, 5=3DDDR_1333, 7=3DD= DR_1600,
+ /// 9=3DDDR_1866, 11=3DDDR_2133, 13=3DDDR2400.
+ // + UINT8 ddrFreqLimit; + + /// + /// @brief + /// Channels interleave setting. + /// @details + /// Valid options are 1, 2, or 3 way interleave. Other values defaults + /// to 3 ways interleave.
+ // + UINT8 chInter; + + /// + /// @brief + /// DIMM types.
+ /// @details + /// 0=3DRDIMM, 1=3DUDIMM, 2 =3D RDIMMandUDIMM or SODIMM, 9=3DLRDIMM; 10= =3DQRDIMM, 11=3DNVMDIMM.
+ // + UINT8 dimmTypeSupport; + + /// + /// @brief + /// CKE Power managment mode.
+ /// @details + /// 0 =3D Disabled.
+ /// 1 =3D APD Enabled, PPD Disabled.
+ /// 2 =3D APD Disabled, PPDF Enabled.
+ /// 3 =3D APD Disabled, PPDS Enabled.
+ /// 4 =3D APD Enabled, PPDF Enabled.
+ /// 5 =3D APD Enabled, PPDS Enabled.
+ // + UINT8 ckeThrottling; + + /// + /// @brief + /// Open Loop Thermal Throttling. + /// @details + /// (value/100) * 255 / max number of dimms per channel =3D DIMM_TEMP_TH= RT_LMT THRT_HI.
+ // + UINT8 olttPeakBWLIMITPercent; + + /// + /// @brief + /// Bitmapped field for Thermal Throttling Modes. + /// @details + /// Defined in mem.thermalThrottlingOptions section.
+ // + UINT16 thermalThrottlingOptions; + + /// + /// @brief + /// Option to manualy enter Temperature refresh value. + /// @details + /// Select Manual to use value from HalfxRefreshValue, TwoxRefreshValue = and + /// FourxRefreshValue. Auto for default value in MRC code.
+ /// 0 =3D Auto.
+ /// 1 =3D Manual option select.
+ // + UINT8 TempRefreshOption; + + /// + /// Half X temperature refresh value. + // + UINT8 HalfxRefreshValue; + + /// + /// Two X temperature refresh value. + // + UINT8 TwoxRefreshValue; + + /// + /// Four X temperature refresh value. + // + UINT8 FourxRefreshValue; + + // + // Receive Enable Average Feature + // + BOOLEAN RecEnDelayAverage; + + /// + /// @brief + /// Thermal Throttling O/P bits - (High | Mid | Low).
+ /// @details + /// 0=3D Memhot output disabled,
+ /// 1 =3D Memhot on High,
+ /// 2 =3D Memhot on High|Mid,
+ /// 3 =3D Memhot on High|Mid|Low.
+ // + UINT8 MemHotOuputAssertThreshold; + + /// + /// @brief + /// Enable/Disable the initialization of THRTMID on TEMPLO.
+ /// @details + /// 0 =3D THRTMID on TEMPLO disabled,
+ /// 1 =3D THRTMID on TEMPLO enabled.
+ // + UINT8 ThrottlingMidOnTempLo; + + /// + /// @brief + /// Enable/Disable DRAM RAPL.
+ /// @details + /// 0 - disable.
+ /// 1 - enable.
+ // + UINT8 DramRaplEnable; + + /// + /// Multipler of BW_LIMIT_TF when DRAM RAPL is enabled. + // + UINT8 dramraplbwlimittf; + + /// + /// @brief + /// Notify PCU to enable/disable DRAM PM of memory controller.
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 CmsEnableDramPm; + + /// + /// @brief + /// DRAM RAPL Refresh Base. + /// @details + /// Allows custom tuning of Power scaling by Refresh rate in units of 0.= 1x + /// when DRAM RAPL is enabled.
+ // + UINT8 dramraplRefreshBase; + + /// + /// Enable disable per Bit DeSkew Training. + // + UINT8 perBitDeSkew; + + UINT8 ReservedS214; + UINT8 ReservedS215; + UINT8 ReservedS86; + UINT8 ReservedS216; + UINT8 ReservedS217; + UINT8 ReservedS218; + UINT8 ReservedS219; + UINT8 ReservedS220; + UINT8 ReservedS221; + UINT8 ReservedS222; + UINT8 ReservedS223; + UINT8 ReservedS224; + UINT8 ReservedS225; + UINT8 ReservedS226; + UINT8 ReservedS227; + UINT8 ReservedS228; + UINT8 ReservedS229; + UINT8 ReservedS230; + UINT8 ReservedS231; + UINT8 ReservedS232; + UINT8 ReservedS233; + + /// + /// NVDIMM Factory Reset Clear + // + UINT8 FactoryResetClear; + + /// + /// Enable Backside RMT. + // + UINT8 enableBacksideRMT; + + /// + /// Enable Backside CMD RMT. + // + UINT8 enableBacksideCMDRMT; + + /// + /// Enable NVMDIMM BCOM margining support. + // + UINT8 enableNgnBcomMargining; + + /// + /// @brief + /// Training Result Offset function enable or disable. + /// @details + /// It controls whether to enable the function to offset the final train= ing results or not.
+ /// Enable - Enables training results to be offset.
+ /// Disable - Disables this feature; current default is Enable disable=
+ + // + UINT8 trainingResultOffsetFunctionEnable; + + /// + /// Platform value to offset the final memory training result of TxDq. + // + INT16 offsetTxDq; + + /// + /// Platform value to offset the final memory training result of RxDq. + // + INT16 offsetRxDq; + + /// + /// Platform value to offset the final memory training result of TxVref. + // + INT16 offsetTxVref; + + /// + /// Platform value to offset the final memory training result of RxVref. + // + INT16 offsetRxVref; + + /// + /// Platform value to offset the final memory training result of CmdAll. + // + INT16 offsetCmdAll; + + /// + /// Platform value to offset the final memory training result of CmdVref. + // + INT16 offsetCmdVref; + + /// + /// Platform value to offset the final memory training result of CtlAll. + // + INT16 offsetCtlAll; + + /// + /// Platform value to offset the final memory training result of RecvEn. + // + INT16 OffsetRecEn; + + /// + /// Rank Margin Test: patten length. + // + UINT32 rmtPatternLength; + + /// + /// Rank Margin Test: patten length extension. + // + UINT32 rmtPatternLengthExt; + + /// + /// Memory RAS: Specifies the number of hours it takes for patrol scrub = to scrub all system memory + // + UINT32 patrolScrubDuration; + + /// + /// Enable/Disable Memory RAS die sparing. + // + UINT8 DieSparing; + + /// + /// Memory RAS: Address Range Scrubbing + // + UINT8 NgnAddressRangeScrub; + + /// + /// Number of MemTests loops to execute for legacy MemTest (type 8 and 1= 0), that + /// provides the ability of inverting the data pattern in every odd pass= for detecting + /// opposite polarity faults + // + UINT16 memTestLoops; + + /// + /// CPGC MemTest step bit fields to enable different advanced MemTest op= tions + // + UINT32 AdvMemTestOptions; + + /// + /// Enable/Disable PPR repair during Advanced Memtest + // + UINT8 AdvMemTestPpr; + + /// + /// Retry the Advanced Memtest step after a PPR repair occurs + /// This option is useful for testing that the PPR repair was successful= , but it adds some latency + // + UINT8 AdvMemTestRetry; + + /// + /// Reset row fail list after executing each Advanced MemTest option + /// This option is useful for testing multiple options. + // + UINT8 AdvMemTestResetList; + + /// + /// Set Test Conditions for Advanced Memtest algorithms + /// ADV_MEM_TEST_COND_DISABLE - Do not modify test conditions during Adv= anced Memtest + /// ADV_MEM_TEST_COND_AUTO - Modify test conditions automatically bas= ed on Advanced Memtest algorithm + /// ADV_MEM_TEST_COND_MANUAL - Modify test conditions manually based on= AdvMemTestCond input options + // + UINT8 AdvMemTestCondition; + + /// + /// Manually set Vdd level when AdvMemTestCondition =3D ADV_MEM_TEST_CON= D_MANUAL + /// Specify Vdd in units of mV + // + UINT16 AdvMemTestCondVdd; + + /// + /// Manually set host Write Recovery time when AdvMemTestCondition =3D A= DV_MEM_TEST_COND_MANUAL + /// Specify host tWR value in units of tCK. This timing is only applicab= le in Open Page mode. + // + UINT8 AdvMemTestCondTwr; + + /// + /// Manually set host tREFI time when AdvMemTestCondition =3D ADV_MEM_TE= ST_COND_MANUAL + /// Specify host tREFI in units of usec. 7800 =3D 1x refresh rate; 15600= =3D 0.5x refresh rate + // + UINT16 AdvMemTestCondTrefi; + + /// + /// Manually set Pause time without refresh when AdvMemTestCondition =3D= ADV_MEM_TEST_COND_MANUAL + /// Specify the Pause time in units of msec. It is applied between write= and read steps to test data retention. + // + + UINT32 AdvMemTestCondPause; + /// + /// Indicate the number of Ranks that will be tested in the system. A va= lue of 0 will test all Ranks + /// + // + UINT8 AdvMemTestRankListNumEntries; + + /// + /// The list of Rank addresses in the sysem that will execute AdvMemTest + // + AdvMemTestRankData AdvMemTestRankList[ADV_MT_LIST_LIMIT]; + + UINT8 Reserved0; + UINT8 Reserved1; + UINT8 Reserved2; + UINT32 Reserved3; + UINT32 Reserved4; + UINT8 Reserved5; + UINT8 Reserved6; + /// + /// Low 16 bits of the data scrambling seed. + // + UINT16 scrambleSeedLow; + + /// + /// High 16 bits of the data scrambling seed + // + UINT16 scrambleSeedHigh; + + /// + /// @brief + /// ADR: Enable/Disable Async DRAM Refresh(ADR) feature
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 ADREn; + + /// + /// @brief + /// ADR: Enable/Dsiable Legacy ADR Async DRAM Refresh(ADR) feature
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 LegacyADRModeEn; + + /// + /// @brief + /// ADR: Minimum memory size assigned as system memory when only JEDEC N= VDIMMs are present
+ /// @details + /// 2 - 2GB.
+ /// 4 - 4GB.
+ /// 6 - 6GB.
+ /// 8 - 8GB.
+ // + UINT8 MinNormalMemSize; + + /// + /// @brief + /// ADR: Data Save Mode for ADR.
+ /// @details + /// 0=3DDisabled,
+ /// 1=3DBatterybacked,
+ /// 2=3DNVDIMM.
+ // + UINT8 ADRDataSaveMode; + + /// + /// @brief + /// ADR: Use the PCH_PM_STS register as ADR recovery indicator.
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 check_pm_sts; + + /// + /// @brief + /// ADR: Use the PlatformDetectADR OEM hook function as ADR recovery ind= icator.
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 check_platform_detect; + + /// + /// @brief + /// Memory RAS: Normal operation duration within sparing interval. + // + UINT16 normOppIntvl; + + /// + /// @brief + /// SM Bus Clock Frequency- see SMB_CLOCK_FREQUENCY.
+ /// @details + /// 0 - SMB_CLK_100K.
+ /// 1 - SMB_CLK_400K.
+ /// 2 - SMB_CLK_700K.
+ /// 3 - SMB_CLK_1M.
+ // + SMB_CLOCK_FREQUENCY SpdSmbSpeed; + + /// + /// @brief + /// Enable(1)/Disable(0) SPD data Print.
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 SpdPrintEn; + + /// + /// @brief + /// Pirnt length of SPD data.
+ /// @details + /// 0 - AUTO(512 for DDR4, 1024 for DDR5).
+ /// 256.
+ /// 512.
+ /// + UINT16 SpdPrintLength; + + /// + /// Socket setup configuration. + // + struct ddrSocketSetup socket[MAX_SOCKET]; + + /// + /// Memory timing settings. + // + struct memTiming inputMemTime; + + UINT32 XMPChecksum[MAX_SOCKET][MAX_CH][MAX_DIMM]; + + UINT32 Reserved7; + + UINT32 Reserved8; + + UINT32 Reserved9; + + /// + /// @brief + /// Custom tuning multiplier of Refresh rate from 2.0x to 4.0x in units = of 0.1x + // + UINT8 customRefreshRate; + + /// + /// @brief + /// Enable Mirror on entire memory for TAD0.
+ /// @details + /// 0 - Disable.
+ /// 1 - Enable.
+ // + UINT8 partialmirrorsad0; + + /// + /// Size of each partial mirror to be created in order. + // + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; + + /// + /// @brief + /// Imitate behavior of UEFI based Address Range Mirror with setup optio= n. + /// @details + /// It controls whether to enable partial mirror in 1LM and 2LM or not. + // + UINT8 partialMirrorUEFI; + + /// + /// @brief + /// Numerator of the mirror ratio.
+ /// @details + /// Given the Numerator (N) and Denominator (D) returned by this functio= n, and
+ /// the total memory size (T), the mirror size (M) should be computed as= follows:
+ /// M =3D (T * N) / D
+ /// MirroredAmountAbove4GB is the amount of available memory above 4GB t= hat needs to be mirrored + /// measured in basis point (hundredths of percent e.g. 12.75% =3D 1275). + /// In a multi-socket system, platform is required to distribute the mir= rored memory ranges such that the + /// amount mirrored is approximately proportional to the amount of memo= ry on each NUMA node. E.g. on + /// a two node machine with 64GB on node 0 and 32GB on node 1, a request= for 12GB of mirrored memory + /// should be allocated with 8GB of mirror on node 0 and 4GB on node 1.<= BR> + UINT32 partialmirrorpercent; + + /// + /// @brief + /// Partial mirror status.
+ /// @details + /// MIRROR_STATUS_SUCCESS 0
+ /// MIRROR_STATUS_MIRROR_INCAPABLE 1
+ /// MIRROR_STATUS_VERSION_MISMATCH 2
+ /// MIRROR_STATUS_INVALID_REQUEST 3
+ /// MIRROR_STATUS_UNSUPPORTED_CONFIG 4
+ /// MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5
+ // + UINT8 partialmirrorsts; + + /// + /// Immediate failover enable or disable when mirror scrub reads a uncor= rected error. + // + UINT8 ImmediateFailoverAction; + + /// + /// Number of times to loop through RMT to test the DLL Reset. + // + UINT8 dllResetTestLoops; + + /// + /// @brief + /// Flags to enable(1)/disable(0) memory training steps in MRC flow. + /// The following are bit to MRC training step map.
+ /// @details + /// MF_X_OVER_EN BIT0;
+ /// MF_SENSE_AMP_EN BIT1;
+ /// MF_E_CMDCLK_EN BIT2;
+ /// MF_REC_EN_EN BIT3;
+ /// MF_RD_DQS_EN BIT4;
+ /// MF_WR_LVL_EN BIT5;
+ /// MF_WR_FLYBY_EN BIT6;
+ /// MF_WR_DQ_EN BIT7;
+ /// MF_CMDCLK_EN BIT8;
+ /// MF_RD_ADV_EN BIT9;
+ /// MF_WR_ADV_EN BIT10;
+ /// MF_RD_VREF_EN BIT11;
+ /// MF_WR_VREF_EN BIT12;
+ /// MF_RT_OPT_EN BIT13;
+ /// MF_RX_DESKEW_EN BIT14;
+ /// MF_TX_DESKEW_EN BIT14;
+ /// MF_TX_EQ_EN BIT15;
+ /// MF_IMODE_EN BIT16;
+ /// MF_EARLY_RID_EN BIT17;
+ /// MF_DQ_SWIZ_EN BIT18;
+ /// MF_LRBUF_RD_EN BIT19;
+ /// MF_LRBUF_WR_EN BIT20;
+ /// MF_RANK_MARGIN_EN BIT21;
+ /// MF_E_WR_VREF_EN BIT22;
+ /// MF_E_RD_VREF_EN BIT23;
+ /// MF_L_RD_VREF_EN BIT24;
+ /// MF_MEMINIT_EN BIT25;
+ /// MF_NORMAL_MODE_EN BIT27;
+ /// MF_CMD_VREF_EN BIT28;
+ /// MF_L_WR_VREF_EN BIT29;
+ /// MF_MEMTEST_EN BIT30;
+ /// MF_E_CTLCLK_EN BIT31.
+ // + UINT32 memFlows; + + /// + /// @brief + /// Extension of flags to enable(1)/disable(0) memory training steps in = MRC flow.
+ /// @details + /// MF_EXT_RX_CTLE_EN BIT0
+ /// MF_EXT_PXC_EN BIT1
+ /// MF_EXT_CMD_NORM_EN BIT2
+ /// MF_EXT_LRDIMM_BKSIDE_EN BIT3
+ /// MF_EXT_CHECK_POR BIT6
+ /// MF_EXT_MMRC_RUN BIT7
+ /// MF_EXT_THROTTLING_EARLY BIT8
+ /// MF_EXT_THROTTLING BIT9
+ /// MF_EXT_POST_TRAINING BIT10
+ /// MF_EXT_E_CONFIG BIT11
+ /// MF_EXT_L_CONFIG BIT12
+ /// MF_EXT_MCODT_EN BIT14
+ /// MF_EXT_MCRON_EN BIT15
+ /// MF_EXT_DIMMRON_EN BIT16
+ /// MF_EXT_CACLK_BACKSIDE_EN BIT17
+ /// MF_DQ_SWIZ_X16_EN BIT18
+ /// MF_EXT_TCO_COMP_EN BIT19
+ /// MF_EXT_TX_SLEW_RATE_EN BIT20
+ /// MF_EXT_INIT_MEM_EN BIT21
+ /// MF_EXT_CMD_TX_EQ_EN BIT22
+ /// MF_EXT_RCOMP_STAT_LEG BIT23
+ /// MF_EXT_DDJC_EN BIT24
+ /// MF_EXT_RX_DFE_EN BIT25
+ /// MF_EXT_CSCLK_EN BIT26
+ /// MF_EXT_CSCLK_BACKSIDE_EN BIT27
+ /// MF_EXT_CACLK_EN BIT28
+ /// MF_X_OVER_HWFSM_EN BIT29
+ /// MF_EXT_INIT_CMI_EN BIT30
+ /// MF_EXT_QxCA_CLK_EN BIT31
+ // + UINT32 memFlowsExt; + + // + // Addtional storage for memory flows + // + + UINT32 memFlowsExt2; + UINT32 memFlowsExt3; + + /// + /// @brief + /// Write Preamble timing.
+ /// @details + /// 0 =3D PREAMBLE_1TCLK;
+ /// 1 =3D PREAMBLE_2TCLK;
+ /// 2 =3D PREAMBLE_3TCLK;
+ /// 3 =3D PREAMBLE_4TCLK.
+ // + UINT8 writePreamble; + + /// + /// @brief + /// Read Preamble timing.
+ /// @details + /// 0 =3D PREAMBLE_1TCLK;
+ /// 1 =3D PREAMBLE_2TCLK;
+ /// 2 =3D PREAMBLE_3TCLK;
+ /// 3 =3D PREAMBLE_4TCLK.
+ // + UINT8 readPreamble; + + /// + /// Enable extended range for DRAM RAPL. + // + UINT8 DramRaplExtendedRange; + + /// + /// @brief + /// Memory RAS: Threshold value for logging Correctable Errors(CE). + /// @details + /// Threshold of 10 logs 10th CE, "All" logs every CE, and "None" + /// means no CE logging. All and None are not valid with Rank Sparing. + // + UINT16 spareErrTh; + + /// + /// Memory RAS: Enable/Disable New 48B SDDC.
+ // + UINT8 NsddcEn; + + + /// + /// Memory RAS: Enable/Disable enhanced sddc.
+ // + UINT8 EsddcEn; + + /// + /// Disable - Turns ON Column Correction feature. Enable - Turns OFF Col= umn Correction feature + // + UINT8 ColumnCorrectionDisable; + + /// + /// Memory RAS: Enable/Disable leaky bucket time window based interface.=
+ // + UINT8 leakyBktTimeWindow; + + /// + /// Leaky bucket low mask position. + // + UINT8 leakyBktLo; + + /// + /// Leaky bucket high mask position. + // + UINT8 leakyBktHi; + + /// + /// Leaky bucket time window based interface Hour(0 - 3744). + // + UINT16 leakyBktHour; + + /// + /// Leaky bucket time window based interface Minute" (0 - 60). + // + UINT8 leakyBktMinute; + + /// + /// Number of spare ranks per channel. + // + UINT8 spareRanks; + + /// + /// Controls if NVDIMMs are interleaved together or not. + // + UINT8 interNVDIMMS; + + /// + /// Control if BIOS will perform NVDIMM Restore operation. + // + UINT8 restoreNVDIMMS; + + /// + /// Control if BIOS will perform NVDIMM erase & ARM operations. + // + UINT8 eraseArmNVDIMMS; + + /// + /// Cmd setup percent offset for late cmd traning result. The possible + /// values are from 0 to 100. + // + UINT8 cmdSetupPercentOffset; + + /// + /// @brief + /// Memory RAS. Power-up DDR4 Post Package Repair (PPR) type.
+ /// @details + /// 0 - PPR disabled.
+ /// 1 - PPR type hard.
+ /// 2 - PPR type soft.
+ // + UINT8 pprType; + + /// + /// @brief + /// PPR Address. + /// @details + /// Buffer to hold DRAM Address that need to be repaired by PPR (Post Pa= ckage Repair).
+ /// Platform Sample Implementation:
+ /// RAS code uses pprAddrSetup to cause MRC to launch PPR (Post Package = Repair) on + /// a subsequent boot. RAS code passes failed DRAM information into pprA= ddrSetup + /// via the UEFI variable PPR_ADDR_VARIABLE. + // + PPR_ADDR_MRC_SETUP pprAddrSetup[MAX_PPR_ADDR_ENTRIES]; + + /// + /// IMC interleave setting (within a socket). Valid options are 1 or 2 w= ay interleave. + // + UINT8 imcInter; + + /// + /// Enable/Disable support for JEDEC RCD v2.0+ One Rank Timing Mode. + // + UINT8 oneRankTimingModeEn; + + struct ReservedS193 ReservedS193; + + /// + /// @brief + /// Volatile Memory Mode + /// @details + /// 0 - 1LM;
+ /// 1 - 2LM;
+ // + UINT8 volMemMode; + + /// + /// For 2LM, the caching type. Only valid if volMemMode is 2LM + /// 0 - DDR caching DDRT. + // + UINT8 CacheMemType; + + /// + /// @brief + /// Size of channel DDR to use as 2LM cache. + /// @details + /// Size of channel DDR to use as 2LM cache when Volatile Memory Mode + /// under Crystal Ridge is 1LM+2LM. + // + UINT8 DdrCacheSize; + + /// + /// Caching contorl for AppDirect. + // + UINT8 PmemCaching; + + /// + /// eADR support. + // + UINT8 EadrSupport; + UINT8 EadrCacheFlushMode; + + /// + /// Enable or disable fADR support. + // + UINT8 FadrSupport; + + /// + /// Memory interleave mode for 1LM. + // + UINT8 memInterleaveGran1LM; + + /// + /// Enable or disable biased 2-way near memory cache. + // + UINT8 EnableTwoWayNmCache; + + /// + /// A 10-bit mask to control the bias counter ratio. + // + UINT16 NonPreferredWayMask; + + /// + /// Reads are issued to the non-preferred or preferred way first. + // + UINT8 PreferredReadFirst; + + /// + /// Enable or disable boot-time fast zero memory support. + // + UINT8 FastZeroMemSupport; + + /// + /// Enable/Disable DDRT memory power saving. + // + UINT8 DdrtMemPwrSave; + + /// + /// @brief + /// Memory RAS: Patrol Scrub Address Mode.
+ /// @details + /// Selects the address mode between System Physical Address (or) Revers= e Address.
+ /// 0 - PATROL_SCRUB_REVERSE_ADDR,
+ /// 1 - PATROL_SCRUB_SPA,
+ // + UINT8 patrolScrubAddrMode; + + /// + /// @brief + /// Self Refresh control programming. + /// @details + /// Memory power managment feature:
+ /// Select manual or auto programming Self Refresh controls at Load Line= point + /// 0/1/2/3 registers.
+ /// 0 - auto - MRC determines the value;
+ /// 1 - manual - use value from user Setup.
+ // + UINT8 SrefProgramming; + + /// + /// @brief + /// Opportunistic self-refresh setting. + /// @details + /// Memory power managment feature:
+ /// opportunistic self-refresh setting in Self Refresh controls at Load = Line point + /// 0/1/2/3 registers.
+ /// 0 - disable;
+ /// 1 - enable.
+ // + UINT8 OppSrefEn; + + /// + /// @brief + /// Master DLLs (MDLL) setting. + /// @details + /// Memory power managment feature:
+ /// Master DLLs (MDLL) setting in Self Refresh controls at Load Line poi= nt 0/1/2/3 registers.
+ /// When 0 - Master DLLs (MDLL) cannot be turned off in Self Refresh.
+ /// When 1 - Master DLLs (MDLL) can be turned off in Self Refresh.
+ // + UINT8 MdllOffEn; + + /// + /// @brief + /// Enables or disables Self Refresh in PkgC flow.
+ /// @details + /// Memory power managment feature.
+ /// 0 - Didable.
+ /// 1 - Enable.
+ // + UINT8 PkgcSrefEn; + + /// + /// @brief + /// Configures CK behavior during self-refresh.
+ /// @details + /// 0 - CK is driven during self refresh.
+ /// 2 - CK is pulled low during self refresh.
+ // + UINT8 CkMode; + + /// + /// @brief + /// CKE Registers Programming Mode. + /// @details + /// Select manual or auto programming registers Control for CKE (DRAM po= werdown modes). + /// at Load Line point 0/1/23.
+ /// 0 - auto - MRC determines the value.
+ /// 1 - manual - use value from user Setup.
+ // + UINT8 CkeProgramming; + + /// + /// @brief + /// CKE Idle Timer. + /// @details + /// Set the number of rank idle cycles that causes CKE power-down entra= nce. + /// The number of idle cycles (in DCLKs) are based from command CS asser= tion. + /// It is important to program this parameter to be greater than roundtr= ip + /// latency parameter in order to avoid the CKE de-assertion sooner than= data return. + // + UINT8 CkeIdleTimer; + + /// + /// @brief + /// CKE Active Power Down Mode for DDR4 DIMMs.
+ /// @details + /// 0 =3D APD is disabled.
+ /// 1 =3D APD is enabled.
+ // + UINT8 ApdEn; + + /// + /// @brief + /// CKE Precharge Power Down (PPD).
+ /// @details + /// 0 =3D PPD is disabled.
+ /// 1 =3D PPD is enabled.
+ // + UINT8 PpdEn; + + /// + /// @brief + /// CKE Active Power Down Mode for DDR-T DIMMs.
+ /// @details + /// 0 =3D APD is disabled.
+ /// 1 =3D APD is enabled.
+ // + UINT8 DdrtCkeEn; + + /// + /// @brief + /// Turn off DDRIO data DLL in CKE Power Down or OppSR low power mode. + /// @details + /// 0 =3D Do not turn off data DLL.
+ /// 1 =3D Turn off data DLL.
+ // + UINT8 DataDllOff; + + /// + /// @brief + /// RAS: Enable/Disable Extended ADDDC sparing.
+ /// @details + /// 0 =3D Disabled.
+ /// 1 =3D Enabled.
+ // + UINT8 ExtendedADDDCEn; + + /// + /// @brief + /// DDRT Defeature Enable/Disable BLOCK GNT2CMD1CYC.
+ /// @details + /// 0 =3D Disabled.
+ /// 1 =3D Enabled.
+ // + UINT8 Blockgnt2cmd1cyc; + + /// + /// @brief + /// Enable/Disable NVMDIMM OPPRD.
+ /// @details + /// 0 =3D DDRT RPQ Reads will not be scheduled in DDR4 mode DDRT Underf= ill Reads + /// will not be scheduled in DDR4 mode.
+ /// 1 =3D DDRT RPQ Reads will be scheduled in DDR4 mode. GNTs continue = to be blocked + /// in DDR4 mode. This should be set for DDRT 2N mode.DDRT Underfil= l Reads will + /// be scheduled in DDR4 mode. GNTs continue to be blocked in DDR4 = mode This + /// bit should be set for DDRT 2N mod.
+ // + UINT8 Disddrtopprd; + + UINT16 Reserved10; + + /// + /// @brief + /// NGNVM DIMM Secure Erase Unit, Erases the persistent memory region of= the selected DIMMs".
+ /// @details + /// 0 - Erase DIMMs according to setting of setSecureEraseSktCh.
+ // 1 - enable Erase All DIMMs, Erases the persistent memory region of= all NVMDIMMs in the system".
+ UINT8 setSecureEraseAllDIMMs; + + /// + /// @brief + /// Enable/Disable secure erase of persistent memory region of NVMDIMM.<= BR> + /// @details + /// 0 =3D Disable erasing the persistent memory region of NVMDIMM in <= Channel 0, Memory controller 0, Socket 0.
+ /// 1 =3D Enable erasing the persistent memory region of NVMDIMM in Ch= annel 0, Memory controller 0, Socket 0.
+ // + UINT8 setSecureEraseSktCh[MAX_SOCKET][MAX_CH]; + + /// + /// @brief + /// Select Crystal Ridge FastGo QoS Configuration Profiles.
+ /// @details + /// CR_FASTGO_DEFAULT 0;
+ /// CR_FASTGO_DISABLE 1;
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_5 2;
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_6 3;
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_8 4;
+ /// CR_FASTGO_DISABLE_MLC_SQ_THRESHOLD_10 5;
+ /// CR_FASTGO_AUTOMATIC 6;
+ /// CR_FASTGO_LAST_OPTION CR_FASTGO_AUTOMATIC;
+ /// CR_FASTGO_KNOB_DEFAULT CR_FASTGO_AUTOMATIC.
+ // + UINT8 FastGoConfig; + + /// + /// @brief + /// Non-Volatile Memory DIMM baseline performance settings depending on = the workload behavior.
+ /// @details + /// 0 =3D BW Optimized.
+ /// 1 =3D Latency Optimized.
+ // + UINT8 NvmdimmPerfConfig; + + /// + /// @brief + /// Memory topology of each channel per socket.
+ /// @details + /// 0 =3D DaisyChainTopology.
+ /// 1 =3D InvSlotsDaisyChainTopology.
+ /// 2 =3D TTopology.
+ // + EFI_MEMORY_TOPOLOGY_TYPE MemoryTopology[MAX_SOCKET][MAX_CH]; + + /// + /// @brief + /// Memory connector type of each channel per socket.
+ /// @details + /// 0 =3D DimmConnectorPth.
+ /// 1 =3D DimmConnectorSmt.
+ /// 2 =3D DimmConnectorMemoryDown.
+ // + EFI_MEMORY_DIMM_CONNECTOR_TYPE MemoryConnectorType[MAX_SOCKET][MAX_CH]; + + /// + /// @brief + /// Enable/Disable the App Direct Memory Hole.
+ /// @details + /// 0 =3D disable.
+ /// 1 =3D enable.
+ // + UINT8 AppDirectMemoryHole; + + /// + /// @brief + /// Enable/disable Latch System Shutdown (LSS) of all enabled NVDIMMs. + /// @details + /// LSS is supposed to be done by the persistent memory driver in OS usi= ng ACPI DSM function, + /// before any write to persistent memory is done. BIOS knob is implemen= ted to enable Latch LSS + /// for operating systems that would not call DSM. Enabling latch twice = is not a problem so the BIOS + /// action does not colide with OSes that use DSM to enable latch.
+ /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 LatchSystemShutdownState; + + /// + /// @brief + /// Select snoopy mode for 2LM. + /// @details + /// Set to 0 to Enables new 2LM specific feature to + /// avoid directory updates to far-memory from non-NUMA optimized worklo= ads.
+ /// 0 =3D Enable eliminating directory in far memory.
+ /// 1 =3D Disable eliminating directory in far memory.
+ // + UINT8 EliminateDirectoryInFarMemory; + + /// + /// @brief + /// Power Cycle Policy on NVM Surprise Clock Stop. + /// @details + /// Enable/Disable power cycle policy when NVMDIMM receive surprise cloc= k stop. + // + UINT8 NvmdimmPowerCyclePolicy; + + /// + /// @brief + /// NV DIMM Energy Policy Management.
+ /// @details + /// 1 =3D Setting Energy Policy to Device Managed.
+ /// 2 =3D Setting Energy Policy to Host Managed.
+ // + UINT8 NvDimmEnergyPolicy; + + /// + /// @brief + /// Option to force Rx DFE enabled or disabled.
+ /// @details + /// 0 =3D Disable Rx DFE.
+ /// 1 =3D Enable Rx DFE.
+ /// 2 =3D Auto. MRC code detemines if enable or disable.
+ // + UINT8 RxDfeEn; + + /// + /// @brief + /// Enable/Disable TX Rise Fall Slew Rate Training.
+ /// @details + /// 0 =3D Dsiable.
+ /// 1 =3D Enable.
+ /// 2 =3D AUTO, will enable if DDR Freq >=3D 2933.
+ // + UINT8 TxRiseFallSlewRate; + + /// + /// @brief + /// Forces PXC (Phase-based Crosstalk Cancellation) initialization. + /// @details + /// Forces PXC (Phase-based Crosstalk Cancellation) initialization even = if + /// PXC training is not enabled.
+ /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 ForcePxcInit; + + /// + /// @brief + /// CMI Initialize Option.
+ /// @details + /// 0 =3D Initialize with desired credit.
+ /// 1 =3D Inialize with default(Reset Value)credit.
+ // + UINT8 CmiInitOption; + + /// + /// @brief + /// Snoopy mode for AD. + /// @details + /// Snoopy mode for AD: Disable/Enable new AD specific feature to avoid = directory + /// updates to DDRT memory from non-NUMA optimized workloads.
+ /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 DisableDirForAppDirect; + + /// + /// @brief + /// Enable/Disable Crystal Ridge MediaStatus Exception.
+ /// @details + /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 NvmMediaStatusException; + + /// + /// @brief + /// Select Crystal Ridge QoS tuning recipes.
+ /// @details + /// 0 =3D Enables tuning recipe 1 for CR QoS knobs
+ /// (recommended for 2-2-2 memory configuration in AD);
+ /// 1 =3D Enables tuning recipe 2 for CR QoS knobs
+ /// (recommended for other memory configuration in AD);
+ /// 2 =3D Enables tuning recipe 3 for CR QoS knobs
+ /// (recommended for 1 DIMM per channel config);
+ /// 3 =3D Disable CR QoS feature.
+ // + UINT8 NvmQos; + + /// + /// @brief + /// Disable/Enable using extended Type 17 SMBIOS Structures.
+ /// @details + /// 0 =3D Disable.
+ /// 1 =3D Enable .
+ // + UINT8 ExtendedType17; + + /// + /// @brief + /// Gen 2 Intel Optane DC Persistent Memory (DCPMM) Average Power Limit= (in mW)". + /// @details + /// Valid range for power limit starts from 10000mW and must be a multip= le of 250mW." + // + UINT16 DcpmmAveragePowerLimit; + + /// + /// @brief + /// Gen 2 DCPMM Average Power Time Constant for Turbo Mode support (in m= Sec). + /// @details + /// This value is used as a base time window for power usage measurement= s. + // + UINT8 DcpmmAveragePowerTimeConstant; + + + /// + /// @brief + /// Gen 2 DCPMM Average Power Time Constant for Memory Bandwidth Boost F= eature support(in mSec). + /// @details + /// This value is used as a base time window for power usage measurement= s. + // + UINT32 DcpmmMbbAveragePowerTimeConstant; + + /// + /// @brief + /// Gen 2 DCPMM Turbo Mode/Memory Bandwidth Boost Feature Enable.
+ /// @details + /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 DcpmmMbbFeature; + + /// + /// @brief + /// DCPPM Power limit in mW for Turbo Mode/Memory Bandwidth Boost Featu= re. + /// @details + /// DCPPM Power limit in mW used for limiting the Turbo Mode/Memory Band= width Boost power consumption (Valid + /// range starts from 15000mW). + // + UINT16 DcpmmMbbMaxPowerLimit; + + /// + /// @brief + /// Select LSx (LSI/LSR/LSW) ACPI method implementation.
+ /// @details + /// 0 =3D Software SMI.
+ /// 1 =3D ASL.
+ // + UINT8 LsxImplementation; + + /// + /// @brief + /// Set Smbus maximum access time
+ /// @details + /// Maximum amount of time (ms) UEFI mgmt driver is allowed to use the S= MBus.
+ // + UINT32 NvdimmSmbusMaxAccessTime; + + /// + /// @brief + /// Set Smbus release delay.
+ /// @details + /// Delay time (ms) before releasing after UEFI mgmt driver requests SMB= us release.
+ // + UINT32 NvdimmSmbusReleaseDelay; + + /// + /// @brief + /// Controls Mailbox structures in the NFIT + /// @details + /// 0 - Publish Mailbox structures in the NFIT + /// 1 - Do not publish Mailbox structures in the NFIT + /// + UINT8 NfitPublishMailboxStructsDisable; + + /// + /// @brief + /// Enforce memory population POR configurations.
+ /// @details + /// 0 (ENFORCE_POPULATION_POR_DIS) - Do not enforce mem= ory population POR.
+ /// 1 (ENFORCE_POPULATION_POR_ENFORCE_SUPPORTED) - Enforce supported = memory populations.
+ /// 2 (ENFORCE_POPULATION_POR_ENFORCE_VALIDATED) - Enforce validated = memory populations.
+ // + UINT8 EnforcePopulationPor; + + /// + /// Configure Stagger Host Refresh feature + /// + UINT8 TrefiPerChannel; + UINT8 TrefiNumofRank; + UINT16 TrefiDelay; + + // + // DFE Path Finding + // + UINT8 EnableTapSweep; + + INT8 DfeGainBias; + + INT8 Tap1Start; + INT8 Tap1End; + UINT8 Tap1Size; + + INT8 Tap2Start; + INT8 Tap2End; + UINT8 Tap2Size; + + INT8 Tap3Start; + INT8 Tap3End; + UINT8 Tap3Size; + + INT8 Tap4Start; + INT8 Tap4End; + UINT8 Tap4Size; + + /// + /// @brief + /// Training Comp Options Values. + /// @details + /// Options for issuing a Comp. cycle (RCOMP) at specific points in trai= ning.
+ /// 0 - One RCOMP cycle only on PHY Init (MMRC Init);
+ /// 1 - One RCOMP cycle after every JEDEC Init;
+ /// 2 - One RCOMP cycle right before every training step;
+ // + UINT8 TrainingCompOptions; + + /// + /// @brief + /// Periodic Rcomp Control. + /// @details + /// Enable/Disable memory periodic Rcomp with PCU.
+ /// 0 - Disable;
+ /// 1 - Enable;
+ /// 2 - Auto;
+ // + UINT8 PeriodicRcomp; + + /// + /// @brief + /// Periodic Rcomp Interval. + /// @details + /// Interval of periodic Rcomp controlled by PCU.
+ // + UINT8 PeriodicRcompInterval; + + /// + /// @brief + /// Use SMBUS for early MRW commands + /// @details + /// Option to require all MRW commands to be sent over SMBUS until QCA t= raining is complete
+ // + BOOLEAN UseSmbusForMrwEarly; + + /// + /// @brief + /// Enable/Disable AEP DIMM Not Supported Exception.
+ /// @details + /// 0 =3D Disable.
+ /// 1 =3D Enable.
+ // + UINT8 AepNotSupportedException; + + // + // Memory Boot Health Check + // + MEM_BOOT_HEALTH_CONFIG MemBootHealthConfig; + + /// @brief + /// Select between Panic/High Watermark of Auto or High or Low.
+ /// @details + /// 0 =3D Auto + /// 1 =3D High
+ /// 2 =3D Low
+ UINT8 PanicWm; + + /// @brief + /// Enable/Disable LRDIMM DB DFE.
+ /// @details + /// 0 - Disable;
+ /// 1 - Pmem Only;
+ /// 2 - All LRDIMM;
+ UINT8 DataBufferDfe; + + /// + /// @brief + /// Enable/Disable Virtual NUMA.
+ /// @details + /// 0 - disable.
+ /// 1 - enable.
+ // + UINT8 VirtualNumaEnable; + + /// + /// @brief + /// Smart Test Key pattern.
+ /// @details + /// Option to enter the confidential key to be used
+ // + UINT32 smartTestKey; + + /// + /// Enable RMT minimum margin check + // + BOOLEAN RmtMinimumMarginCheckEnable; +}; // memSetup + +/// +/// Common Platform Settings of MRC. +/// +struct commonSetup { + /// + /// @brief + /// Flags for common platform settings.
+ /// @details + /// PROMOTE_WARN_EN BIT0 Enables warnings to be treated as fatal= error.
+ /// PROMOTE_MRC_WARN_EN BIT1 Enables MRC warnings to be treated as f= atal error.
+ /// HALT_ON_ERROR_EN BIT2 Enables errors to loop forever.
+ /// HALT_ON_ERROR_AUTO BIT3 Auto reset with Maximum Serial port deb= ug
+ /// message level when fatal error is encou= ntered.
+ // + UINT32 options; + + /// + /// @brief + /// MRC debug feature. It indicates if debug jumper is set.
+ /// @details + /// 0 - Debug jumper is not set.
+ /// 1 - Debug jumper is set.
+ // + UINT8 debugJumper; + + /// + /// @brief + /// Specifies what level of debug messages will be sent to serial port.<= BR> + /// @details + /// Available options are a bitfield where:
+ /// SDBG_MIN BIT0;
+ /// SDBG_MAX BIT1;
+ /// SDBG_TRACE BIT2;
+ /// SDBG_MEM_TRAIN BIT3 + SDBG_MAX;
+ /// SDBG_CPGC BIT5;
+ /// SDBG_MINMAX SDBG_MIN + SDBG_MAX.
+ // + UINT32 serialDebugMsgLvl; + + /// + /// MRC debug feature: Enable/Disable serial port buffer.
+ // + UINT8 serialBufEnable; + + /// + /// MRC debug feature: Enable/Disable serial port pipe.
+ // + UINT8 serialPipeEnable; + + /// + /// MRC debug feature: Enable/Disable serial pipe compress.
+ // + UINT8 serialPipeCompress; + + /// + /// @brief + /// Maximum addressable memory supported by the platform. + /// @details + /// Skylake Processor supports up to 46-bit addressing. This input shoul= d be the + /// total number of addressable bytes in 256MB units. (0x40000 for 46-bit + /// and 0x1000 for 40-bit). + // + UINT32 maxAddrMem; + + /// + /// User configurable IO port for post code which is traditionally locat= ed at 0x80. + // + UINT16 debugPort; + + /// + /// 32-bit pointer to an optional OEM NVRAM image to be copied into the = host NVRAM structure. + /// + UINT32 nvramPtr; + + /// + /// 32-bit pointer to an optional OEM provided Host structure. + // + UINT32 sysHostBufferPtr; + + /// + /// @brief + /// Disable/Enable DDRT Transcator.
+ /// @details + /// 0 - Disable;
+ /// 1 - Enable;
+ // + UINT8 ddrtXactor; + + UINT8 ReservedS3; + + UINT8 ReservedS7[MAX_B2P_MAILBOX_GROUPS]; + + /// + /// @brief + /// Socktet configuration supported by platform + /// @details + /// 0 - SOCKET_UNDEFINED + /// 1 - SOCKET_4S + /// 2 - SOCKET_HEDT High End Desktop + /// 3 - SOCKET_1S + /// 4 - SOCKET_1SWS 1 Socket Work Station + /// 5 - SOCKET_8S + /// 6 - SOCKET_2S + // + UINT8 SocketConfig; +}; + +/// +/// Platform Setting for MRC. +// +typedef struct sysSetup { + + /// + /// Memory technology related settings for MRC. + // + struct memSetup mem; + + /// + /// Common platform settings not related to memory techology. + // + struct commonSetup common; + + /// + /// @brief + /// WFR Uncore GV Rate Reduction.
+ /// @details + /// AUTO: Enable if WFR socket is detected in system.
+ /// Enabled: Always enables WFR Uncore GV Rate Reduction.
+ // + UINT8 WFRWAEnable; + + /// + /// Enable/Disable Pmax through BIOS to Pcode Mailbox. + // + UINT8 PmaxDisable; + + UINT8 Pci64BitResourceAllocation; // TODO - This is IIO related, they ne= ed to stop relying on MRC structures + + + /// + /// Whether of not we should recover from ADR. + // + + UINT32 AdrEvent; + +} SYS_SETUP; + +#pragma pack(pop) + +/// +/// Revison of MEMORY_POLICY_PPI. +// +#define MEMORY_POLICY_PPI_REVISION 0x00000001 + +/// +/// Memory Policy PPI Definition. +// +typedef struct _MEMORY_POLICY_PPI { + + /// + /// Revision of this PPI. + // + UINT32 Revision; + + /// + /// This data structure contanis all platform level configuration for MR= C. + // + SYS_SETUP *SysSetup; +} MEMORY_POLICY_PPI; + +extern EFI_GUID gMemoryPolicyPpiGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h new file mode 100644 index 0000000000..82725bc84e --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h @@ -0,0 +1,53 @@ +/** @file + RAS IMC S3 Data Load PPI + + @copyright + Copyright 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _RAS_IMC_S3_DATA_H_ +#define _RAS_IMC_S3_DATA_H_ + +#include + +typedef struct _RAS_IMC_S3_DATA_PPI RAS_IMC_S3_DATA_PPI; + +/** + Retrieves data for S3 saved memory RAS features from non-volatile storag= e. + + If the Data buffer is too small to hold the contents of the NVS data, + the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the + required buffer size to obtain the data. + + @param[in] This A pointer to this instance of th= e RAS_IMC_S3_DATA_PPI. + @param[in, out] DataSize On entry, points to the size in = bytes of the Data buffer. + On return, points to the size of= the data returned in Data. + @param[out] Data Points to the buffer which will = hold the returned data. + + @retval EFI_SUCCESS The NVS data was read successful= ly. + @retval EFI_NOT_FOUND The NVS data does not exist. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for th= e NVS data. + DataSize is updated with the siz= e required for + the NVS data. + @retval EFI_INVALID_PARAMETER DataSize or Data is NULL. + @retval EFI_DEVICE_ERROR The NVS data could not be retrie= ved because of a device error. + @retval EFI_UNSUPPORTED This platform does not support t= he save/restore of S3 memory data + +**/ +typedef +EFI_STATUS +(EFIAPI *RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA) ( + IN CONST RAS_IMC_S3_DATA_PPI *This, + IN OUT UINT32 *DataSize, + OUT VOID *Data + ); + +struct _RAS_IMC_S3_DATA_PPI { + RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData; +}; + +extern EFI_GUID gRasImcS3DataPpiGuid; + +#endif // _RAS_IMC_S3_DATA_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h new file mode 100644 index 0000000000..e355dcaba3 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h @@ -0,0 +1,39 @@ +/** @file + Silicon Policy PPI is used for specifying platform + related Intel silicon information and policy setting. + This PPI is consumed by the silicon PEI modules and carried + over to silicon DXE modules. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UPI_POLICY_PPI_H_ +#define _UPI_POLICY_PPI_H_ + +#include + +/// +/// PPI revision information +/// This PPI will be extended in a backwards compatible manner over time +/// Added interfaces should be documented here with the revisions added +/// Revision 1: Initial revision +#define UPI_POLICY_PPI_REVISION 0x1 + +typedef struct _UPI_POLICY_PPI UPI_POLICY_PPI; + +struct _UPI_POLICY_PPI { + /** + This member specifies the revision of the UPI_POLICY_PPI. This field i= s used to + indicate backwards compatible changes to the INTERFACE. Platform code = that produces + this INTERFACE must fill with the correct revision value for UPI code + to correctly interpret the content of the INTERFACE fields. + **/ + UINT32 Revision; + KTI_HOST_IN Upi; +}; + +#endif // _UPI_POLICY_PPI_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibr= aryProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiL= ibraryProtocol.h new file mode 100644 index 0000000000..df8317937f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProt= ocol.h @@ -0,0 +1,252 @@ +/** @file + Dynamic link silicon library service access Protocol + + This protocol abstracts silicon static library accesses via a protocol + + @copyright + Copyright 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DYNAMIC_SI_LIBARY_PROTOCOL_H_ +#define _DYNAMIC_SI_LIBARY_PROTOCOL_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define DYNAMIC_SI_LIBARY_PROTOCOL_GUID \ + { 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b= , 0x7e } } + +#define DYNAMIC_SI_LIBARY_PROTOCOL_SIGNATURE SIGNATURE_32('D', 'S', 'L', = 'P') +#define DYNAMIC_SI_LIBARY_PROTOCOL_VERSION 0x01 + +// +// Functions +// + +typedef +EFI_STATUS +(EFIAPI *DXE_SET_GPIO_OUTPUT_VALUE) ( + IN UINT32 GPioPad, + IN UINT32 Value + ); + +typedef +BOOLEAN +(EFIAPI *DXE_IsCpuAndRevision) ( + IN UINT8 CpuType, + IN UINT16 Revision + ); + +typedef +CPU_VAR_DATA * +(EFIAPI *DXE_GetCpuVarData) ( + ); + +typedef +UINT8 +(EFIAPI *DXE_MaxSataControllerNum) ( + VOID + ); + +typedef +UINTN +(EFIAPI *DXE_MmPciBase) ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function + ); + +typedef +CPU_CSR_ACCESS_VAR * +(EFIAPI *DXE_GetSysCpuCsrAccessVar) ( + VOID + ); + +typedef +VOID +(EFIAPI *DXE_IioPciHookBeforeEnumeration) ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 DidVid + ); + +typedef +CHAR8* +(EFIAPI *DXE_PchGetSeriesStr) ( + ); + +typedef +EFI_STATUS +(EFIAPI *DXE_PchGetSteppingStr) ( + OUT CHAR8 *Buffer, + IN UINT32 BufferSize + ); + +typedef +CHAR8* +(EFIAPI *DXE_PchGetSkuStr) ( + VOID + ); + +typedef +EFI_STATUS +(EFIAPI *DXE_SaveVariableFromHob) ( + IN EFI_GUID HobGuid, + IN CHAR16 *VariableName, + IN EFI_GUID VariableGuid + ); + +typedef +VOID +(EFIAPI *DXE_SetColdBootSlowRequired) ( + IN BOOLEAN ColdBootSlowRequired + ); + +typedef +SYS_INFO_VAR_NVRAM * +(EFIAPI *DXE_GetSysInfoVarNvramPtr) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *DXE_HybridSystemLevelEmulationEnabled) ( + VOID + ); + +typedef +SYSTEM_MEMORY_MAP_HOB * +(EFIAPI *DXE_GetSystemMemoryMapData) ( + VOID + ); + +typedef +BOOLEAN +(EFIAPI *DXE_X2ApicIdDetect) ( + IN VOID *Host + ); + +typedef +RETURN_STATUS +(EFIAPI *DXE_RegisterRead) ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +typedef +RETURN_STATUS +(EFIAPI *DXE_RegisterWrite) ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +typedef +UINT8 +(EFIAPI *DXE_SataDevNumber) ( + IN UINT32 SataCtrlIndex + ); + +typedef +UINT8 +(EFIAPI *DXE_SataFuncNumber) ( + IN UINT32 SataCtrlIndex + ); + +typedef +UINT16 +(EFIAPI *DXE_PmcGetAcpiBase) ( + VOID + ); + +typedef +UINTN +(EFIAPI *DXE_PchGetPmcBaseByPchId) ( + IN UINT8 PchId + ); + +typedef +VOID +(EFIAPI *DXE_SetBiosInfoFlagWpe) ( + VOID + ); + +typedef +VOID +(EFIAPI *DXE_ProgramGenProtRangeRegs) ( + IIO_UDS *IioUds + ); + +typedef +VOID +(EFIAPI *DXE_ProgramImrRegs) ( + IIO_UDS *IioUds + ); + +typedef +VOID +(EFIAPI *DXE_ProgramImr2Regs) ( + IIO_UDS *IioUds + ); + +typedef +VOID +(EFIAPI *DXE_CheckAndPopulateIedTraceMemory) ( + UINTN IedTraceSize, + IIO_UDS *IioUds + ); + +typedef +UINT32 +(EFIAPI *DXE_ReadScratchpad7) ( + VOID + ); + +// +// UBA specific silicon abstraction protocol +// +typedef struct { + UINT32 Signature; + UINT32 Version; + + DXE_GetCpuVarData GetCpuVarData; + DXE_IsCpuAndRevision IsCpuAndRevision; + DXE_MaxSataControllerNum MaxSataControllerNum; + DXE_MmPciBase MmPciBase; + DXE_GetSysCpuCsrAccessVar GetSysCpuCsrAccessVar; + DXE_IioPciHookBeforeEnumeration IioPciHookBeforeEnumeration; + DXE_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue; + DXE_PchGetSeriesStr PchGetSeriesStr; + DXE_PchGetSteppingStr PchGetSteppingStr; + DXE_PchGetSkuStr PchGetSkuStr; + DXE_SaveVariableFromHob SaveVariableFromHob; + DXE_SetColdBootSlowRequired SetColdBootSlowRequired; + DXE_GetSysInfoVarNvramPtr GetSysInfoVarNvramPtr; + DXE_X2ApicIdDetect X2ApicIdDetect; + DXE_GetSystemMemoryMapData GetSystemMemoryMapData; + DXE_RegisterRead RegisterRead; + DXE_RegisterWrite RegisterWrite; + DXE_HybridSystemLevelEmulationEnabled HybridSystemLevelEmulationEnable= d; + DXE_SataDevNumber SataDevNumber; + DXE_SataFuncNumber SataFuncNumber; + DXE_PmcGetAcpiBase PmcGetAcpiBase; + DXE_PchGetPmcBaseByPchId PchGetPmcBaseByPchId; + DXE_SetBiosInfoFlagWpe SetBiosInfoFlagWpe; + DXE_ProgramGenProtRangeRegs ProgramGenProtRangeRegs; + DXE_ProgramImrRegs ProgramImrRegs; + DXE_ProgramImr2Regs ProgramImr2Regs; + DXE_CheckAndPopulateIedTraceMemory CheckAndPopulateIedTraceMemory; + DXE_ReadScratchpad7 ReadScratchpad7; +} DYNAMIC_SI_LIBARY_PROTOCOL; + +extern EFI_GUID gDynamicSiLibraryProtocolGuid; + +#endif // _DYNAMIC_SI_LIBARY_PROTOCOL_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibr= arySmmProtocol.h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/Dynamic= SiLibrarySmmProtocol.h new file mode 100644 index 0000000000..53bf977d31 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmP= rotocol.h @@ -0,0 +1,60 @@ +/** @file + Dynamic link silicon library service access Protocol + + This protocol abstracts silicon static library accesses via an SMM proto= col + + @copyright + Copyright 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_ +#define _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_ + + +#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_GUID \ + { 0xb235fbed, 0x3b25, 0x4cb3, { 0x98, 0x9c, 0x8c, 0xe7, 0xec, 0x49, 0x8b= , 0x7e } } + +#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_SIGNATURE SIGNATURE_32('D', 'S', '= L', 'S') +#define DYNAMIC_SI_LIBARY_SMM_PROTOCOL_VERSION 0x01 + +// +// Functions +// + +typedef +UINTN +(EFIAPI *SMM_MmPciBase) ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function + ); + +typedef +UINT16 +(EFIAPI *SMM_PmcGetAcpiBase) ( + VOID + ); + +typedef +UINTN +(EFIAPI *SMM_PchGetPmcBaseByPchId) ( + IN UINT8 PchId + ); + +// +// UBA specific silicon abstraction protocol +// +typedef struct { + UINT32 Signature; + UINT32 Version; + + SMM_MmPciBase MmPciBase; + SMM_PmcGetAcpiBase PmcGetAcpiBase; + SMM_PchGetPmcBaseByPchId PchGetPmcBaseByPchId; +} DYNAMIC_SI_LIBARY_SMM_PROTOCOL; + +extern EFI_GUID gDynamicSiLibrarySmmProtocolGuid; + +#endif // _DYNAMIC_SI_LIBARY_SMM_PROTOCOL_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h new file mode 100644 index 0000000000..b5b51d4799 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h @@ -0,0 +1,212 @@ +/** @file + Definition of the global NVS area protocol. This protocol + publishes the address and format of a global ACPI NVS buffer used as a c= ommunications + buffer between SMM code and ASL code. + Note: Data structures defined in this protocol are not naturally aligne= d. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_GLOBAL_NVS_AREA_H_ +#define _EFI_GLOBAL_NVS_AREA_H_ + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID { 0x74e1e48, 0x8132, 0x47a1, 0x8= c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } +// +// Because of ASL constrains cannot use MAX_SOCKET and MAX_LOGIC_IIO_STACK= to configure ACPI objects. The symbols +// below are the largest values of MAX_SOCKET or MAX_LOGIC_IIO_STACK curre= ntly supported in BiosParameterRegion.asi. +// +#define NVS_MAX_SOCKETS 8 +#define NVS_MAX_LOGIC_IIO_STACKS 14 + +#if NVS_MAX_SOCKETS < MAX_SOCKET +#error "Must update NVS_MAX_SOCKETS and BiosParameterRegion.asi to handle = so many sockets" +#endif +#if NVS_MAX_LOGIC_IIO_STACKS < MAX_LOGIC_IIO_STACK +#error "Must update NVS_MAX_LOGIC_IIO_STACKS and BiosParameterRegion.asi t= o handle so many stacks" +#endif + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +// +// Global NVS Area definition +// BIOS parameters region provided by POST code to ASL, defined as PSYS in= BiosParametersRegion.asi +// +#pragma pack (1) + +typedef struct { + // IOAPIC Start + UINT32 PlatformId; + UINT64 IoApicEnable; + UINT8 ApicIdOverrided :1; + UINT8 PchIoApic_24_119 :1; + UINT8 Cpx4Detect :1; + UINT8 Reserved0 :5; + // IOAPIC End + + // Power Management Start + UINT8 TpmEnable :1; + UINT8 CStateEnable :1; + UINT8 C3Enable :1; + UINT8 C6Enable :1; + UINT8 C7Enable :1; + UINT8 MonitorMwaitEnable :1; + UINT8 PStateEnable :1; + UINT8 EmcaEn :1; + UINT8 HWAllEnable :2; + UINT8 KBPresent :1; + UINT8 MousePresent :1; + UINT8 TStateEnable :1; + UINT8 TStateFineGrained :1; + UINT8 OSCX :1; + UINT8 Reserved1 :1; + // Power Management End + + // RAS Start + UINT8 CpuChangeMask; + UINT8 IioChangeMask; + UINT16 IioPresentBitMask[NVS_MAX_SOCKETS]; + UINT32 SocketBitMask; // make sure this is at 4by= te boundary + UINT8 CpuCoreThreadsCount; + UINT32 ProcessorApicIdBase[NVS_MAX_SOCKETS]; + UINT64 ProcessorBitMask[NVS_MAX_SOCKETS]; // cores 0-63 for each sock= et + UINT64 ProcessorBitMaskHi[NVS_MAX_SOCKETS]; // cores 64-127 for each so= cket + UINT32 MmCfg; + UINT32 TsegSize; + UINT32 SmiRequestParam[4]; + UINT32 SciRequestParam[4]; + UINT64 MigrationActionRegionAddress; + UINT8 Cpu0Uuid[16]; + UINT8 Cpu1Uuid[16]; + UINT8 Cpu2Uuid[16]; + UINT8 Cpu3Uuid[16]; + UINT8 Cpu4Uuid[16]; + UINT8 Cpu5Uuid[16]; + UINT8 Cpu6Uuid[16]; + UINT8 Cpu7Uuid[16]; + UINT8 CpuSpareMask; + UINT8 Mem0Uuid[16]; + UINT8 Mem1Uuid[16]; + UINT8 Mem2Uuid[16]; + UINT8 Mem3Uuid[16]; + UINT8 Mem4Uuid[16]; + UINT8 Mem5Uuid[16]; + UINT8 Mem6Uuid[16]; + UINT8 Mem7Uuid[16]; + UINT8 Mem8Uuid[16]; + UINT8 Mem9Uuid[16]; + UINT8 Mem10Uuid[16]; + UINT8 Mem11Uuid[16]; + UINT8 Mem12Uuid[16]; + UINT8 Mem13Uuid[16]; + UINT8 Mem14Uuid[16]; + UINT8 Mem15Uuid[16]; + UINT64 EmcaL1DirAddr; + UINT32 ProcessorId; + UINT8 PcieAcpiHotPlugEnable; + UINT8 WheaEnabled; + UINT8 WheaSci; + UINT8 PropagateSerrOption; + UINT8 PropagatePerrOption; + // RAS End + + // VTD Start + UINT64 DrhdAddr[3]; + UINT64 AtsrAddr[3]; + UINT64 RhsaAddr[3]; + // VTD End + + // SR-IOV WA Start + UINT8 WmaaSICaseValue; + UINT16 WmaaSISeg; + UINT8 WmaaSIBus; + UINT8 WmaaSIDevice; + UINT8 WmaaSIFunction; + UINT8 WmaaSISts; + UINT8 WheaSupportEn; + // SR-IOV End + + // BIOS Guard Start + UINT64 BiosGuardMemAddress; + UINT8 BiosGuardMemSize; + UINT16 BiosGuardIoTrapAddress; + UINT8 CpuSkuNumOfBitShift; + // BIOS Guard End + + // USB3 Start + UINT8 XhciMode; + UINT8 HostAlertVector1; + UINT8 HostAlertVector2; + // USB3 End + + // HWPM Start + UINT8 HWPMEnable :2; // HWPM + UINT8 Reserved3 :1; // reserved bit + UINT8 HwpInterrupt :1; // HWP Interrupt + UINT8 Reserved2 :4; // reserved bits + // HWPM End + + // SGX Start + UINT8 SgxStatus; + UINT64 EpcLength[8]; // MAX_IMC * MAX_SOCKET + UINT64 EpcBaseAddress[8]; // MAX_IMC * MAX_SOCKET + // SGX End + + // PCIe Multi-Seg Start + UINT8 BusBase[NVS_MAX_SOCKETS][NVS_MAX_LOGIC_IIO_STACKS]; // PCI bus b= ase number for each stack + UINT8 PcieMultiSegSupport; // Enable /Disable switch + UINT8 PcieSegNum[NVS_MAX_SOCKETS]; // PCI segment number array for eac= h socket + // PCIe Multi-seg end + + UINT8 SncAnd2Cluster; // 0 - SNC disabled, 2 - SNC enabled (2 = clusters), 4 - SNC enabled (4 clusters) + + // XTU Start + UINT32 XTUBaseAddress; // 193 XTU Base Address + UINT32 XTUSize; // 197 XTU Entries Size + UINT32 XMPBaseAddress; // 201 XTU Base Address + UINT8 DDRReferenceFreq; // 205 DDR Reference Frequency + UINT8 Rtd3Support; // 206 Runtime D3 support. + UINT8 Rtd3P0dl; // 207 User selctable Delay for Device D= 0 transition. + UINT8 Rtd3P3dl; // 208 User selctable Delay for Device D= 0 transition. + // XTU End + + // FPGA Root Port Bus + UINT8 FpgaBusBase[8]; + UINT8 FpgaBusLimit[8]; + + // FPGA present bit + UINT8 FpgaPresent[8]; + + // FPGA Resource Allocation + UINT32 VFPBMemBase[8]; + UINT32 VFPBMemLimit[8]; + + // FPGA KTI present bitmap + UINT32 FpgaKtiPresent; + // FPGA Bus for KTI + UINT8 FpgaKtiBase[8]; + + UINT16 PmBase; // ACPI IO Base Address + UINT8 DebugModeIndicator; // Debug Mode Indicator + UINT8 IioPcieRpCapOffset; // IIO PCIe root port PCIe Capability o= ffset + UINT8 ArtTscLinkFlag; // Flag to indicate if TSC is linked to= ART +} BIOS_ACPI_PARAM; + +#pragma pack () + +// +// Global NVS Area Protocol +// +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + BIOS_ACPI_PARAM *Area; +} EFI_GLOBAL_NVS_AREA_PROTOCOL; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h b/Si= licon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h new file mode 100644 index 0000000000..9efb4466f1 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h @@ -0,0 +1,47 @@ +/** @file + This protocol provides access to the Ioh Universal Data Structure + This protocol is EFI compatible. + + @copyright + Copyright 2005 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_IIO_UDS_PROTOCOL_H_ +#define _EFI_IIO_UDS_PROTOCOL_H_ + +#include + +#define EFI_IIO_UDS_PROTOCOL_GUID \ + { 0xa7ced760, 0xc71c, 0x4e1a, 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, = 0xcb } + +typedef struct _EFI_IIO_UDS_PROTOCOL EFI_IIO_UDS_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *IIH_ENABLE_VC) ( + IN EFI_IIO_UDS_PROTOCOL *This, + IN UINT32 VcCtrlData + ); +/** + + Enables the requested VC in IIO + + @param This Pointer to the EFI_IOH_UDS_PROTOCOL insta= nce. + @param VcCtrlData Data read from VC resourse control reg. + +**/ + + +typedef struct _EFI_IIO_UDS_PROTOCOL { + IIO_UDS *IioUdsPtr; + IIH_ENABLE_VC EnableVc; +} EFI_IIO_UDS_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiIioUdsProtocolGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h= b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h new file mode 100644 index 0000000000..a782bc3a1e --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h @@ -0,0 +1,85 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PCI_CALLBACK_H +#define _EFI_PCI_CALLBACK_H + +#include +#include +#include + + +// +// Global Id for PCI callback +// +#define EFI_PCI_CALLBACK_PROTOCOL_GUID \ + { \ + 0x1ca0e202, 0xfe9e, 0x4776, 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0= x06 \ + } + +typedef struct _EFI_PCI_CALLBACK_PROTOCOL EFI_PCI_CALLBACK_PROTOCOL; + +typedef enum { + EfiPciEnumerationDeviceScanning =3D 1, + EfiPciEnumerationBusNumberAssigned =3D 2, + EfiPciEnumerationResourceAssigned =3D 4, +} EFI_PCI_ENUMERATION_PHASE; + +typedef struct { + PCI_TYPE00 PciHeader; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + EFI_CPU_IO2_PROTOCOL *CpuIo; +} EFI_PCI_CALLBACK_CONTEXT; + +typedef +VOID +(EFIAPI *EFI_PCI_CALLBACK_FUNC) ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + IN EFI_PCI_CALLBACK_CONTEXT *Context +); + +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_PCI_CALLBACK) ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase +) +/*++ + +Routine Description: + + Register a callback during PCI bus enumeration + +Arguments: + + This - Protocol instance pointer. + Function - Callback function pointer. + Phase - PCI enumeration phase. + +Returns: + + EFI_SUCCESS - Function has registed successfully + EFI_UNSUPPORTED - The function has been regisered + EFI_InVALID_PARAMETER - The parameter is incorrect + +--*/ +; + +// +// Protocol definition +// +typedef struct _EFI_PCI_CALLBACK_PROTOCOL { + EFI_REGISTER_PCI_CALLBACK RegisterPciCallback; +} EFI_PCI_CALLBACK_PROTOCOL; + +extern EFI_GUID gEfiPciCallbackProtocolGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h b/Silicon/= Intel/WhitleySiliconPkg/Include/RcVersion.h new file mode 100644 index 0000000000..f0b618a65f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h @@ -0,0 +1,23 @@ +/** @file + RC Version header file. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _RC_VERSION_H_ +#define _RC_VERSION_H_ + +/// +/// RC version number structure. +/// +typedef struct { + UINT8 Major; + UINT8 Minor; + UINT8 Revision; + UINT16 BuildNumber; +} RC_VERSION; + +#endif // _RC_VERSION_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h b/Sil= icon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h new file mode 100644 index 0000000000..732a3c2be6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h @@ -0,0 +1,49 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SCRATCHPAD_LIST__ +#define __SCRATCHPAD_LIST__ + +// +// Sticky BIOS Scratchpad 7. This struct contains the bit definitions for= this Scratchpad. +// +// Comments: Reserved for Intel use. +// + +#define BIOS_SCRATCHPAD7_COMPLETION_DELAY_RESET_COUNT_SIZE 2 + +typedef union { + struct { + UINT32 Available : 4; // Bits[3:0] - These bits are = not reserved. + UINT32 EnteredColdResetFlow : 1; // Bits[4:4] - Entered cold re= set flow. + UINT32 CompletedColdResetFlow : 1; // Bits[5:5] - Completed cold = reset flow. + UINT32 CompletionDelayResetCount : BIOS_SCRATCHPAD7_COMPLETION_DELAY_R= ESET_COUNT_SIZE; + // Bits[7:6] - The number of r= esets requested because the calculated + // completion delay was out of= bounds. Only the socket 0 instance of this is + // used. This bitfield is used= with workaround S1409301288. + UINT32 Available1 : 7; // Bits[14:8] - These bits are= not reserved. + UINT32 CompletedWarmResetWA : 1; // Bits[15:15] - Indicates if = the Warm reset WA was done in sec. + UINT32 SbspSocketId : 4; // Bits[19:16] - SBSP socket id + UINT32 PrefetchFailRecovery : 1; // Bits[20:20] - Prefetch fail= ure/recovery. + UINT32 UmaBasedClusteringDowngrade : 2; // Bits[22:21] - Indicate UMA = based clusting downgrade + // 0:default; 1: Quad-> Hemi 2= : Quad-> Disable 3: Hemi-> Disable + UINT32 MarginTestfailure : 1; // Bits[23:23] - This bit is s= et when Margin Test Fails + UINT32 DcuModeSelect : 1; // Bits [24:24] - DCU_MODE sel= ect 0/1: 32KB 8-way no-ECC (hardware default) / + // 16KB 4-way with ECC. + UINT32 DwrBiosStall : 1; // Bits[25:25] - BIOS Stall if= enter DWR. + UINT32 InDwr : 1; // Bits[26:26] - In DWR. + UINT32 FailMemChkFastColdBoot : 1; // Bits[27:27] - Bit set when = setup option "DEBUG INTERFACE" is enabled + UINT32 BistFrbEventLastBoot : 1; // Bits[28:28] - BIST/FRB even= t occured during the last boot. + UINT32 RemoteSocketReleased : 1; // Bits[29:29] - Remote socket= released in LT enabled system. + UINT32 SncFailRecovery : 1; // Bits[30:30] - Snc failure/r= ecovery. + UINT32 AepDimmPresent : 1; // Bits[31:31] - AEP Dimm Pres= ent + } Bits; + UINT32 Data; +} BIOS_SCRATCHPAD7_STRUCT; + +#endif // #ifndef __SCRATCHPAD_LIST__ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h new file mode 100644 index 0000000000..da5a879a03 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h @@ -0,0 +1,53 @@ +/** @file + Header file for the SiliconUpdUpdate.h Library. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SILICON_UPD_UPDATE_H_ +#define _SILICON_UPD_UPDATE_H_ + +#pragma pack(1) +typedef struct { + //For IioPcieConfig + UINT8 Socket; + UINT16 PortIndex; + UINT8 HidePort; + UINT8 DeEmphasis; + UINT8 PortLinkSpeed; + UINT8 MaxPayload; + UINT8 ReservedE; + UINT8 ReservedF; + UINT8 ReservedG; + UINT8 Sris; + UINT8 PcieCommonClock; + //For IIO Ntb + UINT8 NtbIndex; + UINT8 NtbPpd; + UINT8 NtbBarSizeOverride; + UINT8 NtbSplitBar; + UINT8 NtbBarSizeImBar1; + UINT8 NtbBarSizeImBar2; + UINT8 NtbBarSizeImBar2_0; + UINT8 NtbBarSizeImBar2_1; + UINT8 NtbBarSizeEmBarSZ1; + UINT8 NtbBarSizeEmBarSZ2; + UINT8 NtbBarSizeEmBarSZ2_0; + UINT8 NtbBarSizeEmBarSZ2_1; + UINT8 NtbXlinkCtlOverride; +} UPD_IIO_PCIE_PORT_CONFIG; + +// IIO_PCIE_PORT_CONFIG: +// PciePortConfiguration - Pointer to an array of PCIe port configuration = structures as declared above +// NumberOfEntries - Number of elements in the PciePortConfiguration= Array + +typedef struct { + UPD_IIO_PCIE_PORT_CONFIG *ConfigurationTable; + UINT16 NumberOfEntries; +} IIO_PCIE_PORT_CONFIG; +#pragma pack() + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h b/Sili= con/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h new file mode 100644 index 0000000000..3eff6110aa --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h @@ -0,0 +1,93 @@ +/** @file + System Infor Var Hearder File + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SYSTEM_INFO_VAR_INCLUDES__ +#define __SYSTEM_INFO_VAR_INCLUDES__ + +#include +#include +#include + +#define SYS_INFO_NVRAM_VAR_NAME L"InfoVarNvramData" + +#pragma pack (push,1) + +typedef enum BootMode { + NormalBoot =3D 0, // Normal path through RC with full init, mem detect= ion, init, training, etc. + // Some of these MRC specific init routines can be = skipped based on MRC input params + // in addition to the sub-boot type (WarmBoot, Warm= BootFast, etc). + S3Resume =3D 1 // S3 flow through RC. Should do the bare minimum re= quired for S3 + // init and be optimized for speed. +} BootMode; + +// +// This is used to determine what type of die is connected to a UPI link +// +typedef enum { + UpiConnectionTypeCpu, + UpiConnectionTypePcieGen4, + UpiConnectionTypeFpga, + UpiConnectionTypeMax +} UPI_CONNECTION_TYPE; + +typedef struct { + UINT16 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present = stacks per socket + UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack + UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO = stack, if it works as CXL, the mmiol base is RCRBBAR + UINT8 SocketFirstBus[MAX_SOCKET]; + UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only + UINT8 SocketLastBus[MAX_SOCKET]; + UINT8 segmentSocket[MAX_SOCKET]; + UINT8 KtiPortCnt; + UINT32 socketPresentBitMap; + UINT32 SecondaryDieBitMap; + UINT32 FpgaPresentBitMap; + UINT32 mmCfgBase; + UINT32 mmCfgBaseH[MAX_SOCKET]; + UINT32 mmCfgBaseL[MAX_SOCKET]; + UINT8 DdrMaxCh; + UINT8 DdrMaxImc; + UINT8 DdrNumChPerMc; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + MRC_MST MemSsType[MAX_SOCKET]; + UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR]; + UINT8 HbmMaxCh; + UINT8 HbmMaxIoInst; + UINT8 HbmNumChPerMc; + UINT8 HbmNumChPerIo; + UINT32 LastCsrAddress[2]; + UINT32 LastCsrMmioAddr; + UINT8 CsrCachingEnable; + UINT32 LastCsrMcAddress[2]; + UINT32 LastCsrMcMmioPhyAddr; + UINT8 CsrPciBarCachingEnable; + UINT32 LastCsrPciBarAddr[2]; + UINT64 LastCsrPciBarPhyAddr; + UINT32 LastSBPortId[MAX_SOCKET]; + UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET]; + BOOLEAN PostedCsrAccessAllowed; // SW is allowed to us= e posted CSR writes method when TRUE + BOOLEAN PostedWritesEnabled; // All CSR writes use = posted method when TRUE, non-posted when FALSE + BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR = is unavailable when FALSE + BOOLEAN HbmSku; + UINT8 SocketConfig; + UINT8 HcxType[MAX_SOCKET]; +} CPU_CSR_ACCESS_VAR; + +typedef struct { + UINT32 MeRequestedSizeNv; + UINT32 MeRequestedAlignmentNv; + UINT32 IeRequestedSizeNv; + UINT32 IeRequestedAlignmentNv; + UINT8 SbspSocketIdNv; +} SYS_INFO_VAR_NVRAM; + +#pragma pack (pop) + +#endif //#ifndef __SYSTEM_INFO_VAR_INCLUDES__ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h= b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h new file mode 100644 index 0000000000..0ea93e9a78 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h @@ -0,0 +1,111 @@ +/** @file + This file defines common equates. + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UNCORE_COMMON_INCLUDES_H_ +#define _UNCORE_COMMON_INCLUDES_H_ + +#include +#include +#include + +#ifndef V_INTEL_VID +#define V_INTEL_VID 0x8086 +#endif + +#define MAX_PROCESSOR_TSEG 5 + +// CPX CPU steppings/revisions +#ifndef CPX_A0_CPU_STEP +#define CPX_A0_CPU_STEP 0x0A +#endif //#ifdef CPX_A0_CPU_STEP + +#ifndef CPX_A1_CPU_STEP +#define CPX_A1_CPU_STEP 0x0B +#endif //#ifdef CPX_A1_CPU_STEP + +// +// ICX SP CPU steppings +// +#ifndef ICXSP_R0_CPU_STEP +#define ICXSP_R0_CPU_STEP 0x00 +#endif +#ifndef ICXSP_L0_CPU_STEP +#define ICXSP_L0_CPU_STEP 0x04 +#endif +#ifndef ICXSP_C0_CPU_STEP +#define ICXSP_C0_CPU_STEP 0x05 +#endif +#ifndef ICXSP_D0_CPU_STEP +#define ICXSP_D0_CPU_STEP 0x06 +#endif + +#define MAX_DIE 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE *= MAX_SOCKET) + +#ifndef MAX_HA +#define MAX_HA 2 +#endif + +// If you change this, please also update MAX_IMC in Library\ProcMemInit\I= nclude\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_IMC +#define MAX_IMC 2 // Maximum mem= ory controllers per socket +#endif + +// If you change this, please also update MAX_MC_CH in Library\ProcMemInit= \Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_MC_CH +#define MAX_MC_CH 3 // Max number = of channels per MC (3 for EP) +#endif + +// If you change this, please also update MAX_CH in Library\ProcMemInit\In= clude\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\P= latform\Include\MemDefaults.h +#ifndef MAX_CH +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max c= hannels per socket (worst case EP * EX combination =3D 16) +#endif + +// If you change this, please also update MAX_DIMM in Library\ProcMemInit\= Include\MemHostChip.h +#ifndef MAX_DIMM +#define MAX_DIMM 2 // Max DIMM = per channel +#endif + +// If you change this, please also update MC_MAX_NODE in Library\ProcMemIn= it\Include\MemHostChip.h +#ifndef MC_MAX_NODE +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max numbe= r of memory nodes +#endif + +#ifndef TOTAL_CB3_DEVICES +#define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKE= T. Note: this covers up to 8S. +#endif + +#ifndef MaxIIO +#define MaxIIO MAX_SOCKET +#endif + +#ifndef TOTAL_IIO_STACKS +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. = Not reflect architecture but only sysHost structure! +#endif + +#ifndef NUMBER_NTB_PORTS_PER_SOCKET +#define NUMBER_NTB_PORTS_PER_SOCKET 5 +#endif // #ifndef NUMBER_NTB_PORTS_PER_SOCKET + +#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM + #if MaxIIO > 4 + #define MAX_DEVHIDE_REGS_PER_SYSTEM 512 // MAX_DEVHID= E_REGS_PER_SOCKET * MaxIIO + #else + #define MAX_DEVHIDE_REGS_PER_SYSTEM 256 // MAX_DEVHID= E_REGS_PER_SOCKET * MaxIIO + #endif +#endif + +#ifndef MAX_B2P_MAILBOX_GROUPS +#define MAX_B2P_MAILBOX_GROUPS 32 +#endif // !MAX_B2P_MAILBOX_GROUPS + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h b/Silico= n/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h new file mode 100644 index 0000000000..67e0acd2ca --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h @@ -0,0 +1,36 @@ +/** @file + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _KTI_DISCOVERY_H_ +#define _KTI_DISCOVERY_H_ + +#include "DataTypes.h" +#include + +#pragma pack(1) + +// +// Generic Data structure to describe Link Exchange Parameter (LEP) info +// +typedef struct { + UINT32 Valid : 1; ///< TRUE, if the link is valid (i.e tra= ined successfully for low speed, no validation override that disables it) + UINT32 PeerSocId : 3; ///< Socket ID + UINT32 PeerSocType : 2; ///< Socket Type + UINT32 PeerPort : 4; ///< Port of the peer socket + UINT32 DualLink : 1; ///< TRUE, if there is a second link to = the same neighbor + UINT32 TwoSkt3Link : 1; ///< TRUE, if there is a second and thir= d link to the same neighbor + UINT32 TwoSkt4Link : 1; ///< TRUE, if there are 4 links between = 2 sockets + UINT32 DualLinkIndex : 3; ///< Index of the second link that is co= nnected to the same immediate neighbor + UINT32 DisallowRouteThru : 1; ///< TRUE if the link is not allowed to = configure as route through traffic + UINT32 SpokeOfPinwheel : 1; ///< TRUE if the link is chosen as spoke= of pinwheel + UINT32 Rsvd1 : 14; +} KTI_LINK_DATA; + +#pragma pack() + +#endif // _KTI_DISCOVERY_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silico= n/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h new file mode 100644 index 0000000000..cf558b3d34 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h @@ -0,0 +1,304 @@ +/** @file + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// Definition Flag: +// 1. KTI_SW_SIMULATION -> run with KTIRC Simulation +// 2. IA32 -> run with IA32 mode + + +#ifndef _KTI_HOST_H_ +#define _KTI_HOST_H_ + +#include "DataTypes.h" +#include "PlatformHost.h" +#include +#include +#include "MemHostChipCommon.h" + +#pragma pack(1) + +/********************************************************* + KTIRC Host Structure Related +*********************************************************/ + +typedef enum { + KTI_LINK0 =3D 0x0, + KTI_LINK1, + KTI_LINK2, + KTI_LINK3, + KTI_LINK4, + KTI_LINK5 +} KTI_LOGIC_LINK; + +typedef struct { + + UINT8 Reserved1; + UINT8 Reserved2; + UINT8 Reserved3; + UINT8 Reserved4; + UINT8 Reserved5; + UINT8 Reserved6; + UINT8 Reserved7; + UINT8 Reserved8; + UINT8 Reserved9; + UINT8 Reserved10; + UINT8 Reserved11; + UINT8 Reserved12; + UINT8 Reserved13; + UINT8 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + UINT8 Reserved19; + UINT8 Reserved20; + UINT8 Reserved21; + UINT8 Reserved22; + UINT8 Reserved23; + UINT8 Reserved24; + UINT8 Reserved25; + UINT8 Reserved26; + UINT8 Reserved27; + UINT8 Reserved28; + UINT8 Reserved29; + + UINT8 Reserved30; + UINT8 Reserved31; + UINT8 Reserved32; + UINT8 Reserved33; + UINT8 Reserved34; + UINT8 Reserved35; + UINT8 Reserved36; + UINT8 Reserved37; + UINT32 Reserved38; + + UINT8 Reserved39; + UINT8 Reserved40; + +} KTI_RESERVED_3; + +typedef struct { + UINT32 Reserved1:2; + UINT32 Reserved2:2; + UINT32 Reserved3:2; + UINT32 Rsvd1 : 26; +} KTI_RESERVED_1; + +typedef struct { + UINT8 Reserved4 : 2; + UINT8 Rsvd1 : 6; +} KTI_RESERVED_2; + +typedef struct { + KTI_RESERVED_1 Link[MAX_FW_KTI_PORTS]; + KTI_RESERVED_2 Phy[MAX_FW_KTI_PORTS]; +} KTI_RESERVED_4; + +// +// PHY settings that are system dependent. Need 1 of these for each sock= et/link/freq. +// + +typedef struct { + UINT8 SocketID; + UINT8 AllLanesUseSameTxeq; + UINT8 Freq; + UINT32 Link; + UINT32 TXEQL[20]; + UINT32 CTLEPEAK[5]; +} PER_LANE_EPARAM_LINK_INFO; + +// +// This is for full speed mode, all lanes have the same TXEQ setting +// +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +#define ADAPTIVE_CTLE 0x3f + +typedef enum { + TYPE_UBOX =3D 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_HFI, + TYPE_NAC, + TYPE_GRAPHICS, + TYPE_DINO, + TYPE_RESERVED, + TYPE_DISABLED, // This item must be prior to stack specific= disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_HFI_DIS, + TYPE_NAC_DIS, + TYPE_GRAPHICS_DIS, + TYPE_DINO_DIS, + TYPE_RESERVED_DIS, + TYPE_NONE +} STACK_TYPE; + +// +// Link layer settings, per link +// +typedef struct { + UINT8 KtiPortDisable:1; // TRUE - Port disabled; FALSE- Port enab= led (default) + UINT8 KtiLinkVnaOverride:7; // Numeric value 0x00-0x7f + UINT8 Rsvd:8; +} KTI_CPU_LINK_SETTING; + + +// +// Phy general setting, per link +// +typedef struct { + UINT32 KtiLinkSpeed:3; + UINT32 Rsvd:29; +} KTI_CPU_PHY_SETTING; + +// +// Per CPU setting +// +typedef struct { + KTI_CPU_LINK_SETTING Link[MAX_FW_KTI_PORTS]; + KTI_CPU_PHY_SETTING Phy[MAX_FW_KTI_PORTS]; +} KTI_CPU_SETTING; + +// +// KTIRC input structure +// +typedef struct { + // + // Protocol layer and other general options; note that "Auto" is provide= d only options whose value will change depending + // on the topology, not for all options. + // + + // + // Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each= CPU's IIO. + // Value 0 indicates, that CPU is not relevant for the system. If resour= ce is + // requested for an CPU that is not currently populated, KTIRC will assu= me + // that the ratio is 0 for that CPU and won't allocate any resources for= it. + // If resource is not requested for an CPU that is populated, KTIRC will= force + // the ratio for that CPU to 1. + // + + + UINT8 BusRatio[MAX_SOCKET]; + + UINT8 D2KCreditConfig; // 1 - Min, 2 - Med (De= fault), 3- Max + UINT8 SnoopThrottleConfig; // 0 - Disabled (Default), 1 -= Min, 2 - Med, 3- Max + UINT8 SnoopAllCores; // 0 - Disabled, 1 - Enabled, = 2 - Auto + UINT8 LegacyVgaSoc; // Socket that claims the legacy= VGA range; valid values are 0-7; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy = VGA range; valid values are 0-3; 0 is default. + UINT8 ColdResetRequestStart; + UINT8 P2pRelaxedOrdering; // 0 - Disable(default) 1 - Enab= le + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning= , Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 SncEn; // 0 - Disable, (default) 1 - En= able + UINT8 UmaClustering; // 0 - Disable, 2 - 2Clusters UM= A, 4 - 4Clusters UMA + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (= default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC= _NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE defini= tion; TOPOLOGY_PRECEDENCE is default + UINT8 Degrade4SPreference;// 4S1LFullConnect topology is d= efault; another option is 4S2LRing topology. + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (defa= ult) + UINT8 XptPrefetchEn; // Xpt Prefetch : 1 - Enable; 0= - Disable; 2 - Auto (default) + UINT8 KtiPrefetchEn; // Kti Prefetch : 1 - Enable; 0= - Disable; 2 - Auto (default) + UINT8 XptRemotePrefetchEn; // Xpt Remote Prefetch : 1= - Enable; 0 - Disable; 2 - Auto (default) (ICX only) + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch := 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiFpgaEnable[MAX_SOCKET]; // Indicate if should en= able Fpga device found in this socket : 0 - Disable, 1 - Enable, 2- Auto + UINT8 DdrtQosMode; // DDRT QoS Feature: 0 - Disa= ble (default), 1 - M2M QoS Enable, Cha QoS Disable + // 2 - M2M QoS Enable, Cha QoS= Enable + + // + // Phy/Link Layer Options (System-wide and per socket) + // + UINT8 KtiLinkSpeedMode; // Link speed mode selection; 0 = - Slow Speed; 1- Full Speed (default) + UINT8 KtiLinkSpeed; // Use KTI_LINKSPEED definition + UINT8 KtiAdaptationEn; // 0 - Disable, 1 - Enable + UINT8 KtiAdaptationSpeed; // Use KTI_LINK_SPEED definition= ; MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed) + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- A= uto (default) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- A= uto (default) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- A= uto (default) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Ena= ble + UINT8 KtiCrcMode; // CRC_MODE_16BIT, CRC_MODE_ROLL= ING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK + + UINT8 KtiCpuSktHotPlugEn; // 0 - Disable (default), = 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (defaul= t), 1 - 8S Topology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (defaul= t) + UINT8 IrqThreshold; // IRQ Threshold setting + UINT8 TorThresLoctoremNorm; // TOR threshold - Loctore= m threshold normal + UINT8 TorThresLoctoremEmpty; // TOR threshold - Loctore= m threshold empty + UINT8 MbeBwCal; // 0 - Linear, 1 - Biased,= 2 - Legacy, 3 - AUTO (default =3D Linear) + UINT8 TscSyncEn; // TSC sync in sockets: 0 = - Disable, 1 - Enable, 2 - AUTO (Default) + UINT8 StaleAtoSOptEn; // HA A to S directory opt= imization: 1 - Enable; 0 - Disable; 2 - Auto (Default) + UINT8 LLCDeadLineAlloc; // LLC dead line alloc: 1 = - Enable(Default); 0 - Disable + UINT8 SplitLock; + UINT8 ColdResetRequestEnd; + + // + // Phy/Link Layer Options (per Port) + // + KTI_CPU_SETTING PhyLinkPerPortSetting[MAX_SOCKET]; + + + UINT8 mmCfgBase; ///< MMCFG Base address, must be 64MB (SK= X, HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G, 1:1.5G, 2:1.75G, = 3:2G, 4:2.25G, 5:3G, 6: Auto} + UINT8 mmCfgSize; ///< MMCFG Size address, must be 64M, 128= M or 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto} + UINT32 mmiolBase; ///< MMIOL Base address, must be 64MB ali= gned + UINT32 mmiolSize; ///< MMIOL Size address + UINT32 mmiohBase; ///< Address bits above 4GB, i,e, the hex= value here is address Bit[45:32] for SKX family, Bit[51:32] for ICX-SP + UINT8 CpuPaLimit; ///< Limits the max address to 46bits. T= his will take precedence over mmiohBase + UINT8 lowGap; + UINT8 highGap; + UINT16 mmiohSize; ////<< Number of 1GB contiguous regions t= o be assigned for MMIOH space per CPU. Range 1-1024 + UINT8 isocEn; ///< 1 - Enable; 0 - Disable (BIOS will f= orce this for 4S) + UINT8 dcaEn; ///< 1 - Enable; 0 - Disable + + /* + BoardTypeBitmask: + Bits[3:0] - Socket0 + Bits[7:4] - Socket1 + Bits[11:8] - Socket2 + Bits[15:12] - Socket3 + Bits[19:16] - Socket4 + Bits[23:20] - Socket5 + Bits[27:24] - Socket6 + Bits[31:28] - Socket7 + + Within each Socket-specific field, bits mean: + Bit0 =3D CPU_TYPE_STD support; always 1 on Socket0 + Bit1 =3D CPU_TYPE_F support + Bit2 =3D CPU_TYPE_P support + Bit3 =3D reserved + */ + UINT32 BoardTypeBitmask; + UINT32 AllLanesPtr; + UINT32 PerLanePtr; + UINT32 AllLanesSizeOfTable; + UINT32 PerLaneSizeOfTable; + UINT32 WaitTimeForPSBP; // the wait time in units of 1000us= for PBSP to check in. + BOOLEAN IsKtiNvramDataReady; + UINT32 OemHookPostTopologyDiscovery; + UINT32 OemGetResourceMapUpdate; + UINT32 OemGetAdaptedEqSettings; + UINT32 OemCheckCpuPartsChangeSwap; + + BOOLEAN WaSerializationEn; // Enable BIOS serialization= WA by PcdWaSerializationEn + KTI_RESERVED_3 Reserved166; + KTI_RESERVED_4 Reserved167[MAX_SOCKET]; + UINT8 KtiInEnableMktme; // 0 - Disabled; 1 - Enabled= ; MkTme status decides D2Kti feature state + UINT32 CFRImagePtr; + UINT8 S3mCFRCommit; // 0 - Disable S3m CFR flow.= 1 - Provision S3m CFR but not Commit. 2 - Provsion and Commit S3M CF= R. + UINT8 PucodeCFRCommit; // 0 - Disable Pucode CFR fl= ow. 1 - Provision Pucode CFR but not Commit. 2 - Provsion and Commit Pucode= CFR. +} KTI_HOST_IN; + +#pragma pack() + +#endif // _KTI_HOST_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h b/Silicon/= Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h new file mode 100644 index 0000000000..c0653bfae0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h @@ -0,0 +1,32 @@ +/** @file + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _KTI_SI_H_ +#define _KTI_SI_H_ + +#include "DataTypes.h" + +#if (MAX_SOCKET =3D=3D 1) + #define MAX_FW_KTI_PORTS 3 // Maximum KTI PORTS to be used in str= ucture definition. +#else + #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in str= ucture definition +#endif //(MAX_SOCKET =3D=3D 1) + +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 + +#define UBOX_STACK MAX_LOGIC_IIO_STACK - 1 //use stack 13 for ubox + +#define IIO_RESERVED_1 6 + +#define MAX_CHA_MAP 4 + +#endif // _KTI_SI_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h b/Sil= icon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h new file mode 100644 index 0000000000..e53aeb285b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h @@ -0,0 +1,291 @@ +/** @file + Unified Silicon Register Access Types + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __USRA_ACCESS_TYPE_H__ +#define __USRA_ACCESS_TYPE_H__ + +typedef enum { + AddrTypePCIE =3D 0, + AddrTypePCIEBLK, + AddrTypeCSR, + AddrTypePCIIO, + AddrTypeCSRMEM, + AddrTypeCSRCFG, + AddrTypeMaximum +} USRA_ADDR_TYPE; + +typedef enum { + CsrBoxInst =3D 0, + CsrMcId, + CsrChId, + CsrIoId, + InstTypeMax +} CSR_INSTANCE_TYPE; + +typedef enum { + UsraWidth8 =3D 0, + UsraWidth16, + UsraWidth32, + UsraWidth64, + UsraWidthFifo8, + UsraWidthFifo16, + UsraWidthFifo32, + UsraWidthFifo64, + UsraWidthFill8, + UsraWidthFill16, + UsraWidthFill32, + UsraWidthFill64, + UsraWidthMaximum +} USRA_ACCESS_WIDTH; + +#define USRA_ENABLE 1; +#define USRA_DISABLE 0; + +#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8 +#define PCI_CONFIGURATION_DATA_PORT 0xCFC + +#pragma pack (1) + +typedef struct { + UINT32 RawData32[2]; // RawData of two UINT32 type, p= lace holder + UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO= , IO, SMBus ... + UINT32 AccessWidth:4; // The Access width for 8, 16,32= ,64 -bit access + UINT32 FastBootEn:1; // Fast Boot Flag, can be used t= o log register access trace for fast boot + UINT32 S3Enable:1; // S3 Enable bit, when enabled, = it will save the write to script to support S3 + UINT32 HptrType:1; // Host Pointer type, below or a= bove 4GB + UINT32 ConvertedType:1; // The address type was from con= verted type, use this field for address migration support + UINT32 RFU3:16; // Reserved for User use or Futu= re Use + + UINT32 HostPtr:32; // The Host Pointer, to point to= Attribute buffer etc. +} ADDR_ATTRIBUTE_TYPE; + +typedef struct { + UINT32 Offset:12; // The PCIE Register Offset + UINT32 Func:3; // The PCIE Function + UINT32 Dev:5; // The PCIE Device + UINT32 Bus:8; // The PCIE Bus + UINT32 RFU1:4; // Reserved for User use or Futu= re Use + + UINT32 Seg:16; // The PCI Segment + UINT32 Count:16; // Access Count + +} USRA_PCIE_ADDR_TYPE; + +#define BUS_DEV_FUN_OFFSET_MASK 0x0FFFFFFF + +typedef struct { + UINT32 Offset; // This Offset occupies 32 bits= . It's platform code's responsibilty to define the meaning of specific + // bits and use them accordingly. + UINT32 InstId:8; // The Box Instance, 0 based, In= dex/Port within the box, Set Index as 0 if the box has only one instances + UINT32 SocketId:8; // The Socket Id + UINT32 InstType:8; // The Instance Type + UINT32 RFU:8; // Reserved for User use or Futu= re Ues +} USRA_CSR_ADDR_TYPE; + +typedef struct { + UINT32 Offset:8; // The PCIIO Register Offset + UINT32 Func:3; // The PCIIO Function + UINT32 Dev:5; // The PCIIO Device + UINT32 Bus:8; // The PCIIO Bus + UINT32 RFU:7; // Reserved for User use or Futu= re Use + UINT32 EnableBit:1; // The PCIIO Register Enable Bit +} USRA_PCIIO_ADDR_TYPE; + +typedef struct { + UINT32 Offset:32; // The register offset + UINT32 SocketId:8; // The socket ID + UINT32 MemBarId:8; // The ID of the BAR + UINT32 High64Split:1; // Move address up to access top= of 64 bit register + UINT32 Reserved:15; // Reserved for User use or Futu= re Use +} USRA_CSR_MEM_ADDR_TYPE; + +typedef struct { + UINT32 Offset:32; // The register offset + UINT32 SocketId:7; // The socket ID + UINT32 Bus:8; // Bus + UINT32 Device:8; // Device + UINT32 Function:8; // Function + UINT32 High64Split:1; // Move address up to access top= of 64 bit register +} USRA_CSR_CFG_ADDR_TYPE; + +#pragma pack() + +typedef union { + UINT32 dwRawData[4]; + ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute typ= e. + USRA_PCIE_ADDR_TYPE Pcie; + USRA_PCIE_ADDR_TYPE PcieBlk; + USRA_CSR_ADDR_TYPE Csr; + USRA_PCIIO_ADDR_TYPE PciIo; + USRA_CSR_MEM_ADDR_TYPE CsrMem; + USRA_CSR_CFG_ADDR_TYPE CsrCfg; +} USRA_ADDRESS; + +// +// Assemble macro for USRA_PCIE_ADDR_TYPE +// +#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET)= \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg =3D (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus =3D (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev =3D (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func =3D (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset =3D (UINT32)(OFFSET) & 0x0FFF + + // + // Assemble macro for USRA_BDFO_ADDR_TYPE + // +#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg =3D (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus =3D (UINT32)(BDFO >> 20) & 0xF= F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev =3D (UINT32)(BDFO >> 15) & 0x1= F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func =3D (UINT32)(BDFO >> 12) & 0x= 07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset =3D (UINT32)(BDFO) & 0x0FFF + + // + // Assemble macro for USRA_PCIE_SEG_LIB_ADDR_TYPE + // +#define USRA_PCIE_SEG_LIB_ADDRESS(Address, PCISEGADDR, WIDTH) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg =3D (UINT32)((PCISEGADDR >> 32)= & 0x0000FFFF); \ + ((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] =3D (UINT32)(PCIS= EGADDR & BUS_DEV_FUN_OFFSET_MASK) + + // + // Assemble macro for USRA_PCIE_BLK_ADDR_TYPE + // +#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC= , OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIEBLK; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Count =3D (UINT32)COUNT; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg =3D (UINT32)SEG; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus =3D (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev =3D (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Func =3D (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset =3D (UINT32)(OFFSET) & 0x= 0FFF + // + // Assemble macro for USRA_PCIE_SEG_ADDR_TYPE + // +#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET) + + // + // Assemble macro for USRA CSR common Address + // +#define USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Csr.SocketId =3D SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstId =3D INSTID; \ + ((USRA_ADDRESS *)(&Address))->Csr.Offset =3D CSROFFSET + + // + // Assemble macro for address type CSR + // +#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \ + USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType =3D CsrBoxInst; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSR + +#define USRA_CSR_MCID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET)= \ + USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType =3D CsrMcId; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSR + +#define USRA_CSR_CHID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET)= \ + USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType =3D CsrChId; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSR + +#define USRA_CSR_IOID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET)= \ + USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType =3D CsrIoId; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSR + + // + // Assemble macro for USRA_PCIIO_ADDR_TYPE + // +#define USRA_PCI_IO_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIIO; \ + ((USRA_ADDRESS *)(&Address))->PciIo.Bus =3D (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->PciIo.Dev =3D (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->PciIo.Func =3D (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->PciIo.Offset =3D (UINT32)(OFFSET) & 0xFF= ; \ + ((USRA_ADDRESS *)(&Address))->PciIo.EnableBit =3D 1 + + // + // Assemble macro for USRA_BDFO_PCIIO_ADDR_TYPE + // +#define USRA_PCI_IO_BDFO_ADDRESS(Address, WIDTH, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypePCIIO; \ + ((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] =3D (UINT32)(BDFO= ) & 0xFFFFFF; \ + ((USRA_ADDRESS *)(&Address))->PciIo.EnableBit =3D 1 + + // + // Assemble macro for USRA_CSR_MMIO_ADDR_TYPE + // +#define USRA_CSR_MEM_ADDRESS(Address, SOCKETID, MEMBARID, OFFSET, WIDTH) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSRMEM; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->CsrMem.SocketId =3D SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->CsrMem.MemBarId =3D MEMBARID; \ + ((USRA_ADDRESS *)(&Address))->CsrMem.Offset =3D OFFSET; \ + ((USRA_ADDRESS *)(&Address))->CsrMem.High64Split =3D 0; + + // + // Assemble macro for USRA_CSR_CFG_ADDR_TYPE + // +#define USRA_CSR_CFG_ADDRESS(Address, SOCKETID, BUS, DEVICE, FUNCTION, OFF= SET, WIDTH) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType =3D AddrTypeCSRCFG; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth =3D WIDTH; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.SocketId =3D SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.Bus =3D BUS; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.Device =3D DEVICE; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.Function =3D Function; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.Offset =3D OFFSET; \ + ((USRA_ADDRESS *)(&Address))->CsrCfg.High64Split =3D 0; + + // + // Assemble macro for ZERO_USRA ADDRESS + // +#define USRA_ZERO_ADDRESS(Address) \ + ((UINT32 *)&Address)[3] =3D (UINT32)0; \ + ((UINT32 *)&Address)[2] =3D (UINT32)0; \ + ((UINT32 *)&Address)[1] =3D (UINT32)0; \ + ((UINT32 *)&Address)[0] =3D (UINT32)0 + + // + // Assemble macro for ZERO_ADDR_TYPE + // +#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \ + ((UINT32 *)&Address)[3] =3D (UINT32)0; \ + ((UINT32 *)&Address)[2] =3D (UINT32)((AddressType) & 0x0FF); \ + ((UINT32 *)&Address)[1] =3D (UINT32)0; \ + ((UINT32 *)&Address)[0] =3D (UINT32)0 + +#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \ + ((UINT32 *)DestAddrPtr)[3] =3D ((UINT32 *)SourceAddrPtr)[3]; \ + ((UINT32 *)DestAddrPtr)[2] =3D ((UINT32 *)SourceAddrPtr)[2]; \ + ((UINT32 *)DestAddrPtr)[1] =3D ((UINT32 *)SourceAddrPtr)[1]; \ + ((UINT32 *)DestAddrPtr)[0] =3D ((UINT32 *)SourceAddrPtr)[0]; + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCo= reLib/Core/Include/DataTypes.h new file mode 100644 index 0000000000..eb4bd92a1d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/DataTypes.h @@ -0,0 +1,36 @@ +/** @file + DataTypes.h + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _datatypes_h +#define _datatypes_h + +#include + +typedef struct u64_struct { + UINT32 lo; + UINT32 hi; +} UINT64_STRUCT, *PUINT64_STRUCT; + +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_DATA; + + +typedef struct u128_struct { + UINT32 one; + UINT32 two; + UINT32 three; + UINT32 four; +} UINT128; + +#endif // _datatypes_h diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Core/Include/MemHost.h new file mode 100644 index 0000000000..8eaea40f72 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemHost.h @@ -0,0 +1,1051 @@ +/** @file + MemHost.h + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _memhost_h +#define _memhost_h + +#include +#include "DataTypes.h" +#include "PlatformHost.h" +#include "MemRegs.h" +#include "MemDefaults.h" +#include "NGNDimmPlatformCfgData.h" +#include "MrcCommonTypes.h" +#include "MemHostChipCommon.h" +#include +#include +#include + +#define RESERVED_2 2 + +typedef struct TrainingStepDoneStruct { + UINT8 DramRxEq : 1; + UINT8 HostFlyBy : 1; + UINT8 TxVref : 1; + UINT8 DqSwzDone : 1; + UINT8 Reserved : 4; +} TRAINING_STEP_DONE_STRUCT; + +#define CADB_MUX_MAX 4 + +#define MAX_BITS_IN_BYTE 8 // BITS per byte +#define MAX_BITS_IN_DWORD 32 // BITS per dword +#define BITS_PER_NIBBLE 4 +#define MAX_NIBBLES_PER_BYTE 2 +#define INDEX_NIBBLE0 0 +#define INDEX_NIBBLE1 1 + +// +// DDR4 DB has 4 DFE coeff taps +// +#define DB_DFE_TAP 4 + +#pragma pack(push, 1) + +/// +/// Rand per channel information +// +typedef struct RankCh { + UINT8 dimm; ///< DIMM this rank = belongs to + UINT8 rank; ///< Rank on the DIM= M (0-3) + UINT8 Roundtrip; + UINT8 IOLatency; +} CHANNEL_RANKS; + +typedef enum { +INVALID_BUS, +SMBUS, +EMRS, +CPGC, +SAD, +} BUS_TYPE; + +// +// -----------------------------------------------------------------------= ------ +/// +/// Common DRAM timings +/// +struct comTime { + UINT8 nCL; + UINT8 nWR; + UINT8 nRCD; + UINT8 nAL; + UINT8 nRP; + UINT8 nRC; + UINT8 nWTR; + UINT8 nWTR_L; + UINT8 nRAS; + UINT8 nRTP; + UINT8 nFAW; + UINT8 nRRD; + UINT8 nRRD_L; + UINT8 nWL; + UINT16 nRFC; + UINT32 tCL; + UINT16 tRCD; + UINT16 tRP; + UINT16 tRC; + UINT16 tRFC; + UINT16 tRRD; + UINT16 tRRD_L; + UINT16 tRAS; + UINT16 tCCD; + UINT16 tCCD_WR; + UINT16 tCCD_L; + UINT16 tCCD_WR_L; + UINT64 casSup; + UINT8 casSupRange; +}; //struct comTime + +// +// Only applicable for x16 devices where 2 strobes are within a single DRA= M device +// +typedef struct _X16_MAPPING { + UINT8 PairLogical[MAX_STROBE/2]; ///< Identifies logical strobe wit= hin the same DRAM device + BOOLEAN IsLow[MAX_STROBE/2]; ///< TRUE: represents the current= logical strobe is connected to DQSL + ///< FALSE: represents the current= logical strobe is connected to DQSU +} X16_MAPPING; + +// +// Packed bit field structure for storing MR1 RX EQ bits +// +typedef struct { + UINT32 Strobe0 : 3; //bits 0...2 + UINT32 Strobe1 : 3; //bits 3...5 + UINT32 Strobe2 : 3; //bits 6...8 + UINT32 Strobe3 : 3; //bits 9...11 + UINT32 Strobe4 : 3; //bits 12..14 + UINT32 Strobe5 : 3; //bits 15..17 + UINT32 Strobe6 : 3; //bits 18..20 + UINT32 Strobe7 : 3; //bits 21..23 + UINT32 Strobe8 : 3; //bits 24..26 + UINT32 Rsvd : 5; //bits 27..31 +} Mr1RxEqStruct; + +// +// NVRAM structures for S3 state +// + +/// +/// DIMM rank info +/// List indexed by rank number +/// +typedef struct ddrRank { + UINT8 enabled; ///< 0 =3D disabled, 1 =3D enabled + UINT8 rankIndex; + UINT8 phyRank; ///< Physical Rank #(3:0) + UINT8 logicalRank; ///< Logical Rank number (0 - 7) + UINT8 ckIndex; ///< Index to the clock for this rank + UINT8 ctlIndex; ///< Index to the control group for = this rank + UINT8 CKEIndex; + UINT8 ODTIndex; + UINT8 CSIndex; + UINT8 devTagInfo; + UINT16 RttWr; + UINT16 RttPrk; + UINT16 RttNom; + UINT16 rankSize; ///< Units of 64 MB + UINT16 remSize; ///< Units of 64 MB + UINT16 NVrankSize; ///< Units of 64 MB + + UINT8 cmdLeft; + UINT8 cmdRight; + UINT8 cmdLow; + UINT8 cmdHigh; + + UINT8 rxDQLeftSt; + UINT8 rxDQRightSt; + UINT8 txDQLeftSt; + UINT8 txDQRightSt; + UINT16 OutDrvImpCtrl; + UINT8 DqSwzDdr5[SUB_CH][20]; + UINT8 faultyParts[MAX_STROBE]; +#ifdef LRDIMM_SUPPORT + UINT8 lrbufRxVref[MAX_STROBE]; ///< Actual value of backside RxVr= ef + UINT8 lrBuf_FxBC4x5x[MAX_STROBE]; + UINT8 lrBuf_FxBC8x9x[MAX_STROBE]; +#endif + UINT8 lrBuf_FxBC2x3x[MAX_STROBE]; + UINT8 lrBuf_FxBCAxBx[MAX_STROBE]; + UINT8 lrBuf_FxBCCxEx[MAX_STROBE/2]; + UINT8 lrBuf_FxBCDxFx[MAX_STROBE/2]; + UINT32 lrbufTxVref[MAX_STROBE]; ///< Actual value of backside TxVr= ef + // + // MR1 per strobe Rx Eq value structure with 9 elements per structure + // therefore you need MAX_STROBE/9 structures to store all elements + // + Mr1RxEqStruct Mr1RxEqSettings[MAX_STROBE/9]; + +} DDR_RANK_STRUCT; //struct ddrRank + +typedef enum { + DIMM_RANK_MAP_OUT_UNKNOWN =3D 0, + DIMM_RANK_MAP_OUT_MEM_DECODE, + DIMM_RANK_MAP_OUT_POP_POR_VIOLATION, + DIMM_RANK_MAP_OUT_RANK_DISABLED, + DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE, + DIMM_RANK_MAP_OUT_MAX +} DIMM_RANK_MAP_OUT_REASON; + +/// +/// DIMM information stored in NVRAM +// +typedef struct dimmNvram { + UINT8 dimmPresent; ///< 1 =3D DIMM presen= t in this slot + UINT8 mailboxReady; + UINT16 lrbufswizzle; + INT32 minTCK; ///< minimum tCK for t= his DIMM (SPD_MIN_TCK) + UINT8 ftbTCK; ///< fine offset for t= CK + UINT32 tCL; + UINT16 tRCD; + UINT16 tRP; + UINT8 ftbTRP; ///< DDR4 fine offset = for tRP + UINT8 ftbTRCD; ///< DDR4 fine offset = for tRCD + UINT8 ftbTAA; ///< DDR4 fine offset = for tAA + UINT8 mapOut[MAX_RANK_DIMM]; ///< 1 =3D User req= uested rank made non-Present + UINT8 numRanks; ///< Number of logical= ranks on this DIMM + UINT8 numDramRanks; ///< Number of physica= l DRAM ranks on this DIMM + UINT8 techIndex; ///< Index into DIMM t= echnology table + UINT8 aepTechIndex; ///< Index into NVM DI= MM technology table + UINT8 fmcType; ///< Far Memory Contro= ller Type + UINT8 fmcRev; ///< Far Memory Contro= ller Rev Type + SPD_AEP_MOD_REVISION_STRUCT FmcModRev; ///< Far Memory Controller Modu= le Rev and Type + UINT8 NvmStepping; ///< NVM Device Steppi= ng + UINT8 NvmDevDensity; ///< NVM DEV DENSITY + UINT8 NvmDevType; ///< NVM DEV TYPE + UINT8 SPDRawCard; ///< Raw Card Number + UINT8 DimmRevType; ///< RCD Revision + UINT8 SPDOtherOptFeatures;///< SDRAM Other Optio= nal features + UINT8 SPDAddrMapp; ///< Address Mapping f= rom Edge connector to DRAM + UINT8 SPDRegRev; ///< Register Revision + UINT8 SPDODCtl; ///< Register Output D= rive Strength for Control + UINT8 SPDODCk; ///< Register Output D= rive Strength for Clock +#ifdef LRDIMM_SUPPORT + UINT16 SPDLrbufVen; ///< LRDIMM Data Buf= fer Vendor ID + UINT8 SPDLrbufDramVrefdqR0; ///< DRAM VrefDQ for= Package Rank 0 + UINT8 SPDLrbufDramVrefdqR1; ///< DRAM VrefDQ for= Package Rank 1 + UINT8 SPDLrbufDramVrefdqR2; ///< DRAM VrefDQ for= Package Rank 2 + UINT8 SPDLrbufDramVrefdqR3; ///< DRAM VrefDQ for= Package Rank 3 + UINT8 SPDLrbufDbVrefdq; ///< LR Data Buffer Vref= DQ for DRAM Interface + UINT8 SPDLrbufDbDsRttLe1866; ///< LR Data Buffer= MDQ Drive Strength and RTT for data rate <=3D 1866 + UINT8 SPDLrbufDbDsRttGt1866Le2400; ///< LR Data = Buffer MDQ Drive Strength and RTT for data rate > 1866 and <=3D 2400 + UINT8 SPDLrbufDbDsRttGt2400Le3200; ///< LR Data = Buffer MDQ Drive Strength and RTT for data rate > 2400 and <=3D 3200 + UINT8 SPDLrbufDramDs; ///< LR Buffer DRAM Drive = Strength (for data rates <1866, 1866 < data rate < 2400, and 2400 < data ra= te < 3200) + UINT8 SPDLrbufDramOdtWrNomLe1866; ///< LR Buffer= DRAM ODT (RTT_WR and RTT_NOM) for data rate <=3D 1866 + UINT8 SPDLrbufDramOdtWrNomGt1866Le2400; ///< LR = Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <=3D 2400 + UINT8 SPDLrbufDramOdtWrNomGt2400Le3200; ///< LR = Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <=3D 3200 + UINT8 SPDLrbufDramOdtParkLe1866; ///< LR Buffer = DRAM ODT (RTT_WR and RTT_NOM) for data rate <=3D 1866 + UINT8 SPDLrbufDramOdtParkGt1866Le2400; ///< LR B= uffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <=3D 2400 + UINT8 SPDLrbufDramOdtParkGt2400Le3200; ///< LR B= uffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <=3D 3200 + UINT8 rcLrFunc; + UINT8 lrBuf_BC00; + UINT8 lrBuf_BC01; + UINT8 lrBuf_BC02; + UINT8 lrBuf_BC03; + UINT8 lrBuf_BC04; + UINT8 lrBuf_BC05; + UINT8 lrBuf_BC1x; + UINT8 LrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP= ][MAX_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB + UINT8 Dfe_F2BCEX; // JEDEC DB02DFE DQ selection = and global enable +#endif // LRDIMM_SUPPORT + + UINT8 XMPOrg; ///< XMP organization = and configuration + UINT8 XMPRev; + UINT32 XMPChecksum; + + UINT8 x4Present; ///< Set if this is a = x4 rank + UINT8 keyByte; + UINT8 keyByte2; ///< Logical module ty= pe (for MRC compat) + UINT8 DcpmmPresent; ///< Is an NVM DIMM pr= esent? + BOOLEAN NvmDimmDisable; ///< 1 =3D NVMDimm pre= sent but got disabled in this slot + UINT8 actKeyByte2; ///< Actual module typ= e reported by SPD + UINT8 SPDModuleOrg; ///< Logical number of= DRAM ranks and device width + UINT8 actSPDModuleOrg; ///< Actual number of = DRAM ranks and device width + UINT8 dramIOWidth; ///< The encoded value= of DRAM IO width + UINT8 dramIOWidthSecondary; ///< The encoded = value of IO width for secondary SDRAM + BOOLEAN rankMix; ///< Used to indicate = if the target DIMM is asymmetric + UINT8 SPDDeviceType; ///< Primary SDRAM Dev= ice Type + UINT8 SPDSecondaryDeviceType; ///< Secondary SDR= AM Device Type + UINT8 numBankAddressBits; ///< Number of bank ad= dress bits per bank group + UINT8 numBankAddressBitsSecondary; ///< Number o= f bank address bits per bank group of Secondary SDRAM + UINT8 numBankGroupBits; ///< Number of bank gr= oup bits + UINT8 numBankGroupBitsSecondary; ///< Number of = bank group bits of Secondary SDRAM + UINT8 sdramCapacity; ///< Encoded SDRAM cap= acity based on DDR4 format + UINT8 sdramCapacitySecondary; ///< Encoded = SDRAM capacity based on DDR4 format for Secondary SDRAM + UINT8 numRowBits; ///< Number of row add= ress bits + UINT8 numRowBitsSecondary; ///< Number of row= address bits of Secondary SDRAM + UINT8 numColBits; ///< Number of column = address bits + UINT8 numColBitsSecondary; ///< Number of col= umn address bits of Secondary SDRAM + UINT8 dieCount; ///< Number of SDRAM d= ies per package for symmetric DIMMs or Primary SDRAM dies per package for a= symmetric DIMMs + UINT8 dieCountSecondary; ///< Number of Seconda= ry DRAM dies per package for asymmetric DIMMs + UINT8 cidBitMap; ///< SubRanks per chip= select per dimm of DDR4 3DS and non3ds_lrdimm + UINT8 lrRankMult; ///< Rank multiplicati= on factor + UINT8 SPDMemBusWidth; ///< Width of the Prim= ary bus and extension + UINT8 dimmTs; ///< Module Thermal Se= nsor + UINT8 dimmAttrib; ///< Module attributes + UINT8 mtbDiv; ///< medium time base = divisor (SPD_MTB_DIV) + UINT8 SPDftb; ///< fine time base (S= PD_FTB) + UINT32 dimmMemTech; ///< Used to program D= IMMMTR + UINT16 SPDRegVen; ///< Register Vendor ID + UINT16 SPDMMfgId; ///< Module Mfg Id fro= m SPD + UINT8 SPDMMfLoc; ///< Module Mfg Locati= on from SPD + UINT16 SPDModDate; ///< Module Manufactur= ing Date + UINT16 SPDDramMfgId; ///< DRAM Mfg Id + UINT8 SPDDramRev; ///< DRAM Rev Id + UINT8 SPDModSN[SPD_MODULE_SERIAL]; = ///< Module Serial Number + UINT8 SPDModPartDDR4[SPD_MODULE_PART_DDR4]; = ///< Module Part Number DDR4 + UINT8 SPDOptionalFeature; ///< DDR4 optional fea= ture + UINT8 AitDramPoll; + BOOLEAN NvDimmNPresent; ///< JEDEC NVDIMM-N Ty= pe Memory Present + UINT16 NvDimmStatus; + // Bit Description + // 0 NVDIMM controller failure + // 1 NVDIMM restore failed + // 2 NVDIMM restore retry + // 3 NVDIMM backup failed + // 4 NVDIMM erase failed + // 5 NVDIMM erase retry + // 6 NVDIMM arm failed + // 7 No backup energy source detected + // 8 Backup energy source charge failed + // 9 NVDIMM uncorrectable memory error + // 10 NVDIMM correctable memory memory error threshold + // 11-15 Reserved + + UINT8 lrbufRid; ///< LR Buffer Revisio= n ID (from buffer not SPD) + UINT8 lrbufGen; ///< LR Buffer Gen + UINT8 SPDIntelSN[5]; ///< Intel DIMM serial= number + struct ddrRank rankList[MAX_RANK_DIMM]; + UINT8 SPDmtb; ///< DDR4 medium time = base (SPD_TB_DDR4) + UINT8 SPDSpecRev; ///< Revision of the S= PD spec for this data + UINT8 SpdModuleType; ///< SPD Byte 2 (0x002= ): Key Byte / Host Bus Command Protocol Type + UINT8 rcCache[16]; /// DDR4 RCD cache + UINT8 rcxCache[16]; + UINT8 lrDimmPresent; + UINT8 rcClk; + UINT8 rcCmd; + UINT8 rcCtl; + UINT16 rcVref; + INT16 QxCAClkOffset; ///< RCD QxCA Training= Offset + UINT8 dqSwz[36]; + UINT16 rawCap; ///< Raw Capacity + UINT16 VendorID; ///< Vendor ID for NVM= DIMM Mgmt driver thru Nfit + UINT16 DeviceID; ///< Device ID for NVM= DIMM Mgmt driver thru Nfit + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 DimmGnt2Erid; ///< DIMM-side Grant-t= o-ERID (produced by SPD and consumed by FMC; distinct from MC-programmed va= lue) + X16_MAPPING LogicalX16Mapping; + UINT8 manufacturer[NGN_MAX_MANUFACTURER_STRLEN];= /* Manufacturer */ + UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN];= /* Serial Number */ + UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; /* = Part Number */ + UINT16 volCap; /* Volatile Capacity (= 2LM region) */ + UINT16 nonVolCap; /* NonVolatile Capacit= y (PMEM/PMEM$ region + Blk region) */ + UINT16 perCap; /* Persistent Capcity = (PMEM/PMEM$). This size is not obtained from FNV. This is derived data. */ + UINT16 WbCachePerCap; /* Persistent WB cache= Capcity (AD-WB) This size is not obtained from FNV. This is derived data. = */ + UINT32 volRegionDPA; /* DPA start address o= f 2LM Region */ + UINT32 perRegionDPA; /* DPA start address o= f PMEM Region */ + struct firmwareRev firmwareRevision; /* Firmware Revision */ + UINT8 dimmSku; /* Dimm SKU info Bit0:= MemorymodeEnabled 1: StoragemodeEnabled 2:AppDirectmodeEnabled 3:DieSparing= Capable 4:SoftProgrammableSKU 5:MemorymodeEncryptionEnabled 6:AppDirectmode= EncryptionEnabled 7:StoragemodeEncrytionEnabled */ + UINT16 InterfaceFormatCode; + UINT16 VendorIDIdentifyDIMM; + UINT16 DeviceIDIdentifyDIMM; + UINT32 DdrtDimmBasicTiming; + UINT8 Uniqueid[NGN_MAX_UID_STRLEN]; /* Unique I= D */ + DIMM_RANK_MAP_OUT_REASON MapOutReason[MAX_RANK_DIMM]; + UINT8 VlpRdimmPresent; + RDIMM_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION_STRUCT SpdThermalHeatSpreade= rSolution; ///< Byte 132 (0x084) (Registered): RDIMM Thermal Heat Spreader = Solution + UINT8 pad[1]; ///< padding added to = eliminate: MemChipDdrio.c(5567): warning C4366: The result of the unary '&'= operator may be unaligned. ie: &((*ChannelNvList)[Channel].ddrCRClkContro= ls) +} DIMM_NVRAM_STRUCT; //struct dimmNvram + +#define MAX_CMD_CSR 16 +#define MAX_SIDE 2 + +/// +/// Channel information stored in NVRAM +/// +typedef struct channelNvram { + UINT8 enabled; ///< 0 =3D channel disabled, 1 =3D= channel enabled + UINT8 mb3trainingfailure; + UINT8 features; ///< Bit mask of features to enabl= e or disable + UINT8 maxDimm; ///< Number of DIMM + UINT8 numRanks; ///< Number of ranks on this chann= el + UINT8 numQuadRanks; ///< Number of QR DIMMs on this ch= annel + UINT8 timingMode; ///< Command timing mode(1N, 2N, o= r 3N) for normal operation + UINT8 trainTimingMode; ///< Command timing mode(1N, 2N, o= r 3N) for training + UINT8 ckeMask; ///< CKE signals to assert during = IOSAV mode + UINT8 chFailed; ///< ddr4 memory in this channel h= ad failed (MFO) + UINT8 ngnChFailed; ///< NGN memory in this channel ha= d failed (MFO) + struct comTime common; ///< Common timings for this chann= el + struct dimmNvram dimmList[MAX_DIMM]; + struct RankCh rankPerCh[MAX_RANK_CH]; + UINT32 dimmVrefControlFnv1; + UINT32 dimmVrefControlFnv1Sa; // SA fub + UINT32 ddrCrCmdPiCodingFnv; + UINT32 ddrCrCmdPiCodingFnv2; + UINT8 encodedCSMode; + UINT8 cidBitMap; + UINT8 txVrefSafe[MAX_RANK_CH]; + UINT8 dimmRevType; + UINT8 lrDimmPresent; +#ifdef LRDIMM_SUPPORT + UINT8 chOneRankTimingModeEnable; +#endif + UINT8 lrRankMultEnabled; + UINT8 v110NotSupported; + UINT8 v120NotSupported; + UINT32 rankErrCountStatus; + UINT32 rankErrCountInfo[(MAX_RANK_CH * SUB_CH)/2]; + UINT32 rankErrThresholdInfo[(MAX_RANK_CH * SUB_CH)/2]; + UINT8 ddrtEnabled; + UINT32 SmiSpareCtlMcMainExt; + UINT8 spareInUse; + UINT8 spareDimm[MAX_RANK_CH/2]; + UINT8 spareRank[MAX_RANK_CH/2]; + UINT16 spareRankSize[MAX_RANK_CH/2]; + UINT8 spareLogicalRank[MAX_SPARE_RANK]; + UINT8 sparePhysicalRank[MAX_SPARE_RANK]; + UINT32 ioLatency1; + UINT32 tcrwp; ///< TCRWP_MCDDC_CTL_STRUCT + UINT32 tcothp; ///< TCOTHP_MCDDC_CTL_STRUCT + UINT32 tcothp2; + UINT32 TCMr0Shadow; + UINT32 TCMr2Shadow; + UINT32 TCMr4Shadow; + UINT32 TCMr5Shadow; + INT16 normalizationFactor; + UINT8 FmcWrCreditLimit; + UINT8 FmcRdCreditLimit; + UINT8 twoXRefreshSetPerCh; /* Saves the refreshRate value f= or each channel */ + UINT8 tCCDAdder; + BUS_TYPE fnvAccessMode; + UINT32 ddrtDimm0BasicTiming; + UINT32 ddrtDimm1BasicTiming; + UINT32 cadbMuxPattern[CADB_MUX_MAX]; + UINT8 EccModeMcMain[(MAX_RANK_CH * SUB_CH)]; + UINT32 Plus1Failover[(MAX_RANK_CH * SUB_CH)]; + UINT32 LinkRetryErrLimits; + UINT32 LinkLinkFail; + UINT32 mtCas2CasDr; /* CNX Change */ + UINT32 mtCas2CasDd; /* CNX Change */ + UINT32 mtCas2CasSr; /* CNX Change */ + UINT32 mtCas2CasSg; /* CNX Change */ + UINT32 mtCas2CasDs; /* CNX Change */ + UINT32 tCke; /* CNX Change */ + UINT32 MemoryTimingsAdj; + UINT8 T_rrdr_org; ///< Nvram Variable to store original tR= RDR turnaround timing parameter + UINT8 T_rrdd_org; ///< Nvram Variable to store original tR= RDD turnaround timing parameter + UINT8 T_rrdr; ///< Nvram Variable to store current tRRDR t= urnaround timing parameter + UINT8 T_rrdd; ///< Nvram Variable to store current tRRDD t= urnaround timing parameter +#ifndef DDRIO_DATA_1S + UINT32 dataControl0; + UINT32 dataControl1[MAX_STROBE]; ///< need to save for = each strobe + UINT32 dataControl2[MAX_STROBE]; + UINT32 dataControl4[MAX_STROBE]; + UINT32 dataControl3[MAX_STROBE]; + UINT32 dataOffsetComp[MAX_STROBE]; + UINT8 DrvStaticLegCfg[MAX_STROBE]; + UINT8 OdtSegmentEnable[MAX_STROBE]; + UINT8 DataSegmentEnable[MAX_STROBE]; + UINT8 RcompCode[MAX_STROBE]; + UINT32 LegacyRxDfeTxEcho[MAX_STROBE]; //Used to store Legac= y RxDfe or TxEcho register values + UINT32 ddrCRClkControls; + UINT32 DdrCrCmdNControls; + UINT32 DdrCrCmdSControls; + UINT32 DdrCrCkeControls; + UINT32 DdrCrCtlControls; + UINT32 clkCsr; + INT16 TxDqsDelay[MAX_RANK_CH][MAX_STROBE]; + UINT32 txGroup0[MAX_RANK_CH][MAX_STROBE]; + UINT32 txGroup1[MAX_RANK_CH][MAX_STROBE]; + UINT32 TxEqCoefTap2[MAX_RANK_CH][MAX_STROBE]; + UINT16 XtalkDeltaN0[MAX_RANK_CH][MAX_STROBE]; + UINT16 XtalkDeltaN1[MAX_RANK_CH][MAX_STROBE]; + UINT32 txTco[MAX_RANK_CH][MAX_STROBE]; + UINT32 rxGroup0[MAX_RANK_CH][MAX_STROBE]; + UINT32 rxGroup1[MAX_RANK_CH][MAX_STROBE]; + UINT32 RxDfeCoeff[MAX_STROBE]; + UINT32 RxDfeControl[MAX_STROBE]; + UINT32 rxOffset[MAX_RANK_CH][MAX_STROBE]; + UINT32 rxVrefCtrl[MAX_STROBE]; + UINT8 txVrefCache[MAX_RANK_CH][MAX_STROBE]; ///< Cached valu= e of txVref (this might not be the programmed value) + UINT8 txVref[MAX_RANK_CH][MAX_STROBE]; ///< Actual curr= ent value of txVref + UINT32 ddrCRCmdTrainingCmdN; + UINT32 ddrCRCmdTrainingCmdS; + UINT32 ddrCRCtlTraining; + UINT32 ddrCRCkeTraining; + UINT32 ddrCRClkTraining; + UINT32 ddrCRClkRanksUsed; + UINT32 dataOffsetTrain[MAX_STROBE]; + UINT32 DataTrainFeedbackMultiCast; + UINT32 ddrCRCmdControls3CmdN; + UINT32 ddrCRCmdControls3CmdS; + UINT32 ddrCRCmdControls3Ctl; + UINT32 ddrCRCmdControls3Cke; + UINT32 cmdCsr[MAX_CMD_CSR]; + UINT32 rxGroup1n[MAX_RANK_CH][MAX_STROBE]; /* CNX Change */ + UINT32 rxGroup1p[MAX_RANK_CH][MAX_STROBE]; /* CNX Change */ + UINT32 DdrCrintfDataTiming0; + UINT32 TxDqBitClockDelta[MAX_RANK_CH][MAX_STROBE]; ///< Each= unit represent 64 ticks + ///< [7:0= ] -> UIs for Bit 0 + ///< [15:= 8] -> UIs for Bit 1 + ///< [23:= 16] -> UIs for Bit 2 + ///< [31:= 24] -> UIs for Bit 3 + UINT32 EnableRidUnderfillOrg; ///< Nvram Variable to store = original EnableRidUnderfill RDB entry + UINT32 EnableRidVc2Org; ///< Nvram Variable to store = original EnableRidVc2 RDB entry + UINT32 EnableRidVc3Org; ///< Nvram Variable to store = original EnableRidVC3 RDB entry +#endif // !DDRIO_DATA_1S +} CHANNEL_NVRAM_STRUCT, *PCHANNEL_NVRAM_STRUCT; + +/// +/// IMC information stored in NVRAM +/// +typedef struct imcNvram { + UINT8 enabled; ///< 0 =3D imc disabled, 1 =3D imc= enabled + UINT32 scrubMask; ///< Scrub mask + UINT32 scrubMask2; ///< Scrub mask2 + UINT8 EmcaLtCtlMcMainExt; + UINT32 ExRasConfigHaCfg; + UINT32 SmiSpareCtlMcMainExt; + UINT8 AppDirectHoleSize; + UINT8 imcNodeId; /* System wide socket id f= or imc */ + BOOLEAN LaneReversalEn; +#ifndef DDRIO_DATA_1S + UINT32 ddrCRCompCtl0; + UINT32 ddrCRCompCtl3; // This is need for silicon workaroun= d 'S1409370801' + UINT32 dimmVrefControl1; +#endif // !DDRIO_DATA_1S +} IMC_NVRAM_STRUCT; //struct imcNvram + +/// +/// Socket information stored in NVRAM +/// +struct socketNvram { + UINT8 enabled; + INT32 minTCK; ///< minimum tCK for this DI= MM + UINT8 ddrFreq; ///< DDR Frequency of this s= ocket + UINT16 ddrFreqMHz; ///< DDR Frequency of this s= ocket in MHz + UINT16 QCLKps; ///< Qclk period in pS + UINT8 cmdClkTrainingDone; + UINT8 ddrVoltage; ///< Voltage of this socket + UINT8 lrDimmPresent; + UINT8 DcpmmPresent; + BOOLEAN x16DimmPresent; + UINT8 maxDimmPop; ///< Maximum number of DIMM = populated on a channel for a socket + UINT8 wa; ///< Bit field for workaroun= ds + UINT8 ddr4SpdPageEn; + struct channelNvram channelList[MAX_CH]; + struct imcNvram imc[MAX_IMC]; + UINT64_STRUCT procPpin; ///< Processor PPIN number + UINT32 smiCtrlUboxMisc; + UINT8 refreshRate; + INT8 normalizationFactorEn; + UINT16 WdbCacheValidPerChannel; ///< Channel bitmask= indicating whether the WDB cache is valid + TRAINING_STEP_DONE_STRUCT TrainingStepDone; ///< Indicators of wheth= er a given training step is done + UINT8 ddrtFreq; + UINT8 cmdVrefTrainingDone; + UINT8 mcpPresent; + UINT32 FaultyPartsFlag[MAX_CH]; ///< Store faulty str= obe info in a channel to NVRAM + UINT32 CsrWriteLatency[MAX_CH]; ///< CSR Write Latenc= y from Core-Ubox-iMC[ch] roundtrip + UINT32 CsrReadLatency[MAX_CH]; ///< CSR Read Latency= from Core-Ubox-iMC[ch] roundtrip +}; //struct socketNvram +typedef struct socketNvram SOCKET_NVRAM; + +typedef struct memNvram { + UINT8 DataGood; ///< Set to one if valid dat= a is present in this structure + UINT8 RASmode; ///< RAS mode (lockstep, mir= ror, sparing) + UINT16 RASmodeEx; ///< Extended RAS mode (patr= ol scrub) + UINT8 ratioIndex; ///< Index into the DDR3 rat= io table + UINT8 eccEn; ///< Set if ECC will be enab= led + UINT8 dimmTypePresent; ///< Type of DIMMs populated= (RDIMM,UDIMM,SODIMM) + UINT8 DcpmmPresent; ///< Is an DCPMM present in = the system? + UINT16 dramType; ///< DDR3 or DDR4 (from keyb= yte in SPD) + UINT32 scrambleSeed; ///< Data scrambling seed + UINT32 socketBitMap; ///< CPU present mask + UINT8 ExtendedADDDCEn; + struct memSetup savedSetupData; + struct socketNvram socket[MAX_SOCKET]; + + UINT8 XMPProfilesSup; + UINT8 XMPProfilesRevision; + struct memTiming profileMemTime[2]; + + UINT16 Crc16; + BOOLEAN FmcCacheDone; ///< Variable to indicate FM= C Register caching is finished + UINT8 threeDsModeDisabled; ///< Variable to track if 3D= S mode is enabled/disabled for CPGC + UINT8 volMemMode; + UINT8 CacheMemType; ///< Only valid if volMemMod= e is 2LM +#ifdef DDRIO_DATA_1S + UINT8 DdrioNvdata[DDRIO_DATA_1S * MAX_SOCKET]; +#endif // DDRIO_DATA_1S +#ifdef DRAM_DATA_1S + UINT8 DramNvdata[DRAM_DATA_1S * MAX_SOCKET]; +#endif // DRAM_DATA_1S +#ifdef RCD_DATA_1S + UINT8 RcdNvdata[RCD_DATA_1S * MAX_SOCKET]; +#endif // RCD_DATA_1S +#ifdef LRDIMM_DB_DATA_1S + UINT8 DbNvdata[LRDIMM_DB_DATA_1S * MAX_SOCKET]; +#endif // LRDIMM_DB_DATA_1S + +} MEM_NVRAM_STRUCT; + +// +// Max number for FMC cache register and structure +// +#define MAX_FMC_CACHE 2 + +struct FmcCacheSt { + UINT8 Status; // Cache status + UINT32 Reg; // Register + UINT32 Data; // Data +}; // struct FmcCacheSt + + +/// +/// Rank info +/// +struct rankDevice { + UINT16 MR0; ///< MR0 value for this rank + UINT16 MR1; ///< MR1 value for this rank + UINT16 MR2; ///< MR2 value for this rank + UINT16 MR3; ///< MR3 value for this rank + UINT16 MR4; ///< MR4 value for this rank + UINT16 MR5; ///< MR5 value for this rank + UINT16 MR6[MAX_STROBE]; ///< MR6 value for this rank/dram +#ifdef LRDIMM_SUPPORT + UINT8 CurrentLrdimmTrainingMode; + UINT8 CurrentDramMode; + UINT16 CurrentMpr0Pattern; + UINT8 lrbufRxVrefCache[MAX_STROBE]; + UINT8 cachedLrBuf_FxBC2x3x[MAX_STROBE]; + UINT8 cachedLrBuf_FxBC4x5x[MAX_STROBE]; + UINT8 cachedLrBuf_FxBC8x9x[MAX_STROBE]; + UINT8 cachedLrBuf_FxBCAxBx[MAX_STROBE]; + UINT8 cachedLrBuf_FxBCCxEx[MAX_STROBE/2]; + UINT8 cachedLrBuf_FxBCDxFx[MAX_STROBE/2]; +#endif + UINT32 lrbufTxVrefCache[MAX_STROBE]; +}; //struct rankDevice + +/// +/// DIMM info +/// List ordered by proximity to Host (far to near) +/// +typedef struct dimmDevice { + INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_= TCK) +#ifdef DEBUG_CODE_BLOCK + UINT32 tCL; + UINT16 tRCD; + UINT16 tRP; +#endif // DEBUG_CODE_BLOCK + UINT16 NVmemSize; + UINT16 memSize; ///< Memory size for this DIMM (64MB gra= nularity) + UINT16 UnmappedMemSize; + struct rankDevice rankStruct[MAX_RANK_DIMM]; + struct FmcCacheSt FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status + UINT8 SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DI= MM partitionRatios + UINT8 CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MA= X_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB + BOOLEAN FmcWdbFlushFailed; /// < 0 =3D WDB flush failed on p= revious boot, 1 =3D WDB flush completed w/o errors on previous boot + BOOLEAN EadrFlushFailed; /// < 0 =3D Extended ADR flush fa= iled on previous boot, 1 =3D Extended ADR flush completed w/o errors on pre= vious boot +} DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice + +/// +/// DDRT DIMM info +/// +typedef struct { + UINT16 NgnLogSeqNum[NGN_LOG_TYPE_NUM][NGN_LOG_LEVEL_NUM]; + UINT16 NgnMaxLogEntries[NGN_LOG_TYPE_NUM][NGN_LOG_LEVEL_N= UM]; + UINT8 NvdimmLinkFailOnPrevBoot : 1, /* Link failure was= detected in this boot */ + NvdimmMediaErrLogged : 1, /* Media error log = was detected in this boot */ + NvdimmTempErrLogged : 1, /* Fatal temperatur= e error log was detected in this boot */ + NvdimmUnmapped : 1, /* NVDIMM is not to= be mapped per memory population POR enforcement or SKU Limit violation. */ + NvdimmUnmappedReason : 1, /* Reason of NVDIMM= is not to be mapped 0 - population POR enforcement, 1 - SKU Limit Violatio= n */ + NvdimmRemapped : 1, /* NVDIMM is not to= be unmapped per memory population POR enforcement. */ + NvdimmAdModeNotEnabled : 1, /* Indicates whethe= r DIMM SKU reports AD mode enabled or not */ + Reserved : 1; + UINT64_STRUCT NgnBsr; /* NGN NVDIMM Boot = Status Register */ +} HOST_DDRT_DIMM_DEVICE_INFO_STRUCT; + +typedef struct { + UINT8 WdbLine[MRC_WDB_LINE_SIZE]; +} TWdbLine; + +/// +/// TT channel info +/// +typedef struct ddrChannel { + UINT8 mcId; /// comparisons; mor= e significant bits are used for match comparison only + UINT32 bankPair : 4; + UINT32 logicalSubRank : 3; + UINT32 logicalRank : 3; + UINT32 upperBgMask : 2; // bit-0 =3D 1 means failure with upper BG bit= =3D 0; bit-1 =3D 1 means failure with upper BG =3D 1 + UINT32 rfu: 1; + UINT32 valid : 1; + } Bits; + UINT32 Data; +} ROW_ADDR; + +typedef struct { + ROW_ADDR addr; + UINT32 size; + UINT32 mask[3]; +} ROW_FAIL_RANGE; + +/// +/// socket info +/// +typedef struct Socket { + UINT8 SocketDieCount; ///< Number of cpu die= s present in the socket + UINT32 NumMemSs; + MRC_MSM MemSsList[MAX_MEM_SS]; + BOOLEAN ImcPresent[MAX_IMC]; ///< on multi-die, som= e iMCs might not exist + UINT8 imcEnabled[MAX_IMC]; + UINT8 fatalError; + UINT8 majorCode; + UINT8 minorCode; + UINT8 maxRankDimm; ///< Maximum number or= ranks supported per DIMM + UINT32 memSize; ///< DDR4 memory size = for this socket (64MB granularity) + TRAINING_STATUS_STRUCT TrainingStatus; + struct ddrChannel channelList[MAX_CH]; + UINT8 socketSubBootMode; + UINT8 hostRefreshStatus; + UINT8 firstJEDECDone; ///< Flag to indicate = the first JEDEC Init has executed + UINT64_STRUCT procPpin; + UINT8 cadbMRSMode; ///< Mode of operation= (LOAD / EXECUTE / NORMAL) + UINT8 cadbMRSIndex[MAX_CH]; + UINT32 NVmemSize; ///< Memory size for t= his node + UINT32 TotalInterleavedMemSize; ///< DDR4 memory size = for this socket (64MB granularity) + UINT32 TotalInterleavedNVMemSize;///< Actual NVMEM inte= rleaved. + UINT32 volSize; ///< Volatile size of = the NVM dimms for this socket (64MB granularity) + UINT32 perSize; ///< Persistent size o= f the NVM dimms for this socket (64MB granularity) + UINT32 WbCachePerSize; ///< Persistent WB cac= he (AD-WB) size of the NVM dimms for this socket (64MB granularity) + BOOLEAN TurnaroundInitDone; ///< Turnaround Initia= lization Done + MRC_TT CurrentTestType; ///< Training step cur= rently being executed by this socket + SOCKET_CHIP ///< Chip hook to enable Soc= ket fields +} SOCKET_INFO_STRUCT; // struct Socket + +/// +/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot = types and paths through KTI RC/MRC - NormalBoot and S3Resume. +/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, f= ast warm, fast cold, and ADR resume. These are populated +/// at the beginning of MRC so they are not applicable for KTI RC. +/// +typedef enum SubBootMode +{ + ColdBoot =3D 8, // Normal path through MRC with full mem detection= , init, training, etc. + WarmBoot =3D 9, // Warm boot path through MRC. Some functionality = can be skipped for speed. + WarmBootFast =3D 10, // Fast warm boot path uses the NVRAM structure to= skip as much MRC + // code as possible to try to get through MRC = fast. Should be as close + // as possible to the S3 flow. + ColdBootFast =3D 11, // Fast cold boot path uses the NVRAM structure to= skip as much MRC + // code as possible on a cold boot. + AdrResume =3D 12, // ADR flow can skip most of MRC (i.e. take the S3= path) for DIMMs that + // are in self-refresh. But the DIMMs that are n= ot in self-refresh + // must go through more of MRC. + NvDimmResume =3D 13 // NvDimm flow is similar to Adr Batterybackup, bu= t the DIMMs need + // Rx & Mx registers initialized. +} SUB_BOOT_MODE; + +/// +/// define the Training_Result_UP/DOWN CRs struct. +/// +struct TrainingResults { + UINT32 results[4]; +}; + +#ifdef LRDIMM_SUPPORT +struct lrMrecTrainingResults { + UINT8 results; +}; +#endif // LRDIMM_SUPPORT + +#define MEM_CHIP_POLICY_DEF(x) Host->var.mem.memChipPolicy.x +#define MEM_CHIP_POLICY_VALUE(Host, x) Host->var.mem.memChipPolicy.x +typedef struct { + UINT8 maxVrefSettings; // MAX= _VREF_SETTINGS + UINT8 earlyVrefStepSize; // EAR= LY_VREF_STEP_SIZE + INT16 ctlPiGrp; // CTL= _PI_GRP + UINT8 minIoLatency; // MIN= _IO_LATENCY + UINT16 cas2DrvenMaxGap; // CAS= 2DRVEN_MAXGAP + UINT8 mrcRoundTripIoComp; // MRC= _ROUND_TRIP_IO_COMPENSATION; + UINT8 mrcRoundTripIoCompStart; // MRC= _ROUND_TRIP_IO_COMP_START; + UINT8 mrcRoundTripMax; // MRC= _ROUND_TRIP_MAX_VALUE; + UINT32 SrPbspCheckinCsr; // SR_= PBSP_CHECKIN_CSR (BIOSNONSTICKYSCRATCHPAD2_UBOX_MISC_= REG) // UBOX scratchpad CSR02 + UINT32 SrBiosSerialDebugCsr; // SR_= BIOS_SERIAL_DEBUG_CSR(BIOSSCRATCHPAD6_UBOX_MISC_REG) = // UBOX scratchpad CSR6 + UINT32 SrPostCodeCsr; // SR_= POST_CODE_CSR (BIOSNONSTICKYSCRATCHPAD7_UBOX_MISC_REG) = // UBOX scratchpad CSR7 + UINT32 SrErrorCodeCsr; // SR_= ERROR_CODE_CSR (BIOSNONSTICKYSCRATCHPAD8_UBOX_MISC_REG) = // UBOX scratchpad CSR8 + UINT32 SrMemoryDataStorageDispatchPipeCsr; // #de= fine SR_MEMORY_DATA_STORAGE_DISPATCH_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD13_U= BOX_MISC_REG) // UBOX scratchpad CSR13 + UINT32 SrMemoryDataStorageCommandPipeCsr; // #de= fine SR_MEMORY_DATA_STORAGE_COMMAND_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD14_U= BOX_MISC_REG) // UBOX scratchpad CSR14 + UINT32 SrMemoryDataStorageDataPipeCsr; // #de= fine SR_MEMORY_DATA_STORAGE_DATA_PIPE_CSR (BIOSNONSTICKYSCRATCHPAD15_U= BOX_MISC_REG) // UBOX scratchpad CSR15 + UINT32 SrBdatStructPtrCsr; // SR_= BDAT_STRUCT_PTR_CSR + UINT32 BiosStickyScratchPad0; // BIO= SSCRATCHPAD0_UBOX_MISC_REG + UINT8 PerBitMarginDefault; // PER= _BIT_MARGIN_DEFAULT + UINT8 RxOdtDefault; // RX_= ODT_DEFAULT + UINT8 CmdTxEqDefault; // CMD= _TX_EQ_DEFAULT + UINT8 RxDfeDefault; // RX_= DFE_DEFAULT + UINT8 TxRiseFallSlewRateDefault; // TX_= RF_SLEW_RATE_DEFAULT + UINT8 RmtColdFastBootDefault; // RMT= _COLD_FAST_BOOT_DEFAULT + UINT8 RxVrefTrainingMode; // RX_= VREF_TRAINING_MODE + UINT8 TxVrefTrainingMode; // TX_= VREF_TRAINING_MODE + UINT16 MaxPhaseInReadAdjustmentDq; // MAX= _PHASE_IN_READ_ADJUSTMENT_DQ +} MEM_CHIP_POLICY; + +struct DimmDeviceTraining { + UINT8 oneRankTimingModeLrbuf_FxBC2x3x[MAX_STROBE]; + UINT8 oneRankTimingModeLrbuf_FxBC4x5x[MAX_STROBE]; + UINT8 oneRankTimingModeLrbuf_FxBC8x9x[MAX_STROBE]; + UINT8 oneRankTimingModeLrbuf_FxBCAxBx[MAX_STROBE]; + UINT8 oneRankTimingModeLrbuf_FxBCCxEx[MAX_STROBE/2]; + UINT8 oneRankTimingModeLrbuf_FxBCDxFx[MAX_STROBE/2]; + UINT8 originalRank0Lrbuf_FxBC2x3x[MAX_RANK_DIMM][MAX_STROBE]; + UINT8 originalRank0Lrbuf_FxBC4x5x[MAX_RANK_DIMM][MAX_STROBE]; + UINT8 originalRank0Lrbuf_FxBC8x9x[MAX_RANK_DIMM][MAX_STROBE]; + UINT8 originalRank0Lrbuf_FxBCAxBx[MAX_RANK_DIMM][MAX_STROBE]; + UINT8 originalRank0Lrbuf_FxBCCxEx[MAX_RANK_DIMM][MAX_STROBE/2]; + UINT8 originalRank0Lrbuf_FxBCDxFx[MAX_RANK_DIMM][MAX_STROBE/2]; +}; //struct DimmDeviceTraining + +/// TT channel info +/// +struct DdrChannelTraining { + TWdbLine WdbLines[MRC_WDB_LINES]; + struct DimmDeviceTraining dimmList[MAX_DIMM]; +}; //struct DdrChannelTraining + +struct TrainingVariable { + UINT8 rdVrefLo; + UINT8 rdVrefHi; + UINT8 wrVrefLo; + UINT8 wrVrefHi; + UINT8 cmdVrefLo; + UINT8 cmdVrefHi; + UINT8 DQPat; ///< Global Variables storing the current DQPat REU= T Test + UINT8 DQPatLC; ///< Global Variables storing the current DQPat Loo= pcount + BOOLEAN EnDumRd; ///< Enable/Disable Logic Analizer + + INT16 TxDqLeft[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 TxDqRight[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 TxVrefLow[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 TxVrefHigh[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 RxDqsLeft[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 RxDqsRight[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 RxVrefLow[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + INT16 RxVrefHigh[MAX_CH][MAX_RANK_CH][MAX_STROBE]; + + struct DdrChannelTraining channelList[MAX_CH]; +}; //struct TrainingVariable + +/// +/// Indicates how SPD data should be retrieved: +/// SpdSmbus Data should be retrieved via SMBUS +/// SpdInternal Data should be retrieved via internal SPD array +/// SpdInternalTrace Data should be retrieved via internal SPD array, bu= t the SMBUS transactions should still be +/// carried out to generate register traces for debug= ging +/// +typedef enum { + SpdSmbus, + SpdInternal, + SpdInternalTrace, + SpdMax +} SPD_SOURCE; + +// +// CMI Read and Write credit configuration register defaults +// +typedef struct { + UINT32 CmiRdCreditConfigN0; + UINT32 CmiRdCreditConfigN1; + UINT32 CmiWrCreditConfigN0; + UINT32 CmiWrCreditConfigN1; + BOOLEAN Valid; /// Set to TRUE when structure is upda= ted +} CMI_CREDIT_CONFIG_DEFAULT; + +/// +/// TT Host info +/// +typedef struct memVar { + UINT8 currentSocket; ///< Current socket being init= ialized + UINT8 PostCodeMinor; + SUB_BOOT_MODE subBootMode; ///< WarmBoot, WarmBootFast, e= tc. + UINT8 wipeMemory; ///< Write 0 to all memory to = clean secrets + UINT8 skipMemoryInit; ///< Skip memory init based on= certain conditions. + UINT8 ddrFreqLimit; ///< Set to limit frequency by= the user + UINT8 chInter; ///< Number of ways to interle= ave channels (1,2,3, or 4) + UINT8 callingTrngOffstCfgOnce; /// + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _memhostchipcommon_h +#define _memhostchipcommon_h + + +#include "SysHostChipCommon.h" +#include "NGNDimmPlatformCfgData.h" +#include +#include + +#define MAX_MEM_SS 8 // Max Memory Subsystems p= er socket +#define MAX_CLUSTERS 4 // Maximum number of clust= ers supported + +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max nu= mber of memory nodes +#define MAX_DIMM 2 // Max DI= MM per channel +#define MAX_DDRT_DIMM_PER_CH 1 // Max DD= RT DIMM per channel +#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max nu= mber of unique interleaves for NGN DIMM + +#define MAX_BITS 72 // Max number of data bits per rank +#define MAX_TECH 19 // Number of entries in DR= AM technology table +#define MAX_TECH_DDRT 8 + +#define TAD_RULES 8 // Number of near memory T= AD rule registers +#define FM_TAD_RULES 12 // Number of far memory TA= D rule registers +#define FM_TAD_RULES_10NM 4 // Number of far memory on= ly TAD rule registers in 10nm +#define MAX_TAD_RULES (TAD_RULES + FM_TAD_RULES) // Number of c= ombined near and far TAD rules +#define MAX_TAD_RULES_10NM (TAD_RULES + FM_TAD_RULES_10NM) // Number of c= ombined near and far TAD rules in 10nm +#define MAX_TAD_WAYS 3 // Number of interleave wa= ys for TAD RULES +#define MAX_RT_WAYS 8 // Max. interleave ways fo= r DDR/DDRT RTs in 256B McChan granularity +#define MAX_RT 2 // Number of RTs per route= table type +#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets ex= ists on ICX platform + +#define MAX_STROBE 18 // Number of strobe groups + +#define MAX_RANK_DIMM_3DS 2 // Max physical CS ranks p= er 3DS DIMM +#define MAX_SUBRANK_3DS 4 // Max logical C[2:0] subr= anks per CS in 3DS DIMM +#define MAX_SPARE_RANK 2 // Max number of spare ran= ks in a channel +#define MAX_SUBRANK 2 // Max subranks per logica= l rank +#define SPD_MODULE_PART_DDR4 20 // Number of bytes of modu= le part - DDR4 +#define SPD_MODULE_SERIAL 4 // Number of bytes of Modu= le Serial Number +#define MAX_PARTIAL_MIRROR 4 //Maximum number of partia= l mirror regions that can be created + +#define CONVERT_64MB_TO_4KB_GRAN 14 +#define CONVERT_4KB_TO_64MB_GRAN 14 +#define CONVERT_64MB_TO_GB_GRAN 4 +#define CONVERT_GB_TO_64MB_GRAN 4 +#define CONVERT_64MB_TO_MB_GRAN 6 +#define CONVERT_MB_TO_64MB_GRAN 6 +#define CONVERT_64MB_TO_4GB_GRAN 6 +#define CONVERT_4GB_TO_64MB_GRAN 6 +#define CONVERT_64MB_TO_32GB_GRAN 9 +#define CONVERT_64B_TO_64MB 20 +#define CONVERT_B_TO_MB 20 +#define CONVERT_MB_TO_B 20 +#define CONVERT_B_TO_64MB 26 +#define CONVERT_64MB_TO_B 26 +#define CONVERT_64MB_TO_128MB_GRAN 1 +#define CONVERT_256MB_TO_64MB_GRAN 2 +#define CONVERT_64MB_TO_256MB_GRAN 2 +#define CONVERT_B_TO_256MB_GRAN 28 + +#define MEM_1GB_AT_64MB_GRAN 0x10 +#define MEM_1GB_AT_4KB_GRAN 0x40000 + +#define GB_TO_MB_CONVERSION 1024 + +#define BITMAP_CH0_CH1_CH2 ( ( BIT0 ) | (BIT1 ) | (BIT2) ) +#define BITMAP_CH0_CH1 ( ( BIT0 ) | (BIT1 ) ) +#define BITMAP_CH1_CH2 ( ( BIT1 ) | (BIT2 ) ) +#define BITMAP_CH0_CH2 ( ( BIT0 ) | (BIT2 ) ) +#define BITMAP_CH0 BIT0 +#define BITMAP_CH1 BIT1 +#define BITMAP_CH2 BIT2 + +#define CONVERT_64MB_TO_BYTE 64 * 1024 * 1024 + +// +// Define the WDB line. The WDB line is like the cache line. +// +#define MRC_WDB_LINES 32 +#define MRC_WDB_LINE_SIZE 64 + +#define MAX_PHASE_IN_FINE_ADJUSTMENT 64 +#define MAX_PHASE_IN_READ_ADJ_DQ_RX_DFE 152 // larger range for added= DQ 1/16 PI adjustments + +#pragma pack(1) +typedef struct TADTable { + UINT8 Enable; // Rule enable + UINT8 SADId; // SAD Index + UINT8 socketWays; // Socket Interleave ways for TAD + UINT8 NmTadIndex; // Index of near memory TAD + UINT8 FmTadIndex; // Index of far memory TAD + UINT32 Limit; // Limit of the current TAD entry + UINT8 TargetGran; // MC granularity of 1LM forward and 2LM for= ward/reverse address decoding. + UINT8 ChGran; // Channel granularity of 1LM forward and 2L= M forward/reverse address decoding. +} TAD_TABLE; + +typedef struct SADTable { + UINT8 Enable; // Rule enable + MEM_TYPE type; // Bit map of memory region types, See defines = 'MEM_TYPE_???' above for bit definitions of the ranges. + UINT8 granularity; // Interleave granularities for current SAD ent= ry. Possible interleave granularity options depend on the SAD entry type. = Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not sup= port any granularity options + UINT32 Base; // Base of the current SAD entry + UINT32 Limit; // Limit of the current SAD entry + UINT8 ways; // Interleave ways for SAD + UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/N= M channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 0= 11b denotes Ch1 & 0 are interleaved + UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM c= hannels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b= denotes Ch1 & 0 are interleaved + UINT8 NmChWays; // Channel Interleave ways for SAD. Represent= s channelInterBitmap ways for DDR4/NM. + UINT8 FmChWays; // Channel Interleave ways for SAD. Represent= s FMchannelInterBitmap ways for DDRT. + UINT8 imcInterBitmap; // Bit map to denote which IMCs are interleav= ed from this socket. + UINT8 NmImcInterBitmap; // Bit map to denote which IMCs are interleav= ed from this socket as NM (10nm usage only). + BOOLEAN local; //0 - Remote 1- Local + UINT8 IotEnabled; // To indicate if IOT is enabled + UINT8 mirrored; //To Indicate the SAD is mirrored while enablin= g partial mirroring + UINT8 Attr; + UINT8 tgtGranularity; // Interleave mode for target list + UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index. +} SAD_TABLE; + +typedef struct IMC { + UINT8 imcEnabled[MAX_IMC]; + UINT8 imcNum; // imc Number + UINT32 memSize; // DDR4 memory size = for this imc (64MB granularity) + UINT32 NVmemSize; // NV Memory size of= this ha + UINT32 volSize; // Volatile size of = the NVM dimms for this imc (64MB granularity) + UINT32 NonVolSize; // Non-Volatile size= of the NVM DIMMs for this iMC (64MB granularity) + UINT32 perSize; // Persistent size o= f the NVM dimms for this imc (64MB granularity) + UINT32 WbCachePerSize; // Persistent WB cac= he (AD-WB) size of the NVM dimms for this imc (64MB granularity) + UINT8 TADintList[MAX_TAD_RULES][MAX_TAD_WAYS]; // TAD interleave li= st for this socket + UINT8 TADChnIndex[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD= channel indexes (per channel) + INT32 TADOffset[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD= offsets (per channel) + TAD_TABLE TAD[MAX_TAD_RULES]; // TAD table + UINT8 imcChannelListStartIndex; // Index in channel = list of first channel on this imc +} IMC_INFO_STRUCT; + +typedef struct firmwareRev { + UINT8 majorVersion; + UINT8 minorVersion; + UINT8 hotfixVersion; + UINT16 buildVersion; +} FIRMWARE_REV; + +typedef struct Reserved168 { + UINT8 Reserved79; + UINT8 Reserved80; + UINT8 Reserved83; + UINT8 Reserved86[MAX_SOCKET * MAX_IMC]; + UINT8 Reserved89; + UINT8 Reserved87; + UINT8 Reserved148; +} MEM_RESERVED_1; + +#pragma pack() + +#define MAX_SI_SOCKET 8 // Maximum silicon supported socket n= umber + +typedef struct { + UINT32 BlockDecoderBase; // 64MB unit + UINT32 BlockDecoderLimit; + UINT8 BlockSocketEnable; + UINT8 BlockMcChEn[MAX_SI_SOCKET][MAX_IMC][MAX_MC_CH]; +} MEMORY_MAP_BLOCK_DECODER_DATA; + +// +// Chip specific section of struct Socket +// +#define SOCKET_CHIP \ + struct SADTable SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; = \ + UINT8 DdrtChRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK me= mory channel route table 2 for CR protocol */ \ + UINT8 DdrtTgtRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK me= mory target route table 2 for CR protocol */ \ + struct IMC imc[MAX_IMC]; = \ + UINT8 ddrClkData; = \ + UINT8 ddrClkType; = \ + UINT8 ddrFreqCheckFlag; = \ + UINT8 SktSkuValid; = \ + UINT32 SktSkuLimit; = \ + UINT32 SktTotMemMapSPA; = \ + UINT32 SktPmemMapSpa; = \ + UINT32 SktMemSize2LM; = \ + UINT8 maxFreq; = \ + UINT8 clkSwapFixDis; = \ + UINT8 ioInitdone; + +#endif // _memhostchipcommon_h diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/MemRegs.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Core/Include/MemRegs.h new file mode 100644 index 0000000000..3c8abe4dbb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemRegs.h @@ -0,0 +1,25 @@ +/** @file + MemRegs.h + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _memregs_h +#define _memregs_h + +// +// NVM DIMM Reg Structs +// + +typedef union { + struct { + UINT8 module_type : 4; + UINT8 module_revision : 4; + } Bits; + UINT8 Data; +} SPD_AEP_MOD_REVISION_STRUCT; + +#endif // _memregs_h diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/MrcCommonTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMem= oryCoreLib/Core/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..eba0a14354 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MrcCommonTypes.h @@ -0,0 +1,28 @@ +/** @file + MrcCommonTypes.h + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#include "DataTypes.h" +#include + +typedef struct { + MRC_MST MemSsType; + UINT32 NumDataCh; // Total number of physical data channels = in the MemSS + UINT32 NumDataIoFubsPerCh; // Total number of IO fubs in a data = channel + UINT32 NumDataIoFubsPerSubCh; // Total number of IO fubs in a da= ta sub channel + UINT32 NumDqLanesPerCh; // Number of active DQ lanes in a data c= hannel (bus width) +} MRC_MSM; + +typedef enum { + MrcTtDelim =3D MAX_INT32 +} MRC_TT; + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/NGNDimmPlatformCfgData.h b/Silicon/Intel/WhitleySiliconPkg/Library= /BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h new file mode 100644 index 0000000000..81ea4fc373 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/NGNDimmPlatformCfgData.h @@ -0,0 +1,22 @@ +/** @file + NGNDimmPlatformCfgData.h + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _NGN_DIMM_PLATFORM_CONFIG_DATA_H_ +#define _NGN_DIMM_PLATFORM_CONFIG_DATA_H_ + +#define NGN_MAX_MANUFACTURER_STRLEN 2 +#define NGN_MAX_SERIALNUMBER_STRLEN 4 +#define NGN_MAX_PARTNUMBER_STRLEN 20 +#define NGN_MAX_UID_STRLEN 9 +#define NGN_FW_VER_LEN 4 + +#define NGN_LOG_TYPE_NUM 2 +#define NGN_LOG_LEVEL_NUM 2 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/SysHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Core/Include/SysHost.h new file mode 100644 index 0000000000..d419edea4a --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/SysHost.h @@ -0,0 +1,193 @@ +/** @file + SysHost.h + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SYS_HOST_H_ +#define _SYS_HOST_H_ + +#include "SysHostChipCommon.h" + + + +#define MAX_LINE 256 + +#define RC_SIM_FASTCADB 0 + + + +typedef struct sysHost SYSHOST, *PSYSHOST; + +#include "DataTypes.h" +#include "SysHostChipCommon.h" +#include "PlatformHost.h" +#include "MemHost.h" +#include + +/// +/// Enhanced Warning Log Header +/// +typedef struct { + EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revisi= on + UINT32 Size; /// Total size in bytes including the header and= buffer + UINT32 FreeOffset; /// Offset of the beginning of the free space fr= om byte 0 + /// of the buffer immediately following this str= ucture + /// Can be used to determine if buffer has suffi= cient space for next entry + UINT32 Crc; /// 32-bit CRC generated over the whole size min= us this crc field + /// Note: UEFI 32-bit CRC implementation (Calcul= ateCrc32) (References [7]) + /// Consumers can ignore CRC check if not needed. + UINT32 Reserved; /// Reserved for future use, must be initialized= to 0 +} EWL_HEADER; + +/// +/// Enhanced Warning Log Spec defined data log structure +/// +typedef struct { + EWL_HEADER Header; /// The size will vary by implementation and= should not be assumed + UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffe= r follow the header +} EWL_PUBLIC_DATA; + +/// +/// EWL private data structure. This is going to be implementation depend= ent +/// When we separate OEM hooks via a PPI, we can remove this +/// +typedef struct { + UINT32 bufSizeOverflow; // Number of bytes that could not be= added to buffer + UINT32 numEntries; // Number of entries currently logged + EWL_PUBLIC_DATA status; // Spec defined EWL +} EWL_PRIVATE_DATA; + +#pragma pack(1) + +/// +/// System NVRAM structure +// +struct sysNvram { + struct memNvram mem; + struct commonNvram common; +}; //struct sysNvram + +#pragma pack() + +// +// -----------------------------------------------------------------------= ------ +// Variable structures +// + +typedef struct CpuidRegisterInfo { + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; +} CPUID_REGISTER_INFO; + +typedef struct processorCommon { + UINT32 capid0; + UINT32 capid1; + UINT32 capid2; + UINT32 capid3; + UINT32 capid4; + UINT32 capid5; + UINT32 capid6lo; + UINT32 capid6hi; + CPUID_REGISTER_INFO ExtCpuid7; + CPUID_REGISTER_INFO ExtCpuid1B; +} PROCESSOR_COMMON; + +/// +/// Common variable structure +/// +struct commonVar { + RC_VERSION RcVersion; ///< Version of the re= ference code last executed + UINT32 rcStatus; ///< Non-zero indicate= s fatal error + UINT8 chopType[MAX_SOCKET]; ///< HCC, MCC, LCC, MC= C-DE, LCC-DE (HSX family only) + UINT8 sbsp; ///< Non-zero value in= dicates that the socket is System BSP + UINT16 pmBase; ///< Power Management = Base Address + UINT32 tohmLimit; + UINT32 JumpBuffer; + +#ifdef COMPRESS_RC + UINT32 rcSrc; ///< Decompression sou= rce code pointer + UINT32 rcDest; ///< Decompression des= tination pointer + UINT32 rcDecompressSourceAddr; ///< Decompression rou= tine address of type func(UINT8*Src, UINT8*Dest); +#endif // #ifdef COMPRESS_RC + + UINT32 heapBase; + UINT32 heapSize; + + UINT32 oemVariable; + EWL_PRIVATE_DATA ewlPrivateData; // implementation data= for EWL + struct processorCommon procCom[MAX_SOCKET]; + UINT32 MicroCodeRev; + +#define MAX_PROMOTE_WARN_LIMIT 90 + UINT32 promoteWarnLimit; + UINT16 promoteWarnList[MAX_PROMOTE_WARN_LIMIT]; + UINT32 printfDepth; ///< handle nested cal= ls to get/releasePrintFControl + UINT32 meRequestedSize; /// Size of the memor= y range requested by ME FW, in MB + UINT32 ieRequestedSize; /// Size of the memor= y range requested by IE FW, in MB +}; //struct commonVar + +/// +/// System Variable structure +/// +struct sysVar { + struct memVar mem; + struct commonVar common; +}; //struct sysVar + +// Bit definitions for commonSetup.options +// ; PROMOTE_WARN_EN enables warnings to be treated as f= atal error +// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be trea= ted as fatal error +// ; HALT_ON_ERROR_EN enables errors to loop forever +// ; HALT_ON_ERROR_AUTO auto reset with Maximum Serial p= ort debug message level when fatal error is encountered. +#define PROMOTE_WARN_EN BIT0 +#define PROMOTE_MRC_WARN_EN BIT1 +#define HALT_ON_ERROR_EN BIT2 +#define HALT_ON_ERROR_AUTO BIT3 + +typedef union _RMT_FLAGS { + UINT8 Data; + struct { + UINT8 EnableShortFormat :1; + UINT8 SkipPerBitMargin :1; + UINT8 SkipDisplayPerBitEyes :1; + UINT8 SkipDisplayPerBitMargins :1; + UINT8 SkipRmtRxDqs :1; + UINT8 SkipRmtRxVref :1; + UINT8 SkipRmtTxDq :1; + UINT8 SkipRmtTxVref :1; + } Bits; +} RMT_FLAGS; + +/// +/// System Host (root structure) +/// +struct sysHost { + struct sysVar var; ///< variable, volatile data + struct sysNvram nvram; ///< variable, non-volatile data for S3 an= d fast path + UINT8 ChannelModeOperation; + UINT32 cpuFlows; ///< Which flows to take + UINT32 ktiFlows; + UINT32 qpiFlows; + UINT32 opioFlows; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT32 memFlowsExt2; + UINT32 memFlowsExt3; + + + UINT32 MrcHooksServicesPpi; + UINT32 MrcHooksChipServicesPpi; + + BOOLEAN PrintCsr; // Enable / disable prin= ting CSR + BOOLEAN MtrrCheck; // Check number of used = MTRR's + INT32 DdrioUltSupport; + RMT_FLAGS RmtFlags; +}; + +#endif // #ifndef _SYS_HOST_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/SysHostChipCommon.h b/Silicon/Intel/WhitleySiliconPkg/Library/Base= MemoryCoreLib/Core/Include/SysHostChipCommon.h new file mode 100644 index 0000000000..a507c4fe23 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/SysHostChipCommon.h @@ -0,0 +1,101 @@ +/** @file + SysHostChipCommon.h + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SYSHOST_CHIP_COMMON_H_ +#define _SYSHOST_CHIP_COMMON_H_ + +#include +#include + +// +// CpuPciAccess +// +#define READ_ACCESS 0 +#define WRITE_ACCESS 1 + +// +// -----------------------------------------------------------------------= ------ +// Nvram structures +// +#pragma pack(1) + +typedef union { + struct { + UINT32 Bit0:1; + UINT32 Bit1:1; + UINT32 Bit2:1; + UINT32 Bit3:1; + UINT32 Bit4:1; + UINT32 Bit5:1; + UINT32 Bit6:1; + UINT32 Bit7:1; + UINT32 Bit8:1; + UINT32 Bit9:1; + UINT32 Bit10:1; + UINT32 Bit11:1; + UINT32 Bit12:1; + UINT32 Bit13:1; + UINT32 Bit14:1; + UINT32 Bit15:1; + UINT32 Bit16:1; + UINT32 Bit17:1; + UINT32 Bit18:1; + UINT32 Bit19:1; + UINT32 Bit20:1; + UINT32 Bit21:1; + UINT32 Bit22:1; + UINT32 Bit23:1; + UINT32 Bit24:1; + UINT32 Bit25:1; + UINT32 Bit26:1; + UINT32 Bit27:1; + UINT32 Bit28:1; + UINT32 Bit29:1; + UINT32 Bit30:1; + UINT32 Bit31:1; + } Bits; + UINT32 Data; +} DUMMY_REG; + +// +// -----------------------------------------------------------------------= ------ +// Nvram structures +// + +struct commonNvram { + UINT64_STRUCT cpuFreq; + RC_VERSION RcVersion; // Version of the reference code l= ast executed + UINT8 platformType; + DUMMY_REG TsegBase; + DUMMY_REG TsegLimit; + DUMMY_REG MeMemLowBaseAddr; + DUMMY_REG MeMemHighBaseAddr; + DUMMY_REG MeMemLowLimit; + DUMMY_REG MeMemHighLimit; + DUMMY_REG MeNcMemLowBaseAddr; + DUMMY_REG MeNcMemHighBaseAddr; + DUMMY_REG MeNcMemLowLimit; + DUMMY_REG MeNcMemHighLimit; + DUMMY_REG MeNcMemLowRac; + DUMMY_REG MeNcMemLowWac; + UINT32 IeRequestedSize; + DUMMY_REG IeMemLowBaseAddr; + DUMMY_REG IeMemHighBaseAddr; + DUMMY_REG IeMemLowLimit; + DUMMY_REG IeMemHighLimit; + DUMMY_REG IeNcMemLowBaseAddr; + DUMMY_REG IeNcMemHighBaseAddr; + DUMMY_REG IeNcMemLowLimit; + DUMMY_REG IeNcMemHighLimit; + DUMMY_REG IeNcMemHighRac; + DUMMY_REG IeNcMemHighWac; +}; +#pragma pack() + +#endif // _SYSHOST_CHIP_COMMON_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Plat= form/MemDefaults.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Platform/MemDefaults.h new file mode 100644 index 0000000000..68c2f447c9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/Me= mDefaults.h @@ -0,0 +1,28 @@ +/** @file + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _mem_defaults_h +#define _mem_defaults_h + +// +// SMBUS Clk Period default set by PcdMrcSmbusSpeedDefault +// +#define SMB_CLK_100K 0 +#define SMB_CLK_400K 1 +#define SMB_CLK_700K 2 +#define SMB_CLK_1M 3 + +#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regi= ons that can be created + +// +// Limit of channels to be tested by AdvMemTest +// +#define ADV_MT_LIST_LIMIT 8 +#define ADV_MT_EMPTY_MASK 0xFFFFFFFF + +#endif // _mem_defaults_h diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Plat= form/PlatformHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCor= eLib/Platform/PlatformHost.h new file mode 100644 index 0000000000..aa9b570f63 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/Pl= atformHost.h @@ -0,0 +1,35 @@ +/** @file + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _platformhost_h +#define _platformhost_h + +#include + +// +// Maximum number of processor sockets and cores per socket supported by p= latform. +// +#include +#include + +// +// Post Package Repair +// + +#define MAX_PPR_ADDR_ENTRIES 20 +#define MAX_PPR_ADDR_ENTRIES_SPPR 40 + +#if !defined(SILENT_MODE) +#define DEBUG_CODE_BLOCK 1 +#endif + +#define UBIOS_GENERATION_EN BIT22 // flag to enable DfxU= biosGeneration from Simics +#define HYBRID_SYSTEM_LEVEL_EMULATION_EN BIT23 // flag to enable DfxH= ybridSystemLevelEmulation from Simics + +#endif // _platformhost_h + diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/= FspWrapperPlatformLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrappe= rPlatformLib/FspWrapperPlatformLib.c new file mode 100644 index 0000000000..453e409523 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.c @@ -0,0 +1,243 @@ +/** @file + Sample to provide FSP wrapper related function. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID * +GetPlatformNvs( +) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + VOID *DataBuffer; + UINT32 DataBufferSize; + UINTN VarAttrib; + CHAR16 EfiMemoryConfigVariable[] =3D L"MemoryConfig"; + + DEBUG ((EFI_D_INFO, "Start PlatformGetNvs\n")); + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &PeiVariable + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "PlatformGetNvs: PeiServicesLocatePpi not found\n= ")); + ASSERT (FALSE); + return NULL; + } + + VarAttrib =3D EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS; + DataBufferSize =3D 0; + DataBuffer =3D NULL; + + Status =3D PeiVariable->GetVariable ( + PeiVariable, + EfiMemoryConfigVariable, + &gFspNonVolatileStorageHobGuid, + (UINT32*)&VarAttrib, + &DataBufferSize, + NULL + ); + if (Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variabl= e not found\n")); + return NULL; + } + + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Get Err= or %r\n", Status)); + ASSERT (FALSE); + } + + DataBuffer =3D AllocateZeroPool(DataBufferSize); + Status =3D PeiVariable->GetVariable ( + PeiVariable, + EfiMemoryConfigVariable, + &gFspNonVolatileStorageHobGuid, + (UINT32*)&VarAttrib, + &DataBufferSize, + DataBuffer + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variabl= e Error %r\n", Status)); + return NULL; + } + DEBUG ((EFI_D_INFO, "PlatformGetNvs: GetNVS %x %x\n", DataBuffer, DataBu= fferSize)); + return DataBuffer; +} + +VOID +EFIAPI +UpdateFspmUpdData ( + IN OUT VOID *FspUpdRgnPtr + ) +{ + FSPM_UPD *FspmUpd; + EFI_STATUS Status; + UPI_POLICY_PPI *UpiPolicyPpi; + KTI_HOST_IN *Upi; + UINTN Index; + VOID *FSPTempMem; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + Status =3D PeiServicesLocatePpi (&gUpiSiPolicyPpiGuid, 0, NULL, &UpiPoli= cyPpi); + ASSERT_EFI_ERROR(Status); + + Upi =3D &UpiPolicyPpi->Upi; + FspmUpd =3D (FSPM_UPD*)FspUpdRgnPtr; + + FSPTempMem =3D (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(= PcdPeiTemporaryRamRcHeapSize));; + if (FSPTempMem !=3D NULL) { + FspmUpd->FspmArchUpd.StackBase =3D (VOID*)(((UINTN)FSPTempMem) & (~0xF= FF)); + FspmUpd->FspmArchUpd.StackSize =3D PcdGet32(PcdFspTemporaryRamSize); + } + + for (Index =3D 0; Index < MAX_SOCKET; Index ++) { + FspmUpd->FspmConfig.BusRatio[Index] =3D Upi->BusRatio[Index]; + FspmUpd->FspmConfig.KtiFpgaEnable[Index] =3D Upi->KtiFpgaEnable[Index]; + } + + FspmUpd->FspmConfig.D2KCreditConfig =3D Upi->D2KCreditConfig; + FspmUpd->FspmConfig.SnoopThrottleConfig =3D Upi->SnoopThrottleConfig; + FspmUpd->FspmConfig.LegacyVgaSoc =3D Upi->LegacyVgaSoc; + FspmUpd->FspmConfig.LegacyVgaStack =3D Upi->LegacyVgaStack; + FspmUpd->FspmConfig.P2pRelaxedOrdering =3D Upi->P2pRelaxedOrdering; + FspmUpd->FspmConfig.SncEn =3D Upi->SncEn; + FspmUpd->FspmConfig.UmaClustering =3D Upi->UmaClustering; + FspmUpd->FspmConfig.IoDcMode =3D Upi->IoDcMode; + FspmUpd->FspmConfig.DegradePrecedence =3D Upi->DegradePrecedence; + FspmUpd->FspmConfig.Degrade4SPreference =3D Upi->Degrade4SPreference; + FspmUpd->FspmConfig.DirectoryModeEn =3D Upi->DirectoryModeEn; + FspmUpd->FspmConfig.XptPrefetchEn =3D Upi->XptPrefetchEn; + FspmUpd->FspmConfig.KtiPrefetchEn =3D Upi->KtiPrefetchEn; + FspmUpd->FspmConfig.XptRemotePrefetchEn =3D Upi->XptRemotePrefetchEn; + FspmUpd->FspmConfig.DdrtQosMode =3D Upi->DdrtQosMode; + FspmUpd->FspmConfig.KtiLinkSpeedMode =3D Upi->KtiLinkSpeedMode; + FspmUpd->FspmConfig.KtiLinkSpeed =3D Upi->KtiLinkSpeed; + FspmUpd->FspmConfig.KtiLinkL0pEn =3D Upi->KtiLinkL0pEn; + FspmUpd->FspmConfig.KtiLinkL1En =3D Upi->KtiLinkL1En; + FspmUpd->FspmConfig.KtiFailoverEn =3D Upi->KtiFailoverEn; + FspmUpd->FspmConfig.KtiLbEn =3D Upi->KtiLbEn; + FspmUpd->FspmConfig.KtiCrcMode =3D Upi->KtiCrcMode; + FspmUpd->FspmConfig.KtiCpuSktHotPlugEn =3D Upi->KtiCpuSktHotPlugEn; + FspmUpd->FspmConfig.KtiCpuSktHotPlugTopology =3D Upi->KtiCpuSktHotPlugTo= pology; + FspmUpd->FspmConfig.KtiSkuMismatchCheck =3D Upi->KtiSkuMismatchCheck; + FspmUpd->FspmConfig.IrqThreshold =3D Upi->IrqThreshold; + FspmUpd->FspmConfig.TorThresLoctoremNorm =3D Upi->TorThresLoctoremNorm; + FspmUpd->FspmConfig.TorThresLoctoremEmpty =3D Upi->TorThresLoctoremEmpty; + FspmUpd->FspmConfig.MbeBwCal =3D Upi->MbeBwCal; + FspmUpd->FspmConfig.TscSyncEn =3D Upi->TscSyncEn; + FspmUpd->FspmConfig.StaleAtoSOptEn =3D Upi->StaleAtoSOptEn; + FspmUpd->FspmConfig.LLCDeadLineAlloc =3D Upi->LLCDeadLineAlloc; + FspmUpd->FspmConfig.SplitLock =3D Upi->SplitLock; + FspmUpd->FspmConfig.mmCfgBase =3D Upi->mmCfgBase; + FspmUpd->FspmConfig.mmCfgSize =3D Upi->mmCfgSize; + FspmUpd->FspmConfig.mmiohBase =3D Upi->mmiohBase; + FspmUpd->FspmConfig.CpuPaLimit =3D Upi->CpuPaLimit; + FspmUpd->FspmConfig.highGap =3D Upi->highGap; + FspmUpd->FspmConfig.mmiohSize =3D Upi->mmiohSize; + FspmUpd->FspmConfig.isocEn =3D Upi->isocEn; + FspmUpd->FspmConfig.dcaEn =3D Upi->dcaEn; + FspmUpd->FspmConfig.BoardTypeBitmask =3D Upi->BoardTypeBitmask; + FspmUpd->FspmConfig.AllLanesPtr =3D Upi->AllLanesPtr; + FspmUpd->FspmConfig.PerLanePtr =3D Upi->PerLanePtr; + FspmUpd->FspmConfig.AllLanesSizeOfTable =3D Upi->AllLanesSizeOfTable; + FspmUpd->FspmConfig.PerLaneSizeOfTable =3D Upi->PerLaneSizeOfTable; + FspmUpd->FspmConfig.WaitTimeForPSBP =3D Upi->WaitTimeForPSBP; + FspmUpd->FspmConfig.IsKtiNvramDataReady =3D Upi->IsKtiNvramDataReady; + FspmUpd->FspmConfig.WaSerializationEn =3D Upi->WaSerializationEn; + FspmUpd->FspmConfig.KtiInEnableMktme =3D Upi->KtiInEnableMktme; + FspmUpd->FspmConfig.BoardId =3D PlatformInfo->BoardId; + FspmUpd->FspmArchUpd.NvsBufferPtr =3D GetPlatformNvs(); +} + +/** + This function overrides the default configurations in the FSP-S UPD data= region. + + @param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strc= ture. + +**/ +VOID +EFIAPI +UpdateFspsUpdData ( + IN OUT VOID *FspUpdRgnPtr + ) +{ +} + +/** + Update TempRamExit parameter. + + @note At this point, memory is ready, PeiServices are available to use. + + @return TempRamExit parameter. +**/ +VOID * +EFIAPI +UpdateTempRamExitParam ( + VOID + ) +{ + return NULL; +} + +/** + Get S3 PEI memory information. + + @note At this point, memory is ready, and PeiServices are available to u= se. + Platform can get some data from SMRAM directly. + + @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase. + @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase. + + @return If S3 PEI memory information is got successfully. +**/ +EFI_STATUS +EFIAPI +GetS3MemoryInfo ( + OUT UINT64 *S3PeiMemSize, + OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Perform platform related reset in FSP wrapper. + + This function will reset the system with requested ResetType. + + @param[in] FspStatusResetType The type of reset the platform has to per= form. +**/ +VOID +EFIAPI +CallFspWrapperResetSystem ( + IN UINT32 FspStatusResetType + ) +{ + // + // Perform reset according to the type. + // + + CpuDeadLoop(); +} diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/= FspWrapperPlatformLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrap= perPlatformLib/FspWrapperPlatformLib.inf new file mode 100644 index 0000000000..625337c453 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.inf @@ -0,0 +1,71 @@ +## @file +# Sample to provide FSP wrapper platform related function. +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseFspWrapperPlatformLibSample + FILE_GUID =3D 12F38E73-B34D-4559-99E5-AE2DCD002156 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspWrapperPlatformLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperPlatformLib.c + + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec + +[Ppis] + gUpiSiPolicyPpiGuid + gEfiPeiReadOnlyVariable2PpiGuid + +[Guids] + gEfiPlatformInfoGuid + gFspNonVolatileStorageHobGuid + +[LibraryClasses] + PeiServicesLib + +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSUMES diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c= b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c new file mode 100644 index 0000000000..b06342c12a --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c @@ -0,0 +1,259 @@ +/** @file + Library functions for SetupLib. + This library instance provides methods to access Setup option. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Gets the data and size of a variable. + + Read the EFI variable (VendorGuid/Name) and return a dynamically allocat= ed + buffer, and the size of the buffer. If failure return NULL. + + @param Name String part of EFI variable name + @param VendorGuid GUID part of EFI variable name + @param VariableSize Returns the size of the EFI variable th= at was + read + + @return Dynamically allocated memory that contains a copy of the EFI var= iable. + Caller is responsible freeing the buffer via FreePages. + + @retval NULL Variable was not read + +**/ +VOID * +EFIAPI +GetVariableAndSize ( + IN CHAR16 *Name, + IN EFI_GUID *Guid, + IN UINTN BufferSize + ) +{ + EFI_STATUS Status; + VOID *Buffer =3D NULL; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D GetPeiServicesTablePointer (); + (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &PeiVariable + ); + + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); + if (Buffer =3D=3D NULL) { + return NULL; + } + // + // Read variable into the allocated buffer. + // + Status =3D PeiVariable->GetVariable (PeiVariable, Name, Guid, NULL, &Buf= ferSize, Buffer); + ASSERT_EFI_ERROR (Status); + + return Buffer; +} + +/** + Retrieves the specified group space. + + @param[in] Guid Pointer to a 128-bit unique value that desi= gnates which namespace + to set a value from. + @reture GroupInfo The found group space. NULL will return if = not found. +**/ +UINTN +InternalGetGroupInfo ( + IN EFI_GUID *Guid + ) +{ + UINTN Index; + + if (Guid =3D=3D NULL) { + return MAX_ADDRESS; + } + + // + // Find the matched GUID space. + // + for (Index =3D 0; mSetupInfo[Index].GuidValue !=3D NULL; Index ++) { + if (CompareGuid (mSetupInfo[Index].GuidValue, Guid)) { + break; + } + } + + // + // No matched GUID space + // + if (mSetupInfo[Index].GuidValue =3D=3D NULL) { + return MAX_ADDRESS; + } + + return Index; +} + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] OptionNumber The option number to retrieve a current value = for. + @param[out] DataType A pointer to basic data type of the retrieved = data. + It is optional. It could be NULL. + @param[in, out] Data A pointer to the buffer to be retrieved. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN OUT VOID *Data, + IN UINTN DataSize + ) +{ + UINTN GroupIndex; + VOID *Variable =3D NULL; + + if (Guid =3D=3D NULL || DataSize =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + GroupIndex =3D InternalGetGroupInfo (Guid); + if (GroupIndex =3D=3D MAX_ADDRESS) { + return EFI_NOT_FOUND; + } + + Variable =3D GetVariableAndSize ( + mSetupInfo[GroupIndex].SetupName, + Guid, + mSetupInfo[GroupIndex].VariableSize + ); + if (Variable =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + CopyMem (Data, (UINT8 *)Variable + OptionNumber, DataSize); + + return EFI_SUCCESS; +} + +/** + Get all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +GetEntireConfig ( + IN OUT SETUP_DATA *SetupData + ) +{ + VOID *Variable; + UINTN Index; + UINT8 *SetupDataPtr; + + if (SetupData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + SetupDataPtr =3D (UINT8 *)SetupData; + ZeroMem (SetupDataPtr, sizeof (SETUP_DATA)); + + for (Index =3D 0; mSetupInfo[Index].GuidValue !=3D NULL; Index ++) { + + Variable =3D NULL; + Variable =3D GetVariableAndSize ( + mSetupInfo[Index].SetupName, + mSetupInfo[Index].GuidValue, + mSetupInfo[Index].VariableSize + ); + ASSERT (Variable !=3D NULL); + if (Variable =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + CopyMem (SetupDataPtr, Variable, mSetupInfo[Index].VariableSize); + SetupDataPtr =3D SetupDataPtr + mSetupInfo[Index].VariableSize; + + FreePages (Variable, EFI_SIZE_TO_PAGES (mSetupInfo[Index].VariableSize= )); + } + + return EFI_SUCCESS; +} + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] Variable Pointer to data location where variable is sto= red. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetSpecificConfigGuid ( + IN EFI_GUID *Guid, + OUT VOID *Variable + ) +{ + EFI_STATUS Status; + UINTN GroupIndex; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + CONST EFI_PEI_SERVICES **PeiServices; + + if ((Guid =3D=3D NULL) || (Variable =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + GroupIndex =3D InternalGetGroupInfo (Guid); + if (GroupIndex =3D=3D MAX_ADDRESS) { + return EFI_NOT_FOUND; + } + PeiServices =3D GetPeiServicesTablePointer (); + (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &PeiVariable + ); + + Status =3D PeiVariable->GetVariable (PeiVariable, mSetupInfo[GroupIndex]= .SetupName, mSetupInfo[GroupIndex].GuidValue, NULL, &mSetupInfo[GroupIndex]= .VariableSize, Variable); + + return Status; +} + diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.i= nf b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf new file mode 100644 index 0000000000..b9d96f66fe --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf @@ -0,0 +1,55 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSetupLib + FILE_GUID =3D C27D6383-F718-490c-8959-CB8370263329 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetupLib | PEIM + + +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.common] + PeiSetupLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + ServerPlatformPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib + BaseMemoryLib + MemoryAllocationLib + +[Guids] + gEfiSocketIioVariableGuid + gEfiSocketCommonRcVariableGuid + gEfiSocketMpLinkVariableGuid + gEfiSocketMemoryVariableGuid + gEfiSocketPowermanagementVarGuid + gEfiSocketProcessorCoreVarGuid + gEfiSetupVariableGuid + gPchSetupVariableGuid + gEfiMeRcVariableGuid + gEfiIeRcVariableGuid + gFpgaSocketVariableGuid + gMemBootHealthGuid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + +[Pcd.common] + diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c b/= Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c new file mode 100644 index 0000000000..ba7f86732d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c @@ -0,0 +1,253 @@ +/** @file + Library functions for SetupLib. + This library instance provides methods to access Setup option. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] OptionNumber The option number to retrieve a current value = for. + @param[in, out] Data A pointer to the buffer to be retrieved. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN OUT VOID *Data, + IN UINTN DataSize + ) +{ + SETUP_DATA *SetupData =3D NULL; + + if (Guid =3D=3D NULL || DataSize =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + // + // Retrieve the variable from PCD + // + if (CompareGuid (&gEfiSocketIioVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketIioConfig); + } else if (CompareGuid (&gEfiSocketCommonRcVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketCommonRcConfig); + } else if (CompareGuid (&gEfiSocketMpLinkVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketMpLinkConfig); + } else if (CompareGuid (&gEfiSocketMemoryVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketMemoryConfig); + } else if (CompareGuid (&gEfiSocketPowermanagementVarGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketPowerManagementConfig); + } else if (CompareGuid (&gEfiSocketProcessorCoreVarGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSocketProcessorCoreConfig); + } else if (CompareGuid (&gEfiSetupVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdSetup); + } else if (CompareGuid (&gPchSetupVariableGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdPchSetup); + } else if (CompareGuid (&gMemBootHealthGuid, Guid)) { + SetupData =3D (SETUP_DATA*) PcdGetPtr (PcdMemBootHealthConfig); + } + + // + // Grab the data from the offset + // + if (SetupData !=3D NULL) { + CopyMem (Data, (UINT8*) SetupData + OptionNumber, DataSize); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_ERROR, "ERROR: Unknown GetOptionData requested\n")); + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the token specified by OptionNumber to the value speci= fied by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] OptionNumber The option number to set a current value f= or. + @param[in] Data A pointer to the buffer to set. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN VOID *Data, + IN UINTN DataSize + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: SetOptionData not implemented\n")); + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; +} + +/** + Get all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +GetEntireConfig ( + OUT SETUP_DATA *SetupData + ) +{ + ZeroMem(SetupData, sizeof(SETUP_DATA) ); + + CopyMem (&SetupData->SocketConfig.IioConfig, PcdGetPtr (PcdSocketIioConf= ig), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData->SocketConfig.CommonRcConfig, PcdGetPtr (PcdSocketCo= mmonRcConfig), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData->SocketConfig.UpiConfig, PcdGetPtr (PcdSocketMpLinkC= onfig), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData->SocketConfig.MemoryConfig, PcdGetPtr (PcdSocketMemo= ryConfig), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData->SocketConfig.PowerManagementConfig, PcdGetPtr (PcdS= ocketPowerManagementConfig), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&SetupData->SocketConfig.SocketProcessorCoreConfiguration, PcdG= etPtr (PcdSocketProcessorCoreConfig), sizeof(SOCKET_PROCESSORCORE_CONFIGURA= TION)); + CopyMem (&SetupData->SystemConfig, PcdGetPtr (PcdSetup), sizeof(SYSTEM_C= ONFIGURATION)); + CopyMem (&SetupData->PchSetup, PcdGetPtr (PcdPchSetup), sizeof(PCH_SETUP= )); + CopyMem (&SetupData->MemBootHealthConfig, PcdGetPtr (PcdMemBootHealthCon= fig), sizeof(MEM_BOOT_HEALTH_CONFIG)); + return EFI_SUCCESS; +} + + +/** + Set all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +SetEntireConfig ( + IN SETUP_DATA *SetupData + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: SetEntireConfig not implemented\n")); + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] Variable Pointer to data location where variable is sto= red. + + @retval EFI_SUCCESS Data is successfully retrieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetSpecificConfigGuid ( + IN EFI_GUID *Guid, + OUT VOID *Variable + ) +{ + if ((Guid =3D=3D NULL) || (Variable =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (CompareGuid (&gEfiSocketIioVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketIioConfig), sizeof(SOCKET_IIO_C= ONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSocketCommonRcVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketCommonRcConfig), sizeof(SOCKET_= COMMONRC_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSocketMpLinkVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketMpLinkConfig), sizeof(SOCKET_MP= _LINK_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSocketMemoryVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketMemoryConfig), sizeof(SOCKET_ME= MORY_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSocketPowermanagementVarGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketPowerManagementConfig), sizeof(= SOCKET_POWERMANAGEMENT_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSocketProcessorCoreVarGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSocketProcessorCoreConfig), sizeof(SO= CKET_PROCESSORCORE_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gEfiSetupVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdSetup), sizeof(SYSTEM_CONFIGURATION)); + return EFI_SUCCESS; + } else if (CompareGuid (&gPchSetupVariableGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdPchSetup), sizeof(PCH_SETUP)); + return EFI_SUCCESS; + } else if (CompareGuid (&gMemBootHealthGuid, Guid)) { + CopyMem (Variable, PcdGetPtr (PcdMemBootHealthConfig), sizeof(MEM_BOOT= _HEALTH_CONFIG)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_ERROR, "ERROR: Unknown GetSpecificConfigGuid requested\n")= ); + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the token specified by OptionNumber to the value speci= fied by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] Variable Pointer to data location where variable is sto= red. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN VOID *Variable + ) +{ + DEBUG ((DEBUG_ERROR, "ERROR: SetSpecificConfigGuid not implemented\n")); + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf = b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf new file mode 100644 index 0000000000..c66eb07629 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf @@ -0,0 +1,59 @@ +## @file +# Status Code Handler Driver which produces general handlers and hook them +# onto the status code router. +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetupLib + FILE_GUID =3D 699ECE4C-8146-4C44-97D9-D1FFC5BCDC11 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetupLib | PEIM DXE_DRIVER DXE_SMM_DRIVER DX= E_RUNTIME_DRIVER UEFI_DRIVER + +[Sources] + SetupLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib + +[Guids] + gEfiSocketIioVariableGuid # CONSUMES + gEfiSocketCommonRcVariableGuid # CONSUMES + gEfiSocketMpLinkVariableGuid # CONSUMES + gEfiSocketMemoryVariableGuid # CONSUMES + gEfiSocketPowermanagementVarGuid # CONSUMES + gEfiSocketProcessorCoreVarGuid # CONSUMES + gEfiSetupVariableGuid # CONSUMES + gPchSetupVariableGuid # CONSUMES + gMemBootHealthGuid # CONSUMES + +[Pcd] + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig + +[FixedPcd] + + +[Depex] + TRUE diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.= c b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c new file mode 100644 index 0000000000..f55657ff67 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c @@ -0,0 +1,159 @@ +/** @file + Library functions for SetupLib. + This library instance provides methods to access Setup option. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] OptionNumber The option number to retrieve a current value = for. + @param[in, out] Data A pointer to the buffer to be retrieved. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN OUT VOID *Data, + IN UINTN DataSize + ) +{ + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the token specified by OptionNumber to the value speci= fied by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] OptionNumber The option number to set a current value f= or. + @param[in] Data A pointer to the buffer to set. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN VOID *Data, + IN UINTN DataSize + ) +{ + return EFI_NOT_FOUND; +} + +/** + Get all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +GetEntireConfig ( + OUT SETUP_DATA *SetupData + ) +{ + return EFI_NOT_FOUND; +} + + +/** + Set all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +SetEntireConfig ( + IN SETUP_DATA *SetupData + ) +{ + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by OptionNumber and = Guid. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] Variable Pointer to data location where variable is sto= red. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetSpecificConfigGuid ( + IN EFI_GUID *Guid, + OUT VOID *Variable + ) +{ + return EFI_NOT_FOUND; +} + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the token specified by OptionNumber to the value speci= fied by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] Variable Pointer to data location where variable is sto= red. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN VOID *Variable + ) +{ + return EFI_NOT_FOUND; +} + diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.= inf b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf new file mode 100644 index 0000000000..45792c88cc --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf @@ -0,0 +1,46 @@ +## @file +# Status Code Handler Driver which produces general handlers and hook them +# onto the status code router. +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetupLibNull + FILE_GUID =3D E92E7B25-7CE3-489e-B985-DC9ED7BF2091 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetupLib | PEIM DXE_DRIVER DXE_SMM_DRIVER DX= E_RUNTIME_DRIVER UEFI_DRIVER + +[Sources] + SetupLibNull.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + + +[LibraryClasses] + DebugLib + + +[Protocols] + + +[Guids] + + +[Pcd] + +[FixedPcd] + + +[Depex] + TRUE diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibSh= im/SiliconPolicyInitLibShim.c b/Silicon/Intel/WhitleySiliconPkg/Library/Sil= iconPolicyInitLibShim/SiliconPolicyInitLibShim.c new file mode 100644 index 0000000000..a1c7fb0f67 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/Sili= conPolicyInitLibShim.c @@ -0,0 +1,104 @@ +/** @file + +Copyright (c) 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN VOID *Policy + ) +{ + RETURN_STATUS Status =3D RETURN_SUCCESS; + SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0,= NULL, &SiliconPolicyInitLibPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return NULL; + } + + return SiliconPolicyInitLibPpi->SiliconPolicyInitPreMem (Policy); +} + +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN VOID *Policy + ) +{ + RETURN_STATUS Status =3D RETURN_SUCCESS; + SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0,= NULL, &SiliconPolicyInitLibPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return SiliconPolicyInitLibPpi->SiliconPolicyDonePreMem (Policy); +} + +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN VOID *Policy + ) +{ + RETURN_STATUS Status =3D RETURN_SUCCESS; + SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0,= NULL, &SiliconPolicyInitLibPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return NULL; + } + + return SiliconPolicyInitLibPpi->SiliconPolicyInitPostMem (Policy); +} + +RETURN_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN VOID *Policy + ) +{ + RETURN_STATUS Status =3D RETURN_SUCCESS; + SILICON_POLICY_INIT_LIB_PPI *SiliconPolicyInitLibPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiliconPolicyInitLibInterfaceGuid, 0,= NULL, &SiliconPolicyInitLibPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return SiliconPolicyInitLibPpi->SiliconPolicyDonePostMem (Policy); +} + +VOID * +EFIAPI +SiliconPolicyInitLate ( + IN VOID *Policy + ) +{ + ASSERT_EFI_ERROR (RETURN_UNSUPPORTED); + return NULL; +} + +RETURN_STATUS +EFIAPI +SiliconPolicyDoneLate ( + IN VOID *Policy + ) +{ + ASSERT_EFI_ERROR (RETURN_UNSUPPORTED); + return RETURN_SUCCESS; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibSh= im/SiliconPolicyInitLibShim.inf b/Silicon/Intel/WhitleySiliconPkg/Library/S= iliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf new file mode 100644 index 0000000000..3579cc5922 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/Sili= conPolicyInitLibShim.inf @@ -0,0 +1,38 @@ +## @file +# Component information file for Silicon Init Library Shim instance +# +# This library provides a "shim" between the library and PPI or protocols = implementing the library services. +# This allows the silicon initialization specifics to be abstracted behind= binaries. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyInitLibShim + FILE_GUID =3D 3af20aaa-ed5d-4d82-bfd4-db7cc85d4188 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib | PEIM DXE_DRIVER + +[LibraryClasses] + BaseLib + DebugLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[Sources] + SiliconPolicyInitLibShim.c + +[Guids] + gSiliconPolicyInitLibInterfaceGuid ## ALWAYS CONSUMES + +[Depex] + gSiliconPolicyInitLibInterfaceGuid \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNu= ll/SiliconWorkaroundLibNull.c b/Silicon/Intel/WhitleySiliconPkg/Library/Sil= iconWorkaroundLibNull/SiliconWorkaroundLibNull.c new file mode 100644 index 0000000000..9602cb2ac0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/Sili= conWorkaroundLibNull.c @@ -0,0 +1,38 @@ +/** @file + Silicon workaround library. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Statements that include other files +// +#include +#include + + +/** + Return whether the workaround is enabled. + + This function returns a boolean that determines whether the workaround i= s enabled + given a workaround name. + + @param[in] WorkaroundName An ASCII string that represents t= he workaround name. + This workaround name should corre= spond to an entry + in the silicon workarounds table(= s). + + @retval TRUE The workaround is enabled. + @retval FALSE The workaround is not found in the table(s) and therefor= e disabled. + +**/ +BOOLEAN +EFIAPI +IsSiliconWorkaroundEnabled ( + IN CONST CHAR8 *WorkaroundName + ) +{ + return FALSE; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNu= ll/SiliconWorkaroundLibNull.inf b/Silicon/Intel/WhitleySiliconPkg/Library/S= iliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf new file mode 100644 index 0000000000..a5b8151f6e --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/Sili= conWorkaroundLibNull.inf @@ -0,0 +1,50 @@ +## @file +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconWorkaroundLib + FILE_GUID =3D 85650F6E-9B35-40C0-9F84-B6C8285D1837 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconWorkaroundLib + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + SiliconWorkaroundLibNull.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + DebugLib + EmulationConfigurationLib + PreSiliconEnvDetectLib + CpuAndRevisionLib + SiliconWorkaroundHelperLib + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77706): https://edk2.groups.io/g/devel/message/77706 Mute This Topic: https://groups.io/mt/84168616/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 16:20:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77705+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77705+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136910; cv=none; d=zohomail.com; s=zohoarc; b=fnfkQBJu22BEl2+3Mp9M/0z35kzNMEs3mPMJ70E/HOFhMulLXMIjhMsbGoG6emP8j+AwC+j6vbaQLZx7PLMK5nInvLSj0ktB9Bg7TATBYw+TysMSBzTe0pZv84hDLWcCjKhO/tf9VjkCmaMEQtAv0CgcWkAouGna2Onwy7AcNYI= ARC-Message-Signature: i=1; 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Mon, 12 Jul 2021 17:41:49 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723115" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723115" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:48 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422921" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:47 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 03/17] WhitleySiliconPkg: Add Cpu Includes Date: Mon, 12 Jul 2021 17:41:17 -0700 Message-Id: <20210713004131.1782-4-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: 3aLUOoKXIeDUOg0AbPdYKEHxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136909; bh=oNM67MoA6CbjplJIzgIfmz7E+03XsPLbRFZdlZp32KE=; h=Cc:Date:From:Reply-To:Subject:To; b=R36Qc768BhC5Pl7grXQ7GlYpfVkHZl8bJBGZap1sBEeJVAQ7rH7tCfK9J+HoQu5h2Av YdiBqviG9+Ho0WuyzEOceOP7DAH/JxvlXpMjVzOBLo75gkOIqlpFHiybtbgHGt9A+4GLM uAA56b3HnhJzkLV/GgJDPNHk57j/NtqxTnQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136910632100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 101 ++++++ .../Cpu/Include/CpuDataStruct.h | 27 ++ .../Cpu/Include/CpuPolicyPeiDxeCommon.h | 58 ++++ .../Cpu/Include/Guid/CpuNvramData.h | 34 ++ .../Cpu/Include/Library/CpuConfigLib.h | 30 ++ .../Cpu/Include/Library/CpuEarlyDataLib.h | 41 +++ .../Cpu/Include/Library/CpuPpmLib.h | 16 + .../Cpu/Include/PpmPolicyPeiDxeCommon.h | 320 ++++++++++++++++++ .../Cpu/Include/ProcessorPpmSetup.h | 14 + .../Cpu/Include/Protocol/CpuPolicyProtocol.h | 31 ++ .../Cpu/Include/Protocol/PpmPolicyProtocol.h | 16 + 11 files changed, 688 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStru= ct.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPe= iDxeCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvr= amData.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= ConfigLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= EarlyDataLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/Cpu= PpmLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPe= iDxeCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPp= mSetup.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/Cp= uPolicyProtocol.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/Pp= mPolicyProtocol.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Int= el/WhitleySiliconPkg/Cpu/CpuRcPkg.dec new file mode 100644 index 0000000000..f30558b5d8 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec @@ -0,0 +1,101 @@ +## @file +# Package for support of CPU RC +# This package supports IA32 family processors, with CPU DXE module, CPU P= EIM, CPU S3 module, +# SMM modules, related libraries, and corresponding definitions. +# +# @copyright +# Copyright 2017 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D CpuRcPkg + PACKAGE_GUID =3D 6F855AF8-759E-4834-9AA4-05EC977A51BB + PACKAGE_VERSION =3D 0.5 + +[Includes] + Include + +[LibraryClasses] + CpuConfigLib|Include/Library/CpuConfigLib.h + CpuS3MsrLib|Include/Library/CpuS3MsrLib.h + CpuPpmLib|Include/Library/CpuPpmLib.h + CpuIpLib|Include/Library/CpuIpLib.h + CpuEarlyDataLib|Include/Library/CpuEarlyDataLib.h + CpuInitLib|Include/Library/CpuInitLib.h + PeiCpuLatePolicyLib|Include/Library/PeiCpuLatePolicyLib.h + CpuPolicyLib|Include/Library/CpuPolicyLib.h + +[Guids] + gCpuPkgTokenSpaceGuid =3D { 0x513876ac, 0x4f71, 0x4543, { 0x8a,= 0xf7, 0x27, 0xb, 0x19, 0x2b, 0xed, 0x3c }} + gEfiCpuNvramDataGuid =3D { 0x184220a2, 0xe14c, 0x4497, { 0x85,= 0xbb, 0x14, 0x90, 0xa9, 0xa1, 0xf0, 0xd3 }} + gEfiPmSsdtTableStorageGuid =3D { 0x1d33f981, 0x43f0, 0x4a09, { 0xab,= 0x3b, 0x2f, 0xf4, 0xf7, 0x11, 0x99, 0x9a }} + +[Ppis] + gPpmPolicyPpiGuid =3D { 0xd86e33b4, 0x414f, 0x4941, { 0xb2,= 0x84, 0x31, 0xe0, 0x3b, 0x3f, 0xc0, 0xf7 }} + gPeiCpuLatePolicyPpiGuid =3D { 0x97415556, 0x8c58, 0x4e12, { 0x8e,= 0xaf, 0x1, 0x98, 0x65, 0x50, 0xc5, 0xaa }} + +[Protocols] + gEfiCpuPolicyProtocolGuid =3D { 0xec7c60b4, 0xa82c, 0x42a5, { 0xbe,= 0x76, 0x87, 0xfc, 0xb5, 0x81, 0xa9, 0x1b }} + gPpmPolicyProtocolGuid =3D { 0xd1b6a52c, 0x6810, 0x4957, { 0xa5,= 0xfb, 0x85, 0x7b, 0xb2, 0xb5, 0xa3, 0xda }} + gEfiCpuPpmProtocolGuid =3D { 0x7e6a6cf5, 0xc89c, 0x492f, { 0xac,= 0x37, 0x23, 0x07, 0x84, 0x9c, 0x3a, 0xd5 }} + ## This protocol indicates CPU config context data is ready. + gCpuConfigContextReadyProtocolGuid =3D { 0x63a25a21, 0xeb79, 0x4835, { 0= xaf, 0x76, 0x75, 0x32, 0x7, 0xa1, 0x31, 0xed }} + +[PcdsFeatureFlag] + gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|FALSE|BOOLEAN|0x10000036 + gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|FALSE|BOOLEAN|0x10000038 + gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + + ## Indicates the platform type: desktop, mobile or server.

+ # 0 - desktop
+ # 1 - mobile
+ # 2 - server
+ # @Prompt Platform type. + # @ValidRange 0x80000001 | 0 - 2 + gCpuPkgTokenSpaceGuid.PcdPlatformType|0|UINT8|0x60000003 + gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|0x0|UINT32|0x600000= 04 + + ## Indicates if Intel Enhanced Debug (IED) will be enabled. + # Note that for some processors, IED is optional, but for others, IED i= s required.

+ # TRUE - IED will be enabled.
+ # FALSE - IED will be disabled.
+ # @Prompt Enable IED. + gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|FALSE|BOOLEAN|0x6000000B + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x20000|UINT32|0x6000000C + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamBase|0x0|UINT32|0x6000001D + + ## Specifies the Energy efficiency policy when Energy Performance Bias f= eature is enabled. + # 0 - indicates preference to highest performance. + # 15 - indicates preference to maximize energy saving. + # @Prompt The Energy efficiency policy. + # @ValidRange 0x80000001 | 0 - 15 + gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy|0x0|UINT8|0x60008000 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x600000= 14 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x60000015 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x60000016 + gCpuPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x60000017 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x60000= 01C + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x60000021 + + ## Specifies the register table entry maximum count for every processor = in the CPU config context buffer. + # @Prompt CPU Config Register Table Entry Maximum Count. + gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x6000= 0022 + +[PcdsDynamic, PcdsDynamicEx] + gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 + + gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 + + ## Contains the pointer to a buffer where new socket IDs to be assigned = are stored. + # @Prompt The pointer to a new socket ID buffer. + gCpuPkgTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x= 1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0= x0,0x3,0x0,0x0,0x0}|VOID*|0x60008007 diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h b/= Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..aaabf032f9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +#define inline __inline + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + +#ifndef MAX_CORE +#define MAX_CORE (FixedPcdGet32 (PcdMaxCpuCoreCount)) +#endif + +// +// Total TDP levels for Config TDP + Speed Select (ISS/SST) +// +#define CONFIG_TDP_TOTAL_LEVEL 5 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h new file mode 100644 index 0000000000..6e84e0f7a6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h @@ -0,0 +1,58 @@ +/** @file + Intel CPU PPM policy common structures and macros for both + CPU late policy PPI and CPU policy protocol. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __CPU_POLICY_PEI_DXE_COMMON_HEADER__ +#define __CPU_POLICY_PEI_DXE_COMMON_HEADER__ + +typedef struct { + BOOLEAN CpuTStateEnable; + UINT8 CpuClockModulationDutyCycle; + BOOLEAN CpuAesEnable; + BOOLEAN CpuFastStringEnable; + BOOLEAN CpuMaxCpuidValueLimitEnable; + BOOLEAN CpuMachineCheckEnable; + BOOLEAN CpuMonitorMwaitEnable; + BOOLEAN CpuVtEnable; + BOOLEAN CpuLtEnable; + BOOLEAN CpuX2ApicEnable; + BOOLEAN CpuEistEnable; + BOOLEAN CpuTurboModeEnable; + BOOLEAN CpuHwCoordinationEnable; + UINT8 CpuBootPState; + BOOLEAN CpuPpinControlEnable; + BOOLEAN CpuPeciDownstreamWriteEnable; + BOOLEAN CpuL1NextPagePrefetcherDisable; + BOOLEAN CpuDcuPrefetcherEnable; + BOOLEAN CpuIpPrefetcherEnable; + BOOLEAN CpuMlcStreamerPrefetecherEnable; + BOOLEAN CpuMlcSpatialPrefetcherEnable; + BOOLEAN CpuAmpPrefetchEnable; + BOOLEAN CpuThreeStrikeCounterEnable; + BOOLEAN CpuCStateEnable; + UINT8 CpuPackageCStateLimit; + BOOLEAN CpuC1AutoDemotionEnable; + BOOLEAN CpuC1AutoUndemotionEnable; + UINT8 CpuCoreCStateValue; + UINT16 CpuAcpiLvl2Addr; + BOOLEAN CpuThermalManagementEnable; + UINT8 CpuTccActivationOffset; + BOOLEAN CpuDbpfEnable; + BOOLEAN CpuEnergyPerformanceBiasEnable; + UINT32 CpuIioLlcWaysBitMask; + UINT32 CpuExpandedIioLlcWaysBitMask; + UINT32 CpuRemoteWaysBitMask; + UINT32 CpuRrqCountThreshold; + UINT8 CpuMtoIWa; + BOOLEAN RunCpuPpmInPei; + BOOLEAN AcExceptionOnSplitLockEnable; + BOOLEAN CpuCrashLogGprs; +} CPU_POLICY_COMMON; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.h new file mode 100644 index 0000000000..f033114d16 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.h @@ -0,0 +1,34 @@ +/** @file + GUID used for Cpu Nvram Data entries in the HOB list. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_NVRAM_DATA_GUID_H_ +#define _CPU_NVRAM_DATA_GUID_H_ + +#include + +#define EFI_CPU_NVRAM_DATA_GUID \ + { \ + 0x184220a2, 0xe14c, 0x4497, { 0x85, 0xbb, 0x14, 0x90, 0xa9, 0xa1, 0xf0, = 0xd3 }\ + } + +#define EFI_CPU_NVRAM_DATA_VARIABLE_NAME L"CpuNvramData" + +// +// CPU_NVRAM +// Data that need to be saved in NVRAM for S3 resume +// +typedef struct { // data that need to be saved in= NVRAM for S3 resume + UINT32 flexRatioCsr; // Common for all sockets + UINT64 DesiredCoresCsr[MAX_SOCKET]; // One per socket 64bits + UINT32 DesiredCoresCfg2Csr[MAX_SOCKET]; // One per socket +} CPU_NVRAM; + +extern EFI_GUID gEfiCpuNvramDataGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigL= ib.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h new file mode 100644 index 0000000000..298fe08624 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h @@ -0,0 +1,30 @@ +/** @file + Public include file for the CPU Configuration Library + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include +#include +#include + + +// CPU C State Settings +#define C0_ENABLE 0x00 +#define C6_ENABLE 0x03 + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT32 DefaultSocketId; + UINT32 NewSocketId; +} CPU_SOCKET_ID_INFO; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDa= taLib.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDataL= ib.h new file mode 100644 index 0000000000..7dbc55f765 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDataLib.h @@ -0,0 +1,41 @@ +/** @file + Interface of CPU early data library. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __CPU_EARLY_DATA_LIB_H__ +#define __CPU_EARLY_DATA_LIB_H__ + +#include + +typedef struct { + UINT64 FusedCores[MAX_SOCKET]; // Fused Core Ma= sk in the package 64bits + UINT64 ActiveCores[MAX_SOCKET]; // Active Core M= ask in the package 64bits + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max N= on-turbo Ratio (per socket) + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maxim= um Efficiency Ratio (per socket) + UINT32 PackageBspApicID[MAX_SOCKET]; + UINT8 IssCapableSystem; // 1 =3D All soc= kets config TDP / ISS capable + UINT8 ConfigTdpCapableSystem; // 1 =3D All soc= kets config TDP capable + UINT8 IssConfigTdpMaxLevel; // B2P CONFIG_TD= P_GET_LEVELS_INFO + UINT8 IssConfigTdpCurrentLevel; // B2P CONFIG_TD= P_GET_LEVELS_INFO + UINT8 IssConfigTdpRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_TDP_INFO + UINT16 IssConfigTdpPower[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_TDP_INFO + UINT32 IssConfigTdpPowerMinMax[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_POWER_INFO + UINT8 IssConfigTdpTjmax[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_ICCP_TJMAX_INFO + UINT8 IssConfigTdpCoreCount[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; //= B2P CONFIG_TDP_GET_CORE_MASK + UINT64 IssConfigTdpEnabledCoreMask[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL];= // B2P CONFIG_TDP_GET_CORE_MASK + UINT8 PbfCapableSystem; // 1 = =3D All sockets PBF Capable + UINT8 PbfCapable[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= GET_CONFIG_TDP_CONTROL PBF_SUPPORT Bit[1] + UINT64 PbfP1HiCoreMap[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P P= BF_GET_CORE_MASK_INFO Bits + UINT8 PbfP1HighRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= PBF_GET_P1HI_P1LO_INFO P1_HI + UINT8 PbfP1LowRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= PBF_GET_P1HI_P1LO_INFO P1_LO + UINT32 SstCpSystemStatus; + UINT8 UncoreP0Ratio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= CONFIG_TDP_GET_RATIO_INFO + UINT8 UncorePnRatio[MAX_SOCKET][CONFIG_TDP_TOTAL_LEVEL]; // B2P= CONFIG_TDP_GET_RATIO_INFO +} CPU_VAR_DATA; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.h new file mode 100644 index 0000000000..400cd52080 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.h @@ -0,0 +1,16 @@ +/** @file + This is an implementation of the BootScript at run time. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + +//CSR_PKG_CST_ENTRY_CRITERIA_MASK bit definition (For SKX) +#define SET_PCIEx_MASK 0xF + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCommon.h new file mode 100644 index 0000000000..86c9f4179f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCommon.h @@ -0,0 +1,320 @@ +/** @file + Intel CPU PPM policy common structures and macros for both PPM policy PP= I and + policy protocol. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PPM_POLICY_PEI_DXE_COMMON_HEADER__ +#define __PPM_POLICY_PEI_DXE_COMMON_HEADER__ + + +/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + !!! Keep this file common for both PEI and DXE use !!! + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/ + + +#include + + +#define NUM_CST_LAT_MSR 3 +#define NUM_TURBO_RATIO_GROUP 8 + +// +// Hardware P States Modes +// +typedef enum { + HWP_MODE_DISABLED =3D 0, // also known as legacy P states + HWP_MODE_NATIVE =3D 1, // native with legacy support + HWP_MODE_OOB =3D 2, // out of band + HWP_MODE_NATIVE_NO_LEGACY =3D 3 // native w/o legacy support +} HWP_MODES; + +// +// Power Perf Tuning options +// +// HWP is disabled : OS, BIOS and PECI control all available. OS c= ontrol is the default +// HWP native mode : OS, BIOS and PECI control all available. OS c= ontrol is the default +// HWP is OOB : BIOS and PECI control available. PECI control= is the default +// HWP is native w/o legacy: BIOS and PECI control available. BIOS control= is the default +// +// On CPX, PECI is not available +// +typedef enum { + PWR_PERF_TUNING_OS_CONTROL =3D 0, + PWR_PERF_TUNING_BIOS_CONTROL =3D 1, + PWR_PERF_TUNING_PECI_CONTROL =3D 2 +} POWER_PERF_TUNING_CONTROL; + +#pragma pack(1) + + +typedef struct { + UINT8 PkgCstEntryValCtl; + UINT8 SapmctlValCtl; + UINT8 SkipPkgCstEntry; + UINT8 SwLtrOvrdCtl; + UINT8 PriPlnCurrCfgCtl; + UINT8 CurrentConfig; + UINT8 MsrLock; + UINT8 MsrPkgCstConfigControlLock; + UINT8 MpllOffEnaAuto; + UINT8 DynamicL1Disable; + UINT8 VccsaVccioDisable; + UINT8 PcodeWdogTimerEn; + UINT8 DramRaplPwrLimitLockCsr; + UINT8 EnableLowerLatencyMode; +} ADV_PWR_CTL; + +typedef struct { + UINT8 BidirProchotEnable; + UINT8 C1eEnable; + UINT8 EeTurboDisable; + UINT8 ProchotOutputDisable; + UINT8 SapmControl; + UINT8 PwrPerfSwitch; + POWER_PERF_TUNING_CONTROL PwrPerfTuning; + UINT8 ProchotLock; + UINT8 LtrSwInput; + UINT8 PkgCLatNeg; + UINT8 SetvidDecayDisable; +} POWER_CTL; + +typedef struct { + UINT16 PowerLimit1Power; + UINT8 PowerLimit1En; + UINT16 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT16 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2En; + UINT16 PowerLimit2Time; + UINT8 TurboPowerLimitLock; + UINT8 TurboLimitCsrLock; +} TURBO_POWRER_LIMIT; + +typedef struct { + UINT16 CurrentLimit; + UINT8 PpcccLock; +} PPO_CURRENT_CFG; + +typedef struct { + UINT8 WorkLdConfig; + UINT8 AltEngPerfBIAS; + UINT8 P0TtlTimeHigh1; + UINT8 P0TtlTimeLow1; + UINT16 EngAvgTimeWdw1; +} PERF_BIAS_CONFIG; + +typedef struct { + UINT8 PmaxDetector; + UINT8 PmaxAutoAdjustment; + UINT8 PmaxLoadLine; + UINT8 PmaxSign; + UINT8 PmaxOffset; + UINT8 PmaxOffsetNegative; + UINT8 PmaxTriggerSetup; + UINT16 BasePackageTdp[MAX_SOCKET]; + UINT8 EnhancedPmaxDetector; +} PMAX_CONFIG; + +typedef struct { + UINT8 Iio0PkgcClkGateDis; + UINT8 Iio1PkgcClkGateDis; + UINT8 Iio2PkgcClkGateDis; + UINT8 Kti01PkgcClkGateDis; + UINT8 Kti23PkgcClkGateDis; + UINT8 Kti45PkgcClkGateDis; + UINT8 Mc0PkgcClkGateDis; + UINT8 Mc1PkgcClkGateDis; + UINT8 P0pllOffEna; + UINT8 P1pllOffEna; + UINT8 P2pllOffEna; + UINT8 Kti01pllOffEna; + UINT8 Kti23pllOffEna; + UINT8 Kti45pllOffEna; + UINT8 Mc0pllOffEna; + UINT8 Mc1pllOffEna; + UINT8 Mc0PkgcIoVolRedDis; + UINT8 Mc1PkgcIoVolRedDis; + UINT8 Mc0PkgcDigVolRedDis; + UINT8 Mc1PkgcDigVolRedDis; + UINT8 SetvidDecayDisable; + UINT8 SapmCtlLock; +} SAPM_CTL; + +typedef struct { + UINT8 PerfPLimitEn; + UINT8 PerfPLmtThshld; + UINT8 PerfPLimitClipC; + UINT8 PerfPlimitDifferential; +} PERF_PLIMIT_CTL; + +typedef struct { + UINT8 KtiApmOvrdEn; + UINT8 IomApmOvrdEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 UncrPerfPlmtOvrdEn; +} DYNAMIC_PER_POWER_CTL; + +typedef struct { + UINT16 NonSnpLatVal; + UINT8 NonSnpLatMult; + UINT8 NonSnpLatOvrd; + UINT16 NonSnpLatVld; + UINT16 SnpLatVal; + UINT8 SnpLatMult; + UINT8 SnpLatOvrd; + UINT8 SnpLatVld; +} PCIE_ILTR_OVRD; + +typedef struct { + UINT16 Value; + UINT8 Multiplier; + UINT8 Valid; +} CST_LATENCY_CTL; + + +typedef struct { + BOOLEAN C1e; + + UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET]; + UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET]; + CST_LATENCY_CTL LatencyCtrl[NUM_CST_LAT_MSR]; +} PPM_CSTATE_STRUCT; + +typedef struct { + BOOLEAN Enable; + UINT32 Voltage; + UINT16 RatioLimit[MAX_CORE]; +} PPM_XE_STRUCT; + +typedef struct { + UINT8 RatioLimitRatio[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitRatioMask[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitCores[NUM_TURBO_RATIO_GROUP]; + UINT8 RatioLimitCoresMask[NUM_TURBO_RATIO_GROUP]; +} TURBO_RATIO_LIMIT; + +typedef struct { + HWP_MODES HWPMEnable; + UINT8 HWPMNative; + UINT8 HWPMOOB; + UINT8 HWPMInterrupt; + UINT8 EPPEnable; + UINT8 EPPProfile; + UINT8 APSrocketing; + UINT8 Scalability; + UINT8 PPOTarget; + UINT8 RaplPrioritization; + UINT32 SstCpSystemStatus; + UINT8 OutofBandAlternateEPB; + UINT8 ConfigurePbf; + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority = Cores Bitmap + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio +} PPM_HWPM_STRUCT; + +typedef struct { + UINT8 EnablePkgcCriteria; + UINT8 EnablePkgCCriteriaKti[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaRlink[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaFxr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMcddr[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHbm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaIio[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHqm[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaNac[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaTip[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaMdfs[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaHcx[MAX_SOCKET]; + UINT8 EnablePkgCCriteriaDino[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpType[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaLogicalIpTypeIio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoKti[MAX_SOCKET]; + UINT8 EnableLinkInL1Kti[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoRlink[MAX_SOCKET]; + UINT8 EnableLinkInL1Rlink[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoFxr[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskFxr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMcddr[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionMcddr[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHbm[MAX_SOCKET]; + UINT8 PkgcCriteriaPsOptionHbm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoIio[MAX_SOCKET]; + UINT8 EnableLinkInL1Iio[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHqm[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHqm[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoNac[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskNac[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoTip[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskTip[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoMdfs[MAX_SOCKET]; + UINT8 AllowLpStateMdfs[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoHcx[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskHcx[MAX_SOCKET]; + UINT8 PkgCCriteriaInstanceNoDino[MAX_SOCKET]; + UINT8 PkgcCriteraPsMaskDino[MAX_SOCKET]; + UINT8 PkgCCriteriaAllowedPsMaskDino[MAX_SOCKET]; +} PKGC_SA_PS_CRITERIA_STRUCT; + +typedef struct { + UINT8 ThermalMonitorStatusFilter; + UINT8 ThermalMonitorStatusFilterTimeWindow; +} TM_STATUS_Filter; + +typedef struct { + UINT8 IssCapableSystem; + UINT8 DynamicIss; + UINT8 ConfigTDPLevel; + UINT8 ConfigTDPLock; + UINT16 CurrentPackageTdp[MAX_SOCKET]; + UINT8 FastRaplDutyCycle; + UINT32 ProchotRatio; + UINT8 OverclockingLock; + UINT32 C2C3TT; + UINT8 AvxSupport; + UINT8 AvxLicensePreGrant; + UINT8 AvxIccpLevel; + UINT8 GpssTimer; + + ADV_PWR_CTL AdvPwrMgtCtl; + POWER_CTL PowerCtl; + TURBO_POWRER_LIMIT TurboPowerLimit; + PPO_CURRENT_CFG PpoCurrentCfg; + PERF_BIAS_CONFIG PerfBiasConfig; + PMAX_CONFIG PmaxConfig; + TM_STATUS_Filter ThermalReport; + SAPM_CTL SapmCtl[MAX_SOCKET]; + PERF_PLIMIT_CTL PerPLimitCtl; + DYNAMIC_PER_POWER_CTL DynamicPerPowerCtl; + PCIE_ILTR_OVRD PcieIltrOvrd; + + PPM_CSTATE_STRUCT PpmCst; + PPM_XE_STRUCT PpmXe; + PPM_HWPM_STRUCT Hwpm; + TURBO_RATIO_LIMIT TurboRatioLimit; + + PKGC_SA_PS_CRITERIA_STRUCT PkgcCriteria; + + UINT8 CpuThermalManagement; + UINT8 RunCpuPpmInPei; +} PPM_POLICY_CONFIGURATION; + + +#pragma pack() + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.= h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.h new file mode 100644 index 0000000000..8623ca5fd9 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.h @@ -0,0 +1,14 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PROCESSOR_PPM_SETUP_H +#define _PROCESSOR_PPM_SETUP_H + +#define PPM_AUTO 0xFF + +#endif // _PROCESSOR_PPM_SETUP_H \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicy= Protocol.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicy= Protocol.h new file mode 100644 index 0000000000..955136139c --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicyProtoco= l.h @@ -0,0 +1,31 @@ +/** @file + Intel CPU policy protocol should be installed after CPU related setting + are set by platform driver. CPU driver only could get CPU policy data af= ter this + protocol installed. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_PROTOCOL_H_ +#define _CPU_POLICY_PROTOCOL_H_ + +#include + +#define CPU_POLICY_PROTOCOL_GUID \ + { \ + 0xec7c60b4, 0xa82c, 0x42a5, { 0xbe, 0x76, 0x87, 0xfc, 0xb5, 0x81, 0xa9= , 0x1b } \ + } + +typedef struct { + UINT64 PlatformCpuSocketNames; + UINT64 PlatformCpuAssetTags; + UINT8 SbspSelection; + CPU_POLICY_COMMON Policy; +} CPU_POLICY_CONFIGURATION; + +extern EFI_GUID gEfiCpuPolicyProtocolGuid; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicy= Protocol.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicy= Protocol.h new file mode 100644 index 0000000000..5534a345de --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicyProtoco= l.h @@ -0,0 +1,16 @@ +/** @file + Intel CPU PPM policy protocol should be installed after CPU related sett= ing + are set by platform driver. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PPM_POLICY_PROTOCOL_H_ +#define _PPM_POLICY_PROTOCOL_H_ + +#include + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77705): https://edk2.groups.io/g/devel/message/77705 Mute This Topic: https://groups.io/mt/84168615/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 16:20:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77708+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77708+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136920; cv=none; d=zohomail.com; s=zohoarc; b=NRlXhQKCY3W0oRAcP1wDDIX2UZaYfp0FAIBFe7xGM2TQVX4syj6ZvS/eokXq1xfXf61/C3wHoVylTj5K8PjK8SML6guHj1KJm6l7UzeGKvGq7QFqbDwWqFw6TawtAF7edpVt3bCHpkscTbrQ6ilNvFv9LNF9lBxT05RH/83BJSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626136920; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=yLs/NGOzKBBDCSQ5VzkEFiIBvykDPMb3AHhbs4Ij3tU=; b=idIv+qtJtsV8UwQbhVs0o0XuEb1lHWmqejaVwh0XBA1M9T++H18X04XiHJS+yHPDGmhRY8bpg281JDl9Q3EtB0Z37gINSQxEFmS1p9LJ1Pg4O0CO+o/BoXeVg/ES1KUFrUIBN4VEWE66lMBCHsjlfR11ys+K6w3iVFCFmsbVwlQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77708+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162613692059912.890586170474421; Mon, 12 Jul 2021 17:42:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qK7TYY1788612xoX9oW6xvWS; Mon, 12 Jul 2021 17:42:00 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.2559.1626136908854305417 for ; Mon, 12 Jul 2021 17:41:49 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723116" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723116" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:48 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422924" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:48 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 04/17] WhitleySiliconPkg: Add Me Includes Date: Mon, 12 Jul 2021 17:41:18 -0700 Message-Id: <20210713004131.1782-5-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: IwNQ3il43rRF2q9Dwy3MAleWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136920; bh=Pv4M1lOJKtIU4Z8N8HrgFUg0ubVgtpMfGVdShh7J+ts=; h=Cc:Date:From:Reply-To:Subject:To; b=FKctisebdeaacnRqECb45Wg8lu6Ma2mouVN7kwts3XE7sAGa42yVYDBWGLL5B5S3egA k40RF4X5VX3i+0Zq6Iau8sxdovGfUUyJ9nAQdh/0ZsXBdCcygeHUeJC+aolHOP0YFJa3Y feD0tfXelcHveGrRDo8PgfTCfd2qsMcfAb4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136921185100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Me/MeSps.4/Include/Library/SpsPeiLib.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Me/MeSps.4/Include/Libr= ary/SpsPeiLib.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Me/MeSps.4/Include/Library/Sps= PeiLib.h b/Silicon/Intel/WhitleySiliconPkg/Me/MeSps.4/Include/Library/SpsPe= iLib.h new file mode 100644 index 0000000000..1c5c00aacf --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Me/MeSps.4/Include/Library/SpsPeiLib.h @@ -0,0 +1,22 @@ +/** @file + Definitions for Sps Pei Library + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPS_PEI_LIB_H +#define _SPS_PEI_LIB_H + +// Available clocking modes +typedef enum _CLOCKING_MODES { + InternalStandard =3D 0, + InternalAlternate, + HybridStandard, + HybridAlternate, + External +} CLOCKING_MODES; + +#endif // _SPS_PEI_LIB_H --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.zohomail.com with SMTPS id 1626136926993104.94525546399495; Mon, 12 Jul 2021 17:42:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Z3BgYY1788612x5IkwelqQDT; Mon, 12 Jul 2021 17:42:06 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.2664.1626136920574620140 for ; Mon, 12 Jul 2021 17:42:00 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456217" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456217" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422929" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:48 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 05/17] WhitleySiliconPkg: Add PCH Register Includes Date: Mon, 12 Jul 2021 17:41:19 -0700 Message-Id: <20210713004131.1782-6-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: FMadZjJ1HtCv1zaBoelCiv54x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136926; bh=1Qg4mxb55tVgwiIYPZhydQHWR0n1CneiXfy74x/D2Io=; h=Cc:Date:From:Reply-To:Subject:To; b=u8AXPy/cwUsxbjvhUU0+x2TlcfPDqhAY4g/gJ0fO8G5hkfSVkNWRHAfPmuzwnnXpxfK sJ2hC6jH7AqAyuh+L6AbKXj2csldLd16n2ibO4bOFJkbLY46vRIDC9JMzODfHcoZgl1pX 2pJ67jKRQucyu6qIbLTfyrBamL3/6De9Fk0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136927885100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Include/Register/PchRegsDci.h | 44 ++ .../Include/Register/PchRegsDmi.h | 302 ++++++++ .../Include/Register/PchRegsEva.h | 124 +++ .../Include/Register/PchRegsFia.h | 106 +++ .../Include/Register/PchRegsGpio.h | 531 +++++++++++++ .../Include/Register/PchRegsHda.h | 271 +++++++ .../Include/Register/PchRegsHsio.h | 190 +++++ .../Include/Register/PchRegsItss.h | 90 +++ .../Include/Register/PchRegsLan.h | 156 ++++ .../Include/Register/PchRegsLpc.h | 490 ++++++++++++ .../Include/Register/PchRegsP2sb.h | 132 ++++ .../Include/Register/PchRegsPcie.h | 620 +++++++++++++++ .../Include/Register/PchRegsPcr.h | 177 +++++ .../Include/Register/PchRegsPmc.h | 731 ++++++++++++++++++ .../Include/Register/PchRegsPsf.h | 304 ++++++++ .../Include/Register/PchRegsPsth.h | 66 ++ .../Include/Register/PchRegsSata.h | 713 +++++++++++++++++ .../Include/Register/PchRegsSmbus.h | 157 ++++ .../Include/Register/PchRegsSpi.h | 354 +++++++++ .../Include/Register/PchRegsThermal.h | 113 +++ .../Include/Register/PchRegsTraceHub.h | 147 ++++ .../Include/Register/PchRegsUsb.h | 529 +++++++++++++ 22 files changed, 6347 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsDci.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsDmi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsEva.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsFia.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsGpio.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsHda.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsHsio.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsItss.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsLan.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsLpc.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsP2sb.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsPcie.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsPcr.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsPmc.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsPsf.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsPsth.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsSata.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsSmbus.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsSpi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsThermal.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsTraceHub.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Register/PchRegsUsb.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsDci.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsDci.h new file mode 100644 index 0000000000..c2ced719cc --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsDci.h @@ -0,0 +1,44 @@ +/** @file + Register names for PCH DCI device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI= Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Hos= t DCI lock +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Hos= t DCI enable +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI= Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI= Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Har= dware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-= Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 = Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC= Request Enable + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsDmi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsDmi.h new file mode 100644 index 0000000000..4f42debf91 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsDmi.h @@ -0,0 +1,302 @@ +/** @file + Register names for DMI and OP-DMI + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DMI_H_ +#define _PCH_REGS_DMI_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// VC Configuration (Common) +// +#define R_PCH_DMI_PCR_V0CTL 0x2014 /= //< Virtual channel 0 resource control +#define B_PCH_DMI_PCR_V0CTL_EN BIT31 +#define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) /= //< Bit[26:24] +#define N_PCH_DMI_PCR_V0CTL_ID 24 +#define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E +#define R_PCH_DMI_PCR_V0STS 0x201A /= //< Virtual channel 0 status +#define B_PCH_DMI_PCR_V0STS_NP BIT1 +#define R_PCH_DMI_PCR_V1CTL 0x2020 /= //< Virtual channel 1 resource control +#define B_PCH_DMI_PCR_V1CTL_EN BIT31 +#define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) /= //< Bit[27:24] +#define N_PCH_DMI_PCR_V1CTL_ID 24 +#define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE +#define R_PCH_DMI_PCR_V1STS 0x2026 /= //< Virtual channel 1 status +#define B_PCH_DMI_PCR_V1STS_NP BIT1 +#define R_PCH_DMI_PCR_VMCTL 0x2040 /= //< ME Virtual Channel (VCm) resource control +#define R_PCH_DMI_PCR_VMSTS 0x2046 /= //< ME Virtual Channel Resource Status +#define R_PCH_DMI_PCR_IOSFC1TC 0x2054 /= //< Offset of credits for VC1 register +#define R_PCH_DMI_PCR_IOSFC2TC 0x2058 /= //< Offset of credits for VCm register +#define V_PCH_DMI_PCR_IOSFC1TC_ICX 0x00021002 /= //< Credits for VC1 - values for ICX +#define V_PCH_DMI_PCR_IOSFC2TC_ICX 0x00082005 /= //< Credits for VCm - values for ICX +#define R_PCH_DMI_PCR_UEM 0x2088 /= //< Uncorrectable Error Mask +#define R_PCH_DMI_PCR_REC 0x20AC /= //< Root Error Command + +// +// DMI Error Reporting +// +#define R_PCH_DMI_PCR_UES 0x2084 = ///< Uncorrectable Error Status +#define R_PCH_DMI_PCR_UEM 0x2088 = ///< Uncorrectable Error Mask +#define B_PCH_DMI_UE_DLPE BIT4 = // Data Link Protocol Error +#define B_PCH_DMI_UE_PT BIT12 = // Poisoned TLP +#define B_PCH_DMI_UE_CA BIT15 = // Completer Abort +#define B_PCH_DMI_UE_RO BIT17 = // Receiver Overflow +#define B_PCH_DMI_UE_MT BIT18 = // Malformed TLP +#define R_PCH_DMI_PCR_CES 0x2090 = ///< Correctable Error Status +#define R_PCH_DMI_PCR_CEM 0x2094 = ///< Correctable Error Mask +#define B_PCH_DMI_CE_RE BIT0 = // Indicates a receiver error +#define B_PCH_DMI_CE_BT BIT6 = // Bad TLP +#define B_PCH_DMI_CE_BD BIT7 = // Bad DLLP +#define B_PCH_DMI_CE_RNR BIT8 = // Replay Number Rollover +#define R_PCH_DMI_PCR_RES 0x20B0 = ///< Root Error Status +#define B_PCH_DMI_RES_CR BIT0 = // correctable error message is received or an internal correctable error i= s detected +#define B_PCH_DMI_RES_ENR BIT2 = // either afatal or a non-fatal error message is received or an internal fa= tal error is detected + +// +// Internal Link Configuration (DMI Only) +// +#define R_PCH_DMI_PCR_LCAP 0x21A4 /= //< Link Capabilities +#define B_PCH_DMI_PCR_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_DMI_PCR_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_DMI_PCR_LCAP_APMS (BIT11 | BIT10) /= //< L0 is supported on DMI +#define B_PCH_DMI_PCR_LCAP_MLW 0x000003F0 +#define B_PCH_DMI_PCR_LCAP_MLS 0x0000000F + +#define R_PCH_DMI_PCR_LCTL 0x21A8 /= //< Link Control +#define B_PCH_DMI_PCR_LCTL_ES BIT7 +#define B_PCH_DMI_PCR_LCTL_ASPM (BIT1 | BIT0) /= //< Link ASPM +#define R_PCH_DMI_PCR_LSTS 0x21AA /= //< Link Status + +#define R_PCH_DMI_PCR_LCAP2 0x21AC /= //< Link Control 2 +typedef union { + UINT32 Dword; + struct { + UINT32 Rsrvd0 : 1, + SLSV : 7, // Supported Link Speed Vector + CS : 1, // Crosslink Supported + LSOSGSSV : 7, // Lower SKP OS Generation Supported Speeds Vector + LSOSRSS : 7, // Lower SKP OS Reception Supported Speeds Vector + Rsrvd1 : 9; + } Bits; +} PCH_DMI_PCR_LCAP2; + +#define R_PCH_DMI_PCR_LCTL2 0x21B0 /= //< Link Control 2 +typedef union { + UINT32 Dword; + struct { + UINT32 TLS : 4, // 0:3 Target Link Speed + EC : 1, // 4 Enter Compliance + HASD : 1, // 5 Hardware Autonomous Speed Disable + SD : 1, // 6 Selectable De-emphasis + TM : 3, // 9:7 Transmit Margin + EMC : 1, // 10 Enter Modified Compliance + CSOS : 1, // 11 Compliance SOS + CD : 4, // 15:12 Compliance Preset/De-emphasis + CDL : 1, // 16 Current De-emphasis Level + EqC : 1, // 17 Equalization Complete + EQP1S : 1, // 18 Equalization Phase 1 Successful + EQP2S : 1, // 19 Equalization Phase 2 Successful + EQP3S : 1, // 20 Equalization Phase 3 Successful + LER : 1, // 21 Link Equalization Request + Rsrvd0 :10; // 31:22 + } Bits; +} PCH_DMI_PCR_LCTL2; + +#define R_PCH_DMI_PCR_LSTS2 0x21B2 /= //< Link Status 2 +#define R_PCH_PCR_DMI_L01EC 0x21BC /= //< Lane 0 and Lane 1 Equalization Control +#define R_PCH_PCR_DMI_L23EC 0x21C0 /= //< Lane 2 and Lane 3 Equalization Control +#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 /= //< Upstream Port Lane 1/3 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL13RPH 24 /= //< Upstream Port Lane 1/3 Transmitter Preset Hint value offset +#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 /= //< Upstream Port Lane 0/2 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL02RPH 8 /= //< Upstream Port Lane 0/2 Transmitter Preset Hint value offset +#define V_PCH_PCR_DMI_UPL0RPH 7 /= //< Upstream Port Lane 0 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL1RPH 7 /= //< Upstream Port Lane 1 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL2RPH 7 /= //< Upstream Port Lane 2 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL3RPH 7 /= //< Upstream Port Lane 3 Transmitter Preset Hint value + + +// +// North Port Error Injection Configuration (DMI Only) +// +#define R_PCH_DMI_PCR_DMIEN 0x2230 /= //< DMI Error Injection Enable + +// +// DMI Control +// +#define R_PCH_DMI_PCR_DMIC 0x2234 = ///< DMI Control +#define B_PCH_DMI_PCR_DMIC_SRL BIT31 = ///< Secured register lock +#define B_PCH_DMI_PCR_DMIC_ORCE (BIT25 | BIT24) = ///< Offset Re-Calibration Enable +#define N_PCH_DMI_PCR_DMIC_ORCE 24 +#define V_PCH_DMI_PCR_DMIC_ORCE_EN_GEN2_GEN3 1 = ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only. +#define B_PCH_DMI_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | = BIT0) ///< DMI Clock Gate Enable +#define R_PCH_DMI_PCR_DMIHWAWC 0x2238 = ///< DMI HW Autonomus Width Control +#define R_PCH_DMI_PCR_IOSFSBCS 0x223E = ///< IOSF Sideband Control and Status +#define B_PCH_DMI_PCR_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) = ///< DMI Clock Gate Enable +#define B_PCH_PCR_DMI_DMIC_DNPRL BIT19 + +#define R_PCH_DMI_PCR_2300 0x2300 +#define R_PCH_DMI_PCR_2304 0x2304 +#define R_PCH_DMI_PCR_2310 0x2310 +#define B_PCH_PCR_DMI_2310_HALEP BIT22 +#define R_PCH_DMI_PCR_2314 0x2314 +#define R_PCH_DMI_PCR_2320 0x2320 +#define R_PCH_DMI_PCR_2324 0x2324 +#define R_PCH_DMI_PCR_232C 0x232C +#define R_PCH_DMI_PCR_2334 0x2334 +#define R_PCH_DMI_PCR_2338 0x2338 +#define R_PCH_DMI_PCR_2340 0x2340 +#define R_PCH_DMI_PCR_2344 0x2344 +#define R_PCH_DMI_PCR_2348 0x2348 +#define R_PCH_PCR_DMI_234C 0x234C + +// +// Port Configuration Extension(DMI Only) +// +#define R_PCH_DMI_PCR_EQCFG1 0x2450 +#define B_PCH_DMI_PCR_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCR_DMI_EQCFG1_RTPCOE BIT15 /= //< Remote Transmitter Preset Coefficient Override Enable + +#define R_PCH_PCR_DMI_RTPCL1 0x2454 /= //< Remote Transmitter Preset Coefficient List 1 + +#define N_PCH_PCR_DMI_RTPCL1_RTPRECL2PL4 24 +#define N_PCH_PCR_DMI_RTPCL1_RTPOSTCL1PL3 18 +#define N_PCH_PCR_DMI_RTPCL1_RTPRECL1PL2 12 +#define N_PCH_PCR_DMI_RTPCL1_RTPOSTCL0PL1 6 +#define N_PCH_PCR_DMI_RTPCL1_RTPRECL0PL0 0 + +#define B_PCH_PCR_DMI_RTPCL1_PCM BIT31 +#define B_PCH_PCR_DMI_RTPCL1_RTPRECL2PL4 (0X3F << N_PCH_PCR_DMI_RTPCL1_= RTPRECL2PL4) +#define B_PCH_PCR_DMI_RTPCL1_RTPOSTCL1PL3 (0X3F << N_PCH_PCR_DMI_RTPCL1_= RTPOSTCL1PL3) +#define B_PCH_PCR_DMI_RTPCL1_RTPRECL1PL2 (0X3F << N_PCH_PCR_DMI_RTPCL1_= RTPRECL1PL2) +#define B_PCH_PCR_DMI_RTPCL1_RTPOSTCL0PL1 (0X3F << N_PCH_PCR_DMI_RTPCL1_= RTPOSTCL0PL1) +#define B_PCH_PCR_DMI_RTPCL1_RTPRECL0PL0 (0X3F << N_PCH_PCR_DMI_RTPCL1_= RTPRECL0PL0) +#define R_PCH_PCR_DMI_RTPCL2 0x2458 /= //< Remote Transmitter Preset Coefficient List 2 + +#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL4PL9 24 +#define N_PCH_PCR_DMI_RTPCL2_RTPRECL4PL8 18 +#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL3PL7 12 +#define N_PCH_PCR_DMI_RTPCL2_RTPRECL3PL6 6 +#define N_PCH_PCR_DMI_RTPCL2_RTPOSTCL2PL5 0 + +#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL4PL9 (0X3F << N_PCH_PCR_DMI_RTPCL2_= RTPOSTCL4PL9) +#define B_PCH_PCR_DMI_RTPCL2_RTPRECL4PL8 (0X3F << N_PCH_PCR_DMI_RTPCL2_= RTPRECL4PL8) +#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL3PL7 (0X3F << N_PCH_PCR_DMI_RTPCL2_= RTPOSTCL3PL7) +#define B_PCH_PCR_DMI_RTPCL2_RTPRECL3PL6 (0X3F << N_PCH_PCR_DMI_RTPCL2_= RTPRECL3PL6) +#define B_PCH_PCR_DMI_RTPCL2_RTPOSTCL2PL5 (0X3F << N_PCH_PCR_DMI_RTPCL2_= RTPOSTCL2PL5) + + +#define R_PCH_DMI_PCR_LTCO1 0x2470 /= //< Local Transmitter Coefficient Override 1 +#define R_PCH_DMI_PCR_LTCO2 0x2474 /= //< Local Transmitter Coefficient Override 2 +#define B_PCH_DMI_PCR_L13TCOE BIT25 /= //< Lane 1/3 Transmitter Coefficient Override Enable +#define B_PCH_DMI_PCR_L02TCOE BIT24 /= //< Lane 0/2 Transmitter Coefficient Override Enable +#define B_PCH_DMI_PCR_L13TPOSTCO 0x00fc0000 /= //< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_DMI_PCR_L13TPOSTCO 18 /= //< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_DMI_PCR_L13TPRECO 0x0003f000 /= //< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_DMI_PCR_L13TPRECO 12 /= //< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset +#define B_PCH_DMI_PCR_L02TPOSTCO 0x00000fc0 /= //< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_DMI_PCR_L02TPOSTCO 6 /= //< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_DMI_PCR_L02TPRECO 0x0000003f /= //< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_DMI_PCR_L02TPRECO 0 /= //< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset +#define R_PCH_DMI_PCR_G3L0SCTL 0x2478 /= //< GEN3 L0s Control + +// +// OP-DMI Specific Registers (OP-DMI Only) +// +#define R_PCH_OPDMI_PCR_LCTL 0x2600 = ///< Link Control +#define R_PCH_OPDMI_PCR_STC 0x260C = ///< Sideband Timing Control +#define R_PCH_OPDMI_PCR_LPMC 0x2614 = ///< Link Power Management Control +#define R_PCH_OPDMI_PCR_LCFG 0x2618 = ///< Link Configuration + +// +// DMI Source Decode PCRs (Common) +// +#define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Po= rt IOxAPIC Range 1 Enable +#define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Po= rt IOxAPIC Range 2 Enable +#define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Po= rt IOxAPIC Range 3 Enable +#define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Po= rt IOxAPIC Range 4 Enable +#define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE Po= rt IOxAPIC Range 1 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE Po= rt IOxAPIC Range 2 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE Po= rt IOxAPIC Range 3 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE Po= rt IOxAPIC Range 4 Destination ID +#define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO= Range +#define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal= Throttling BIOS Assigned Thermal Base Address +#define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal= Throttling BIOS Assigned Thermal Base High Address +#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC Gen= eric I/O Range 1 +#define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC Gen= eric I/O Range 2 +#define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC Gen= eric I/O Range 3 +#define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC Gen= eric I/O Range 4 +#define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC Gen= eric Memory Range +#define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIO= S Decode Enable +#define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode P= atch Region +#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode P= atch Region Enable +#define R_PCH_DMI_PCR_GCS 0x274C ///< Generic= Control and Status +#define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR Des= tination ID +#define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BI= OS Strap +#define B_PCH_DMI_PCR_RPR BIT11 ///< Reserve= d Page Route +#define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS In= terface Lock-Down +#define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Tra= p Register 1 +#define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Tra= p Register 2 +#define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Tra= p Register 3 +#define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Tra= p Register 4 +#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O= Decode Ranges +#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O= Enables +#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Bas= e Address +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Bas= e Address Mask +#define R_PCH_DMI_PCR_GPMR1 0x277C ///< General= Purpose Memory Range 1 +#define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General= Purpose Memory Range 1 Destination ID +#define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General= Purpose Memory Range 2 +#define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General= Purpose Memory Range 2 Destination ID +#define R_PCH_DMI_PCR_GPMR3 0x278C ///< General= Purpose Memory Range 3 +#define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General= Purpose Memory Range 3 Destination ID +#define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General= Purpose I/O Range 1 +#define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General= Purpose I/O Range 1 Destination ID +#define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General= Purpose I/O Range 2 +#define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General= Purpose I/O Range 2 Destination ID +#define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General= Purpose I/O Range 3 +#define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General= Purpose I/O Range 3 Destination ID +#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base= Address +#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base= Control +#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Ba= se Address +#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Ba= se Destination ID +#define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second = eSPI Generic Memory Range +#define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second = eSPI Generic I/O Range + +// +// Opi PHY registers +// +#define R_PCH_OPIPHY_PCR_0110 0x0110 +#define R_PCH_OPIPHY_PCR_0118 0x0118 +#define R_PCH_OPIPHY_PCR_011C 0x011C +#define R_PCH_OPIPHY_PCR_0354 0x0354 +#define R_PCH_OPIPHY_PCR_B104 0xB104 +#define R_PCH_OPIPHY_PCR_B10C 0xB10C + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsEva.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsEva.h new file mode 100644 index 0000000000..77ec6284a5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsEva.h @@ -0,0 +1,124 @@ +/** @file + Register names for PCH Eva devices. + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the= registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH__" in register/bit names. e.g., "_PCH_LPT_" + Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_EVA_H_ +#define _PCH_REGS_EVA_H_ + +#define PCI_DEVICE_NUMBER_EVA 17 +#define PCI_FUNCTION_NUMBER_EVA_MROM0 0 +#define PCI_FUNCTION_NUMBER_EVA_MROM1 1 +#define PCI_FUNCTION_NUMBER_EVA_SSATA 5 + +/// +/// Lewisburg SKUs +/// +#define LBG_SKU_G 1 +#define LBG_SKU_X 2 +#define LBG_SKU_A 3 + +#define PCI_DEVICE_NUMBER_PCH_SSATA 17 +#define PCI_FUNCTION_NUMBER_PCH_SSATA 5 + +#define R_PCH_LBG_SSATA_DEVICE_ID 0x02 + +/// +/// LBG Production sSATA Controller DID definition +/// +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI 0xA1D2 = // LBG Production Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID 0xA1D4 = // LBG Production Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA1D6 = // LBG Production Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1 0xA1DE = // LBG Production Server RAID 1/RRT + +/// +/// LBG Production (PRQ) MSUint SMBUS DID definition +/// +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_0 0xA1F0 = // LBG MS Unit MROM 0 PRQ DID +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_1 0xA1F1 = // LBG MS Unit MROM 1 PRQ DID + + +/// +/// LBG SSX (Super SKUs and Pre Production) sSATA Controller DID definiti= on +/// +#define V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI 0xA252 // L= BG SSX Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID 0xA254 // L= BG SSX Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA256 // L= BG SSX Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1 0xA25E // L= BG SSX Server RAID 1/RRT + +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2823 /= / Server RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2827 /= / Server RAID 0/1/5/10 - premium - Alternate ID for RSTe + +/// +/// LBG Super SKU (SSX) MSUint DID definition +/// +#define V_PCH_LBG_MROM_DEVICE_ID_0 0xA270 // = LBG NS MS Unit MROM 0 Super SKU DID +#define V_PCH_LBG_MROM_DEVICE_ID_1 0xA271 // = LBG NS MS Unit MROM 1 Super SKU DID + +#define R_PCH_LBG_MROM_DEVCLKGCTL 0xE4 + +#define R_PCH_LBG_MROM_PLKCTL 0xE8 +#define B_PCH_LBG_MROM_PLKCTL_CL BIT0 + +#define ADR_TMR_HELD_OFF_SETUP_OPTION 2 +#define R_PCH_LBG_MROM_ADRTIMERCTRL 0x180 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MASK (BIT27|BIT26|BIT25|BIT24) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT 24 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_8 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_24 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_40 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_56 0x4 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_64 0x5 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_72 0x6 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_80 0x7 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_88 0x8 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96 0x9 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MAX (V_PCH_LBG_MROM_ADRTIMER= CTRL_ADR_MULT_96) +#define ADR_MULT_SETUP_DEFAULT_POR 99 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_DBG_DIS BIT28 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_DIS BIT29 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MASK (BIT30|BIT31) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR 30 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_25US 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_50US 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MAX (V_PCH_LBG_MROM_ADRTIMER= CTRL_ADR_TMR_0US) +#define ADR_TMR_SETUP_DEFAULT_POR 4 + +/// +/// MS Unit Hide Control Register +/// +#define PCH_LBG_MSUINT_FUNCS 3 +#define R_PCH_LBG_MSUINT_MSDEVFUNCHIDE 0xD4 +#define B_PCH_LBG_MSUINT_MSDEVFUNCHIDE_RSVD (BIT30|BIT29|BIT28|BIT27|BI= T26|BIT25|BIT24|\ + BIT23|BIT22|BIT21|BIT20|BIT19|= BIT18|BIT17|\ + BIT16|BIT15|BIT14|BIT13|BIT12|= BIT11|BIT10|\ + BIT9|BIT8|BIT7|BIT6|BIT4|BIT3|= BIT2) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_SSATA (BIT5) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM1 BIT1 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM0 BIT0 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_REGLOCK BIT31 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsFia.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsFia.h new file mode 100644 index 0000000000..c66de3404b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsFia.h @@ -0,0 +1,106 @@ +/** @file + Register definition for FIA component + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_FIA_H_ +#define _PCH_REGS_FIA_H_ + + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PID:FIA +// +#define PCH_MAX_PCI_SATA_COMBO_PORT 14 +#define PCH_MAX_FIA_DRCRM 3 +#define R_PCH_PCR_FIA_CC 0 +#define B_PCH_PCR_FIA_CC_SRL BIT31 +#define B_PCH_PCR_FIA_CC_PTOCGE BIT17 +#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16 +#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15 + +#define R_PCH_PCR_FIA_PLLCTL 0x20 +#define R_PCH_PCR_FIA_DRCRM1 0x100 +#define R_PCH_PCR_FIA_DRCRM2 0x104 +#define R_PCH_PCR_FIA_DRCRM3 0x108 +#define N_PCH_PCR_FIA_DRCRM3_GBEPCKRQM 28 +#define S_PCH_PCR_FIA_DRCRM 4 +#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 |= BIT28) +#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28 +#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204 +#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208 +#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C +#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210 +#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214 +#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218 +#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C +#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220 +#define R_PCH_PCR_FIA_PCIEUDL_STRPFUSECFG_REG_BASE 0x224 +#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250 +#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254 +#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258 +#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C +#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0 +#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1 +#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2 +#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3 +#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5 + +#define V_PCH_PCR_FIA_LANE_OWN_UX8 0x8 + +#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | B= IT5 | BIT4) + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsGpio.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsGpio.h new file mode 100644 index 0000000000..bbf4df90ae --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsGpio.h @@ -0,0 +1,531 @@ +/** @file + Register names for PCH GPIO + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_GPIO_H_ +#define _PCH_REGS_GPIO_H_ + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11 +#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20 +#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11 + +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define V_PCH_GPIO_GROUP_MAX 13 +#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX +#define V_PCH_LP_GPIO_GROUP_MAX 8 +#define PCH_GPIO_NUM_SUPPORTED_GPIS 261 +#define S_GPIO_PCR_GP_SMI_EN 4 +#define S_GPIO_PCR_GP_SMI_STS 4 + +/// +/// Groups mapped to 2-tier General Purpose Event will all be under +/// one master GPE_111 (0x6F) +/// +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F + + +// +// GPIO Common Private Configuration Registers +// +#define R_GPIO_PCR_REV_ID 0x00 +#define R_GPIO_PCR_CAP_LIST 0x04 +#define R_GPIO_PCR_FAMBAR 0x08 +#define R_GPIO_PCR_PADBAR 0x0C +#define B_GPIO_PCR_PADBAR 0x0000FFFF +#define R_GPIO_PCR_MISCCFG 0x10 +#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16 +#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12 +#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8 +#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3 +#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3 +#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1 +#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14 + +// +// GPIO Community 0 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580 + +// Common +#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 1 Private Configuration Registers +// +//SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40 +#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0 +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4 +//SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38 +// Server SKX PCH +#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74 +// Common +#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138 +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148 +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158 +#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160 +#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168 +#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170 +#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178 + + +// Common: +#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200 +#define R_GPIO_PCR_PWMC 0x0204 +#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208 +#define R_GPIO_PCR_GP_SER_BLINK 0x020C +#define B_GPIO_PCR_GP_SER_BLINK 0x1F +#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210 +#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22) +#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22 +#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000 +#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16 +#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8 +#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0 +#define R_GPIO_PCR_GP_SER_DATA 0x0210 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 + +// +// GPIO Community 2 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4 +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64 +// Common +#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 + +// +// GPIO Community 3 Private Configuration Registers +// +// SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0 +#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400 + +// +// GPIO Community 4 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 5 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580 + + + + +// +// Define Pad Number +// +#define V_GPIO_PAD0 0 +#define V_GPIO_PAD1 1 +#define V_GPIO_PAD2 2 +#define V_GPIO_PAD3 3 +#define V_GPIO_PAD4 4 +#define V_GPIO_PAD5 5 +#define V_GPIO_PAD6 6 +#define V_GPIO_PAD7 7 +#define V_GPIO_PAD8 8 +#define V_GPIO_PAD9 9 +#define V_GPIO_PAD10 10 +#define V_GPIO_PAD11 11 +#define V_GPIO_PAD12 12 +#define V_GPIO_PAD13 13 +#define V_GPIO_PAD14 14 +#define V_GPIO_PAD15 15 +#define V_GPIO_PAD16 16 +#define V_GPIO_PAD17 17 +#define V_GPIO_PAD18 18 +#define V_GPIO_PAD19 19 +#define V_GPIO_PAD20 20 +#define V_GPIO_PAD21 21 +#define V_GPIO_PAD22 22 +#define V_GPIO_PAD23 23 + +// +// Host Software Pad Ownership modes +// +#define V_GPIO_PCR_HOSTSW_OWN_ACPI 0x00 +#define V_GPIO_PCR_HOSTSW_OWN_GPIO 0x01 + +// +// Pad Ownership modes +// +#define V_GPIO_PCR_PAD_OWN_HOST 0x00 +#define V_GPIO_PCR_PAD_OWN_CSME 0x01 +#define V_GPIO_PCR_PAD_OWN_ISH 0x02 + +// +// Pad Configuration Register DW0 +// + +//Pad Reset Config +#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30) +#define N_GPIO_PCR_RST_CONF 30 +#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00 +#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01 +#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02 +#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group + +//RX Pad State Select +#define B_GPIO_PCR_RX_PAD_STATE BIT29 +#define N_GPIO_PCR_RX_PAD_STATE 29 +#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00 +#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01 + +//RX Raw Overrride to 1 +#define B_GPIO_PCR_RX_RAW1 BIT28 +#define N_GPIO_PCR_RX_RAW1 28 +#define V_GPIO_PCR_RX_RAW1_DIS 0x00 +#define V_GPIO_PCR_RX_RAW1_EN 0x01 + +//RX Level/Edge Configuration +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25) +#define N_GPIO_PCR_RX_LVL_EDG 25 +#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00 +#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01 +#define V_GPIO_PCR_RX_LVL_EDG_0 0x02 +#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03 + +//RX Invert +#define B_GPIO_PCR_RXINV BIT23 +#define N_GPIO_PCR_RXINV 23 +#define V_GPIO_PCR_RXINV_NO 0x00 +#define V_GPIO_PCR_RXINV_YES 0x01 + +//GPIO Input Route IOxAPIC +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20 +#define N_GPIO_PCR_RX_APIC_ROUTE 20 +#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01 + +//GPIO Input Route SCI +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19 +#define N_GPIO_PCR_RX_SCI_ROUTE 19 +#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01 + +//GPIO Input Route SMI +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18 +#define N_GPIO_PCR_RX_SMI_ROUTE 18 +#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01 + +//GPIO Input Route NMI +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17 +#define N_GPIO_PCR_RX_NMI_ROUTE 17 +#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01 + +//GPIO Pad Mode +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_PAD_MODE 10 +#define V_GPIO_PCR_PAD_MODE_GPIO 0 +#define V_GPIO_PCR_PAD_MODE_NAT_1 1 +#define V_GPIO_PCR_PAD_MODE_NAT_2 2 +#define V_GPIO_PCR_PAD_MODE_NAT_3 3 +#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only + +//GPIO RX Disable +#define B_GPIO_PCR_RXDIS BIT9 +#define N_GPIO_PCR_RXDIS 9 +#define V_GPIO_PCR_RXDIS_EN 0x00 +#define V_GPIO_PCR_RXDIS_DIS 0x01 + +//GPIO TX Disable +#define B_GPIO_PCR_TXDIS BIT8 +#define N_GPIO_PCR_TXDIS 8 +#define V_GPIO_PCR_TXDIS_EN 0x00 +#define V_GPIO_PCR_TXDIS_DIS 0x01 + +//GPIO RX State +#define B_GPIO_PCR_RX_STATE BIT1 +#define N_GPIO_PCR_RX_STATE 1 +#define V_GPIO_PCR_RX_STATE_LOW 0x00 +#define V_GPIO_PCR_RX_STATE_HIGH 0x01 + +//GPIO TX State +#define B_GPIO_PCR_TX_STATE BIT0 +#define N_GPIO_PCR_TX_STATE 0 +#define V_GPIO_PCR_TX_STATE_LOW 0x00 +#define V_GPIO_PCR_TX_STATE_HIGH 0x01 + +// +// Pad Configuration Register DW1 +// + +//Padtol +#define B_GPIO_PCR_PADTOL BIT25 +#define N_GPIO_PCR_PADTOL 25 +#define V_GPIO_PCR_PADTOL_NONE 0x00 +#define V_GPIO_PCR_PADTOL_CLEAR 0x00 +#define V_GPIO_PCR_PADTOL_SET 0x01 + +//Termination +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_TERM 10 +#define V_GPIO_PCR_TERM_WPD_NONE 0x00 +#define V_GPIO_PCR_TERM_WPD_5K 0x02 +#define V_GPIO_PCR_TERM_WPD_20K 0x04 +#define V_GPIO_PCR_TERM_WPU_NONE 0x08 +#define V_GPIO_PCR_TERM_WPU_1K 0x09 +#define V_GPIO_PCR_TERM_WPU_2K 0x0B +#define V_GPIO_PCR_TERM_WPU_5K 0x0A +#define V_GPIO_PCR_TERM_WPU_20K 0x0C +#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D +#define V_GPIO_PCR_TERM_NATIVE 0x0F + +//Interrupt number +#define B_GPIO_PCR_INTSEL 0x7F +#define N_GPIO_PCR_INTSEL 0 + +// +// Ownership +// +#define V_GPIO_PCR_OWN_GPIO 0x01 +#define V_GPIO_PCR_OWN_ACPI 0x00 + +// +// GPE +// +#define V_GPIO_PCR_GPE_EN 0x01 +#define V_GPIO_PCR_GPE_DIS 0x00 +// +// SMI +// +#define V_GPIO_PCR_SMI_EN 0x01 +#define V_GPIO_PCR_SMI_DIS 0x00 +// +// NMI +// +#define V_GPIO_PCR_NMI_EN 0x01 +#define V_GPIO_PCR_NMI_DIS 0x00 +// +// Reserved: RSVD1 +// +#define V_PCH_GPIO_RSVD1 0x00 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsHda.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsHda.h new file mode 100644 index 0000000000..b7c737be42 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsHda.h @@ -0,0 +1,271 @@ +/** @file + Register names for PCH High Definition Audio device. + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// HD-A Controller Registers (D31:F3) +// +// PCI Configuration Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_HDA 31 +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 + +#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_LP_HDA_DEVICE_ID_0 0x9D70 +#define V_PCH_LP_HDA_DEVICE_ID_1 0x9D71 +#define V_PCH_LP_HDA_DEVICE_ID_2 0x9D72 +#define V_PCH_LP_HDA_DEVICE_ID_3 0x9D73 +#define V_PCH_LP_HDA_DEVICE_ID_4 0x9D74 +#define V_PCH_LP_HDA_DEVICE_ID_5 0x9D75 +#define V_PCH_LP_HDA_DEVICE_ID_6 0x9D76 +#define V_PCH_LP_HDA_DEVICE_ID_7 0x9D77 +#define V_PCH_H_HDA_DEVICE_ID_0 0xA170 +#define V_PCH_H_HDA_DEVICE_ID_1 0xA171 +#define V_PCH_H_HDA_DEVICE_ID_2 0xA172 +#define V_PCH_H_HDA_DEVICE_ID_3 0xA173 +#define V_PCH_H_HDA_DEVICE_ID_4 0xA174 +#define V_PCH_H_HDA_DEVICE_ID_5 0xA175 +#define V_PCH_H_HDA_DEVICE_ID_6 0xA176 +#define V_PCH_H_HDA_DEVICE_ID_7 0xA177 +// +// LBG SSX (Super SKU) DIDs +// +#define V_PCH_LBG_HDA_DEVICE_ID_0 0xA270 +#define V_PCH_LBG_HDA_DEVICE_ID_1 0xA271 +#define V_PCH_LBG_HDA_DEVICE_ID_2 0xA272 +#define V_PCH_LBG_HDA_DEVICE_ID_3 0xA273 +#define V_PCH_LBG_HDA_DEVICE_ID_4 0xA274 +#define V_PCH_LBG_HDA_DEVICE_ID_5 0xA275 +#define V_PCH_LBG_HDA_DEVICE_ID_6 0xA276 +#define V_PCH_LBG_HDA_DEVICE_ID_7 0xA277 +// +// LBG PRODUCTION (PRQ) DIDs +// +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_0 0xA1F0 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_1 0xA1F1 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_2 0xA1F2 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_3 0xA1F3 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_4 0xA1F4 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_5 0xA1F5 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_6 0xA1F6 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_7 0xA1F7 + + +#define R_PCH_HDA_PI 0x09 +#define V_PCH_HDA_PI_ADSP_UAA 0x80 +#define R_PCH_HDA_SCC 0x0A +#define V_PCH_HDA_SCC_ADSP 0x01 +#define R_PCH_HDA_HDALBA 0x10 +#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000 +#define V_PCH_HDA_HDBAR_SIZE (1 << 14) +#define R_PCH_HDA_HDAUBA 0x14 +#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MEMDCGE BIT0 +#define B_PCH_HDA_CGCTL_ADSPDCGE BIT1 +#define B_PCH_HDA_CGCTL_GPDMADCGE BIT2 +#define B_PCH_HDA_CGCTL_HDALDCGE BIT3 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define B_PCH_HDA_CGCTL_ODMABDCGE BIT4 +#define B_PCH_HDA_CGCTL_IDMABDCGE BIT5 +#define B_PCH_HDA_CGCTL_IOSFBDCGE BIT7 +#define B_PCH_HDA_CGCTL_IOSFSDCGE BIT8 +#define B_PCH_HDA_CGCTL_DMICDCGE BIT10 +#define B_PCH_HDA_CGCTL_I2SDCGE BIT11 +#define B_PCH_HDA_CGCTL_APTCGE BIT16 +#define B_PCH_HDA_CGCTL_XOTCGE BIT17 +#define B_PCH_HDA_CGCTL_SROTCGE BIT18 +#define B_PCH_HDA_CGCTL_IOSFBTCGE BIT19 +#define B_PCH_HDA_CGCTL_IOSFSTCGE BIT20 +#define B_PCH_HDA_CGCTL_FROTCGE BIT21 +#define B_PCH_HDA_CGCTL_APLLSE BIT31 +#define V_PCH_HDA_CGCTL_CGEN (B_PCH_HDA_CGCTL_MEMDCGE | \ + B_PCH_HDA_CGCTL_ADSPDCGE | \ + B_PCH_HDA_CGCTL_GPDMADCGE | \ + B_PCH_HDA_CGCTL_HDALDCGE | \ + B_PCH_HDA_CGCTL_MISCBDCGE | \ + B_PCH_HDA_CGCTL_ODMABDCGE | \ + B_PCH_HDA_CGCTL_IDMABDCGE | \ + B_PCH_HDA_CGCTL_IOSFBDCGE | \ + B_PCH_HDA_CGCTL_IOSFSDCGE | \ + B_PCH_HDA_CGCTL_DMICDCGE | \ + B_PCH_HDA_CGCTL_I2SDCGE | \ + B_PCH_HDA_CGCTL_APTCGE | \ + B_PCH_HDA_CGCTL_XOTCGE | \ + B_PCH_HDA_CGCTL_SROTCGE | \ + B_PCH_HDA_CGCTL_IOSFBTCGE | \ + B_PCH_HDA_CGCTL_IOSFSTCGE | \ + B_PCH_HDA_CGCTL_FROTCGE | \ + B_PCH_HDA_CGCTL_APLLSE ) +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define R_PCH_HDA_PC 0x52 +#define V_PCH_HDA_PC_PMES 0x18 +#define N_PCH_HDA_PC_PMES 11 +#define R_PCH_HDA_PCS 0x54 +#define B_PCH_HDA_PCS_PMES BIT15 +#define B_PCH_HDA_PCS_PMEE BIT8 +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) +#define R_PCH_HDA_MMC 0x62 +#define B_PCH_HDA_MMC_ME BIT0 +#define R_PCH_HDA_DEVC 0x78 +#define B_PCH_HDA_DEVC_NSNPEN BIT11 +#define R_PCH_HDA_SEM1 0xC0 +#define B_PCH_HDA_SEM1_LFLCS BIT24 +#define B_PCH_HDA_SEM1_BLKC3DIS BIT17 +#define B_PCH_HDA_SEM1_TMODE BIT12 +#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9) +#define R_PCH_HDA_SEM2 0xC4 +#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26) +#define V_PCH_HDA_SEM2_BSMT 0x1 +#define N_PCH_HDA_SEM2_BSMT 26 +#define B_PCH_HDA_SEM2_VC0PSNR BIT24 +#define R_PCH_HDA_SEM3L 0xC8 +#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2 +#define N_PCH_HDA_SEM3L_ISL1EXT2 20 +#define R_PCH_HDA_SEM4L 0xD0 +#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3 +#define N_PCH_HDA_SEM4L_OSL1EXT2 20 + +// +// Memory Space Registers +// +// +// Resides in 'HD Audio Global Registers' (0000h) +// +#define R_PCH_HDABA_GCAP 0x00 +#define R_PCH_HDABA_GCTL 0x08 +#define B_PCH_HDABA_GCTL_CRST BIT0 + +#define R_PCH_HDABA_OUTPAY 0x04 +#define R_PCH_HDABA_INPAY 0x06 +#define V_PCH_HDABA_INPAY_DEFAULT 0x1C + +#define R_PCH_HDABA_WAKEEN 0x0C +#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3 +#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2 +#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1 +#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0 + +#define R_PCH_HDABA_WAKESTS 0x0E +#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3 +#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2 +#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1 +#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0 + +// +// Resides in 'HD Audio Controller Registers' (0030h) +// +#define R_PCH_HDABA_IC 0x60 +#define R_PCH_HDABA_IR 0x64 +#define R_PCH_HDABA_ICS 0x68 +#define B_PCH_HDABA_ICS_IRV BIT1 +#define B_PCH_HDABA_ICS_ICB BIT0 + +// +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +// +#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe = Capability Structure (Memory Space, offset 0800h) +#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04) +#define B_PCH_HDABA_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define V_PCH_HDA_HDALINK_INDEX 0 +#define V_PCH_HDA_IDISPLINK_INDEX 1 + +#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links C= apability Structure (Memory Space, offset 0C00h) +#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 += (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_PCH_HDABA_LCTLX_CPA BIT23 +#define B_PCH_HDABA_LCTLX_SPA BIT16 +#define N_PCH_HDABA_LCTLX_SCF 0 +#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0 +#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1 +#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2 +#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3 +#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4 + +// +// Resides in 'HD Audio Vendor Specific Registers' (1000h) +// +#define R_PCH_HDABA_LTRC 0x1048 +#define V_PCH_HDABA_LTRC_GB 0x29 +#define N_PCH_HDABA_LTRC_GB 0 +#define R_PCH_HDABA_PCE 0x104B +#define B_PCH_HDABA_PCE_D3HE BIT2 + +// +// Private Configuration Space Registers +// +// +// Resides in IOSF & Fabric Configuration Registers (000h) +// +#define R_PCH_PCR_HDA_TTCCFG 0xE4 +#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1 + +// +// Resides in PCI & Codec Configuration Registers (500h) +// +#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Confi= guration Registers (PCR, offset 500h) +#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00 +#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8 +#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG += 0x30) +#define B_PCH_PCR_HDA_FNCFG_PGD BIT5 +#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4 +#define B_PCH_PCR_HDA_FNCFG_CGD BIT3 +#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2 + +#define B_PCH_PCR_HDA_FNCFG_HDASPCID BIT1 + +#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0 +#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG += 0x34) +#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2 + +// +// Resides in Power Management & EBB Configuration Registers (600h) +// +#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management = & EBB Configuration Registers (PCR, offset 600h) +#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG += 0x10) +#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000 +#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG += 0x14) +#define V_PCH_PCR_HDA_APLLP1 0x00003F00 +#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG += 0x18) +#define V_PCH_PCR_HDA_APLLP2 0x0000011D +#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG += 0x1C) +#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8) +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3 +#define N_PCH_PCR_HDA_IOBCTL_OSEL 8 +#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsHsio.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsHsio.h new file mode 100644 index 0000000000..52a27fccf5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsHsio.h @@ -0,0 +1,190 @@ +/** @file + Register definition for HSIO + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_HSIO_H_ +#define _PCH_REGS_HSIO_H_ + +#define B_HSIO_PCR_ACCESS_TYPE (BIT15 | BIT14) +#define N_HSIO_PCR_ACCESS_TYPE 14 +#define V_HSIO_PCR_ACCESS_TYPE_BDCAST (BIT15 | BIT14) +#define V_HSIO_PCR_ACCESS_TYPE_MULCAST BIT15 +#define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9) +#define B_HSIO_PCR_FUNCTION_NO (BIT8 | BIT7) +#define N_HSIO_PCR_FUNCTION_NO 7 +#define B_HSIO_PCR_REG_OFFSET (BIT6 | BIT5 | B= IT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define V_HSIO_PCR_ACCESS_TYPE_BCAST 0x03 +#define V_HSIO_PCR_ACCESS_TYPE_MCAST 0x02 +#define V_HSIO_PCR_ACCESS_TYPE_UCAST 0x00 + +#define V_HSIO_PCR_LANE_GROUP_NO_CMN_LANE 0x00 + +#define V_HSIO_PCR_FUNCTION_NO_PCS 0x00 +#define V_HSIO_PCR_FUNCTION_NO_TX 0x01 +#define V_HSIO_PCR_FUNCTION_NO_RX 0x02 + +#define V_HSIO_PCR_FUNCTION_NO_CMNDIG 0x00 +#define V_HSIO_PCR_FUNCTION_NO_CMNANA 0x01 +#define V_HSIO_PCR_FUNCTION_NO_PLL 0x02 + +#define R_HSIO_PCR_PCS_DWORD4 0x10 + +#define R_HSIO_PCR_PCS_DWORD8 0x20 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000 +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00 +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8 + +#define R_HSIO_PCR_PCS_DWORD9 0x24 +#define B_HSIO_PCR_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29 + +#define R_HSIO_PCR_RX_DWORD8 0x120 +#define B_HSIO_PCR_RX_DWORD8_ICFGDFETAP3_EN BIT10 + +#define R_HSIO_PCR_RX_DWORD9 0x124 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30 + +#define R_HSIO_PCR_RX_DWORD12 0x130 +#define B_HSIO_PCR_RX_DWORD12_O_CFGEWMARGINSEL BIT14 + +#define R_HSIO_PCR_RX_DWORD20 0x150 +#define B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28= | BIT27 | BIT26 | BIT25 | BIT24) +#define N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24 + +#define R_HSIO_PCR_RX_DWORD21 0x154 +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12= | BIT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8 +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 |= BIT3 | BIT2 | BIT1 | BIT0) +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0 + +#define R_HSIO_PCR_RX_DWORD23 0x15C +#define B_HSIO_PCR_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2 +#define B_HSIO_PCR_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4 + +#define R_HSIO_PCR_RX_DWORD25 0x164 +#define B_HSIO_PCR_RX_DWORD25_RX_TAP_CFG_CTRL BIT3 +#define B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000 +#define N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16 + +#define R_HSIO_PCR_RX_DWORD26 0x168 +#define B_HSIO_PCR_RX_DWORD26_SATA_EQ_DIS BIT16 + +#define R_HSIO_PCR_RX_DWORD34 0x188 +#define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | B= IT12) +#define N_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12 + +#define R_HSIO_PCR_RX_DWORD44 0x1B0 +#define B_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000 +#define N_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16 + +#define R_HSIO_PCR_RX_DWORD39 0x19C +#define B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0 0x7C0000 +#define N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0 18 + +#define R_HSIO_PCR_RX_DWORD40 0x1A0 +#define B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP 0xFF000000 +#define N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP 24 + +#define R_HSIO_PCR_RX_DWORD41 0x1A4 +#define B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS 0xFFFFFF +#define N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS 0 + +#define R_HSIO_PCR_RX_DWORD7 0x11C +#define B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL 0xF8000000 +#define N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL 27 + + +#define R_HSIO_PCR_RX_DWORD56 0x1E0 +#define B_HSIO_PCR_RX_DWORD56_ICFGPIDACCFGVALID BIT16 + +#define R_HSIO_PCR_RX_DWORD57 0x1E4 +#define B_HSIO_PCR_RX_DWORD57_JIM_COURSE BIT30 +#define B_HSIO_PCR_RX_DWORD57_JIM_ENABLE BIT29 +#define B_HSIO_PCR_RX_DWORD57_JIMMODE BIT28 +#define B_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000 +#define N_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 24 +#define B_HSIO_PCR_RX_DWORD57_ICFGMARGINEN BIT0 + +#define R_HSIO_PCR_RX_DWORD59 0x1EC +#define R_HSIO_PCR_RX_DWORD60 0x1F0 + +#define R_HSIO_PCR_TX_DWORD5 0x94 +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16 +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8 + +#define R_HSIO_PCR_TX_DWORD6 0x98 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT= 3 | BIT2 | BIT1 | BIT0) + +#define R_HSIO_PCR_TX_DWORD8 0xA0 +#define B_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | B= IT27 | BIT26 | BIT25 | BIT24) +#define N_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 24 +#define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 16 +#define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 8 + +#define R_HSIO_PCR_TX_DWORD19 0xCC + +#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020 +#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220 +#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820 +#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020 +#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220 +#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420 +#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620 +#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20 +#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20 + +#define R_HSIO_PCR_CLANE0_CMN_ANA_DWORD2 0x8088 +#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN = BIT5 +#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDE= N BIT3 + +#define R_HSIO_PCR_PLL_SSC_DWORD2 0x8108 +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | B= IT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16 +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN BIT10 +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN 10 + +#define R_HSIO_PCR_PLL_SSC_DWORD3 0x810C +#define B_HSIO_PCR_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0 + +#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030 +#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0 + +// +// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/= write access +// +#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0 +#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000 +#define R_PCH_PCR_MMP0_IMPREG21 0x1050 +#define R_PCH_PCR_MMP0_IMPREG22 0x1054 +#define R_PCH_PCR_MMP0_IMPREG23 0x1058 +#define R_PCH_PCR_MMP0_IMPREG24 0x105C +#define R_PCH_PCR_MMP0_IMPREG25 0x1060 +#define R_PCH_PCR_MMP0_CMNREG4 0xF00C +#define R_PCH_PCR_MMP0_CMNREG15 0xF038 +#define R_PCH_PCR_MMP0_CMNREG16 0xF03C + +#endif //_PCH_REGS_HSIO_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsItss.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsItss.h new file mode 100644 index 0000000000..fecfe22c5c --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsItss.h @@ -0,0 +1,90 @@ +/** @file + Register names for ITSS + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_ITSS_H_ +#define _PCH_REGS_ITSS_H_ + +// +// ITSS PCRs (PID:ITSS) +// +#define R_ITSS_PCR_PIRQA_ROUT 0x3100 ///< PIRQA Routi= ng Control register +#define R_ITSS_PCR_PIRQB_ROUT 0x3101 ///< PIRQB Routi= ng Control register +#define R_ITSS_PCR_PIRQC_ROUT 0x3102 ///< PIRQC Routi= ng Control register +#define R_ITSS_PCR_PIRQD_ROUT 0x3103 ///< PIRQD Routi= ng Control register +#define R_ITSS_PCR_PIRQE_ROUT 0x3104 ///< PIRQE Routi= ng Control register +#define R_ITSS_PCR_PIRQF_ROUT 0x3105 ///< PIRQF Routi= ng Control register +#define R_ITSS_PCR_PIRQG_ROUT 0x3106 ///< PIRQG Routi= ng Control register +#define R_ITSS_PCR_PIRQH_ROUT 0x3107 ///< PIRQH Routi= ng Control register +#define B_ITSS_PCR_PIRQX_ROUT_REN 0x80 ///< Interrupt R= outing Enable +#define B_ITSS_PCR_PIRQX_ROUT_IR 0x0F ///< IRQ Routng +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx= to IRQ3 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx= to IRQ4 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx= to IRQ5 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx= to IRQ6 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx= to IRQ7 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx= to IRQ9 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx= to IRQ10 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx= to IRQ11 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx= to IRQ12 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx= to IRQ14 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx= to IRQ15 + +#define R_ITSS_PCR_PIR0 0x3140 ///< PCI Interru= pt Route 0 +#define R_ITSS_PCR_PIR1 0x3142 ///< PCI Interru= pt Route 1 +#define R_ITSS_PCR_PIR2 0x3144 ///< PCI Interru= pt Route 2 +#define R_ITSS_PCR_PIR3 0x3146 ///< PCI Interru= pt Route 3 +#define R_ITSS_PCR_PIR4 0x3148 ///< PCI Interru= pt Route 4 +#define R_ITSS_PCR_PIR5 0x314A ///< PCI Interru= pt Route 5 +#define R_ITSS_PCR_PIR6 0x314C ///< PCI Interru= pt Route 6 +#define R_ITSS_PCR_PIR7 0x314E ///< PCI Interru= pt Route 7 +#define R_ITSS_PCR_PIR8 0x3150 ///< PCI Interru= pt Route 8 +#define R_ITSS_PCR_PIR9 0x3152 ///< PCI Interru= pt Route 9 +#define R_ITSS_PCR_PIR10 0x3154 ///< PCI Interru= pt Route 10 +#define R_ITSS_PCR_PIR11 0x3156 ///< PCI Interru= pt Route 11 +#define R_ITSS_PCR_PIR12 0x3158 ///< PCI Interru= pt Route 12 + +#define R_ITSS_PCR_GIC 0x31FC ///< General Int= errupt Control +#define B_ITSS_PCR_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ ent= ry size, 1 =3D 24 entry size, 0 =3D 120 entry size +#define B_ITSS_PCR_GIC_SERM BIT8 ///< Server Erro= r Reporting Mode +#define B_ITSS_PCR_GIC_AME BIT17 ///< Alternate A= ccess Mode Enable +#define B_ITSS_PCR_GIC_SPS BIT16 ///< Shutdown Po= licy Select +#define N_ITSS_PCR_GIC_SPS 16 ///< Shutdown Po= licy Select bit shift +#define R_ITSS_PCR_IPC0 0x3200 ///< Interrupt P= olarity Control 0 +#define R_ITSS_PCR_IPC1 0x3204 ///< Interrupt P= olarity Control 1 +#define R_ITSS_PCR_IPC2 0x3208 ///< Interrupt P= olarity Control 2 +#define R_ITSS_PCR_IPC3 0x320C ///< Interrupt P= olarity Control 3 +#define R_ITSS_PCR_ITSSPRC 0x3300 ///< ITSS Power = Reduction Control +#define B_ITSS_PCR_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynami= c Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynami= c Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_8254CGE BIT2 ///< 8254 Static= Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideba= nd Interface Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock = Gate Enable + +#define R_ITSS_PCR_MMC 0x3334 ///< Master Mess= age Control +#define B_ITSS_PCR_MMC_MSTRMSG_EN BIT0 ///< Master Mess= age Enable + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsLan.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsLan.h new file mode 100644 index 0000000000..d298e2ad66 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsLan.h @@ -0,0 +1,156 @@ +/** @file + Register names for PCH LAN device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// Gigabit LAN Controller configuration registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LAN 31 +#define PCI_FUNCTION_NUMBER_PCH_LAN 6 + +#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_LAN_DEVICE_ID 0x156F + +// +// LBG Production Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_PROD_LAN_DEVICE_ID 0xA1A5 +// +// LBG SSX (Super SKU) Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_LAN_DEVICE_ID 0xA225 + +#define V_PCH_LP_LAN_DEVICE_ID 0x156F +#define R_PCH_LAN_MBARA 0x10 +#define B_PCH_LAN_MBARA_BA 0xFFFE0000 +#define N_PCH_LAN_MBARA_ALIGN 17 +#define R_PCH_LAN_LTR_CAP 0xA8 +#define R_PCH_LAN_CLIST1 0xC8 +#define B_PCH_LAN_CLIST1_NEXT 0xFF00 +#define B_PCH_LAN_CLIST1_CID 0x00FF +#define R_PCH_LAN_PMC 0xCA +#define B_PCH_LAN_PMC_PMES 0xF800 +#define B_PCH_LAN_PMC_D2S BIT10 +#define B_PCH_LAN_PMC_D1S BIT9 +#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6) +#define B_PCH_LAN_PMC_DSI BIT5 +#define B_PCH_LAN_PMC_PMEC BIT3 +#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) +#define R_PCH_LAN_PMCS 0xCC +#define B_PCH_LAN_PMCS_PMES BIT15 +#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13) +#define B_PCH_LAN_PMCS_DSL 0x1E00 +#define V_PCH_LAN_PMCS_DSL0 0x0000 +#define V_PCH_LAN_PMCS_DSL3 0x0600 +#define V_PCH_LAN_PMCS_DSL4 0x0800 +#define V_PCH_LAN_PMCS_DSL7 0x0E00 +#define V_PCH_LAN_PMCS_DSL8 0x1000 +#define B_PCH_LAN_PMCS_PMEE BIT8 +#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0) +#define V_PCH_LAN_PMCS_PS0 0x00 +#define V_PCH_LAN_PMCS_PS3 0x03 +#define R_PCH_LAN_DR 0xCF +#define B_PCH_LAN_DR 0xFF +#define R_PCH_LAN_CLIST2 0xD0 +#define B_PCH_LAN_CLIST2_NEXT 0xFF00 +#define B_PCH_LAN_CLIST2_CID 0x00FF +#define R_PCH_LAN_MCTL 0xD2 +#define B_PCH_LAN_MCTL_CID BIT7 +#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_LAN_MCTL_MSIE BIT0 +#define R_PCH_LAN_MADDL 0xD4 +#define B_PCH_LAN_MADDL 0xFFFFFFFF +#define R_PCH_LAN_MADDH 0xD8 +#define B_PCH_LAN_MADDH 0xFFFFFFFF +#define R_PCH_LAN_MDAT 0xDC +#define B_PCH_LAN_MDAT 0xFFFFFFFF +#define R_PCH_LAN_FLRCAP 0xE0 +#define B_PCH_LAN_FLRCAP_NEXT 0xFF00 +#define B_PCH_LAN_FLRCAP_CID 0x00FF +#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13 +#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09 +#define R_PCH_LAN_FLRCLV 0xE2 +#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9 +#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8 +#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000 +#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF +#define R_PCH_LAN_DEVCTRL 0xE4 +#define B_PCH_LAN_DEVCTRL BIT0 +#define R_PCH_LAN_CPCE 0x80 +#define B_PCH_LAN_CPCE_HAE BIT5 +#define B_PCH_LAN_CPCE_SE BIT3 +#define B_PCH_LAN_CPCE_D3HE BIT2 +#define B_PCH_LAN_CPCE_I3E BIT1 +#define B_PCH_LAN_CPCE_PCMCRE BIT0 +#define R_PCH_LAN_CD0I3 0x84 +#define B_PCH_LAN_CD0I3_RR BIT3 +#define B_PCH_LAN_CD0I3_D0I3 BIT2 +#define R_PCH_LAN_CLCTL 0x94 +#define R_PCH_LAN_LANDISCTRL 0xA0 +#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0 +#define R_PCH_LAN_LOCKLANDIS 0xA4 +#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0 +// +// Gigabit LAN Capabilities and Status Registers (Memory space) +// +#define R_PCH_LAN_CSR_CTRL 0 +#define B_PCH_LAN_CSR_CTRL_MEHE BIT19 +#define R_PCH_LAN_CSR_STRAP 0x000C +#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11 +#define R_PCH_LAN_CSR_FEXTNVM6 0x0010 +#define R_PCH_LAN_CSR_CTRL_EXT 0x0018 +#define B_PCH_LAN_CSR_CTRL_EXT_CGEN BIT19 +#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11 +#define R_PCH_LAN_CSR_MDIC 0x0020 +#define B_PCH_LAN_CSR_MDIC_RB BIT28 +#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF +#define R_PCH_LAN_CSR_FEXT 0x002C +#define B_PCH_LAN_CSR_FEXT_WOL BIT30 +#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31 +#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00 +#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5 +#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8 +#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10 +#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6 +#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1 +#define R_PCH_LAN_CSR_F18 0x0F18 +#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31 +#define R_PCH_LAN_CSR_PBECCSTS 0x100C +#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16 +#define R_PCH_LAN_CSR_RAL 0x5400 +#define R_PCH_LAN_CSR_RAH 0x5404 +#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF +#define R_PCH_LAN_CSR_WUC 0x5800 +#define B_PCH_LAN_CSR_WUC_APME BIT0 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsLpc.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsLpc.h new file mode 100644 index 0000000000..356cc05f96 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsLpc.h @@ -0,0 +1,490 @@ +/** @file + Register names for PCH LPC/eSPI device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +#include +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +typedef enum { + PchHA0 =3D 0x00, + PchHB0 =3D 0x01, + PchHC0, + PchHD0, + PchHD1, +#ifdef SIMICS_FLAG + PchLpA0 =3D 0x20, +#endif + PchLpB0 =3D 0x23, + PchLpB1, + PchLpC0, + PchLpC1, + LbgA0 =3D LBG_A0, + LbgB0, + LbgB1, + LbgB2, + LbgB3, + LbgS0, + LbgS1, + LbgS2, + PchMiniA0, + PchSteppingMax +} PCH_STEPPING; + +#define PCH_H_MIN_SUPPORTED_STEPPING PchHA0 +#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0 + +#define PCH_LBG_MIN_SUPPORTED_STEPPING LbgA0 +#define R_PCH_LPC_VENDOR_ID 0x00 +#define R_PCH_LPC_DEVICE_ID 0x02 + +// +// +// SKL PCH Server/WS LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Ser= ver SKU Intel C236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Ser= ver SKU Intel C232 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Ser= ver SKU Intel CM236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Sup= er SKU Unlocked + +// +// SKL PCH-H Desktop LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH= H Desktop Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH= H Desktop Super SKU locked +#define V_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH= H Desktop H110 +#define V_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH= H Desktop H170 +#define V_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH= H Desktop Z170 +#define V_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH= H Desktop Q170 +#define V_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH= H Desktop Q150 +#define V_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH= H Desktop B150 +#define V_PCH_H_LPC_DEVICE_ID_UNFUSE 0xA140 ///< PCH= -H Unfuse +// +// PCH-H Mobile LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH= H Mobile Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH= H Mobile QM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH= H Mobile HM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_2 0xA14F ///< PCH= H Mobile QMS170 (SFF) +// +// PCH-LP LPC Device IDs +// +#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH= LP Mobile Super SKU unlocked +#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH= LP Mobile Super SKU locked +#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH= LP Mobile (U) Base SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH= LP Mobile (Y) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH= LP Mobile (U) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_UNFUSE 0x9D40 ///< PCH= LP Unfuse + +// +// Lewisburg Production LPC Device ID's +// +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_0 0xA1C0 ///< LBG= PRQ Unfused LBG 0 SKU +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_1G 0xA1C1 ///< LBG= PRQ Fused LBG 1G +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_2 0xA1C2 ///< LBG= PRQ Fused LBG 2 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_4 0xA1C3 ///< LBG= PRQ Fused LBG 4 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_E 0xA1C4 ///< LBG= PRQ Fused LBG E +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_M 0xA1C5 ///< LBG= PRQ Fused LBG M +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_T 0xA1C6 ///< LBG= PRQ Fused LBG T (both uplinks SKU - NS) +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_LP 0xA1C7 ///< LBG= PRQ Fused LBG LP +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C 0xA1CA ///< LBG= PRQ Fused LBG C +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C621A 0xA1CB ///< LBG= -R PRQ Fused LBG C621A +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C627A 0xA1CC ///< LBG= -R PRQ Fused LBG C627A +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_C629A 0xA1CD ///< LBG= -R PRQ Fused LBG C629A +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_ADG 0xA1CE ///< LBG= -R PRQ Fused LBG ADG + +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX 0xA1CF ///< 0xA= 1CF reserved for future QS/PRQ SKUs + +// +// Lewisburg SSX (Super SKUs and pre production) LPC Device ID's +// +#define V_PCH_LBG_LPC_DEVICE_ID_UNFUSED 0xA240 ///< LBG= SSX Unfused SKU +#define V_PCH_LBG_LPC_DEVICE_ID_SS_0 0xA241 ///< LBG= SSX Super SKU 0 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD 0xA242 ///< LBG= SSX Super SKU 4/SD +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS 0xA243 ///< LBG= SSX Super SKU T80/NS +#define V_PCH_LBG_LPC_DEVICE_ID_SS_1G 0xA244 ///< LBG= SSX Super SKU 1G +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T 0xA245 ///< LBG= Super SKU - T +#define V_PCH_LBG_LPC_DEVICE_ID_SS_L 0xA246 ///< LBG= Super SKU - L +#define V_PCH_LBG_LPC_DEVICE_ID_SS_C621A 0xA24A ///< LBG= -R Super SKU - C621A +#define V_PCH_LBG_LPC_DEVICE_ID_SS_C627A 0xA24B ///< LBG= -R Super SKU - C627A +#define V_PCH_LBG_LPC_DEVICE_ID_SS_C629A 0xA24C ///< LBG= -R Super SKU - C629A +#define V_PCH_LBG_LPC_DEVICE_ID_SS_ADG 0xA24E ///< LBG= -R Super SKU - ADG + +#define V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX 0xA24F ///< 0xA= 24D, 0xA24F Super SKU reserved + + +#define V_PCH_LBG_LPC_RID_0 0x00 ///< A0 = stepping +#define V_PCH_LBG_LPC_RID_1 0x01 ///< A1 = stepping +#define V_PCH_LBG_LPC_RID_2 0x02 ///< B0 = stepping +#define V_PCH_LBG_LPC_RID_3 0x03 ///< B1 = stepping +#define V_PCH_LBG_LPC_RID_4 0x04 ///< B2 = stepping +#define V_PCH_LBG_LPC_RID_5 0x05 ///< C0 = stepping +#define V_PCH_LBG_LPC_RID_8 0x08 ///< S0 = stepping +#define V_PCH_LBG_LPC_RID_9 0x09 ///< S1 = stepping +#define V_PCH_LBG_LPC_RID_A 0x0A ///< T0 = stepping + +#define V_PCH_MINI_LPC_RID_0 0xC0 ///< FPG= A PCH stepping + +#define V_LPC_CFG_RID_0 0x00 +#define V_LPC_CFG_RID_1 0x01 +#define V_LPC_CFG_RID_9 0x09 +#define V_LPC_CFG_RID_10 0x10 +#define V_LPC_CFG_RID_11 0x11 +#define V_LPC_CFG_RID_20 0x20 +#define V_LPC_CFG_RID_21 0x21 +#define V_LPC_CFG_RID_30 0x30 +#define V_LPC_CFG_RID_31 0x31 +#define R_LPC_CFG_SERIRQ_CNT 0x64 +#define B_LPC_CFG_SERIRQ_CNT_SIRQEN 0x80 +#define B_LPC_CFG_SERIRQ_CNT_SIRQMD 0x40 +#define B_LPC_CFG_SERIRQ_CNT_SIRQSZ 0x3C +#define N_LPC_CFG_SERIRQ_CNT_SIRQSZ 2 +#define B_LPC_CFG_SERIRQ_CNT_SFPW 0x03 +#define N_LPC_CFG_SERIRQ_CNT_SFPW 0 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_LPC_CFG_IOD 0x80 +#define B_LPC_CFG_IOD_FDD 0x1000 +#define N_LPC_CFG_IOD_FDD 12 +#define V_LPC_CFG_IOD_FDD_3F0 0 +#define V_LPC_CFG_IOD_FDD_370 1 +#define B_LPC_CFG_IOD_LPT 0x0300 +#define N_LPC_CFG_IOD_LPT 8 +#define V_LPC_CFG_IOD_LPT_378 0 +#define V_LPC_CFG_IOD_LPT_278 1 +#define V_LPC_CFG_IOD_LPT_3BC 2 +#define B_LPC_CFG_IOD_COMB 0x0070 +#define N_LPC_CFG_IOD_COMB 4 +#define V_LPC_CFG_IOD_COMB_3F8 0 +#define V_LPC_CFG_IOD_COMB_2F8 1 +#define V_LPC_CFG_IOD_COMB_220 2 +#define V_LPC_CFG_IOD_COMB_228 3 +#define V_LPC_CFG_IOD_COMB_238 4 +#define V_LPC_CFG_IOD_COMB_2E8 5 +#define V_LPC_CFG_IOD_COMB_338 6 +#define V_LPC_CFG_IOD_COMB_3E8 7 +#define B_LPC_CFG_IOD_COMA 0x0007 +#define N_LPC_CFG_IOD_COMA 0 +#define V_LPC_CFG_IOD_COMA_3F8 0 +#define V_LPC_CFG_IOD_COMA_2F8 1 +#define V_LPC_CFG_IOD_COMA_220 2 +#define V_LPC_CFG_IOD_COMA_228 3 +#define V_LPC_CFG_IOD_COMA_238 4 +#define V_LPC_CFG_IOD_COMA_2E8 5 +#define V_LPC_CFG_IOD_COMA_338 6 +#define V_LPC_CFG_IOD_COMA_3E8 7 +#define R_LPC_CFG_IOE 0x82 +#define B_LPC_CFG_IOE_ME2 BIT13 ///< Mic= rocontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC +#define B_LPC_CFG_IOE_SE BIT12 ///< Sup= er I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC. +#define B_LPC_CFG_IOE_ME1 BIT11 ///< Mic= rocontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LP= C. +#define B_LPC_CFG_IOE_KE BIT10 ///< Key= board Enable, Enables decoding of the keyboard I/O locations 60h and 64h to= LPC. +#define B_LPC_CFG_IOE_HGE BIT9 ///< Hig= h Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LP= C. +#define B_LPC_CFG_IOE_LGE BIT8 ///< Low= Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC. +#define B_LPC_CFG_IOE_FDE BIT3 ///< Flo= ppy Drive Enable, Enables decoding of the FDD range to LPC. Range is select= ed by LIOD.FDE +#define B_LPC_CFG_IOE_PPE BIT2 ///< Par= allel Port Enable, Enables decoding of the LPT range to LPC. Range is selec= ted by LIOD.LPT. +#define B_LPC_CFG_IOE_CBE BIT1 ///< Com= Port B Enable, Enables decoding of the COMB range to LPC. Range is selecte= d LIOD.CB. +#define B_LPC_CFG_IOE_CAE BIT0 ///< Com= Port A Enable, Enables decoding of the COMA range to LPC. Range is selecte= d LIOD.CA. +#define R_LPC_CFG_GEN1_DEC 0x84 +#define R_LPC_CFG_GEN2_DEC 0x88 +#define R_LPC_CFG_GEN3_DEC 0x8C +#define R_LPC_CFG_GEN4_DEC 0x90 +#define B_LPC_CFG_GENX_DEC_IODRA 0x00FC0000 +#define B_LPC_CFG_GENX_DEC_IOBAR 0x0000FFFC +#define B_LPC_CFG_GENX_DEC_EN 0x00000001 +#define R_LPC_CFG_ULKMC 0x94 +#define B_LPC_CFG_ULKMC_SMIBYENDPS BIT15 +#define B_LPC_CFG_ULKMC_TRAPBY64W BIT11 +#define B_LPC_CFG_ULKMC_TRAPBY64R BIT10 +#define B_LPC_CFG_ULKMC_TRAPBY60W BIT9 +#define B_LPC_CFG_ULKMC_TRAPBY60R BIT8 +#define B_LPC_CFG_ULKMC_SMIATENDPS BIT7 +#define B_LPC_CFG_ULKMC_PSTATE BIT6 +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5 +#define B_LPC_CFG_ULKMC_USBSMIEN BIT4 +#define B_LPC_CFG_ULKMC_64WEN BIT3 +#define B_LPC_CFG_ULKMC_64REN BIT2 +#define B_LPC_CFG_ULKMC_60WEN BIT1 +#define B_LPC_CFG_ULKMC_60REN BIT0 +#define R_LPC_CFG_LGMR 0x98 +#define B_LPC_CFG_LGMR_MA 0xFFFF0000 +#define B_LPC_CFG_LGMR_LMRD_EN BIT0 +#define R_LPC_CFG_PCCS1IORE 0xA0 +#define R_LPC_CFG_PCCS1GIR1 0xA4 +#define R_LPC_CFG_PCCS1GMR1 0xA8 +#define R_ESPI_CFG_CS1IORE 0xA0 +#define R_ESPI_CFG_CS1IORE_DPCS1RE BIT14 +#define R_ESPI_CFG_CS1GIR1 0xA4 +#define R_ESPI_CFG_CS1GMR1 0xA8 + +#define R_LPC_CFG_FWH_BIOS_SEL 0xD0 +#define B_LPC_CFG_FWH_BIOS_SEL_F8 0xF0000000 +#define B_LPC_CFG_FWH_BIOS_SEL_F0 0x0F000000 +#define B_LPC_CFG_FWH_BIOS_SEL_E8 0x00F00000 +#define B_LPC_CFG_FWH_BIOS_SEL_E0 0x000F0000 +#define B_LPC_CFG_FWH_BIOS_SEL_D8 0x0000F000 +#define B_LPC_CFG_FWH_BIOS_SEL_D0 0x00000F00 +#define B_LPC_CFG_FWH_BIOS_SEL_C8 0x000000F0 +#define B_LPC_CFG_FWH_BIOS_SEL_C0 0x0000000F +#define R_LPC_CFG_FWH_BIOS_SEL2 0xD4 +#define B_LPC_CFG_FWH_BIOS_SEL2_70 0xF000 +#define B_LPC_CFG_FWH_BIOS_SEL2_60 0x0F00 +#define B_LPC_CFG_FWH_BIOS_SEL2_50 0x00F0 +#define B_LPC_CFG_FWH_BIOS_SEL2_40 0x000F +#define R_LPC_CFG_BDE 0xD8 = ///< BIOS decode enable +#define B_LPC_CFG_BDE_F8 0x8000 +#define B_LPC_CFG_BDE_F0 0x4000 +#define B_LPC_CFG_BDE_E8 0x2000 +#define B_LPC_CFG_BDE_E0 0x1000 +#define B_LPC_CFG_BDE_D8 0x0800 +#define B_LPC_CFG_BDE_D0 0x0400 +#define B_LPC_CFG_BDE_C8 0x0200 +#define B_LPC_CFG_BDE_C0 0x0100 +#define B_LPC_CFG_BDE_LEG_F 0x0080 +#define B_LPC_CFG_BDE_LEG_E 0x0040 +#define B_LPC_CFG_BDE_70 0x0008 +#define B_LPC_CFG_BDE_60 0x0004 +#define B_LPC_CFG_BDE_50 0x0002 +#define B_LPC_CFG_BDE_40 0x0001 +#define R_LPC_CFG_PCC 0xE0 +#define B_LPC_CFG_PCC_CLKRUN_EN 0x0001 +#define B_LPC_CFG_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_LPC_CFG_FVEC0_USB_14_PORT 0x00000000 +#define V_LPC_CFG_FVEC0_USB_12_PORT 0x00000400 +#define V_LPC_CFG_FVEC0_USB_10_PORT 0x00000800 +#define B_LPC_CFG_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_LPC_CFG_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_LPC_CFG_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_LPC_CFG_FVEC0_PCI_CAP 0x00000002 +#define R_LPC_CFG_FVEC1 0x01 +#define B_LPC_CFG_FVEC1_USB_R_CAP 0x00400000 +#define R_LPC_CFG_FVEC2 0x02 +#define B_PCH_LPC_FVEC2_IATT_CAP 0x00400000 ///< Int= el Anti-Theft Technology Capability +#define V_LPC_CFG_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH= Integrated Graphics Support Capability +#define R_LPC_CFG_FVEC3 0x03 +#define B_LPC_CFG_FVEC3_DCMI_CAP 0x00002000 ///< Dat= a Center Manageability Interface (DCMI) Capability +#define B_LPC_CFG_FVEC3_NM_CAP 0x00001000 ///< Nod= e Manager Capability + +#define R_LPC_CFG_MDAP 0xC0 +#define B_LPC_CFG_MDAP_POLICY_EN BIT31 +#define B_LPC_CFG_MDAP_PDMA_EN BIT30 +#define B_LPC_CFG_MDAP_VALUE 0x0001FFFF + +// +// APM Registers +// +#define R_PCH_IO_APM_CNT 0xB2 +#define R_PCH_IO_APM_STS 0xB3 + +#define R_LPC_CFG_BC 0xDC ///< Bio= s Control +#define S_LPC_CFG_BC 1 +#define B_LPC_CFG_BC_BILD BIT7 ///< BIO= S Interface Lock-Down +#define B_LPC_CFG_BC_BBS BIT6 ///< Boo= t BIOS strap +#define N_LPC_CFG_BC_BBS 6 +#define V_LPC_CFG_BC_BBS_SPI 0 ///< Boo= t BIOS strapped to SPI +#define V_LPC_CFG_BC_BBS_LPC 1 ///< Boo= t BIOS strapped to LPC +#define B_LPC_CFG_BC_EISS BIT5 ///< Ena= ble InSMM.STS +#define B_LPC_CFG_BC_TS BIT4 ///< Top= Swap +#define B_LPC_CFG_BC_LE BIT1 ///< Loc= k Enable +#define N_LPC_CFG_BC_LE 1 +#define B_LPC_CFG_BC_WPD BIT0 ///< Wri= te Protect Disable + +#define R_ESPI_CFG_PCBC 0xDC ///< Per= ipheral Channel BIOS Control +#define S_ESPI_CFG_PCBC 4 ///< Per= ipheral Channel BIOS Control register size +#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIO= S Write Report Enable +#define N_ESPI_CFG_PCBC_BWRE 11 ///< BIO= S Write Report Enable bit position +#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIO= S Write Report Status +#define N_ESPI_CFG_PCBC_BWRS 10 ///< BIO= S Write Report Status bit position +#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIO= S Write Protect Disable Status +#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIO= S Write Protect Disable Status bit position +#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSP= I Enable Pin Strap +#define B_ESPI_CFG_PCBC_LE BIT1 ///< Loc= k Enable + +// +// Processor interface registers +// +#define R_PCH_IO_NMI_SC 0x61 +#define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_IO_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_IO_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_IO_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_IO_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_IO_NMI_EN 0x70 +#define B_PCH_IO_NMI_EN_NMI_EN BIT7 + +// +// Reset Generator I/O Port +// +#define R_PCH_IO_RST_CNT 0xCF9 +#define B_PCH_IO_RST_CNT_FULL_RST BIT3 +#define B_PCH_IO_RST_CNT_RST_CPU BIT2 +#define B_PCH_IO_RST_CNT_SYS_RST BIT1 +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E +#define V_PCH_IO_RST_CNT_HARDRESET 0x06 +#define V_PCH_IO_RST_CNT_SOFTRESET 0x04 +#define V_PCH_IO_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_IO_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_RTC_IO_INDEX 0x70 +#define R_RTC_IO_TARGET 0x71 +#define R_RTC_IO_EXT_INDEX 0x72 +#define R_RTC_IO_EXT_TARGET 0x73 +#define R_RTC_IO_INDEX_ALT 0x74 +#define R_RTC_IO_TARGET_ALT 0x75 +#define R_RTC_IO_EXT_INDEX_ALT 0x76 +#define R_RTC_IO_EXT_TARGET_ALT 0x77 +#define R_RTC_IO_REGA 0x0A +#define B_RTC_IO_REGA_UIP 0x80 +#define R_RTC_IO_REGB 0x0B +#define B_RTC_IO_REGB_SET 0x80 +#define B_RTC_IO_REGB_PIE 0x40 +#define B_RTC_IO_REGB_AIE 0x20 +#define B_RTC_IO_REGB_UIE 0x10 +#define B_RTC_IO_REGB_DM 0x04 +#define B_RTC_IO_REGB_HOURFORM 0x02 +#define R_RTC_IO_REGC 0x0C +#define R_RTC_IO_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_RTC_PCR_CONF 0x3400 ///< RT= C Configuration register +#define S_PCH_PCR_RTC_CONF 4 +#define B_RTC_PCR_CONF_UCMOS_LOCK BIT4 +#define B_RTC_PCR_CONF_LCMOS_LOCK BIT3 +#define B_PCH_PCR_RTC_CONF_RESERVED BIT31 +#define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///< Up= per CMOS bank enable +#define R_RTC_PCR_BUC 0x3414 ///< Ba= cked Up Control +#define B_RTC_PCR_BUC_TS BIT0 ///< To= p Swap +#define B_RTC_PCR_BUC_NMFLUSH BIT3 +#define R_RTC_PCR_RTCDCG 0x3418 ///< RT= C Dynamic Clock Gating Control +#define R_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ip= ciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define R_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0 ///< ro= sc_side_clk (120 MHz) Dynamic Clock Gate Enable +#define R_RTC_PCR_3F00 0x3F00 +#define R_RTC_PCR_UIPSMI 0x3F04 ///< RT= C Update In Progress SMI Control + +// +// LPC PCR Registers +// +#define R_LPC_PCR_HVMTCTL 0x3410 +#define R_LPC_PCR_GCFD 0x3418 +#define R_PCH_PCR_LPC_CCE 0x341C +#define B_PCH_PCR_LPC_CCE_LCG BIT0 +#define B_PCH_PCR_LPC_CCE_ISBICGEN BIT1 +#define B_PCH_PCR_LPC_CCE_IPICGEN BIT2 +#define B_PCH_PCR_LPC_CCE_PGCBCGEN BIT3 +#define V_PCH_PCR_LPC_CCE_CGEN (B_PCH_PCR_LPC_CCE_LCG = | \ + B_PCH_PCR_LPC_CCE_ISBICG= EN | \ + B_PCH_PCR_LPC_CCE_IPICGE= N | \ + B_PCH_PCR_LPC_CCE_PGCBCG= EN ) +#define R_LPC_PCR_PCT 0x3420 +#define R_LPC_PCR_SCT 0x3424 +#define R_LPC_PCR_LPCCT 0x3428 +#define R_LPC_PCR_ULTOR 0x3500 + +// +// eSPI PCR Registers +// +#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///<= Slave Configuration Register and Link Control +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///<= Slave Configuration Register Access Enable +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///<= Slave Configuration Register Access Status +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///<= Slave Configuration Register Access Status bit position +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///<= IOSF-SB eSPI Link Configuration Lock +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///<= No errors (transaction completed successfully) +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///<= Slave ID +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///<= Slave ID bit position +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///<= Slave Configuration Register Access Type +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///<= Slave Configuration Register Access Type bit position +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0 ///<= Slave Configuration register read from address SCRA[11:0] +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1 ///<= Slave Configuration register write to address SCRA[11:0] +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2 ///<= Slave Status register read +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3 ///<= In-Band reset +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///<= Slave Configuration Register Address +#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///<= Slave Configuration Register Data + +#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Periphe= ral Channel Error for Slave 0 +#define S_ESPI_PCR_PCERR_SLV0 4 ///< Periphe= ral Channel Error register size +#define B_ESPI_PCR_PCERR_PCFES BIT4 ///< Periphe= ral Channel Error Fatal Error Status bit +#define R_ESPI_PCR_PCERR_SLV1 0x4024 ///< Periphe= ral Channel Error for Slave 1 +#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual= Wire Channel Error for Slave 0 +#define S_ESPI_PCR_VWERR_SLV0 4 ///< Virtual= Wire Channel Error register size +#define B_ESPI_PCR_VWERR_VWFES BIT4 ///< Virtual= Wire Channel Error Fatal Error status bit +#define R_ESPI_PCR_VWERR_SLV1 0x4034 ///< Virtual= Wire Channel Error for Slave 1 +#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash A= ccess Channel Error for Slave 0 +#define B_ESPI_PCR_FCERR_FCNFES BIT12 ///< Flash A= ccess Channel Non-Fatal Error Status +#define B_ESPI_PCR_PCERR_FCNFEC (BIT11 | BIT10 | BIT9 | BIT8= ) ///< Non-Fatal Error Cause bits +#define N_ESPI_PCR_PCERR_FCNFEC 8 ///< Flash A= ccess Channel Error for Slave 0 bit position +#define V_ESPI_PCR_PCERR_FCNFEC_SRC_NFE 1 ///< Slave R= esponse Code: NONFATAL_ERROR +#define V_ESPI_PCR_PCERR_FCNFEC_SCR_UC 2 ///< Slave R= esponse Code: Unsuccessful Completion +#define V_ESPI_PCR_PCERR_FCNFEC_UCT 4 ///< Unsuppo= rted Cycle Type +#define V_ESPI_PCR_PCERR_FCNFEC_UA 6 ///< Unsuppo= rted Address +#define B_ESPI_PCR_FCERR_FCFES BIT4 ///< Flash A= ccess Channel Fatal Error status bit +#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fat= al Error Reporting Enable bits +#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fat= al Error Reporting Enable bit position +#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable = Non-Fatal Error Reporting as SMI +#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal E= rror Status +#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal E= rror Reporting Enable bits +#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal E= rror Reporting Enable bit position +#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable = Fatal Error Reporting as SMI +#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal E= rror Status +#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Periphe= ral Channel Unsupported Request Detected +#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Er= ror for Slave 0 +#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Er= ror for Slave 0 register size +#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Li= nk and Slave Channel Recovery Required +#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal E= rror Type 1 Reporting Enable +#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal E= rror Type 1 Reporting Enable bit position +#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable = Fatal Error Type 1 Reporting as SMI +#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fa= tal Error Type 1 Status +#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Er= ror for Slave 1 + +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI So= fstraps Register 0 +#define R_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# En= able + +// +// eSPI Slave registers +// +#define R_ESPI_PCR_SLAVE_PCREG 0x10 ///< Slave C= hannel 1 Capabilities and Configurations register (Peripheral Channel) +#define R_ESPI_PCR_SLAVE_VWREG 0x20 ///< Slave C= hannel 2 Capabilities and Configurations register (Virtual Wire Channel) +#define R_ESPI_PCR_SLAVE_FCREG 0x40 ///< Slave C= hannel 4 Capabilities and Configurations register (Flash Access Channel) +#define B_ESPI_PCR_SLAVE_CHEN BIT0 ///< Slave C= hannel enable bit +#define B_ESPI_PCR_SLAVE_CHRDY BIT1 ///< Slave C= hannel ready bit + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsP2sb.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsP2sb.h new file mode 100644 index 0000000000..f74fd5800b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsP2sb.h @@ -0,0 +1,132 @@ +/** @file + Register names for PCH P2SB device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D31:F1) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + +#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_P2SB_CFG_SBREG_BAR 0x10 +#define B_PCH_P2SB_SBREG_RBA 0xFF000000 +#define R_PCH_P2SB_SBREG_BARH 0x14 +#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF +#define R_PCH_P2SB_VBDF 0x50 +#define B_PCH_P2SB_VBDF_BUF 0xFF00 +#define B_PCH_P2SB_VBDF_DEV 0x00F8 +#define B_PCH_P2SB_VBDF_FUNC 0x0007 +#define R_PCH_P2SB_ESMBDF 0x52 +#define B_PCH_P2SB_ESMBDF_BUF 0xFF00 +#define B_PCH_P2SB_ESMBDF_DEV 0x00F8 +#define B_PCH_P2SB_ESMBDF_FUNC 0x0007 +#define R_PCH_P2SB_RCFG 0x54 +#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00 +#define B_PCH_P2SB_RCFG_RSE BIT0 +#define R_PCH_P2SB_HPTC 0x60 +#define B_PCH_P2SB_HPTC_AE BIT7 +#define B_PCH_P2SB_HPTC_AS 0x0003 +#define N_PCH_HPET_ADDR_ASEL 12 +#define V_PCH_HPET_BASE0 0xFED00000 +#define V_PCH_HPET_BASE1 0xFED01000 +#define V_PCH_HPET_BASE2 0xFED02000 +#define V_PCH_HPET_BASE3 0xFED03000 +#define R_PCH_P2SB_IOAC 0x64 +#define B_PCH_P2SB_IOAC_AE BIT8 +#define B_PCH_P2SB_IOAC_ASEL 0x00FF +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define R_PCH_IO_APIC_EOI 0xFEC00040 +#define R_PCH_P2SB_IBDF 0x6C +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_80 0x80 +#define R_PCH_P2SB_84 0x84 +#define R_PCH_P2SB_88 0x88 +#define R_PCH_P2SB_8C 0x8C +#define R_PCH_P2SB_90 0x90 +#define R_PCH_P2SB_94 0x94 +#define R_PCH_P2SB_98 0x98 +#define R_PCH_P2SB_9C 0x9C +#define R_PCH_P2SB_DISPBDF 0xA0 +#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000 +#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00 +#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8 +#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007 +#define R_PCH_P2SB_ICCOS 0xA4 +#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00 +#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF +#define R_PCH_P2SB_EPMASK0 0x220 +#define R_PCH_P2SB_EPMASK1 0x224 +#define R_PCH_P2SB_EPMASK2 0x228 +#define R_PCH_P2SB_EPMASK3 0x22C +#define R_PCH_P2SB_EPMASK4 0x230 +#define R_PCH_P2SB_EPMASK5 0x234 +#define R_PCH_P2SB_EPMASK6 0x238 +#define R_PCH_P2SB_EPMASK7 0x23C +#define B_PCH_P2SB_MASKLOCK BIT17 +// +// Definition for SBI +// +#define R_PCH_P2SB_SBIADDR 0xD0 +#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000 +#define B_PCH_P2SB_SBIADDR_RS 0x000F0000 +#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF +#define R_PCH_P2SB_SBIDATA 0xD4 +#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF +#define R_PCH_P2SB_SBISTAT 0xD8 +#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00 +#define B_PCH_P2SB_SBISTAT_POSTED BIT7 +#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006 +#define N_PCH_P2SB_SBISTAT_RESPONSE 1 +#define B_PCH_P2SB_SBISTAT_INITRDY BIT0 +#define R_PCH_P2SB_SBIRID 0xDA +#define B_PCH_P2SB_SBIRID_FBE 0xF000 +#define B_PCH_P2SB_SBIRID_BAR 0x0700 +#define B_PCH_P2SB_SBIRID_FID 0x00FF +#define R_PCH_P2SB_SBIEXTADDR 0xDC +#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_PCH_P2SB_E0 0xE0 +#define R_PCH_P2SB_PCE 0xE4 +#define R_PCH_P2SB_PCE_HAE BIT5 +#define R_PCH_P2SB_PCE_PMCRE BIT0 + +#define R_PCH_P2SB_F4 0xF4 +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsPcie.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsPcie.h new file mode 100644 index 0000000000..0d10c9dbeb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsPcie.h @@ -0,0 +1,620 @@ +/** @file + Register names for PCH PCI-E root port devices + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +#define PCI_INVALID_VALUE_16BIT 0xFFFF +#define PCI_INVALID_VALUE_32BIT 0xFFFFFFFF + +// +// PCH PCI Express Root Ports (D28:F0~7 & D29:F0~3) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3 + +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define V_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express= Root Port #1, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express= Root Port #2, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express= Root Port #3, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express= Root Port #4, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express= Root Port #5, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express= Root Port #6, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express= Root Port #7, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express= Root Port #8, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express= Root Port #9, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express= Root Port #10, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express= Root Port #11, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express= Root Port #12, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express= Root Port #13, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express= Root Port #14, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express= Root Port #15, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express= Root Port #16, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express= Root Port #17, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express= Root Port #18, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express= Root Port #19, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express= Root Port #20, SKL PCH H + +#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express= Root Port #1, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express= Root Port #2, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express= Root Port #3, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express= Root Port #4, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express= Root Port #5, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express= Root Port #6, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express= Root Port #7, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express= Root Port #8, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express= Root Port #9, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express= Root Port #10, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express= Root Port #11, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express= Root Port #12, SKL PCH LP PCIe Device ID + +#define V_PCH_QAT_DEVICE_ID 0x37c8 ///< PCH QAT Dev= ice ID + +// +// LBG Production (PRQ) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1 0xA190 ///< PCI Ex= press Root Port #1, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2 0xA191 ///< PCI Ex= press Root Port #2, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3 0xA192 ///< PCI Ex= press Root Port #3, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4 0xA193 ///< PCI Ex= press Root Port #4, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5 0xA194 ///< PCI Ex= press Root Port #5, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6 0xA195 ///< PCI Ex= press Root Port #6, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7 0xA196 ///< PCI Ex= press Root Port #7, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8 0xA197 ///< PCI Ex= press Root Port #8, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9 0xA198 ///< PCI Ex= press Root Port #9, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10 0xA199 ///< PCI Ex= press Root Port #10, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11 0xA19A ///< PCI Ex= press Root Port #11, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12 0xA19B ///< PCI Ex= press Root Port #12, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13 0xA19C ///< PCI Ex= press Root Port #13, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14 0xA19D ///< PCI Ex= press Root Port #14, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15 0xA19E ///< PCI Ex= press Root Port #15, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16 0xA19F ///< PCI Ex= press Root Port #16, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17 0xA1E7 ///< PCI Ex= press Root Port #17, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18 0xA1E8 ///< PCI Ex= press Root Port #18, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19 0xA1E9 ///< PCI Ex= press Root Port #19, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20 0xA1EA ///< PCI Ex= press Root Port #20, LBG PRQ +// +// LBG Super SKU (SSX) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT1 0xA210 ///< PCI Express Ro= ot Port #1, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT2 0xA211 ///< PCI Express Ro= ot Port #2, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT3 0xA212 ///< PCI Express Ro= ot Port #3, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT4 0xA213 ///< PCI Express Ro= ot Port #4, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT5 0xA214 ///< PCI Express Ro= ot Port #5, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT6 0xA215 ///< PCI Express Ro= ot Port #6, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT7 0xA216 ///< PCI Express Ro= ot Port #7, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT8 0xA217 ///< PCI Express Ro= ot Port #8, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT9 0xA218 ///< PCI Express Ro= ot Port #9, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT10 0xA219 ///< PCI Express Ro= ot Port #10, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT11 0xA21A ///< PCI Express Ro= ot Port #11, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT12 0xA21B ///< PCI Express Ro= ot Port #12, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT13 0xA21C ///< PCI Express Ro= ot Port #13, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT14 0xA21D ///< PCI Express Ro= ot Port #14, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT15 0xA21E ///< PCI Express Ro= ot Port #15, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT16 0xA21F ///< PCI Express Ro= ot Port #16, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT17 0xA267 ///< PCI Express Ro= ot Port #17, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT18 0xA268 ///< PCI Express Ro= ot Port #18, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT19 0xA269 ///< PCI Express Ro= ot Port #19, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT20 0xA26A ///< PCI Express Ro= ot Port #20, LBG SSKU +typedef enum { + PCIE_SPA, + PCIE_SPB, + PCIE_SPC, + PCIE_SPD, + PCIE_SPE +} PCIE_CONTROLLER_INDEX; + +#define R_PCH_PCIE_PCISTS 0x06 +#define B_PCH_PCIE_PCISTS_CAP_LST BIT4 +#define B_PCH_PCIE_XCAP_CV 0x000F +#define B_PCH_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BI= T4) + +#define R_PCH_PCIE_CLIST 0x40 +#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PC= IE_XCAP_OFFSET) +#define R_PCH_PCIE_CFG_DEVCAP (R_PCH_PCIE_CLIST + R_PC= IE_DCAP_OFFSET) +#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PC= IE_DCTL_OFFSET) +#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PC= IE_DSTS_OFFSET) +#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PC= IE_LCAP_OFFSET) +#define B_PCH_PCIE_LCAP_PN 0xFF000000 +#define N_PCH_PCIE_LCAP_PN 24 +#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PC= IE_LCTL_OFFSET) +#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PC= IE_LSTS_OFFSET) +#define R_PCH_PCIE_CFG_LINKSTS (R_PCH_PCIE_CLIST + R_PC= IE_LSTS_OFFSET) +#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PC= IE_SLCAP_OFFSET) +#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PC= IE_SLCTL_OFFSET) +#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PC= IE_SLSTS_OFFSET) +#define R_PCH_PCIE_CFG_ROOTCTL (R_PCH_PCIE_CLIST + R_PC= IE_RCTL_OFFSET) +#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PC= IE_RSTS_OFFSET) +#define R_PCH_PCIE_CFG_DCAP2 (R_PCH_PCIE_CLIST + R_PC= IE_DCAP2_OFFSET) +#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PC= IE_DCTL2_OFFSET) +#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PC= IE_LCTL2_OFFSET) +#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PC= IE_LSTS2_OFFSET) + + +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 + +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define R_PCH_PCIE_SSVID 0x94 +#define S_PCH_PCIE_SSVID 4 + +#define R_PCH_PCIE_PMCAP 0xA0 +#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PC= IE_PMCS_OFFST) + +#define R_PCH_PCIE_CCFG 0xD0 +#define B_PCH_PCIE_CCFG_UPMWPD BIT25 +#define B_PCH_PCIE_CCFG_UPSD BIT24 +#define B_PCH_PCIE_CCFG_UNSD BIT23 +#define B_PCH_PCIE_CCFG_NPAP BIT16 +#define B_PCH_PCIE_CCFG_DCGEISMA BIT15 +#define B_PCH_PCIE_CCFG_UNRD (BIT13 | BIT12) +#define N_PCH_PCIE_CCFG_UNRD 12 +#define B_PCH_PCIE_CCFG_UNRS (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_CCFG_UNRS 4 +#define V_PCH_PCIE_CCFG_UNRS_128B 0 +#define V_PCH_PCIE_CCFG_UNRS_256B 1 +#define B_PCH_PCIE_CCFG_UPRS (BIT2 | BIT1 | BIT0) +#define N_PCH_PCIE_CCFG_UPRS 0 +#define V_PCH_PCIE_CCFG_UPRS_128B 0 +#define V_PCH_PCIE_CCFG_UPRS_256B 1 + +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_MPC2_LSTP BIT6 +#define B_PCH_PCIE_MPC2_IEIME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2) +#define B_PCH_PCIE_MPC2_EOIFD BIT1 + +#define R_PCH_PCIE_MPC 0xD8 +#define S_PCH_PCIE_MPC 4 +#define B_PCH_PCIE_MPC_PMCE BIT31 +#define B_PCH_PCIE_MPC_HPCE BIT30 +#define B_PCH_PCIE_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_MPC_P8XDE BIT26 +#define B_PCH_PCIE_MPC_IRRCE BIT25 +#define B_PCH_PCIE_MPC_SRL BIT23 +#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18) +#define N_PCH_PCIE_MPC_UCEL 18 +#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15) +#define N_PCH_PCIE_MPC_CCEL 15 +#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13) +#define N_PCH_PCIE_MPC_PCIESD 13 +#define V_PCH_PCIE_MPC_PCIESD_GEN1 1 +#define V_PCH_PCIE_MPC_PCIESD_GEN2 2 +#define B_PCH_PCIE_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_MPC_HPME BIT1 +#define N_PCH_PCIE_MPC_HPME 1 +#define B_PCH_PCIE_MPC_PMME BIT0 + +#define R_PCH_PCIE_SMSCS 0xDC +#define S_PCH_PCIE_SMSCS 4 +#define N_PCH_PCIE_SMSCS_LERSMIS 5 +#define N_PCH_PCIE_SMSCS_HPLAS 4 +#define N_PCH_PCIE_SMSCS_HPPDM 1 + +#define R_PCH_PCIE_RPDCGEN 0xE1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 + +#define R_PCH_PCIE_RPPGEN 0xE2 +#define B_PCH_PCIE_RPPGEN_PTOTOP BIT6 +#define B_PCH_PCIE_RPPGEN_SEOSCGE BIT4 + +#define R_PCH_PCIE_PWRCTL 0xE8 +#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20 +#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17 +#define B_PCH_PCIE_PWRCTL_DBUPI BIT15 +#define B_PCH_PCIE_PWRCTL_TXSWING BIT13 +#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1 +#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0 + +#define R_PCH_PCIE_DC 0xEC +#define B_PCH_PCIE_DC_PCIBEM BIT2 + +#define R_PCH_PCIE_PHYCTL2 0xF5 +#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6) +#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) +#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4 +#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1 +#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0 + +#define R_PCH_PCIE_IOSFSBCS 0xF7 +#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6 +#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2) + +#define R_PCH_PCIE_STRPFUSECFG 0xFC +#define B_PCH_PCIE_STRPFUSECFG_SERM BIT29 +#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 |= BIT24) +#define N_PCH_PCIE_STRPFUSECFG_PXIP 24 +#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2 +#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3 +#define N_PCH_PCIE_STRPFUSECFG_RPC 14 +#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9 +#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8 +#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7 +#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6 +#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5 +#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4 +#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3 +#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_CFG_ROOTERRSTS 0x130 +#define S_PCH_PCIE_CFG_ROOTERRSTS 4 +#define B_PCH_PCIE_CFG_ROOTERRSTS_AEMN 0xF8000000 +#define B_PCH_PCIE_CFG_ROOTERRSTS_FEMR BIT6 +#define B_PCH_PCIE_CFG_ROOTERRSTS_NFEMR BIT5 +#define B_PCH_PCIE_CFG_ROOTERRSTS_FUF BIT4 +#define B_PCH_PCIE_CFG_ROOTERRSTS_MEFR BIT3 +#define B_PCH_PCIE_CFG_ROOTERRSTS_EFR BIT2 +#define B_PCH_PCIE_CFG_ROOTERRSTS_MCER BIT1 +#define B_PCH_PCIE_CFG_ROOTERRSTS_CER BIT0 + +#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Erro= r Reporting Capability Header +#define V_PCH_PCIE_EX_AEC_CV 0x1 +#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_= PCIE_EX_UEM_OFFSET) +#define R_PCH_PCIE_EX_REC 0x12C ///< Root Error Co= mmand +#define B_PCH_PCIE_EX_REC_FERE BIT2 ///< Root Error Co= mmand Fatal Error Reporting Enable +#define B_PCH_PCIE_EX_REC_NERE BIT1 ///< Root Error Co= mmand Non-fatal Error Reporting Enable +#define B_PCH_PCIE_EX_REC_CERE BIT0 ///< Root Error Co= mmand Correctable Error Reporting Enable + +#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable E= rror Status +#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Stat= us +#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status +#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Erro= r Status + + +//CES.RE, CES.BT, CES.BD + +#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended = Capability Header +#define V_PCH_PCIE_EX_ACS_CV 0x1 +#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + = R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States= Extended Capability Header +#define V_PCH_PCIE_EX_L1S_CV 0x1 +#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCAP_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCTL1_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + = R_PCIE_EX_L1SCTL2_OFFSET) + +#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI= Express Extended Capability Header +#define V_PCH_PCIE_EX_SPEECH_CV 0x1 + +#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_LES_OFFSET) +#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EX_LECTL_UPTPH 12 +#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00 +#define N_PCH_PCIE_EX_LECTL_UPTP 8 +#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_EX_LECTL_DPTPH 4 +#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F +#define N_PCH_PCIE_EX_LECTL_DPTP 0 + +#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L01EC_OFFSET) +#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + = R_PCIE_EX_L23EC_OFFSET) + +#define R_PCH_PCIE_PCIERTP1 0x300 +#define R_PCH_PCIE_PCIERTP2 0x304 +#define R_PCH_PCIE_PCIENFTS 0x314 +#define R_PCH_PCIE_PCIEL0SC 0x318 + +#define R_PCH_PCIE_PCIECFG2 0x320 +#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30 +#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27 +#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24 +#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23 +#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22 +#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20) +#define V_PCH_PCIE_PCIECFG2_PMET 1 +#define N_PCH_PCIE_PCIECFG2_PMET 20 + +#define R_PCH_PCIE_PCIEDBG 0x324 +#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26) +#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) +#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14 +#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7 +#define B_PCH_PCIE_PCIEDBG_SPCE BIT5 +#define B_PCH_PCIE_PCIEDBG_LR BIT4 +#define B_PCH_PCIE_DMIL1EDM BIT3 + +#define R_PCH_PCIE_PCIESTS1 0x328 +#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F + + +#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 |= BIT19) +#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7 + +#define R_PCH_PCIE_PCIESTS2 0x32C +#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31 +#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30 +#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29 +#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28 +#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000 +#define N_PCH_PCIE_PCIESTS2_CLRE 12 + +#define R_PCH_PCIE_PCIEALC 0x338 +#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29 +#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28 +#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26 + +#define R_PCH_PCIE_LTROVR 0x400 + +#define R_PCH_PCIE_LTROVR2 0x404 + +#define R_PCH_PCIE_PHYCTL4 0x408 +#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27 + + +#define R_PCH_PCIE_PCIEPMECTL 0x420 +#define B_PCH_PCIE_PCIEPMECTL_FDPPGE BIT31 +#define B_PCH_PCIE_PCIEPMECTL_DLSULPPGE BIT30 +#define B_PCH_PCIE_PCIEPMECTL_DLSULDLSD BIT29 +#define B_PCH_PCIE_PCIEPMECTL_L1LE BIT17 +#define B_PCH_PCIE_PCIEPMECTL_L1LTRTLV (BIT13 | BIT12 | BIT11 |= BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_PCIEPMECTL_L1LTRTLV 4 +#define V_PCH_PCIE_PCIEPMECTL_L1LTRTLV 0x32 +#define B_PCH_PCIE_PCIEPMECTL_L1FSOE BIT0 + +#define R_PCH_PCIE_PCIEPMECTL2 0x424 +#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11 +#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8 +#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7 +#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6 +#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5 +#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4 + +#define R_PCH_PCIE_PCE 0x428 +#define B_PCH_PCIE_PCE_HAE BIT5 +#define B_PCH_PCIE_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_EQCFG1 0x450 +#define S_PCH_PCIE_EQCFG1 4 +#define B_PCH_PCIE_EQCFG1_REC 0xFF000000 +#define N_PCH_PCIE_EQCFG1_REC 24 +#define B_PCH_PCIE_EQCFG1_REIFECE BIT23 +#define N_PCH_PCIE_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_EQCFG1_LEP23B BIT18 +#define B_PCH_PCIE_EQCFG1_LEP3B BIT17 +#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13 +#define B_PCH_PCIE_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_RTPCL1 0x454 +#define B_PCH_PCIE_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_RTPCL2 0x458 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_RTPCL3 0x45C +#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_RTPCL4 0x460 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_FOMS 0x464 +#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29) +#define N_PCH_PCIE_FOMS_I 29 +#define B_PCH_PCIE_FOMS_LN 0x1F000000 +#define N_PCH_PCIE_FOMS_LN 24 +#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF +#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF +#define N_PCH_PCIE_FOMS_FOMSV0 0 +#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00 +#define N_PCH_PCIE_FOMS_FOMSV1 8 +#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000 +#define N_PCH_PCIE_FOMS_FOMSV2 16 + +#define R_PCH_PCIE_HAEQ 0x468 +#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 |= BIT28) +#define N_PCH_PCIE_HAEQ_HAPCCPI 28 +#define B_PCH_PCIE_HAEQ_MACFOMC BIT19 + +#define R_PCH_PCIE_LTCO1 0x470 +#define B_PCH_PCIE_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000 +#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18 +#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000 +#define N_PCH_PCIE_LTCO1_L1TPRECO 12 +#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0 +#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6 +#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F +#define N_PCH_PCIE_LTCO1_L0TPRECO 0 + +#define R_PCH_PCIE_LTCO2 0x474 +#define B_PCH_PCIE_LTCO2_L3TCOE BIT25 +#define B_PCH_PCIE_LTCO2_L2TCOE BIT24 +#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F + +#define R_PCH_PCIE_G3L0SCTL 0x478 +#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_EQCFG2 0x47C +#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20) +#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 |= BIT16) +#define N_PCH_PCIE_EQCFG2_PCET 16 +#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 |= BIT12) +#define N_PCH_PCIE_EQCFG2_HAPCSB 12 +#define B_PCH_PCIE_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_EQCFG2_REWMET 0xFF + +#define R_PCH_PCIE_MM 0x480 +#define B_PCH_PCIE_MM_MSST 0xFFFFFF00 +#define N_PCH_PCIE_MM_MSST 8 +#define B_PCH_PCIE_MM_MSS 0xFF + +// +//PCI Express Extended End Point Capability Registers +// + +#define R_PCH_PCIE_LTRECH_OFFSET 0 +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 + +// +// Pcie Uplink ports related registers and defines +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_UX16 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_UX16 0 +#define PCI_DEVICE_NUMBER_PCH_PCIE_UX8 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_UX8 0 +#define V_PCH_LBG_PCIE_DEVICE_ID_UX16 0x37C0 ///< PCI Express= Uplink x16 Device ID +#define V_PCH_LBG_NS_PCIE_DEVICE_ID_UX8 0x37C1 ///< PCI Express= Uplink x8 Device ID, LBG-NS + + + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE) +// +#define R_PCH_PCR_SPX_PCD 0 = ///< Port configuration and disable +#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) = ///< Port 1 Function Number +#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 = ///< Port 1 config hide +#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) = ///< Port 2 Function Number +#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 = ///< Port 2 config hide +#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) = ///< Port 3 Function Number +#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 = ///< Port 3 config hide +#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) = ///< Port 4 Function Number +#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 = ///< Port 4 config hide +#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 = ///< 4 bits for each RP FN +#define B_PCH_PCR_SPX_PCD_P1D BIT16 = ///< Port 1 disable +#define B_PCH_PCR_SPX_PCD_P2D BIT17 = ///< Port 2 disable +#define B_PCH_PCR_SPX_PCD_P3D BIT18 = ///< Port 3 disable +#define B_PCH_PCR_SPX_PCD_P4D BIT19 = ///< Port 4 disable +#define B_PCH_PCR_SPX_PCD_SRL BIT31 = ///< Secured Register Lock + +#define R_PCH_PCR_SPX_PCIEHBP 0x0004 = ///< PCI Express high-speed bypass +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 = ///< PCIe HBP mode enable +#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) = ///< PCIe gen mode override +#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 = ///< PCIe transmitter-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 = ///< PCIe receiver-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 = ///< PCIe link recovery override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 = ///< PCIe link down override +#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 = ///< PCIe SKP suppression mode +#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 = ///< PCIe suppress SKP transmission +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) = ///< PCIe HBP port select +#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) = ///< CRC select +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 = ///< PCIe HBP CRC + + +// +// ICC PCR (PID: ICC) +// +#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 = ///< Timing Control SRC Clock Register +#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 = ///< Timing Control SRC Clock Register 2 + + +#define R_PCH_VSPX_ERRCORSTS 0x0110 = //< Correctable Error Status Register +#define B_PCH_VSPX_ERRCORSTS_ANFE BIT13 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsPcr.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsPcr.h new file mode 100644 index 0000000000..ad0d54342f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsPcr.h @@ -0,0 +1,177 @@ +/** @file + Register names for PCH private chipset register + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/// +/// Definition for PCR base address (defined in PchReservedResources.h) +/// +//#define PCH_PCR_BASE_ADDRESS 0xFD000000 +//#define PCH_PCR_MMIO_SIZE 0x01000000 +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_= ADDRESS | ((UINT8) (Pid) << 16) | (UINT16) (Offset)) +#define PCH_PCR_ADDRESS_BASE(PcrBaseAddress, Pid, Offset) ((UINTN) (PcrB= aseAddress) | ((UINT8) (Pid) << 16) | (UINT16) (Offset)) + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well. +**/ + +#define PID_BROADCAST1 0xFF +#define PID_BROADCAST2 0xFE +//Rsv =3D 0xFD-0xF0, +#define PID_DMI 0xEF +#define PID_ESPISPI 0xEE +#define PID_ICLK 0xED +#define PID_MODPHY4 0xEB +#define PID_MODPHY5 0x10 +#define PID_MODPHY1 0xE9 +#define PID_PMC 0xE8 +//Rsv =3D 0xE7, +#define PID_XHCI 0xE6 +#define PID_OTG 0xE5 +#define PID_SPE 0xE4 // Reserved in = SKL PCH LP +#define PID_SPD 0xE3 // Reserved in = SKL PCH LP +#define PID_SPC 0xE2 +#define PID_SPB 0xE1 +#define PID_SPA 0xE0 +#define PID_UPSX8 0x06 +#define PID_UPSX16 0x07 +#define PID_TAP2IOSFSB1 0xDF +#define PID_TRSB 0xDD +#define PID_ICC 0xDC +#define PID_GBE 0xDB +//Rsv =3D 0xDA, +#define PID_SATA 0xD9 +#define PID_SSATA 0x0F +#define PID_LDO 0x14 +//Rsv =3D 0xD8, +#define PID_DSP 0xD7 +//Rsv =3D 0xD6, +#define PID_FUSE 0xD5 +#define PID_FSPROX0 0xD4 +#define PID_DRNG 0xD2 +//Rsv =3D 0xD1, +#define PID_FIA 0xCF +#define PID_FIAWM26 0x13 +//Rsv =3D 0xCE-0xCC, +#define PID_USB2 0xCA +//Rsv =3D 0xC8 +#define PID_LPC 0xC7 +#define PID_SMB 0xC6 +#define PID_P2S 0xC5 +#define PID_ITSS 0xC4 +#define PID_RTC_HOST 0xC3 +//Rsv =3D 0xC2-0xC1, +#define PID_PSF5 0x8F +#define PID_PSF6 0x70 +#define PID_PSF7 0x01 +#define PID_PSF8 0x29 +#define PID_PSF9 0x21 +#define PID_PSF10 0x36 +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_HOTHARM 0xB9 +#define PID_DCI 0xB8 +#define PID_DFXAGG 0xB7 +#define PID_NPK 0xB6 +//Rsv =3D 0xB5-0xB1, +#define PID_MMP0 0xB0 +#define PID_GPIOCOM0 0xAF +#define PID_GPIOCOM1 0xAE +#define PID_GPIOCOM2 0xAD +#define PID_GPIOCOM3 0xAC +#define PID_GPIOCOM4 0xAB +#define PID_GPIOCOM5 0x11 +#define PID_MODPHY2 0xA9 +#define PID_MODPHY3 0xA8 +//Rsv =3D 0xA7-0xA6, +#define PID_PNCRC 0xA5 +#define PID_PNCRB 0xA4 +#define PID_PNCRA 0xA3 +#define PID_PNCR0 0xA2 +#define PID_CSME15 0x9F // SMS2 +#define PID_CSME14 0x9E // SMS1 +#define PID_CSME13 0x9D // PMT +#define PID_CSME12 0x9C // PTIO +#define PID_CSME11 0x9B // PECI +#define PID_CSME9 0x99 // SMT6 +#define PID_CSME8 0x98 // SMT5 +#define PID_CSME7 0x97 // SMT4 +#define PID_CSME6 0x96 // SMT3 +#define PID_CSME5 0x95 // SMT2 +#define PID_CSME4 0x94 // SMT1 (SMBus Messag= e Transport 1) +#define PID_CSME3 0x93 // FSC +#define PID_CSME2 0x92 // USB-R SAI +#define PID_CSME0 0x90 // CSE +#define PID_CSME_PSF 0x8F // ME PSF +//Rsv =3D 0x88-0x30, +//#define PID_EVA 0x2F-0x00 +#define PID_CSMERTC 0x8E +#define PID_IEUART 0x80 +#define PID_IEHOTHAM 0x7F +#define PID_IEPMT 0x7E +#define PID_IESSTPECI 0x7D +#define PID_IEFSC 0x7C +#define PID_IESMT5 0x7B +#define PID_IESMT4 0x7A +#define PID_IESMT3 0x79 +#define PID_IESMT2 0x78 +#define PID_IESMT1 0x77 +#define PID_IESMT0 0x76 +#define PID_IEUSBR 0x74 +#define PID_IEPTIO 0x73 +#define PID_IEIOSFGASKET 0x72 +#define PID_IEPSF 0x70 +#define PID_FPK 0x0A +#define PID_MP0KR 0x3C +#define PID_MP1KR 0x3E +#define PID_RUAUX 0x0B +#define PID_RUMAIN 0x3B +#define PID_EC 0x20 +#define PID_CPM2 0x38 +#define PID_CPM1 0x37 +#define PID_CPM0 0x0C +#define PID_VSPTHERM 0x25 +#define PID_VSPP2SB 0x24 +#define PID_VSPFPK 0x22 +#define PID_VSPCPM2 0x35 +#define PID_VSPCPM1 0x34 +#define PID_VSPCPM0 0x33 +#define PID_MSMROM 0x08 +#define PID_PSTH 0x89 + +typedef UINT8 PCH_SBI_PID; + + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsPmc.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsPmc.h new file mode 100644 index 0000000000..83a18f92c5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsPmc.h @@ -0,0 +1,731 @@ +/** @file + Register names for PCH PMC device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +//PMC Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_PMC 31 +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 + +#define V_PCH_PMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_PMC_DEVICE_ID 0x9D21 +// +// LBG Production (PRQ) PMC Device ID +// +#define V_PCH_LBG_PROD_PMC_DEVICE_ID 0xA1A1 +// +// LBG Super SKU (SSX) PMC Device ID +// +#define V_PCH_LBG_PMC_DEVICE_ID 0xA221 + +#define R_PCH_PMC_BM_CX_CNF 0xA8 +#define V_PCH_LP_PMC_DEVICE_ID 0x9D21 +#define R_PCH_PMC_PM_DATA_BAR 0x10 +#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000 +#define R_PCH_PMC_ACPI_BASE 0x40 +#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC +#define R_PCH_PMC_ACPI_CNT 0x44 +#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 = ///< PWRM enable +#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 = ///< ACPI eanble +#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) = ///< SCI IRQ select +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7 +#define R_PCH_PMC_PWRM_BASE 0x48 +#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 = ///< PWRM must be 64KB alignment to align the source decode. +#define R_PCH_PMC_GEN_PMCON_A 0xA0 +#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30 +#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29 +#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28 +#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27 +#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23 +#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21 +#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18 +#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_PLL_SD_INC0 BIT13 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12 +#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10 +#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5 +#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4 +#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 = ///< ESPI SMI lock +#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003 +#define R_PCH_PMC_GEN_PMCON_B 0xA4 +#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 = ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 = ///< Lock ACPI BASE at 0x40, only cleared by reset when set +#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16 +#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15 +#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 +#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13 +#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00 +#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9 +#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3 +#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 +#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1 +#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0 +#define R_PCH_PMC_BM_CX_CNF 0xA8 +#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31 +#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30 +#define B_PCH_PMC_BM_CX_CNF_EHCI_BREAK_EN BIT26 +#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24 +#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19 +#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17 +#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16 +#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15 +#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 +#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11 +#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10 +#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9 +#define R_PCH_PMC_ETR3 0xAC +#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h= Lockdown +#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21 +#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h= Global Reset +#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19 +#define B_PCH_PMC_ETR3_CWORWRE BIT18 +#define R_PCH_PMC_PMC_THROT_1 0xB0 +#define B_PCH_PMC_PMC_PMC_THROT_LOCK BIT15 +#define B_PCH_PMC_PMC_THROT_1_VRALERT_EN BIT0 +#define R_PCH_PMC_MDAP 0xC0 +#define B_PCH_PMC_MDAP_MDAP_POLICY_EN BIT31 +#define B_PCH_PMC_MDAP_PDMA_EN BIT30 +#define B_PCH_PMC_MDAP_AUTO_POLICY_CTL BIT29 +#define V_PCH_PMC_MDAP_MDAP_VALUE 0x1FFFF +#define R_PCH_PMC_MANID 0xF8 + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_ACPI_IO_PM1_STS 0x00 +#define S_ACPI_IO_PM1_STS 2 +#define B_ACPI_IO_PM1_STS_WAK 0x8000 +#define B_ACPI_IO_PM1_STS_PRBTNOR 0x0800 +#define B_ACPI_IO_PM1_STS_RTC 0x0400 +#define B_ACPI_IO_PM1_STS_PWRBTN 0x0100 +#define B_ACPI_IO_PM1_STS_GBL 0x0020 +#define B_ACPI_IO_PM1_STS_BM 0x0010 +#define B_ACPI_IO_PM1_STS_TMROF 0x0001 +#define N_ACPI_IO_PM1_STS_WAK 15 +#define N_ACPI_IO_PM1_STS_PRBTNOR 11 +#define N_ACPI_IO_PM1_STS_RTC 10 +#define N_ACPI_IO_PM1_STS_PWRBTN 8 +#define N_ACPI_IO_PM1_STS_GBL 5 +#define N_ACPI_IO_PM1_STS_BM 4 +#define N_ACPI_IO_PM1_STS_TMROF 0 + +#define R_ACPI_IO_PM1_EN 0x02 +#define S_ACPI_IO_PM1_EN 2 +#define B_ACPI_IO_PM1_EN_PCIEXP_WAKE_DIS 0x4000 +#define B_ACPI_IO_PM1_EN_RTC 0x0400 +#define B_ACPI_IO_PM1_EN_PWRBTN 0x0100 +#define B_ACPI_IO_PM1_EN_GBL 0x0020 +#define B_ACPI_IO_PM1_EN_TMROF 0x0001 +#define N_ACPI_IO_PM1_EN_RTC 10 +#define N_ACPI_IO_PM1_EN_PWRBTN 8 +#define N_ACPI_IO_PM1_EN_GBL 5 +#define N_ACPI_IO_PM1_EN_TMROF 0 + +#define R_ACPI_IO_PM1_CNT 0x04 +#define S_ACPI_IO_PM1_CNT 4 +#define B_ACPI_IO_PM1_CNT_SLP_EN 0x00002000 +#define B_ACPI_IO_PM1_CNT_SLP_TYP 0x00001C00 +#define V_ACPI_IO_PM1_CNT_S0 0x00000000 +#define V_ACPI_IO_PM1_CNT_S1 0x00000400 +#define V_ACPI_IO_PM1_CNT_S3 0x00001400 +#define V_ACPI_IO_PM1_CNT_S4 0x00001800 +#define V_ACPI_IO_PM1_CNT_S5 0x00001C00 +#define B_ACPI_IO_PM1_CNT_GBL_RLS 0x00000004 +#define B_ACPI_IO_PM1_CNT_BM_RLD 0x00000002 +#define B_ACPI_IO_PM1_CNT_SCI_EN 0x00000001 + +#define R_ACPI_IO_PM1_TMR 0x08 +#define V_ACPI_IO_TMR_FREQUENCY 3579545 +#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The = timer is 24 bit overflow + +#define R_ACPI_IO_SMI_EN 0x30 +#define S_ACPI_IO_SMI_EN 4 +#define B_ACPI_IO_SMI_EN_LEGACY_USB3 BIT31 +#define B_ACPI_IO_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_ACPI_IO_SMI_EN_IE_SMI BIT23 +#define B_ACPI_IO_SMI_EN_INTEL_USB2 BIT18 +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17 +#define B_ACPI_IO_SMI_EN_PERIODIC BIT14 +#define B_ACPI_IO_SMI_EN_TCO BIT13 +#define B_ACPI_IO_SMI_EN_MCSMI BIT11 +#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7 +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6 +#define B_ACPI_IO_SMI_EN_APMC BIT5 +#define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4 +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3 +#define B_ACPI_IO_SMI_EN_BIOS BIT2 +#define B_ACPI_IO_SMI_EN_EOS BIT1 +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0 +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_EN_ESPI 28 +#define N_ACPI_IO_SMI_EN_GPIO_UNLOCK 27 +#define N_ACPI_IO_SMI_EN_INTEL_USB2 18 +#define N_ACPI_IO_SMI_EN_LEGACY_USB2 17 +#define N_ACPI_IO_SMI_EN_PERIODIC 14 +#define N_ACPI_IO_SMI_EN_TCO 13 +#define N_ACPI_IO_SMI_EN_MCSMI 11 +#define N_ACPI_IO_SMI_EN_BIOS_RLS 7 +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_EN_APMC 5 +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3 +#define N_ACPI_IO_SMI_EN_BIOS 2 +#define N_ACPI_IO_SMI_EN_EOS 1 +#define N_ACPI_IO_SMI_EN_GBL_SMI 0 + +#define R_ACPI_IO_SMI_STS 0x34 +#define S_ACPI_IO_SMI_STS 4 +#define B_ACPI_IO_SMI_STS_LEGACY_USB3 BIT31 +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27 +#define B_ACPI_IO_SMI_STS_SPI BIT26 +#define B_ACPI_IO_SMI_STS_IE_SMI BIT23 +#define B_ACPI_IO_SMI_STS_MONITOR BIT21 +#define B_ACPI_IO_SMI_STS_PCI_EXP BIT20 +#define B_ACPI_IO_SMI_STS_PATCH BIT19 +#define B_ACPI_IO_SMI_STS_INTEL_USB2 BIT18 +#define B_ACPI_IO_SMI_STS_LEGACY_USB2 BIT17 +#define B_ACPI_IO_SMI_STS_SMBUS BIT16 +#define B_ACPI_IO_SMI_STS_SERIRQ BIT15 +#define B_ACPI_IO_SMI_STS_PERIODIC BIT14 +#define B_ACPI_IO_SMI_STS_TCO BIT13 +#define B_ACPI_IO_SMI_STS_DEVMON BIT12 +#define B_ACPI_IO_SMI_STS_MCSMI BIT11 +#define B_ACPI_IO_SMI_STS_GPIO_SMI BIT10 +#define B_ACPI_IO_SMI_STS_GPE1 BIT10 +#define B_ACPI_IO_SMI_STS_GPE0 BIT9 +#define B_ACPI_IO_SMI_STS_PM1_STS_REG BIT8 +#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6 +#define B_ACPI_IO_SMI_STS_APM BIT5 +#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4 +#define B_ACPI_IO_SMI_STS_LEGACY_USB BIT3 +#define B_ACPI_IO_SMI_STS_BIOS BIT2 +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_STS_ESPI 28 +#define N_ACPI_IO_SMI_STS_GPIO_UNLOCK 27 +#define N_ACPI_IO_SMI_STS_SPI 26 +#define N_ACPI_IO_SMI_STS_MONITOR 21 +#define N_ACPI_IO_SMI_STS_PCI_EXP 20 +#define N_ACPI_IO_SMI_STS_PATCH 19 +#define N_ACPI_IO_SMI_STS_INTEL_USB2 18 +#define N_ACPI_IO_SMI_STS_LEGACY_USB2 17 +#define N_ACPI_IO_SMI_STS_SMBUS 16 +#define N_ACPI_IO_SMI_STS_SERIRQ 15 +#define N_ACPI_IO_SMI_STS_PERIODIC 14 +#define N_ACPI_IO_SMI_STS_TCO 13 +#define N_ACPI_IO_SMI_STS_DEVMON 12 +#define N_ACPI_IO_SMI_STS_MCSMI 11 +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10 +#define N_ACPI_IO_SMI_STS_GPE0 9 +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8 +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_STS_APM 5 +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3 +#define N_ACPI_IO_SMI_STS_BIOS 2 + +#define R_ACPI_IO_GPE_CNTL 0x40 +#define B_ACPI_IO_GPE_CNTL_SWGPE_CTRL BIT17 + +#define R_ACPI_IO_DEVACT_STS 0x44 +#define S_ACPI_IO_DEVACT_STS 2 +#define B_ACPI_IO_DEVACT_STS_MASK 0x13E1 +#define B_ACPI_IO_DEVACT_STS_KBC 0x1000 +#define B_ACPI_IO_DEVACT_STS_PIRQDH 0x0200 +#define B_ACPI_IO_DEVACT_STS_PIRQCG 0x0100 +#define B_ACPI_IO_DEVACT_STS_PIRQBF 0x0080 +#define B_ACPI_IO_DEVACT_STS_PIRQAE 0x0040 +#define B_ACPI_IO_DEVACT_STS_D0_TRP 0x0001 +#define N_ACPI_IO_DEVACT_STS_KBC 12 +#define N_ACPI_IO_DEVACT_STS_PIRQDH 9 +#define N_ACPI_IO_DEVACT_STS_PIRQCG 8 +#define N_ACPI_IO_DEVACT_STS_PIRQBF 7 +#define N_ACPI_IO_DEVACT_STS_PIRQAE 6 + +#define R_ACPI_IO_PM2_CNT 0x50 +#define B_ACPI_IO_PM2_CNT_ARB_DIS 0x01 + +#define R_ACPI_IO_OC_WDT_CTL 0x54 +#define B_ACPI_IO_OC_WDT_CTL_RLD BIT31 +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_ACPI_IO_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_ACPI_IO_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_ACPI_IO_OC_WDT_CTL_EN BIT14 +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV BIT13 +#define B_ACPI_IO_OC_WDT_CTL_LCK BIT12 +#define B_ACPI_IO_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_ACPI_IO_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_ACPI_IO_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_ACPI_IO_OC_WDT_CTL_STATUS_OK 0 + +#define R_ACPI_IO_GPE0_STS_127_96 0x8C +#define S_ACPI_IO_GPE0_STS_127_96 4 +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18 +#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17 +#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16 +#define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15 +#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13 +#define B_ACPI_IO_GPE0_STS_127_96_ME_SCI BIT12 +#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11 +#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10 +#define B_ACPI_IO_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 +#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_ACPI_IO_GPE0_STS_127_96_TC0SCI BIT6 +#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 +#define B_ACPI_IO_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 15 +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_STS_127_96_PME 11 +#define N_ACPI_IO_GPE0_STS_127_96_BATLOW 10 +#define N_ACPI_IO_GPE0_STS_127_96_PCI_EXP 9 +#define N_ACPI_IO_GPE0_STS_127_96_RI 8 +#define N_ACPI_IO_GPE0_STS_127_96_SMB_WAK 7 +#define N_ACPI_IO_GPE0_STS_127_96_TC0SCI 6 +#define N_ACPI_IO_GPE0_STS_127_96_SWGPE 2 +#define N_ACPI_IO_GPE0_STS_127_96_HOT_PLUG 1 + + +#define R_ACPI_IO_GPE0_EN_31_0 0x90 +#define R_ACPI_IO_GPE0_EN_63_31 0x94 +#define R_ACPI_IO_GPE0_EN_94_64 0x98 +#define R_ACPI_IO_GPE0_EN_127_96 0x9C +#define S_ACPI_IO_GPE0_EN_127_96 4 +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18 +#define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17 +#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16 +#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13 +#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12 +#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11 +#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10 +#define B_ACPI_IO_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 +#define B_ACPI_IO_GPE0_EN_127_96_TC0SCI BIT6 +#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 +#define B_ACPI_IO_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_EN_127_96_USB3 12 +#define N_ACPI_IO_GPE0_EN_127_96_PME 11 +#define N_ACPI_IO_GPE0_EN_127_96_BATLOW 10 +#define N_ACPI_IO_GPE0_EN_127_96_PCI_EXP 9 +#define N_ACPI_IO_GPE0_EN_127_96_RI 8 +#define N_ACPI_IO_GPE0_EN_127_96_TC0SCI 6 +#define N_ACPI_IO_GPE0_EN_127_96_SWGPE 2 +#define N_ACPI_IO_GPE0_EN_127_96_HOT_PLUG 1 + + +// +// TCO register I/O map +// +#define R_TCO_IO_RLD 0x0 +#define R_TCO_IO_DAT_IN 0x2 +#define R_TCO_IO_DAT_OUT 0x3 +#define R_TCO_IO_TCO1_STS 0x04 +#define S_TCO_IO_TCO1_STS 2 +#define B_TCO_IO_TCO1_STS_DMISERR BIT12 +#define B_TCO_IO_TCO1_STS_DMISMI BIT10 +#define B_TCO_IO_TCO1_STS_DMISCI BIT9 +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8 +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7 +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3 +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2 +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1 +#define B_TCO_IO_TCO1_STS_NMI2SMI BIT0 +#define N_TCO_IO_TCO1_STS_DMISMI 10 +#define N_TCO_IO_TCO1_STS_BIOSWR 8 +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7 +#define N_TCO_IO_TCO1_STS_TIMEOUT 3 +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1 +#define N_TCO_IO_TCO1_STS_NMI2SMI 0 + +#define R_TCO_IO_TCO2_STS 0x06 +#define S_TCO_IO_TCO2_STS 2 +#define B_TCO_IO_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_TCO_IO_TCO2_STS_BAD_BIOS BIT3 +#define B_TCO_IO_TCO2_STS_BOOT BIT2 +#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1 +#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0 +#define N_TCO_IO_TCO2_STS_INTRD_DET 0 + +#define R_TCO_IO_TCO1_CNT 0x08 +#define S_TCO_IO_TCO1_CNT 2 +#define B_TCO_IO_TCO1_CNT_LOCK BIT12 +#define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11 +#define B_TCO_IO_TCO1_CNT_NMI2SMI_EN BIT9 +#define B_TCO_IO_TCO1_CNT_NMI_NOW BIT8 +#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9 + +#define R_TCO_IO_TCO2_CNT 0x0A +#define S_TCO_IO_TCO2_CNT 2 +#define B_TCO_IO_TCO2_CNT_OS_POLICY 0x0030 +#define B_TCO_IO_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_TCO_IO_TCO2_CNT_INTRD_SEL 0x0006 +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2 + +#define R_TCO_IO_MESSAGE1 0x0C +#define R_TCO_IO_MESSAGE2 0x0D +#define R_TCO_IO_TWDS 0x0E ///< T= CO_WDSTATUS register. +#define R_TCO_IO_LE 0x10 ///< L= EGACY_ELIM register +#define B_TCO_IO_LE_IRQ12_CAUSE BIT1 +#define B_TCO_IO_LE_IRQ1_CAUSE BIT0 +#define R_TCO_IO_TMR 0x12 + +// +// PWRM Registers +// +#define R_PCH_WADT_AC 0x0 = ///< Wake Alarm Device Timer: AC +#define R_PCH_WADT_DC 0x4 = ///< Wake Alarm Device Timer: DC +#define R_PCH_WADT_EXP_AC 0x8 = ///< Wake Alarm Device Expired Timer: AC +#define R_PCH_WADT_EXP_DC 0xC = ///< Wake Alarm Device Expired Timer: DC +#define R_PCH_PWRM_PRSTS 0x10 = ///< Power and Reset Status +#define B_PCH_PWRM_PRSTS_PM_WD_TMR BIT15 = ///< Power Management Watchdog Timer +#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 = ///< VE Watchdog Timer Status +#define B_PCH_PWRM_PRSTS_ME_WD_TMR_STS BIT6 = ///< Management Engine Watchdog Timer Status +#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4 +#define B_PCH_PWRM_PRSTS_ME_HOST_PWRDN BIT3 +#define B_PCH_PWRM_PRSTS_ME_HRST_WARM_STS BIT2 +#define B_PCH_PWRM_PRSTS_ME_HRST_COLD_STS BIT1 +#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0 +#define R_PCH_PWRM_14 0x14 +#define R_PCH_PWRM_CFG 0x18 = ///< Power Management Configuration +#define V_PCH_PWRM_CFG_TIMING_T581_10MS (BIT0 | BIT1) = ///< Timing t581 - 10ms +#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 = ///< Allow 24MHz Crystal Oscillator Shutdown +#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 = ///< Allow USB2 Core Power Gating +#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 = ///< RTC Wake from Deep S4/S5 Disable +#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18= ) ///< SLP_SUS# Min Assertion Width +#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18= ) ///< 4 seconds +#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 = ///< 1 second +#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 = ///< 0.5 second (500ms) +#define V_PCH_PWRM_CFG_SSMAW_0S 0 = ///< 0 second +#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16= ) ///< SLP_A# Min Assertion Width +#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16= ) ///< 2 seconds +#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 = ///< 98ms +#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 = ///< 4 seconds +#define V_PCH_PWRM_CFG_SAMAW_0S 0 = ///< 0 second +#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) = ///< Reset Power Cycle Duration +#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) = ///< 1-2 seconds +#define V_PCH_PWRM_CFG_RPCD_2S BIT9 = ///< 2-3 seconds +#define V_PCH_PWRM_CFG_RPCD_3S BIT8 = ///< 3-4 seconds +#define V_PCH_PWRM_CFG_RPCD_4S 0 = ///< 4-5 seconds (Default) +#define R_PCH_PWRM_MTPMC 0x20 = ///< Message to PMC +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE = ///< Command to override lanes 0-15 power gating +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF = ///< Command to override lanes 16-31 power gating +#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 = ///< Data part of PowerGate Message to PMC +#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16 +#define R_PCH_PWRM_PCH_PM_STS 0x1C = ///< PCH Power Management Status +#define B_PCH_PWRM_PCH_PM_STS_ADR_RST_STS BIT16 = ///< ADR Reset Status +#define R_PCH_PWRM_S0_S1_PWRGATE_POL 0x24 = ///< S0/S1 Power Gating Policies +#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 = ///< S3 Power Gating Policies +#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 = ///< Deep S3 Enable in DC Mode +#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 = ///< Deep S3 Enable in AC Mode +#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C = ///< Deep S4 Power Policies +#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 = ///< Deep S4 Enable in DC Mode +#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 = ///< Deep S4 Enable in AC Mode +#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 = ///< Deep S5 Power Policies +#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 = ///< Deep S5 Enable in DC Mode +#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 = ///< Deep S5 Enable in AC Mode +#define R_PCH_PWRM_DSX_CFG 0x34 = ///< Deep SX Configuration +#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 = ///< WAKE# Pin DeepSx Enable +#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 = ///< AC_PRESENT pin pulldown in DeepSx disable +#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 = ///< LAN_WAKE Pin DeepSx Enable +#define R_PCH_PWRM_CFG2 0x3C = ///< Power Management Configuration Reg 2 +#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30= | BIT29) ///< Power Button Override Period (PBOP) +#define N_PCH_PWRM_CFG2_PBOP 29 = ///< Power Button Override Period (PBOP) +#define B_PCH_PWRM_CFG2_PB_DIS BIT28 = ///< Power Button Native Mode Disable (PB_DIS) +#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 = ///< DRAM RESET# control +#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 = ///< Enable Snoop Request to SLOW_RING +#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C = ///< Enable Snoop Request to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_SN_SA 0x50 = ///< Enable Snoop Request to SA +#define R_PCH_PWRM_EN_SN_SA2 0x54 = ///< Enable Snoop Request to SA 2nd Reg +#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 = ///< Enable Snoop Request to SLOW_RING_CF +#define R_PCH_PWRM_EN_NS_SA 0x68 = ///< Enable Non-Snoop Request to SA +#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 = ///< Enable Clock Wake to SLOW_RING +#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 = ///< Enable Clock Wake to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_CW_SA 0x88 = ///< Enable Clock Wake to SA +#define R_PCH_PWRM_EN_CW_SA2 0x8C = ///< Enable Clock Wake to SA 2nd Reg +#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 = ///< Enable Clock Wake to SLOW_RING_CF +#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 = ///< Enable Pegged Active to SLOW_RING +#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC = ///< Enable Pegged Active to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_PA_SA 0xB0 = ///< Enable Pegged Active to SA +#define R_PCH_PWRM_EN_PA_SA2 0xB4 = ///< Enable Pegged Active to SA 2nd Reg +#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 = ///< Enable Misc PM_SYNC Events +#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4 +#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) +#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24 +#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1 +#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8 +#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 = ///< PM_SYNC Configuration Lock +#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11 +#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10 +#define B_PCH_PWRM_PMSYNC_GPIO_B_SEL BIT9 +#define B_PCH_PWRM_PMSYNC_GPIO_A_SEL BIT8 +#define R_PCH_PWRM_PMSYNC_TPR_CONFIG2 0xCC + +#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 +#define B_PCH_PWRM_PM_SYNC_MODE_GPIO_B BIT13 +#define B_PCH_PWRM_PM_SYNC_MODE_GPIO_C BIT14 +#define PM_SYNC_GPIO_B 0 +#define PM_SYNC_GPIO_C 1 +#define B_PCH_PWRM_PM_SYNC_MODE_32_64_WR BIT29 +#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 +#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 = ///< PM_SYNC State Hysteresis +#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 = ///< PM_SYNC Pin Mode +#define R_PCH_PWRM_CFG3 0xE0 = ///< Power Management Configuration Reg 3 +#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 = ///< Deep-Sx WLAN Phy Power Enable +#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 = ///< Host Wireless LAN Phy Power Enable +#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 = ///< Lock power gating override messages +#define B_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF (BIT25 | BIT24) +#define N_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF 24 +#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_1US 0 +#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_2US 1 +#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_5US 2 +#define V_PCH_PWRM_CFG3_GR_PFET_DUR_ON_DEF_20US 3 +#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 = ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION +#define R_PCH_PWRM_CFG4 0xE8 = ///< Power Management Configuration Reg 4 +#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 = ///< USB2 PHY SUS Well Power Gating Enable +#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) = ///< CPU I/O VR Ramp Duration, [8:0] +#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018 +#define R_PCH_PWRM_CPU_EPOC 0xEC +#define R_PCH_PWRM_ADR_EN 0xF0 +#define B_PCH_PWRM_ADR_EN_ADR_FEAT_EN BIT0 +#define B_PCH_PWRM_ADR_EN_CTWDT_ADR_EN BIT9 +#define B_PCH_PWRM_ADR_EN_SYSPWR_ADR_EN BIT12 +#define B_PCH_PWRM_ADR_EN_OCWDT_ADR_EN BIT13 +#define B_PCH_PWRM_ADR_EN_PMC_PARERR_ADR_EN BIT14 +#define B_PCH_PWRM_ADR_EN_HPR_ADR_EN BIT28 +#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_MASK BIT31|BIT30 +#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_GPIO_B BIT30 +#define B_PCH_PWRM_ADR_EN_ADR_GPIO_SEL_GPIO_C BIT31 +#define R_PCH_PWRM_GBL2HOST_EN 0x10C ///< = Global to Host Reset Enable +#define V_PCH_PWRM_GBL2HOST_EN 0x001F2DE4///<= Global to Host Reset Enable default value +#define B_PCH_PWRM_GBL2HOST_EN_G2H_FEAT_EN BIT0 ///< = G2H Feature Enable +#define B_PCH_PWRM_GBL2HOST_EN_LTRESET_G2H_EN BIT1 ///< = LT RESET G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_PMCGBL_G2H_EN BIT2 ///< = PMC FW-Initiated Global Reset G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_CPUTHRM_G2H_EN BIT3 ///< = CPU Thermal Trip G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_PCHTHRM_G2H_EN BIT4 ///< = PCH Internal Thermal Trip G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_PBO_G2H_EN BIT5 ///< = Power Button Override G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_MEPBO_G2H_EN BIT6 ///< = ME-Initiated Power Button Override G2H +#define B_PCH_PWRM_GBL2HOST_EN_MEWDT_G2H_EN BIT7 ///< = ME FW Watchdog Timer G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_MEGBL_G2H_EN BIT8 ///< = ME-Initiated Global Reset G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_CTWDT_G2H_EN BIT9 ///< = CPU Thermal Watchdog Timer G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_PMCWDT_G2H_EN BIT10 ///< = PMC FW Watchdog Timer G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_ME_UERR_G2H_EN BIT11 ///< = ME Uncorrectable Error G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_SYSPWR_G2H_EN BIT12 ///< = SYS_PWROK Failure G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_OCWDT_G2H_EN BIT13 ///< = Over-Clocking WDT G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_PMC_PARERR_G2H_EN BIT14 ///< = PMC Parity Error G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_IEPBO_G2H_EN BIT16 ///< = IE-Initiated Power Button Override G2H +#define B_PCH_PWRM_GBL2HOST_EN_IEWDT_G2H_EN BIT17 ///< = IE FW Watchdog Timer G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_IEGBL_G2H_EN BIT18 ///< = IE-Initiated Global Reset G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_IE_UERR_G2H_EN BIT19 ///< = IE Uncorrectable Error G2H Enable +#define B_PCH_PWRM_GBL2HOST_EN_ACRU_ERR_G2H_EN BIT20 ///< = AC RU Error G2H Enable +#define R_PCH_PWRM_VR_MISC_CTL 0x100 +#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3 +#define R_PCH_PWRM_GPIO_CFG 0x120 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10= | BIT9 | BIT8) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 |= BIT5 | BIT4) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 |= BIT1 | BIT0) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0 +#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 = ///< PM_SYNC Pin Mode in C0 +#define R_PCH_PWRM_GBLRST_CAUSE0 0x124 //Glo= bal reset cause 0 +#define R_PCH_PWRM_GBLRST_CAUSE1 0x128 //Glo= bal reset cause 1 +#define R_PCH_PWRM_HPR_CAUSE0 0x12C ///< = Host partition reset causes +#define B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< = Global reset converted to Host reset +#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200 +#define B_PCH_PWRM_MODPHY_PM_CFG1_MLSXSWPGP 0xFFFF +#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< = ModPHY Power Management Configuration Reg 2 +#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< = ModPHY Lane SUS Power Domain Dynamic Gating Enable +#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< = Enable ModPHY FET Control +#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27= | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time +#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24 +#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A +#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< = UFS ModPHY SPD SPD Override +#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< = ModPHY Power Management Configuration Reg 3 +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< = UFS ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< = xDCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< = xHCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< = GbE ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< = SATA ModPHY SPD RT Request +#define R_PCH_PWRM_30C 0x30C +#define R_PCH_PWRM_OBFF_CFG 0x314 = ///< OBFF Configuration +#define R_PCH_PWRM_31C 0x31C +#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 = ///< CPPM Miscellaneous Configuration +#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 = ///< CPPM Clock Gating Policy Reg 1 +#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 = ///< CPPM Clock Gating Policy Reg 3 +#define R_PCH_PWRM_34C 0x34C +#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 = ///< CPPM Clock Gating Policy Reg 5 +#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 = ///< CPPM Shutdown Qualifier Enable for Clock Source Group X +#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) = ///< LTR Threshold for Clock Source Group X, [8:0] +#define R_PCH_PWRM_3D0 0x3D0 +#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 = ///< CPPM ModPHY Gating Policy Reg 1A +#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 = ///< CPPM Shutdown Qualifier Enable for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 = ///< ASLT/PLT Selection for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) = ///< LTR Threshold for ModPHY, [8:0] +#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 = ///< Clock Source Shutdown Control Reg 1 +#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21= | BIT20) ///< Clock Source 5 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20 +#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 |= BIT0) ///< Clock Source 1 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0 +#define R_PCH_PWRM_CS_SD_CTL2 0x3EC = ///< Clock Source Shutdown Control Reg 2 +#define R_PCH_PWRM_HSWPGCR1 0x5D0 +#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31 +#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0 +#define R_PCH_PWRM_600 0x600 +#define R_PCH_PWRM_604 0x604 +#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Sta= tic PG Related Function Disable Register 1 +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Sta= tic Function Disable Lock (ST_FDIS_LK) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Cam= era Function Disable (PMC Version) (CAM_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH = Function Disable (PMC Version) (ISH_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE= Function Disable (PMC Version) (GBE_FDIS_PMC) +#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Sta= tic Function Disable Control Register 2 +#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Sta= tic Function Disable Control Register 2 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< Ser= ialIo Controller GSPI Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< Ser= ialIo Controller GSPI Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< Ser= ialIo Controller UART Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< Ser= ialIo Controller UART Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< Ser= ialIo Controller UART Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< Ser= ialIo Controller I2C Device 5 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< Ser= ialIo Controller I2C Device 4 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< Ser= ialIo Controller I2C Device 3 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< Ser= ialIo Controller I2C Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< Ser= ialIo Controller I2C Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< Ser= ialIo Controller I2C Device 0 Function Disable +#define R_PCH_PWRM_NST_PG_FDIS_1 0x628 +#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC= Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDC= I Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADS= P Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SAT= A Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_sSATA_FDIS_PMC BIT27 ///< sSA= TA Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCI= e Controller C Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCI= e Controller C Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCI= e Controller C Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCI= e Controller C Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCI= e Controller B Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCI= e Controller B Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCI= e Controller B Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCI= e Controller B Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCI= e Controller A Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCI= e Controller A Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCI= e Controller A Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCI= e Controller A Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHC= I Function Disable +#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fus= e Disable Read 1 Register +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCI= e Controller E Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCI= e Controller E Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCI= e Controller E Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCI= e Controller E Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCI= e Controller D Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCI= e Controller D Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCI= e Controller D Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCI= e Controller D Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCI= e Controller C Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCI= e Controller C Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCI= e Controller C Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCI= e Controller C Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCI= e Controller B Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCI= e Controller B Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCI= e Controller B Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCI= e Controller B Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCI= e Controller A Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCI= e Controller A Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCI= e Controller A Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCI= e Controller A Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHC= I Fuse Disable +#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fus= e Disable Read 2 Register +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA= Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ESPISPI_FUSE_SS_DIS BIT22 ///< ESP= ISPI Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PST= H Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHC= I Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SAT= A Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRS= B Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITS= S Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_TRACEHUB_FUSE_SS_DIS BIT7 ///< Tra= ceHub Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< Ser= ialIo Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_FLIS_FUSE_SS_DIS BIT5 ///< FLI= S Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Cam= era Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH= Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE= Fuse or Soft Strap Disable +#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Sta= tic PG Fuse and Soft Strap Disable Read Register 3 +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNC= RA3 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNC= RA2 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNC= RA1 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNC= RA Fuse or Soft Strap Disable + + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsPsf.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsPsf.h new file mode 100644 index 0000000000..e824e98913 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsPsf.h @@ -0,0 +1,304 @@ +/** @file + Register definition for PSF component + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PSF_H_ +#define _PCH_REGS_PSF_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSFx segment registers +// +#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 = ///< PSF Segment Global Configuration Register +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4 +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3 +#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4014 = ///< PSF Segment Rootspace Configuration Register +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_ENADDRP2P BIT1 +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_VTDEN BIT0 +#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4020 = ///< PSF Segment Port Configuration Register + +#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4 +#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4 +#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F +#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F + +// +// PSFx PCRs definitions +// +#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 = ///< PCI BAR0 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 = ///< PCI BAR1 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 = ///< PCI BAR2 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C = ///< PCI BAR3 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 = ///< PCI BAR4 +#define R_PCH_PSFX_PCR_T0_SHDW_PCIEN 0x1C = ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 = ///< Disable BAR0 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 = ///< Disable BAR1 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 = ///< Disable BAR2 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 = ///< Disable BAR3 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 = ///< Disable BAR4 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 = ///< Disable BAR5 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable +#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 = ///< PCI power management configuration +#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) = ///< Power status +#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 = ///< PCI configuration disable +#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 = ///< config disable + +#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C = ///< PCI configuration space enable bits +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable + +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 = ///< device number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4 +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BI= T2 | BIT1) ///< function number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1 + +#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00 +#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00 + +// +// PSF1 PCRs +// +// PSF1 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 = ///< D31F6 PSF base address (GBE) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 = ///< D20F3 PSF base address (CAM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 = ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 = ///< D22F4 PSF base address (CSME: HECI3) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 = ///< D22F1 PSF base address (CSME: HECI2) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 = ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 = ///< D22F0 PSF base address (CSME: HECI1) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 = ///< D22F3 PSF base address (CSME: KT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 = ///< D22F2 PSF base address (CSME: IDER) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 = ///< D18F1 PSF base address (CSME: CLINK) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 = ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 = ///< D18F0 PSF base address (CSME: KVM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 = ///< PCH-LP D23F0 PSF base address (SATA) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 = ///< PCH-LP D29F3 PSF base address (PCIE PORT 12) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 = ///< PCH-LP D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 = ///< PCH-LP D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 = ///< PCH-LP D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 = ///< PCH-LP D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 = ///< PCH-LP D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 = ///< PCH-LP D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 = ///< PCH-LP D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 = ///< PCH-LP D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 = ///< PCH-LP D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 = ///< PCH-LP D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 = ///< PCH-LP D28F0 PSF base address (PCIE PORT 01) + +// PSF1 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 = ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 = ///< SPT-H D22F4 PSF base address (CSME: HECI3) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 = ///< SPT-H D22F1 PSF base address (CSME: HECI2) +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 = ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 = ///< SPT-H D22F0 PSF base address (CSME: HECI1) +#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 = ///< SPT-H D22F3 PSF base address (CSME: KT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 = ///< SPT-H D22F2 PSF base address (CSME: IDER) +#define R_PCH_H_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0900 = ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_IEPMT_REG_BASE 0x0A00 = ///< D16F5 PSF base address (CSME: IEPMT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x0B00 = ///< D23F0 PSF base address (SATA) +#define R_PCH_H_PCR_PSF1_T0_SHDW_sSATA_REG_BASE 0x0C00 = ///< D17F5 PSF base address (sSATA) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 = ///< PCH-H D27F3 PSF base address (PCIE PORT 20) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 = ///< PCH-H D27F2 PSF base address (PCIE PORT 19) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 = ///< PCH-H D27F1 PSF base address (PCIE PORT 18) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 = ///< PCH-H D27F0 PSF base address (PCIE PORT 17) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 = ///< PCH-H D29F7 PSF base address (PCIE PORT 16) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 = ///< PCH-H D29F6 PSF base address (PCIE PORT 15) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 = ///< PCH-H D29F5 PSF base address (PCIE PORT 14) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 = ///< PCH-H D29F4 PSF base address (PCIE PORT 13) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 = ///< PCH-H D29F3 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 = ///< PCH-H D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 = ///< PCH-H D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 = ///< PCH-H D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 = ///< PCH-H D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 = ///< PCH-H D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 = ///< PCH-H D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 = ///< PCH-H D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 = ///< PCH-H D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 = ///< PCH-H D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 = ///< PCH-H D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 = ///< PCH-H D28F0 PSF base address (PCIE PORT 01) + +// Other PSF1 PCRs definition +#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_VS_CAP_VR_RS0_D23_F0_OFFSET16 0x1024 +#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_MMIOPI_VR_RS0_D23_F0_OFFSET16 0x1030 +#define R_PCH_H_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x4040= ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C= ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050= ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060= ///< Destination ID +#define R_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4054= ///< Multicast Control Register +#define R_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x406C= ///< Destination ID + + +//PSF 1 Multicast Message Configuration + +#define R_PCH_PCR_PSF1_RC_OWNER_RS0 = 0x4008 ///< Destination ID + +#define B_PCH_PCR_PSF1_TARGET_CHANNELID = 0xFF +#define B_PCH_PCR_PSF1_TARGET_PORTID = 0x7F00 +#define N_PCH_PCR_PSF1_TARGET_PORTID = 8 +#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID = BIT15 +#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID = 15 +#define B_PCH_PCR_PSF1_TARGET_PSFID = 0xFF0000 +#define N_PCH_PCR_PSF1_TARGET_PSFID = 16 +#define B_PCH_PCR_PSF1_TARGET_CHANMAP = BIT31 + +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID = 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID = 10 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM = 1 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT = 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 = 1 + +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 = 0x409C ///< Destination ID +#define R_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 = 0x40D0 ///< Destination ID +#define R_PCH_H_PCR_PSF5_PSF_MC_AGENT_MCAST0_RS0_TGT0_MCTP0 = 0x404C ///< Destination ID +#define R_PCH_H_PCR_PSF6_PSF_MC_AGENT_MCAST0_RS0_TGT0_MCTP0 = 0x4050 ///< Destination ID + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPST= REAM 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWN= STREAM 1 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 = 1 + +#define R_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 = 0x4060 ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 = 0x4058 ///< Multicast Control Register +#define R_PCH_H_PCR_PSF5_PSF_MC_CONTROL_MCAST0_RS0_MCTP0 = 0x4040 ///< Multicast Control Register +#define R_PCH_H_PCR_PSF6_PSF_MC_CONTROL_MCAST0_RS0_MCTP0 = 0x4044 ///< Multicast Control Register + +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN = BIT0 +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC = 0xFE +#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC = 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI = 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI = 0 + +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_VR_RS0_D23_F0 0x4240 = ///< VR +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PMT_RS0_D18_F2 0x4248 = ///< PMT +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PTIO_RS0_D22_F2 0x424C = ///< PTIO +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_PTIO_RS0_D22_F3 0x4250 = ///< PTIO +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F0 0x4254 = ///< CSE +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D18_F3 0x4258 = ///< CSE +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F1 0x425C = ///< CSE +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F4 0x4260 = ///< CSE +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D22_F7 0x4264 = ///< CSE +#define R_PCH_PCR_PSF1_T0_AGENT_FUNCTION_CONFIG_CSE_RS0_D18_F4 0x4268 = ///< CSE + +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_IFR BIT0 = ///< IFR +#define R_PCH_PCR_PSF1_RS_IFR 0x42C0 = ///< This register can be used to reset all functions in a particular Root = Space simultaneously + +// +// controls the PCI configuration header of a PCI function +// +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 /= //< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 /= //< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 /= //< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 /= //< SPC + +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x426C /= //< SPA +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x4270 /= //< SPA +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x4274 /= //< SPA +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x4278 /= //< SPA +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x427C /= //< SPB +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x4280 /= //< SPB +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x4284 /= //< SPB +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x4288 /= //< SPB +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x428C /= //< SPC +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x4290 /= //< SPC +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x4294 /= //< SPC +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x4298 /= //< SPC +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F4 0x429C /= //< SPD +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F5 0x42A0 /= //< SPD +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F6 0x42A4 /= //< SPD +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F7 0x42A8 /= //< SPD +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F0 0x42AC /= //< SPE +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F1 0x42B0 /= //< SPE +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F2 0x42B4 /= //< SPE +#define R_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F3 0x42B8 /= //< SPE + +// +// PSF1 grant count registers +// +#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC +#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0 + +#define R_PCH_H_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x42C0 +#define R_PCH_H_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x47AC + +// +// PSF2 PCRs (PID:PSF2) +// +#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 = ///< D20F2 PSF base address (Thermal). // LP&H +// PSF2 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 = ///< D30F7 PSF base address (SCC: UFS) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 = ///< D30F6 PSF base address (SCC: SDCard) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 = ///< D30F5 PSF base address (SCC: SDIO) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 = ///< D30F4 PSF base address (SCC: eMMC) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 = ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 = ///< D20F0 PSF base address (XHCI) +// PSF2 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 = ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 = ///< D20F0 PSF base address (XHCI) + +// +// PSF3 PCRs (PID:PSF3) +// +#define R_PCH_PCR_PSF3_T0_SHDW_HECI3_REG_BASE 0x0100 = ///< D16F4 PSF base address (IE: HECI3) +#define R_PCH_PCR_PSF3_T0_SHDW_HECI2_REG_BASE 0x0200 = ///< D16F1 PSF base address (IE: HECI2) +#define R_PCH_PCR_PSF3_T0_SHDW_HECI1_REG_BASE 0x0400 = ///< D16F0 PSF base address (IE: HECI1) +#define R_PCH_PCR_PSF3_T0_SHDW_KT_REG_BASE 0x0500 = ///< D16F3 PSF base address (IE: KT) +#define R_PCH_PCR_PSF3_T0_SHDW_IDER_REG_BASE 0x0600 = ///< D16F2 PSF base address (IE: IDER) +#define R_PCH_PCR_PSF3_T0_SHDW_P2SB_REG_BASE 0x0700 = ///< D31F1 PSF base address (P2SB) +#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_ACPI_REG_BASE 0x0800 = ///< D20F4 PSF base address (TraceHub ACPI) +#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_REG_BASE 0x0900 = ///< D31F7 PSF base address (TraceHub PCI) +#define R_PCH_PCR_PSF3_T0_SHDW_LPC_REG_BASE 0x0A00 = ///< D31F0 PSF base address (LPC) +#define R_PCH_PCR_PSF3_T0_SHDW_SMBUS_REG_BASE 0x0B00 = ///< D31F4 PSF base address (SMBUS) +#define R_PCH_PCR_PSF3_T0_SHDW_PMC_REG_BASE 0x0E00 = ///< D31F2 PSF base address (PMC) +#define R_PCH_PCR_PSF3_T0_SHDW_SPI_SPI_REG_BASE 0x1300 = ///< D31F5 PSF base address (SPI SPI) +#define R_PCH_H_PCR_PSF3_T0_SHDW_GBE_REG_BASE 0x1600 = ///< D31F6 PSF base address (GBE) +#define R_PCH_PCR_PSF3_T0_SHDW_AUD_REG_BASE 0x1800 = ///< D31F3 PSF base address (HDA, ADSP) +#define R_PCH_PCR_PSF3_T0_SHDW_AUD_PCIEN 0x181C = ///< D31F3 PCI Configuration space enable bits (HDA, ADSP) +#define R_PCH_PCR_PSF3_T0_SHDW_MROM1_REG_BASE 0x1A00 = ///< D17F1 PSF base address (MROM1) +#define B_PCH_PCR_PSF3_T0_SHDW_AUD_PCIEN_FUNDIS BIT8 = ///< D31F3 Function Disable +#define R_PCH_PSF3_T0_SHDW_AUD_RS1_D24_F0_BASE 0x1700 = ///< RS1D24F0 PSF base address (HDA) + +#define R_PCH_PCR_PSF3_T0_AGENT_FUNCTION_CONFIG_GBE_RS0_D31_F6 0x40F8 = ///< GBE + +#define R_PCH_PCR_PSF3_PSF_MC_CONTROL_MCAST0_EOI 0x4058 = ///< Multicast Control Register +#define R_PCH_PCR_PSF3_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4064 = ///< Destination ID + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsPsth.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsPsth.h new file mode 100644 index 0000000000..2f30ef3b5d --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsPsth.h @@ -0,0 +1,66 @@ +/** @file + Register definition for PSTH component + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PSTH_H_ +#define _PCH_REGS_PSTH_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSTH and IO Trap PCRs (PID:PSTH) +// +#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH co= ntrol register +#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IO= SF primary trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IO= SF sideband trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dy= namic clock gating enable +#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap st= atus regsiter +#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle T= rap SMI# Status mask +#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped= cycle +#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Wr= ite#: 1=3DRead, 0=3DWrite +#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active = high byte enables +#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cy= cle I/O address +#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped= write data +#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cy= cle I/O data +#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp= 0 register +#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp= 1 register +#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp= 2 register +#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp= 3 register +#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32= for 32 bit access, Read/Write mask +#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32= for 32 bit access, Read/Write#, 1=3DRead, 0=3DWrite +#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32= for 32 bit access, 16bit shift for Read/Write field +#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32) +#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte en= able mask +#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte en= able +#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Addr= ess mask +#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Addr= ess +#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap an= d SMI# Enable + + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsSata.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Register/PchRegsSata.h new file mode 100644 index 0000000000..c031c4da76 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsSata.h @@ -0,0 +1,713 @@ +/** @file + Register names for PCH SATA controllers + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller Registers (D23:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SATA 23 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 +#define V_SATA_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define PCH_SATA_FIRST_CONTROLLER 1 +#define PCH_SATA_SECOND_CONTROLLER 2 + +// +// SKL PCH-LP SATA Device ID's +// +#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controlle= r (AHCI) - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controlle= r (RAID 0/1/5/10) - premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controlle= r (RAID 1/RRT Only) - Mobile + +// +// SKL PCH-H SATA Device ID's +// +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controlle= r (AHCI) +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controlle= r (AHCI) - SPTH A0 +#define V_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controlle= r (RAID 0/1/5/10) - NOT premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controlle= r (RAID 0/1/5/10) - premium - Alternate ID +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controlle= r (RAID 0/1/5/10) - RSTe of Server SKU +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controlle= r (RAID 0/1/5/10) - premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controlle= r (RAID 1/RRT Only) + + +// +// LBG PRODUCTION INCLUDING QUAL SAMPLES SATA Device ID's +// +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI 0xA182 ///= < Server AHCI Mode (Ports 0-5) +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID 0xA184 ///= < Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA186 ///= < Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1 0xA18E ///= < Server RAID 1/RRT Only + +// +// LBG SSX (Super SKUs and Pre Production) SATA Device ID's +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_AHCI 0xA202 ///< Server= AHCI Mode (Ports 0-5) +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID 0xA204 ///< Server= RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA206 ///< Server= RAID 0/1/5/10 - premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID1 0xA20E ///< Server= RAID 1/RRT Only + +// +// LBG Alternate RST Device IDs +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2822 ///< Ser= ver RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2826 ///< Ser= ver RAID 0/1/5/10 - premium - Alternate ID for RSTe + +// +// SATA Controller common Registers +// +#define R_PCH_SATA_PI_REGISTER 0x09 +#define B_PCH_SATA_PI_REGISTER_SNC BIT3 +#define B_PCH_SATA_PI_REGISTER_SNE BIT2 +#define B_PCH_SATA_PI_REGISTER_PNC BIT1 +#define B_PCH_SATA_PI_REGISTER_PNE BIT0 +#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06 +#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04 +#define R_PCH_SATA_AHCI_BAR 0x24 +#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11 +#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19 +#define B_PCH_SATA_AHCI_BAR_PF BIT3 +#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_PCH_SATA_AHCI_BAR_RTE BIT0 +#define R_PCH_SATA_PID 0x70 +#define B_PCH_SATA_PID_NEXT 0xFF00 +#define V_PCH_SATA_PID_NEXT_0 0xB000 +#define V_PCH_SATA_PID_NEXT_1 0xA800 +#define B_PCH_SATA_PID_CID 0x00FF +#define R_PCH_SATA_PC 0x72 +#define S_PCH_SATA_PC 2 +#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12= | BIT11) +#define V_PCH_SATA_PC_PME_0 0x0000 +#define V_PCH_SATA_PC_PME_1 0x4000 +#define B_PCH_SATA_PC_D2_SUP BIT10 +#define B_PCH_SATA_PC_D1_SUP BIT9 +#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_SATA_PC_DSI BIT5 +#define B_PCH_SATA_PC_PME_CLK BIT3 +#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_SATA_PMCS 0x74 +#define B_PCH_SATA_PMCS_PMES BIT15 +#define B_PCH_SATA_PMCS_PMEE BIT8 +#define B_PCH_SATA_PMCS_NSFRST BIT3 +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 +#define R_PCH_SATA_MID 0x80 +#define B_PCH_SATA_MID_NEXT 0xFF00 +#define B_PCH_SATA_MID_CID 0x00FF +#define R_PCH_SATA_MC 0x82 +#define B_PCH_SATA_MC_C64 BIT7 +#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_PCH_SATA_MC_MME_4 0x04 +#define V_PCH_SATA_MC_MME_2 0x02 +#define V_PCH_SATA_MC_MME_1 0x01 +#define V_PCH_SATA_MC_MME_0 0x00 +#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_PCH_SATA_MC_MMC_4 0x04 +#define V_PCH_SATA_MC_MMC_0 0x00 +#define B_PCH_SATA_MC_MSIE BIT0 +#define V_PCH_SATA_MC_MSIE_1 0x01 +#define V_PCH_SATA_MC_MSIE_0 0x00 +#define R_PCH_SATA_MA 0x84 +#define B_PCH_SATA_MA 0xFFFFFFFC +#define R_PCH_SATA_MD 0x88 +#define B_PCH_SATA_MD_MSIMD 0xFFFF + +// +// Sata Register for PCH-LP +// +#define R_PCH_LP_SATA_MAP 0x90 +#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8) +#define N_PCH_LP_SATA_MAP_SPD 8 +#define B_PCH_LP_SATA_MAP_SPD2 BIT10 +#define B_PCH_LP_SATA_MAP_SPD1 BIT9 +#define B_PCH_LP_SATA_MAP_SPD0 BIT8 +#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6 +#define N_PCH_LP_SATA_MAP_SMS_MASK 6 +#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0 +#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1 +#define R_PCH_LP_SATA_PCS 0x92 +#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15 +#define B_PCH_LP_SATA_PCS_P2P BIT10 +#define B_PCH_LP_SATA_PCS_P1P BIT9 +#define B_PCH_LP_SATA_PCS_P0P BIT8 +#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0) +#define B_PCH_LP_SATA_PCS_P2E BIT2 +#define B_PCH_LP_SATA_PCS_P1E BIT1 +#define B_PCH_LP_SATA_PCS_P0E BIT0 +#define R_PCH_LP_SATA_SCLKGC 0x94 +#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24) +#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26 +#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25 +#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24 +#define R_PCH_LP_SATA_98 0x98 + +// +// Sata Register for PCH-H +// +#define R_PCH_H_SATA_MAP 0x90 +#define B_PCH_H_SATA_MAP_SPD 0xFF0000 +#define N_PCH_H_SATA_MAP_SPD 16 +#define B_PCH_H_SATA_MAP_SPD7 BIT23 +#define B_PCH_H_SATA_MAP_SPD6 BIT22 +#define B_PCH_H_SATA_MAP_SPD5 BIT21 +#define B_PCH_H_SATA_MAP_SPD4 BIT20 +#define B_PCH_H_SATA_MAP_SPD3 BIT19 +#define B_PCH_H_SATA_MAP_SPD2 BIT18 +#define B_PCH_H_SATA_MAP_SPD1 BIT17 +#define B_PCH_H_SATA_MAP_SPD0 BIT16 +#define B_PCH_H_SATA_MAP_PCD 0xFF +#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7 +#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6 +#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5 +#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4 +#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3 +#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2 +#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1 +#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0 +#define R_PCH_H_SATA_PCS 0x94 +#define B_PCH_H_SATA_PCS_P7P BIT23 +#define B_PCH_H_SATA_PCS_P6P BIT22 +#define B_PCH_H_SATA_PCS_P5P BIT21 +#define B_PCH_H_SATA_PCS_P4P BIT20 +#define B_PCH_H_SATA_PCS_P3P BIT19 +#define B_PCH_H_SATA_PCS_P2P BIT18 +#define B_PCH_H_SATA_PCS_P1P BIT17 +#define B_PCH_H_SATA_PCS_P0P BIT16 +#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF +#define B_PCH_H_SATA_PCS_P7E BIT7 +#define B_PCH_H_SATA_PCS_P6E BIT6 +#define B_PCH_H_SATA_PCS_P5E BIT5 +#define B_PCH_H_SATA_PCS_P4E BIT4 +#define B_PCH_H_SATA_PCS_P3E BIT3 +#define B_PCH_H_SATA_PCS_P2E BIT2 +#define B_PCH_H_SATA_PCS_P1E BIT1 +#define B_PCH_H_SATA_PCS_P0E BIT0 + +#define R_PCH_SATA_SATAGC 0x9C +#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16 +#define N_PCH_H_SATA_SATAGC_SMS_MASK 16 +#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0 +#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1 +#define B_PCH_SATA_SATAGC_AIE BIT7 +#define B_PCH_SATA_SATAGC_AIES BIT6 +#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3) +#define V_PCH_SATA_SATAGC_MSS_8K 0x2 +#define N_PCH_SATA_SATAGC_MSS 3 +#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) + +#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0 +#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1 +#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2 +#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3 +#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4 +#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5 +#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6 + +#define R_PCH_SATA_SIRI 0xA0 +#define R_PCH_SATA_STRD 0xA4 +#define R_PCH_SATA_SIR_50 0x50 +#define R_PCH_SATA_SIR_54 0x54 +#define R_PCH_SATA_SIR_58 0x58 +#define R_PCH_SATA_SIR_5C 0x5C +#define R_PCH_SATA_SIR_60 0x60 +#define R_PCH_SATA_SIR_64 0x64 +#define R_PCH_SATA_SIR_68 0x68 +#define R_PCH_SATA_SIR_6C 0x6C +#define R_PCH_SATA_SIR_70 0x70 +#define R_PCH_SATA_SIR_80 0x80 +#define R_PCH_SATA_SIR_84 0x84 +#define R_PCH_SATA_SIR_8C 0x8C +#define R_PCH_SATA_SIR_90 0x90 +#define R_PCH_SATA_SIR_98 0x98 +#define R_PCH_SATA_SIR_9C 0x9C +#define R_PCH_SATA_SIR_A0 0xA0 +#define R_PCH_SATA_SIR_A4 0xA4 +#define R_PCH_SATA_SIR_A8 0xA8 +#define R_PCH_SATA_SIR_C8 0xC8 +#define R_PCH_SATA_SIR_CC 0xCC +#define R_PCH_SATA_SIR_D0 0xD0 +#define R_PCH_SATA_SIR_D4 0xD4 +#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF +#define B_PCH_SATA_SIR_CTM4_ORM BIT6 +#define R_PCH_SATA_CR0 0xA8 +#define B_PCH_SATA_CR0_MAJREV 0x00F00000 +#define B_PCH_SATA_CR0_MINREV 0x000F0000 +#define B_PCH_SATA_CR0_NEXT 0x0000FF00 +#define B_PCH_SATA_CR0_CAP 0x000000FF +#define R_PCH_SATA_CR1 0xAC +#define B_PCH_SATA_CR1_BAROFST 0xFFF0 +#define B_PCH_SATA_CR1_BARLOC 0x000F +#define R_PCH_SATA_FLR_CID 0xB0 +#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 +#define B_PCH_SATA_FLR_CID 0x00FF +#define V_PCH_SATA_FLR_CID_1 0x0009 +#define V_PCH_SATA_FLR_CID_0 0x0013 +#define R_PCH_SATA_FLR_CLV 0xB2 +#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_PCH_SATA_FLRC 0xB4 +#define B_PCH_SATA_FLRC_TXP BIT8 +#define B_PCH_SATA_FLRC_INITFLR BIT0 +#define R_PCH_SATA_SP 0xC0 +#define B_PCH_SATA_SP 0xFFFFFFFF +#define R_PCH_SATA_MXID 0xD0 +#define N_PCH_SATA_MXID_NEXT 8 + +#define R_PCH_SATA_BFCS 0xE0 +#define B_PCH_SATA_BFCS_P7BFI BIT17 +#define B_PCH_SATA_BFCS_P6BFI BIT16 +#define B_PCH_SATA_BFCS_P5BFI BIT15 +#define B_PCH_SATA_BFCS_P4BFI BIT14 +#define B_PCH_SATA_BFCS_P3BFI BIT13 +#define B_PCH_SATA_BFCS_P2BFI BIT12 +#define B_PCH_SATA_BFCS_P2BFS BIT11 +#define B_PCH_SATA_BFCS_P2BFF BIT10 +#define B_PCH_SATA_BFCS_P1BFI BIT9 +#define B_PCH_SATA_BFCS_P0BFI BIT8 +#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7 +#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6 +#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5 +#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4 +#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3 +#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 +#define R_PCH_SATA_BFTD1 0xE4 +#define B_PCH_SATA_BFTD1 0xFFFFFFFF +#define R_PCH_SATA_BFTD2 0xE8 +#define B_PCH_SATA_BFTD2 0xFFFFFFFF + +#define R_PCH_SATA_VS_CAP 0xA4 +#define B_PCH_SATA_VS_CAP_NRMBE BIT0 = ///< NVM Remap Memory BAR Enable +#define B_PCH_SATA_VS_CAP_MSL 0x1FFE = ///< Memory Space Limit +#define N_PCH_SATA_VS_CAP_MSL 1 +#define V_PCH_SATA_VS_CAP_MSL 0x1EF = ///< Memory Space Limit Field Value +#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 = ///< NVM Remapped Memory Offset +#define N_PCH_SATA_VS_CAP_NRMO 16 +#define V_PCH_SATA_VS_CAP_NRMO 0x10 = ///< NVM Remapped Memory Offset Field Value + +// +// RST PCIe Storage Remapping Registers +// +#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 = ///< Remap Capability Register +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) = ///< Number of Remapping Supported +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 = ///< Number of Remapping Supported (RST PCIe Storage Cycle Router = #1) +#define R_PCH_RST_PCIE_STORAGE_AMXC 0x808 = ///< AHCI MSI-X Configuration +#define B_PCH_RST_PCIE_STORAGE_AMXC_AMXV 0x7FF = ///< AHCI MSI-X Vector +#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C = ///< Scratch Pad Register +#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 = ///< CR#1 Device Class Code +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8 +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16 +#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 = ///< Device Type +#define R_PCH_RST_PCIE_STORAGE_CR1_DMBL 0x884 = ///< CR#1 Device Memory BAR Length +#define R_PCH_RST_PCIE_STORAGE_CR1_DMXC 0x888 = ///< CR#1 Device MSI-X Configuration +#define N_PCH_RST_PCIE_STORAGE_CR1_DMXC_MXEV 16 +#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 = ///< Remapped Configuration for RST PCIe Storage Cycle Router #n +#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 = ///< Remapped Root Port Offset Value +#define R_PCH_RST_PCIE_STORAGE_GCR 0x300 = ///< General Configuration Register +#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 = ///< Port Configuration Register +#define B_PCH_RST_PCIE_STORAGE_GCR_CRE BIT0 = ///< RST PCIe Storage Cycle Router Enable +#define B_PCH_RST_PCIE_STORAGE_GCR_PLS 0x1FFFFE = ///< PCIe Lane Selected Field +#define B_PCH_RST_PCIE_STORAGE_GCR_PNCAIDL BIT29 = ///< Configuration Access Index/Data Lockdown +#define B_PCH_RST_PCIE_STORAGE_GCR_RCL BIT30 = ///< Remapping Configuration Lockdown +#define B_PCH_RST_PCIE_STORAGE_GCR_CREL BIT31 = ///< RST PCIe Storage Cycle Router Enable Lockdown +#define R_PCH_RST_PCIE_STORAGE_GSR 0x304 = ///< General Status Register +#define B_PCH_RST_PCIE_STORAGE_GSR_PLRC 0x1FFFFE = ///< PCIe Lane Remap Capable Field +#define B_PCH_RST_PCIE_STORAGE_GSR_PCCS BIT30 = ///< Port Configuration Check Status +#define B_PCH_RST_PCIE_STORAGE_GSR_PCCD BIT31 = ///< Port Configuration Check Disable +#define R_PCH_RST_PCIE_STORAGE_CAIR 0x308 = ///< Configuration Access Index Register +#define R_PCH_RST_PCIE_STORAGE_CADR 0x30C = ///< Configuration Access Data Register +#define R_PCH_RST_PCIE_STORAGE_MBRC 0x310 = ///< Memory BAR Remap Configuration +#define B_PCH_RST_PCIE_STORAGE_MBRC_TMB (BIT19|BIT18|BIT17|BIT1= 6) ///< Memory BAR Remap Configuration Target Memory BAR +#define N_PCH_RST_PCIE_STORAGE_MBRC_TMB 16 +#define V_PCH_RST_PCIE_STORAGE_MBRC_TMB_BAR0 0x4 = ///< Memory BAR Remap Configuration Target Memory BAR - BAR0 +#define V_PCH_RST_PCIE_STORAGE_MBRC_TMB_BAR5 0x9 = ///< Memory BAR Remap Configuration Target Memory BAR - BAR5 +#define B_PCH_RST_PCIE_STORAGE_MBRC_TT BIT20 = ///< Remap Configuration Target Type +#define B_PCH_RST_PCIE_STORAGE_MBRC_RE BIT31 = ///< Remap Configuration Remap Enable +#define R_PCH_RST_PCIE_STORAGE_IOBRSC 0x320 ///< I/O BA= R Remap Source Configuration +#define B_PCH_RST_PCIE_STORAGE_IOBRSC_RE BIT31 ///< I/O BA= R Remap Source Configuration Remap Enable +#define R_PCH_RST_PCIE_STORAGE_AIDPCRC 0x338 ///< AHCI I= ndex/Data Pair Capability Remap Configuration +#define B_PCH_RST_PCIE_STORAGE_AIDPCRC_TCSO 0xFF0000 ///< AHCI I= ndex/Data Pair Capability Remap Configuration Target Capability Structure O= ffsBet +#define N_PCH_RST_PCIE_STORAGE_AIDPCRC_TCSO 16 +#define B_PCH_RST_PCIE_STORAGE_AIDPCRC_RE BIT31 ///< AHCI I= ndex/Data Pair Capability Remap Configuration Remap Enable +#define R_PCH_RST_PCIE_STORAGE_MXCRC 0x33C ///< MSI-X = Capability Remap Configuration +#define B_PCH_RST_PCIE_STORAGE_MXCRCC_TCSO 0xFF0000 ///< MSI-X = Capability Remap Configuration Target Capability Structure Offset +#define N_PCH_RST_PCIE_STORAGE_MXCRCC_TCSO 16 +#define B_PCH_RST_PCIE_STORAGE_MXCRC_RE BIT31 ///< MSI-X = Capability Remap Configuration Remap Enable +#define R_PCH_RST_PCIE_STORAGE_MXTRC 0x340 ///< MSI-X = Table Remap Configuration +#define B_PCH_RST_PCIE_STORAGE_MXTRC_TBIR 0x07 ///< MSI-X = Table Remap Configuration Table BIR +#define B_PCH_RST_PCIE_STORAGE_MXTRC_TO 0xFFFFFFF8 ///< MSI-X = Table Remap Configuration Table Offset +#define R_PCH_RST_PCIE_STORAGE_MXTBAR 0x344 ///< MSI-X = Table Base Address Register +#define B_PCH_RST_PCIE_STORAGE_MXTBAR_TBAV BIT0 ///< MSI-X = Table Base Address Register Table Base Address Valid +#define R_PCH_RST_PCIE_STORAGE_MXPRC 0x348 ///< MSI-X = PBA Remap Configuration +#define B_PCH_RST_PCIE_STORAGE_MXPRC_TBIR 0x07 ///< MSI-X = PBA Remap Configuration Table BIR +#define B_PCH_RST_PCIE_STORAGE_MXPRC_TO 0xFFFFFFF8 ///< MSI-X = PBA Remap Configuration Table Offset +#define R_PCH_RST_PCIE_STORAGE_MXPBAR 0x34C ///< MSI-X = PBA Base Address Register +#define B_PCH_RST_PCIE_STORAGE_MXPBAR_TBAV BIT0 ///< MSI-X = PBA Base Address Register Table Base Address Valid +#define R_PCH_RST_PCIE_STORAGE_NRDF 0x350 ///< NVM Re= mapping Device:Function +#define R_PCH_RST_PCIE_STORAGE_EGCR 0x354 ///< Extend= ed General Configuration Register +#define B_PCH_RST_PCIE_STORAGE_EGCR_CRDCGE BIT16 ///< RST PC= Ie Storage Cycle Router Dynamic Clock Gating Enable +#define B_PCH_RST_PCIE_STORAGE_EGCR_CRTCGE BIT17 ///< RST PC= Ie Storage Cycle Router Trunk Clock Gating Enable +#define B_PCH_RST_PCIE_STORAGE_EGCR_ICAS BIT19 ///< IOSF C= LKREQ Assertion Select +#define B_PCH_RST_PCIE_STORAGE_EGCR_TSCAS BIT20 ///< To SAT= A CLKREQ Assertion Select +#define R_PCH_RST_PCIE_STORAGE_SAPI 0x358 ///< Shadow= ed AHCI Ports Implemented +#define R_PCH_RST_PCIE_STORAGE_CRGC 0xFC0 ///< RST PC= Ie Storage Cycle Router Global Control +#define B_PCH_RST_PCIE_STORAGE_CRGC_CRAS (BIT1|BIT0) ///< RST PC= Ie Storage Cycle Router Global Control Cycle Router Accessibility Select + +// +// AHCI BAR Area related Registers +// +#define R_PCH_SATA_AHCI_CAP 0x0 +#define B_PCH_SATA_AHCI_CAP_S64A BIT31 +#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 +#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 +#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock = Switch +#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Sp= in-up +#define B_PCH_SATA_AHCI_CAP_SALP BIT26 +#define B_PCH_SATA_AHCI_CAP_SAL BIT25 +#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command Li= st Override +#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Sup= port +#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 +#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 +#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 +#define B_PCH_SATA_AHCI_CAP_SAM BIT18 +#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multi= plier +#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Bl= ock +#define B_PCH_SATA_AHCI_CAP_SSC BIT14 +#define B_PCH_SATA_AHCI_CAP_PSC BIT13 +#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 +#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 +#define B_PCH_SATA_AHCI_CAP_EMS BIT6 +#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is su= pported +#define B_PCH_SATA_AHCI_CAP_NPS 0x001F + +#define R_PCH_SATA_AHCI_GHC 0x04 +#define B_PCH_SATA_AHCI_GHC_AE BIT31 +#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 +#define B_PCH_SATA_AHCI_GHC_IE BIT1 +#define B_PCH_SATA_AHCI_GHC_HR BIT0 + +#define R_PCH_SATA_AHCI_IS 0x08 +#define B_PCH_SATA_AHCI_IS_PORT7 BIT7 +#define B_PCH_SATA_AHCI_IS_PORT6 BIT6 +#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 +#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 +#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 +#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 +#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 +#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 +#define R_SATA_MEM_AHCI_PI 0x0C +#define B_PCH_H_SATA_PORT_MASK 0xFF +#define B_PCH_LP_SATA_PORT_MASK 0x03 +#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7 +#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6 +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 +#define R_PCH_SATA_AHCI_VS 0x10 +#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 +#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_LOC 0x1C +#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_CTRL 0x20 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 +#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 +#define R_PCH_SATA_AHCI_CAP2 0x24 +#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 +#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 +#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 +#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial t= o Slumber Transitions +#define R_PCH_SATA_AHCI_VSP 0xA0 +#define B_PCH_SATA_AHCI_VSP_SLPD BIT0 +#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabil= ities +#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10) +#define N_PCH_SATA_AHCI_RSTF_OUD 10 +#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9 +#define B_PCH_SATA_AHCI_RSTF_IROES BIT8 +#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7 +#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6 +#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5 +#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4 +#define B_PCH_SATA_AHCI_RSTF_R5E BIT3 +#define B_PCH_SATA_AHCI_RSTF_R10E BIT2 +#define B_PCH_SATA_AHCI_RSTF_R1E BIT1 +#define B_PCH_SATA_AHCI_RSTF_R0E BIT0 +#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF +#define R_PCH_SATA_AHCI_P0CLB 0x100 +#define R_PCH_SATA_AHCI_P1CLB 0x180 +#define R_PCH_SATA_AHCI_P2CLB 0x200 +#define R_PCH_SATA_AHCI_P3CLB 0x280 +#define R_PCH_SATA_AHCI_P4CLB 0x300 +#define R_PCH_SATA_AHCI_P5CLB 0x380 +#define R_PCH_SATA_AHCI_P6CLB 0x400 +#define R_PCH_SATA_AHCI_P7CLB 0x480 +#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 +#define R_PCH_SATA_AHCI_P0CLBU 0x104 +#define R_PCH_SATA_AHCI_P1CLBU 0x184 +#define R_PCH_SATA_AHCI_P2CLBU 0x204 +#define R_PCH_SATA_AHCI_P3CLBU 0x284 +#define R_PCH_SATA_AHCI_P4CLBU 0x304 +#define R_PCH_SATA_AHCI_P5CLBU 0x384 +#define R_PCH_SATA_AHCI_P6CLBU 0x404 +#define R_PCH_SATA_AHCI_P7CLBU 0x484 +#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0FB 0x108 +#define R_PCH_SATA_AHCI_P1FB 0x188 +#define R_PCH_SATA_AHCI_P2FB 0x208 +#define R_PCH_SATA_AHCI_P3FB 0x288 +#define R_PCH_SATA_AHCI_P4FB 0x308 +#define R_PCH_SATA_AHCI_P5FB 0x388 +#define R_PCH_SATA_AHCI_P6FB 0x408 +#define R_PCH_SATA_AHCI_P7FB 0x488 +#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 +#define R_PCH_SATA_AHCI_P0FBU 0x10C +#define R_PCH_SATA_AHCI_P1FBU 0x18C +#define R_PCH_SATA_AHCI_P2FBU 0x20C +#define R_PCH_SATA_AHCI_P3FBU 0x28C +#define R_PCH_SATA_AHCI_P4FBU 0x30C +#define R_PCH_SATA_AHCI_P5FBU 0x38C +#define R_PCH_SATA_AHCI_P6FBU 0x40C +#define R_PCH_SATA_AHCI_P7FBU 0x48C +#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0IS 0x110 +#define R_PCH_SATA_AHCI_P1IS 0x190 +#define R_PCH_SATA_AHCI_P2IS 0x210 +#define R_PCH_SATA_AHCI_P3IS 0x290 +#define R_PCH_SATA_AHCI_P4IS 0x310 +#define R_PCH_SATA_AHCI_P5IS 0x390 +#define R_PCH_SATA_AHCI_P6IS 0x410 +#define R_PCH_SATA_AHCI_P7IS 0x490 +#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 +#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 +#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 +#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 +#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 +#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 +#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 +#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 +#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 +#define B_PCH_SATA_AHCI_PXIS_DIS BIT7 +#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 +#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 +#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 +#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 +#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 +#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 +#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 +#define R_PCH_SATA_AHCI_P0IE 0x114 +#define R_PCH_SATA_AHCI_P1IE 0x194 +#define R_PCH_SATA_AHCI_P2IE 0x214 +#define R_PCH_SATA_AHCI_P3IE 0x294 +#define R_PCH_SATA_AHCI_P4IE 0x314 +#define R_PCH_SATA_AHCI_P5IE 0x394 +#define R_PCH_SATA_AHCI_P6IE 0x414 +#define R_PCH_SATA_AHCI_P7IE 0x494 +#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 +#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 +#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 +#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 +#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 +#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 +#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 +#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 +#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 +#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 +#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 +#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 +#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 +#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 +#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 +#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 +#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 +#define R_PCH_SATA_AHCI_P0CMD 0x118 +#define R_PCH_SATA_AHCI_P1CMD 0x198 +#define R_PCH_SATA_AHCI_P2CMD 0x218 +#define R_PCH_SATA_AHCI_P3CMD 0x298 +#define R_PCH_SATA_AHCI_P4CMD 0x318 +#define R_PCH_SATA_AHCI_P5CMD 0x398 +#define R_PCH_SATA_AHCI_P6CMD 0x418 +#define R_PCH_SATA_AHCI_P7CMD 0x498 +#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21= | BIT19 | BIT18) +#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 +#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 +#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 +#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 +#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 +#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 +#define R_PCH_SATA_AHCI_P2DEVSLP 0x244 +#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4 +#define R_PCH_SATA_AHCI_P4DEVSLP 0x344 +#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4 +#define R_PCH_SATA_AHCI_P6DEVSLP 0x444 +#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4 +#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 +#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an extern= al SATA device +#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch A= ttached to Port +#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 +#define B_SATA_MEM_AHCI_PxCMD_FR BIT14 +#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13 +#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 +#define B_SATA_MEM_AHCI_PxCMD_FRE BIT4 +#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 +#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 +#define R_PCH_SATA_AHCI_P0TFD 0x120 +#define R_PCH_SATA_AHCI_P1TFD 0x1A0 +#define R_PCH_SATA_AHCI_P2TFD 0x220 +#define R_PCH_SATA_AHCI_P3TFD 0x2A0 +#define R_PCH_SATA_AHCI_P4TFD 0x320 +#define R_PCH_SATA_AHCI_P5TFD 0x3A0 +#define R_PCH_SATA_AHCI_P6TFD 0x420 +#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF +#define R_PCH_SATA_AHCI_P0SIG 0x124 +#define R_PCH_SATA_AHCI_P1SIG 0x1A4 +#define R_PCH_SATA_AHCI_P2SIG 0x224 +#define R_PCH_SATA_AHCI_P3SIG 0x2A4 +#define R_PCH_SATA_AHCI_P4SIG 0x324 +#define R_PCH_SATA_AHCI_P5SIG 0x3A4 +#define R_PCH_SATA_AHCI_P6SIG 0x424 +#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF +#define R_PCH_SATA_AHCI_P0SSTS 0x128 +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 +#define R_PCH_SATA_AHCI_P2SSTS 0x228 +#define R_PCH_SATA_AHCI_P3SSTS 0x2A8 +#define R_PCH_SATA_AHCI_P4SSTS 0x328 +#define R_PCH_SATA_AHCI_P5SSTS 0x3A8 +#define R_PCH_SATA_AHCI_P6SSTS 0x428 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SCTL 0x12C +#define R_PCH_SATA_AHCI_P1SCTL 0x1AC +#define R_PCH_SATA_AHCI_P2SCTL 0x22C +#define R_PCH_SATA_AHCI_P3SCTL 0x2AC +#define R_PCH_SATA_AHCI_P4SCTL 0x32C +#define R_PCH_SATA_AHCI_P5SCTL 0x3AC +#define R_PCH_SATA_AHCI_P6SCTL 0x42C +#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F +#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SERR 0x130 +#define R_PCH_SATA_AHCI_P1SERR 0x1B0 +#define R_PCH_SATA_AHCI_P2SERR 0x230 +#define R_PCH_SATA_AHCI_P3SERR 0x2B0 +#define R_PCH_SATA_AHCI_P4SERR 0x330 +#define R_PCH_SATA_AHCI_P5SERR 0x3B0 +#define R_PCH_SATA_AHCI_P6SERR 0x430 +#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1 +#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0 +#define R_PCH_SATA_AHCI_P0SACT 0x134 +#define R_PCH_SATA_AHCI_P1SACT 0x1B4 +#define R_PCH_SATA_AHCI_P2SACT 0x234 +#define R_PCH_SATA_AHCI_P3SACT 0x2B4 +#define R_PCH_SATA_AHCI_P4SACT 0x334 +#define R_PCH_SATA_AHCI_P5SACT 0x3B4 +#define R_PCH_SATA_AHCI_P6SACT 0x434 +#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0CI 0x138 +#define R_PCH_SATA_AHCI_P1CI 0x1B8 +#define R_PCH_SATA_AHCI_P2CI 0x238 +#define R_PCH_SATA_AHCI_P3CI 0x2B8 +#define R_PCH_SATA_AHCI_P4CI 0x338 +#define R_PCH_SATA_AHCI_P5CI 0x3B8 +#define R_PCH_SATA_AHCI_P6CI 0x438 +#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsSmbus.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg= /Include/Register/PchRegsSmbus.h new file mode 100644 index 0000000000..80d116493a --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsSmbus.h @@ -0,0 +1,157 @@ +/** @file + Register names for PCH Smbus Device. + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 +#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SMBUS_DEVICE_ID 0xA123 +// +// LBG Production SMBus Controller Device ID +// +#define V_PCH_LBG_PROD_SMBUS_DEVICE_ID 0xA1A3 +// +// LBG SSX (Super SKU) SMBus Controller Device ID +// +#define V_PCH_LBG_SMBUS_DEVICE_ID 0xA223 +#define V_PCH_LP_SMBUS_DEVICE_ID 0x9D23 +#define R_PCH_SMBUS_BASE 0x20 +#define V_PCH_SMBUS_BASE_SIZE (1 << 5) +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SPDWD BIT4 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +#define R_PCH_SMBUS_TCOBASE 0x50 +#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_TCOCTL 0x54 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 +#define R_PCH_SMBUS_64 0x64 +#define R_PCH_SMBUS_80 0x80 + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register = R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_= BERR | B_PCH_SMBUS_FAIL) +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register= R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 +#define B_PCH_SMBUS_SMB_CMD 0x1C +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_PCH_SMBUS_LAST_BYTE 0x20 +#define B_PCH_SMBUS_START 0x40 +#define B_PCH_SMBUS_PEC_EN 0x80 +#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register= R/W +#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Addres= s Register R/W +#define B_PCH_SMBUS_RW_SEL 0x01 +#define B_PCH_SMBUS_READ 0x01 // RW +#define B_PCH_SMBUS_WRITE 0x00 // RW +#define B_PCH_SMBUS_ADDRESS 0xFE +#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Regis= ter R/W +#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Da= ta Register R/W +#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address= Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F +#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Re= gister R/W +#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Regi= ster R/WC +#define B_PCH_SMBUS_CRCE 0x01 +#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode +#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Reg= ister R/W +#define B_PCH_SMBUS_AAC 0x01 +#define B_PCH_SMBUS_E32B 0x02 +#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Re= gister R/W +#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 +#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 +#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 +#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Reg= ister R/W +#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 +#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 +#define B_PCH_SMBUS_SMBCLK_CTL 0x04 +#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register= R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 +#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Registe= r R/W +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 +#define B_PCH_SMBUS_SMBALERT_DIS 0x04 +#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address= Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE +#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte = Register RO +#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte= Register RO + +// +// SMBus Private Config Registers +// (PID:SMB) +// +#define R_PCH_PCR_SMBUS_TCOCFG 0x00 = ///< TCO Configuration register +#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 = ///< TCO IRQ Enable +#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) = ///< TCO IRQ Select +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 = ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 = ///< only if APIC enabled +#define R_PCH_PCR_SMBUS_SMBTM 0x04 = ///< SMBus Test Mode +#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 = ///< SMBus Counter +#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 = ///< SMBus Deglitch +#define R_PCH_PCR_SMBUS_SCTM 0x08 = ///< Short Counter Test Mode +#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 = ///< Simulation Speed-Up +#define R_PCH_PCR_SMBUS_GC 0x0C = ///< General Control +#define B_PCH_PCR_SMBUS_GC_FD BIT0 = ///< Function Disable +#define B_PCH_PCR_SMBUS_GC_NR BIT1 = ///< No Reboot +#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 = ///< SMB Static Clock Gating Enable +#define R_PCH_PCR_SMBUS_PCE 0x10 = ///< Power Control Enable +#define B_PCH_PCR_SMBUS_PCE_HAE BIT5 = ///< Hardware Autonomous Enable + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsSpi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsSpi.h new file mode 100644 index 0000000000..cbd3dad872 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsSpi.h @@ -0,0 +1,354 @@ +/** @file + Register names for PCH SPI device. + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Registers (D31:F5) +// + +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 +#define V_PCH_SPI_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SPI_DEVICE_ID 0xA124 +// +// LBG PRODUCTION SPI Device ID +// +#define V_PCH_LBG_PROD_SPI_DEVICE_ID 0xA1A4 +// +// LBG SSX (Super SKU) SPI Device ID +// +#define V_PCH_LBG_SPI_DEVICE_ID 0xA224 +#define V_PCH_LP_SPI_DEVICE_ID 0x9D24 +#define R_SPI_CFG_BAR0 0x10 +#define B_SPI_CFG_BAR0_MASK 0x0FFF + +#define R_SPI_CFG_BDE 0xD8 +#define B_SPI_CFG_BDE_F8 0x8000 +#define B_SPI_CFG_BDE_F0 0x4000 +#define B_SPI_CFG_BDE_E8 0x2000 +#define B_SPI_CFG_BDE_E0 0x1000 +#define B_SPI_CFG_BDE_D8 0x0800 +#define B_SPI_CFG_BDE_D0 0x0400 +#define B_SPI_CFG_BDE_C8 0x0200 +#define B_SPI_CFG_BDE_C0 0x0100 +#define B_SPI_CFG_BDE_LEG_F 0x0080 +#define B_SPI_CFG_BDE_LEG_E 0x0040 +#define B_SPI_CFG_BDE_70 0x0008 +#define B_SPI_CFG_BDE_60 0x0004 +#define B_SPI_CFG_BDE_50 0x0002 +#define B_SPI_CFG_BDE_40 0x0001 + +#define R_SPI_CFG_BC 0xDC +#define S_SPI_CFG_BC 4 +#define N_SPI_CFG_BC_ASE_BWP 11 +#define B_SPI_CFG_BC_ASE_BWP BIT11 +#define N_SPI_CFG_BC_ASYNC_SS 10 +#define B_SPI_CFG_BC_ASYNC_SS BIT10 +#define B_SPI_CFG_BC_OSFH BIT9 ///< OS Functi= on Hide +#define N_SPI_CFG_BC_SYNC_SS 8 +#define B_SPI_CFG_BC_SYNC_SS BIT8 +#define B_SPI_CFG_BC_BILD BIT7 +#define B_SPI_CFG_BC_BBS BIT6 ///< Boot BIOS= strap +#define N_SPI_CFG_BC_BBS 6 +#define V_SPI_CFG_BC_BBS_SPI 0 ///< Boot BIOS= strapped to SPI +#define V_SPI_CFG_BC_BBS_LPC 1 ///< Boot BIOS= strapped to LPC +#define B_SPI_CFG_BC_EISS BIT5 ///< Enable In= SMM.STS +#define B_SPI_CFG_BC_TSS BIT4 +#define B_SPI_CFG_BC_SRC (BIT3 | BIT2) +#define N_SPI_CFG_BC_SRC 2 +#define V_SPI_CFG_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetchi= ng and Caching enabled +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefet= ching and no caching +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefet= ching, but caching enabled +#define B_SPI_CFG_BC_LE BIT1 ///< Lock Enab= le +#define N_SPI_CFG_BC_BLE 1 +#define B_SPI_CFG_BC_WPD BIT0 ///< Write Pro= tect Disable + +// +// BIOS Flash Program Registers (based on SPI_BAR0) +// +#define R_SPI_MEM_BFPR 0x00 = ///< BIOS Flash Primary Region Register(32bits), which is RO and contains t= he same value from FREG1 +#define B_SPI_MEM_BFPR_PRL 0x7FFF0000 = ///< BIOS Flash Primary Region Limit mask +#define N_SPI_MEM_BFPR_PRL 16 = ///< BIOS Flash Primary Region Limit bit position +#define B_SPI_MEM_BFPR_PRB 0x00007FFF = ///< BIOS Flash Primary Region Base mask +#define N_SPI_MEM_BFPR_PRB 0 = ///< BIOS Flash Primary Region Base bit position +#define B_PCH_SPI_BFPR_SBRS BIT31 = ///< BIOS Flash Primary Region Shadowed BIOS Region Select +#define R_SPI_MEM_HSFSC 0x04 = ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_SPI_MEM_HSFSC_FSMIE BIT31 = ///< Flash SPI SMI# Enable +#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 = ///< Flash Data Byte Count ( <=3D 64), Count =3D (Value in this field) + 1. +#define N_SPI_MEM_HSFSC_FDBC 24 +#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 = ///< Flash Cycle. +#define N_SPI_MEM_HSFSC_CYCLE 17 +#define V_SPI_MEM_HSFSC_CYCLE_READ 0 = ///< Flash Cycle Read +#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 = ///< Flash Cycle Write +#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 = ///< Flash Cycle 4K Block Erase +#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 = ///< Flash Cycle 64K Sector Erase +#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 = ///< Flash Cycle Read SFDP +#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 = ///< Flash Cycle Read JEDEC ID +#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 = ///< Flash Cycle Write Status +#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 = ///< Flash Cycle Read Status +#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 = ///< Flash Cycle Go. +#define B_SPI_MEM_HSFSC_FLOCKDN BIT15 = ///< Flash Configuration Lock-Down +#define B_SPI_MEM_HSFSC_FDV BIT14 = ///< Flash Descriptor Valid, once valid software can use hareware sequencin= g regs +#define B_SPI_MEM_HSFSC_FDOPSS BIT13 = ///< Flash Descriptor Override Pin-Strap Status +#define B_SPI_MEM_HSFSC_PRR34_LOCKDN BIT12 = ///< PRR3 PRR4 Lock-Down +#define B_SPI_MEM_HSFSC_WRSDIS BIT11 = ///< Flash Write Status Register Disable +#define B_SPI_MEM_HSFSC_SAF_CE BIT8 = ///< SAF ctype error +#define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7 = ///< Indicates flash is attached either directly to the PCH via the SPI bus= or EC/BMC +#define B_SPI_MEM_HSFSC_SAF_LE BIT6 = ///< SAF link error +#define B_SPI_MEM_HSFSC_SCIP BIT5 = ///< SPI cycle in progress +#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 = ///< SAF Data length error +#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 = ///< SAF Error +#define B_SPI_MEM_HSFSC_AEL BIT2 = ///< Access Error Log +#define B_SPI_MEM_HSFSC_FCERR BIT1 = ///< Flash Cycle Error +#define B_SPI_MEM_HSFSC_FDONE BIT0 = ///< Flash Cycle Done +#define R_SPI_MEM_FADDR 0x08 = ///< SPI Flash Address +#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF = ///< SPI Flash Address Mask (0~26bit) +#define R_SPI_MEM_DLOCK 0x0C = ///< Discrete Lock Bits +#define B_SPI_MEM_DLOCK_PR0LOCKDN BIT8 = ///< PR0LOCKDN +#define R_SPI_MEM_FDATA00 0x10 = ///< SPI Data 00 (32 bits) +#define R_SPI_MEM_FDATA01 0x14 = ///< SPI Data 01 +#define R_SPI_MEM_FDATA02 0x18 = ///< SPI Data 02 +#define R_SPI_MEM_FDATA03 0x1C = ///< SPI Data 03 +#define R_SPI_MEM_FDATA04 0x20 = ///< SPI Data 04 +#define R_SPI_MEM_FDATA05 0x24 = ///< SPI Data 05 +#define R_SPI_MEM_FDATA06 0x28 = ///< SPI Data 06 +#define R_SPI_MEM_FDATA07 0x2C = ///< SPI Data 07 +#define R_SPI_MEM_FDATA08 0x30 = ///< SPI Data 08 +#define R_SPI_MEM_FDATA09 0x34 = ///< SPI Data 09 +#define R_SPI_MEM_FDATA10 0x38 = ///< SPI Data 10 +#define R_SPI_MEM_FDATA11 0x3C = ///< SPI Data 11 +#define R_SPI_MEM_FDATA12 0x40 = ///< SPI Data 12 +#define R_SPI_MEM_FDATA13 0x44 = ///< SPI Data 13 +#define R_SPI_MEM_FDATA14 0x48 = ///< SPI Data 14 +#define R_SPI_MEM_FDATA15 0x4C = ///< SPI Data 15 +#define R_SPI_MEM_FRAP 0x50 = ///< Flash Region Access Permisions Register +#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 = ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIO= S; 2: ME; 3: GbE; 4: PlatformData +#define N_SPI_MEM_FRAP_BRWA 8 = ///< BIOS Region Write Access bit position +#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF = ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS= ; 2: ME; 3: GbE; 4: PlatformData +#define B_SPI_MEM_FRAP_BMRAG_MASK 0x00FF0000 = ///< BIOS Master Read Access Grant +#define B_SPI_MEM_FRAP_BMWAG_MASK 0xFF000000 = ///< BIOS Master Write Access Grant +#define R_PCH_SPI_BM_RAP 0x118 = ///< SPI Flash BIOS Master Read Access Permissions +#define R_PCH_SPI_BM_WAP 0x11C = ///< SPI Flash BIOS Master Write Access Permissions +#define B_PCH_SPI_BM_AP_REG15 BIT15 = ///< Region read or write access for Region15 +#define B_PCH_SPI_BM_AP_PLATFORM BIT4 = ///< Region read or write access for Region4 PlatformData +#define B_PCH_SPI_BM_AP_GBE BIT3 = ///< Region read or write access for Region3 GbE +#define B_PCH_SPI_BM_AP_ME BIT2 = ///< Region read or write access for Region2 ME +#define B_PCH_SPI_BM_AP_BIOS BIT1 = ///< Region read or write access for Region1 BIOS +#define B_PCH_SPI_BM_AP_FLASHD BIT0 = ///< Region read or write access for Region0 Flash Descriptor +#define R_SPI_MEM_FREG0_FLASHD 0x54 = ///< Flash Region 0(Flash Descriptor)(32bits) +#define B_SPI_MEM_FREG0_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG0_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG0_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG0_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define B_SPI_MEM_FREG1_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG1_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG1_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG1_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define B_SPI_MEM_FREG2_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG2_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG2_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG2_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define B_SPI_MEM_FREG3_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG3_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG3_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG3_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define R_SPI_MEM_FREG1_BIOS 0x58 = ///< Flash Region 1(BIOS)(32bits) +#define R_SPI_MEM_FREG2_ME 0x5C = ///< Flash Region 2(ME)(32bits) +#define R_SPI_MEM_FREG3_GBE 0x60 = ///< Flash Region 3(GbE)(32bits) +#define R_SPI_MEM_FREG4_PLATFORM_DATA 0x64 = ///< Flash Region 4(Platform Data)(32bits) +#define B_SPI_MEM_FREG4_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG4_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG4_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG4_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define R_SPI_MEM_FREG5_DER 0x68 = ///< Flash Region 5(Device Expansion Region)(32bits) +#define R_SPI_MEM_FREG6_SECONDARY_BIOS 0x6C = ///< Flash Region 6(Secondary BIOS)(32bits) +#define R_PCH_SPI_FREG7_UCODE_PATCH 0x70 = ///< Flash Region 7(uCode Patch)(32bits) +#define R_PCH_SPI_FREG12 0xE0 = ///< Flash Region 12(32bits) +#define R_PCH_SPI_FREG15 0xEC = ///< Flash Region 15 (32bits) +#define B_SPI_MEM_FREG15_LIMIT_MASK 0x7FFF0000 = ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_MEM_FREG15_LIMIT 4 = ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_MEM_FREG15_BASE_MASK 0x00007FFF = ///< Base, [14:0] here represents base [26:12] +#define N_SPI_MEM_FREG15_BASE 12 = ///< Bit 14:0 identifies address bits [26:2] +#define S_SPI_MEM_FREGX 4 = ///< Size of Flash Region register +#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 = ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to b= e FFFh +#define N_SPI_MEM_FREGX_LIMIT 16 = ///< Region limit bit position +#define N_SPI_MEM_FREGX_LIMIT_REPR 12 = ///< Region limit bit represents position +#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF = ///< Flash Region Base, [14:0] represents [26:12] +#define N_SPI_MEM_FREGX_BASE 0 = ///< Region base bit position +#define N_SPI_MEM_FREGX_BASE_REPR 12 = ///< Region base bit represents position +#define R_SPI_MEM_PR0 0x84 = ///< Protected Region 0 Register +#define R_SPI_MEM_PR1 0x88 = ///< Protected Region 1 Register +#define R_SPI_MEM_PR2 0x8C = ///< Protected Region 2 Register +#define R_SPI_MEM_PR3 0x90 = ///< Protected Region 3 Register +#define R_SPI_MEM_PR4 0x94 = ///< Protected Region 4 Register +#define S_SPI_MEM_PRX 4 = ///< Protected Region X Register size +#define B_SPI_MEM_PRX_WPE BIT31 = ///< Write Protection Enable +#define B_SPI_MEM_PRX_PRL_MASK 0x7FFF0000 = ///< Protected Range Limit Mask, [30:16] here represents upper limit of add= ress [26:12] +#define N_SPI_MEM_PRX_PRL 16 = ///< Protected Range Limit bit position +#define B_SPI_MEM_PRX_RPE BIT15 = ///< Read Protection Enable +#define B_SPI_MEM_PRX_PRB_MASK 0x00007FFF = ///< Protected Range Base Mask, [14:0] here represents base limit of addres= s [26:12] +#define N_SPI_MEM_PRX_PRB 0 = ///< Protected Range Base bit position +#define R_SPI_MEM_SFRAP 0xB0 = ///< Secondary Flash Regions Access Permisions Register +#define R_SPI_MEM_FDOC 0xB4 = ///< Flash Descriptor Observability Control Register(32 bits) +#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) = ///< Flash Descritor Section Select +#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 = ///< Flash Signature and Descriptor Map +#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 = ///< Component +#define V_SPI_MEM_FDOC_FDSS_REGN 0x2000 = ///< Region +#define V_SPI_MEM_FDOC_FDSS_MSTR 0x3000 = ///< Master +#define V_SPI_MEM_FDOC_FDSS_PCHS 0x4000 = ///< PCH soft straps +#define V_SPI_MEM_FDOC_FDSS_SFDP 0x5000 = ///< SFDP Parameter Table +#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC = ///< Flash Descriptor Section Index +#define R_SPI_MEM_FDOD 0xB8 = ///< Flash Descriptor Observability Data Register(32 bits) +#define R_SPI_MEM_SFDP0_VSCC0 0xC4 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_SPI_MEM_SFDPX_VSCCX_CPPTV BIT31 = ///< Component Property Parameter Table Valid +#define B_SPI_MEM_SFDP0_VSCC0_VCL BIT30 = ///< Vendor Component Lock +#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 = ///< 64k Erase valid (EO_64k_valid) +#define B_SPI_MEM_SFDPX_VSCCX_EO_4K BIT28 = ///< 4k Erase valid (EO_4k_valid) +#define B_SPI_MEM_SFDPX_VSCCX_RPMC BIT27 = ///< RPMC Supported +#define B_SPI_MEM_SFDPX_VSCCX_DPD BIT26 = ///< Deep Powerdown Supported +#define B_SPI_MEM_SFDPX_VSCCX_SUSRES BIT25 = ///< Suspend/Resume Supported +#define B_SPI_MEM_SFDPX_VSCCX_SOFTRES BIT24 = ///< Soft Reset Supported +#define B_SPI_MEM_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 = ///< 64k Erase Opcode (EO_64k) +#define B_SPI_MEM_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 = ///< 4k Erase Opcode (EO_4k) +#define B_SPI_MEM_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) = ///< Quad Enable Requirements +#define B_SPI_MEM_SFDPX_VSCCX_WEWS BIT4 = ///< Write Enable on Write Status +#define B_SPI_MEM_SFDPX_VSCCX_WSR BIT3 = ///< Write Status Required +#define B_SPI_MEM_SFDPX_VSCCX_WG_64B BIT2 = ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define R_SPI_MEM_SFDP1_VSCC1 0xC8 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define R_SPI_MEM_PINTX 0xCC = ///< Parameter Table Index +#define N_SPI_MEM_PINTX_SPT 14 +#define V_SPI_MEM_PINTX_SPT_CPT0 0x0 = ///< Component 0 Property Parameter Table +#define V_SPI_MEM_PINTX_SPT_CPT1 0x1 = ///< Component 1 Property Parameter Table +#define N_SPI_MEM_PINTX_HORD 12 +#define V_SPI_MEM_PINTX_HORD_SFDP 0x0 = ///< SFDP Header +#define V_SPI_MEM_PINTX_HORD_PT 0x1 = ///< Parameter Table Header +#define V_SPI_MEM_PINTX_HORD_DATA 0x2 = ///< Data +#define R_SPI_MEM_PTDATA 0xD0 = ///< Parameter Table Data +#define R_SPI_MEM_SBRS 0xD4 = ///< SPI Bus Requester Status +#define R_PCH_SPI_SSML 0xF0 = ///< Set Strap Msg Lock +#define B_PCH_SPI_SSML_SSL BIT0 = ///< Set_Strap Lock +#define R_PCH_SPI_SSMC 0xF4 = ///< Set Strap Msg Control +#define B_PCH_SPI_SSMC_SSMS BIT0 = ///< Set_Strap Mux Select +#define R_PCH_SPI_SSMD 0xF8 = ///< Set Strap Msg Data +// +// @todo Follow up with EDS owner if it should be 3FFF or FFFF. +// +#define B_SPI_MEM_SRD_SSD 0x0000FFFF = ///< Set_Strap Data +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_SPI_FLASH_FDBAR_FLVALSIG 0x00 = ///< Flash Valid Signature +#define V_SPI_FLASH_FDBAR_FLVALSIG 0x0FF0A55A +#define R_SPI_FLASH_FDBAR_FLASH_MAP0 0x04 +#define B_SPI_FLASH_FDBAR_FCBA 0x000000FF = ///< Flash Component Base Address +#define B_SPI_FLASH_FDBAR_NC 0x00000300 = ///< Number Of Components +#define N_SPI_FLASH_FDBAR_NC 8 = ///< Number Of Components +#define V_SPI_FLASH_FDBAR_NC_1 0x00000000 +#define V_SPI_FLASH_FDBAR_NC_2 0x00000100 +#define B_SPI_FLASH_FDBAR_FRBA 0x00FF0000 = ///< Flash Region Base Address +#define B_SPI_FLASH_FDBAR_NR 0x07000000 = ///< Number Of Regions +#define R_SPI_FLASH_FDBAR_FLASH_MAP1 0x08 +#define B_SPI_FLASH_FDBAR_FMBA 0x000000FF = ///< Flash Master Base Address +#define B_SPI_FLASH_FDBAR_NM 0x00000700 = ///< Number Of Masters +#define B_SPI_FLASH_FDBAR_FPSBA 0x00FF0000 = ///< PCH Strap Base Address, [23:16] represents [11:4] +#define N_SPI_FLASH_FDBAR_FPSBA 16 = ///< PCH Strap base Address bit position +#define N_SPI_FLASH_FDBAR_FPSBA_REPR 4 = ///< PCH Strap base Address bit represents position +#define B_SPI_FLASH_FDBAR_PCHSL 0xFF000000 = ///< PCH Strap Length, [31:24] represents number of Dwords +#define R_SPI_MEM_FDBAR_FLASH_MAP1_RW 0x18 = ///< For Use With FlashRead() and FlashWrite() +#define N_SPI_FLASH_FDBAR_PCHSL 24 = ///< PCH Strap Length bit position +#define R_SPI_FLASH_FDBAR_FLASH_MAP2 0x0C +#define B_SPI_FLASH_FDBAR_FCPUSBA 0x000000FF = ///< CPU Strap Base Address, [7:0] represents [11:4] +#define N_SPI_FLASH_FDBAR_FCPUSBA 0 = ///< CPU Strap Base Address bit position +#define N_SPI_FLASH_FDBAR_FCPUSBA_REPR 4 = ///< CPU Strap Base Address bit represents position +#define B_SPI_FLASH_FDBAR_CPUSL 0x0000FF00 = ///< CPU Strap Length, [15:8] represents number of Dwords +#define N_SPI_FLASH_FDBAR_CPUSL 8 = ///< CPU Strap Length bit position +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_SPI_FLASH_FCBA_FLCOMP 0x00 = ///< Flash Components Register +#define B_SPI_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) = ///< Read ID and Read Status Clock Frequency +#define B_SPI_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) = ///< Write and Erase Clock Frequency +#define B_SPI_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) = ///< Fast Read Clock Frequency +#define B_SPI_FLASH_FLCOMP_FR_SUP BIT20 = ///< Fast Read Support. +#define B_SPI_FLASH_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) = ///< Read Clock Frequency. +#define V_SPI_FLASH_FLCOMP_FREQ_48MHZ 0x02 +#define V_SPI_FLASH_FLCOMP_FREQ_30MHZ 0x04 +#define V_SPI_FLASH_FLCOMP_FREQ_17MHZ 0x06 +#define B_SPI_FLASH_FLCOMP_COMP1_MASK 0xF0 = ///< Flash Component 1 Size MASK +#define N_SPI_FLASH_FLCOMP_COMP1 4 = ///< Flash Component 1 Size bit position +#define B_SPI_FLASH_FLCOMP_COMP0_MASK 0x0F = ///< Flash Component 0 Size MASK +#define V_SPI_FLASH_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_SPI_FLASH_UMAP1 0xEFC ///<= Flash Upper Map 1 +#define B_SPI_FLASH_UMAP1_VTBA 0x000000FF ///<= VSCC Table Base Address +#define B_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///<= VSCC Table Length + +#define R_SPI_MEM_VTBA_JID0 0x00 = ///< JEDEC-ID 0 Register +#define S_SPI_MEM_VTBA_JID0 0x04 +#define B_SPI_MEM_VTBA_JID0_VID 0x000000FF +#define B_SPI_MEM_VTBA_JID0_DID0 0x0000FF00 +#define B_SPI_MEM_VTBA_JID0_DID1 0x00FF0000 +#define N_SPI_MEM_VTBA_JID0_DID0 0x08 +#define N_SPI_MEM_VTBA_JID0_DID1 0x10 +#define R_SPI_MEM_VTBA_VSCC0 0x04 +#define S_SPI_MEM_VTBA_VSCC0 0x04 + +#define R_PCH_PCR_SPI_CONF_VALUE 0xC00C +#define B_ESPI_ENABLE_STRAP BIT0 + +// +// SPI Private Configuration Space Registers +// +#define R_SPI_PCR_CLK_CTL 0xC004 +#define R_SPI_PCR_PWR_CTL 0xC008 + +// +// MMP0 +// +#define R_SPI_MEM_STRP_MMP0 0xC4 ///< MMP0 Soft strap o= ffset +#define B_SPI_MEM_STRP_MMP0 0x10 ///< MMP0 Soft strap b= it + + +#define R_SPI_MEM_STRP_SFDP 0xF0 ///< PCH Soft Strap SF= DP +#define B_SPI_MEM_STRP_SFDP_QIORE BIT3 = ///< Quad IO Read Enable +#define B_SPI_MEM_STRP_SFDP_QORE BIT2 = ///< Quad Output Read Enable +#define B_SPI_MEM_STRP_SFDP_DIORE BIT1 = ///< Dual IO Read Enable +#define B_SPI_MEM_STRP_SFDP_DORE BIT0 = ///< Dual Output Read Enable + +// +// Descriptor Record 0 +// +#define R_SPI_MEM_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0 +#define B_SPI_MEM_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported + +#define R_PCH_SPI_SS119_PMC 0x1DC = ///< PCH soft strap 119 - PMC +#define B_PCH_SPI_SS119_PMC_GBE_DIS BIT14 = ///< PCH soft strap 119 - GbE Disable +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsThermal.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterL= bg/Include/Register/PchRegsThermal.h new file mode 100644 index 0000000000..97faa15255 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsThermal.h @@ -0,0 +1,113 @@ +/** @file + Register names for PCH Thermal Device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D20:2) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 20 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2 +#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_THERMAL_DEVICE_ID 0x8C24 + +// +// LBG Production Thermal Device Device ID +// +#define V_PCH_LBG_PROD_THERMAL_DEVICE_ID 0xA1B1 +// +// LBG SSX (Super SKU) Thermal Device Device ID +// +#define V_PCH_LBG_THERMAL_DEVICE_ID 0xA231 + +#define V_PCH_LP_THERMAL_DEVICE_ID 0x9C24 +#define R_PCH_THERMAL_TBAR 0x10 +#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBAR_ALIGNMENT 12 +#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000 +#define R_PCH_THERMAL_TBARH 0x14 +#define R_PCH_THERMAL_TBARB 0x40 +#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBARB_ALIGNMENT 12 +#define B_PCH_THERMAL_SPTYPEN BIT0 +#define R_PCH_THERMAL_TBARBH 0x44 +#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000 + +// +// Thermal TBAR MMIO registers +// +#define R_PCH_TBAR_TSC 0x04 +#define B_PCH_TBAR_TSC_PLD BIT7 +#define B_PCH_TBAR_TSC_CPDE BIT0 +#define R_PCH_TBAR_TSS 0x06 +#define R_PCH_TBAR_TSEL 0x08 +#define B_PCH_TBAR_TSEL_PLD BIT7 +#define B_PCH_TBAR_TSEL_ETS BIT0 +#define R_PCH_TBAR_TSREL 0x0A +#define R_PCH_TBAR_TSMIC 0x0C +#define B_PCH_TBAR_TSMIC_PLD BIT7 +#define B_PCH_TBAR_TSMIC_SMIE BIT0 +#define R_PCH_TBAR_CTT 0x10 +#define R_PCH_TBAR_TAHV 0x14 +#define R_PCH_TBAR_TALV 0x18 +#define R_PCH_TBAR_TSPM 0x1C +#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 = | BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_TBAR_TSPM_LTT 0x0C8 +#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9) +#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9) +#define B_PCH_TBAR_TSPM_MINTSST BIT12 +#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13 +#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14 +#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15 +#define R_PCH_TBAR_TL 0x40 +#define B_PCH_TBAR_TL_LOCK BIT31 +#define B_PCH_TBAR_TL_TTEN BIT29 +#define R_PCH_TBAR_TL2 0x50 +#define R_PCH_TBAR_TL2_LOCK BIT15 +#define R_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_PHL 0x60 +#define B_PCH_TBAR_PHLE BIT15 +#define R_PCH_TBAR_PHLC 0x62 +#define B_PCH_TBAR_PHLC_LOCK BIT0 +#define R_PCH_TBAR_TAS 0x80 +#define R_PCH_TBAR_TSPIEN 0x82 +#define R_PCH_TBAR_TSGPEN 0x84 +#define B_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_A4 0xA4 +#define R_PCH_TBAR_C0 0xC0 +#define R_PCH_TBAR_C4 0xC4 +#define R_PCH_TBAR_C8 0xC8 +#define R_PCH_TBAR_CC 0xCC +#define R_PCH_TBAR_D0 0xD0 +#define R_PCH_TBAR_E0 0xE0 +#define R_PCH_TBAR_E4 0xE4 +#define R_PCH_TBAR_E8 0xE8 +#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal c= ontroller function disable +#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal c= ontroller disable + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsTraceHub.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthCluster= Lbg/Include/Register/PchRegsTraceHub.h new file mode 100644 index 0000000000..87d0f2cb34 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsTraceHub.h @@ -0,0 +1,147 @@ +/** @file + Register names for PCH TraceHub device + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_TRACE_HUB_H_ +#define _PCH_REGS_TRACE_HUB_H_ + +// +// TraceHub Registers (D31:F7) +// +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31 +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7 + +#define V_PCH_TRACE_HUB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_TRACE_HUB_DEVICE_ID 0x0963 + +// +// LBG Production (PRQ) TraceHub Device ID +// +#define V_PCH_LBG_PROD_TRACE_HUB_DEVICE_ID 0xA1A6 +// +// LBG SuperSKU (SSX) TraceHub Device ID +// +#define V_PCH_LBG_TRACE_HUB_DEVICE_ID 0xA226 + +#define R_TRACE_HUB_CFG_CSR_MTB_LBAR 0x10 +#define B_TRACE_HUB_CFG_CSR_MTB_RBAL 0xFFF00000 +#define R_TRACE_HUB_CFG_CSR_MTB_UBAR 0x14 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_SW_LBAR 0x18 +#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000 +#define R_PCH_TRACE_HUB_SW_UBAR 0x1C +#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20 +#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00 +#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24 +#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_MSICID 0x40 +#define R_PCH_TRACE_HUB_MSINCP 0x41 +#define R_PCH_TRACE_HUB_MSIMC 0x42 +#define R_PCH_TRACE_HUB_MSILMA 0x44 +#define R_PCH_TRACE_HUB_MSIUMA 0x48 +#define R_PCH_TRACE_HUB_MSIMD 0x4C +#define R_PCH_TRACE_HUB_FW_LBAR 0x70 +#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000 +#define R_PCH_TRACE_HUB_FW_UBAR 0x74 +#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_DSC 0x80 +#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub By= pass +#define R_PCH_TRACE_HUB_DSS 0x81 +#define R_PCH_TRACE_HUB_ISTOT 0x84 +#define R_PCH_TRACE_HUB_ICTOT 0x88 +#define R_PCH_TRACE_HUB_IPAD 0x8C +#define R_PCH_TRACE_HUB_DSD 0x90 + +// +// Offsets from CSR_MTB_BAR +// +#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15 +#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A +#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08 +#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00 +#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0 +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10 +#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F +#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14 +#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18 +#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100 +#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3 +#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8) +#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4) +#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4 +#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2 +#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1 +#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0 +#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4 +#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8 +#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7 +#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108 +#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C +#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208 +#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C +#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000 +#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28 +#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00 +#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0 +#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16) +#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT= 20) +#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0 +#define R_PCH_TRACE_HUB_MTB_SCR 0xC8 +#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC +#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40 +#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14 +#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0 +#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80 +#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20 +#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000 +#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Re= gister/PchRegsUsb.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Register/PchRegsUsb.h new file mode 100644 index 0000000000..6ae9ec1640 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/= PchRegsUsb.h @@ -0,0 +1,529 @@ +/** @file + Register names for PCH USB devices + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + In general, PCH registers are denoted by "_PCH_" in register names + Registers / bits that are different between PCH generations are denoted = by + _PCH_[generation_name]_" in register/bit names. + Registers / bits that are specific to PCH-H denoted by "_H_" in register= /bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regist= er/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + Registers / bits that are different between SKUs are denoted by "_[SKU_n= ame]" + at the end of the register/bit names + Registers / bits of new devices introduced in a PCH generation will be j= ust named + as "_PCH_" without [generation_name] inserted. + + @copyright + Copyright 1999 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +// +// USB3 (XHCI) related definitions +// +#define PCI_BUS_NUMBER_PCH_XHCI 0 +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// XHCI PCI Config Space registers +// +#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_USB_DEVICE_ID_XHCI_1 0x8C31 ///< SKL PCH H XHCI#1 +// +// LBG Production (PRQ) XHCI Controller Device ID +// +#define V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1 0xA1AF ///< LBG Production DI= D XHCI#1 +// +// LBG Super SKU (SSX) XHCI Controller Device ID +// +#define V_PCH_LBG_USB_DEVICE_ID_XHCI_1 0xA22F ///< LBG Super SKU DID= XHCI#1 +#define V_PCH_LP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< SKL PCH LP XHCI#1 + +#define B_PCH_XHCI_CMD_PER BIT6 // PCI_COMMAND_OFFSET= , Parity Error Response +#define B_PCH_XHCI_CMD_SERR BIT8 // PCI_COMMAND_OFFSET= , SERR# Enable + +#define R_XHCI_CFG_BAR0 0x10 +#define V_PCH_XHCI_MEM_LENGTH 0x10000 +#define N_PCH_XHCI_MEM_ALIGN 16 +#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF + +#define R_PCH_XHCI_XHCC1 0x40 +#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 +#define B_PCH_XHCI_XHCC1_RMTASERR BIT24 +#define B_PCH_XHCI_XHCC1_URD BIT23 +#define B_PCH_XHCI_XHCC1_URRE BIT22 +#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 +#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 +#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 +#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13= | BIT12) +#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 +#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) +#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) +#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) +#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) + +#define R_PCH_XHCI_XHCC2 0x44 +#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 +#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT21 +#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 +#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) +#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) +#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) + +#define R_PCH_XHCI_XHCLKGTEN 0x50 +#define B_PCH_XHCI_XHCLKGTEN_SRAMPGTEN BIT27 +#define N_PCH_XHCI_XHCLKGTEN_HSTCGE 20 +#define V_PCH_XHCI_XHCLKGTEN_HSTCGE 0xC +#define N_PCH_XHCI_XHCLKGTEN_SSTCGE 16 +#define V_PCH_XHCI_XHCLKGTEN_SSTCGE 0xE +#define N_PCH_XHCI_XHCLKGTEN_HSPLLSU 8 +#define V_PCH_XHCI_XHCLKGTEN_HSPLLSU 0x2 +#define N_PCH_XHCI_XHCLKGTEN_SSPLLSUE 5 +#define V_PCH_XHCI_XHCLKGTEN_SSPLLSUE 0x2 +#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 +#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 +#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 +#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 +#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 +#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 +#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 +#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) +#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) +#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) +#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 +#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 +#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 +#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 +#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 + +#define R_PCH_XHCI_USB_RELNUM 0x60 +#define B_PCH_XHCI_USB_RELNUM 0xFF +#define R_PCH_XHCI_FL_ADJ 0x61 +#define B_PCH_XHCI_FL_ADJ 0x3F +#define R_PCH_XHCI_PWR_CAPID 0x70 +#define B_PCH_XHCI_PWR_CAPID 0xFF +#define R_PCH_XHCI_NXT_PTR1 0x71 +#define B_PCH_XHCI_NXT_PTR1 0xFF +#define R_PCH_XHCI_PWR_CAP 0x72 +#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_XHCI_PWR_CAP_DSI BIT5 +#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) +#define R_PCH_XHCI_MSI_MCTL 0x82 +#define R_PCH_XHCI_U2OCM 0xB0 +#define R_PCH_XHCI_U3OCM 0xD0 +#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8 + +#define R_PCH_XHCI_FUS 0xE0 +#define B_PCH_XHCI_FUS_USBR (BIT5) +#define V_PCH_XHCI_FUS_USBR_EN 0 +#define V_PCH_XHCI_FUS_USBR_DIS (BIT5) + +#define R_PCH_XHCI_FC 0xFC + +#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) +#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) + +#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) +#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) + +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 + +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF + +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F + +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF + +// +// xHCI MMIO registers +// + +// +// 0x00 - 0x1F - Capability Registers +// +#define R_PCH_XHCI_CAPLENGTH 0x00 +#define R_PCH_XHCI_HCIVERSION 0x02 +#define R_PCH_XHCI_HCSPARAMS1 0x04 +#define R_PCH_XHCI_HCSPARAMS2 0x08 +#define R_PCH_XHCI_HCSPARAMS3 0x0C +#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 +#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF +#define R_PCH_XHCI_HCCPARAMS 0x10 +#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 +#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 +#define R_PCH_XHCI_DBOFF 0x14 +#define R_PCH_XHCI_RTSOFF 0x18 + +// +// 0x80 - 0xBF - Operational Registers +// +#define R_PCH_XHCI_USBCMD 0x80 +#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop +#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST +#define B_PCH_XHCI_USBCMD_HSEE BIT3 //Host System Error Ena= ble +#define R_PCH_XHCI_USBSTS 0x84 +#define B_PCH_XHCI_USBSTS_HCH BIT0 +#define B_PCH_XHCI_USBSTS_CNR BIT11 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_LP_XHCI_PORTSC01USB2 0x480 +#define R_PCH_LP_XHCI_PORTSC02USB2 0x490 +#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_LP_XHCI_PORTSC09USB2 0x500 +#define R_PCH_LP_XHCI_PORTSC10USB2 0x510 + +#define R_PCH_LP_XHCI_PORTSC13USBR 0x520 +#define R_PCH_LP_XHCI_PORTSC14USBR 0x530 + +#define R_PCH_LP_XHCI_PORTSC01USB3 0x540 +#define R_PCH_LP_XHCI_PORTSC02USB3 0x550 +#define R_PCH_LP_XHCI_PORTSC03USB3 0x560 +#define R_PCH_LP_XHCI_PORTSC04USB3 0x570 +#define R_PCH_LP_XHCI_PORTSC05USB3 0x580 +#define R_PCH_LP_XHCI_PORTSC06USB3 0x590 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_H_XHCI_PORTSC01USB2 0x480 +#define R_PCH_H_XHCI_PORTSC02USB2 0x490 +#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_H_XHCI_PORTSC09USB2 0x500 +#define R_PCH_H_XHCI_PORTSC10USB2 0x510 +#define R_PCH_H_XHCI_PORTSC11USB2 0x520 +#define R_PCH_H_XHCI_PORTSC12USB2 0x530 +#define R_PCH_H_XHCI_PORTSC13USB2 0x540 +#define R_PCH_H_XHCI_PORTSC14USB2 0x550 + +#define R_PCH_H_XHCI_PORTSC15USBR 0x560 +#define R_PCH_H_XHCI_PORTSC16USBR 0x570 + +#define R_PCH_H_XHCI_PORTSC01USB3 0x580 +#define R_PCH_H_XHCI_PORTSC02USB3 0x590 +#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0 +#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0 +#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0 +#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0 +#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0 +#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0 +#define R_PCH_H_XHCI_PORTSC09USB3 0x600 +#define R_PCH_H_XHCI_PORTSC10USB3 0x610 + +#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_WDE BIT26 ///< Wake on Disconnect= Enable +#define B_PCH_XHCI_PORTSCXUSB2_WCE BIT25 ///< Wake on Connect En= able +#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error = Change +#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Ch= ange +#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Ch= ange +#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disab= led Change +#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Cha= nge +#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Wr= ite Strobe +#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 +#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) /= //< Port Link State +#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabl= ed +#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect St= atus +#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | = B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSC= XUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH= _XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) +#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31= ) ///< Port Test Control + +#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_WDE BIT26 ///< Wake on Disconnect= Enable +#define B_PCH_XHCI_PORTSCXUSB3_WCE BIT25 ///< Wake on Connect En= able +#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error = Change +#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Ch= ange +#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Ch= ange +#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disab= led Change +#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Cha= nge +#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power +#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) = ///< Port Link State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in = the Polling State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in = the RxDetect State +#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabl= ed +#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3= _CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI= _PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC = | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) +// +// 0x2000 - 0x21FF - Runtime Registers +// 0x3000 - 0x307F - Doorbell Registers +// + + +#define R_PCH_XHCI_PCE 0xA2 +#define R_PCH_XHCI_HSCFG2 0xA4 +#define R_PCH_XHCI_SSCFG1 0xA8 +#define R_PCH_XHCI_HSCFG1 0xAC + +#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008 +#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028 +#define R_PCH_XHCI_HOST_CTRL_TRM_REG 0x8090 +#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094 +#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C +#define R_PCH_XHCI_PMCTRL 0x80A4 +#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control +#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controll= er Misc Reg +#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controll= er Misc Reg 2 +#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed P= ort Enables +#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for = 6 USB3 ports +#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 1= 0 USB3 ports +#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8 +#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC +#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0 +#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Po= rt Link Control +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manag= er Control 1 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manag= er Control 2 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manag= er Control 3 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR= _CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM= _REG2 - Host Controller Transfer Manager Control 2 +#define R_PCH_XHCI_HOST_CTRL_BW_MAX_REG_DW1 0x8128 ///< HOST_CTRL_BW_= MAX_REG - MAX BW Control Reg 4 +#define R_PCH_XHCI_HOST_CTRL_BW_MAX_REG_DW2 0x812C ///< HOST_CTRL_BW_= MAX_REG - MAX BW Control Reg 4 +#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2= - Aux PM Control Register 2 +#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Cloc= k Control Register +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_C= TRL_REG0 - Power Scheduler Control 0 +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_C= TRL_REG1 - Power Scheduler Control 1 +#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency T= olerance Parameters - LTV Control +#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency T= olerance Parameters - High Idle Time Control +#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency T= olerance Parameters - Medium Idle Time Control +#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency T= olerance Parameters - Low Idle Time Control +#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Powe= r Management Control +#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown = Disable Control +#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle= Control +#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Contr= ol +#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle +#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count +#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control = Register +#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Ma= nagement Control + +// +// SKL PCH LP FUSE +// +#define R_PCH_XHCI_LP_FUSE1 0x8410 +#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1) +#define B_PCH_XHCI_LP_FUS_USBR (BIT5) +#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Str= ap +#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Su= pport Control Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR St= atus +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Co= mmand Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Own= ership Change Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR En= able +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Co= mmand Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Own= ership Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host S= ystem Error Enable +#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable + +// +// Extended Capability Registers +// +#define R_PCH_XHCI_USB2PDO 0x84F8 +#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for = 10 USB2 ports +#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 1= 4 USB2 ports +#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 + +#define R_PCH_XHCI_USB3PDO 0x84FC +#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for = 6 USB3 ports +#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 1= 0 USB3 ports +#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 + +// +// Debug Capability Descriptor Parameters +// +#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - Db= C Control + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +#define V_PCH_XDCI_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_XDCI_DEVICE_ID 0x9D30 + +// +// LBG Pruduction (PRQ) xDCI (OTG) USB Device Controller Device ID +// +#define V_PCH_LBG_PROD_XDCI_DEVICE_ID 0xA1B0 +// +// LBG SuperSKU (SSX) xDCI (OTG) USB Device Controller Device ID +// +#define V_PCH_LBG_XDCI_DEVICE_ID 0xA230 + +// +// xDCI (OTG) PCI Config Space Registers +// +#define R_PCH_XDCI_MEM_BASE 0x10 +#define V_PCH_XDCI_MEM_LENGTH 0x200000 +#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management = Control and Status Register +#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose P= CI RW Register1 +#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gat= e Enable +#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose P= CI RW Register4 +#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Reg= ister + +// +// xDCI (OTG) MMIO registers +// +#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl +#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation ena= ble +#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY= Configuration Register +#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 = HS/FS/LS PHY +#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIP= E Control Register 0 +#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px +#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810 +#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818 + +// +// xDCI (OTG) Private Configuration Registers +// (PID:OTG) +// +#define R_PCH_PCR_OTG_IOSF_A2 0xA2 +#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0 +#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20 +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00 +#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8 +#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080 +#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001 + +// +// USB2 Private Configuration Registers +// USB2 HIP design featured +// (PID:USB2) +// +#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL P= ORT +#define R_PCH_PCR_USB2_400C 0x400C +#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base = address +#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT= Addr[7:2] =3D 0x00 +#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG= PER PORT Addr[7:2] =3D 0x08 +#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT= 2 Addr[7:2] =3D 0x26 +#define R_PCH_PCR_USB2_402A 0x402A +#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS = REG +#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL P= ORT 2 +#define R_PCH_PCR_USB2_PLLDIVRATIOS_0 0x7000 +#define R_PCH_PCR_USB2_SFRCONFIG_0 0x702C +#define R_PCH_PCR_USB2_CONFIG_0 0x7008 +#define R_PCH_PCR_USB2_CONFIG_3 0x7014 +#define R_PCH_PCR_USB2_DFT_1 0x7024 +#define R_PCH_PCR_USB2_7034 0x7034 +#define R_PCH_PCR_USB2_7038 0x7038 +#define R_PCH_PCR_USB2_703C 0x703C +#define R_PCH_PCR_USB2_7040 0x7040 +#define R_PCH_PCR_USB2_7044 0x7044 +#define R_PCH_PCR_USB2_7048 0x7048 +#define R_PCH_PCR_USB2_704C 0x704C +#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG + +// +// xHCI SSIC registers +// +#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global C= onfiguration Control +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configur= ation Register 1 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configur= ation Register 2 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configur= ation Register 3 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configur= ation Register 1 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configur= ation Register 2 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configur= ation Register 3 Port 2 +#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31 +#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attri= butes: Port 1 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N R= egister Access Control: Port 1 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attri= butes: Port 2 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N R= egister Access Control: Port 2 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38 + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 12 Jul 2021 17:42:01 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456218" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456218" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422938" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:49 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 06/17] WhitleySiliconPkg: Add PCH Includes Date: Mon, 12 Jul 2021 17:41:20 -0700 Message-Id: <20210713004131.1782-7-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: YOvDJcDupKYXM9O1I71ARnLNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136922; bh=WI1aq/mIYqn/0XrjTh1hAiVjy1LE9kbdfzXnbN9Mj74=; h=Cc:Date:From:Reply-To:Subject:To; b=eyKg5Jp4pvlS2zg2c33xPVuSz6lpwAeiT1y++F4/N/v2/nonM8G9L3aFIIqADeu/rJd knqIucNp6GNsjJ5MBjSB4lCbWnII4OnWPg9P2J5AKjMqXIuEAC1eSX0jOv8BK7yt1+rq1 4PY9mQq/IwfNDeafRLtYYgyB0q8zly+c5lA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136923671100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../SouthClusterLbg/Include/GpioPinsSklH.h | 300 +++ .../SouthClusterLbg/Include/Library/GpioLib.h | 1016 ++++++++ .../Include/Library/PchMultiPchBase.h | 37 + .../Include/Library/PchPcieRpLib.h | 145 ++ .../Pch/SouthClusterLbg/Include/PchAccess.h | 629 +++++ .../Pch/SouthClusterLbg/Include/PchLimits.h | 108 + .../SouthClusterLbg/Include/PchPolicyCommon.h | 2161 +++++++++++++++++ .../Include/PchReservedResources.h | 82 + .../Pch/SouthClusterLbg/Include/PcieRegs.h | 288 +++ .../Include/Ppi/PchHsioPtssTable.h | 31 + .../Include/Ppi/PchPcieDeviceTable.h | 126 + .../SouthClusterLbg/Include/Ppi/PchPolicy.h | 23 + .../SouthClusterLbg/Include/Ppi/PchReset.h | 95 + .../Pch/SouthClusterLbg/Include/Ppi/Spi.h | 28 + .../Include/Private/Library/PchSpiCommonLib.h | 458 ++++ .../Include/Protocol/PchReset.h | 114 + .../SouthClusterLbg/Include/Protocol/Spi.h | 305 +++ 17 files changed, 5946 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/GpioPinsSklH.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Library/GpioLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Library/PchMultiPchBase.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Library/PchPcieRpLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/PchAccess.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/PchLimits.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/PchPolicyCommon.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/PchReservedResources.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/PcieRegs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Ppi/PchHsioPtssTable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Ppi/PchPcieDeviceTable.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Ppi/PchPolicy.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Ppi/PchReset.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Ppi/Spi.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Private/Library/PchSpiCommonLib.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Protocol/PchReset.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Protocol/Spi.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Gp= ioPinsSklH.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/= GpioPinsSklH.h new file mode 100644 index 0000000000..79d6e73dc4 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsS= klH.h @@ -0,0 +1,300 @@ +/** @file + GPIO pins for SKL-PCH-H, + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// SKL H GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Li= brary/GpioLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inclu= de/Library/GpioLib.h new file mode 100644 index 0000000000..17b433ac78 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/G= pioLib.h @@ -0,0 +1,1016 @@ +/** @file + Header file for GpioLib. + All function in this library is available for PEI, DXE, and SMM + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include +#include + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those in= clude: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... = n - Non-Legacy PCH) + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePadsByPchId ( + IN UINT8 PchId, + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those in= clude: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... = n - Non-Legacy PCH) + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfigByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... = n - Non-Legacy PCH) + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfigByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValueByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + + /** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversionByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversionByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost =3D 0x0, + GpioPadOwnCsme =3D 0x1, + GpioPadOwnIsh =3D 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN UINT8 PchId, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN UINT8 PchId, + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN UINT8 PchId, + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected = GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiStsByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +// +// Extended interface for Server RAS usage +// +/** + This procedure is used to get SMI STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] SmiStsReg Smi status register for given pad + The bit position is set for given Pad nu= mber + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiStsByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT BOOLEAN *SmiSts + ); + +/** + This procedure is used to get SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] SmiStsReg Smi status register for given pad + The bit position is set for given Pad nu= mber + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiSts ( + IN GPIO_PAD GpioPad, + OUT BOOLEAN *SmiSts + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + IN UINT8 PchId + ); + +/** + This procedure is used to disable all GPI SMI + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + IN UINT8 PchId + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNumByPchId ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO = pad + configuration is changed. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + IN UINT8 PchId + ); + +/** + Unlocks all PCH GPIO pads + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + IN UINT8 PchId + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Li= brary/PchMultiPchBase.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterL= bg/Include/Library/PchMultiPchBase.h new file mode 100644 index 0000000000..546d7e3212 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/P= chMultiPchBase.h @@ -0,0 +1,37 @@ +/** @file + Prototype of the MultiPch library - Base definitions. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_MULTI_PCH_BASE_H_ +#define _PCH_MULTI_PCH_BASE_H_ + + +#define PCH_LEGACY_ID 0 +#define PCH_MAX 4 + +/** + Function returns PchId for devices of passed Segment and Bus. + PchId is an index in PCH_IP_INFO table + + @param [in] Segment Segment to look for + @param [in] Bus Bas to look for + @param [in, out] PchId pointer to variable to return PchId + + @retval EFI_SUCCESS Function returned valid PchId + @retval EFI_INVALID_PARAMETER Passed pointer is invalid + @retval EFI_DEVICE_ERROR Not found valid PchInfo + @retval EFI_NOT_FOUND For given input parameters not found valid= PchId +**/ +EFI_STATUS +FindMultiPchInfo ( + IN UINTN HeciSegment, + IN UINTN HeciBus, + IN OUT UINTN *PchId + ); + +#endif // _PCH_MULTI_PCH_BASE_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Li= brary/PchPcieRpLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..26b2f8fbaf --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/P= chPcieRpLib.h @@ -0,0 +1,145 @@ +/** @file + Header file for PchPcieRpLib. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIERP_LIB_H_ +#define _PCH_PCIERP_LIB_H_ + +/** + PCIe controller bifurcation configuration. +**/ +typedef enum { + PcieBifurcation4x1 =3D 0, + PcieBifurcation1x2_2x1 =3D 1, + PcieBifurcation2x2 =3D 2, + PcieBifurcation1x4 =3D 3, + PcieUnknownConfig +} PCIE_BIFURCATION_CONFIG; + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCH_PCIE_CONTROLLER_INFO; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device nu= mber. + @param[out] RpFun Return corresponding root port function = number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFunByPchId ( + IN UINT8 PchId, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device nu= mber. + @param[out] RpFun Return corresponding root port function = number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Root Port physical Number by Pch Pcie Root Port Device and Function = Number + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - = Non-Legacy PCH) + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding physical Root Por= t index (0-based) + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not a= ssigned to any physical root port +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpNumber ( + IN UINT8 PchId, + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ); + +/** + Gets base address of PCIe root port. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINTN +PchPcieBase ( + IN UINT8 PchId, + IN UINT32 RpIndex + ); + +/** + Determines whether L0s is supported on current stepping. + + @return TRUE if L0s is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieL0sSupported ( + VOID + ); + +/** + Some early SKL PCH steppings require Native ASPM to be disabled due to h= ardware issues: + - RxL0s exit causes recovery + - Disabling PCIe L0s capability disables L1 + Use this function to determine affected steppings. + + @return TRUE if Native ASPM is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieNativeAspmSupported ( + VOID + ); + +/** + Returns the maximum value of the "Payload" parameter of all available Pc= hPcie Ports. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @retval INT16 The value to assign in field max payload size field +**/ +UINT16 +PchPcieGetMaxPayloadSizeForAllPortsByPchId ( + IN UINT8 PchId + ); + +/** + Returns the maximum value of the "Payload" parameter of all available Pc= hPcie Ports. + + @param VOID + @retval INT16 The value to assign in field max payload size field +**/ +UINT16 +PchPcieGetMaxPayloadSizeForAllPorts ( + VOID + ); + +#endif // _PCH_PCIERP_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pc= hAccess.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pch= Access.h new file mode 100644 index 0000000000..ec020651fb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess= .h @@ -0,0 +1,629 @@ +/** @file + Macros that simplify accessing PCH devices's PCI registers. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + + +// +// SKX defines to get to sspad7 +// +#define UBOX_SCRATCH_DEVICE 0x8 +#define UBOX_SCRATCH_FUNC2 0x2 +#define UBOX_BIOS_SCRATCHPAD7 0xBC + +/// +/// The default PCH PCI segment and bus number +/// +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor = ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsyst= em ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID <<= 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 +#define PCH_DEVICE_DEFAULT 2 + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include "Register/PchRegsThermal.h" +#include "Register/PchRegsUsb.h" +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsPsf.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" +#include "Register/PchRegsEva.h" + +// +// LPC Device ID macros +// +// +// Device IDs that are PCH-H Desktop specific +// +#define IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_3) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_4) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_5) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_6) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +// +// Device IDs that are PCH-H Mobile specific +// + +#define IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU) \ + ) + + +// +// Device IDs that are PCH-LP Mobile specific +// +#define IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_0) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_1) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_2) || \ + (DeviceId =3D=3D V_PCH_LP_LPC_DEVICE_ID_MB_3) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +// +// Device IDS that are PCH Server\Workstation specific +#define IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId =3D=3D V_PCH_H_LPC_DEVICE_ID_A14B) \ + ) + + +#define IS_PCH_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_SERVER (DeviceId) \ + ) + +#define IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE (DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_0) && \ + (DeviceId <=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX) \ + ) + +#define IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >=3D V_PCH_LBG_LPC_DEVICE_ID_UNFUSED) && \ + (DeviceId <=3D V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX ) \ + ) + +#define IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_T) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_LPC_DEVICE_ID_C) \ + ) + +#define IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) \ + ( \ + FALSE \ + ) + +#define IS_PCH_LBG_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ) + + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_LBG_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LBG_SSATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI) \ + ) + + +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) \ + ) + + + +// +// SATA RAID Device ID macros +// +#define IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId =3D=3D V_PCH_LBG_SATA_DEVICE_ID_D_RAID1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1) \ + ) + +#define IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId =3D=3D V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1) \ + ) + + +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE) || \ + (DeviceId =3D=3D V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT) \ + ) + + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId =3D=3D V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_LBG_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_SSATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_H_RAID_AVAILABLE(DeviceId) (TRUE) +#define IS_PCH_LP_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_RAID_AVAILABLE(DeviceId) \ + ( \ + IS_PCH_LBG_RAID_AVAILABLE(DeviceId) \ + ) + +// +// SPI Device ID macros +// +#define IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SPI_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SPI_DEVICE_ID) \ + ) + +#define IS_PCH_H_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_LP_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_SPI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ) + +// +// USB Device ID macros +// +#define IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_USB_DEVICE_ID_XHCI_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_H_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_LP_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_USB_DEVICE_ID_XHCI_1) \ + ) +#define IS_PCH_USB_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ) + +// +// PCIE Device ID macros +// +#define IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_LBG_PCIE_DEVICE_ID_PORT20) \ + ) + +#define IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20) \ + ) + + + +#define IS_PCH_H_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_PORT20) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_MB_SUBD) || \ + (DeviceId =3D=3D V_PCH_H_PCIE_DEVICE_ID_DT_SUBD) \ + ) + +#define IS_PCH_LP_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId =3D=3D V_PCH_LP_PCIE_DEVICE_ID_PORT12) \ + ) + +#define IS_PCH_PCIE_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ) + + +// +// HD Audio Device ID macros +// +#define IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LBG_HDA_DEVICE_ID_7) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_H_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_H_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_LP_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_2) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_3) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_4) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_5) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_6) || \ + (DeviceId =3D=3D V_PCH_LP_HDA_DEVICE_ID_7) \ + ) +#define IS_PCH_HDA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ) + + +/// +/// Any device ID that is PCH-LBG +/// +#define IS_PCH_LBG_SMBUS_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_PCH_LBG_SMBUS_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_SMBUS_DEVICE_ID) \ + ) + +#define IS_PCH_LBG_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SMBUS_DEVICE_ID (DeviceId) || \ + (DeviceId =3D=3D V_PCH_LBG_MROM_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_MROM_DEVICE_ID_0) || \ + (DeviceId =3D=3D V_PCH_LBG_MROM_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_MROM_DEVICE_ID_1) || \ + (DeviceId =3D=3D V_PCH_LBG_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_LAN_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LBG_PROD_LAN_DEVICE_ID) \ + ) + +/// +/// Any device ID that is PCH-H +/// +#define IS_PCH_H_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_H_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_H_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SPI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId) =3D=3D V_PCH_H_THERMAL_DEVICE_ID || \ + (DeviceId) =3D=3D V_PCH_H_SMBUS_DEVICE_ID || \ + (DeviceId) =3D=3D V_PCH_H_LAN_DEVICE_ID \ + ) + +/// +/// Any device ID that is PCH-Lp +/// +#define IS_PCH_LP_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId =3D=3D V_PCH_LP_THERMAL_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SMBUS_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SPI_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_LAN_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_DMA_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID ) || \ + (DeviceId =3D=3D V_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID) \ + ) + +/// +/// Combined any device ID that is PCH-H or PCH-LP +/// +/// +/// And any device that is PCH LBG +/// +#define IS_PCH_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_DEVICE_ID(DeviceId) \ + ) + + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, SbMmioBaseAddress, Pid, Offset, C= ount, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS_BASE (SbMmioBas= eAddress, Pid, Offset), Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS_BASE (SbMmioBase= Address, Pid, Offset), Buffer, Buffer, 1, 1); + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, SbMmioBaseAddress, Pid, Offs= et, DataOr, DataAnd) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS_BASE (SbMmi= oBaseAddress, Pid, Offset), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS_BASE (SbMmioBase= Address, Pid, Offset), DataOr, DataOr, 1, 1); + +#endif + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pc= hLimits.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pch= Limits.h new file mode 100644 index 0000000000..fc5e0f2516 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits= .h @@ -0,0 +1,108 @@ +/** @file + Build time limits of PCH resources. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_H_PCIE_MAX_ROOT_PORTS 20 +#define PCH_LP_PCIE_MAX_ROOT_PORTS 12 + +#define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS +#define PCH_PCIE_CONTROLLER_PORTS 4 +#define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / P= CH_PCIE_CONTROLLER_PORTS) +#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / = PCH_PCIE_CONTROLLER_PORTS) + +#define PCH_MAX_WM20_LANES_NUMBER 20 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_LP_PCIE_MAX_CLK_REQ 6 +#define PCH_H_PCIE_MAX_CLK_REQ 16 + +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define SATA_1_CONTROLLER_INDEX 0 +#define SATA_2_CONTROLLER_INDEX 1 +#define SATA_3_CONTROLLER_INDEX 2 +#define PCH_MAX_SATA_CONTROLLERS 2 +#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS +#define PCH_MAX_SSATA_PORTS 6 +#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sat= a ports in SKL PCH H +#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sat= a ports in SKL PCH LP +#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support devic= e numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS + +#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Conn= ector XHCI, not counting virtual ports like USB-R. +#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Conn= ector XHCI, not counting virtual ports like USB-R. + +#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lan= es + Including two ports reserved for USBr +#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lan= es + Including two ports reserved for USBr + +#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS + +#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed la= nes +#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lan= es + +#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in S= KL PCH-LP and SKL PCH-H + +// +// SerialIo limits +// +#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo c= ontrollers, this includes I2C, SPI and UART +#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I= 2C controllers +#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I= 2C controllers for PCH-LP +#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I= 2C controllers for PCH-H +#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo S= PI controllers +#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo U= ART controllers + +// +// ISH limits +// +#define PCH_ISH_MAX_GP_PINS 8 +#define PCH_ISH_MAX_UART_CONTROLLERS 2 +#define PCH_ISH_MAX_I2C_CONTROLLERS 3 +#define PCH_ISH_MAX_SPI_CONTROLLERS 1 + +// +// SCS limits +// +#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and C= ommunication Subsystem controllers, this includes eMMC, SDIO, SDCARD + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +// +// Number of eSPI slaves +// +#define PCH_ESPI_MAX_SLAVE_ID 2 + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +#define LBG_A0 0x30 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pc= hPolicyCommon.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inclu= de/PchPolicyCommon.h new file mode 100644 index 0000000000..f5861ccafd --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicy= Common.h @@ -0,0 +1,2161 @@ +/** @file + PCH configuration based on PCH policy + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include "PchLimits.h" +#include +#include +#include + +#define FLASH_PROTECTION_CONFIG_REVISION 1 +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) +// +// ---------------------------- PCH General Config -----------------------= -------- +// + +typedef struct { + /** + Subsystem Vendor ID and Subsystem ID of the PCH devices. + This fields will be ignored if the value of SubSystemVendorId and SubS= ystemId + are both 0. + **/ + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID o= f the PCH devices. Default is 0x8086 + UINT16 SubSystemId; ///< Default Subsystem ID of the P= CH devices. Default is 0x7270 + /** + This member describes whether or not the Compatibility Revision ID (CR= ID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 EnableClockSpreadSpec : 1; + UINT32 Serm : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_GENERAL_CONFIG; + + +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define PLATFORM_POR 0 +#define AUTO 0 +#define DCI_DISABLE 0 +// +// ---------------------------- Reserved Page Config ---------------------= -------- +// + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +// +// ---------------------------- PCI Express Config ---------------------- +// + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 =3D 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +enum PCH_PCIE_MPL { + PchPcieMaxPayLoad128B, + PchPcieMaxPayLoad256B, + PchPcieMaxPayLoad512B, +}; + +typedef enum { + PchPcieEqDefault =3D 0, ///< Use reference code default (software = margining) + PchPcieEqHardware =3D 1, ///< Hardware equalization (experimental),= note this requires PCH-LP C0 or PCH-H D0 or newer + PchPcieEqSoftware =3D 2, ///< Use software margining flow + PchPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffici= ent settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port. +**/ +typedef struct { + UINT32 Enable : 1; ///< Root Port enabling,= 0: Disable; 1: Enable. + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether de= dicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if = ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals for= LP and H. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits1 : 3; ///< Reserved fields for= future expansion w/o protocol change + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. + /** + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX= _PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the r= oot port. + **/ + UINT32 MaxPayload : 2; + + /** + Indicates how this root port is connected to endpoint. + 0: built-in device; + 1: slot + Built-in is incompatible with hotplug-capable ports + **/ + UINT32 SlotImplemented : 1; + + UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether P= ERST# is active 0: Low; 1: High, See: DeviceResetPad + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + 0: Default; 2: Software Search; 4: Fixed Coeficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default. + /** + The PCH pin assigned to device PERST# signal if available, zero otherw= ise. + This entry is used mainly in Gen3 software equalization flow. It is ne= cessary for some devices + (mainly some graphic adapters) to successfully complete the software e= qualization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 DeviceResetPad; + UINT32 Rsvd1; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig. + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable. + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Speci= fies upper limit on power supplie by slot. Leave as 0 to set to default. De= fault is zero. + + UINT32 HsioRxSetCtleEnable : 1; ///< @deprecated, please= use HsioRxSetCtleEnable from PCH_HSIO_PCIE_LANE_CONFIG + UINT32 HsioRxSetCtle : 6; ///< @deprecated, please= use HsioRxSetCtle from PCH_HSIO_PCIE_LANE_CONFIG + // + // Gen3 Equaliztion settings + // + UINT32 Uptp : 4; ///< (Test) Upstr= eam Port Transmiter Preset used during Gen3 Link Equalization. Used for all= lanes. Default is 5. + UINT32 Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7. + UINT32 RsvdBits3 : 3; ///< Reserved Bits + UINT32 Rsvd2[16]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/// +/// The PCH_PCIE_CONFIG block describes the expected configuration of the = PCH PCI Express controllers +/// +typedef struct { + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Pci Delay (Latency) Optimization ECR - Engineering Change Request + /// + UINT8 PciDelayOptimizationEcr; + /// + /// Pch Pcie Max Read Request Size + /// + UINT8 MaxReadRequestSize; + /// + /// Gen3 Equalization settings for physiacal PCIe lane, index 0 represen= ts PCIe lane 1, etc. + /// Correstponding entries are used when root port EqPh3Method is PchPci= eEqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS= ]; + /// + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCI= e devices are LTR capable + or leaving untouched. + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR cap= ablility. + - To allow ICC PLL shutdown if all present PCIe devices are LTR capa= ble or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable = PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not sup= port LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal= , or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 21; + /** + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect. + I case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + + /// + /// These are Competions Timeout settings for Uplink ports in Server PCH + /// + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + /// + /// Max Payload Size settings for Upling ports in Server PCH + /// + UINT8 PchPcieUX16MaxPayload; + UINT8 PchPcieUX8MaxPayload; + + /// + /// Intel+ Virtual Technology for Directed I/O (VT-d) Support + /// + UINT8 VTdSupport; + UINT16 Rsvd0; ///< Reserved bytes + UINT32 Rsvd1[2]; ///< Reserved bytes +} PCH_PCIE_CONFIG; + + +/// +/// The PCH_PCIE_CONFIG2 block describes the additional configuration of t= he PCH PCI Express controllers +/// +typedef struct { + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; ///= < List of coefficients used during equalization (applicable to both softwar= e and hardware EQ) + PCH_PCIE_EQ_PARAM Rsvd0[3]; + UINT32 Rsvd1[4]; +} PCH_PCIE_CONFIG2; + +typedef struct { + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + UINT8 AdrSysPwrOk; + UINT8 AdrOverClockingWdt; + UINT8 AdrCpuThermalWdt; + UINT8 AdrPmcParityError; +} PCH_ADR_CONFIG; + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set = CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX O= utput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value ove= rride + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX O= utput De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX O= utput -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX O= utput -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits + + // + // Server specific offsets + // + UINT32 HsioIcfgAdjLimitLoEnable : 1; /// < 0: Disable;= 1: Enable Set the floor on how many ticks the autovref can take. + UINT32 HsioIcfgAdjLimitLo : 5; /// < Set the floor on h= ow many ticks the autovref can take. (offset 0x9c) + UINT32 HsioSampOffstEvenErrSpEnable : 1; /// < 0: Disable;= 1: Enable EVEN ERR P sampler manual offset. + UINT32 HsioSampOffstEvenErrSp : 8; /// < EVEN ERR P sampler= manual offset. (offset 0xA0) + UINT32 RsvdBits2 : 17; ///< Reserved Bits + + UINT32 HsioRemainingSamplerOffEnable : 1; /// < 0: Disable;= 1: Enable Remaining EVEN/ODD ERR P and N sampler manual offset. + UINT32 HsioRemainingSamplerOff : 24; /// < Remaining EVEN/ODD= ERR P and N sampler manual offset. (offset 0xA4) + UINT32 HsioVgaGainCalEnable : 1; /// < 0: Disable;= 1: Enable VGA Gain CAL + UINT32 HsioVgaGainCal : 5; /// < VGA Gain Calibratio= n Value (offset 0x1C) + UINT32 RsvdBits3 : 1; ///< Reserved Bits + + UINT32 Rsvd4[12]; ///< Reserved bytes + +} PCH_HSIO_PCIE_LANE_CONFIG; + +/// +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO= for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_CONFIG; + + +/// +/// The PCH_HSIO_PCIE_WM20_CONFIG block describes the configuration of the= HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_WM20_LANES_NUMBER]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_WM20_CONFIG; + +// +// ---------------------------- EVA Config ----------------------------- +// + +// EVA port function hide registers. + +typedef union { + UINT32 FuncHideVal; + struct _FuncHideBits { + UINT32 PchEvaMROM0Enable : 1; ///< MROM is never hidden + UINT32 PchEvaMROM1Hidden : 1; ///< Enable/disable MROM1 funcion, = 1 - hidden + UINT32 RsvdBits1 : 3; + UINT32 PchEvasSata1Hidden : 1; ///< Enable/disable sSata1, 1 - hid= den + UINT32 RsvdBits2 : 25; + UINT32 PchEvaLock : 1; ///< Lock registers in EVA + + } FuncHideBits; +} +PCH_EVA_DNDEVFUNCHIDE; + + +typedef struct { + PCH_EVA_DNDEVFUNCHIDE FuncHide; + UINT8 LockDown; +} +PCH_EVA_CONFIG; +// +// ---------------------------- SATA Config ----------------------------- +// + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +/** + This structure configures the features, property, and capability for eac= h SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: E= nable + UINT32 HotPlug : 1; ///< 0: Disable; = 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; = 1: Enable + UINT32 External : 1; ///< 0: Disable; = 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; = 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: S= SD + UINT32 DevSlp : 1; ///< 0: Disable; = 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; = 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. De= fault is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout= (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for= future expansion w/o protocol change + + UINT32 HsioRxEqBoostMagAdEnable : 1; ///< @deprecated, please= use HsioRxGen3EqBoostMagEnable + UINT32 HsioRxEqBoostMagAd : 6; ///< @deprecated, please= use HsioRxGen3EqBoostMag + + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< @deprecated, please= use HsioTxGen1DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen1DownscaleAmp : 6; ///< @deprecated, please= use HsioTxGen1DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< @deprecated, please= use HsioTxGen2DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmp : 6; ///< @deprecated, please= use HsioTxGen2DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 Rsvd0 : 11; ///< Reserved bits + +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 RaidAlternateId : 1; ///< 0: Disable; 1: Enable = RAID Alternate ID + UINT32 Raid0 : 1; ///< 0: Disable; 1: Enable = RAID0 + UINT32 Raid1 : 1; ///< 0: Disable; 1: Enable = RAID1 + UINT32 Raid10 : 1; ///< 0: Disable; 1: Enable = RAID10 + UINT32 Raid5 : 1; ///< 0: Disable; 1: Enable = RAID5 + UINT32 Irrt : 1; ///< 0: Disable; 1: Enable = Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0: Disable; 1: Enable = OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b: 2 secs; 01b: 4 se= cs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0: Disable; 1: Enable.= Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0: Disable; 1: Enable.= Indicates that the LED/SGPIO hardware is attached and ping to locate featu= re is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0: Disable; 1: Enable.= Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0: Disable; 1: Enable = RST Smart Storage caching Bit + UINT32 EfiRaidDriverLoad :1; ///< 0: Dont load EFI RST/RSTe dri= ver; 1: Load EFI RST/RSTe driver + UINT32 Resvdbits : 18; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure describes the details of Intel RST for PCIe Storage remap= ping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage re= mapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should = be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI = controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <= b>0 =3D autodetect) + The supported ports for PCIe Storage remapping is different depend on = the platform and cycle router, the assignments are as below: + SKL PCH-LP RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + SKL PCH-H RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarant= ees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an re= set caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/// +/// The PCH_SATA_CONFIG block describes the expected configuration of the = SATA controllers. +/// +typedef struct { + /// + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test)= 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disabl= e; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disabl= e; 1: Enable SATA Power Optimizer on PCH side. + /** + eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSA= TA port speed. + Please be noted, this setting could be cleared by HBA reset, which mig= ht be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver = after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should = preserve the + setting before and after initialization. For support it after POST, it= 's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT32 eSATASpeedLimit : 1; + UINT32 EnclosureSupport : 1; ///< 0: Disa= ble; 1: Enable Enclosure Management Support + UINT32 Rsvdbits : 26; ///< Reserv= ed bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_= MODE). Default is PchSataModeAhci. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + 0h: PchSataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2= ); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each= SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting a= pplicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORA= GE_CR]; + UINT32 Rsvd0[4]; ///< Reserved fiel= ds for future expansion +} PCH_SATA_CONFIG; + + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Ou= tput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits + + UINT32 Rsvd0[8]; ///< Reserved bytes +} PCH_HSIO_SATA_PORT_LANE; + + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the= SATA controller. +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; + UINT32 Rsvd0[8]; /= //< Reserved bytes + +} PCH_HSIO_SATA_CONFIG; + +// +// --------------------------- IO APIC Config ----------------------------= -- +// +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the = PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit = is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpos= e: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is vali= d, PCH code will not program these fields if this bit is not TRUE. 0: Di= sable; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as R= equestor / Completer ID. Default is 0x00. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable = IOAPIC Entry 24-119 + UINT32 RsvdBits1 : 7; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC= ID. Default is 0x02. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for= the IOxAPIC range. Default is 0 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +// +// ---------------------------- HPET Config ----------------------------- +// + +/** + The PCH_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + /** + Determines if enable HPET timer. 0: Disable; 1: Enable. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _S= TA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halte= d. + **/ + UINT32 Enable : 1; + UINT32 BdfValid : 1; ///< Whether the BDF value is vali= d. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requ= estor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as R= equestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as= Requestor / Completer ID. Default is 0x00. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Defaul= t is 0xFED00000. +} PCH_HPET_CONFIG; + +// +// --------------------------- HD-Audio Config ---------------------------= --- +// +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of t= he Intel HD Audio feature. +/// +#define PCH_HDAUDIO_AUTO 2 + +enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP { + PchHdaIoBufOwnerHdaLink =3D 0, ///< HD-Audio link owns all the I= /O buffers. + PchHdaIoBufOwnerHdaLinkI2sPort =3D 1, ///< HD-Audio link owns 4 and I2S= port owns 4 of the I/O buffers. + PchHdaIoBufOwnerI2sPort =3D 3 ///< I2S0 and I2S1 ports own all = the I/O buffers. +}; + +enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE { + PchHdaIoBuf33V =3D 0, + PchHdaIoBuf18V =3D 1 +}; + +enum PCH_HDAUDIO_VC_TYPE { + PchHdaVc0 =3D 0, + PchHdaVc1 =3D 1 +}; + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled =3D 0, + PchHdaDmic2chArray =3D 1, + PchHdaDmic4chArray =3D 2, + PchHdaDmic1chArray =3D 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz =3D 0, + PchHdaLinkFreq12MHz =3D 1, + PchHdaLinkFreq24MHz =3D 2, + PchHdaLinkFreq48MHz =3D 3, + PchHdaLinkFreq96MHz =3D 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T =3D 0, + PchHdaIDispMode1T =3D 1 +} PCH_HDAUDIO_IDISP_TMODE; + +typedef struct { + /** + This member describes whether or not Intel HD Audio (Azalia) should be= enabled. + If enabled (in Auto mode) and no codec exists the reference code will = automatically disable + the HD Audio device. + 0: Disable, 1: Enable, 2: Auto (enabled if codec detected and initi= alized, disabled otherwise) + **/ + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <= b>1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Di= sable; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: = 0: HD-A Link; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Selec= t: 0: 3.3V; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: = 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUD= IO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDA= UDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDI= O_IDISP_TMODE enum): 0: 2T, 1: 1T + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconne= ction, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enu= merable + UINT32 RsvdBits0 : 13; ///< Reserved bits 1 + /** + Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI = table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC= _TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: D= isable; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: 0: Disable= ; 1: Enable + UINT32 RsvdBits1 : 28; ///< Reserved bits 2 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT In= tel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel W= oV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; + /** + Bitmask of supported DSP Pre/Post-Processing Modules. + Specific pre/post-processing module bit position must be coherent with= the ACPI implementation: + \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Suppo= rt. + DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable + Default is zero. + **/ + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< (Test) The delay timer= after Azalia reset, the value is number of microseconds. Default is 600= . + UINT8 Rsvd0[2]; ///< Reserved bytes, align to mult= iple 4 +} PCH_HDAUDIO_CONFIG; + +// +// ------------------------------ LAN Config -----------------------------= ---- +// + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + /** + Determines if enable PCH internal LAN, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to di= sabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL r= egister. + So it's recommendated to issue a global reset when changing the status= for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management;= 1: Enabled, 0: Disabled; + UINT32 RsvdBits0 : 4; ///< Reserved bits + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# i= s supported; 1: Enabled, 0: Disabled; + UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReq= Supported is TRUE. + UINT32 RsvdBits1 : 21; ///< Reserved bits + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LAN_CONFIG; + +// +// --------------------------- SMBUS Config ------------------------------ +// + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + /** + This member describes whether or not the SMBus controller of PCH shoul= d be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating. + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_CONFIG; + +// +// --------------------------- Lock Down Config --------------------------= ---- +// +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH + for security requirement. +**/ +typedef struct { + /** + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI = Enable bit. 0: Disable; 1: Enable. + **/ + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps. 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + (Test) Enable RTC lower and upper 128 byte Lock bits to lock By= tes 38h-3Fh in the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to = take care + of BIOS modification (including SetVariable) in DXE or runtime phase a= fter + EndOfDxe protocol is installed. 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + Enable InSMM.STS (EISS) in SPI + If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' a= lso + in order to write to BIOS regions of SPI Flash. If this bit is clear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programm= ing in + PEI phase or early DXE phase. + 0: Clear EISS bit; 1: Set EISS bit. + **/ + UINT32 SpiEiss : 1; + /** + Lock configuration and/or state of vendor-defined set of GPIOs. + 0: Don't lock; 1: Lock + **/ + UINT32 GpioLockDown : 1; + /** + Lock TCO Base Address. + D31:F4 (SMBus Controller) Offset 54h: TCOCTL (TCO Control Register) Bi= t 0: TCO_BASE_LOCK (TCO Base Lock) + 0: Don't lock; 1: Lock + **/ + UINT32 TcoLock : 1; + + /** + (Test) Enable Lock bit for Device Function Hide Register in + MS Unit Device Function Hide Control Register (MSDEVFUNCHIDE) + 0: Disable; 1: Enable. + **/ + UINT32 EvaLockDown : 1; + UINT32 RsvdBits0 : 24; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +// +// --------------------------- Thermal Config ----------------------------= -------- +// +/** + This structure lists PCH supported throttling register setting for custi= mization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle f= unction. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13= will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked = until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling= between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit f= ields to update the PCH + thermal status to the processor which is factored into the processor t= hrottling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for T= hermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonom= ous Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Wi= dth + UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Wi= dth + UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Wi= dth + UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Wi= dth + UINT32 RsvdBits1 : 16; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure lists PCH supported SATA thermal throttling register sett= ing for custimization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init= Tdispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init= Tdispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLE; + +/** + This structure decides the settings of PCH Thermal throttling. When the = Suggested Setting + is enabled, PCH RC will use the suggested representative values. +**/ +typedef struct { + THERMAL_THROTTLE_LEVELS TTLevels; + DMI_HW_WIDTH_CONTROL DmiHaAWC; + SATA_THERMAL_THROTTLE SataTT; + SATA_THERMAL_THROTTLE sSataTT; +} PCH_THERMAL_THROTTLING; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN = settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, C= PU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 st= ate, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection= , 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or= TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throt= tling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the= PCH for Thermal. +**/ +typedef struct { + /** + This field reports the status of Thermal Device. When it reports Therm= alDevice + is disabled, the PCI configuration space of thermal device will be hid= den by + setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST. + **/ + UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, 1: Enabled in= PCI mode, 2: Enabled in ACPI mode + UINT32 TsmicLock : 1; ///< This locks down "SMI Enable o= n Alert Thermal Sensor Trip". 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 29; + /** + This field decides the settings of Thermal throttling. When the Sugges= ted Setting + is enabled, PCH RC will use the suggested representative values. + **/ + PCH_THERMAL_THROTTLING ThermalThrottling; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is zero. + - 0x00 is the hottest + - 0x1FF is the lowest temperature + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +enum PCH_THERMAL_DEVICE { + PchThermalDeviceDisabled, + PchThermalDeviceEnabledPci, + PchThermalDeviceEnabledAcpi, + PchThermalDeviceAuto +}; + +// +// ---------------------- Power Management Config ------------------------= -- +// +/** + This PCH_POWER_RESET_STATUS Specifies which Power/Reset bits need to be = cleared by the PCH Init Driver. + Usually platform drivers take care of these bits, but if not, let PCH In= it driver clear the bits. +**/ +typedef struct { + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in = the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bi= t in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable<= /b>. + UINT32 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bi= t in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable<= /b>. + UINT32 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit i= n the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit = in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 27; +} PCH_POWER_RESET_STATUS; + +/** + This PCH_GBL2HOST_EN specifes enable bits related to the "Convert Global= Resets to Host Resets" (G2H) feature +**/ +typedef union { + struct { + UINT32 G2H_FEA : 1; ///< G2H Feature Enable: 0: Disable; = 1: Enable. + UINT32 LTRESET : 1; ///< LT RESET G2H Enable: 0: Disable;= 1: Enable. + UINT32 PMCGBL : 1; ///< PMC FW-Initiated Global Reset G2= H Enable: 0: Disable; 1: Enable. + UINT32 CPUTHRM : 1; ///< CPU Thermal Trip G2H Enable: 0: = Disable; 1: Enable. + UINT32 PCHTHRM : 1; ///< PCH Internal Thermal Trip G2H En= able: Disable; 1: Enable. + UINT32 PBO : 1; ///< Power Button Override G2H Enable= : 0: Disable; 1: Enable. + UINT32 MEPBO : 1; ///< ME-Initiated Power Button Overri= de G2H: 0: Disable; 1: Enable. + UINT32 MEWDT : 1; ///< ME FW Watchdog Timer G2H Enable:= 0: Disable; 1: Enable. + UINT32 MEGBL : 1; ///< ME-Initiated Global Reset G2H En= able: Disable; 1: Enable. + UINT32 CTWDT : 1; ///< CPU Thermal Watchdog Timer G2H E= nable: Disable; 1: Enable. + UINT32 PMCWDT : 1; ///< PMC FW Watchdog Timer G2H Enable= : Disable; 1: Enable. + UINT32 ME_UERR : 1; ///< ME Uncorrectable Error G2H Enabl= e: Disable; 1: Enable. + UINT32 SYSPWR : 1; ///< SYS_PWROK Failure G2H Enable: Di= sable; 1: Enable. + UINT32 OCWDT : 1; ///< Over-Clocking WDT G2H Enable: Di= sable; 1: Enable. + UINT32 PMC_PARERR : 1; ///< PMC Parity Error G2H Enable: 0: = Disable; 1: Enable. + UINT32 Reserved : 1; ///< Reserved + UINT32 IEPBO : 1; ///< IE-Initiated Power Button Overri= de G2H: 0: Disable; 1: Enable. + UINT32 IEWDT : 1; ///< IE FW Watchdog Timer G2H Enable:= 0: Disable; 1: Enable. + UINT32 IEGBLN : 1; ///< IE-Initiated Global Reset G2H En= able: 0: Disable; 1: Enable. + UINT32 IE_UERRN : 1; ///< IE Uncorrectable Error G2H Enabl= e: 0: Disable; 1: Enable. + UINT32 ACRU_ERR_2H_EN : 1; ///< AC RU Error G2H Enable: 0: Disab= le; 1: Enable. + } Bits; + UINT32 Value; +} PCH_GBL2HOST_EN; + +/** + This structure allows to customize PCH wake up capability from S5 or Dee= pSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B= (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, rega= rdless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 = if PME_B0_EN =3D 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enabl= e Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0= : Disable; 1: Enable. + UINT32 Gp27WakeFromDeepSx : 1; ///< @deprecated + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to w= ake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from S= x, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0= : Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from D= eepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <= b>0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wa= ke from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 25; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing a= nd Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + PchPmGrPfetDur1us, + PchPmGrPfetDur2us, + PchPmGrPfetDur5us, + PchPmGrPfetDur20us +} PCH_PM_GR_PFET_DUR; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power managemen= t settings. + The PowerResetStatusClear field would clear the Power/Reset status bits,= please + set the bits if you want PCH Init driver to clear it, if you want to che= ck the + status later then clear the bits. +**/ +typedef struct { + /** + Specify which Power/Reset bits need to be cleared by + the PCH Init Driver. + Usually platform drivers take care of these bits, but if + not, let PCH Init driver clear the bits. + **/ + PCH_POWER_RESET_STATUS PowerResetStatusClear; + PCH_WAKE_CONFIG WakeConfig; ///< Specify W= ake Policy + PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx P= olicy. Default is PchDeepSxPolDisable. + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Mi= nimum Assertion Width Policy. Default is PchSlpS350ms. + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Mi= nimum Assertion Width Policy. Default is PchSlpS44s. + PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS M= inimum Assertion Width Policy. Default is PchSlpSus4s. + PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Min= imum Assertion Width Policy. Default is PchSlpA2s. + /** + This member describes whether or not the PCI ClockRun feature of PCH s= hould + be enabled. 0: Disable; 1: Enable + **/ + UINT32 PciClockRun : 1; + UINT32 SlpStrchSusUp : 1; ///< 0: Dis= able; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is lo= w. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: = Enable. + Enery Report is must have feature. Wihtout Energy Report, the performa= nce report + by workloads/benchmarks will be unrealistic because PCH's energy is no= t being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to = try to reduce + its power by throttling, then it could try to disable Energy Report to= do first debug. + This might be due to energy scaling factors are not correct or the LPM= settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX= and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + (Test) + When set to true, this bit disallows Host reads to PMC XRAM. + BIOS must set this bit (to disable and lock the feature) prior to pass= ing control to OS + 0:Disable, 1:Enable + **/ + UINT32 PmcReadDisable : 1; + /** + This determines the type of reset issued during the capsule update proc= ess by UpdateCapsule(). + The default is 0:S3 Resume, 1:Warm reset. + **/ + UINT32 CapsuleResetType : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input valu= e from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the po= wer button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle stat= e. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, 1:Enable + + Warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# = being asserted. + If a platform is using SLP_S0 to lower PCH voltage the below policy mu= st be disabled. + **/ + UINT32 SlpS0Enable : 1; + UINT32 DirtyWarmReset : 1; ///< DirtyWarm= Reset enable + UINT32 StallDirtyWarmReset : 1; ///< Stall dur= ing DWR + UINT32 GrPfetDurOnDef : 2; ///< Global Re= set PFET duration + UINT32 Dwr_MeResetPrepDone : 1; ///< ME Reset = Prep Done + UINT32 Dwr_IeResetPrepDone : 1; ///< IE Reset = Prep Done + UINT32 Dwr_BmcRootPort : 8; ///< Root port= where BMC is connected to + UINT32 RsvdBits0 : 6; ///< @todo ADD= DESCRIPTION + + PCH_GBL2HOST_EN PchGbl2HostEn; + /** + Reset Power Cycle Duration could be customized in the unit of second. = Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~= 4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following= register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reser= ved bytes + +} PCH_PM_CONFIG; + +// +// ---------------------------- DMI Config ----------------------------- +// + +/// +/// The PCH_DMI_CONFIG block describes the expected configuration of the P= CH for DMI. +/// +typedef struct { + /** + 0: Disable; 1: Enable ASPM on PCH side of the DMI Link. + While DmiAspm is enabled, DMI ASPM will be set to Intel recommended va= lue. + **/ + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side. + BOOLEAN DmiStopAndScreamEnable : 1; + UINT32 DmiLinkDownHangBypass : 1; + UINT32 Rsvdbits : 29; + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_DMI_CONFIG; + +// +// --------------------------- Serial IRQ Config -------------------------= ----- +// + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continu= ous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of = the PCH for Serial IRQ. +/// +typedef struct { + UINT32 SirqEnable : 1; ///< Determines if enabl= e Serial IRQ. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Sel= ect. 0: quiet mode 1: continuous mode. + PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse W= idth. Default is PchSfpw4Clk. + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LPC_SIRQ_CONFIG; + + +// +// --------------------------- Port 61h Emulation in SMM -----------------= ------------- +// +/** + This structure is used for the emulation feature for Port61h read. The p= ort is trapped + and the SMI handler will toggle bit4 according to the handler's internal= state. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disabl= e; 1: Enable the emulation + UINT32 RsvdBits0 : 31; ///< Reserved = bits +} PCH_PORT61H_SMM_CONFIG; + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_I= NT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers= in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[2]; = ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; = ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; = ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; = ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; = ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. + UINT8 ShutdownPolicySelect; = ///< Shutdown mode 0: PCH will drive INIT#; 1: PCH will drive PLTRST# = active +} PCH_INTERRUPT_CONFIG; + +// +// --------------------- TraceHub Config ------------------------------ +// +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + TRACE_HUB_CONFIG TraceHub; + UINT32 AetEnableMode : 2; + UINT32 PchTraceHubHide : 1; +} PCH_TRACE_HUB_CONFIG; + + +// +// ------------------- CIO2 FLIS registers Config -------------------- +// + +/// +/// The PCH_SKYCAM_CIO2_FLS_CONFIG block describes SkyCam CIO2 FLS registe= rs configuration. +/// +typedef struct { + UINT32 PortATrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port A Clk Trim + UINT32 PortBTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port B Clk Trim + UINT32 PortCTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port C Clk Trim + UINT32 PortDTrimEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port D Clk Trim + UINT32 PortACtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port A Ctle + UINT32 PortBCtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port B Ctle + UINT32 PortCDCtleEnable : 1; ///< 0: Disable; 1: Ena= ble - Enable Port C/D Ctle + UINT32 RsvdBits0 : 25; + + UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value + UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value + UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value + UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value + UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value + UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value + UINT32 RsvdBits1 : 5; + + UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value + UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value + UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value + UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value + UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value + + UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value + UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value + +} PCH_SKYCAM_CIO2_FLS_CONFIG; +// +// ---------------------------- USB Config ----------------------------- +// + +/// +/// The location of the USB connectors. This information is use to decide= eye diagram tuning value for Usb 2.0 motherboard trace. +/// +enum PCH_USB_PORT_LOCATION{ + PchUsbPortLocationBackPanel =3D 0, + PchUsbPortLocationFrontPanel, + PchUsbPortLocationDock, + PchUsbPortLocationMiniPciE, + PchUsbPortLocationFlex, + PchUsbPortLocationInternalTopology, + PchUsbPortLocationSkip, + PchUsbPortLocationMax +}; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the= port strength accordingly. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable= . + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, = align to multiple 4. + USB2_PHY_PARAMETERS Afe; ///< USB2 AFE settings + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N of PCH is enabled by pl= atform modules. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 3.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multipl= e 4 + + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3= .0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2dee= mph3p5) + HSIO_TX_DWORD5[21:16] + Default =3D 29h (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 6; + + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3= .0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default =3D 00h + **/ + UINT32 HsioTxDownscaleAmp : 6; + + UINT32 RsvdBits1 : 18; ///< Reserved bits + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB30_PORT_CONFIG; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 + +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + /** + 0: Disable; 1: Enable SSIC support. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits1 : 31; +} PCH_XHCI_SSIC_PORT; +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT]; +} PCH_SSIC_CONFIG; + +/** + The PCH_XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be ena= bled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_XDCI_CONFIG; + +/** + This member describes the expected configuration of the PCH USB controll= ers, + Platform modules may need to refer Setup options, schematic, BIOS specif= ication + to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring + the schematic. +**/ +typedef struct { + /** + This feature intends to reduce the necessary initialization time for U= SB HC + and devices on root ports. It is assembled by PCHInit drivers in PEI a= nd DXE phase. + In PEI phase, the feature resets all USB HCs on PCH bus, including Int= el EHCI + and XHCI. After reset USB HC, continue the system initialization witho= ut waiting + for the USB XHC reset ready. After running to DXE phase, the feature r= esets + those USB devices installed on each USB HC root port in parallel, incl= uding + any non USB3 speed devices on XHCI root port if XHCI is enabled. + For USB3 protocol root port, USB3 speed devices will be advanced to + enable state if link training succeeds after XHC reset. + + UsbPrecondition =3D Enable , Force USB Init happen in PEI as part of 2= Sec Fast Boot bios optimization. + UsbPrecondition =3D Disable, USB Init happen in DXE just like traditio= nally where it happen. + Remark: With Precondition Enabled some USB2 devices which are not comp= liant with usb2 specification + are not being detected if installed in the system during S4/S5. + + + 0: Disable; 1: Enable. + **/ + UINT32 UsbPrecondition : 1; + /** + This policy will disable XHCI compliance mode on all ports. Complicanc= e Mode should be default enabled. + For the platform that support USB Type-C, it can disable Compliance Mo= de, and enable Compliance Mode when testing. + 0:Disable , 1: Enable + **/ + UINT32 DisableComplianceMode : 1; + // Following option is now exposed since there are no restricted registe= rs used. + UINT32 XhciOcMapEnabled : 1; = ///< 0: To disable OC mapping for USB XHCI ports 1: Set Xhci OC registers,= Set Xhci OCCDone bit, XHCI Access Control Bit. + UINT32 XhciWakeOnUsb : 1; = ///< 0: To disable Wake on USB connect/Disconnect 1: Enables Wake on USB c= onnect/disconnect event. + UINT32 XhciDisMSICapability : 1; + UINT32 RsvdBits0 : 27; ///< Re= served bits + + /** + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules. + Panel and Dock are used to describe the layout of USB port. Panel is o= nly available for Desktop PCH. + Dock is only available for Mobile LPT. + **/ + PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules. + **/ + PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be ena= bled. + **/ + PCH_XDCI_CONFIG XdciConfig; + /** + These members describe some settings which are related to the SSIC por= ts. + **/ + PCH_SSIC_CONFIG SsicConfig; + + UINT32 Rsvd0[6]; ///< Reserved b= ytes +} PCH_USB_CONFIG; + +// +// --------------------------- Flash Protection Range Registers ----------= -------------------- +// +/** + The PCH provides a method for blocking writes and reads to specific rang= es + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAdd= resses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or = erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is b= locked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +// +// --------------------- WatchDog (WDT) Configuration --------------------= ---------- +// +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le. + UINT32 RsvdBits : 31; +} PCH_WDT_CONFIG; + +// +// --------------------- P2SB Configuration ------------------------------ +// +/** + This structure contains the policies which are related to P2SB device. +**/ +typedef struct { + /** + (Test) + This unlock the SBI lock bit to allow SBI after post time. 0: Disab= le; 1: Enable. + NOTE: Do not set this policy "SbiUnlock" unless necessary. + **/ + UINT32 SbiUnlock : 1; + /** + (Test) + The PSF registers will be locked before 3rd party code execution. + This policy unlock the PSF space. 0: Disable; 1: Enable. + NOTE: Do not set this policy "PsfUnlock" unless necessary. + **/ + UINT32 PsfUnlock : 1; + /** + Debug + The P2SB PCIe device will be hidden at end of PEI stage. + This policy reveal P2SB PCIe device at end of EXE. 0: Disable (hidd= en); 1: Enable (visible). + NOTE: Do not set this policy "P2SbReveal" unless necessary. + **/ + UINT32 P2SbReveal : 1; + UINT32 RsvdBits : 29; +} PCH_P2SB_CONFIG; + +// +// --------------------- DCI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to Direct Connect= ion Interface (DCI). +**/ +typedef struct { + /** + (Test) DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the Host control= is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able = to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a co= nsent from the user to enable this DCI feature. + 0:Disabled; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + (Test) When set to Auto detect mode, it detects DCI being conne= cted during BIOS post time and enable DCI. + Else it disable DCI. This policy only apply when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, 1: Enable AUTO mode + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_DCI_CONFIG; + +// +// --------------------- LPC Configuration ------------------------------ +// +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement = LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this = is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_LPC_CONFIG; + +// +// --------------------- SPI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to SPI. +**/ +typedef struct { + /** + Force to show SPI controller. + 0: FALSE, 1: TRUE + NOTE: For Windows OS, it MUST BE false. It's optional for other OSs. + **/ + UINT32 ShowSpiController : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_SPI_CONFIG; + +// +// --------------------------------------------------------------------- +// + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an upd= ate in the revision number +**/ +#define PCH_POLICY_REVISION 15 + +/** + The PCH Policy allows the platform code to publish a set of + configuration information that the PCH drivers will use to configure the= PCH hardware. + The Revision field is used to accommodate backward compatible changes to= the PPI/protocol. + The Revision should be initialized to PCH_POLICY_REVISION_X + by the PPI producer. + The BusNumber field is used for platform to assign Bus number with multi= ple instances. + + All reserved/unused fields must be initialized with zeros. +**/ +struct _PCH_POLICY { + /** + This member specifies the revision of the PCH policy PPI. This field i= s used to + indicate backwards compatible changes to the protocol. Platform code t= hat produces + this PPI must fill with the correct revision value for the PCH referen= ce code + to correctly interpret the content of the PPI fields. + + Revision 1: Original version + - Add DciAutoDetect policy in PCH_GENERAL_CONFIG. + - Add SbiUnlock policy in PCH_P2SB_CONFIG. + - Add the following policies in PCH_ISH_CONFIG: + - SpiGpioAssign + - Uart0GpioAssign + - Uart1GpioAssign + - I2c0GpioAssign + - I2c1GpioAssign + - I2c2GpioAssign + - Gp0GpioAssign + - Gp1GpioAssign + - Gp2GpioAssign + - Gp3GpioAssign + - Gp4GpioAssign + - Gp5GpioAssign + - Gp6GpioAssign + - Gp7GpioAssign + - Add ClkReqSupported and ClkReqDetect in PCH_PCIE_ROOT_PO= RT_CONFIG. + - Add the following in PCH_SKYCAM_CIO2_CONFIG + - SkyCamPortATermOvrEnable + - SkyCamPortBTermOvrEnable + - SkyCamPortCTermOvrEnable + - SkyCamPortDTermOvrEnable + - Add UartHwFlowCtrl in PCH_SERIAL_IO + - Move DciEn and DciAutoDetect to PCH_DCI_CONFIG + + + + Revision 2: Updated version + - Add Enable policy in PCH_SSIC_CONFIG + - Deprecated Target Debugger option of EnableMode in PCH_T= RACE_HUB_CONFIG + - Deprecated the following policies in PCH_TRACE_HUB_CONFIG + - MemReg0WrapEnable + - MemReg1WrapEnable + - TraceDestination + - PtiMode + - PtiSpeed + - PtiTraining + - Deprecated the Usb3PinsTermination and ManualModeUsb30Pe= rPinEnable in PCH_XHCI_CONFIG + - Redefine the Enable policy in PCH_HPET_CONFIG + - Add EnhancePort8xhDecoding in PCH_LPC_CONFIG + - Add PsfUnlock in PCH_P2SB_CONFIG + - Add AllowNoLtrIccPllShutdown in PCH_PCIE_CONFIG + - Add PdtUnlock in PCH_ISH_CONFIG + - Remove PwrmBase from policy since the base address is pr= edefined. + - Add DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2= s in PCH_HDAUDIO_CONFIG + - Add Gen3EqPh3Method abd EqPh3LaneParam in PCH_PCIE_ROOT_= PORT_CONFIG/PCH_PCIE_CONFIG + - Remove SlotImplemented and PmeInterrupt from PCH_PCIE_RO= OT_PORT_CONFIG + + + + Revision 3: Updated version + - Add PwrBtnOverridePeriod policy in PCH_PM_CONFIG + - Add USB20_AFE in PCH_USB20_PORT_CONFIG + - Add ClkReqSupported in PCH_LAN_CONFIG + + + + Revision 4: Updated version + - Add DeviceResetPad and DeviceResetPadActiveHigh in PCH_P= CIE_ROOT_PORT_CONFIG + + + Revision 5: Updated version + - Deprecated ScsSdioMode in PCH_SCS_CONFIG + - Deprecated PchScsSdioMode (PCH_SCS_DEV_SD_MODE enum) for= ScsSdSwitch in PCH_SCS_CONFIG + - Add HSIO RX and TX EQ policy for PCIe and SATA + - Add ComplianceTestMode in PCH_PCIE_CONFIG + + Revision 6: Updated version + - Add DisableEnergyReport in PCH_PM_CONFIG + + + Revision 7: Updated version + - Deprecated Enabled as Acpi device option of DeviceEnable= in PCH_SKYCAM_CIO2_CONFIG + - Add PCH_SKYCAM_CIO2_FLS_CONFIG with the following elemen= ts: + - PortACtleEnable + - PortBCtleEnable + - PortCCtleEnable + - PortDCtleEnable + - PortACtleCapValue + - PortBCtleCapValue + - PortCCtleCapValue + - PortDCtleCapValue + - PortACtleResValue + - PortBCtleResValue + - PortCCtleResValue + - PortDCtleResValue + - PortATrimEnable + - PortBTrimEnable + - PortCTrimEnable + - PortDTrimEnable + - PortADataTrimValue + - PortBDataTrimValue + - PortCDataTrimValue + - PortDDataTrimValue + - PortAClkTrimValue + - PortBClkTrimValue + - PortCClkTrimValue + - PortDClkTrimValue + - Rename and reorder the policies for better understanding. + - HsioTxOutDownscaleAmpAd3GbsEnable to HsioTxGen1Downsca= leAmpEnable + - HsioTxOutDownscaleAmpAd6GbsEnable to HsioTxGen2Downsca= leAmpEnable + - HsioTxOutDownscaleAmpAd3Gbs to HsioTxGen2DownscaleAmp + - HsioTxOutDownscaleAmpAd6Gbs to HsioTxGen2DownscaleAmp + - Update SerialIo DevMode default to PCI mode. + + + Revision 8: Updated version + - Deprecate GP27WakeFromDeepSx and add LanWakeFromDeepSx t= o align EDS naming + - Add ShowSpiController policy and PCH_SPI_CONFIG. + - Add DspUaaCompliance in PCH_HDAUDIO_CONFIG + - Add PchPcieEqHardware support in PCH_PCIE_EQ_METHOD + + + Revision 9: Updated version + - Add DebugUartNumber and EnableDebugUartAfterPost in PCH_= SERIAL_IO_CONFIG + - Add DetectTimeoutMs in PCH_PCIE_CONFIG + - Add PciePllSsc in PCH_PM_CONFIG + + + Revision 10: Updated version + - Add HsioTxDeEmph in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmp in PCH_USB30_PORT_CONFIG + - Add HsioTxDeEmphEnable in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmpEnable in PCH_USB30_PORT_CONFIG + + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAdEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAd + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmpEn= able + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmp + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmpEn= able + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmp + + - Add PCH_HSIO_SATA_CONFIG HsioSataConfig in PCH_POLICY + - Add HsioRxGen1EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen1EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_SATA_PORT_L= ANE + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + + - Add PCH_HSIO_PCIE_CONFIG HsioPcieConfig in PCH_POLICY + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtleEnable + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtle + - Add HsioRxSetCtleEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioRxSetCtle in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen1DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen2DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_C= ONFIG + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmph in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5Enable in PCH_HSIO_PCIE_LANE_CONF= IG + - Add HsioTxGen2DeEmph3p5 in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0Enable in PCH_HSIO_PCIE_LANE_CONF= IG + - Add HsioTxGen2DeEmph6p0 in PCH_HSIO_PCIE_LANE_CONFIG + + - Add DisableDsxAcPresentPulldown in PCH_PM_CONFIG + - Add DynamicPowerGating in PCH_SMBUS_CONFIG + - Add ZpOdd in PCH_SATA_PORT_CONFIG + - Add Uptp and Dptp in PCH_PCIE_ROOT_PORT_CONFIG + - Add PCH_PCIE_CONFIG2 PcieConfig2 in PCH_POLICY + + + Revision 11: Updated version + - Add DisableComplianceMode in PCH_USB_CONFIG + + + Revision 12: Updated version + - Add PmcReadDisable in PCH_PM_CONFIG + - Add CapsuleResetType in PCH_PM_CONFIG + - Add RpFunctionSwap in PCH_PCIE_CONFIG + + + Revision 13: Update version + - Add DisableNativePowerButton in PCH_PM_CONFIG + - Add MaxPayload in PCH_PCIE_ROOT_PORT_CONFIG + - Add IDispCodecDisconnect in PCH_HDAUDIO_CONFIG + Revision 13a: Server updates + - Add HsioIcfgAdjLimitLoEnable + - Add HsioIcfgAdjLimitLo + - Add HsioSampOffstEvenErrSpEnable + - Add HsioSampOffstEvenErrSp + - Add HsioRemainingSamplerOffEnable + - Add HsioRemainingSamplerOff + - Add HsioVgaGainCal + in PCH_HSIO_PCIE_LANE_CONFIG + + **/ + UINT8 Revision; + + UINT8 Port80Route; ///< Control where the P= ort 80h cycles are sent, 0: LPC; 1: PCI. + UINT16 AcpiBase; ///< Power management I/= O base address. Default is 0x1800. + UINT32 Rsvd; + /// + /// PCH General configuration + /// + PCH_GENERAL_CONFIG PchConfig; + /// + /// This member describes PCI Express controller's related configuration. + /// + PCH_PCIE_CONFIG PcieConfig; + /** + SATA controller's related configuration. + SATA configuration that decides which Mode the SATA controller should = operate in + and whether PCH SATA TEST mode is enabled. + **/ + PCH_SATA_CONFIG SataConfig; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG UsbConfig; + /** + This member describes IOAPIC related configuration. + Determines IO APIC ID and IO APIC Range. + **/ + PCH_IOAPIC_CONFIG IoApicConfig; + /// + /// This member describes HPET related configuration. + /// + PCH_HPET_CONFIG HpetConfig; + /// + /// This member describes the Intel HD Audio (Azalia) related configurat= ion. + /// + PCH_HDAUDIO_CONFIG HdAudioConfig; + /// + /// LAN controller settings + /// + PCH_LAN_CONFIG LanConfig; + /// + /// This member describes SMBus related configuration. + /// + PCH_SMBUS_CONFIG SmbusConfig; + /// + /// This member describes LockDown related configuration. + /// + PCH_LOCK_DOWN_CONFIG LockDownConfig; + /// + /// This member describes Thermal related configuration. + /// + PCH_THERMAL_CONFIG ThermalConfig; + /// + /// This member describes miscellaneous platform power management config= urations. + /// + PCH_PM_CONFIG PmConfig; + /// + /// This member describes DMI related configuration. + /// + PCH_DMI_CONFIG DmiConfig; + /// + /// This member describes the expected configuration of the PCH for Seri= al IRQ. + /// + PCH_LPC_SIRQ_CONFIG SerialIrqConfig; + /// + /// This member describes interrupt settings for PCH. + /// + PCH_INTERRUPT_CONFIG PchInterruptConfig; + /// + /// This member describes TraceHub settings for PCH. + /// + PCH_TRACE_HUB_CONFIG PchTraceHubConfig; + /// + /// This member describes the enabling of emulation for port 61h + /// + PCH_PORT61H_SMM_CONFIG Port61hSmmConfig; + /// + /// This member describes the Flash Protection related configuration + /// + PCH_FLASH_PROTECTION_CONFIG FlashProtectConfig; + /// + /// This member describes the sSata related configuration + /// + PCH_SATA_CONFIG sSataConfig; + /// + /// This member contains WDT enable configuration. + /// + PCH_WDT_CONFIG WdtConfig; + /// + /// This member contains P2SB configuration. + /// + PCH_P2SB_CONFIG P2sbConfig; + /// + /// This member contains DCI configuration. + /// + PCH_DCI_CONFIG DciConfig; + + /// + /// Platform specific common policies that used by several silicon compo= nents. + /// + /// + /// Temp Bus Number range available to be assigned to each root port and= its downstream + /// devices for initialization of these devices before PCI Bus enumerati= on. + /// + UINT8 TempPciBusMin; + UINT8 TempPciBusMax; + /// + /// Temporary Memory Base Address for PCI devices to be used to initiali= ze MMIO registers. + /// Minimum size is 2MB bytes + /// + UINT32 TempMemBaseAddr; + /// + /// This member contains LPC configuration. + /// + PCH_LPC_CONFIG LpcConfig; + /// + /// This member describes SkyCam CIO2 FLS registers configuration. + /// + PCH_SKYCAM_CIO2_FLS_CONFIG PchCio2FlsConfig; + /// + /// This member contains SPI configuration. + /// + PCH_SPI_CONFIG SpiConfig; + /// + /// This member describes HSIO settings for SATA controller + /// + PCH_HSIO_SATA_CONFIG HsioSataConfig; + /// + /// This member describes HSIO settings for second SATA controller + /// + PCH_HSIO_SATA_CONFIG HsiosSataConfig; + /// + /// This member describes HSIO settings for PCIe controller + /// + PCH_HSIO_PCIE_CONFIG HsioPcieConfig; + /// + /// This member describes HSIO settings for FIA WM20 PCIe + /// + PCH_HSIO_PCIE_WM20_CONFIG HsioPcieConfigFIAWM20; + /// + /// This is the extension of PCIE CONFIG + /// + PCH_PCIE_CONFIG2 PcieConfig2; + + PCH_ADR_CONFIG AdrConfig; + + +}; + +#pragma pack (pop) + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pc= hReservedResources.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/PchReservedResources.h new file mode 100644 index 0000000000..df9762365f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReserv= edResources.h @@ -0,0 +1,82 @@ +/** @file + PCH preserved MMIO resource definitions. + + @copyright + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** +#ifdef SERVER_BIOS_FLAG + SKX map: +#endif //SERVER_BIOS_FLAG + PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused = | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode = | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused = | + | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR = | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode = | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +-----------------------------------------------------------------------= --+ + +#ifdef SERVER_BIOS_FLAG + HSX map: + PCH preserved MMIO range, from 0xFC000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +---------------------------------------------------------------------= ----+ + | Size | Start | End | Usage = | + | 256 KB | 0xFC0C0000 | 0xFC0FFFFF | TraceHub FW BAR = | + | 1 MB | 0xFC100000 | 0xFC1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFC200000 | 0xFC3FFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused = | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mod= e | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused = | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode= | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +---------------------------------------------------------------------= ----+ +#endif //SERVER_BIOS_FLAG +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved = MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device= in ACPI mode +#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB + +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MM= IO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB M= MIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MM= IO base address +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR = in ACPI mode +#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp= address for misc usage +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pc= ieRegs.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pcie= Regs.h new file mode 100644 index 0000000000..9ee146b941 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h @@ -0,0 +1,288 @@ +/** @file + Register names for PCIE standard register + Conventions: + Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#include + +// +// PCI type 0 Header +// +#define R_PCI_PI_OFFSET 0x09 +#define R_PCI_SCC_OFFSET 0x0A +#define R_PCI_BCC_OFFSET 0x0B + +// +// PCI type 1 Header +// +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Reg= ister +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordin= ate Bus Number +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondar= y Bus Number +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary = Bus Number +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN = | B_PCI_BRIDGE_BNUM_SCBN) + +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and L= imit Register + +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base an= d Limit Register +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory L= imit +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory B= ase + +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable M= emory Base and Limit Register +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetch= able Memory Limit +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit I= ndicator +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetch= able Memory Base +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit I= ndicator + +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable M= emory Base Upper 32-Bit Register +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF + +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable M= emory Limit Upper 32-Bit Register +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF + +// +// PCIE capabilities register +// +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capabilit= y Capability ID Pointer + +// +// PCI Express Capability List Register (CAPID:10h) +// +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Ca= pabilities Register (Offset 02h) +#define S_PCIE_XCAP 2 +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implement= ed +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BI= T4) ///< Device/Port Type +#define N_PCIE_XCAP_DT 4 + +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabil= ities Register (Offset 04h) +#define S_PCIE_DCAP 4 +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) /= //< Endpoint L1 Acceptable Latency +#define N_PCIE_DCAP_E1AL 9 +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///= < Endpoint L0s Acceptable Latency +#define N_PCIE_DCAP_E0AL 6 +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///= < Max_Payload_Size Supported + +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control= Register (Offset 08h) +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///= < Max_Payload_Size +#define N_PCIE_DCTL_MPS 5 +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Re= quest Reporting Enable +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Re= porting Enable +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Erro= r Reporting Enable +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Er= ror Reporting Enable + +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status = Register (Offset 0Ah) +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions P= ending +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Dete= cted +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Re= quest Detected +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error De= tected +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Erro= r Detected +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Er= ror Detected + +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilit= ies Register (Offset 0Ch) +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optional= ity Compliance +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power M= anagement +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) = ///< L1 Exit Latency +#define N_PCIE_LCAP_EL1 15 +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) = ///< L0s Exit Latency +#define N_PCIE_LCAP_EL0 12 +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Act= ive State Power Management (ASPM) Support +#define B_PCIE_LCAP_APMS_L0S BIT10 +#define B_PCIE_LCAP_APMS_L1 BIT11 +#define N_PCIE_LCAP_APMS 10 +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum = Link Width +#define N_PCIE_LCAP_MLW 4 +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Max Link Speed +#define V_PCIE_LCAP_MLS_GEN3 3 + +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control R= egister (Offset 10h) +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock P= ower Management +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock C= onfiguration +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Activ= e State Power Management (ASPM) Control +#define V_PCIE_LCTL_ASPM_L0S 1 +#define V_PCIE_LCTL_ASPM_L1 2 +#define V_PCIE_LCTL_ASPM_L0S_L1 3 + +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Re= gister (Offset 12h) +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Lay= er Link Active +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Co= nfiguration +#define B_PCIE_LSTS_LT BIT11 ///< Link Training +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated L= ink Width +#define N_PCIE_LSTS_NLW 4 +#define V_PCIE_LSTS_NLW_1 0x0010 +#define V_PCIE_LSTS_NLW_2 0x0020 +#define V_PCIE_LSTS_NLW_4 0x0040 +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link= Speed +#define V_PCIE_LSTS_CLS_GEN1 1 +#define V_PCIE_LSTS_CLS_GEN2 2 +#define V_PCIE_LSTS_CLS_GEN3 3 + +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilit= ies Register (Offset 14h) +#define S_PCIE_SLCAP 4 +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical= Slot Number +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Pow= er Limit Scale +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Pow= er Limit Value +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capab= le +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surpr= ise + +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control R= egister (Offset 18h) +#define S_PCIE_SLCTL 2 +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Inter= rupt Enable +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detec= t Changed Enable + +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Re= gister (Offset 1Ah) +#define S_PCIE_SLSTS 2 +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detec= t State +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detec= t Changed + +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control R= egister (Offset 1Ch) +#define S_PCIE_RCTL 2 +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt = Enable +#define B_PCIE_RCTL_SFE BIT2 ///< System Error o= n Fatal Error Enable +#define B_PCIE_RCTL_SNE BIT1 ///< System Error o= n Non-Fatal Error Enable +#define B_PCIE_RCTL_SCE BIT0 ///< System Error o= n Correctable Error Enable + +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Re= gister (Offset 20h) +#define S_PCIE_RSTS 4 + +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabil= ities 2 Register (Offset 24h) +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBF= F Supported +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism= Supported + +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control= 2 Register (Offset 28h) +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBF= F Enable +#define N_PCIE_DCTL2_OBFFEN 13 +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAK= E# signaling +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism= Enable +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Tim= eout Disable +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BI= T0) ///< Completion Timeout Value +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA + +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2= Register (Offset 30h) +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-= emphasis (0 =3D -6dB, 1 =3D -3.5dB) +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Target Link Speed +#define V_PCIE_LCTL2_TLS_GEN1 1 +#define V_PCIE_LCTL2_TLS_GEN2 2 +#define V_PCIE_LCTL2_TLS_GEN3 3 + +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 = Register (Offset 32h) +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalizat= ion Request +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization P= hase 3 Successful +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization P= hase 2 Successful +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization P= hase 1 Successful +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization C= omplete +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emp= hasis Level + +// +// PCI Power Management Capability (CAPID:01h) +// +#define R_PCIE_PMC_OFFSET 0x02 ///< Power Manageme= nt Capabilities Register +#define S_PCIE_PMC 2 +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 |= BIT12 | BIT11) ///< PME Support +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock + +#define R_PCIE_PMCS_OFFST 0x04 ///< Power Manageme= nt Status/Control Register +#define S_PCIE_PMCS 4 +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clo= ck Control Enable +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power= State +#define V_PCIE_PMCS_PS_D0 0 +#define V_PCIE_PMCS_PS_D3H 3 + +// +// PCIE Extension Capability Register +// +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Cap= ability Offset +#define N_PCIE_EXCAP_NCO 20 +#define V_PCIE_EXCAP_NCO_LISTEND 0 +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capabili= ty Version +#define N_PCIE_EXCAP_CV 16 +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capabili= ty ID + +// +// Advanced Error Reporting Capability (CAPID:0001h) +// +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable = Error Mask Register +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Ti= meout Mask +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Co= mpletion + +// +// ACS Extended Capability (CAPID:000Dh) +// +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability= Register +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control = Register (NOTE: register size in PCIE spce is not match the PCH register si= ze) + +// +// Secondary PCI Express Extended Capability Header (CAPID:0019h) +// +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3= Register +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equali= zation +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Sta= tus +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan= 1 Equalization Control Register (Offset 0Ch) +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream= Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_UPL1TP 24 +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstre= am Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_DPL1TP 16 +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream= Port Transmitter Preset +#define N_PCIE_EX_L01EC_UPL0TP 8 +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstre= am Port Transmitter Preset +#define N_PCIE_EX_L01EC_DPL0TP 0 + +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lan= e 3 Equalization Control Register (Offset 10h) +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream= Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL3TP 24 +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstre= am Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL3TP 16 +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream= Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL2TP 8 +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstre= am Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL2TP 0 + + +// +// L1 Sub-States Extended Capability Register (CAPID:001Eh) +// +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States = Capabilities +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States = Control 1 +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States = Control 2 +#define N_PCIE_EX_L1SCTL2_POWT 3 + +// +// Base Address Offset +// +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address= Register 0 +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address= Register 1 +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address= Register 2 +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address= Register 3 +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address= Register 4 +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address= Register 5 + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pp= i/PchHsioPtssTable.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/= Include/Ppi/PchHsioPtssTable.h new file mode 100644 index 0000000000..d0ade33035 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHs= ioPtssTable.h @@ -0,0 +1,31 @@ +/** @file + PCH policy PPI produced by a platform driver specifying HSIO PTSS Table. + This PPI is consumed by the PCH PEI modules. This is deprecated. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HSIO_PTSS_TABLE_H_ +#define _PCH_HSIO_PTSS_TABLE_H_ + +/// +/// HSIO PTSS table PPI GUID. +/// +extern EFI_GUID gPchHsioPtssTablePpiGuid; + +/// +/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH. +/// +typedef struct { + UINT8 SbPortID; + UINT8 LaneNum; + UINT8 PhyMode; + UINT16 Offset; + UINT32 Value; + UINT32 BitMask; +} PCH_SBI_PTSS_HSIO_TABLE; + +#endif // _PCH_HSIO_PTSS_TABLE_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pp= i/PchPcieDeviceTable.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLb= g/Include/Ppi/PchPcieDeviceTable.h new file mode 100644 index 0000000000..6766805f68 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPc= ieDeviceTable.h @@ -0,0 +1,126 @@ +/** @file + PCH policy PPI produced by a platform driver specifying PCIe device over= rides. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_DEVICE_TABLE_H_ +#define _PCH_PCIE_DEVICE_TABLE_H_ + + +// +// PCIe device table PPI GUID. +// +extern EFI_GUID gPchPcieDeviceTablePpiGuid; + +typedef enum { + PchPcieOverrideDisabled =3D 0, + PchPcieL1L2Override =3D 0x01, + PchPcieL1SubstatesOverride =3D 0x02, + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, + PchPcieLtrOverride =3D 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + UINT32 Reserved; +} PCH_PCIE_DEVICE_OVERRIDE; + +#endif // _PCH_PCIE_DEVICE_TABLE_H_ + diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pp= i/PchPolicy.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include= /Ppi/PchPolicy.h new file mode 100644 index 0000000000..b75613a5c7 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPo= licy.h @@ -0,0 +1,23 @@ +/** @file + PCH policy PPI produced by a platform driver specifying various + expected PCH settings. This PPI is consumed by the PCH PEI modules + and carried over to PCH DXE modules. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_PPI_H_ +#define _PCH_POLICY_PPI_H_ + +#include +#include + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + + +typedef struct _PCH_POLICY PCH_POLICY_PPI; + +#endif // PCH_POLICY_PPI_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pp= i/PchReset.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/= Ppi/PchReset.h new file mode 100644 index 0000000000..2b5afbb929 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchRe= set.h @@ -0,0 +1,95 @@ +/** @file + PCH Reset PPI + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PPI PCH_RESET_PPI; +typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI; + +// +// Related Definitions +// +// +// PCH Reset Types +// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the Host controller. + + @param[in] This Pointer to the PCH_RESET_PPI instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset= , WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalRese= tWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_PPI_API) ( + IN PCH_RESET_PPI *This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycl= e, Globalreset. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. O= r, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN EFI_RESET_TYPE ResetType + ); + +/** + Interface structure to execute Pch Reset from the Host controller. +**/ +struct _PCH_RESET_PPI { + PCH_RESET_PPI_API Reset; +}; + +/** + This ppi is used to execute PCH Reset from the Host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Res= et Interface + for DXE and PEI environments, respectively. If other drivers need to run= their + callback function right before issuing the reset, they can install PCH R= eset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PPI { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pp= i/Spi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/S= pi.h new file mode 100644 index 0000000000..c0f126ef41 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h @@ -0,0 +1,28 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiSe= rvice pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pr= ivate/Library/PchSpiCommonLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/South= ClusterLbg/Include/Private/Library/PchSpiCommonLib.h new file mode 100644 index 0000000000..f93740f4f0 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/L= ibrary/PchSpiCommonLib.h @@ -0,0 +1,458 @@ +/** @file + Header file for the PCH SPI Common Driver. + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_COMMON_LIB_H_ +#define _PCH_SPI_COMMON_LIB_H_ + +#include + +// +// Maximum time allowed while waiting the SPI cycle to complete +// Wait Time =3D 6 seconds =3D 6000000 microseconds +// Wait Period =3D 10 microseconds +// +#define SPI_WAIT_TIME 6000000 ///< Wait Time =3D 6 seconds =3D 60000= 00 microseconds +#define SPI_WAIT_PERIOD 10 ///< Wait Period =3D 10 microseconds + +/// +/// Flash cycle Type +/// +typedef enum { + FlashCycleRead, + FlashCycleWrite, + FlashCycleErase, + FlashCycleReadSfdp, + FlashCycleReadJedecId, + FlashCycleWriteStatus, + FlashCycleReadStatus, + FlashCycleMax +} FLASH_CYCLE_TYPE; + +/// +/// Flash Component Number +/// +typedef enum { + FlashComponent0, + FlashComponent1, + FlashComponentMax +} FLASH_COMPONENT_NUM; + +/// +/// Private data structure definitions for the driver +/// +#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + PCH_SPI_PROTOCOL SpiProtocol; + UINT16 PchAcpiBase; + UINTN PchSpiBase; + UINT16 ReadPermission; + UINT16 WritePermission; + UINT32 SfdpVscc0Value; + UINT32 SfdpVscc1Value; + UINT16 PchStrapBaseAddr; + UINT16 PchStrapSize; + UINT16 CpuStrapBaseAddr; + UINT16 CpuStrapSize; + UINT8 NumberOfComponents; + UINT32 Component1StartAddr; + UINT32 TotalFlashSize; +} SPI_INSTANCE; + +#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol= , PCH_SPI_PRIVATE_DATA_SIGNATURE) + +// +// Function prototypes used by the SPI protocol. +// + +/** + Initialize an SPI protocol instance. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +SpiProtocolConstructor ( + IN UINT8 PchId, + IN SPI_INSTANCE *SpiInstance + ); + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @param[in] SpiBaseAddress SPI base address + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + UINTN SpiBaseAddress + ); + +/** + This function is a hook for Spi to enable BIOS Write Protect + + @param[in] SpiBaseAddress SPI base address + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + UINTN SpiBaseAddress + ); + +/** + Acquire pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval PchSpiBar0 return SPI MMIO address +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Release pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Check if a save and restore of the SPI controller state is necessary + + @retval TRUE It's necessary to save and restore SPI controller state + @retval FALSE It's not necessary to save and restore SPI controller st= ate +**/ +BOOLEAN +IsSpiControllerSaveRestoreEnabled ( + VOID + ); + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashRead ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWrite ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashErase ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadSfdp ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadJedecId ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWriteStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiProtocolGetRegionAddress ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadPchSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Function updates entire softstrap region. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL ins= tance. + @param[in] ByteCount Number of bytes in SoftStrap data porti= on of the SPI cycle + @param[out] Buffer Pointer to the PCH Soft Strap Values = to be writen. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not va= lid. + @exception EFI_UNSUPPORTED Command not supported. + @retval EFI_DEVICE_ERROR Device error, command aborts abnorm= ally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolUpdatePchSoftStraps ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + This function sends the programmed SPI command to the slave device. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the dada received or sent during the SPI cycle. + + @retval EFI_SUCCESS SPI command completes successfully. + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly. + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in= hardware sequencing mode + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. +**/ +EFI_STATUS +SendSpiCmd ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN FLASH_CYCLE_TYPE FlashCycleType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN OUT UINT8 *Buffer + ); + +/** + Wait execution cycle to complete on the SPI interface. + + @param[in] This The SPI protocol instance + @param[in] PchSpiBar0 Spi MMIO base address + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check + + @retval TRUE SPI cycle completed on the interface. + @retval FALSE Time out while waiting the SPI cycle to = complete. + It's not safe to program the next comman= d on the SPI interface. +**/ +BOOLEAN +WaitForSpiCycleComplete ( + IN PCH_SPI_PROTOCOL *This, + IN UINTN PchSpiBar0, + IN BOOLEAN ErrorCheck + ); + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pr= otocol/PchReset.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Inc= lude/Protocol/PchReset.h new file mode 100644 index 0000000000..f951b381a6 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/= PchReset.h @@ -0,0 +1,114 @@ +/** @file + PCH Reset Protocol + + @copyright + Copyright 2011 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + +#include + +#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData" +extern EFI_GUID gEfiCapsuleVendorGuid; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; +extern EFI_GUID gPchPowerCycleResetGuid; +extern EFI_GUID gPchGlobalResetGuid; +extern EFI_GUID gPchGlobalResetWithEcGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Platform Specific ResetData +// +#define PCH_POWER_CYCLE_RESET_GUID \ + { \ + 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d= , 0x24 } \ + } + +#define PCH_GLOBAL_RESET_GUID \ + { \ + 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e= , 0x40 } \ + } + +#define PCH_GLOBAL_RESET_WITH_EC_GUID \ + { \ + 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9= , 0x93 } \ + } + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH sizeof (PCH_PLATFORM_SPECIFIC_R= ESET_STRING) + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + + +// +// Member functions +// +/** + Execute Pch Reset from the Host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instan= ce. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL *This, + IN PCH_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific re= set. +**/ +typedef +VOID * +(EFIAPI *PCH_RESET_GET_RESET_DATA) ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ); + +/** + Interface structure to execute Pch Reset from the Host controller. +**/ +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; + PCH_RESET_GET_RESET_DATA GetResetData; +}; + +#endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Pr= otocol/Spi.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/= Protocol/Spi.h new file mode 100644 index 0000000000..45560d67f5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/= Spi.h @@ -0,0 +1,305 @@ +/** @file + This file defines the PCH SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSpiProtocolGuid; +extern EFI_GUID gPchSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionSecondaryBios, + FlashRegionuCodePatch, + FlashRegionEC, + FlashRegionDeviceExpansion2, + FlashRegionIE, + FlashRegion10Gbe_A, + FlashRegion10Gbe_B, + FlashRegion13, + FlashRegion14, + FlashRegion15, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations t= hrough the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data fro= m the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to= the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some ar= ea on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP dat= a from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id= from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the sta= tus register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status r= egister in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI r= egion base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft= Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft= Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 12 Jul 2021 17:42:04 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456227" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456227" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:57 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422942" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:54 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 07/17] WhitleySiliconPkg: Add PCH Libraries Date: Mon, 12 Jul 2021 17:41:21 -0700 Message-Id: <20210713004131.1782-8-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: KxMjT1AYRPuPCMRn7MzGkGjVx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136924; bh=6MdqscHljtE5gImRp6kH3aZ31Kyi97n+Di1q0LZ70XU=; h=Cc:Date:From:Reply-To:Subject:To; b=DTm12NZDLjYKxNP94Zv3Yc3MB/kjkYna1QVE15IzHPZYmyG30uufm0XsR0cOi5mt3o4 9jE4n24RXfsTemIiANjYcXXB8135bPb7gd+Qfn+fYP5KvOOGoW7pSYVwNWfnBwZYfnNM2 MyVx0/vztNu1k92gLLqJZNrr4nHQVn1va2g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136925467100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 224 ++++++++++++++++++ 1 file changed, 224 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Lib= rary/PeiDxeSmmGpioLib/GpioLibrary.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Library/Pe= iDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClu= sterLbg/Library/PeiDxeSmmGpioLib/GpioLibrary.h new file mode 100644 index 0000000000..7f22e8b342 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Library/PeiDxeSmm= GpioLib/GpioLibrary.h @@ -0,0 +1,224 @@ +/** @file + Header file for GPIO Lib implementation. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_LIBRARY_H_ +#define _GPIO_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + GPIO_PAD Pad; + GPIO_PAD_MODE Mode; +} GPIO_PAD_NATIVE_FUNCTION; + + +// BIT15-0 - pad number +// BIT31-16 - group info +// BIT23- 16 - group index +// BIT31- 24 - chipset ID +#define PAD_INFO_MASK 0x0000FFFF +#define GROUP_INFO_POSITION 16 +#define GROUP_INFO_MASK 0xFFFF0000 +#define GROUP_INDEX_MASK 0x00FF0000 +#define UNIQUE_ID_MASK 0xFF000000 +#define UNIQUE_ID_POSITION 24 + +#define GPIO_PAD_DEF(Group,Pad) (UINT32)((Group << 16) + Pad) +#define GPIO_GROUP_DEF(Index,ChipsetId) (Index | (ChipsetId << 8)) +#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF) +#define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX ((Pad >= > 16)) +#define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF) +#define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24) +#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32) +#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u) + + +// +// Unique ID used in GpioPad defines +// +#define GPIO_SKL_H_CHIPSET_ID 0x1 +#define GPIO_SKL_LP_CHIPSET_ID 0x2 + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +// +// Structure for storing information about registers offset, community, +// maximal pad number for available groups +// +typedef struct { + PCH_SBI_PID Community; + UINT32 PadOwnOffset; + UINT32 HostOwnOffset; + UINT32 GpiIsOffset; + UINT32 GpiIeOffset; + UINT32 GpiGpeStsOffset; + UINT32 GpiGpeEnOffset; + UINT32 SmiStsOffset; + UINT32 SmiEnOffset; + UINT32 NmiStsOffset; + UINT32 NmiEnOffset; + UINT32 PadCfgLockOffset; + UINT32 PadCfgLockTxOffset; + UINT32 PadCfgOffset; + UINT32 PadPerGroup; +} GPIO_GROUP_INFO; + +// +// If in GPIO_GROUP_INFO structure certain register doesn't exist +// it will have value equal to NO_REGISTER_FOR_PROPERTY +// +#define NO_REGISTER_FOR_PROPERTY (~0u) + + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ); + + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINTN *GpioGroupInfoTableLength + ); + +/** + This procedure will set GPIO mode + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +SetGpioPadMode ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ); + +/** + This procedure will get GPIO mode + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GetGpioPadMode ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ); + +/** + This function checks if GPIO pin is a GSPI chip select pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsGpioPadAGSpiCsbPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + This function checks if GPIO pin is a SataDevSlp pin + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsPadASataDevSlpPin ( + IN UINT8 PchId, + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + Check if given GPIO Pad is locked + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... = n - Non-Legacy PCH) + @param[in] GroupIndex GPIO group index + @param[in] PadNumber GPIO pad number + + @retval TRUE Pad is locked + @retval FALSE Pad is not locked +**/ +BOOLEAN +GpioIsPadLocked ( + IN UINT8 PchId, + IN UINT32 GroupIndex, + IN GPIO_PAD PadNumber + ); + +#endif // _GPIO_LIBRARY_H_ --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 12 Jul 2021 17:42:03 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456228" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456228" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422945" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:54 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 08/17] WhitleySiliconPkg: Add Security Includes Date: Mon, 12 Jul 2021 17:41:22 -0700 Message-Id: <20210713004131.1782-9-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: EGjAmWp9G0gQK0bcItc7QEudx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136928; bh=emr0FjaJKaIHm0b+lC5czkXzlAL2o1bVKseiyeJeOFQ=; h=Cc:Date:From:Reply-To:Subject:To; b=tFbuykxYuSU8UA+9W1WffKq7uGU5ZqJARtzmV5ePLyTf3Ok8gA0W8wP8q7w7QF6nZYH yjjm/9b+dxdVif+ic+I5BwiXC0/AgEKu84AikbMv3LnJAg/C6wR4rFNVRLpZIof4kRl8L GUg1DPX1thS0xhuwu3H+zbd6hCD49f1A3Ow= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136929782100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../SecurityIp/SecurityIpMkTme1v0_Inputs.h | 25 ++++++++++++ .../SecurityIp/SecurityIpMkTme1v0_Outputs.h | 18 +++++++++ .../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 39 +++++++++++++++++++ .../SecurityIp/SecurityIpSgxTem1v0_Outputs.h | 22 +++++++++++ .../Guid/SecurityIp/SecurityIpTdx1v0_Inputs.h | 13 +++++++ .../SecurityIp/SecurityIpTdx1v0_Outputs.h | 11 ++++++ .../Include/Guid/SecurityPolicy_Flat.h | 22 +++++++++++ 7 files changed, 150 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpMkTme1v0_Inputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpMkTme1v0_Outputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpSgxTem1v0_Inputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpSgxTem1v0_Outputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpTdx1v0_Inputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityIp/SecurityIpTdx1v0_Outputs.h create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/S= ecurityPolicy_Flat.h diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpMkTme1v0_Inputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/I= nclude/Guid/SecurityIp/SecurityIpMkTme1v0_Inputs.h new file mode 100644 index 0000000000..4c48ca19ee --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpMkTme1v0_Inputs.h @@ -0,0 +1,25 @@ +/** @file + Provides data structure information used by SiliconIp MK-TME + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// TME +// +UINT8 EnableTme; // TME Enable +UINT8 EnableTmeCR; // Exclude Crystal Ridge memory fro= m encryption. + +// +// MK-TME +// +UINT8 EnableMktme; // MK-TME Enable + +UINT8 ReservedS234; +UINT8 ReservedS235; +UINT64 ReservedS236; +UINT64 ReservedS237; +UINT8 ReservedS238; diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpMkTme1v0_Outputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/= Include/Guid/SecurityIp/SecurityIpMkTme1v0_Outputs.h new file mode 100644 index 0000000000..3a6262a658 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpMkTme1v0_Outputs.h @@ -0,0 +1,18 @@ +/** @file + Provides data structure information used by SiliconIp MK-TME + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// MK-TME +// +// NAK - Not a knob, used just for indication +UINT8 TmeCapability; // TME Capable +UINT8 TmeCrSupport; // Flag used to check if Crystal Ridge is supported i= n UEFI +UINT8 MktmeCapability; // MK-TME Capable +UINT16 MktmeMaxKeys; // Max number of keys used for encryption +UINT8 MkTmeKeyIdBits; // Used to suppress setup menu key-splits \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpSgxTem1v0_Inputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/= Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h new file mode 100644 index 0000000000..2deabd0b50 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpSgxTem1v0_Inputs.h @@ -0,0 +1,39 @@ +/** @file + Provides data structure information used by SiliconIp SGX-TEM + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// SGX +// +UINT8 EnableSgx; +UINT8 SgxFactoryReset; // Delete all registration data, if= SGX enabled force IPE/FirstBinding flow +UINT64 PrmrrSize; // SGX PRMRR size +UINT64 ReservedS239; +UINT8 SgxQoS; // SGX Quality of Service +UINT8 SgxAutoRegistrationAgent; +UINT8 SgxPackageInfoInBandAccess; // Expose Package Info to OS +UINT8 EpochUpdate; +UINT64 SgxEpoch0; // SGX EPOCH0 value {0 - 0xFFFFFFFF= FFFFFFFF} +UINT64 SgxEpoch1; // SGX EPOCH1 value {0 - 0xFFFFFFFF= FFFFFFFF} +UINT8 SgxLeWr; // Flexible Launch Enclave Policy (= Wr En) +UINT64 SgxLePubKeyHash0; // Launch Enclave Hash 0 +UINT64 SgxLePubKeyHash1; // Launch Enclave Hash 1 +UINT64 SgxLePubKeyHash2; // Launch Enclave Hash 2 +UINT64 SgxLePubKeyHash3; // Launch Enclave Hash 3 +// Client SGX - unused in server +UINT8 SgxSinitNvsData; // SGX NVS data from Flash passed d= uring previous boot using CPU_INFO_PROTOCOL.SGX_INFO; + // Pass value of zero if there is n= ot data saved or when SGX is disabled. +UINT8 SgxSinitDataFromTpm; // SGX SVN data from TPM; 0: when S= GX is disabled or TPM is not present or no data + // is present in TPM. +UINT8 SgxDebugMode; + +UINT8 ReservedS240; +UINT8 ReservedS241; +UINT8 ReservedS242; +UINT8 ReservedS243; +UINT8 ReservedS244; diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpSgxTem1v0_Outputs.h b/Silicon/Intel/WhitleySiliconPkg/Security= /Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h new file mode 100644 index 0000000000..45b63b21c5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpSgxTem1v0_Outputs.h @@ -0,0 +1,22 @@ +/** @file + Provides data structure information used by SiliconIp SGX-TEM + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// NAK - Not a knob, used just for indication +UINT8 IsSgxCapable; +UINT8 IsHwCongifSupportedBySgx; // ## PRODUCED by SgxPreMe= mInit +UINT8 CrDimmsPresent; +UINT64 ValidPrmrrBitMap; +UINT64 SprspOrLaterPrmSizeBitmap; // ## PRODUCED by SgxPreMe= mInit +UINT8 ShowEpoch; +UINT8 SkipSignalPpmDone; // ## PRODUCED by SgxEarly= Init + +UINT8 SprspOrLaterIsPrmSizeInvalidated; // ## PRODUCED by SgxPreMe= mInit +UINT8 SprspOrLaterAreHardwarePreconditionsMet; // ## PRODUCED by SgxPreMe= mInit +UINT8 SprspOrLaterAreMemoryPreconditionsMet; // ## PRODUCED by SgxPreMe= minit +UINT8 SprspOrLaterAreSetupPreconditionsMet; // ## PRODUCED by SgxPreMe= mInit diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpTdx1v0_Inputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/Inc= lude/Guid/SecurityIp/SecurityIpTdx1v0_Inputs.h new file mode 100644 index 0000000000..db5081c0aa --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpTdx1v0_Inputs.h @@ -0,0 +1,13 @@ +/** @file + Provides data structure information used by SiliconIp TDX + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +UINT8 EnableTdx; // TDX Enable +UINT8 KeySplit; // TDX/MK-TME key split + +UINT8 ReservedS245; diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Ip/SecurityIpTdx1v0_Outputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/In= clude/Guid/SecurityIp/SecurityIpTdx1v0_Outputs.h new file mode 100644 index 0000000000..d744baefb5 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Secu= rityIpTdx1v0_Outputs.h @@ -0,0 +1,11 @@ +/** @file + Provides data structure information used by SiliconIp TDX + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// NAK - Not a knob, used just for indication +UINT8 TdxCapability; // TDX socket capability \ No newline at end of file diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Security= Policy_Flat.h b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/Secur= ityPolicy_Flat.h new file mode 100644 index 0000000000..ba62b8c3ab --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy_= Flat.h @@ -0,0 +1,22 @@ +/** @file + Provides data structure information used by ServerSecurity features in l= iterally all products + Header is flat and injected directly in SecurityPolicy sructuture and SO= CKET_PROCESSORCORE_CONFIGURATION. + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // Header is flat and injected directly in SecurityPolicy sructuture and= SOCKET_PROCESSORCORE_CONFIGURATION. + // Put common definitons here either directly or via intermediate header= file.. + +// SECURITY_IP_MKTME_1V0 MkTme; +#include "SecurityIp/SecurityIpMkTme1v0_Inputs.h" +#include "SecurityIp/SecurityIpMkTme1v0_Outputs.h" +// SECURITY_IP_SGXTEM_1V0 SgxTem; +#include "SecurityIp/SecurityIpSgxTem1v0_Inputs.h" +#include "SecurityIp/SecurityIpSgxTem1v0_Outputs.h" +// SECURITY_IP_TDX_1V0 Tdx; +#include "SecurityIp/SecurityIpTdx1v0_Inputs.h" +#include "SecurityIp/SecurityIpTdx1v0_Outputs.h" \ No newline at end of file --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77712): https://edk2.groups.io/g/devel/message/77712 Mute This Topic: https://groups.io/mt/84168624/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 16:20:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77711+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77711+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136923; cv=none; d=zohomail.com; s=zohoarc; b=f+D2cDF1aPbCT8mmnYmbAHoY/3MMjxEKI05fuZHvtS8tizKgfk75QAZlIk8EQIzbdtC1EPnuXUnlC/FZpbi03ItZrQq/Ewvc2TjxBUBL5rigIHSCSjQPuIcDWVLWY6Efo2IDJtCdLWkErlOYhujtd6RbsbN2n6ei8bfXPBRN9x0= ARC-Message-Signature: i=1; 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Mon, 12 Jul 2021 17:42:01 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="207059518" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="207059518" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:58 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653422949" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:41:54 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 09/17] WhitleySiliconPkg: Add SiliconPolicyInit Date: Mon, 12 Jul 2021 17:41:23 -0700 Message-Id: <20210713004131.1782-10-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: JxiSKYKz61gw6QW8KWGCrwNCx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136922; bh=+t+gq8il5aW4iY1DAKFAjDS8TnGZt/ZdYZyB0A1R9gA=; h=Cc:Date:From:Reply-To:Subject:To; b=ZUtUhMLznUYo3/TrVUeDFmXF6r/N3wm51Obpl/gfjKQAgU2ulCB0J1HUDVTnrSIkG+Z sBZV26X9wrFRoP0TebbHsYk1lm4tS9yP+fA0LFfll5puZRJwIo3TJDMyZaC7gIoqku1Fr 9s4M0jrPRaXcKbhRp7xpEFYZ0x5T869gmds= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136925352100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../SiliconPolicyInit/SiliconPolicyInitLate.c | 52 +++++++++++++++ .../SiliconPolicyInitLate.inf | 49 +++++++++++++++ .../SiliconPolicyInitPreAndPostMem.c | 63 +++++++++++++++++++ .../SiliconPolicyInitPreAndPostMem.inf | 48 ++++++++++++++ 4 files changed, 212 insertions(+) create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/Silic= onPolicyInitLate.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/Silic= onPolicyInitLate.inf create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/Silic= onPolicyInitPreAndPostMem.c create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/Silic= onPolicyInitPreAndPostMem.inf diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolic= yInitLate.c b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPoli= cyInitLate.c new file mode 100644 index 0000000000..d5c1828cce --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitLa= te.c @@ -0,0 +1,52 @@ +/** @file + SiliconPolicyInitLib DXE. + + This driver initializes silicon policy with the defaults from the silico= n provider. + It publishes a protocol that is consumed by a shim library instance that= provides the functions used by the + common MinPlatformPkg PolicyInit late policy initialization code. + + @copyright + Copyright 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +STATIC SILICON_POLICY_INIT_LIB_PROTOCOL mSiliconPolicyInitLibProtocol =3D { + SiliconPolicyInitLate, + SiliconPolicyDoneLate +}; + +/** + Entry point function + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Protocol installed sucessfully. +**/ +EFI_STATUS +EFIAPI +SiliconPolicyInitLateDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_HANDLE Handle; + + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface (&Handle, &gSiliconPolicyInitLi= bInterfaceGuid, EFI_NATIVE_INTERFACE, &mSiliconPolicyInitLibProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolic= yInitLate.inf b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPo= licyInitLate.inf new file mode 100644 index 0000000000..d6ef987f5b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitLa= te.inf @@ -0,0 +1,49 @@ +## @file +# SiliconPolicyInitLate DXE Boot Services Driver +# +# This driver initializes silicon policy with the defaults from the silico= n provider. +# It publishes a protocol that is consumed by a shim library instance that= provides the functions used by the +# common MinPlatformPkg PolicyInit late silicon init code. +# This driver produces SiliconPolicyInit LATE services. A PEIM provides t= he PRE and POST memory services. +# +# @copyright +# Copyright 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyInitLate + FILE_GUID =3D ff6216f2-d911-44a5-9f48-c174223acc7c + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SiliconPolicyInitLateDxeEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + SiliconPolicyInitLate.c + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenboardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DriverEntryPoint + UefiBootServicesTableLib + SiliconPolicyInitLib + +[Guids] + gSiliconPolicyInitLibInterfaceGuid ## ALWAYS_PRODUCES a PROTOCOL wi= th this GUID + +[Depex] + TRUE diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolic= yInitPreAndPostMem.c b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/Si= liconPolicyInitPreAndPostMem.c new file mode 100644 index 0000000000..5bc410f21f --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitPr= eAndPostMem.c @@ -0,0 +1,63 @@ +/** @file + SiliconPolicyInit PEIM. + + This PEIM initializes silicon policy with the defaults from the silicon = provider. + We publish a PPI that is consumed by a shim library instance that provid= es the functions used by the + common MinPlatformPkg PolicyInit pre and post memory code. + + @copyright + Copyright 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +STATIC SILICON_POLICY_INIT_LIB_PPI mSiliconPolicyInitLibPpi =3D { + SiliconPolicyInitPreMem, + SiliconPolicyDonePreMem, + SiliconPolicyInitPostMem, + SiliconPolicyDonePostMem +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mSiliconPolicyInitLibPpiDescriptor =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gSiliconPolicyInitLibInterfaceGuid, + &mSiliconPolicyInitLibPpi + }; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI +**/ +EFI_STATUS +EFIAPI +SiliconPolicyInitPreAndPostMemPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + // + // Just produce our PPI + // + Status =3D PeiServicesInstallPpi (&mSiliconPolicyInitLibPpiDescriptor); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "EntryPoint: failed to register PPI!\n")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolic= yInitPreAndPostMem.inf b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/= SiliconPolicyInitPreAndPostMem.inf new file mode 100644 index 0000000000..6416457fdb --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitPr= eAndPostMem.inf @@ -0,0 +1,48 @@ +## @file +# SiliconPolicyInitPreAndPostMem PEIM. +# +# This PEIM initializes silicon policy with the defaults from the silicon = provider. +# We publish a PPI that is consumed by a shim library instance that provid= es the functions used by the +# common MinPlatformPkg PolicyInit pre and post memory code. +# This PEIM produces SiliconPolicyInit PRE and POST memory services. A DX= E driver provides the LATE services. +# +# @copyright +# Copyright 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyInitPreAndPostMem + FILE_GUID =3D ca8efb69-d7dc-4e94-aad6-9fb373649161 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SiliconPolicyInitPreAndPostMemPeimEnt= ry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + SiliconPolicyInitPreAndPostMem.c + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + BaseLib + PeiServicesLib + PeimEntryPoint + DebugLib + SiliconPolicyInitLib + +[Guids] + gSiliconPolicyInitLibInterfaceGuid ## ALWAYS_PRODUCES a PPI with th= is GUID + +[Depex] + TRUE --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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, Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 10/17] WhitleyOpenBoardPkg: Add Includes and Libraries Date: Mon, 12 Jul 2021 17:41:24 -0700 Message-Id: <20210713004131.1782-11-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: n7elTEZe6Jqf4UtcheWA7pPjx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136925; bh=FYrrREndofz2Sheil9EM45RBXPgveDhoqnCeM04uCtM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=YIQ+odThgD7PJhulSPeGIgWjnOjiZTj+HOS/zFmST/2EZE2myUW7jdZVcfNGNMqhmc0 853yfFAz4Empl5/xYP2tFtyQNVxpb9OXbF4/iaFrP1ScsPE708S18NS0RMxYHSi8Qu2PC GQvNGBnw5WMdQ/wbi4VG0eIwx5zAXuZLOQ0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136928027100004 Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Include/Dsc/CoreDxeInclude.dsc | 135 ++ ...blePerformanceMonitoringInfrastructure.dsc | 40 + .../Include/Dsc/EnableRichDebugMessages.dsc | 50 + .../Include/Fdf/CommonNvStorageFtwWorking.fdf | 20 + .../Include/Fdf/CommonSpiFvHeaderInfo.fdf | 24 + ...anceMonitoringInfrastructurePostMemory.fdf | 14 + ...manceMonitoringInfrastructurePreMemory.fdf | 11 + .../Include/Fdf/NvStorage512K.fdf | 46 + .../Include/GpioInitData.h | 26 + .../Include/Guid/PlatformVariableCommon.h | 33 + .../Include/Guid/SetupVariable.h | 720 ++++++++ .../Include/Guid/UbaCfgHob.h | 74 + .../WhitleyOpenBoardPkg/Include/IoApic.h | 23 + .../Include/Library/MultiPlatSupportLib.h | 67 + .../Include/Library/PeiPlatformHooklib.h | 17 + .../Include/Library/PlatformClocksLib.h | 87 + .../Include/Library/PlatformOpromPolicyLib.h | 83 + .../Library/PlatformSetupVariableSyncLib.h | 60 + .../Include/Library/PlatformVariableHookLib.h | 47 + .../Include/Library/ReadFfsLib.h | 58 + .../Include/Library/SetupLib.h | 134 ++ .../Include/Library/UbaAcpiUpdateLib.h | 38 + .../Include/Library/UbaBoardSioInfoLib.h | 47 + .../Include/Library/UbaClkGenUpdateLib.h | 49 + .../Include/Library/UbaClocksConfigLib.h | 51 + .../Include/Library/UbaGpioInitLib.h | 26 + .../Include/Library/UbaGpioPlatformConfig.h | 259 +++ .../Include/Library/UbaGpioUpdateLib.h | 51 + .../Library/UbaHsioPtssTableConfigLib.h | 52 + .../Include/Library/UbaIioConfigLib.h | 227 +++ .../Library/UbaIioPortBifurcationInitLib.h | 47 + .../Include/Library/UbaOpromUpdateLib.h | 115 ++ .../Include/Library/UbaPcdUpdateLib.h | 44 + .../Include/Library/UbaPchEarlyUpdateLib.h | 63 + .../Library/UbaPcieBifurcationUpdateLib.h | 130 ++ .../Include/Library/UbaPlatLib.h | 25 + .../Include/Library/UbaSlotUpdateLib.h | 124 ++ .../Include/Library/UbaSoftStrapUpdateLib.h | 57 + .../Include/Library/UbaSystemBoardInfoLib.h | 36 + .../Library/UbaSystemConfigUpdateLib.h | 42 + .../Include/Library/UbaUsbOcUpdateLib.h | 51 + .../Include/OnboardNicStructs.h | 98 ++ .../Include/PchSetupVariable.h | 10 + .../Include/PchSetupVariableLbg.h | 372 ++++ .../WhitleyOpenBoardPkg/Include/PlatDevData.h | 183 ++ .../Include/PlatPirqData.h | 36 + .../Include/Ppi/ExReportStatusCodeHandler.h | 38 + .../Include/Ppi/SmbusPolicy.h | 29 + .../Include/Ppi/UbaCfgDb.h | 144 ++ .../Include/Protocol/LegacyBios.h | 1550 +++++++++++++++++ .../Include/Protocol/LegacyBiosPlatform.h | 752 ++++++++ .../Include/Protocol/PciIovPlatform.h | 72 + .../Include/Protocol/PlatformType.h | 48 + .../Include/Protocol/UbaCfgDb.h | 114 ++ .../Include/Protocol/UbaDevsUpdateProtocol.h | 86 + .../Include/Protocol/UbaMakerProtocol.h | 22 + .../WhitleyOpenBoardPkg/Include/SetupTable.h | 25 + .../WhitleyOpenBoardPkg/Include/SioRegs.h | 251 +++ .../WhitleyOpenBoardPkg/Include/SystemBoard.h | 75 + .../WhitleyOpenBoardPkg/Include/UbaKti.h | 29 + .../BoardAcpiLib/DxeBoardAcpiTableLib.c | 37 + .../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 44 + .../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 54 + .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 51 + .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 48 + .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 138 ++ .../Library/BoardInitLib/BoardInitDxeLib.c | 299 ++++ .../Library/BoardInitLib/BoardInitDxeLib.inf | 72 + .../Library/BoardInitLib/BoardInitDxeLib.uni | 29 + .../Library/BoardInitLib/BoardInitPreMemLib.c | 450 +++++ .../BoardInitLib/BoardInitPreMemLib.inf | 66 + .../MultiPlatSupportLib/MultiPlatSupport.h | 48 + .../MultiPlatSupportLib/MultiPlatSupportLib.c | 255 +++ .../MultiPlatSupportLib.inf | 49 + .../FspWrapperHobProcessLib.c | 722 ++++++++ .../PeiFspWrapperHobProcessLib.inf | 99 ++ .../PeiPlatformHookLib/PeiPlatformHooklib.c | 43 + .../PeiPlatformHookLib/PeiPlatformHooklib.inf | 34 + .../Library/PeiReportFvLib/PeiReportFvLib.c | 270 +++ .../Library/PeiReportFvLib/PeiReportFvLib.inf | 65 + .../PeiUbaGpioPlatformConfigLib.c | 518 ++++++ .../Library/PeiUbaPlatLib/PeiUbaPlatLib.inf | 60 + .../PeiUbaPlatLib/PeiUbaUsbOcUpdateLib.c | 61 + .../PeiUbaPlatLib/UbaBoardSioInfoLib.c | 54 + .../PeiUbaPlatLib/UbaClkGenUpdateLib.c | 134 ++ .../PeiUbaPlatLib/UbaClocksConfigLib.c | 59 + .../Library/PeiUbaPlatLib/UbaGpioUpdateLib.c | 68 + .../PeiUbaPlatLib/UbaHsioPtssTableConfigLib.c | 58 + .../PeiUbaPlatLib/UbaIioConfigLibPei.c | 219 +++ .../UbaIioPortBifurcationInitLib.c | 55 + .../Library/PeiUbaPlatLib/UbaPcdUpdateLib.c | 69 + .../PeiUbaPlatLib/UbaPchEarlyUpdateLib.c | 108 ++ .../PeiUbaPlatLib/UbaPchPcieBifurcationLib.c | 57 + .../PeiUbaPlatLib/UbaSlotUpdateLibPei.c | 156 ++ .../PeiUbaPlatLib/UbaSoftStrapUpdateLib.c | 95 + .../PlatformClocksLib/Pei/PlatformClocksLib.c | 347 ++++ .../Pei/PlatformClocksLib.inf | 40 + .../PlatformCmosAccessLib.c | 73 + .../PlatformCmosAccessLib.inf | 45 + .../Library/PlatformHooksLib/PlatformHooks.c | 203 +++ .../PlatformHooksLib/PlatformHooksLib.inf | 28 + .../PlatformOpromPolicyLibNull.c | 88 + .../PlatformOpromPolicyLibNull.inf | 29 + .../PlatformSetupVariableSyncLibNull.c | 81 + .../PlatformSetupVariableSyncLibNull.inf | 28 + .../PlatformVariableHookLibNull.c | 55 + .../PlatformVariableHookLibNull.inf | 24 + .../Library/ReadFfsLib/ReadFfsLib.c | 446 +++++ .../Library/ReadFfsLib/ReadFfsLib.inf | 34 + .../Library/SerialPortLib/Ns16550.h | 46 + .../Library/SerialPortLib/SerialPortLib.c | 1023 +++++++++++ .../Library/SerialPortLib/SerialPortLib.inf | 55 + .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 867 +++++++++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 55 + .../PchPolicyUpdateUsb.c | 152 ++ .../SiliconPolicyUpdateLib.c | 778 +++++++++ .../SiliconPolicyUpdateLib.inf | 64 + .../SiliconPolicyUpdateLibFsp.c | 770 ++++++++ .../SiliconPolicyUpdateLibFsp.inf | 68 + .../SmmSpiFlashCommonLib.inf | 57 + .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 237 +++ .../SpiFlashCommonSmmLib.c | 55 + .../DxeTcg2PhysicalPresenceLib.c | 41 + .../DxeTcg2PhysicalPresenceLib.inf | 29 + .../Library/UbaGpioInitLib/UbaGpioInitLib.c | 145 ++ .../Library/UbaGpioInitLib/UbaGpioInitLib.inf | 46 + 126 files changed, 17890 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeI= nclude.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePe= rformanceMonitoringInfrastructure.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRi= chDebugMessages.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNv= StorageFtwWorking.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSp= iFvHeaderInfo.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePe= rformanceMonitoringInfrastructurePostMemory.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePe= rformanceMonitoringInfrastructurePreMemory.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorag= e512K.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/Platfor= mVariableCommon.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVa= riable.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgH= ob.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Mult= iPlatSupportLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiP= latformHooklib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formClocksLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formOpromPolicyLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formSetupVariableSyncLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Plat= formVariableHookLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Read= FfsLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Setu= pLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaA= cpiUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaB= oardSioInfoLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaC= lkGenUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaC= locksConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioInitLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioPlatformConfig.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaG= pioUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaH= sioPtssTableConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaI= ioConfigLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaI= ioPortBifurcationInitLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaO= promUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= cdUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= chEarlyUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= cieBifurcationUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaP= latLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= lotUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= oftStrapUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= ystemBoardInfoLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaS= ystemConfigUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaU= sbOcUpdateLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicSt= ructs.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVari= able.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVari= ableLbg.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReport= StatusCodeHandler.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPol= icy.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb= .h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Leg= acyBios.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Leg= acyBiosPlatform.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Pci= IovPlatform.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Pla= tformType.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= CfgDb.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= DevsUpdateProtocol.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/Uba= MakerProtocol.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /DxeMtOlympusAcpiTableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitDxeLib.uni create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitPreMemLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib= /BoardInitPreMemLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupport.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupportLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSup= portLib/MultiPlatSupportLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrappe= rHobProcessLib/FspWrapperHobProcessLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrappe= rHobProcessLib/PeiFspWrapperHobProcessLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformH= ookLib/PeiPlatformHooklib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformH= ookLib/PeiPlatformHooklib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvL= ib/PeiReportFvLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvL= ib/PeiReportFvLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaGpioPlatformConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaPlatLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaUsbOcUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaBoardSioInfoLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaClkGenUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaClocksConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaGpioUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaHsioPtssTableConfigLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaIioConfigLibPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaIioPortBifurcationInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPcdUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchEarlyUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchPcieBifurcationLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaSlotUpdateLibPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaSoftStrapUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCloc= ksLib/Pei/PlatformClocksLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCloc= ksLib/Pei/PlatformClocksLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmos= AccessLib/PlatformCmosAccessLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmos= AccessLib/PlatformCmosAccessLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHook= sLib/PlatformHooks.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHook= sLib/PlatformHooksLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpro= mPolicyLibNull/PlatformOpromPolicyLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpro= mPolicyLibNull/PlatformOpromPolicyLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetu= pVariableSyncLibNull/PlatformSetupVariableSyncLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetu= pVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVari= ableHookLibNull/PlatformVariableHookLibNull.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVari= ableHookLibNull/PlatformVariableHookLibNull.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/R= eadFfsLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/R= eadFfsLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/Ns16550.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/SerialPortLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLi= b/SerialPortLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrr= Lib/SetCacheMtrrLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrr= Lib/SetCacheMtrrLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/PchPolicyUpdateUsb.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLibFsp.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolic= yUpdateLib/SiliconPolicyUpdateLibFsp.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SmmSpiFlashCommonLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SpiFlashCommon.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashC= ommonLib/SpiFlashCommonSmmLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2Physical= PresenceLibNull/DxeTcg2PhysicalPresenceLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2Physical= PresenceLibNull/DxeTcg2PhysicalPresenceLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitL= ib/UbaGpioInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitL= ib/UbaGpioInitLib.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.= dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc new file mode 100644 index 0000000000..13f65ff43d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc @@ -0,0 +1,135 @@ +## @file +# Platform description. +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + + # + # Generic EDKII Driver + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf + } + + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!endif +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + #UefiCpuPkg/CpuDxe/CpuDxe.inf + + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + + #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferD= xe.inf + + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + } + SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf +!endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePerforman= ceMonitoringInfrastructure.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include= /Dsc/EnablePerformanceMonitoringInfrastructure.dsc new file mode 100644 index 0000000000..c308e0df4f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnablePerformanceMonit= oringInfrastructure.dsc @@ -0,0 +1,40 @@ +## @file EnablePerformanceMonitoringInfrastructure.dsc +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdEdkiiFpdtStringRecordEnableOnly|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|100 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries16|100 + gEfiMdeModulePkgTokenSpaceGuid.PcdExtFpdtBootRecordPadSize|0x10000 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + +[LibraryClasses.X64] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + +[LibraryClasses.X64.DXE_CORE] + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.= inf + +[LibraryClasses.X64.SMM_CORE] + PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerform= anceLib.inf + +[Components.IA32] + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerf= ormancePei.inf + +[Components.X64] + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerf= ormanceDxe.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerf= ormanceSmm.inf + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf + +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebug= Messages.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDeb= ugMessages.dsc new file mode 100644 index 0000000000..6a66f2ebbb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessage= s.dsc @@ -0,0 +1,50 @@ +## @file EnableRichDebugMessages.dsc +# This takes care to turn on a higher level of debug messages that produce= s a +# balance between performance and greater levels of detail. +# This also customizes cores to use BaseDebugLibSerialPort for maximum +# messaging. +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# Customize debug messages +# +[PcdsFixedAtBuild] + ## This flag is used to control the built in Debug messages. + # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT4 - Allocate or Free Pool message.
+ # BIT5 - Allocate or Free Page message.
+ # BIT6 - Information message.
+ # BIT7 - Dispatcher message.
+ # BIT8 - Variable message.
+ # BIT10 - Boot Manager message.
+ # BIT12 - BlockIo Driver message.
+ # BIT14 - Network Driver message.
+ # BIT16 - UNDI Driver message + # BIT17 - LoadFile message.
+ # BIT19 - Event message.
+ # BIT20 - Global Coherency Database changes message.
+ # BIT21 - Memory range cachability changes message.
+ # BIT22 - Detailed debug message.
+ # BIT31 - Error message.
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x802A00C7 + +[PcdsPatchableInModule] + # + # This flag is used to control the displayed Debug messages. + # For simplification, we like to ensure both built in and enabled are in= sync + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|gEfiMdePkgTokenSpaceGui= d.PcdFixedDebugPrintErrorLevel + +[LibraryClasses.IA32.PEI_CORE] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + +[LibraryClasses.X64.DXE_CORE] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorage= FtwWorking.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvSto= rageFtwWorking.fdf new file mode 100644 index 0000000000..97c7c2a28f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWork= ing.fdf @@ -0,0 +1,20 @@ +## @file CommonNvStorageFtwWorking.fdf +# FV contents for FTW Working block FV +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHead= erInfo.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHead= erInfo.fdf new file mode 100644 index 0000000000..08f8b95938 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.= fdf @@ -0,0 +1,24 @@ +## @file CommonSpiFvHeaderInfo.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +FvAlignment =3D 16 #FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerforman= ceMonitoringInfrastructurePostMemory.fdf b/Platform/Intel/WhitleyOpenBoardP= kg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf new file mode 100644 index 0000000000..a3576bd7a8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonit= oringInfrastructurePostMemory.fdf @@ -0,0 +1,14 @@ +## @file EnablePerformanceMonitoringInfrastructurePostMemory.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/Firmwar= ePerformanceDxe.inf + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/Firmwar= ePerformanceSmm.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.= inf + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerforman= ceMonitoringInfrastructurePreMemory.fdf b/Platform/Intel/WhitleyOpenBoardPk= g/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf new file mode 100644 index 0000000000..dbc98f6f1f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonit= oringInfrastructurePreMemory.fdf @@ -0,0 +1,11 @@ +## @file EnablePerformanceMonitoringInfrastructurePreMemory.fdf +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +!if $(PERFORMANCE_ENABLE) =3D=3D TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwar= ePerformancePei.inf +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.f= df b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf new file mode 100644 index 0000000000..089d9bbf06 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf @@ -0,0 +1,46 @@ +## @file NvStorage512K.fdf +# FV contents for NV storage variable and fault tolerant write usage. +# The size and block layout here must match the actual layout built by the= build tools. +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0= x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 8 Blocks * 0x10000 Bytes / Block + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0= x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98= , 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x3C000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3BFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xBF, 0x03, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h new file mode 100644 index 0000000000..2e25c4b6c5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/GpioInitData.h @@ -0,0 +1,26 @@ +/** @file + Platform specific information + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "Platform.h" + +#ifndef __GPIO_INIT_DATA_H__ +#define __GPIO_INIT_DATA_H__ + +#include +#include + + +// +// SKX_TODO: Platform Update GPIO table +// +// +// SKX_TODO: Create GPIO tables for LBG platforms (PCH_GPIO_CONFIG type) +// + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariab= leCommon.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariab= leCommon.h new file mode 100644 index 0000000000..aab9856c66 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/PlatformVariableCommo= n.h @@ -0,0 +1,33 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_VARIABLE_COMMON_H_ +#define _PLATFORM_VARIABLE_COMMON_H_ + + +#ifndef PLATFORM_SETUP_VARIABLE_NAME +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup" +#endif + +#define CMOS_CLEAR_EVENT BIT0 +#define CMOS_BAD_CHECKSUM_EVENT BIT1 +#define MFG_MODE_EVENT BIT2 +#define RECOVERY_MODE_EVENT BIT3 +#define LOAD_FAILSAFE_EVENT BIT4 +#define LOAD_CUSTOMIZED_EVENT BIT5 +#define NULL_VARIABLE_EVENT BIT6 + +#define PLATFORM_VARIABLE_HOB_GUID { 0x71e6d4bc, 0x4837, 0x45f1, { 0xa2, 0= xd7, 0x3f, 0x93, 0x8, 0xb1, 0x7e, 0xd7 } } + +extern EFI_GUID gPlatformVariableHobGuid; + +#define LOAD_FAILSAFE_VARIABLE_NAME L"LoadEPSDConfigurationDefaults" +#define LOAD_CUSTOMIZED_VARIABLE_NAME L"LoadSystemConfigurationDefaults" + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..c47f040ca3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h @@ -0,0 +1,720 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SETUP_VARIABLE_H__ +#define __SETUP_VARIABLE_H__ + +// -----------------------------------------------------------------------= ---- +// +// Driver Configuration +// +// -----------------------------------------------------------------------= ---- +// +//Copied from client SetupVariable.h +#ifndef PLATFORM_SETUP_VARIABLE_NAME +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup" +#endif + +#ifndef PCH_SETUP_VARIABLE +#define PCH_SETUP_VARIABLE_NAME L"PchSetup" +#endif + +#define EFI_EPG_GENERIC_VARIABLE_GUID \ + { \ + 0x8302cc54, 0xbb1a, 0x4564, {0x92, 0xdc, 0xae, 0x1a, 0xbb, 0x15, 0x5f,= 0x35} \ + } + +// +// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9} +// +#define SYSTEM_CONFIGURATION_GUID \ + { \ + 0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, = 0xa9} \ + } + +#define PCH_SETUP_GUID \ + { \ + 0x4570b7f1, 0xade8, 0x4943, {0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0= x84} \ + } + +#define FAKE_VARSTORE_GUID \ + { \ + 0xe57d5cb9, 0x148f, 0x444d, {0x9e, 0xcb, 0x9d, 0xf8, 0x65, 0x30, 0xa0,= 0xb4} \ + } + +#define SYSTEM_CONFIGURATION_CONTROL_GUID \ + { \ + 0x8d247131, 0x385e, 0x491f, {0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3,= 0xa6} \ + } + +#define SYSTEM_CONFIGURATION_ICHPCIE_GUID \ + { \ + 0x10e023a7, 0x4ce5, 0x4a6a, {0xa1, 0xbb, 0xbd, 0xd0, 0x8d, 0x16, 0x37,= 0x57} \ + } + +#define SYSTEM_DEFAULT_CONFIGURATION_GUID \ + { \ + 0x99a96812, 0x4730, 0x4290, {0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9,= 0x3b} \ + } + +#define RESERVEMEMFLAG_VARIABLE_GUID \ +{\ + 0xb87aa73f, 0xdcb3, 0x4533, {0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, = 0x40} \ +} + +#define BMC_ENABLE_FLAG_GUID \ +{\ + 0x7bb08ce4, 0x6988, 0x4c59, {0xb5, 0x37, 0xb4, 0xb1, 0xd5, 0xbe, 0xb0, = 0x6e} \ +} + +#define MAX_PCH_PCI_EXPRESS_ROOT_PORTS 8 +#define PASSWORD_MAX_SIZE 16 +#define SHA256_DIGEST_LENGTH 32 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 + +#define FAKE_VARSTORE_ID 0x1234 +#define ME_SETUP_STORAGE_ID 0x1235 +#define ICC_SETUP_ID 0x1236 + +extern EFI_GUID gReserveMemFlagVariableGuid; + +#pragma pack(1) + +typedef struct { + + UINT8 UserPassword[SHA256_DIGEST_LENGTH]; + UINT8 AdminPassword[SHA256_DIGEST_LENGTH]; + UINT8 Access; + + // + // Keyboard + // + UINT8 Numlock; + UINT8 Ps2PortSwap; + + // + // TPM + // + UINT8 TpmEnable; + UINT8 TpmState; + UINT8 MorState; + + // + // XmlCli + // + UINT8 XmlCliSupport; + UINT8 SkipXmlComprs; + UINT8 PublishSetupPgPtr; + UINT32 XmlCLiDramCmosAddr; + + // + // Breakpoints + // + UINT8 ValidationBreakpointType; + UINT16 bsdBreakpoint; + + // + // Power State + // + UINT8 PowerState; + + // + // Wake On Lan + // + UINT8 WakeOnLanS5; + + // + // Boot from Network + // + UINT8 BootNetwork; + + // + // Video + // + UINT8 VideoSelect; + UINT8 EfiWindowsInt10Workaround; + UINT8 UefiOptimizedBootToggle; + + // + // Fan PWM Offset + // + UINT8 FanPwmOffset; + + // + // Benchmark + // + UINT8 ApplicationProfile; + + // + // PCI Minimum Secondary Bus Number + // + UINT8 PCIe_MultiSeg_Support; + + // + UINT8 WakeOnLanSupport; + // + // Enable/disable for PCIe LOM by using GPO44/45 + // NOT PCH LAN + // + UINT8 LomDisableByGpio; + + UINT8 FpkPortConfig[4]; + UINT8 FpkPortConfigPrev[4]; + UINT8 FpkPortPresent[4]; + + // RTC WAKE + // + UINT8 WakeOnRTCS4S5; + UINT8 RTCWakeupTimeHour; + UINT8 RTCWakeupTimeMinute; + UINT8 RTCWakeupTimeSecond; + // PCI_EXPRESS_CONFIG, ROOT PORTS + // + // AJW: these cross the line, but depend on Platform Info + UINT8 PcieClockGatingDisabled ; + UINT8 PcieDmiAspm; + UINT8 PcieSBDE; + UINT8 GbePciePortNum; + UINT8 PciePortConfig1; + UINT8 PciePortConfig2; + UINT8 PciePortConfig3; + UINT8 PciePortConfig4; + UINT8 PciePortConfig5; + + // GBE + UINT8 GbeEnabled; + + // PCH Stepping + UINT8 PchStepping; + + // + // XHCI Wake On USB + // + UINT8 XhciWakeOnUsbEnabled; + + // + // EventLog + // +// +// SKX_TODO: add these for RAS, may be best to find new home for them in a= new setup variable and setup page +// + UINT8 SystemErrorEn; + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + UINT8 RasLogLevel; + UINT8 PoisonEn; + UINT8 ViralEn; + UINT8 CloakDevHideRegistersOs; + UINT8 ClearViralStatus; + UINT8 CloakingEn; + UINT8 UboxToPcuMcaEn; + UINT8 FatalErrSpinLoopEn; + + UINT8 EmcaEn; + UINT8 EmcaIgnOptin; + UINT8 EmcaCsmiEn; + UINT16 EmcaCsmiThreshold; + UINT8 CsmiDynamicDisable; + UINT8 EmcaMsmiEn; + UINT8 ElogCorrErrEn; + UINT8 ElogMemErrEn; + UINT8 ElogProcErrEn; + UINT8 LmceEn; + UINT8 HideWriteDataParityLogs; + UINT8 UboxErrorMask; + + UINT8 WheaSupportEn; + UINT8 WheaLogMemoryEn; + UINT8 WheaLogProcEn; + + UINT8 WheaLogPciEn; + UINT8 AEPErrorInjEn; + UINT8 WheaErrorInjSupportEn; + UINT8 McaBankErrInjEn; + UINT8 WheaErrInjEn; + UINT8 WheaPcieErrInjEn; + UINT8 MeSegErrorInjEn; + UINT8 SgxErrorInjEn; + UINT8 PcieErrInjActionTable; + + UINT8 MemErrEn; + UINT8 CorrMemErrEn; + UINT8 SpareIntSelect; + UINT8 PfdEn; + UINT8 DcpmmEccModeSwitch; + UINT8 FnvErrorEn; + UINT8 FnvErrorLowPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 FnvErrorHighPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3= - BOTH + UINT8 NgnAddressRangeScrub; + UINT8 NgnHostAlertDpa; //Signal Poison or Viral upon receiving = DIMM Physical Address Error + UINT8 NgnHostAlertPatrolScrubUNC; //Signal DDRT interrupt upon receiv= ing Uncorrectable Error for NGN Patrol Scrub + UINT8 ReportAlertSPA; //Include SPA when reporting DDRT a= lert. Only to disable for MCE recovery test. + UINT8 DcpmmUncPoison; // Poison media location for Uncorr= ectable error on Read (via patrol scrubber..) + UINT8 DdrtInternalAlertEn; + + UINT8 IioErrorEn; + UINT8 OsNativeAerSupport; + UINT8 IoMcaEn; + UINT8 IioSev1Pcc; + UINT8 IioErrRegistersClearEn; + UINT8 IioErrorPin0En; + UINT8 IioErrorPin1En; + UINT8 IioErrorPin2En; + UINT8 LerEn; + UINT8 DisableMAerrorLoggingDueToLER; + UINT8 EdpcEn; + UINT8 EdpcInterrupt; + UINT8 EdpcErrCorMsg; + UINT8 PciePtlpEgrBlk; + + UINT8 IioIrpErrorEn; + UINT8 IioMiscErrorEn; + UINT8 IioVtdErrorEn; + UINT8 IioDmaErrorEn; + UINT8 IioDmiErrorEn; + UINT8 IioPcieAddCorrErrorEn; + UINT8 IioPcieAddUnCorrEn; + UINT8 IioPcieAddRcvComWithUr; + UINT8 IioPcieAerSpecCompEn; + UINT8 ItcOtcCaMaEnable; + UINT8 PsfUrEnable; + UINT8 PmsbRouterParityErrEn; + UINT8 PcieErrEn; + UINT8 PcieCorrErrEn; + UINT8 PcieUncorrErrEn; + UINT8 PcieFatalErrEn; + UINT8 PcieCorErrCntr; + UINT16 PcieCorErrThres; + UINT8 PcieCorErrLimitEn; + UINT32 PcieCorErrLimit; + UINT8 PcieAerCorrErrEn; + UINT8 PcieAerAdNfatErrEn; + UINT8 PcieAerNfatErrEn; + UINT8 PcieAerFatErrEn; + UINT8 PcieAerEcrcEn; + UINT8 PcieAerSurpriseLinkDownEn; + UINT8 PcieAerUreEn; + UINT8 McaSpinLoop; + UINT8 IioOOBMode; + +// Endof RAS add + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX f= lag + + UINT8 McBankWarmBootClearError; + UINT8 ShutdownSuppression; + UINT8 KTIFailoverSmiEn; + + UINT8 irpp0_parityError; + UINT8 irpp0_qtOverflow; + UINT8 irpp0_unexprsp; + UINT8 irpp0_csraccunaligned; + UINT8 irpp0_unceccCs1; + UINT8 irpp0_unceccCs0; + UINT8 irpp0_rcvdpoison; + UINT8 irpp0_crreccCs1; + UINT8 irpp0_crreccCs0; + + UINT8 PropagateSerr; + UINT8 PropagatePerr; + + // + // Boot Options + // + UINT8 serialDebugMsgLvl; + UINT8 serialDebugTrace; + UINT8 serialDebugMsgLvlTrainResults; + UINT8 ResetOnMemMapChange; + UINT8 ForceSetup; + UINT8 BiosGuardEnabled; + UINT8 BiosGuardPlatformSupported; + UINT8 EnableAntiFlashWearout; + UINT8 AntiFlashWearoutSupported; + UINT8 ReservedS1; + + UINT8 Use1GPageTable; + // + // UINT8 QuietBoot; + // + UINT8 FastBoot; + + // PFR { + UINT8 PfrSupported; + UINT8 PfrCpldRotReleaseVersion; + UINT8 PfrCpldRotSvn; + UINT8 PfrPchPfrActiveSvn; + UINT8 PfrPchPfmActiveMajorVersion; + UINT8 PfrPchPfmActiveMinorVersion; + UINT8 PfrBmcPfrActiveSvn; + UINT8 PfrBmcPfmActiveMajorVersion; + UINT8 PfrBmcPfmActiveMinorVersion; + UINT8 PfrPchPfrRecoverySvn; + UINT8 PfrPchPfmRecoveryMajorVersion; + UINT8 PfrPchPfmRecoveryMinorVersion; + UINT8 PfrBmcPfrRecoverySvn; + UINT8 PfrBmcPfmRecoveryMajorVersion; + UINT8 PfrBmcPfmRecoveryMinorVersion; + UINT8 PfrLockStatus; + UINT8 PfrProvisionStatus; + UINT8 PfrPitL1Status; + UINT8 PfrPitL2Status; + UINT8 PfrLock; + UINT8 PfrProvision; + UINT8 PfrUnProvision; + UINT8 PfrPitL1; + UINT8 PfrPitL2; + // PFR } + + // + // Reserve Memory that is hidden from the OS. + // + UINT8 ReserveMem; + UINT64 ReserveStartAddr; + // + // Reserve TAGEC Memory + // + UINT8 TagecMem; + + //Usb Configdata + UINT8 UsbMassDevNum; + UINT8 UsbLegacySupport; + UINT8 UsbEmul6064; + UINT8 UsbMassResetDelay; + UINT8 UsbNonBoot; + UINT8 UsbEmu1; + UINT8 UsbEmu2; + UINT8 UsbEmu3; + UINT8 UsbEmu4; + UINT8 UsbEmu5; + UINT8 UsbEmu6; + UINT8 UsbEmu7; + UINT8 UsbEmu8; + UINT8 UsbEmu9; + UINT8 UsbEmu10; + UINT8 UsbEmu11; + UINT8 UsbEmu12; + UINT8 UsbEmu13; + UINT8 UsbEmu14; + UINT8 UsbEmu15; + UINT8 UsbEmu16; + UINT8 UsbStackSupport; + + // Console Redirection + UINT8 ConsoleRedirection; + UINT8 FlowControl; + UINT64 BaudRate; + UINT8 TerminalType; + UINT8 LegacyOsRedirection; + UINT8 TerminalResolution; + UINT8 DataBits; + UINT8 Parity; + UINT8 StopBits; + +#ifdef EFI_PCI_IOV_SUPPORT + UINT8 SystemPageSize; + UINT8 ARIEnable; + UINT8 ARIForward; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; +#endif + // + // RAS + // + +// +// Network setup entries - start here <><><><><> +// + UINT8 LegacyPxeRom; + UINT8 EfiNetworkSupport; +// +// Network setup entries - end here <><><><><> +// + +// +// SERIALPORT BAUD RATE: Begin +// + UINT32 SerialBaudRate; +// +// SERIALPORT BAUD RATE: END +// + + UINT8 BootAllOptions; + UINT8 SetShellFirst; + UINT8 ShellEntryTime; + + // + // Overclocking related setup variables + // + UINT8 PlatformOCSupport; + UINT8 FilterPll; + UINT8 OverclockingSupport; + + UINT8 CoreMaxOcRatio; + UINT8 CoreVoltageMode; + UINT16 CoreVoltageOverride; + UINT16 CoreVoltageOffset; + UINT8 CoreVoltageOffsetPrefix; + UINT16 CoreExtraTurboVoltage; + + // + // OC related + // + UINT8 MemoryVoltage; + UINT8 MemoryVoltageDefault; + UINT8 tCL; + + // + // CLR Related + // + UINT8 ClrMaxOcRatio; + UINT8 ClrVoltageMode; + UINT16 ClrVoltageOverride; + UINT16 ClrVoltageOffset; + UINT8 ClrVoltageOffsetPrefix; + UINT16 ClrExtraTurboVoltage; + + // + // Uncore Related + // + UINT16 UncoreVoltageOffset; + UINT8 UncoreVoltageOffsetPrefix; + UINT16 IoaVoltageOffset; + UINT8 IoaVoltageOffsetPrefix; + UINT16 IodVoltageOffset; + UINT8 IodVoltageOffsetPrefix; + + // + // SVID and FIVR Related + // + UINT8 SvidEnable; + UINT16 SvidVoltageOverride; + UINT8 FivrFaultsEnable; + UINT8 FivrEfficiencyEnable; + +// +// UBA_START +// + UINT8 SataInterfaceRAIDMode; + UINT8 sSataInterfaceRAIDMode; +// +// UBA_END +// + UINT16 C01MemoryVoltage; + UINT16 C23MemoryVoltage; + + UINT16 CpuVccInVoltage; + + UINT8 VccIoVoltage; + + UINT16 VariablePlatId; + + //XTU 3.0 + + UINT8 FlexRatioOverrideDefault; + UINT8 RatioLimit1Default; + UINT8 RatioLimit2Default; + UINT8 RatioLimit3Default; + UINT8 RatioLimit4Default; + UINT8 OverclockingLockDefault; + UINT8 DdrRefClkDefault; + UINT8 DdrRatioDefault; + UINT8 tCLDefault; + UINT8 tCWLDefault; + UINT16 tFAWDefault; + UINT16 tRASDefault; + UINT16 tRCDefault; + UINT8 tRCDDefault; + UINT16 tREFIDefault; + UINT16 tRFCDefault; + UINT8 tRPDefault; + UINT8 tRPabDefault; + UINT8 tRRDDefault; + UINT8 tRTPDefault; + UINT8 tWRDefault; + UINT8 tWTRDefault; + UINT8 NModeDefault; + UINT8 CoreMaxOcRatioDefault; + UINT8 CoreVoltageModeDefault; + UINT16 CoreVoltageOverrideDefault; + UINT16 CoreVoltageOffsetDefault; + UINT8 CoreVoltageOffsetPrefixDefault; + UINT16 CoreExtraTurboVoltageDefault; + UINT8 GtOcSupportDefault; + UINT8 GtOcFrequencyDefault; + UINT16 GtExtraTurboVoltageDefault; + UINT16 GtOcVoltageDefault; + UINT8 GtVoltageModeDefault; + UINT16 GtVoltageOverrideDefault; + UINT16 GtVoltageOffsetDefault; + UINT8 GtVoltageOffsetPrefixDefault; + UINT8 ClrMaxOcRatioDefault; + UINT8 ClrVoltageModeDefault; + UINT16 ClrVoltageOverrideDefault; + UINT16 ClrVoltageOffsetDefault; + UINT8 ClrVoltageOffsetPrefixDefault; + UINT16 ClrExtraTurboVoltageDefault; + UINT16 UncoreVoltageOffsetDefault; + UINT8 UncoreVoltageOffsetPrefixDefault; + UINT16 IoaVoltageOffsetDefault; + UINT8 IoaVoltageOffsetPrefixDefault; + UINT16 IodVoltageOffsetDefault; + UINT8 IodVoltageOffsetPrefixDefault; + UINT8 SvidEnableDefault; + UINT16 SvidVoltageOverrideDefault; + UINT8 FivrFaultsEnableDefault; + UINT8 FivrEfficiencyEnableDefault; + UINT16 VrCurrentLimitDefault; + UINT8 EnableGvDefault; + UINT8 TurboModeDefault; + UINT8 PowerLimit1TimeDefault; + UINT16 PowerLimit1Default; + UINT16 PowerLimit2Default; + + + UINT8 RatioLimit1; //ratiolimit handling has changed in SKX. knobs might= need to change too. Will have to revisit again. + UINT8 RatioLimit2; + UINT8 RatioLimit3; + UINT8 RatioLimit4; + UINT8 CpuRatio; // need to understand what is the difference between max= nonturboratio and cpuratio. if cpuratiooverride is 0, then cpuratio is same= as maxnonturboratio. add this to platform cpu policy or socketsetup. + UINT8 CpuRatioOverride; + UINT8 IsTurboRatioDefaultsInitalized; // related to initializing all the= vardefault. is this flow needed for HEDT/intended only for clients? no nee= d for set up creation. + + + UINT8 DdrRefClk; //cant find any in purley. new one? + UINT8 PcieRatioDisabled;//need to check if this is applicable to HEDT. a= lso no need to create a setup variable. + UINT8 NMode ; + + UINT16 GtVoltageOffset; //existing but no set up option + UINT16 VrCurrentLimit;//done + //UINT8 SpdProfileSelected; same as XMPMode + UINT8 NModeSupport; + UINT8 WDTSupportforNextOSBoot; // no setup option needed + UINT16 TimeforNextOSBoot; // no setup optiom needed + UINT8 PlatformUnstable; // no set up option needed. this decides if all = the vardefaults are needed. + UINT8 GtVoltageMode; //existing but no set up option + UINT8 DdrRatio; + UINT8 GtOcFrequency; + UINT16 GtExtraTurboVoltage; //existing but no set up option + UINT16 GtVoltageOverride; //existing but no set up option + UINT8 GtVoltageOffsetPrefix; + UINT8 GtOcSupport; + // + // CPU releated + // + UINT8 FlexOverrideEnable; + UINT8 FlexRatioOverride; + UINT8 PowerLimit3Override; + UINT32 PowerLimit3; + UINT8 PowerLimit3Time; + UINT8 PowerLimit3DutyCycle; + UINT8 PowerLimit3Lock; + UINT8 MemoryVoltageOverride; + + // + // ICC Related + // + UINT8 BClkOverride; + UINT8 BclkAdjustable; + UINT8 DmiPegRatio; + UINT8 ReservedS2; + UINT8 ReservedS3; + + UINT8 StorageOpROMSuppression; + UINT8 RsaSupport; + + UINT8 ReservedS4; + UINT8 ReservedS5; + + // + // PCIe Leaky Bucket Feature (requires Gen4 IP) + // + UINT64 ExpectedBer; + UINT32 Gen12TimeWindow; + UINT8 Gen34TimeWindow; + UINT8 Gen12ErrorThreshold; + UINT8 Gen34ErrorThreshold; + UINT8 Gen34ReEqualization; + UINT8 Gen2LinkDegradation; + UINT8 Gen3LinkDegradation; + UINT8 Gen4LinkDegradation; + + // + // Crash Log Feature + // + UINT8 CrashLogFeature; + UINT8 CrashLogOnAllReset; + UINT8 CrashLogClear; + UINT8 CrashLogReArm; + + // + // Error Control + // + UINT8 Ce2LmLoggingEn; + UINT8 KtiFirstCeLatchEn; + UINT8 PatrolScrubErrorReporting; + UINT8 LlcEwbErrorControl; + UINT8 KcsAccessPolicy; + + // + // Platform Deep S5 Feature + // + UINT8 PlatformDeepS5; + UINT8 DeepS5DelayTime; + + UINT8 EnableClockSpreadSpec; + + // + // TCC Mode + // + UINT8 TccMode; +} SYSTEM_CONFIGURATION; + +typedef struct { + UINT8 FakeItem; +} FAKE_VARSTORE; + +#pragma pack() + +#define EFI_HDD_PRESENT 0x01 +#define EFI_HDD_NOT_PRESENT 0x00 +#define EFI_CD_PRESENT 0x02 +#define EFI_CD_NOT_PRESENT 0x00 + +#define EFI_HDD_WARNING_ON 0x01 +#define EFI_CD_WARNING_ON 0x02 +#define EFI_SMART_WARNING_ON 0x04 +#define EFI_HDD_WARNING_OFF 0x00 +#define EFI_CD_WARNING_OFF 0x00 +#define EFI_SMART_WARNING_OFF 0x00 + + +extern EFI_GUID gMainPkgListGuid; +extern EFI_GUID gAdvancedPkgListGuid; +extern EFI_GUID gTpmPkgListGuid; +extern EFI_GUID gSecurityPkgListGuid; +extern EFI_GUID gBootOptionsPkgListGuid; +extern EFI_GUID gServerMgmtPkgListGuid; + + +#ifndef VFRCOMPILE + +extern EFI_GUID gEfiSetupVariableGuid; +extern EFI_GUID gEfiSetupVariableDefaultGuid; +extern EFI_GUID gEfiGlobalVariableControlGuid; + +typedef struct { + UINT8 ProcessController; +} SYSTEM_CONFIGURATION_CONTROL; + +#endif + +#define SYSTEM_PASSWORD_ADMIN 0 +#define SYSTEM_PASSWORD_USER 1 + +#define PASSWORD_ADMIN_NAME L"AdminName" +#define PASSWORD_USER_NAME L"UserName" + +#endif // #ifndef _SETUP_VARIABLE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h b/= Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h new file mode 100644 index 0000000000..b5c8510f8c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/UbaCfgHob.h @@ -0,0 +1,74 @@ +/** @file + uba config database head file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_HOB_H_ +#define _UBA_CONFIG_DATABASE_HOB_H_ + + +#define UBA_CONFIG_HOB_SIGNATURE SIGNATURE_32('U', 'B', 'A', 'H') +#define UBA_CONFIG_HOB_VERSION 0x01 + +#define UBA_BOARD_SIGNATURE SIGNATURE_32('S', 'K', 'U', 'D') +#define UBA_BOARD_VERSION 0x01 + +// +// Interface data between PEI & DXE +// Should keep same align +// +#pragma pack (1) + +typedef struct _UBA_CONFIG_HOB_FIELD { + UINT32 Signature; + UINT32 Version; + EFI_GUID ResId; + UINT64 DataOffset; + UINT32 Size; +} UBA_CONFIG_HOB_FIELD; + +typedef struct _UBA_CONFIG_HOB_HEADER { + UINT32 Signature; + UINT32 Version; + EFI_GUID DataGuid; + UINT32 HobLength; + UINT32 BoardId; + EFI_GUID BoardGuid; + CHAR8 BoardName[16]; + UINT32 DataCount; + UBA_CONFIG_HOB_FIELD HobField[1]; +} UBA_CONFIG_HOB_HEADER; + + +typedef struct _UBA_BOARD_NODE { + UINT32 Signature; + UINT32 Version; + LIST_ENTRY DataLinkHead; + + UINT32 BoardId; + EFI_GUID BoardGuid; + CHAR8 BoardName[16]; + UINT32 DataCount; +} UBA_BOARD_NODE; + +typedef struct _UBA_CONFIG_NODE { + UINT32 Signature; + UINT32 Version; + LIST_ENTRY DataLink; + + EFI_HANDLE Handle; + EFI_GUID ResId; + UINT32 Size; + VOID *Data; +} UBA_CONFIG_NODE; + +#pragma pack () + +#define BOARD_NODE_INSTANCE_FROM_THIS(p) CR(p, UBA_BOARD_NODE, DataL= inkHead, UBA_BOARD_SIGNATURE) +#define CONFIG_NODE_INSTANCE_FROM_THIS(p) CR(p, UBA_CONFIG_NODE, Data= Link, UBA_BOARD_SIGNATURE) + +#endif // _UBA_CONFIG_DATABASE_HOB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h b/Platform= /Intel/WhitleyOpenBoardPkg/Include/IoApic.h new file mode 100644 index 0000000000..47d73172bc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/IoApic.h @@ -0,0 +1,23 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IOAPIC_H_ +#define _IOAPIC_H_ + +#define EFI_IO_APIC_INDEX_OFFSET 0x00 +#define EFI_IO_APIC_DATA_OFFSET 0x10 +#define EFI_IO_APIC_IRQ_ASSERTION_OFFSET 0x20 +#define EFI_IO_APIC_EOI_OFFSET 0x40 + +#define EFI_IO_APIC_ID_REGISTER 0x0 +#define EFI_IO_APIC_ID_BITSHIFT 24 +#define EFI_IO_APIC_VER_REGISTER 0x1 +#define EFI_IO_APIC_BOOT_CONFIG_REGISTER 0x3 +#define EFI_IO_APIC_FSB_INT_DELIVERY 0x1 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSu= pportLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSu= pportLib.h new file mode 100644 index 0000000000..6389c393d6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/MultiPlatSupportLi= b.h @@ -0,0 +1,67 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MULTI_PLATFORM_SUPPORT_LIB_H_ +#define _MULTI_PLATFORM_SUPPORT_LIB_H_ + +#define MAX_TEMP_BUFFER 0x5000 +//#define MULTI_PLATFORM_DEBUG TRUE + + + + +/*++ +Description: + + This function finds the matched default data and create GUID hob for it. + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateDefaultVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + + + +/** + Gets a vairable store header from FFS inserted by FCE + + Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + + + @return The start address of VARIABLE_STORE_HEADER *. Null if cannot fin= d it + +**/ + +VOID * FindDefaultHobinFfs ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + + + + + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatform= Hooklib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatformH= ooklib.h new file mode 100644 index 0000000000..d94a483f89 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PeiPlatformHooklib= .h @@ -0,0 +1,17 @@ +/** @file + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ + +EFI_STATUS +BoardInit ( + ); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClo= cksLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClock= sLib.h new file mode 100644 index 0000000000..0dc9c690fe --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformClocksLib.h @@ -0,0 +1,87 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PLATFORM_CLOCKS_LIB__ +#define __PLATFORM_CLOCKS_LIB__ + +// +// Known clock generator types +// +typedef enum { + ClockGeneratorCk410, + ClockGeneratorCk420, + ClockGeneratorCk440, + ClockGeneratorCk505, + ClockGeneratorMax +} CLOCK_GENERATOR_TYPE; + +#define CLOCK_GENERATOR_ADDRESS 0xD2 +// +// Clock generator details table +// +typedef struct { + CLOCK_GENERATOR_TYPE ClockType; + UINT8 ClockId; + UINT8 SpreadSpectrumByteOffset; + UINT8 SpreadSpectrumBitOffset; +} CLOCK_GENERATOR_DETAILS; + +// +// An arbitrary maximum length for clock generator buffers +// +#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20 + +// +// CK410 Definitions +// +#define CK410_GENERATOR_ID 0x65 +#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1 +#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 +#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4 +#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2) + +// +// CK420 Definitions +// +#define CK420_GENERATOR_ID 0x11 // IDT ICS932SQ42= 0B +#define CK420_GENERATOR_SPREAD_SPECTRUM_BYTE 1 +#define CK420_GENERATOR_SPREAD_SPECTRUM_BIT BIT0 + +// +// CK440 Definitions +// +#define CK440_GENERATOR_ID 0x12 +#define CK440_GENERATOR_SPREAD_SPECTRUM_BYTE 6 +#define CK440_GENERATOR_SPREAD_SPECTRUM_BIT BIT2 + +// +// CK505 Definitions +// +#define CK505_GENERATOR_ID 0x26 // Silego SLG505Y= C264B +#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4 +#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1) + +#define CLOCK_GENERATOR_SETTINGS_PLATFORMSRP {0xFF, 0x9E, 0x3F, 0x00, 0x00= , 0x0F, 0x08, 0x31, 0x0A, 0x17, 0xFF, 0xFE} +#define CLOCK_GENERATOR_SETTINGS_PLATFORMDVP {0xFF, 0x9E, 0x3F, 0x00, 0x00= , 0x0F, 0x08, 0x31, 0x0A, 0x17} + +EFI_STATUS +ConfigureClockGenerator ( + IN EFI_PEI_SERVICES **PeiServices, + IN CLOCK_GENERATOR_TYPE ClockType, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN OUT UINT8 *ConfigurationTable, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN BOOLEAN SecondarySmbus + ); + +#define PEI_STALL_RESOLUTION 1 + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformOpr= omPolicyLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Platform= OpromPolicyLib.h new file mode 100644 index 0000000000..16ea3d7493 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformOpromPolic= yLib.h @@ -0,0 +1,83 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLAT_OPROM_ +#define _PLAT_OPROM_ +#include + +typedef enum _OPROM_LOAD_POLICY +{ + DONT_LOAD, + EXCLUSIVE_LOAD, + INCLUSIVE_LOAD +} OPROM_LOAD_POLICY; + +/** + Decide if BIOS embdded option roms should be loaded for a certain PCI de= vice. + + @param PciIo PCI device to return the ROM image for. + + @retval TRUE BIOS embedded option roms should not be loaded for th= e PCI device. + @retval FALSE BIOS embedded option roms could be loaded for the PCI= device. +**/ + +BOOLEAN +PlatformOpromLoadDevicePolicy ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ); + +/** + For devices that support multiple option roms like FCoE, PXE, iSCSI etc.= , this function decides if one of these BIOS embdded option roms should be = loaded for a certain PCI device based on platform choices. + + @param PciHandle PCI device to return the ROM image for. + @param TableIndex The index pointing to the option rom in the platf= orm option rom table for the PCI device. + + @retval FALSE The specific BIOS embedded option rom should not = be loaded for the PCI device. + @retval TRUE The specific BIOS embedded option rom could be lo= aded for a certain PCI device. +**/ + +OPROM_LOAD_POLICY +PlatformOpromLoadTypePolicy ( + IN EFI_HANDLE PciHandle, + IN UINTN TableIndex + ); + +/** + Decide if a PCIe device option rom should be dispacthed. + + @param PciHandle PCI device handle. + + @retval FALSE The specific PCIe option rom should not be dispat= ched for the PCI device. + @retval TRUE The specific PCIe option rom could be dispatched = for a certain PCI device. + +**/ + +BOOLEAN +PlatformOpromDispatchPolicy ( + IN EFI_HANDLE DeviceHandle +); + +/** + Enable the legacy console redirection before dispatch the legacy ORPOM o= r disable the legacy console redirection after dispatch + the legacy ORPOM based on setup option and SOL status. + + @param Mode Subfunction. + @param CheckIsAhciRom If the device is legacy Ahci device. + + @retval + +**/ + +VOID +PlatformOpromLegacyCRPolicy ( + IN UINTN Mode, + IN BOOLEAN CheckIsAhciRom +); + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformSet= upVariableSyncLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Pl= atformSetupVariableSyncLib.h new file mode 100644 index 0000000000..02c8411007 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformSetupVaria= bleSyncLib.h @@ -0,0 +1,60 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PLATFORM_SETUP_VAR_SYNC +#define __PLATFORM_SETUP_VAR_SYNC +#include +#include "Uefi/UefiBaseType.h" + +/** + THis function can sync PC/OEM setup variable value to Rp setup variable = before variable service is ready + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, - The input paramter should be VARIABLE_STORE_= HEADER *VarStoreHeader. + Since we don't know whether SECURE_BOOT_ENABLE= is used, we don't know to include which ***VariableFormat.h + So just use VOID* to pass to platform library + IN BOOLEAN CreateHobDataForRpDefaults - whether need to create a hob for= RP setup variable only, + in normal boot case, we should = set this to TRUE to make sure RP setup variable can always sync latest PC v= ariable value + + + + @return The number of Unicode characters. + +**/ +EFI_STATUS SyncSetupVariable ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, + IN BOOLEAN CreateHobDataForRpDefaults +); + + +/*++ +Description: + + This function finds the matched default data and create GUID hob only fo= r RP variable . + This is used to sync Pc variable to RP variable value + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateRPVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformVar= iableHookLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Platfor= mVariableHookLib.h new file mode 100644 index 0000000000..82582bcd45 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/PlatformVariableHo= okLib.h @@ -0,0 +1,47 @@ +/** @file + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + + + + +/*++ +Description: + + This function is a hook for PlatformVariableInitPeiEntry + +--*/ +VOID PlatformVariableHookForEntry( + VOID +); + + +/*++ +Description: + + This function allow platform to generate variable hob base on different = event. + +Arguments: + IN VOID *Interface -point to EFI_PEI_READ_ONLY_VARIABL= E2_PPI + IN OUT UINT8 *phobdata, -pont to hob data + IN OUT UINT16 *pDefaultId -pointer to defautlID + +Returns: + TRUE:platform have its own variable hob that need be createn + FALSE:platform don;t need to create variable hob in this case + + +--*/ +BOOLEAN PlatformVariableHookForHobGeneration( + IN VOID *Interface, + IN OUT UINT8 *phobdata, + IN OUT UINT16 *pDefaultId +); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.h new file mode 100644 index 0000000000..ca8a2994c2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/ReadFfsLib.h @@ -0,0 +1,58 @@ +/** @file + Read FFS Library. + + @copyright + Copyright 2009 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __READ_FFS__ +#define __READ_FFS__ +#include +#include + +#define MAX_COMPRESS_ITEM 196 +#define MAX_FFS_BUFFER_SIZE 8*1024 +#define COMPRESS_DUPLICATE 1 +#define COMPRESS_SINGLE 2 + +#pragma pack(1) +typedef struct { + UINT16 Value; + UINT16 Length; + UINT8 Type; + UINT16 Offset; +} COMPRESS_ITEM; + +typedef struct { + UINT32 Signature; + UINT32 Count; + //COMPRESS_ITEM item[Count]; +} COMPRESS_HOBO_DATA; +#pragma pack() + + +BOOLEAN NormalHobToCompressHob(IN OUT VOID* hobAddr,IN OUT UINTN* size); +BOOLEAN CompressHobToNormalHob(IN OUT VOID* hobAddr,OUT UINTN* size); + +//read a FFS from FV. +UINT8* +PreMemReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN BOOLEAN skipheader + ); + +EFI_STATUS +ReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN OUT VOID *FFSData, + OUT UINT32 *FFSSize, + IN BOOLEAN skipheader + ); +EFI_STATUS ValidateCommonFvHeader ( EFI_FIRMWARE_VOLUME_HEADER = *FwVolHeader ); +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h = b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h new file mode 100644 index 0000000000..43eb60e6ca --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SetupLib.h @@ -0,0 +1,134 @@ +/** @file + This library abstracts read/write access for basic type data those value= s may be + stored into the different media. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_LIB_H_ +#define _SETUP_LIB_H_ + +#include + +typedef struct { + EFI_GUID *GuidValue; + CHAR16 *SetupName; + UINTN VariableSize; +} GROUP_INFO; + +/** + This function provides a means by which to retrieve a value for a given = option. + + Returns the data, data type and data size specified by Guid and OptionNu= mber. + + @param[in] Guid Pointer to a 128-bit unique value that designa= tes + which namespace to retrieve a value from. + @param[in] OptionNumber The option number to retrieve a current value = for. + @param[out] DataType A pointer to basic data type of the retrieved = data. + It is optional. It could be NULL. + @param[in, out] Data A pointer to the buffer to be retrieved. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid is NULL or DataSize is NULL or Option= Number is invalid. + @retval EFI_BUFFER_TOO_SMALL Input data buffer is not enough. + @retval EFI_NOT_FOUND The given option is not found. + +**/ +EFI_STATUS +EFIAPI +GetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN OUT VOID *Data, + IN OUT UINTN DataSize + ); + +/** + This function provides a means by which to set a value for a given optio= n number. + + Sets a buffer for the data specified by Guid and OptionNumber to the val= ue specified by + Data and DataSize. + If DataSize is greater than the maximum size support by OptionNumber, + then set DataSize to the maximum size supported by OptionNumber. + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value = from. + @param[in] OptionNumber The option number to set a current value f= or. + @param[in] Data A pointer to the buffer to set. + @param[in, out] DataSize The size, in bytes, of Buffer. + + @retval EFI_SUCCESS Data is successfully updated. + @retval EFI_INVALID_PARAMETER OptionNumber is invalid, Guid is NULL, or = Data is NULL, or DataSize is NULL. + @retval EFI_NOT_FOUND The given option is not found. + @retval EFI_UNSUPPORTED Set action is not supported. +**/ +EFI_STATUS +EFIAPI +SetOptionData ( + IN EFI_GUID *Guid, + IN UINTN OptionNumber, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +GetEntireConfig ( + IN OUT SETUP_DATA *SetupData + ); + +/** + Set all data in the setup + + @retval EFI_SUCCESS Data is committed successfully. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_NOT_FOUND Guid is not found. + @retval EFI_DEVICE_ERROR Data can't be committed. +**/ +EFI_STATUS +EFIAPI +SetEntireConfig ( + IN SETUP_DATA *SetupData + ); + +/** + Get Specified data in the setup + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. +**/ +EFI_STATUS +EFIAPI +GetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN OUT VOID *Variable + ); + +/** + Set Specified data in the setup + + @retval EFI_SUCCESS Data is successfully reterieved. + @retval EFI_INVALID_PARAMETER Guid or Variable is null. + @retval EFI_NOT_FOUND The given option is not found. +**/ +EFI_STATUS +EFIAPI +SetSpecificConfigGuid ( + IN EFI_GUID *Guid, + IN VOID *Variable + ); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpdateL= ib.h new file mode 100644 index 0000000000..291f687db3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaAcpiUpdateLib.h @@ -0,0 +1,38 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_ACPI_UPDATE_LIB_H +#define _PLATFORM_ACPI_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_ACPI_FIX_UPDATE_SIGNATURE SIGNATURE_32 ('A', 'C', 'P', '= F') +#define PLATFORM_ACPI_FIX_UPDATE_VERSION 01 + + +// {81129EF8-391D-4f63-AE99-58517EC077E3} +#define PLATFORM_ACPI_FIX_TABLE_GUID \ +{ 0x81129ef8, 0x391d, 0x4f63, { 0xae, 0x99, 0x58, 0x51, 0x7e, 0xc0, 0x77, = 0xe3 } } + +typedef struct { + UINT32 Signature; + UINT32 Version; + + VOID *TablePtr; + +} ACPI_FIX_UPDATE_TABLE; + +EFI_STATUS +PlatformGetAcpiFixTableDataPointer ( + IN VOID **TablePtr +); + +STATIC EFI_GUID gPlatformAcpiFixTableGuid =3D PLATFORM_ACPI_FIX_TABLE_GUI= D; + +#endif //_PLATFORM_ACPI_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSio= InfoLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSioI= nfoLib.h new file mode 100644 index 0000000000..92b50c78dd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaBoardSioInfoLib= .h @@ -0,0 +1,47 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_BOARD_SIO_INFO_H_ +#define _UBA_BOARD_SIO_INFO_H_ + +#include + +#define BOARD_SIO_INFO_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'I', 'O') +#define BOARD_SIO_INFO_DATA_VERSION 01 + +// {32C1F731-C2CD-4325-888B-60A0C3DEBB30} +#define PLATFORM_BOARD_SIO_INFO_DATA_GUID \ +{ 0x32c1f731, 0xc2cd, 0x4325, { 0x88, 0x8b, 0x60, 0xa0, 0xc3, 0xde, 0xbb, = 0x30 } } + +// +// board sio information table +// +typedef struct _PEI_BOARD_SIO_INFO{ + // + // Header information + // + INT32 Signature; + INT32 Version; + // + // SIO initialization table + // + UINT8 SioIndexPort; // SIO Index Port va= lue + UINT8 SioDataPort; // SIO Data Port val= ue + SIO_INDEX_DATA *mSioInitTable; // SIO init table + UINT8 NumSioItems; // Number of items i= n the SIO init table. +} PEI_BOARD_SIO_INFO; + +EFI_STATUS +PlatformGetBoardSioInfo ( + OUT PEI_BOARD_SIO_INFO *BoardSioInfoData +); + +STATIC EFI_GUID gPlatformBoardSioInfoDataGuid =3D PLATFORM_BOARD_SIO_INFO= _DATA_GUID; + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUp= dateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUpd= ateLib.h new file mode 100644 index 0000000000..b5f97c9b1e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClkGenUpdateLib= .h @@ -0,0 +1,49 @@ +/** @file + UBA ClockGen Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CLOCKGEN_UPDATE_LIB_H +#define _UBA_CLOCKGEN_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_CLOCKGEN_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'C', 'L', '= K') +#define PLATFORM_CLOCKGEN_UPDATE_VERSION 0x01 + +// {CF3845B1-7EB0-44ef-9D67-A80ECE6FED73} +#define PLATFORM_CLOCKGEN_CONFIG_DATA_GUID \ +{ 0xcf3845b1, 0x7eb0, 0x44ef, { 0x9d, 0x67, 0xa8, 0xe, 0xce, 0x6f, 0xed, 0= x73 } } + +#define PLATFORM_NUMBER_OF_CLOCKGEN_DATA 20 +#define PLATFORM_CLOCKGEN_NO_ID 0xFF + +typedef struct { + UINT32 Signature; + UINT32 Version; + + UINTN IdOffset; // Clockgen ID register offset + UINT8 Id; // Clockgen ID + UINTN DataLength; // Number of clockgen data for wri= te + + UINTN SpreadSpectrumByteOffset; + UINT8 SpreadSpectrumValue; + + UINT8 Data[PLATFORM_NUMBER_OF_CLOCKGEN_DATA]; + +} PLATFORM_CLOCKGEN_UPDATE_TABLE; + + +EFI_STATUS +PlatformUpdateClockgen ( + IN BOOLEAN EnableSpreadSpectrum +); + +STATIC EFI_GUID gPlatformClockgenConfigDataGuid =3D PLATFORM_CLOCKGEN_CON= FIG_DATA_GUID; + +#endif //_UBA_CLOCKGEN_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksCo= nfigLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksCon= figLib.h new file mode 100644 index 0000000000..c4114a0d54 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaClocksConfigLib= .h @@ -0,0 +1,51 @@ +/** @file + UBA Clocks Config Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CLOCKS_CONFIG_LIB_H +#define _UBA_CLOCKS_CONFIG_LIB_H + +#include +#include +#include +#include + +#define PLATFORM_CLOCKS_CONFIG_SIGNATURE SIGNATURE_32 ('P', 'C', 'L', 'K') +#define PLATFORM_CLOCKS_CONFIG_VERSION 01 + +// {34F1B964-49C7-4CB6-B9BD-7043B37C90BE} +#define PLATFORM_CLOCKS_CONFIG_DATA_GUID \ +{ 0x34f1b964, 0x49c7, 0x4cb6, { 0xb9, 0xbd, 0x70, 0x43, 0xb3, 0x7c, 0x90, = 0xbe } } + +typedef +EFI_STATUS +(*CLOCKS_CONFIG_CALLBACK) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + CLOCKS_CONFIG_CALLBACK CallUpdate; + +} PLATFORM_CLOCKS_CONFIG_TABLE; + +EFI_STATUS +ConfigurePlatformClock ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi +); + +STATIC EFI_GUID gPlatformClocksConfigDataGuid =3D PLATFORM_CLOCKS_CONFIG_= DATA_GUID; + +#endif //_UBA_CLOCKS_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInit= Lib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInitLib.h new file mode 100644 index 0000000000..d8c692c17d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioInitLib.h @@ -0,0 +1,26 @@ +/** @file + UBA GPIO Initializtion Library Header File. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_INIT_LIB_H +#define _UBA_GPIO_INIT_LIB_H + +#include +#include + +// {9282563E-AE17-4E12-B1DC-070F29F37120} +#define PLATFORM_GPIO_INIT_DATA_GUID { 0x9282563e, 0xae17, 0x4e12, { 0x= b1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } + +EFI_STATUS +PlatformInitGpios ( + VOID +); + +extern EFI_GUID gPlatformGpioInitDataGuid; + +#endif //_UBA_GPIO_INIT_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPlat= formConfig.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPl= atformConfig.h new file mode 100644 index 0000000000..e227a75c94 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioPlatformCon= fig.h @@ -0,0 +1,259 @@ +/** @file + UBA GPIO Platform Specific functions Library Header File. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_PLATFORM_CONFIG_LIB_H +#define _UBA_GPIO_PLATFORM_CONFIG_LIB_H + +#include +#include +#include + +#define PLATFORM_GPIO_CONFIG_SIGNATURE SIGNATURE_32 ('P', 'G', 'P', 'O') +#define PLATFORM_GPIO_CONFIG_VERSION 01 + + +// {d2c2adab-80c0-4a13-a0f8-adede1a51740} +#define PLATFORM_GPIO_PLATFORM_CONFIG_DATA_GUID \ +{ 0xd2c2adab, 0x80c0, 0x4a13, { 0xa0, 0xf8, 0xad, 0xed, 0xe1, 0xa5, 0x17, = 0x40 } } + +//Use this define to skip the usage of a gpio in PLATFORM_GPIO_CONFIG_TABLE +#define UNUSED_GPIO 0x0 + +typedef struct _PLATFORM_GPIO_CONFIG_TABLE{ + // + // Header information + // + INT32 Signature; + INT32 Version; + + GPIO_INIT_CONFIG GpioMfgPad; + GPIO_PAD ReservedM; + GPIO_PAD RcvJumper; + + // + // ADR pads + // + GPIO_PAD FmAdrTrigger; + GPIO_PAD AdrEnable; + + // + // OemProcMemInit pad + // + GPIO_PAD ForceTo1SConfigModePad; + + // + // Used by PC Platforms + // + GPIO_PAD QATGpio; + + // + // Used by PC platforms. This is the first GPIO pad of the pad series to= indicate Board ID + // + GPIO_PAD BoardID0Gpio; + + // + // Used to indicate proper pin to for WHEA SCI detection + // + GPIO_PAD WheaSciPad; + + // + // Used to generate CPU HP SMI + // + GPIO_PAD CpuHpSmiPad; + + // + // Used to signal FPGA error + // + GPIO_PAD FpgaErrorSingnalPad1; + + // + // Used to signal FPGA error + // + GPIO_PAD FpgaErrorSingnalPad2; + + // Flash Security override + GPIO_PAD FlashSecOverride; +} PLATFORM_GPIO_CONFIG_TABLE; + + +/** + + Reads GPIO pin to get Flash Security Override jumper status + + @param[out] Jumper - The pointer to the jumper output + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFlashSecOvrdVal ( + OUT UINT32 *Jumper +); +/** + + Reads GPIO pin to get recovery jumper status + + @param[out] RcvJumper - The pointer to the Recovery jumper input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetRcvPadVal ( + OUT UINT32 *RcvJumper +); + + +/** + + Reads GPIO pin to get FM ADR trigger pin + + @param[out] FmAdrTrigger - The pointer to the ADR trigger input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFmAdrTriggerPadVal ( + OUT UINT32 *FmAdrTrigger +); + +/** + + Sets GPIO pin to enable ADR on the board + + @param Set[in] - If TRUE means the pas should go 'high', otherwise 'lo= w' + + @retval Status - Success if GPIO set properly + +**/ +EFI_STATUS +GpioSetAdrEnablePadOutVal ( + IN BOOLEAN Set +); + +/** + + Reads GPIO pin to Force to S1 config mode pad + + @param[out] ForceS1ConfigPad - Input value of the Froce S1 Config pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetForcetoS1ConfigModePadVal ( + OUT UINT32 *ForceS1ConfigPad +); + +/** + + Reads GPIO pin related to QAT + + @param[out] QATPad - Input value of the QAT pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetQATPadVal ( + OUT UINT32 *QATPad +); + + +/** + + Get GPIO pin for SCI detection for WHEA RAS functionality + + @param[out] WheaSciPad - Input value of the Whea SCI pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetWheaSciPad ( + OUT UINT32 *WheaSciPad +); + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 1 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad1 ( + OUT UINT32 *FpgaErrorPad +); + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 2 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad2 ( + OUT UINT32 *FpgaErrorPad +); + +/** + + Get GPIO pin for CPU HP SMI detection for RAS functionality + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetCpuHpSmiPad ( + OUT UINT32 *CpuHpSmiPad +); + + +/** + + Reads GPIO pin that is first bit of the Board ID indication word + + @param[out] BoardID0Gpio - Input value of the first Board ID pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId0PadVal ( + OUT UINT32 *BoardID0Gpio +); + + +/** + + Checks whether the MDF jumper has been set + + @param None + + @retval ManufacturingMode - TRUE when MFG jumper is on, FALSE otherwise + +**/ +BOOLEAN +IsManufacturingMode ( + VOID +); + + +STATIC EFI_GUID gPlatformGpioPlatformConfigDataGuid =3D PLATFORM_GPIO_PLA= TFORM_CONFIG_DATA_GUID; + +#endif //_UBA_GPIO_PLATFORM_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpdateL= ib.h new file mode 100644 index 0000000000..72c3766908 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaGpioUpdateLib.h @@ -0,0 +1,51 @@ +/** @file + UBA GPIO Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_GPIO_UPDATE_LIB_H +#define _UBA_GPIO_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_GPIO_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'G', 'P', 'O') +#define PLATFORM_GPIO_UPDATE_VERSION 01 + +// {E02C2982-0009-46f6-AF19-DF52BB9742BF} +#define PLATFORM_GPIO_CONFIG_DATA_GUID \ +{ 0xe02c2982, 0x9, 0x46f6, { 0xaf, 0x19, 0xdf, 0x52, 0xbb, 0x97, 0x42, 0xb= f } } + +#define PLATFORM_NUMBER_OF_GPIO_REGISTERS 20 +#define PLATFORM_END_OF_GPIO_LIST 0xFFFFFFFF + +#define GPIO_NO_OR 0 +#define GPIO_NO_AND 0xFFFFFFFF + + +typedef struct { + UINT32 Register; + UINT32 Value; +} GPIO_DATA; + +typedef struct { + UINT32 Signature; + UINT32 Version; + + GPIO_DATA Gpios[PLATFORM_NUMBER_OF_GPIO_REGISTERS]; + +} PLATFORM_GPIO_UPDATE_TABLE; + + +EFI_STATUS +PlatformUpdateGpios ( + VOID +); + +STATIC EFI_GUID gPlatformGpioConfigDataGuid =3D PLATFORM_GPIO_CONFIG_DATA= _GUID; + +#endif //_UBA_GPIO_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHsioPtss= TableConfigLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHs= ioPtssTableConfigLib.h new file mode 100644 index 0000000000..49204ca2b1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaHsioPtssTableCo= nfigLib.h @@ -0,0 +1,52 @@ +/** @file + UBA Hsio Ptss Table Config Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H +#define _UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H + +#include +#include +#include +#include +#include +#include + +#define PLATFORM_HSIO_PTSS_TABLE_SIGNATURE SIGNATURE_32 ('P', 'H', 'P', '= T') +#define PLATFORM_HSIO_PTSS_TABLE_VERSION 01 + +// {47EA4CA7-F89A-42E6-89F0-20F4B72BA616} +#define PLATFORM_HSIO_PTSS_TABLE_GUID \ +{ 0x47ea4ca7, 0xf89a, 0x42e6, { 0x89, 0xf0, 0x20, 0xf4, 0xb7, 0x2b, 0xa6, = 0x16 } } + +typedef +VOID +(*HSIO_PTSS_TABLE_CONFIG_CALLBACK) ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy + +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + HSIO_PTSS_TABLE_CONFIG_CALLBACK CallUpdate; + +} PLATFORM_HSIO_PTSS_CONFIG_TABLE; + +EFI_STATUS +InstallPlatformHsioPtssTable ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy +); + +STATIC EFI_GUID gPlatformHsioPtssTableGuid =3D PLATFORM_HSIO_PTSS_TABLE_G= UID; + +#endif //_UBA_HSIO_PTSS_TABLE_CONFIG_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfi= gLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfigLib= .h new file mode 100644 index 0000000000..dc47de6bd7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioConfigLib.h @@ -0,0 +1,227 @@ +/** @file + UBA IIO Config Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_IIO_CONFIG_LIB_H +#define _UBA_IIO_CONFIG_LIB_H + +#include +#include + +#include + +#define PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'I',= 'O') +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION 01 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_2 02 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_3 03 +#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_UNSUPPORTED 0x20 + +// {EB35ED63-EACA-4e29-9516-7EDF1F818837} +#define PLATFORM_IIO_CONFIG_DATA_GUID \ +{ 0xeb35ed63, 0xeaca, 0x4e29, { 0x95, 0x16, 0x7e, 0xdf, 0x1f, 0x81, 0x88, = 0x37 } } + +// {3093F83B-5934-473e-8523-24BF297EE684} +#define PLATFORM_IIO_CONFIG_DATA_GUID_1 \ +{ 0x3093f83b, 0x5934, 0x473e, { 0x85, 0x23, 0x24, 0xbf, 0x29, 0x7e, 0xe6, = 0x84 } } + +// {1C5267A4-634B-4bf2-BFF8-9A1164E6D198} +#define PLATFORM_IIO_CONFIG_DATA_GUID_2 \ +{ 0x1c5267a4, 0x634b, 0x4bf2, { 0xbf, 0xf8, 0x9a, 0x11, 0x64, 0xe6, 0xd1, = 0x98 } } + +// {1E486CCA-048E-4702-B28C-0B677201683A} +#define PLATFORM_IIO_CONFIG_DATA_GUID_3 \ +{ 0x1e486cca, 0x48e, 0x4702, { 0xb2, 0x8c, 0xb, 0x67, 0x72, 0x1, 0x68, 0x3= a } } + +// {6FE6C559-4F35-4111-98E1-332A251512F3} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID \ +{ 0x6fe6c559, 0x4f35, 0x4111, { 0x98, 0xe1, 0x33, 0x2a, 0x25, 0x15, 0x12, = 0xf3 } } + +// {0F722F2A-650F-448a-ABB7-04EECD75BB30} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_1 \ +{ 0xf722f2a, 0x650f, 0x448a, { 0xab, 0xb7, 0x4, 0xee, 0xcd, 0x75, 0xbb, 0x= 30 } } + +// {EBD11A00-8C5C-4f71-BB9E-5394032B01F4} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_2 \ +{ 0xebd11a00, 0x8c5c, 0x4f71, { 0xbb, 0x9e, 0x53, 0x94, 0x3, 0x2b, 0x1, 0x= f4 } } + +// {123BD082-3201-465c-B139-0CB8C77208F8} +#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_3 \ +{ 0x123bd082, 0x3201, 0x465c, { 0xb1, 0x39, 0xc, 0xb8, 0xc7, 0x72, 0x8, 0x= f8 } } + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF +#define SMB_ADDR_MAX 0xFF +#define SMB_DATA_MAX 0xFF +#define NO_BIF_INPUT 0xFF +#define NOT_EXIST 0xFF + +typedef +EFI_STATUS +(*IIO_VAR_UPDATE_CALLBACK) ( + IN IIO_GLOBALS *IioGlobalData +); + +typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} IIO_BIFURCATION_DATA_ENTRY; + +typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY_EX { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card -= use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension car= d - use to dynamically determine PCIe bifurcation + UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to com= municate to different group of devices + UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to sel= ect the channel that will be used to communicate to the different group of = devices. +} IIO_BIFURCATION_DATA_ENTRY_EX; + +typedef struct _PLATFORM_IIO_SLOT_ENTRY { + UINT8 PortIndex; + UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if= slot implemented + BOOLEAN InterLockPresent; + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; + BOOLEAN Hidden; +} IIO_SLOT_CONFIG_DATA_ENTRY; + +typedef struct _PLATFORM_IIO_SLOT_ENTRY_EX { + UINT8 PortIndex; //( {1,2,3,4} =3D {1A,,1B,,1C,1D} ), ( {5,6,= 7,8} =3D {2A,2B,2C,2D} ), ( {9,10,11,12} =3D {3A,3B,3C,3D}),... + UINT16 SlotNumber; // 0xff if slot not implemented , Slot numbe= r if slot implemented + BOOLEAN InterLockPresent; // Yes / No + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; // Yes / No + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; // Yes / No + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled + BOOLEAN Hidden; // deprecate this as it should be purely bas= ed on bifurcation + + BOOLEAN CommonClock; // Yes / No - whether the both side of the = link are in same clock domain or not + BOOLEAN SRIS; // Yes / No - in case of distinct clocking = whether the separate ref. clk supports SSC or not + BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is conne= cted to Uplink port of another chip + BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to b= ifurcate the retimers explicitly + UINT8 RetimerSMBusAddress; // SMBus address to read the retimer status= and bifurcate if required + UINT8 RetimerSMBusChannel; // SMBus Mux channel to read the retimer st= atus and bifurcate if required + UINT8 RetimerWidth; // Retimer width to determine adjacent Reti= mers for the same PCIe slot + UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to comm= unicate to different group of devices + UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to sele= ct the channel that will be used to communicate to the different group of d= evices. + + BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension car= d which are supported in board thro' SMBus address (typically BW5) + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card= - use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension c= ard - use to dynamically determine PCIe bifurcation + BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension c= ard (BW5), or No + UINT8 ExtnCardRetimerSMBusAddress; // SMBus address to read the retime= r status and bifurcate if required + UINT8 ExtnCardRetimerWidth; // use to determine adjacent Retimers to= the x16 PCIe slot on which this Riser is mounted + BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indic= ates slot in which this PCIe extn. Card is mounted + UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled + UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled + + UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercept= ed between the PCIe port and the slot device. Retimer may appear mutually = exclusive. +} IIO_SLOT_CONFIG_DATA_ENTRY_EX; + + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY *IioSlotTablePtr; + UINTN IioSlotTableSize; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE; + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr; + UINTN IioSlotTableSize; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX; + +typedef struct { + UINT8 MuxSmbAddress; + UINT8 MuxSmbChannel; + UINT8 SmbAddress0; + UINT8 SmbAddress1; + UINT8 RegOffset; + UINT8 RegValue; +} MUX_SMB_ADDR; + +typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_3 { + UINT32 Signature; + UINT32 Version; + IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr; + UINTN IioBifurcationTableSize; + IIO_VAR_UPDATE_CALLBACK CallUpdate; + IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr; + UINTN IioSlotTableSize; + MUX_SMB_ADDR *RetimerInitTablePtr; +} PLATFORM_IIO_CONFIG_UPDATE_TABLE_3; + +typedef struct { + UINT8 PortHide[8]; +} PCIE_PORT_HIDE_TABLE; + +EFI_STATUS +PlatformIioConfigInit ( + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +); + +EFI_STATUS +PlatformIioConfigInit2 ( + IN UINT8 SkuPersonalityType, + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +); + +EFI_STATUS +PlatformUpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData +); + +EFI_STATUS +PlatformUpdateIioConfig_EX ( + IN IIO_GLOBALS *IioGlobalData +); + +STATIC EFI_GUID gPlatformIioConfigDataGuid =3D PLATFORM_IIO_CONFIG_DATA_G= UID; +STATIC EFI_GUID gPlatformIioConfigDataGuid_1 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_1; +STATIC EFI_GUID gPlatformIioConfigDataGuid_2 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_2; +STATIC EFI_GUID gPlatformIioConfigDataGuid_3 =3D PLATFORM_IIO_CONFIG_DATA= _GUID_3; + +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid =3D PLATFORM_IIO_CONFIG_DAT= A_DXE_GUID; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_1 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_1; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_2 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_2; +STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_3 =3D PLATFORM_IIO_CONFIG_D= ATA_DXE_GUID_3; + +#endif //_UBA_IIO_CONFIG_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioPortB= ifurcationInitLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Ub= aIioPortBifurcationInitLib.h new file mode 100644 index 0000000000..874be715f9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaIioPortBifurcat= ionInitLib.h @@ -0,0 +1,47 @@ +/** @file + UBA Iio Port Bifurcation Init Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_IIO_PORT_BIFURCATION_INIT_LIB_H +#define _UBA_IIO_PORT_BIFURCATION_INIT_LIB_H + +#include +#include +#include +#include + +#define IIO_PORT_BIFURCATION_INIT_SIGNATURE SIGNATURE_32 ('P', 'B', 'I', = 'F') +#define IIO_PORT_BIFURCATION_INIT_VERSION 01 + +// {853E5958-B3D6-4D98-A77C-100BB4ED940B} +#define IIO_PORT_BIFURCATION_INIT_GUID \ +{ 0x853e5958, 0xb3d6, 0x4d98, { 0xa7, 0x7c, 0x10, 0xb, 0xb4, 0xed, 0x94, 0= xb } } + +typedef +VOID +(*IIO_PORT_BIFURCATION_INIT_CALLBACK) ( + IN IIO_GLOBALS *IioGlobalData +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + IIO_PORT_BIFURCATION_INIT_CALLBACK CallUpdate; + +} IIO_PORT_BIFURCATION_INIT_TABLE; + +EFI_STATUS +IioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +); + +STATIC EFI_GUID gIioPortBifurcationInitDataGuid =3D IIO_PORT_BIFURCATION_= INIT_GUID; + +#endif //_UBA_IIO_PORT_BIFURCATION_INIT_LIB_H + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpd= ateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpdat= eLib.h new file mode 100644 index 0000000000..8984a70f9f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaOpromUpdateLib.h @@ -0,0 +1,115 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_OPTION_ROM_UPDATE_LIB_ +#define _PLATFORM_OPTION_ROM_UPDATE_LIB_ + + +#include +#include + +#include +#include +#include "OnboardNicStructs.h" + +#define PLATFORM_OPTION_ROM_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'B', 'D',= 'S') +#define PLATFORM_OPTION_ROM_UPDATE_VERSION 01 + + +// {371BD79C-DE79-4c5f-AA2B-BC9EBEFA988F} +STATIC EFI_GUID gPlatformOptionRomUpdateConfigDataGuid =3D +{ 0x371bd79c, 0xde79, 0x4c5f, { 0xaa, 0x2b, 0xbc, 0x9e, 0xbe, 0xfa, 0x98, = 0x8f } }; + + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PC_PCI_OPTION_ROM_TABLE; + + +typedef +BOOLEAN +(*PLATFORM_PCIE_ROOT_PORT_CHECK_CALLBACK) ( + IN UINTN Bus, + IN UINT32 PcieSlotOpromBitMap + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_OPTIONROM_TABLE) ( + IN PC_PCI_OPTION_ROM_TABLE **OptionRomTable + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_NIC_SETUP_CONFIG) ( + IN NIC_SETUP_CONFIGURATION_STUCT **NicSetupConfigTable, + IN UINTN *NumOfConfig + ); + +typedef +EFI_STATUS +(*PLATFORM_GET_NIC_CAPABILITY_TABLE) ( + IN NIC_OPTIONROM_CAPBILITY_STRUCT **NicCapabilityTable, + IN UINTN *NumOfNicCapTable + ); + +typedef +EFI_STATUS +(*PLATFORM_SETUP_PCIE_SLOT_NUMBER ) ( + OUT UINT8 *PcieSlotItemCtrl + ); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + + PLATFORM_PCIE_ROOT_PORT_CHECK_CALLBACK CallCheckRootPort; + PLATFORM_GET_OPTIONROM_TABLE GetOptionRomTable; + PLATFORM_GET_NIC_SETUP_CONFIG GetNicSetupConfigTable; + PLATFORM_GET_NIC_CAPABILITY_TABLE GetNicCapabilityTable; + PLATFORM_SETUP_PCIE_SLOT_NUMBER SetupSlotNumber; + +} PLATFORM_OPTION_ROM_UPDATE_DATA; + + +BOOLEAN +PlatformCheckPcieRootPort ( + IN UINTN Bus, + IN UINT32 PcieSlotOpromBitMap +); + +EFI_STATUS +PlatformGetOptionRomTable ( + IN PC_PCI_OPTION_ROM_TABLE **OptionRomTable +); + +EFI_STATUS +PlatformGetNicSetupConfigTable ( + IN NIC_SETUP_CONFIGURATION_STUCT **NicSetupConfigTable, + IN UINTN *NumOfConfig + ); + +EFI_STATUS +PlatformGetNicCapabilityTable ( + IN NIC_OPTIONROM_CAPBILITY_STRUCT **NicCapabilityTable, + IN UINTN *NumOfNicCapTable + ); + +EFI_STATUS +PlatformSetupPcieSlotNumber ( + OUT UINT8 *PcieSlotItemCtrl +); + +#endif //_PLATFORM_OPTION_ROM_UPDATE_LIB_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdat= eLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdateLib= .h new file mode 100644 index 0000000000..23e4c146b7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcdUpdateLib.h @@ -0,0 +1,44 @@ +/** @file + UBA PCD Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PCD_UPDATE_LIB_H +#define _UBA_PCD_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_PCD_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'P', 'C', 'D') +#define PLATFORM_PCD_UPDATE_VERSION 01 + +// {D5081573-B3B6-4a1f-9FBC-C3DEDA04CD49} +#define PLATFORM_PCD_CONFIG_DATA_GUID \ +{ 0xd5081573, 0xb3b6, 0x4a1f, { 0x9f, 0xbc, 0xc3, 0xde, 0xda, 0x4, 0xcd, 0= x49 } } + +typedef +EFI_STATUS +(*PCD_UPDATE_CALLBACK) ( + VOID +); + +typedef struct { + UINT32 Signature; + UINT32 Version; + + PCD_UPDATE_CALLBACK CallUpdate; + +} PLATFORM_PCD_UPDATE_TABLE; + +EFI_STATUS +PlatformUpdatePcds ( + VOID +); + +STATIC EFI_GUID gPlatformPcdConfigDataGuid =3D PLATFORM_PCD_CONFIG_DATA_G= UID; + +#endif //_UBA_PCD_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarly= UpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarl= yUpdateLib.h new file mode 100644 index 0000000000..f6bcd535cb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPchEarlyUpdateL= ib.h @@ -0,0 +1,63 @@ +/** @file + + @copyright + Copyright 2008 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_PCH_EARLY_UPDATE_LIB_H +#define _PLATFORM_PCH_EARLY_UPDATE_LIB_H + + +#include +#include + +#include + +#define PLATFORM_PCH_EARLY_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'P', 'C', = 'H') +#define PLATFORM_PCH_EARLY_UPDATE_VERSION 01 + + +// {1763F1D2-6A47-43f8-8279-3765A6929060} +#define PLATFORM_PCH_EARLY_CONFIG_DATA_GUID \ +{ 0x1763f1d2, 0x6a47, 0x43f8, { 0x82, 0x79, 0x37, 0x65, 0xa6, 0x92, 0x90, = 0x60 } } + + +typedef +EFI_STATUS +(*PLATFORM_PCH_LAN_CONFIG) ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +typedef +EFI_STATUS +(*PLATFORM_EARLY_INIT_HOOK) ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + + PLATFORM_PCH_LAN_CONFIG ConfigLan; + PLATFORM_EARLY_INIT_HOOK InitLateHook; + +} PLATFORM_PCH_EARLY_UPDATE_TABLE; + + +EFI_STATUS +PlatformPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + +EFI_STATUS +PlatformInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +); + + +STATIC EFI_GUID gPlatformPchEarlyConfigDataGuid =3D PLATFORM_PCH_EARLY_CO= NFIG_DATA_GUID; + +#endif //_PLATFORM_PCH_EARLY_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcieBifu= rcationUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/Uba= PcieBifurcationUpdateLib.h new file mode 100644 index 0000000000..e8a64a7a10 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPcieBifurcation= UpdateLib.h @@ -0,0 +1,130 @@ +/** @file + PCH PCIe Bifurcation Update Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PCIE_BIFURCATION_UPDATE_LIB_H +#define _UBA_PCIE_BIFURCATION_UPDATE_LIB_H + +#include +#include +#include + +#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_SIGNATURE SIGNATURE_32 ('P',= 'P', 'C', 'I') +#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_VERSION 01 + +typedef struct { + UINT8 PortIndex; + UINT16 SlotNumber; // 0xff if slot not implemented , Slot numbe= r if slot implemented + BOOLEAN InterLockPresent; // Yes / No + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; // Yes / No + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; // Yes / No + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled + BOOLEAN Hidden; // deprecate this as it should be purely bas= ed on bifurcation + + BOOLEAN CommonClock; // Yes / No - whether the both side of the = link are in same clock domain or not + BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is conne= cted to Uplink port of another chip + BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to b= ifurcate the retimers explicitly + UINT8 RetimerSMBusAddress; // SNBus address to read the retimer status= and bifurcate if required + + BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension car= d which are supported in board thro' SMBus address (typically BW5) + UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card= - use to dynamically determine PCIe bifurcation + UINT8 ExtnCardSMBusAddress; //SNBus address for the PCIe extension c= ard - use to dynamically determine PCIe bifurcation + BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension c= ard (BW5), or No + UINT8 ExtnCardRetimerSMBusAddress; // SNBus address to read the retime= r status and bifurcate if required + BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indic= ates slot in which this PCIe extn. Card is mounted + UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled + UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled + + UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercept= ed between the PCIe port and the slot device. Retimer may appear mutually = exclusive. +} PCH_SLOT_CONFIG_DATA_ENTRY_EX; + +// {187576ac-fec1-41bf-91f6-7d1ace7f2bee} +#define PLATFORM_UBA_PCIE_BIFURCATION_GUID \ +{ 0x187576ac, 0xfec1, 0x41bf, { 0x91, 0xf6, 0x7d, 0x1a, 0xce, 0x7f, 0x2b, = 0xee } } + +typedef +EFI_STATUS +(*PCIE_BIFURCATION_UPDATE_CALLBACK) ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +); + +typedef struct _PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE{ + UINT32 Signature; + UINT32 Version; + PCIE_BIFURCATION_UPDATE_CALLBACK CallPcieBifurcationUpdate; +} PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF +#define SMB_ADDR_MAX 0xFF +#define NO_BIF_INPUT 0xFF +#define PORT_0_INDEX 0 +#define PORT_1_INDEX 1 +#define PORT_2_INDEX 2 +#define PORT_3_INDEX 3 +#define PORT_4_INDEX 4 +#define PORT_5_INDEX 5 +#define PORT_6_INDEX 6 +#define PORT_7_INDEX 7 +#define PORT_8_INDEX 8 +#define PORT_9_INDEX 9 +#define PORT_10_INDEX 10 +#define PORT_11_INDEX 11 +#define PORT_12_INDEX 12 +#define PORT_13_INDEX 13 +#define PORT_14_INDEX 14 +#define PORT_15_INDEX 15 +#define PORT_16_INDEX 16 // Added dummy ports(16-27) TODO_FHF +#define PORT_17_INDEX 17 +#define PORT_18_INDEX 18 +#define PORT_19_INDEX 19 +#define PORT_20_INDEX 20 +#define PORT_21_INDEX 21 +#define PORT_22_INDEX 22 +#define PORT_23_INDEX 23 +#define PORT_24_INDEX 24 +#define PORT_25_INDEX 25 +#define PORT_26_INDEX 26 +#define PORT_27_INDEX 27 + +//------------------------------------------------------------------------= ----------- +// PCIE port index for SKX +//------------------------------------------------------------------------= ------------ +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +EFI_STATUS +PlatformGetPchPcieBifurcationConfig ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +); +STATIC EFI_GUID gPlatformUbaPcieBifurcationGuid =3D PLATFORM_UBA_PCIE_BIF= URCATION_GUID; + +#endif //_UBA_PCIE_BIFURCATION_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.h new file mode 100644 index 0000000000..429e63e6ec --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPlatLib.h @@ -0,0 +1,25 @@ +/** @file + Uba Liarary Definition Header File. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_PLAT_LIB_H_ +#define _UBA_PLAT_LIB_H_ + +#include "UbaAcpiUpdateLib.h" +#include "UbaOpromUpdateLib.h" +#include "UbaPchEarlyUpdateLib.h" +#include "UbaClkGenUpdateLib.h" +#include "UbaGpioUpdateLib.h" +#include "UbaPcdUpdateLib.h" +#include "UbaSoftStrapUpdateLib.h" +#include "UbaIioConfigLib.h" +#include "UbaSlotUpdateLib.h" +#include "UbaSystemBoardInfoLib.h" +#include "UbaSystemConfigUpdateLib.h" + +#endif // _UBA_PLAT_LIB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpda= teLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpdateL= ib.h new file mode 100644 index 0000000000..54272ae2d2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSlotUpdateLib.h @@ -0,0 +1,124 @@ +/** @file + UBA Slot Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SLOT_UPDATE_LIB_H +#define _UBA_SLOT_UPDATE_LIB_H + +#include +#include + +#define PLATFORM_SLOT_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'S', 'L', 'T') +#define PLATFORM_SLOT_UPDATE_VERSION 01 + +// {BE1CC570-03FC-4a44-8068-5B6E36CAEBB2} +#define PLATFORM_SLOT_DATA_GUID \ +{ 0xbe1cc570, 0x03fc, 0x4a44, { 0x80, 0x68, 0x5b, 0x6e, 0x36, 0xca, 0xeb, = 0xb2 } } + +// {226763AE-972C-4e3c-80D1-73B25E8CBBA3} +#define PLATFORM_SLOT_DATA_GUID2 \ +{ 0x226763ae, 0x972c, 0x4e3c, { 0x80, 0xd1, 0x73, 0xb2, 0x5e, 0x8c, 0xbb, = 0xa3 } }; + +// {56F676D3-24DF-4c77-A336-009DAE693598} +#define PLATFORM_SLOT_DATA_GUID2_1 \ +{ 0x56f676d3, 0x24df, 0x4c77, { 0xa3, 0x36, 0x01, 0x9d, 0xae, 0x69, 0x35, = 0x98 } }; + + +// {B93613E1-48F0-4b32-B3A8-4FEDFC7C1365} +#define PLATFORM_SLOT_DATA_DXE_GUID \ +{ 0xb93613e1, 0x48f0, 0x4b32, { 0xb3, 0xa8, 0x4f, 0xed, 0xfc, 0x7c, 0x13, = 0x65 } } + +// {8185B70E-9A20-4fc4-A1D6-77D54A736518} +#define PLATFORM_SLOT_DATA_DXE_GUID2 \ +{ 0x8185b70e, 0x9a20, 0x4fc4, { 0xa1, 0xd6, 0x77, 0xd5, 0x4a, 0x73, 0x65, = 0x18 } }; + +// {A87C540B-3D69-4c3b-B7F7-6383589C21CE} +#define PLATFORM_SLOT_DATA_DXE_GUID2_1 \ +{ 0xa87c540b, 0x3d69, 0x4c3b, { 0xb7, 0xf7, 0x63, 0x83, 0x58, 0x9c, 0x21, = 0xce } }; + +// {B4CB70B3-558D-4478-84CA-22616034EA16} +#define PLATFORM_PCI_SLOT_IMPLEMENTED_GUID \ +{ 0xb4cb70b3, 0x558d, 0x4478, { 0x84, 0xca, 0x22, 0x61, 0x60, 0x34, 0xea, = 0x16 } }; + +typedef struct _IIO_BROADWAY_ADDRESS_DATA_ENTRY { + UINT8 Socket; + UINT8 IouNumber; + UINT8 BroadwayAddress; // 0xff, no override bifurcation settings. + // 0-2 BW5 card can be present +} IIO_BROADWAY_ADDRESS_DATA_ENTRY; + +typedef +UINT8 +(*PLATFORM_GET_IOU_SETTING) ( + IN UINT8 IOU2Data +); + +typedef +UINT8 +(*PLATFORM_GET_IOU2_SETTING) ( + IN UINT8 SkuPersonalityType, + IN UINT8 IOU2Data +); + +typedef struct _PLATFORM_SLOT_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + IIO_BROADWAY_ADDRESS_DATA_ENTRY *BroadwayTablePtr; + PLATFORM_GET_IOU_SETTING GetIOU2Setting; + UINT8 FlagValue; +} PLATFORM_SLOT_UPDATE_TABLE; + +typedef struct _PLATFORM_SLOT_UPDATE_TABLE2 { + UINT32 Signature; + UINT32 Version; + IIO_BROADWAY_ADDRESS_DATA_ENTRY *BroadwayTablePtr; + PLATFORM_GET_IOU_SETTING GetIOU0Setting; + UINT8 FlagValue; + PLATFORM_GET_IOU2_SETTING GetIOU2Setting; +} PLATFORM_SLOT_UPDATE_TABLE2; + +typedef struct _PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + UINT8 *SlotImplementedTableDataPtr; +} PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE; + +EFI_STATUS +PlatformGetSlotTableData ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU2Setting, + IN OUT UINT8 *FlagValue +); + +EFI_STATUS +PlatformGetSlotTableData2 ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU0Setting, + IN OUT UINT8 *FlagValue, + IN OUT UINT8 *IOU2Setting, + IN UINT8 SkuPersonalityType +); + +EFI_STATUS +PlatformPchGetPciSlotImplementedTableData ( + IN OUT UINT8 **SlotImplementedTable +); + +STATIC EFI_GUID gPlatformSlotDataGuid =3D PLATFORM_SLOT_DATA_GUID; +STATIC EFI_GUID gPlatformSlotDataGuid2 =3D PLATFORM_SLOT_DATA_GUID2; +STATIC EFI_GUID gPlatformSlotDataGuid2_1 =3D PLATFORM_SLOT_DATA_GUID2_1; + + +STATIC EFI_GUID gPlatformSlotDataDxeGuid =3D PLATFORM_SLOT_DATA_DXE_GUID; +STATIC EFI_GUID gPlatformSlotDataDxeGuid2 =3D PLATFORM_SLOT_DATA_DXE_GUID= 2; +STATIC EFI_GUID gPlatformSlotDataDxeGuid2_1 =3D PLATFORM_SLOT_DATA_DXE_GU= ID2_1; + +STATIC EFI_GUID gPlatformPciSlotImplementedGuid =3D PLATFORM_PCI_SLOT_IMP= LEMENTED_GUID; + + +#endif //_UBA_SLOT_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftStra= pUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftSt= rapUpdateLib.h new file mode 100644 index 0000000000..a790b7c55a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSoftStrapUpdate= Lib.h @@ -0,0 +1,57 @@ +/** @file + UBA PCH Softstrap Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SOFT_STRAP_UPDATE_LIB_H +#define _UBA_SOFT_STRAP_UPDATE_LIB_H + +#include +#include +#include + +#define PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'S', 'T',= 'P') +#define PLATFORM_SOFT_STRAP_UPDATE_VERSION 02 + +// {F06383FE-54BD-4ae1-9C99-1DC83B6A7277} +#define PLATFORM_PCH_SOFTSTRAP_CONFIG_DATA_GUID \ +{ 0xf06383fe, 0x54bd, 0x4ae1, { 0x9c, 0x99, 0x1d, 0xc8, 0x3b, 0x6a, 0x72, = 0x77 } } + +STATIC EFI_GUID gPlatformPchSoftStrapConfigDataGuid =3D PLATFORM_PCH_SOFT= STRAP_CONFIG_DATA_GUID; + +typedef struct _PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY { + UINT8 SoftStrapNumber; + UINT8 BitfieldOffset; + UINT8 BitfieldLength; + UINT32 Value; +} PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY; + +typedef +VOID +(*PLATFORM_SPECIFIC_PCH_SOFTSTRAP_UPDATE) ( + IN UINT8 *FlashDescriptorCopy + ); + +typedef struct { + UINT32 Signature; + UINT32 Version; + PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY *PchSoftStrapTablePtr; + PLATFORM_SPECIFIC_PCH_SOFTSTRAP_UPDATE PchSoftStrapPlatformSpecificUpda= te; +} PLATFORM_PCH_SOFTSTRAP_UPDATE; + + +EFI_STATUS +GetPchSoftSoftStrapTable ( + IN VOID **PchSoftStrapTable + ); + +VOID +PlatformSpecificPchSoftStrapUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ); + +#endif //_UBA_SOFT_STRAP_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemBo= ardInfoLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystem= BoardInfoLib.h new file mode 100644 index 0000000000..e4c980e170 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemBoardInfo= Lib.h @@ -0,0 +1,36 @@ +/** @file + UBA System Board Info Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SYSTEM_BOARD_INFO_LIB_H +#define _UBA_SYSTEM_BOARD_INFO_LIB_H + +#include +#include +#include + +#define SYSTEM_SYSTEM_BOARD_INFO_SIGNATURE SIGNATURE_32 ('I', 'N', 'F', '= O') +#define SYSTEM_SYSTEM_BOARD_INFO_VERSION 01 + +typedef DXE_SYSTEM_BOARD_INFO *(*SYSTEM_BOARD_INFO_CALLBACK) (); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + SYSTEM_BOARD_INFO_CALLBACK CallUpdate; +} SYSTEM_BOARD_INFO_DATA; + +EFI_STATUS +GetSystemBoardInfo ( + IN OUT DXE_SYSTEM_BOARD_INFO **SystemboardInfoTableBuffer + ); + +extern EFI_GUID gSystemBoardInfoConfigDataGuid; + +#endif //_UBA_SYSTEM_BOARD_INFO_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemCo= nfigUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSys= temConfigUpdateLib.h new file mode 100644 index 0000000000..fd8f30daee --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaSystemConfigUpd= ateLib.h @@ -0,0 +1,42 @@ +/** @file + UBA System Config Update Library Header File. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ +#define _UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ + +#include +#include + +#include + +#define SYSTEM_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('S', 'C', 'O', 'N') +#define SYSTEM_CONFIG_UPDATE_VERSION 01 + +STATIC EFI_GUID gSystemConfigUpdateDataGuid =3D +{ 0x41037136, 0x8834, 0x4F35, { 0xBB, 0x10, 0x28, 0x0, 0x87, 0xAD, 0xB2, 0= x22 } }; + +typedef +VOID +(*IIO_DEFAULT_CONFIG_UPDATE_CALLBACK) ( + IN SYSTEM_CONFIGURATION *Default + ); + +typedef struct +{ + UINT32 Signature; + UINT32 Version; + IIO_DEFAULT_CONFIG_UPDATE_CALLBACK CallUpdateIioConfig; +} SYSTEM_CONFIG_UPDATE_DATA; + +EFI_STATUS +UpdateIioDefaultConfig ( + IN SYSTEM_CONFIGURATION *Default + ); + +#endif //_UBA_SYSTEM_CONFIG_UPDATE_LIB_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpd= ateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpdat= eLib.h new file mode 100644 index 0000000000..96cabc7dd8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaUsbOcUpdateLib.h @@ -0,0 +1,51 @@ +/** @file + UBA USB OC Update Library Header File. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_USBOC_UPDATE_LIB_H +#define _UBA_USBOC_UPDATE_LIB_H + +#include +#include +#include +#include + +#define PLATFORM_USBOC_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'U', 'S', 'B') +#define PLATFORM_USBOC_UPDATE_VERSION 02 + +// {88238275-5922-46b6-9e35-656df55df44c} +#define PEI_PLATFORM_USBOC_CONFIG_DATA_GUID \ +{ 0x88238275, 0x5922, 0x46f6, { 0x9e, 0x35, 0x65, 0x6d, 0xf5, 0x5d, 0xf4, = 0x4c } } +// {2638009e-3850-4e4b-b05d-042a32dbb9d1} +#define DXE_PLATFORM_USBOC_CONFIG_DATA_GUID \ +{ 0x2638009e, 0x3850, 0x4e4b, { 0xb0, 0x5d, 0x04, 0x2a, 0x32, 0xdb, 0xb9, = 0xd1 } } + +typedef +EFI_STATUS +(*USBOC_UPDATE_CALLBACK) ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +); + +typedef struct _PLATFORM_USBOC_UPDATE_TABLE{ + UINT32 Signature; + UINT32 Version; + USBOC_UPDATE_CALLBACK CallUsbOcUpdate; +} PLATFORM_USBOC_UPDATE_TABLE; + +EFI_STATUS +PlatformGetUsbOcMappings ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +); +STATIC EFI_GUID gPeiPlatformUbaOcConfigDataGuid =3D PEI_PLATFORM_USBOC_CO= NFIG_DATA_GUID; +STATIC EFI_GUID gDxePlatformUbaOcConfigDataGuid =3D DXE_PLATFORM_USBOC_CO= NFIG_DATA_GUID; + +#endif //_UBA_USBOC_UPDATE_LIB_H diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h= b/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h new file mode 100644 index 0000000000..b9f7acdc86 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/OnboardNicStructs.h @@ -0,0 +1,98 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ONBOARD_NIC_STRUCTS_H +#define _ONBOARD_NIC_STRUCTS_H + +#include + +#pragma pack(1) +typedef struct { + + NIC_TYPE NicType; //Onboard or IO modue? + UINT8 NicIndex; //Nic index in setup page, 1 for Nic = 1, 2 for Nic 2..... + // + //Parent + // + UINT8 RootPortBusNo; //Who is connected to? + UINT8 RootPortDevNo; + UINT8 RootPortFunNo; + + // + //Nic controller for Onboard Nic + // + UINT16 NicVID; //Vendor ID + UINT16 NicDID; //Device ID + UINT8 PortNumbers; //How many ports inside NIC? + UINT8 DescriptionIndex; //Index to Nic description list + + // + //Disable Method for Onboard Nic + // + UINT8 IsGpioCtrl; //Disable by Gpio? + UINT32 GpioForDev; //Ctrl Gpio Pin number for device + UINT8 GpioForDevValue; //what value is used to enable? + + UINT32 PortEnableGPIO[4]; //Ctrl Gpio Pin number for this port + UINT8 PortEnableGPIOValue[4];//what value is used to enable the port + UINT8 IsPchNIC; + +} NIC_SETUP_CONFIGURATION_STUCT; + +typedef struct { + UINT16 NicDID; // Device ID + UINT16 SubDID; // Subsystem ID, if preset to 0xFFFF, th= en negore this field during detection + UINT8 NIC10Gb; // 10Gbe Pxe Seupported + UINT8 PXE_Support; // Pxe supported? + UINT8 iSCSI_Support; // iScsi supported? + UINT8 FCoE_Support; // FCoe supported? + UINT8 InfB_Support; // InfiniBand supported? + UINT8 PchNIC; //PCH integrated NIC? +} NIC_OPTIONROM_CAPBILITY_STRUCT; + +typedef struct { + UINT16 IOM1DID; //Device ID for IOM1 + UINT16 IOM1SubDID; //Subsystem ID for IOM1 + UINT16 IOM2DID; //Device ID for IOM2 + UINT16 IOM2SubDID; //Subsystem ID for IOM2 + UINT16 IOM3DID; //Device ID for IOM3 + UINT16 IOM3SubDID; //Subsystem ID for IOM3 + UINT16 IOM4DID; //Device ID for IOM4 + UINT16 IOM4SubDID; //Subsystem ID for IOM4 +} IOMS_NV_VARIABLE; + +typedef struct { + UINT8 PXE10GPreValue; + UINT8 PXE1GPreValue; + UINT8 Reserved[6]; +} PXE_PREVIOUS_SETTINGS; + +#pragma pack() + +#define NIC_CHARACTER_NUMBER_FOR_VALUE 30 + +#define CPU0_IIO_BUS 0x00 +#define IIO_PCIE_PORT_1A_DEV 0x1 +#define IIO_PCIE_PORT_1A_FUN 0x0 +#define IIO_PCIE_PORT_1B_DEV 0x1 +#define IIO_PCIE_PORT_1B_FUN 0x1 +#define IIO_PCIE_PORT_2A_DEV 0x2 +#define IIO_PCIE_PORT_2A_FUN 0x0 +#define IIO_PCIE_PORT_3A_DEV 0x3 +#define IIO_PCIE_PORT_3A_FUN 0x0 +#define IIO_PCIE_PORT_3C_DEV 0x3 +#define IIO_PCIE_PORT_3C_FUN 0x2 + +#define OB_NIC_POWERVILLE_DID 0x1521 + +#define INTEL_MAC_ADDRESS_REG 0x5400 + +#define VENDOR_ID_MELLANOX 0x15B3 +#define DEVICE_ID_MELLANOX 0x1003 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h = b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h new file mode 100644 index 0000000000..a46ed4d1e1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariable.h @@ -0,0 +1,10 @@ +/** @file + Intermediate header file. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSetupVariableLbg.h" diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg= .h b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg.h new file mode 100644 index 0000000000..f87999a71f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PchSetupVariableLbg.h @@ -0,0 +1,372 @@ +/** @file + Data format for Universal Data Structure + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_VARIABLE_LBG_H_ +#define _SETUP_VARIABLE_LBG_H_ + +// for PCH_RC_CONFIGURATION +extern EFI_GUID gEfiPchSetupGuid; +#define PCH_SETUP_NAME L"PchSetup" + + +#include +#define HDAUDIO_FEATURES 3 +#define HDAUDIO_PP_MODULES 2 + +#define SATA_MODE_AHCI 0 +#define SATA_MODE_RAID 1 +#define SATA_TEST_MODE_ENABLE 1 + + +/// sSATA max ports for Wellsburg +#define PCH_MAX_SSATA_PORTS 6 + +#pragma pack(1) +typedef struct { + UINT8 Dwr_Enable; + UINT8 Dwr_Stall; + UINT8 Dwr_BmcRootPort; + + UINT8 DwrEn_PMCGBL; + UINT8 DwrEn_MEWDT; + UINT8 DwrEn_IEWDT; + + UINT8 Dwr_MeResetPrepDone; + UINT8 Dwr_IeResetPrepDone; + + // + // PCH_DEVICE_ENABLES + // + UINT8 DeepSxMode; + UINT8 Gp27WakeFromDeepSx; + UINT8 GbeRegionInvalid; + UINT8 LomLanSupported; + UINT8 PchWakeOnLan; + UINT8 PchSlpLanLowDc; + UINT8 PchCrid; + UINT8 PchRtcLock; + UINT8 PchBiosLock; + UINT8 PchAllUnLock; + UINT8 PchThermalUnlock; + UINT8 PchSerm; + + UINT8 Hpet; + UINT8 PchPort80Route; + UINT8 EnableClockSpreadSpec; + UINT8 IchPort80Route; + UINT8 PchSirqMode; + + // + // Usb Config + // + UINT8 PchUsbManualMode; + UINT8 PchGpioLockDown; + UINT8 Usb3PinsTermination; + UINT8 EnableUsb3Pin[10]; + UINT8 PchUsbHsPort[16]; + UINT8 PchUsbSsPort[10]; + UINT8 PchUsbPortDisable; + UINT8 UsbSensorHub; + UINT8 UsbSsicSupport[2]; + UINT8 XhciDisMSICapability; + UINT8 PchUsbPerPortCtl; + UINT8 PchUsb30Port[6]; + UINT8 UsbPrecondition; + UINT8 XhciIdleL1; + UINT8 Btcg; + UINT8 PchUsbDegradeBar; + // + // XHCI OC Map + // + UINT8 XhciOcMapEnabled; + // + // xDCI Config + // + UINT8 PchXdciSupport; + // + // Sata CONFIG + // + UINT8 PchSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 SataInterfaceMode; + UINT8 SataPort[PCH_MAX_SATA_PORTS]; + UINT8 SataHotPlug[PCH_MAX_SATA_PORTS]; + UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS]; + UINT8 SataSpinUp[PCH_MAX_SATA_PORTS]; + UINT8 SataExternal[PCH_MAX_SATA_PORTS]; + UINT8 SataType[PCH_MAX_SATA_PORTS]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SataRaidSrt; + UINT8 SataRaidLoadEfiDriver[PCH_MAX_SATA_CONTROLLERS]; + UINT8 SataRaidOromDelay; + UINT8 SataAlternateId; + UINT8 SataSalp; + UINT8 SataTestMode; + UINT8 PxDevSlp[PCH_MAX_SATA_PORTS]; + UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS]; + UINT16 DitoVal[PCH_MAX_SATA_PORTS]; + UINT8 DmVal[PCH_MAX_SATA_PORTS]; + UINT8 SataTopology[PCH_MAX_SATA_PORTS]; + + // + // sSata CONFIG + // + UINT8 PchsSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 sSataInterfaceMode; + UINT8 sSataPort[PCH_MAX_SSATA_PORTS]; + UINT8 sSataHotPlug[PCH_MAX_SSATA_PORTS]; + UINT8 sSataSpinUp[PCH_MAX_SSATA_PORTS]; + UINT8 sSataExternal[PCH_MAX_SSATA_PORTS]; + UINT8 sPxDevSlp[PCH_MAX_SSATA_PORTS]; + UINT8 sSataType[PCH_MAX_SSATA_PORTS]; + UINT8 sSataRaidR0; + UINT8 sSataRaidR1; + UINT8 sSataRaidR10; + UINT8 sSataRaidR5; + UINT8 sSataRaidIrrt; + UINT8 sSataRaidOub; + UINT8 sSataHddlk; + UINT8 sSataLedl; + UINT8 sSataRaidIooe; + UINT8 sSataRaidSrt; + UINT8 sSataRaidOromDelay; + UINT8 sSataAlternateId; + UINT8 sSataSalp; + UINT8 sSataTestMode; + UINT8 sEnableDitoConfig[PCH_MAX_SSATA_PORTS]; + UINT8 sDmVal[PCH_MAX_SSATA_PORTS]; + UINT8 sDitoVal[PCH_MAX_SSATA_PORTS]; + UINT8 sSataTopology[PCH_MAX_SSATA_PORTS]; + + //PCH THERMAL SENSOR + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + + UINT8 PchDmiExtSync; + UINT8 PcieDmiExtSync; + // AcpiDebug Setup Options + UINT8 PciDelayOptimizationEcr; + UINT8 PchPcieGlobalAspm; + + UINT8 PcieDmiStopAndScreamEnable; + UINT8 DmiLinkDownHangBypass; + UINT8 XTpmLen; + UINT8 PcieRootPort8xhDecode; + UINT8 Pcie8xhDecodePortIndex; + UINT8 PcieRootPortPeerMemoryWriteEnable; + UINT8 PcieComplianceTestMode; + + + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + + UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 PcieRootPortFunctionSwapping; + UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieSwEqOverride; + UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PchPcieUX8MaxPayloadSize; + UINT8 PchPcieUX16MaxPayloadSize; + UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieClockGatingDisabled; + UINT8 PcieUsbGlitchWa; + UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxReadRequestSize; + UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // PCI Bridge Resources + // + UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 MemoryThermalManagement; + UINT8 ExttsViaTsOnBoard; + UINT8 ExttsViaTsOnDimm; + UINT8 FixupPlatformSpecificSoftstraps; + + // + // SMBUS Configuration + // + UINT8 TestSmbusSpdWriteDisable; + + // + // HD-Audio Configuration + // + UINT8 PchHdAudio; + UINT8 PchHdAudioDsp; + UINT8 PchHdAudioPme; + UINT8 PchHdAudioIoBufferOwnership; + UINT8 PchHdAudioIoBufferVoltage; + UINT8 PchHdAudioCodecSelect; + UINT8 PchHdAudioFeature[HDAUDIO_FEATURES]; + UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES]; + + UINT8 DfxHdaVcType; + // + // DMI Configuration + // + UINT8 TestDmiAspmCtrl; + + + // + // + // PCIe LTR Configuration + // + UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS= ]; + UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchSataLtrOverride; + UINT8 PchSataLtrEnable; + UINT16 PchSataSnoopLatencyOverrideValue; + UINT8 PchSataSnoopLatencyOverrideMultiplier; + UINT8 PchSataLtrConfigLock; + + UINT8 PchSSataLtrOverride; + UINT16 PchSSataSnoopLatencyOverrideValue; + UINT8 PchSSataSnoopLatencyOverrideMultiplier; + UINT8 PchSSataLtrEnable; + UINT8 PchSSataLtrConfigLock; + + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + // + // Interrupt Configuration + // + UINT8 PchIoApic24119Entries; + UINT8 ShutdownPolicySelect; + + // + // DPTF SETUP items begin + // + UINT8 EnableDptf; + UINT8 EnablePchDevice; + + // + // Miscellaneous options + // + UINT8 SlpLanLowDc; + UINT8 PchLanK1Off; + UINT8 PchWakeOnWlan; + UINT8 PchWakeOnWlanDeepSx; + UINT8 StateAfterG3; + UINT8 PciePllSsc; + UINT8 FirmwareConfiguration; + UINT8 DciEn; + UINT8 PchDciAutoDetect; + + // Acpi.sd + UINT8 CSNotifyEC; + UINT8 EcLowPowerMode; + + // + // TraceHub Setup Options + // + UINT8 PchTraceHubMode; + UINT32 PchTraceHubMemReg0Size; + UINT32 PchTraceHubMemReg1Size; + UINT8 AetEnableMode; + + // + // PCH P2SB hide and lock options + // + UINT8 PchP2sbDevReveal; + UINT8 PchP2sbUnlock; + + // + // PCH SPI hide and lock options + // + UINT8 ShowSpiController; + UINT8 FlashLockDown; + + // + // PCH PMC DFX options + // + UINT8 PmcReadDisable; + + + // + // ADR Configuration + // + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + UINT8 AdrSysPwrOk; + UINT8 AdrOverClockingWdt; + UINT8 AdrCpuThermalWdt; + UINT8 AdrPmcParityError; + + // + // Audio DSP Configuration + // + UINT8 PchAudioDsp; + UINT8 PchAudioDspD3PowerGating; + UINT8 PchAudioDspAcpiMode; + UINT8 PchAudioDspBluetooth; + UINT8 PchAudioDspAcpiInterruptMode; + + // + // DFX Configuration + // + UINT8 PchEvaMrom0HookEnable; + UINT8 PchEvaMrom1HookEnable; + UINT8 TestMctpBroadcastCycle; + UINT8 PchEvaLockDown; + UINT8 PchTraceHubHide; +} PCH_SETUP; +#pragma pack() + +#endif + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h b/Pla= tform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h new file mode 100644 index 0000000000..0082cf0fa9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatDevData.h @@ -0,0 +1,183 @@ +/** @file + EFI Platform Device Data Definition Header File. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PLAT_DEVICE_DATA_H_ +#define _EFI_PLAT_DEVICE_DATA_H_ + +#include +#include + +#include +#include + + +typedef struct { + UINT8 Dev; // Device numbers of a chain of br= idges starting at PCI Bus, behind which this device is located. + UINT8 Fun; // Function numbers of a chain of = bridges starting at PCI Bus, behind which this device is located. +} DEVICE_DATA_DEV_PATH; + +typedef struct { + UINT32 UID; // The Root Bridge ID as appears i= n the device path for that bridge. +} DEVICE_DATA_RBRG_PATH; + +typedef struct { + DEVICE_DATA_RBRG_PATH RootBridgePath; // Path to starting PCI Bus from w= hich the SourceBusPath begins. This is used if there are multiple root brid= ges. Each such bridge will originate a lowest level PCI bus. + DEVICE_DATA_DEV_PATH BridgePath[4]; // Pairs of device/function number= s of a chain of bridges starting at PCI Bus, behind which this device is lo= cated. Must terminate with Dev =3D 0xFF. The size of 3 may be bumped up if = there is more bus depth levels than 3 on a particular platform. +} DEVICE_DATA_BUS_PATH; + +// +// Holds live system PCI Root Bridge info. +// +typedef struct { + EFI_HANDLE Handle; // Handle to the PCI dev= ice. + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRbIoProt; // Root Bridge IO protoc= ol. + EFI_DEVICE_PATH_PROTOCOL *DevPath; // Device path to the br= idge. + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources; // Bus/IO/Mem ranges exp= osed via the root bridge. +} DEVICE_DATA_PCI_RBRG; + +// +// Holds live system PCI device info. +// +typedef struct { + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Fun; +} LOCATION; + +typedef struct { + EFI_HANDLE Handle; // Handle to the PCI device. + EFI_PCI_IO_PROTOCOL *PciIoProt; + LOCATION Location; // Bus/Dev/Fun location of this device. + PCI_TYPE_GENERIC ConfSpace; // First 40h bytes of PCI config space for= each device. +} DEVICE_DATA_PCI_DEV; + +// +// Holds live system CPU device info. +// +typedef struct { + UINTN PackageNumber; + UINTN CoreNumber; + UINTN ThreadNumber; + UINT8 Present; + UINT8 Enabled; + UINT8 Stepping; + UINT8 Model; + UINT8 Family; + UINT8 Bsp; + UINT8 Apic; + UINT8 ApicId; + UINT8 ApicVer; + UINT8 Fpu; + UINT8 Mce; + UINT8 Cx8; +} DEVICE_DATA_CPU; + +// +// Platform hardwired data describing all I/O APICs in the system. +// +typedef struct { + UINT8 Enabled; + UINT32 Address; + UINT8 Id; + UINT8 Version; +} DEVICE_DATA_HW_IO_APIC; + +// +// Platform hardwired data describing connection of interrupt sources to l= ocal APICs. +// +typedef struct { + DEVICE_DATA_BUS_PATH SourceBusPath; + UINT8 SourceBusIrq; + UINT8 DestApicId; + UINT8 DestApicIntIn; + UINT8 IntType; + UINT16 Polarity; + UINT16 Trigger; +} DEVICE_DATA_HW_LOCAL_INT; + +// +// Platform hardwired data describing the built-in devices. +// +typedef struct { + DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes ro= ot bridge and P2P bridge chain. + DEVICE_DATA_DEV_PATH DevFun; // Device/function number of the b= uilt-in PCI device being described. 0xff if not applicable e.g., it's an IS= A device. + UINT8 DestApicId; // Destination APIC. + UINT8 DestApicIntIn; // The pin of the destination APIC= the interrupt wire is connected to. + UINT8 IntType; // As defined in the MPS. + UINT16 Polarity; // As defined in the MPS. + UINT16 Trigger; // As defined in the MPS. +} DEVICE_DATA_HW_BUILT_IN; + +// +// Platform hardwired data describing the add-in devices. +// An add-in device is defined here as a pluggable into a PCI slot. +// Thus there must be as many entries as there are slots in the system. +// The devices as defined above may have any complexity (wile complying +// with the PCI spec) including possibly multiple levels of bridges and bu= ses +// possibly with multiple devices possibly with multiple functions. +// The routing of the interrupts from such functions is governed by the +// PCI-to-PCI Bridge Architecture Specification. +// It short it requires that functions rotate mod 4 the interrupt assignme= nts +// (A/B/C/D) with PCI devices of single function devices and that the bus = depth +// does not cause such a rotation. +// +typedef struct { + DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes = root bridge and P2P bridge chain. + UINT8 Dev; // Device number of the slot bei= ng described. + UINT8 DestApicId; // Destination APIC. As defined = in the MPS. + UINT8 DestApicIntIn[4]; // Interrupt pins to destination= APIC, indexes correspond to PCI interrupt pins A/B/C/D. +} DEVICE_DATA_HW_PCI_SLOT; + +// +// Platform hardwired data describing the address space mapping. +// +typedef struct { + DEVICE_DATA_RBRG_PATH RootBridgePath; + UINT8 AddressType; + UINT64 AddressBase; + UINT64 AddressLength; +} DEVICE_DATA_HW_ADDR_SPACE_MAPPING; + +// +// This is the module global containing platform device data. +// +typedef struct { + DEVICE_DATA_HW_LOCAL_INT *LocalIntData; + UINTN LocalIntDataSize; + DEVICE_DATA_HW_ADDR_SPACE_MAPPING *AddrDataMapping; + UINTN AddrDataMappingSize; + + DEVICE_DATA_PCI_RBRG *PciRBridgeInfo; // Info for PCI Root= Bridges in the system. + DEVICE_DATA_PCI_DEV *PciDevInfo; // Info for PCI devi= ces in the system. + UINT8 PciBusNo; // Number of PCI bus= es. Assumes that PCI bus numbers are continous and start from 0. + UINT8 LegacyBusIdx; // Bus number of the= legacy bus like ISA. EISA etc. There could only be one legacy bus. It has = to be the last bus after all the PCI buses. + DEVICE_DATA_CPU *CpuInfo; // Info for all proc= essors. + UINTN CpuMax; +} DEVICE_DATA; + +// +// This is the module global containing platform device data. +// +typedef struct { + DEVICE_DATA_HW_PCI_SLOT *HwPciSlotUpdate; + UINTN HwPciSlotUpdateSize; + DEVICE_DATA_HW_BUILT_IN *HwBuiltInUpdate; + UINTN HwBuiltInUpdateSize; +} DEVICE_UPDATE_DATA; + + +typedef struct _MP_TABLE_CPU_INFO { + UINT8 ApicVersion; + UINT32 CpuSignature; + UINT32 FeatureFlags; +} MP_TABLE_CPU_INFO; + +#endif //_EFI_PLAT_DEVICE_DATA_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h new file mode 100644 index 0000000000..f2fd18bf16 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/PlatPirqData.h @@ -0,0 +1,36 @@ +/** @file + EFI Platform Pirq Data Definition Header File. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PLATF_PIRQ_DATA_H_ +#define _EFI_PLATF_PIRQ_DATA_H_ + +#include + +#define EFI_PIRQ_TABLE_SIGNATURE 0x52495024 +#define EFI_PIRQ_TABLE_VERSION 0x100 + +// +// Common path types. +// +typedef struct { + EFI_LEGACY_PIRQ_TABLE_HEADER PirqTable; +} EFI_LEGACY_PIRQ_TABLE; + +// +// This is the module global containing platform PIRQ data. +// +typedef struct { + EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY *PriorityTable; + UINTN PriorityTableSize; + EFI_LEGACY_PIRQ_TABLE *TableHead; + UINTN TableHeadSize; +} PLATFORM_PIRQ_DATA; + +#endif //_EFI_PLATF_PIRQ_DATA_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatusC= odeHandler.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatu= sCodeHandler.h new file mode 100644 index 0000000000..37c7e19e38 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/ExReportStatusCodeHand= ler.h @@ -0,0 +1,38 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ +#define __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ + + +/** + Registers ExSerialStatusCodeReportWorker as callback function for Report= StatusCode() notification. + + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_EX_RSC_HANDLER_REGISTER)( + IN CONST EFI_PEI_SERVICES **PeiServices +); + +typedef struct _EFI_EX_PEI_RSC_HANDLER_PPI { + EFI_PEI_EX_RSC_HANDLER_REGISTER RegisterExStatusCodeHandler; +} EFI_PEI_EX_RSC_HANDLER_PPI; + +extern EFI_GUID gEfiPeiExStatusCodeHandlerPpiGuid; + +#endif // __EX_REPORT_STATUS_CODE_HANDLER_PPI_H__ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h b= /Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h new file mode 100644 index 0000000000..4b9c8b677f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/SmbusPolicy.h @@ -0,0 +1,29 @@ +/** @file + Smbus Policy PPI as defined in EFI 2.0 + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SMBUS_POLICY_PPI_H +#define _PEI_SMBUS_POLICY_PPI_H + +#define PEI_SMBUS_POLICY_PPI_GUID \ + { \ + 0x63b6e435, 0x32bc, 0x49c6, { 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, = 0x6c } \ + } + +typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI; + +typedef struct _PEI_SMBUS_POLICY_PPI { + UINTN BaseAddress; + UINT32 PciAddress; + UINT8 NumRsvdAddress; + UINT8 *RsvdAddress; +} PEI_SMBUS_POLICY_PPI; + +extern EFI_GUID gPeiSmbusPolicyPpiGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h b/Pl= atform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h new file mode 100644 index 0000000000..2db2ac8b9a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Ppi/UbaCfgDb.h @@ -0,0 +1,144 @@ +/** @file + uba central config database PPI + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_PPI_H_ +#define _UBA_CONFIG_DATABASE_PPI_H_ + +// {C1176733-159F-42d5-BCB9-320660B17310} +#define UBA_CONFIG_DATABASE_PPI_GUID \ + { 0xc1176733, 0x159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73,= 0x10 } } + +typedef struct _UBA_CONFIG_DATABASE_PPI UBA_CONFIG_DATABASE_PPI; + +#define UBA_CONFIG_PPI_VERSION 01 +#define UBA_CONFIG_PPI_SIGNATURE SIGNATURE_32('U', 'S', 'K', 'U') + +// +// Functions +// + +/** + Set board's GUID and user friendly name by BoardId. + + If the BoardId is not exist in database, it will create a new platform. + + @param This uba Ppi instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_INIT_BOARD) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN UINT32 BoardId, + IN EFI_GUID *BoardGuid, OPTIONAL + IN CHAR8 *BoardName OPTIONAL + ); + +/** + Get board's GUID and user friendly name by BoardId. + + This is used when you need a BoardGuid to Add/Get platform data + + Core will create a new platform for you if the BoardId is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Ppi instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_GET_BOARD) ( + IN UBA_CONFIG_DATABASE_PPI *This, + OUT UINT32 *BoardId, + OUT EFI_GUID *BoardGuid, OPTIONAL + OUT CHAR8 *BoardName OPTIONAL + ); + +/** + Add configuration data to uba configuration database. + + @param This uba Ppi instance. + @param BoardGuid The GUID for this platform. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_ADD_DATA) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get configuration data from uba configuration database. + + @param This uba Ppi instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_UBA_CONFIG_GET_DATA) ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + IN OUT UINTN *DataSize + ); + + +// +// Multi Sku config database PPI +// +struct _UBA_CONFIG_DATABASE_PPI { + UINT32 Signature; + UINT32 Version; + + PEI_UBA_CONFIG_INIT_BOARD InitSku; + PEI_UBA_CONFIG_GET_BOARD GetSku; + + PEI_UBA_CONFIG_ADD_DATA AddData; + PEI_UBA_CONFIG_GET_DATA GetData; +}; + +extern EFI_GUID gUbaConfigDatabasePpiGuid; + +#endif // _UBA_CONFIG_DATABASE_PPI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= .h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios.h new file mode 100644 index 0000000000..b0bd90d1cb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios.h @@ -0,0 +1,1550 @@ +/** @file + The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage + under EFI and Legacy OS boot. This file also includes all the related + COMPATIBILIY16 structures and defintions. + + Note: The names for EFI_IA32_REGISTER_SET elements were picked to follow + well known naming conventions. + + Thunk is the code that switches from 32-bit protected environment into t= he 16-bit real-mode + environment. Reverse thunk is the code that does the opposite. + + @copyright + Copyright 2007 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_BIOS_H_ +#define _EFI_LEGACY_BIOS_H_ + +/// +/// +/// +#pragma pack(1) + +typedef UINT8 SERIAL_MODE; +typedef UINT8 PARALLEL_MODE; + +#define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E', '= $') + +/// +/// There is a table located within the traditional BIOS in either the 0xF= 000:xxxx or 0xE000:xxxx +/// physical address range. It is located on a 16-byte boundary and provid= es the physical address of the +/// entry point for the Compatibility16 functions. These functions provide= the platform-specific +/// information that is required by the generic EfiCompatibility code. The= functions are invoked via +/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit= physical +/// entry point. +/// +typedef struct { + /// + /// The string "$EFI" denotes the start of the EfiCompatibility table. B= yte 0 is "I," byte + /// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed = as a DWORD or UINT32. + /// + UINT32 Signature; + + /// + /// The value required such that byte checksum of TableLength equals zer= o. + /// + UINT8 TableChecksum; + + /// + /// The length of this table. + /// + UINT8 TableLength; + + /// + /// The major EFI revision for which this table was generated. + /// + UINT8 EfiMajorRevision; + + /// + /// The minor EFI revision for which this table was generated. + /// + UINT8 EfiMinorRevision; + + /// + /// The major revision of this table. + /// + UINT8 TableMajorRevision; + + /// + /// The minor revision of this table. + /// + UINT8 TableMinorRevision; + + /// + /// Reserved for future usage. + /// + UINT16 Reserved; + + /// + /// The segment of the entry point within the traditional BIOS for Compa= tibility16 functions. + /// + UINT16 Compatibility16CallSegment; + + /// + /// The offset of the entry point within the traditional BIOS for Compat= ibility16 functions. + /// + UINT16 Compatibility16CallOffset; + + /// + /// The segment of the entry point within the traditional BIOS for EfiCo= mpatibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckSegment; + + /// + /// The Offset of the entry point within the traditional BIOS for EfiCom= patibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckOffset; + + /// + /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the = IntelPlatform + ///Innovation Framework for EFI Driver Execution Environment Core Interf= ace Specification (DXE CIS). + /// + UINT32 EfiSystemTable; + + /// + /// The address of an OEM-provided identifier string. The string is null= terminated. + /// + UINT32 OemIdStringPointer; + + /// + /// The 32-bit physical address where ACPI RSD PTR is stored within the = traditional + /// BIOS. The remained of the ACPI tables are located at their EFI addre= sses. The size + /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill= in the ACPI + /// RSD PTR with either the ACPI 1.0b or 2.0 values. + /// + UINT32 AcpiRsdPtrPointer; + + /// + /// The OEM revision number. Usage is undefined but provided for OEM mod= ule usage. + /// + UINT16 OemRevision; + + /// + /// The 32-bit physical address where INT15 E820 data is stored within t= he traditional + /// BIOS. The EfiCompatibility code will fill in the E820Pointer value a= nd copy the + /// data to the indicated area. + /// + UINT32 E820Pointer; + + /// + /// The length of the E820 data and is filled in by the EfiCompatibility= code. + /// + UINT32 E820Length; + + /// + /// The 32-bit physical address where the $PIR table is stored in the tr= aditional BIOS. + /// The EfiCompatibility code will fill in the IrqRoutingTablePointer va= lue and + /// copy the data to the indicated area. + /// + UINT32 IrqRoutingTablePointer; + + /// + /// The length of the $PIR table and is filled in by the EfiCompatibilit= y code. + /// + UINT32 IrqRoutingTableLength; + + /// + /// The 32-bit physical address where the MP table is stored in the trad= itional BIOS. + /// The EfiCompatibility code will fill in the MpTablePtr value and copy= the data + /// to the indicated area. + /// + UINT32 MpTablePtr; + + /// + /// The length of the MP table and is filled in by the EfiCompatibility = code. + /// + UINT32 MpTableLength; + + /// + /// The segment of the OEM-specific INT table/code. + /// + UINT16 OemIntSegment; + + /// + /// The offset of the OEM-specific INT table/code. + /// + UINT16 OemIntOffset; + + /// + /// The segment of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Segment; + + /// + /// The offset of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Offset; + + /// + /// The segment of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Segment; + + /// + /// The offset of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Offset; + + /// + /// The segment of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmSegment; + + /// + /// The offset of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmOffset; + + /// + /// A pointer to a string identifying the independent BIOS vendor. + /// + UINT32 IbvPointer; + + /// + /// This field is NULL for all systems not supporting PCI Express. This = field is the base + /// value of the start of the PCI Express memory-mapped configuration re= gisters and + /// must be filled in prior to EfiCompatibility code issuing the Compati= bility16 function + /// Compatibility16InitializeYourself(). + /// Compatibility16InitializeYourself() is defined in Compatability16 + /// Functions. + /// + UINT32 PciExpressBase; + + /// + /// Maximum PCI bus number assigned. + /// + UINT8 LastPciBus; + + /// + /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If + /// UmaAddress is a valid address in the shadow RAM, it also indicates t= hat the region + /// from 0xC0000 to (UmaAddress - 1) can be used for Option ROM. + /// + UINT32 UmaAddress; + + /// + /// Upper Memory Area size in bytes to be set as Read/Write. If zero, no= UMA region + /// will be set as Read/Write (i.e. all Shadow RAM is set as Read-Only). + /// + UINT32 UmaSize; + + /// + /// Start Address of high memory that can be used for permanent allocati= on. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemoryAddress; + + /// + /// Size of high memory that can be used for permanent allocation in byt= es. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemorySize; +} EFI_COMPATIBILITY16_TABLE; + +/// +/// Functions provided by the CSM binary which communicate between the Efi= Compatibility +/// and Compatability16 code. +/// +/// Inconsistent with the specification here: +/// The member's name started with "Compatibility16" [defined in Intel Fra= mework +/// Compatibility Support Module Specification / 0.97 version] +/// has been changed to "Legacy16" since keeping backward compatible. +/// +typedef enum { + /// + /// Causes the Compatibility16 code to do any internal initialization re= quired. + /// Input: + /// AX =3D Compatibility16InitializeYourself + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE + /// Return: + /// AX =3D Return Status codes + /// + Legacy16InitializeYourself =3D 0x0000, + + /// + /// Causes the Compatibility16 BIOS to perform any drive number translat= ions to match the boot sequence. + /// Input: + /// AX =3D Compatibility16UpdateBbs + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE + /// Return: + /// AX =3D Returned status codes + /// + Legacy16UpdateBbs =3D 0x0001, + + /// + /// Allows the Compatibility16 code to perform any final actions before = booting. The Compatibility16 + /// code is read/write. + /// Input: + /// AX =3D Compatibility16PrepareToBoot + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure + /// Return: + /// AX =3D Returned status codes + /// + Legacy16PrepareToBoot =3D 0x0002, + + /// + /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is= Read/Only. + /// Input: + /// AX =3D Compatibility16Boot + /// Output: + /// AX =3D Returned status codes + /// + Legacy16Boot =3D 0x0003, + + /// + /// Allows the Compatibility16 code to get the last device from which a = boot was attempted. This is + /// stored in CMOS and is the priority number of the last attempted boot= device. + /// Input: + /// AX =3D Compatibility16RetrieveLastBootDevice + /// Output: + /// AX =3D Returned status codes + /// BX =3D Priority number of the boot device. + /// + Legacy16RetrieveLastBootDevice =3D 0x0004, + + /// + /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 af= ter dispatching a legacy OpROM. + /// Input: + /// AX =3D Compatibility16DispatchOprom + /// ES:BX =3D Pointer to EFI_DISPATCH_OPROM_TABLE + /// Output: + /// AX =3D Returned status codes + /// BX =3D Number of non-BBS-compliant devices found. Equals 0 if BBS = compliant. + /// + Legacy16DispatchOprom =3D 0x0005, + + /// + /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified = length and returns the address + /// of that region. + /// Input: + /// AX =3D Compatibility16GetTableAddress + /// BX =3D Allocation region + /// 00 =3D Allocate from either 0xE0000 or 0xF0000 64 KB blocks. + /// Bit 0 =3D 1 Allocate from 0xF0000 64 KB block + /// Bit 1 =3D 1 Allocate from 0xE0000 64 KB block + /// CX =3D Requested length in bytes. + /// DX =3D Required address alignment. Bit mapped. First non-zero bit = from the right is the alignment. + /// Output: + /// AX =3D Returned status codes + /// DS:BX =3D Address of the region + /// + Legacy16GetTableAddress =3D 0x0006, + + /// + /// Enables the EfiCompatibility module to do any nonstandard processing= of keyboard LEDs or state. + /// Input: + /// AX =3D Compatibility16SetKeyboardLeds + /// CL =3D LED status. + /// Bit 0 Scroll Lock 0 =3D Off + /// Bit 1 NumLock + /// Bit 2 Caps Lock + /// Output: + /// AX =3D Returned status codes + /// + Legacy16SetKeyboardLeds =3D 0x0007, + + /// + /// Enables the EfiCompatibility module to install an interrupt handler = for PCI mass media devices that + /// do not have an OpROM associated with them. An example is SATA. + /// Input: + /// AX =3D Compatibility16InstallPciHandler + /// ES:BX =3D Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure + /// Output: + /// AX =3D Returned status codes + /// + Legacy16InstallPciHandler =3D 0x0008 +} EFI_COMPATIBILITY_FUNCTIONS; + + +/// +/// EFI_DISPATCH_OPROM_TABLE +/// +typedef struct { + UINT16 PnPInstallationCheckSegment; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 PnPInstallationCheckOffset; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 OpromSegment; ///< The segment where the OpROM w= as placed. Offset is assumed to be 3. + UINT8 PciBus; ///< The PCI bus. + UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI f= unction. + UINT8 NumberBbsEntries; ///< The number of valid BBS table= entries upon entry and exit. The IBV code may + ///< increase this number, if BBS-= compliant devices also hook INTs in order to force the + ///< OpROM BIOS Setup to be execut= ed. + UINT32 BbsTablePointer; ///< A pointer to the BBS table. + UINT16 RuntimeSegment; ///< The segment where the OpROM c= an be relocated to. If this value is 0x0000, this + ///< means that the relocation of = this run time code is not supported. + ///< Inconsistent with specificati= on here: + ///< The member's name "OpromDesti= nationSegment" [defined in Intel Framework Compatibility Support Module Spe= cification / 0.97 version] + ///< has been changed to "RuntimeS= egment" since keeping backward compatible. + +} EFI_DISPATCH_OPROM_TABLE; + +/// +/// EFI_TO_COMPATIBILITY16_INIT_TABLE +/// +typedef struct { + /// + /// Starting address of memory under 1 MB. The ending address is assumed= to be 640 KB or 0x9FFFF. + /// + UINT32 BiosLessThan1MB; + + /// + /// The starting address of the high memory block. + /// + UINT32 HiPmmMemory; + + /// + /// The length of high memory block. + /// + UINT32 HiPmmMemorySizeInBytes; + + /// + /// The segment of the reverse thunk call code. + /// + UINT16 ReverseThunkCallSegment; + + /// + /// The offset of the reverse thunk call code. + /// + UINT16 ReverseThunkCallOffset; + + /// + /// The number of E820 entries copied to the Compatibility16 BIOS. + /// + UINT32 NumberE820Entries; + + /// + /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory. + /// + UINT32 OsMemoryAbove1Mb; + + /// + /// The start of thunk code in main memory. Memory cannot be used by BIO= S or PMM. + /// + UINT32 ThunkStart; + + /// + /// The size of the thunk code. + /// + UINT32 ThunkSizeInBytes; + + /// + /// Starting address of memory under 1 MB. + /// + UINT32 LowPmmMemory; + + /// + /// The length of low Memory block. + /// + UINT32 LowPmmMemorySizeInBytes; +} EFI_TO_COMPATIBILITY16_INIT_TABLE; + +/// +/// DEVICE_PRODUCER_SERIAL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned = to the serial port. + UINT8 Irq; ///< IRQ assigned to the s= erial port. + SERIAL_MODE Mode; ///< Mode of serial port. = Values are defined below. +} DEVICE_PRODUCER_SERIAL; + +/// +/// DEVICE_PRODUCER_SERIAL's modes. +///@{ +#define DEVICE_SERIAL_MODE_NORMAL 0x00 +#define DEVICE_SERIAL_MODE_IRDA 0x01 +#define DEVICE_SERIAL_MODE_ASK_IR 0x02 +#define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00 +#define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10 +///@) + +/// +/// DEVICE_PRODUCER_PARALLEL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned to= the parallel port. + UINT8 Irq; ///< IRQ assigned to the par= allel port. + UINT8 Dma; ///< DMA assigned to the par= allel port. + PARALLEL_MODE Mode; ///< Mode of the parallel po= rt. Values are defined below. +} DEVICE_PRODUCER_PARALLEL; + +/// +/// DEVICE_PRODUCER_PARALLEL's modes. +///@{ +#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00 +#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01 +#define DEVICE_PARALLEL_MODE_MODE_EPP 0x02 +#define DEVICE_PARALLEL_MODE_MODE_ECP 0x03 +///@} + +/// +/// DEVICE_PRODUCER_FLOPPY +/// +typedef struct { + UINT16 Address; ///< I/O address ass= igned to the floppy. + UINT8 Irq; ///< IRQ assigned to= the floppy. + UINT8 Dma; ///< DMA assigned to= the floppy. + UINT8 NumberOfFloppy; ///< Number of flopp= ies in the system. +} DEVICE_PRODUCER_FLOPPY; + +/// +/// LEGACY_DEVICE_FLAGS +/// +typedef struct { + UINT32 A20Kybd : 1; ///< A20 controller = by keyboard controller. + UINT32 A20Port90 : 1; ///< A20 controlled = by port 0x92. + UINT32 Reserved : 30; ///< Reserved for fu= ture usage. +} LEGACY_DEVICE_FLAGS; + +/// +/// DEVICE_PRODUCER_DATA_HEADER +/// +typedef struct { + DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial p= ort x. Type DEVICE_PRODUCER_SERIAL is defined below. + DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel= port x. Type DEVICE_PRODUCER_PARALLEL is defined below. + DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. = Type DEVICE_PRODUCER_FLOPPY is defined below. + UINT8 MousePresent; ///< Flag to indicate = if mouse is present. + LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boo= lean state information passed to CSM. +} DEVICE_PRODUCER_DATA_HEADER; + +/// +/// ATAPI_IDENTIFY +/// +typedef struct { + UINT16 Raw[256]; ///< Raw data from the I= DE IdentifyDrive command. +} ATAPI_IDENTIFY; + +/// +/// HDD_INFO +/// +typedef struct { + /// + /// Status of IDE device. Values are defined below. There is one HDD_INF= O structure + /// per IDE controller. The IdentifyDrive is per drive. Index 0 is maste= r and index + /// 1 is slave. + /// + UINT16 Status; + + /// + /// PCI bus of IDE controller. + /// + UINT32 Bus; + + /// + /// PCI device of IDE controller. + /// + UINT32 Device; + + /// + /// PCI function of IDE controller. + /// + UINT32 Function; + + /// + /// Command ports base address. + /// + UINT16 CommandBaseAddress; + + /// + /// Control ports base address. + /// + UINT16 ControlBaseAddress; + + /// + /// Bus master address. + /// + UINT16 BusMasterAddress; + + UINT8 HddIrq; + + /// + /// Data that identifies the drive data; one per possible attached drive. + /// + ATAPI_IDENTIFY IdentifyDrive[2]; +} HDD_INFO; + +/// +/// HDD_INFO status bits +/// +#define HDD_PRIMARY 0x01 +#define HDD_SECONDARY 0x02 +#define HDD_MASTER_ATAPI_CDROM 0x04 +#define HDD_SLAVE_ATAPI_CDROM 0x08 +#define HDD_MASTER_IDE 0x20 +#define HDD_SLAVE_IDE 0x40 +#define HDD_MASTER_ATAPI_ZIPDISK 0x10 +#define HDD_SLAVE_ATAPI_ZIPDISK 0x80 + +/// +/// BBS_STATUS_FLAGS;\. +/// +typedef struct { + UINT16 OldPosition : 4; ///< Prior priorit= y. + UINT16 Reserved1 : 4; ///< Reserved for = future use. + UINT16 Enabled : 1; ///< If 0, ignore = this entry. + UINT16 Failed : 1; ///< 0 =3D Not kno= wn if boot failure occurred. + ///< 1 =3D Boot at= tempted failed. + + /// + /// State of media present. + /// 00 =3D No bootable media is present in the device. + /// 01 =3D Unknown if a bootable media present. + /// 10 =3D Media is present and appears bootable. + /// 11 =3D Reserved. + /// + UINT16 MediaPresent : 2; + UINT16 Reserved2 : 4; ///< Reserved for = future use. +} BBS_STATUS_FLAGS; + +/// +/// BBS_TABLE, device type values & boot priority values. +/// +typedef struct { + /// + /// The boot priority for this boot device. Values are defined below. + /// + UINT16 BootPriority; + + /// + /// The PCI bus for this boot device. + /// + UINT32 Bus; + + /// + /// The PCI device for this boot device. + /// + UINT32 Device; + + /// + /// The PCI function for the boot device. + /// + UINT32 Function; + + /// + /// The PCI class for this boot device. + /// + UINT8 Class; + + /// + /// The PCI Subclass for this boot device. + /// + UINT8 SubClass; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringSegment; + + /// + /// BBS device type. BBS device types are defined below. + /// + UINT16 DeviceType; + + /// + /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below. + /// + BBS_STATUS_FLAGS StatusFlags; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerOffset; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerSegment; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringSegment; + + /// + /// Reserved. + /// + UINT32 InitPerReserved; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq13Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq18Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq19Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq40Handler; + UINT8 AssignedDriveNumber; + UINT32 AdditionalIrq41Handler; + UINT32 AdditionalIrq46Handler; + UINT32 IBV1; + UINT32 IBV2; +} BBS_TABLE; + +/// +/// BBS device type values +///@{ +#define BBS_FLOPPY 0x01 +#define BBS_HARDDISK 0x02 +#define BBS_CDROM 0x03 +#define BBS_PCMCIA 0x04 +#define BBS_USB 0x05 +#define BBS_EMBED_NETWORK 0x06 +#define BBS_BEV_DEVICE 0x80 +#define BBS_UNKNOWN 0xff +///@} + +/// +/// BBS boot priority values +///@{ +#define BBS_DO_NOT_BOOT_FROM 0xFFFC +#define BBS_LOWEST_PRIORITY 0xFFFD +#define BBS_UNPRIORITIZED_ENTRY 0xFFFE +#define BBS_IGNORE_ENTRY 0xFFFF +///@} + +/// +/// SMM_ATTRIBUTES +/// +typedef struct { + /// + /// Access mechanism used to generate the soft SMI. Defined types are be= low. The other + /// values are reserved for future usage. + /// + UINT16 Type : 3; + + /// + /// The size of "port" in bits. Defined values are below. + /// + UINT16 PortGranularity : 3; + + /// + /// The size of data in bits. Defined values are below. + /// + UINT16 DataGranularity : 3; + + /// + /// Reserved for future use. + /// + UINT16 Reserved : 7; +} SMM_ATTRIBUTES; + +/// +/// SMM_ATTRIBUTES type values. +///@{ +#define STANDARD_IO 0x00 +#define STANDARD_MEMORY 0x01 +///@} + +/// +/// SMM_ATTRIBUTES port size constants. +///@{ +#define PORT_SIZE_8 0x00 +#define PORT_SIZE_16 0x01 +#define PORT_SIZE_32 0x02 +#define PORT_SIZE_64 0x03 +///@} + +/// +/// SMM_ATTRIBUTES data size constants. +///@{ +#define DATA_SIZE_8 0x00 +#define DATA_SIZE_16 0x01 +#define DATA_SIZE_32 0x02 +#define DATA_SIZE_64 0x03 +///@} + +/// +/// SMM_FUNCTION & relating constants. +/// +typedef struct { + UINT16 Function : 15; + UINT16 Owner : 1; +} SMM_FUNCTION; + +/// +/// SMM_FUNCTION Function constants. +///@{ +#define INT15_D042 0x0000 +#define GET_USB_BOOT_INFO 0x0001 +#define DMI_PNP_50_57 0x0002 +///@} + +/// +/// SMM_FUNCTION Owner constants. +///@{ +#define STANDARD_OWNER 0x0 +#define OEM_OWNER 0x1 +///@} + +/// +/// This structure assumes both port and data sizes are 1. SmmAttribute mu= st be +/// properly to reflect that assumption. +/// +typedef struct { + /// + /// Describes the access mechanism, SmmPort, and SmmData sizes. Type + /// SMM_ATTRIBUTES is defined below. + /// + SMM_ATTRIBUTES SmmAttributes; + + /// + /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below. + /// + SMM_FUNCTION SmmFunction; + + /// + /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmPort; + + /// + /// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmData; +} SMM_ENTRY; + +/// +/// SMM_TABLE +/// +typedef struct { + UINT16 NumSmmEntries; ///< Number of entri= es represented by SmmEntry. + SMM_ENTRY SmmEntry; ///< One entry per f= unction. Type SMM_ENTRY is defined below. +} SMM_TABLE; + +/// +/// UDC_ATTRIBUTES +/// +typedef struct { + /// + /// This bit set indicates that the ServiceAreaData is valid. + /// + UINT8 DirectoryServiceValidity : 1; + + /// + /// This bit set indicates to use the Reserve Area Boot Code Address (RA= CBA) only if + /// DirectoryServiceValidity is 0. + /// + UINT8 RabcaUsedFlag : 1; + + /// + /// This bit set indicates to execute hard disk diagnostics. + /// + UINT8 ExecuteHddDiagnosticsFlag : 1; + + /// + /// Reserved for future use. Set to 0. + /// + UINT8 Reserved : 5; +} UDC_ATTRIBUTES; + +/// +/// UD_TABLE +/// +typedef struct { + /// + /// This field contains the bit-mapped attributes of the PARTIES informa= tion. Type + /// UDC_ATTRIBUTES is defined below. + /// + UDC_ATTRIBUTES Attributes; + + /// + /// This field contains the zero-based device on which the selected + /// ServiceDataArea is present. It is 0 for master and 1 for the slave d= evice. + /// + UINT8 DeviceNumber; + + /// + /// This field contains the zero-based index into the BbsTable for the p= arent device. + /// This index allows the user to reference the parent device informatio= n such as PCI + /// bus, device function. + /// + UINT8 BbsTableEntryNumberForParentDevice; + + /// + /// This field contains the zero-based index into the BbsTable for the b= oot entry. + /// + UINT8 BbsTableEntryNumberForBoot; + + /// + /// This field contains the zero-based index into the BbsTable for the H= DD diagnostics entry. + /// + UINT8 BbsTableEntryNumberForHddDiag; + + /// + /// The raw Beer data. + /// + UINT8 BeerData[128]; + + /// + /// The raw data of selected service area. + /// + UINT8 ServiceAreaData[64]; +} UD_TABLE; + +#define EFI_TO_LEGACY_MAJOR_VERSION 0x02 +#define EFI_TO_LEGACY_MINOR_VERSION 0x00 +#define MAX_IDE_CONTROLLER 8 + +/// +/// EFI_TO_COMPATIBILITY16_BOOT_TABLE +/// +typedef struct { + UINT16 MajorVersion; ///< The= EfiCompatibility major version number. + UINT16 MinorVersion; ///< The= EfiCompatibility minor version number. + UINT32 AcpiTable; ///< The= location of the RSDT ACPI table. < 4G range. + UINT32 SmbiosTable; ///< The= location of the SMBIOS table in EFI memory. < 4G range. + UINT32 SmbiosTableLength; + // + // Legacy SIO state + // + DEVICE_PRODUCER_DATA_HEADER SioData; ///< Sta= ndard traditional device information. + UINT16 DevicePathType; ///< The= default boot type. + UINT16 PciIrqMask; ///< Mas= k of which IRQs have been assigned to PCI. + UINT32 NumberE820Entries; ///< Num= ber of E820 entries. The number can change from the + ///< Com= patibility16InitializeYourself() function. + // + // Controller & Drive Identify[2] per controller information + // + HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Har= d disk drive information, including raw Identify Drive data. + UINT32 NumberBbsEntries; ///< Num= ber of entries in the BBS table + UINT32 BbsTable; ///< A p= ointer to the BBS table. Type BBS_TABLE is defined below. + UINT32 SmmTable; ///< A p= ointer to the SMM table. Type SMM_TABLE is defined below. + UINT32 OsMemoryAbove1Mb; ///< The= amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can + ///< dif= fer from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more + ///< mem= ory may have been discovered. + UINT32 UnconventionalDeviceTable; ///< Inf= ormation to boot off an unconventional device like a PARTIES partition. Type + ///< UD_= TABLE is defined below. +} EFI_TO_COMPATIBILITY16_BOOT_TABLE; + +/// +/// EFI_LEGACY_INSTALL_PCI_HANDLER +/// +typedef struct { + UINT8 PciBus; ///< The PCI bus o= f the device. + UINT8 PciDeviceFun; ///< The PCI devic= e in bits 7:3 and function in bits 2:0. + UINT8 PciSegment; ///< The PCI segme= nt of the device. + UINT8 PciClass; ///< The PCI class= code of the device. + UINT8 PciSubclass; ///< The PCI subcl= ass code of the device. + UINT8 PciInterface; ///< The PCI inter= face code of the device. + // + // Primary section + // + UINT8 PrimaryIrq; ///< The primary d= evice IRQ. + UINT8 PrimaryReserved; ///< Reserved. + UINT16 PrimaryControl; ///< The primary d= evice control I/O base. + UINT16 PrimaryBase; ///< The primary d= evice I/O base. + UINT16 PrimaryBusMaster; ///< The primary d= evice bus master I/O base. + // + // Secondary Section + // + UINT8 SecondaryIrq; ///< The secondary= device IRQ. + UINT8 SecondaryReserved; ///< Reserved. + UINT16 SecondaryControl; ///< The secondary= device control I/O base. + UINT16 SecondaryBase; ///< The secondary= device I/O base. + UINT16 SecondaryBusMaster; ///< The secondary= device bus master I/O base. +} EFI_LEGACY_INSTALL_PCI_HANDLER; + +// +// Restore default pack value +// +#pragma pack() + +#define EFI_LEGACY_BIOS_PROTOCOL_GUID \ + { \ + 0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e,= 0x2d } \ + } + +typedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL; + +/// +/// Flags returned by CheckPciRom(). +/// +#define NO_ROM 0x00 +#define ROM_FOUND 0x01 +#define VALID_LEGACY_ROM 0x02 +#define ROM_WITH_CONFIG 0x04 ///< Not defined in the Framework CSM S= pecification. + +/// +/// The following macros do not appear in the Framework CSM Specification = and +/// are kept for backward compatibility only. They convert 32-bit address= (_Adr) +/// to Segment:Offset 16-bit form. +/// +///@{ +#define EFI_SEGMENT(_Adr) (UINT16) ((UINT16) (((UINTN) (_Adr)) >> 4) &= 0xf000) +#define EFI_OFFSET(_Adr) (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xff= ff) +///@} + +#define CARRY_FLAG 0x01 + +/// +/// EFI_EFLAGS_REG +/// +typedef struct { + UINT32 CF:1; + UINT32 Reserved1:1; + UINT32 PF:1; + UINT32 Reserved2:1; + UINT32 AF:1; + UINT32 Reserved3:1; + UINT32 ZF:1; + UINT32 SF:1; + UINT32 TF:1; + UINT32 IF:1; + UINT32 DF:1; + UINT32 OF:1; + UINT32 IOPL:2; + UINT32 NT:1; + UINT32 Reserved4:2; + UINT32 VM:1; + UINT32 Reserved5:14; +} EFI_EFLAGS_REG; + +/// +/// EFI_DWORD_REGS +/// +typedef struct { + UINT32 EAX; + UINT32 EBX; + UINT32 ECX; + UINT32 EDX; + UINT32 ESI; + UINT32 EDI; + EFI_EFLAGS_REG EFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT32 EBP; + UINT32 ESP; +} EFI_DWORD_REGS; + +/// +/// EFI_FLAGS_REG +/// +typedef struct { + UINT16 CF:1; + UINT16 Reserved1:1; + UINT16 PF:1; + UINT16 Reserved2:1; + UINT16 AF:1; + UINT16 Reserved3:1; + UINT16 ZF:1; + UINT16 SF:1; + UINT16 TF:1; + UINT16 IF:1; + UINT16 DF:1; + UINT16 OF:1; + UINT16 IOPL:2; + UINT16 NT:1; + UINT16 Reserved4:1; +} EFI_FLAGS_REG; + +/// +/// EFI_WORD_REGS +/// +typedef struct { + UINT16 AX; + UINT16 ReservedAX; + UINT16 BX; + UINT16 ReservedBX; + UINT16 CX; + UINT16 ReservedCX; + UINT16 DX; + UINT16 ReservedDX; + UINT16 SI; + UINT16 ReservedSI; + UINT16 DI; + UINT16 ReservedDI; + EFI_FLAGS_REG Flags; + UINT16 ReservedFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT16 BP; + UINT16 ReservedBP; + UINT16 SP; + UINT16 ReservedSP; +} EFI_WORD_REGS; + +/// +/// EFI_BYTE_REGS +/// +typedef struct { + UINT8 AL, AH; + UINT16 ReservedAX; + UINT8 BL, BH; + UINT16 ReservedBX; + UINT8 CL, CH; + UINT16 ReservedCX; + UINT8 DL, DH; + UINT16 ReservedDX; +} EFI_BYTE_REGS; + +/// +/// EFI_IA32_REGISTER_SET +/// +typedef union { + EFI_DWORD_REGS E; + EFI_WORD_REGS X; + EFI_BYTE_REGS H; +} EFI_IA32_REGISTER_SET; + +/** + Thunk to 16-bit real mode and execute a software interrupt with a vector + of BiosInt. Regs will contain the 16-bit register context on entry and + exit. + + @param[in] This The protocol instance pointer. + @param[in] BiosInt The processor interrupt vector to invoke. + @param[in,out] Reg Register contexted passed into (and returned) f= rom thunk to + 16-bit mode. + + @retval TRUE Thunk completed with no BIOS errors in the t= arget code. See Regs for status. + @retval FALSE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_INT86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 BiosInt, + IN OUT EFI_IA32_REGISTER_SET *Regs + ); + +/** + Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the + 16-bit register context on entry and exit. Arguments can be passed on + the Stack argument + + @param[in] This The protocol instance pointer. + @param[in] Segment The segemnt of 16-bit mode call. + @param[in] Offset The offset of 16-bit mdoe call. + @param[in] Reg Register contexted passed into (and returned) fro= m thunk to + 16-bit mode. + @param[in] Stack The caller allocated stack used to pass arguments. + @param[in] StackSize The size of Stack in bytes. + + @retval FALSE Thunk completed with no BIOS errors in the= target code. See Regs for status. @retval = TRUE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_FARCALL86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT16 Segment, + IN UINT16 Offset, + IN EFI_IA32_REGISTER_SET *Regs, + IN VOID *Stack, + IN UINTN StackSize + ); + +/** + Test to see if a legacy PCI ROM exists for this device. Optionally return + the Legacy ROM instance for this PCI device. + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR wi= ll be loaded + @param[out] RomImage Return the legacy PCI ROM for this device. + @param[out] RomSize The size of ROM Image. + @param[out] Flags Indicates if ROM found and if PC-AT. Multiple bi= ts can be set as follows: + - 00 =3D No ROM. + - 01 =3D ROM Found. + - 02 =3D ROM is a valid legacy ROM. + + @retval EFI_SUCCESS The Legacy Option ROM available for this device + @retval EFI_UNSUPPORTED The Legacy Option ROM is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_CHECK_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, OPTIONAL + OUT UINTN *RomSize, OPTIONAL + OUT UINTN *Flags + ); + +/** + Load a legacy PC-AT OPROM on the PciHandle device. Return information + about how many disks were added by the OPROM and the shadow address and + size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C: + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM= BAR will be loaded. + This value is NULL if RomImage is non-NUL= L. This is the normal + case. + @param[in] RomImage A PCI PC-AT ROM image. This argument is n= on-NULL if there is + no hardware associated with the ROM and t= hus no PciHandle, + otherwise is must be NULL. + Example is PXE base code. + @param[out] Flags The type of ROM discovered. Multiple bits= can be set, as follows: + - 00 =3D No ROM. + - 01 =3D ROM found. + - 02 =3D ROM is a valid legacy ROM. + @param[out] DiskStart The disk number of first device hooked by= the ROM. If DiskStart + is the same as DiskEnd no disked were hoo= ked. + @param[out] DiskEnd disk number of the last device hooked by = the ROM. + @param[out] RomShadowAddress Shadow address of PC-AT ROM. + @param[out] RomShadowSize Size of RomShadowAddress in bytes. + + @retval EFI_SUCCESS Thunk completed, see Regs for status. + @retval EFI_INVALID_PARAMETER PciHandle not found + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_INSTALL_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + IN VOID **RomImage, + OUT UINTN *Flags, + OUT UINT8 *DiskStart, OPTIONAL + OUT UINT8 *DiskEnd, OPTIONAL + OUT VOID **RomShadowAddress, OPTIONAL + OUT UINT32 *ShadowedRomSize OPTIONAL + ); + +/** + This function attempts to traditionally boot the specified BootOption. I= f the EFI context has + been compromised, this function will not return. This procedure is not u= sed for loading an EFI-aware + OS off a traditional device. The following actions occur: + - Get EFI SMBIOS data structures, convert them to a traditional format, = and copy to + Compatibility16. + - Get a pointer to ACPI data structures and copy the Compatibility16 RSD= PTR to F0000 block. + - Find the traditional SMI handler from a firmware volume and register t= he traditional SMI + handler with the EFI SMI handler. + - Build onboard IDE information and pass this information to the Compati= bility16 code. + - Make sure all PCI Interrupt Line registers are programmed to match 825= 9. + - Reconfigure SIO devices from EFI mode (polled) into traditional mode (= interrupt driven). + - Shadow all PCI ROMs. + - Set up BDA and EBDA standard areas before the legacy boot. + - Construct the Compatibility16 boot memory map and pass it to the Compa= tibility16 code. + - Invoke the Compatibility16 table function Compatibility16PrepareToBoot= (). This + invocation causes a thunk into the Compatibility16 code, which sets al= l appropriate internal + data structures. The boot device list is a parameter. + - Invoke the Compatibility16 Table function Compatibility16Boot(). This = invocation + causes a thunk into the Compatibility16 code, which does an INT19. + - If the Compatibility16Boot() function returns, then the boot failed in= a graceful + manner--meaning that the EFI code is still valid. An ungraceful boot f= ailure causes a reset because the state + of EFI code is unknown. + + @param[in] This The protocol instance pointer. + @param[in] BootOption The EFI Device Path from BootXXXX variable. + @param[in] LoadOptionSize The size of LoadOption in size. + @param[in] LoadOption LThe oadOption from BootXXXX variable. + + @retval EFI_DEVICE_ERROR Failed to boot from any boot device and me= mory is uncorrupted. Note: This function nor= mally does not returns. It will either boot the = OS or reset the system if memory has been "corrupted" by loading = a boot sector and passing control to it. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN BBS_BBS_DEVICE_PATH *BootOption, + IN UINT32 LoadOptionsSize, + IN VOID *LoadOptions + ); + +/** + This function takes the Leds input parameter and sets/resets the BDA acc= ordingly. + Leds is also passed to Compatibility16 code, in case any special process= ing is required. + This function is normally called from EFI Setup drivers that handle user= -selectable + keyboard options such as boot with NUM LOCK on/off. This function does n= ot + touch the keyboard or keyboard LEDs but only the BDA. + + @param[in] This The protocol instance pointer. + @param[in] Leds The status of current Scroll, Num & Cap lock LEDS: + - Bit 0 is Scroll Lock 0 =3D Not locked. + - Bit 1 is Num Lock. + - Bit 2 is Caps Lock. + + @retval EFI_SUCCESS The BDA was updated successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 Leds + ); + +/** + Retrieve legacy BBS info and assign boot priority. + + @param[in] This The protocol instance pointer. + @param[out] HddCount The number of HDD_INFO structures. + @param[out] HddInfo Onboard IDE controller information. + @param[out] BbsCount The number of BBS_TABLE structures. + @param[in,out] BbsTable Points to List of BBS_TABLE. + + @retval EFI_SUCCESS Tables were returned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_BBS_INFO)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *HddCount, + OUT HDD_INFO **HddInfo, + OUT UINT16 *BbsCount, + IN OUT BBS_TABLE **BbsTable + ); + +/** + Assign drive number to legacy HDD drives prior to booting an EFI + aware OS so the OS can access drives without an EFI driver. + + @param[in] This The protocol instance pointer. + @param[out] BbsCount The number of BBS_TABLE structures + @param[out] BbsTable List of BBS entries + + @retval EFI_SUCCESS Drive numbers assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *BbsCount, + OUT BBS_TABLE **BbsTable + ); + +/** + To boot from an unconventional device like parties and/or execute + HDD diagnostics. + + @param[in] This The protocol instance pointer. + @param[in] Attributes How to interpret the other input parameter= s. + @param[in] BbsEntry The 0-based index into the BbsTable for th= e parent + device. + @param[in] BeerData A pointer to the 128 bytes of ram BEER dat= a. + @param[in] ServiceAreaData A pointer to the 64 bytes of raw Service A= rea data. The + caller must provide a pointer to the speci= fic Service + Area and not the start all Service Areas. + + @retval EFI_INVALID_PARAMETER If error. Does NOT return if no error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UDC_ATTRIBUTES Attributes, + IN UINTN BbsEntry, + IN VOID *BeerData, + IN VOID *ServiceAreaData + ); + +/** + Shadow all legacy16 OPROMs that haven't been shadowed. + Warning: Use this with caution. This routine disconnects all EFI + drivers. If used externally, then the caller must re-connect EFI + drivers. + + @param[in] This The protocol instance pointer. + + @retval EFI_SUCCESS OPROMs were shadowed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This + ); + +/** + Get a region from the LegacyBios for S3 usage. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of required region. + @param[in] Region The region to use. + 00 =3D Either 0xE0000 or 0xF0000 block. + - Bit0 =3D 1 0xF0000 block. + - Bit1 =3D 1 0xE0000 block. + @param[in] Alignment Address alignment. Bit mapped. The fir= st non-zero + bit from right is alignment. + @param[out] LegacyMemoryAddress The Region Assigned + + @retval EFI_SUCCESS The Region was assigned. + @retval EFI_ACCESS_DENIED The function was previously invoked. + @retval Other The Region was not assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN UINTN Region, + IN UINTN Alignment, + OUT VOID **LegacyMemoryAddress + ); + +/** + Get a region from the LegacyBios for Tiano usage. Can only be invoked on= ce. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of data to copy. + @param[in] LegacyMemoryAddress The Legacy Region destination ad= dress. + Note: must be in region assigned= by + LegacyBiosGetLegacyRegion. + @param[in] LegacyMemorySourceAddress The source of the data to copy. + + @retval EFI_SUCCESS The Region assigned. + @retval EFI_ACCESS_DENIED Destination was outside an assigned region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_COPY_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN VOID *LegacyMemoryAddress, + IN VOID *LegacyMemorySourceAddress + ); + +/// +/// Abstracts the traditional BIOS from the rest of EFI. The LegacyBoot() +/// member function allows the BDS to support booting a traditional OS. +/// EFI thunks drivers that make EFI bindings for BIOS INT services use +/// all the other member functions. +/// +struct _EFI_LEGACY_BIOS_PROTOCOL { + /// + /// Performs traditional software INT. See the Int86() function descript= ion. + /// + EFI_LEGACY_BIOS_INT86 Int86; + + /// + /// Performs a far call into Compatibility16 or traditional OpROM code. + /// + EFI_LEGACY_BIOS_FARCALL86 FarCall86; + + /// + /// Checks if a traditional OpROM exists for this device. + /// + EFI_LEGACY_BIOS_CHECK_ROM CheckPciRom; + + /// + /// Loads a traditional OpROM in traditional OpROM address space. + /// + EFI_LEGACY_BIOS_INSTALL_ROM InstallPciRom; + + /// + /// Boots a traditional OS. + /// + EFI_LEGACY_BIOS_BOOT LegacyBoot; + + /// + /// Updates BDA to reflect the current EFI keyboard LED status. + /// + EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS UpdateKeyboardLedStatus; + + /// + /// Allows an external agent, such as BIOS Setup, to get the BBS data. + /// + EFI_LEGACY_BIOS_GET_BBS_INFO GetBbsInfo; + + /// + /// Causes all legacy OpROMs to be shadowed. + /// + EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS ShadowAllLegacyOproms; + + /// + /// Performs all actions prior to boot. Used when booting an EFI-aware OS + /// rather than a legacy OS. + /// + EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI PrepareToBootEfi; + + /// + /// Allows EFI to reserve an area in the 0xE0000 or 0xF0000 block. + /// + EFI_LEGACY_BIOS_GET_LEGACY_REGION GetLegacyRegion; + + /// + /// Allows EFI to copy data to the area specified by GetLegacyRegion. + /// + EFI_LEGACY_BIOS_COPY_LEGACY_REGION CopyLegacyRegion; + + /// + /// Allows the user to boot off an unconventional device such as a PARTI= ES partition. + /// + EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE BootUnconventionalDevice; +}; + +// +// Legacy BIOS needs to access memory in page 0 (0-4095), which is disable= d if +// NULL pointer detection feature is enabled. Following macro can be used = to +// enable/disable page 0 before/after accessing it. +// +#define ACCESS_PAGE0_CODE(statements) \ + do { \ + EFI_STATUS Status_; \ + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc_; \ + \ + Desc_.Attributes =3D 0; \ + Status_ =3D gDS->GetMemorySpaceDescriptor (0, &Desc_); \ + ASSERT_EFI_ERROR (Status_); \ + if ((Desc_.Attributes & EFI_MEMORY_RP) !=3D 0) { \ + Status_ =3D gDS->SetMemorySpaceAttributes ( \ + 0, \ + EFI_PAGES_TO_SIZE(1), \ + Desc_.Attributes & ~(UINT64)EFI_MEMORY_RP \ + ); \ + ASSERT_EFI_ERROR (Status_); \ + } \ + \ + { \ + statements; \ + } \ + \ + if ((Desc_.Attributes & EFI_MEMORY_RP) !=3D 0) { \ + Status_ =3D gDS->SetMemorySpaceAttributes ( \ + 0, \ + EFI_PAGES_TO_SIZE(1), \ + Desc_.Attributes \ + ); \ + ASSERT_EFI_ERROR (Status_); \ + } \ + } while (FALSE) + +extern EFI_GUID gEfiLegacyBiosProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= Platform.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBios= Platform.h new file mode 100644 index 0000000000..b52ad94c3e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/LegacyBiosPlatfor= m.h @@ -0,0 +1,752 @@ +/** @file + The EFI Legacy BIOS Patform Protocol is used to mate a Legacy16 + implementation with this EFI code. The EFI driver that produces + the Legacy BIOS protocol is generic and consumes this protocol. + A driver that matches the Legacy16 produces this protocol + + @copyright + Copyright 2007 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_BIOS_PLATFORM_H_ +#define _EFI_LEGACY_BIOS_PLATFORM_H_ + +/// +/// Legacy BIOS Platform depends on HDD_INFO and EFI_COMPATIBILITY16_TABLE= that +/// are defined with the Legacy BIOS Protocol +/// +#include + +#define EFI_LEGACY_BIOS_PLATFORM_PROTOCOL_GUID \ + { \ + 0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x9, 0x7, 0x9c, 0xc, 0x= b4 } \ + } + +typedef struct _EFI_LEGACY_BIOS_PLATFORM_PROTOCOL EFI_LEGACY_BIOS_PLATFORM= _PROTOCOL; + +/** + This enum specifies the Mode param values for GetPlatformInfo() +**/ +typedef enum { + /// + /// This mode is invoked twice. The first invocation has LegacySegment a= nd + /// LegacyOffset set to 0. The mode returns the MP table address in EFI = memory, along with its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the MP table is to be copie= d. The second + /// invocation allows any MP table address fixes to occur in the EFI mem= ory copy of the + /// MP table. The caller, not EfiGetPlatformBinaryMpTable, copies the mo= dified MP + /// table to the allocated region in 0xF0000 or 0xE0000 block after the = second invocation. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to the MP table. + /// + /// TableSize Size in bytes of the MP table. + /// + /// Location Location to place table. 0x00. Either 0xE0000 or 0xF0000 = 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit-mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + // LegacySegment Segment in which EfiCompatibility code will place th= e MP table. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = MP table. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The MP table was returned. + /// + /// EFI_UNSUPPORTED The MP table is not supported on this platform. + /// + EfiGetPlatformBinaryMpTable =3D 0, + /// + /// This mode returns a block of data. The content and usage is IBV or O= EM defined. + /// OEMs or IBVs normally use this function for nonstandard Compatibilit= y16 runtime soft + /// INTs. It is the responsibility of this routine to coalesce multiple = OEM 16 bit functions, if + /// they exist, into one coherent package that is understandable by the = Compatibility16 code. + /// This function is invoked twice. The first invocation has LegacySegme= nt and + /// LegacyOffset set to 0. The function returns the table address in EFI= memory, as well as its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the data (table) is to be c= opied. The second + /// invocation allows any data (table) address fixes to occur in the EFI= memory copy of + /// the table. The caller, not GetOemIntData(), copies the modified data= (table) to the + /// allocated region in 0xF0000 or 0xE0000 block after the second invoca= tion. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to OEM legacy 16 bit code or data. + /// + /// TableSize Size of data. + /// + /// Location Location to place table. 0x00. Either 0xE0000 or 0xF0000 = 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The data was returned successfully. + /// + /// EFI_UNSUPPORTED Oem INT is not supported on this platform. + /// + EfiGetPlatformBinaryOemIntData =3D 1, + /// + /// This mode returns a block of data. The content and usage is IBV defi= ned. OEMs or + /// IBVs normally use this mode for nonstandard Compatibility16 runtime = 16 bit routines. It + /// is the responsibility of this routine to coalesce multiple OEM 16 bi= t functions, if they + /// exist, into one coherent package that is understandable by the Compa= tibility16 code. + /// + /// Example usage: A legacy mobile BIOS that has a pre-existing runtime + /// interface to return the battery status to calling applications. + /// + /// This mode is invoked twice. The first invocation has LegacySegment a= nd + /// LegacyOffset set to 0. The mode returns the table address in EFI mem= ory and its size. + /// The second invocation has LegacySegment and LegacyOffset set to the = location + /// in the 0xF0000 or 0xE0000 block to which the table is to be copied. = The second + /// invocation allows any table address fixes to occur in the EFI memory= copy of the table. + /// The caller, not EfiGetPlatformBinaryOem16Data, copies the modified t= able to + /// the allocated region in 0xF0000 or 0xE0000 block after the second in= vocation. + /// + /// The function parameters associated with this mode are: + /// + /// Table Pointer to OEM legacy 16 bit code or data. + /// + /// TableSize Size of data. + /// + /// Location Location to place the table. 0x00. Either 0xE0000 or 0xF0= 000 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS The data was returned successfully. + /// + /// EFI_UNSUPPORTED Oem16 is not supported on this platform. + /// + EfiGetPlatformBinaryOem16Data =3D 2, +/// +/// This mode returns a block of data. The content and usage are IBV defin= ed. OEMs or +/// IBVs normally use this mode for nonstandard Compatibility16 runtime 32= bit routines. It +/// is the responsibility of this routine to coalesce multiple OEM 32 bit = functions, if they +/// exist, into one coherent package that is understandable by the Compati= bility16 code. +/// +/// Example usage: A legacy mobile BIOS that has a pre existing runtime +/// interface to return the battery status to calling applications. +/// +/// This mode is invoked twice. The first invocation has LegacySegment and +/// LegacyOffset set to 0. The mode returns the table address in EFI memor= y and its size. +/// +/// The second invocation has LegacySegment and LegacyOffset set to the lo= cation +/// in the 0xF0000 or 0xE0000 block to which the table is to be copied. Th= e second +/// invocation allows any table address fix ups to occur in the EFI memory= copy of the table. +/// The caller, not EfiGetPlatformBinaryOem32Data, copies the modified tab= le to +/// the allocated region in 0xF0000 or 0xE0000 block after the second invo= cation.. +/// +/// Note: There are two generic mechanisms by which this mode can be used. +/// Mechanism 1: This mode returns the data and the Legacy BIOS Protocol c= opies +/// the data into the F0000 or E0000 block in the Compatibility16 code. The +/// EFI_COMPATIBILITY16_TABLE entries Oem32Segment and Oem32Offset can +/// be viewed as two UINT16 entries. +/// Mechanism 2: This mode directly fills in the EFI_COMPATIBILITY16_TABLE= with +/// a pointer to the INT15 E820 region containing the 32 bit code. It retu= rns +/// EFI_UNSUPPORTED. The EFI_COMPATIBILITY16_TABLE entries, +/// Oem32Segment and Oem32Offset, can be viewed as two UINT16 entries or +/// as a single UINT32 entry as determined by the IBV. +/// +/// The function parameters associated with this mode are: +/// +/// TableSize Size of data. +/// +/// Location Location to place the table. 0x00 or 0xE0000 or 0xF0000 64 = KB blocks. +/// Bit 0 =3D 1 0xF0000 64 KB block. +/// Bit 1 =3D 1 0xE0000 64 KB block. +/// Multiple bits can be set. +/// +/// Alignment Bit mapped address alignment granularity. +/// The first nonzero bit from the right is the address granularity. +/// +/// LegacySegment Segment in which EfiCompatibility code will place the = table or data. +/// +/// LegacyOffset Offset in which EfiCompatibility code will place the ta= ble or data. +/// +/// The return values associated with this mode are: +/// EFI_SUCCESS The data was returned successfully. +/// EFI_UNSUPPORTED Oem32 is not supported on this platform. +/// +EfiGetPlatformBinaryOem32Data =3D 3, + /// + /// This mode returns a TPM binary image for the onboard TPM device. + /// + /// The function parameters associated with this mode are: + /// + /// Table TPM binary image for the onboard TPM device. + /// + /// TableSize Size of BinaryImage in bytes. + /// + /// Location Location to place the table. 0x00. Either 0xE0000 or 0xF0= 000 64 KB blocks. + /// Bit 0 =3D 1 0xF0000 64 KB block. + /// Bit 1 =3D 1 0xE0000 64 KB block. + /// Multiple bits can be set. + /// + /// Alignment Bit mapped address alignment granularity. + /// The first nonzero bit from the right is the address granularity. + /// + /// LegacySegment Segment in which EfiCompatibility code will place th= e table or data. + /// + /// LegacyOffset Offset in which EfiCompatibility code will place the = table or data. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS BinaryImage is valid. + /// + /// EFI_UNSUPPORTED Mode is not supported on this platform. + /// + /// EFI_NOT_FOUND No BinaryImage was found. + /// + EfiGetPlatformBinaryTpmBinary =3D 4, + /// + /// The mode finds the Compatibility16 Rom Image. + /// + /// The function parameters associated with this mode are: + /// + /// System ROM image for the platform. + /// + /// TableSize Size of Table in bytes. + /// + /// Location Ignored. + /// + /// Alignment Ignored. + /// + /// LegacySegment Ignored. + /// + /// LegacyOffset Ignored. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS ROM image found. + /// + /// EFI_NOT_FOUND ROM not found. + /// + EfiGetPlatformBinarySystemRom =3D 5, + /// + /// This mode returns the Base address of PciExpress memory mapped confi= guration + /// address space. + /// + /// The function parameters associated with this mode are: + /// + /// Table System ROM image for the platform. + /// + /// TableSize Size of Table in bytes. + /// + /// Location Ignored. + /// + /// Alignment Ignored. + /// + /// LegacySegment Ignored. + /// + /// LegacyOffset Ignored. + /// + /// The return values associated with this mode are: + /// + /// EFI_SUCCESS Address is valid. + /// + /// EFI_UNSUPPORTED System does not PciExpress. + /// + EfiGetPlatformPciExpressBase =3D 6, + /// + EfiGetPlatformPmmSize =3D 7, + /// + EfiGetPlatformEndOpromShadowAddr =3D 8, + /// +} EFI_GET_PLATFORM_INFO_MODE; + +/** + This enum specifies the Mode param values for GetPlatformHandle(). +**/ +typedef enum { + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the VGA + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all VGA handles found. + /// + /// HandleCount Number of VGA handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformVgaHandle =3D 0, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the IDE + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all IDE handles found. + /// + /// HandleCount Number of IDE handles found. + /// + /// AdditionalData Pointer to HddInfo. + /// Information about all onboard IDE controllers. + /// + EfiGetPlatformIdeHandle =3D 1, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the ISA bus + /// controller used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all ISA bus handles found. + /// + /// HandleCount Number of ISA bus handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformIsaBusHandle =3D 2, + /// + /// This mode returns the Compatibility16 policy for the device that sho= uld be the USB + /// device used during a Compatibility16 boot. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0x00. + /// + /// HandleBuffer Buffer of all USB handles found. + /// + /// HandleCount Number of USB bus handles found. + /// + /// AdditionalData NULL. + /// + EfiGetPlatformUsbHandle =3D 3 +} EFI_GET_PLATFORM_HANDLE_MODE; + +/** + This enum specifies the Mode param values for PlatformHooks(). + Note: Any OEM defined hooks start with 0x8000. +**/ +typedef enum { + /// + /// This mode allows any preprocessing before scanning OpROMs. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle Handle of device OpROM is associated with. + /// + /// ShadowAddress Address where OpROM is shadowed. + /// + /// Compatibility16Table NULL. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookPrepareToScanRom =3D 0, + /// + /// This mode shadows legacy OpROMS that may not have a physical device = associated with + /// them. It returns EFI_SUCCESS if the ROM was shadowed. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle 0. + /// + /// ShadowAddress First free OpROM area, after other OpROMs have bee= n dispatched.. + /// + /// Compatibility16Table Pointer to the Compatability16 Table. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookShadowServiceRoms=3D 1, + /// + /// This mode allows platform to perform any required operation after an= OpROM has + /// completed its initialization. + /// + /// The function parameters associated with this mode are: + /// + /// Type 0. + /// + /// DeviceHandle Handle of device OpROM is associated with. + /// + /// ShadowAddress Address where OpROM is shadowed. + /// + /// Compatibility16Table NULL. + /// + /// AdditionalData NULL. + /// + EfiPlatformHookAfterRomInit =3D 2 +} EFI_GET_PLATFORM_HOOK_MODE; + +/// +/// This IRQ has not been assigned to PCI. +/// +#define PCI_UNUSED 0x00 +/// +/// This IRQ has been assigned to PCI. +/// +#define PCI_USED 0xFF +/// +/// This IRQ has been used by an SIO legacy device and cannot be used by P= CI. +/// +#define LEGACY_USED 0xFE + +#pragma pack(1) + +typedef struct { + /// + /// IRQ for this entry. + /// + UINT8 Irq; + /// + /// Status of this IRQ. + /// + /// PCI_UNUSED 0x00. This IRQ has not been assigned to PCI. + /// + /// PCI_USED 0xFF. This IRQ has been assigned to PCI. + /// + /// LEGACY_USED 0xFE. This IRQ has been used by an SIO legacy + /// device and cannot be used by PCI. + /// + UINT8 Used; +} EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY; + +// +// Define PIR table structures +// +#define EFI_LEGACY_PIRQ_TABLE_SIGNATURE SIGNATURE_32 ('$', 'P', 'I', 'R') + +typedef struct { + /// + /// $PIR. + /// + UINT32 Signature; + /// + /// 0x00. + /// + UINT8 MinorVersion; + /// + /// 0x01 for table version 1.0. + /// + UINT8 MajorVersion; + /// + /// 0x20 + RoutingTableEntries * 0x10. + /// + UINT16 TableSize; + /// + /// PCI interrupt router bus. + /// + UINT8 Bus; + /// + /// PCI interrupt router device/function. + /// + UINT8 DevFun; + /// + /// If nonzero, bit map of IRQs reserved for PCI. + /// + UINT16 PciOnlyIrq; + /// + /// Vendor ID of a compatible PCI interrupt router. + /// + UINT16 CompatibleVid; + /// + /// Device ID of a compatible PCI interrupt router. + /// + UINT16 CompatibleDid; + /// + /// If nonzero, a value passed directly to the IRQ miniport's Initialize= function. + /// + UINT32 Miniport; + /// + /// Reserved for future usage. + /// + UINT8 Reserved[11]; + /// + /// This byte plus the sum of all other bytes in the LocalPirqTable equa= l 0x00. + /// + UINT8 Checksum; +} EFI_LEGACY_PIRQ_TABLE_HEADER; + + +typedef struct { + /// + /// If nonzero, a value assigned by the IBV. + /// + UINT8 Pirq; + /// + /// If nonzero, the IRQs that can be assigned to this device. + /// + UINT16 IrqMask; +} EFI_LEGACY_PIRQ_ENTRY; + +typedef struct { + /// + /// PCI bus of the entry. + /// + UINT8 Bus; + /// + /// PCI device of this entry. + /// + UINT8 Device; + /// + /// An IBV value and IRQ mask for PIRQ pins A through D. + /// + EFI_LEGACY_PIRQ_ENTRY PirqEntry[4]; + /// + /// If nonzero, the slot number assigned by the board manufacturer. + /// + UINT8 Slot; + /// + /// Reserved for future use. + /// + UINT8 Reserved; +} EFI_LEGACY_IRQ_ROUTING_ENTRY; + +#pragma pack() + + +/** + Finds the binary data or other platform information. + + @param This The protocol instance pointer. + @param Mode Specifies what data to return. See See EFI= _GET_PLATFORM_INFO_MODE enum. + @param Table Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param TableSize Mode specific. See EFI_GET_PLATFORM_INFO= _MODE enum. + @param Location Mode specific. See EFI_GET_PLATFORM_INFO= _MODE enum. + @param Alignment Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param LegacySegment Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + @param LegacyOffset Mode specific. See EFI_GET_PLATFORM_INFO_= MODE enum. + + @retval EFI_SUCCESS Data returned successfully. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + @retval EFI_NOT_FOUND Binary image or table not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_INFO)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_INFO_MODE Mode, + OUT VOID **Table, + OUT UINTN *TableSize, + OUT UINTN *Location, + OUT UINTN *Alignment, + IN UINT16 LegacySegment, + IN UINT16 LegacyOffset + ); + +/** + Returns a buffer of handles for the requested subfunction. + + @param This The protocol instance pointer. + @param Mode Specifies what handle to return. See EFI_G= ET_PLATFORM_HANDLE_MODE enum. + @param Type Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param HandleBuffer Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param HandleCount Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + @param AdditionalData Mode specific. See EFI_GET_PLATFORM_HANDLE= _MODE enum. + + @retval EFI_SUCCESS Handle is valid. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + @retval EFI_NOT_FOUND Handle is not known. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_HANDLE)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_HANDLE_MODE Mode, + IN UINT16 Type, + OUT EFI_HANDLE **HandleBuffer, + OUT UINTN *HandleCount, + IN VOID **AdditionalData OPTIONAL + ); + +/** + Load and initialize the Legacy BIOS SMM handler. + + @param This The protocol instance pointer. + @param EfiToLegacy16BootTable A pointer to Legacy16 boot table. + + @retval EFI_SUCCESS SMM code loaded. + @retval EFI_DEVICE_ERROR SMM code failed to load + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_SMM_INIT)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN VOID *EfiToLegacy16BootTable + ); + +/** + Allows platform to perform any required action after a LegacyBios operat= ion. + Invokes the specific sub function specified by Mode. + + @param This The protocol instance pointer. + @param Mode Specifies what handle to return. See EFI_G= ET_PLATFORM_HOOK_MODE enum. + @param Type Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param DeviceHandle Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param ShadowAddress Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param Compatibility16Table Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + @param AdditionalData Mode specific. See EFI_GET_PLATFORM_HOOK_= MODE enum. + + @retval EFI_SUCCESS The operation performed successfully. Mode= specific. + @retval EFI_UNSUPPORTED Mode is not supported on the platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_HOOKS)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN EFI_GET_PLATFORM_HOOK_MODE Mode, + IN UINT16 Type, + IN EFI_HANDLE DeviceHandle, OPTIONAL + IN OUT UINTN *ShadowAddress, OPTIONAL + IN EFI_COMPATIBILITY16_TABLE *Compatibility16Table, OPTIONAL + OUT VOID **AdditionalData OPTIONAL + ); + +/** + Returns information associated with PCI IRQ routing. + This function returns the following information associated with PCI IRQ = routing: + * An IRQ routing table and number of entries in the table. + * The $PIR table and its size. + * A list of PCI IRQs and the priority order to assign them. + + @param This The protocol instance pointer. + @param RoutingTable The pointer to PCI IRQ Routing table. + This location is the $PIR table minus th= e header. + @param RoutingTableEntries The number of entries in table. + @param LocalPirqTable $PIR table. + @param PirqTableSize $PIR table size. + @param LocalIrqPriorityTable A list of interrupts in priority order t= o assign. + @param IrqPriorityTableEntries The number of entries in the priority ta= ble. + + @retval EFI_SUCCESS Data was successfully returned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_GET_ROUTING_TABLE)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + OUT VOID **RoutingTable, + OUT UINTN *RoutingTableEntries, + OUT VOID **LocalPirqTable, OPTIONAL + OUT UINTN *PirqTableSize, OPTIONAL + OUT VOID **LocalIrqPriorityTable, OPTIONAL + OUT UINTN *IrqPriorityTableEntries OPTIONAL + ); + +/** + Translates the given PIRQ accounting for bridge. + This function translates the given PIRQ back through all buses, if requi= red, + and returns the true PIRQ and associated IRQ. + + @param This The protocol instance pointer. + @param PciBus The PCI bus number for this device. + @param PciDevice The PCI device number for this device. + @param PciFunction The PCI function number for this device. + @param Pirq Input is PIRQ reported by device, and outp= ut is true PIRQ. + @param PciIrq The IRQ already assigned to the PIRQ, or t= he IRQ to be + assigned to the PIRQ. + + @retval EFI_SUCCESS The PIRQ was translated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_TRANSLATE_PIRQ)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN UINTN PciBus, + IN UINTN PciDevice, + IN UINTN PciFunction, + IN OUT UINT8 *Pirq, + OUT UINT8 *PciIrq + ); + +/** + Attempt to legacy boot the BootOption. If the EFI contexted has been + compromised this function will not return. + + @param This The protocol instance pointer. + @param BbsDevicePath The EFI Device Path from BootXXXX variabl= e. + @param BbsTable The Internal BBS table. + @param LoadOptionSize The size of LoadOption in size. + @param LoadOption The LoadOption from BootXXXX variable + @param EfiToLegacy16BootTable A pointer to BootTable structure + + @retval EFI_SUCCESS Ready to boot. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PLATFORM_PREPARE_TO_BOOT)( + IN EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *This, + IN BBS_BBS_DEVICE_PATH *BbsDevicePath, + IN VOID *BbsTable, + IN UINT32 LoadOptionsSize, + IN VOID *LoadOptions, + IN VOID *EfiToLegacy16BootTable + ); + +/** + This protocol abstracts the platform portion of the traditional BIOS. +**/ +struct _EFI_LEGACY_BIOS_PLATFORM_PROTOCOL { + /// + /// Gets binary data or other platform information. + /// + EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_INFO GetPlatformInfo; + /// + /// Returns a buffer of all handles matching the requested subfunction. + /// + EFI_LEGACY_BIOS_PLATFORM_GET_PLATFORM_HANDLE GetPlatformHandle; + /// + /// Loads and initializes the traditional BIOS SMM handler. + EFI_LEGACY_BIOS_PLATFORM_SMM_INIT SmmInit; + /// + /// Allows platform to perform any required actions after a LegacyBios = operation. + /// + EFI_LEGACY_BIOS_PLATFORM_HOOKS PlatformHooks; + /// + /// Gets $PIR table. + EFI_LEGACY_BIOS_PLATFORM_GET_ROUTING_TABLE GetRoutingTable; + /// + /// Translates the given PIRQ to the final value after traversing any P= CI bridges. + /// + EFI_LEGACY_BIOS_PLATFORM_TRANSLATE_PIRQ TranslatePirq; + /// + /// Final platform function before the system attempts to boot to a tra= ditional OS. + /// + EFI_LEGACY_BIOS_PLATFORM_PREPARE_TO_BOOT PrepareToBoot; +}; + +extern EFI_GUID gEfiLegacyBiosPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlat= form.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlatform= .h new file mode 100644 index 0000000000..77423481ce --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h @@ -0,0 +1,72 @@ +/** @file + This file declares PCI IOV platform protocols. + + @copyright + Copyright 2005 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_IOV_PLATFORM_H_ +#define _PCI_IOV_PLATFORM_H_ + + +// +// Protocol for GUID. +// + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL EFI_PCI_IOV_PLATFORM_PROTOCO= L; + +typedef UINT32 EFI_PCI_IOV_PLATFORM_POLICY; + +#define EFI_PCI_IOV_POLICY_ARI 0x0001 +#define EFI_PCI_IOV_POLICY_SRIOV 0x0002 +#define EFI_PCI_IOV_POLICY_MRIOV 0x0004 + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +/** + + The GetPlatformPolicy() function retrieves the platform policy regardi= ng PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +; + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL { + EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE GetSystemLowes= tPageSize; + EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY GetPlatformPol= icy; +} EFI_PCI_IOV_PLATFORM_PROTOCOL; + +extern EFI_GUID gEfiPciIovPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformTy= pe.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformType.h new file mode 100644 index 0000000000..6fdfea0fde --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/PlatformType.h @@ -0,0 +1,48 @@ +/** @file + This file defines platform policies for Platform Type. + + @copyright + Copyright 1996 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_TYPE_H_ +#define _PLATFORM_TYPE_H_ + +#include + +typedef struct _EFI_PLATFORM_TYPE_PROTOCOL { + UINT8 SystemUuid[16]; // 16 bytes + UINT32 Signature; // "$PIT" 0x54495024 + UINT32 Size; // Size of the table + UINT16 Revision; // Revision of the table + UINT16 Type; // Platform Type + UINT32 CpuType; // Cpu Type + UINT8 CpuStepping; // Cpu Stepping + UINT32 TypeRevisionId; // Board Revision ID + UINT16 IioSku; + UINT16 IioRevision; + UINT16 PchSku; + UINT16 PchRevision; + UINT16 PchType; // Retrive PCH SKU type = installed + BOOLEAN ExtendedInfoValid; // If TRUE then below fi= elds are Valid + UINT8 Checksum; // Checksum minus System= Uuid is valid in DXE only. + UINT64 TypeStringPtr; + UINT64 IioStringPtr; + UINT64 PchStringPtr; + EFI_PLATFORM_PCI_DATA PciData; + EFI_PLATFORM_CPU_DATA CpuData; + EFI_PLATFORM_MEM_DATA MemData; + EFI_PLATFORM_SYS_DATA SysData; + EFI_PLATFORM_PCH_DATA PchData; + UINT8 IioRiserId; + UINT8 BoardId; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 Emulation; // 100b =3D Simics +} EFI_PLATFORM_TYPE_PROTOCOL; + +extern EFI_GUID gEfiPlatformTypeProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h= b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h new file mode 100644 index 0000000000..658188e467 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaCfgDb.h @@ -0,0 +1,114 @@ +/** @file + uba central config database Protocol + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_H_ +#define _UBA_CONFIG_DATABASE_H_ + +// {E03E0D46-5263-4845-B0A4-58D57B3177E2} +#define UBA_CONFIG_DATABASE_PROTOCOL_GUID \ + { 0xe03e0d46, 0x5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77= , 0xe2 } } + + +typedef struct _UBA_CONFIG_DATABASE_PROTOCOL UBA_CONFIG_DATABASE_PROTOCOL; + +#define UBA_CONFIG_PROTOCOL_SIGNATURE SIGNATURE_32('M', 'S', 'K', 'P') +#define UBA_CONFIG_PROTOCOL_VERSION 0x01 + +/** + Get platform's GUID and user friendly name by PlatformType. + + This is used when you need a PlatformId to Add/Get platform data + + Core will create a new platform for you if the PlatformType is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Protocol instance. + @param PlatformType The platform type, same define as Platform= .h. + @param PlatformId The GUID for this platform. + @param PlatformName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_GET_PLATFORM) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + OUT UINT32 *PlatformType, + OUT EFI_GUID *PlatformId, + OUT CHAR8 *PlatformName + ); + +/** + Add configuration data to uba configuration database. + + @param This uba Protocol instance. + @param PlatformId The GUID for this platform. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_ADD_DATA) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get configuration data from uba configuration database. + + @param This uba Protocol instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. + +**/ +typedef +EFI_STATUS +(EFIAPI *UBA_CONFIG_GET_DATA) ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + OUT UINTN *DataSize + ); + + +// +// UbaConfigDatabaseProtocol +// +struct _UBA_CONFIG_DATABASE_PROTOCOL { + UINT32 Signature; + UINT32 Version; + + UBA_CONFIG_GET_PLATFORM GetSku; + UBA_CONFIG_ADD_DATA AddData; + UBA_CONFIG_GET_DATA GetData; +}; + +extern EFI_GUID gUbaConfigDatabaseProtocolGuid; + +#endif // __UBA_CONFIG_DATABASE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevsUpd= ateProtocol.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevs= UpdateProtocol.h new file mode 100644 index 0000000000..ee7fabc719 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaDevsUpdateProt= ocol.h @@ -0,0 +1,86 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLT_DEVS_UPDATE_H_ +#define _PLT_DEVS_UPDATE_H_ + +// {1E22C6FA-B39E-419a-A071-D60B672B21C8} +#define EFI_PLT_DEVS_UPDATE_GUID \ + { \ + 0x1e22c6fa, 0xb39e, 0x419a, { 0xa0, 0x71, 0xd6, 0xb, 0x67, 0x2b, 0x21, = 0xc8 }\ + } + +#define PORTNUMMAX 8 + +typedef struct _EFI_PLT_DEVS_UPDATE_PROTOCOL EFI_PLT_DEVS_UPDATE_PROTOCOL; + +typedef enum { + NET_PXE_1GB =3D 0, + NET_PXE_10GB =3D 1, + NET_ISCSI =3D 2, + NET_FCOE =3D 3, + NET_INFINITBADN =3D 4 +} OPROM_FILE_TYPE; + +typedef enum { + HIDDEN =3D 0, + ONBOARD_NIC =3D 1, + IO_MODULE_NIC =3D 2, +} NIC_TYPE; + +typedef enum { + UNDEF =3D 0, + ETHERNET =3D 1, + INFIBAND =3D 2 +} NIC_SUB_TYPE; + +#define DFT_MAC_SIZE 0x20 +#define DFT_GUID_SIZE 0x64 + +#define PXE1GBit 0x1 +#define PXE10GBit 0x2 +#define FcoeBit 0x4 +#define iSCSIBit 0x8 + +#pragma pack(1) +typedef struct _PLAT_NIC_SETUP_INFO{ + NIC_TYPE NicType; //Onboard or IO module + NIC_SUB_TYPE NicSubType; //Ethernect or Infinitband c= ontroller + UINT8 NicIndex; //Onboard Nic1,2,3 or IOM 1,= 2,3 per setup option + UINT8 RootPortBusNo; //Root Bridge Bus No + UINT8 RootPortDevNo; //Root Bridge device No + UINT8 RootPortFunNo; //Root Bridge Function No + UINT16 NicVID; //Nic Vendor ID + UINT16 NicDID; //Nic Device ID + UINT16 SubDID; //Nic Subsystem ID + UINT8 PortNumbers; //Ports numbder after detect= ion + CHAR8 NicDescription[64]; //Nic description defined in= Eps + EFI_MAC_ADDRESS PortMacAddress[PORTNUMMAX]; + EFI_GUID InfinitbandGuid; + UINT8 OpROMCapMap; + UINT8 IsPchNIC; +}PLAT_NIC_SETUP_INFO; +#pragma pack() + +typedef EFI_STATUS (*PLATFORM_HKS_GET_EMBEDED_OPTIONROM) (IN EFI_PLT_DEVS_= UPDATE_PROTOCOL *This, IN EFI_HANDLE PciHandle,OPROM_FILE_TYPE OpRomType); +typedef EFI_STATUS (*PLATFORM_HKS_DISPATCH_OPTIONROM) (IN EFI_PLT_DEVS_UPD= ATE_PROTOCOL *This, IN EFI_HANDLE PciHandle); +typedef EFI_STATUS (*PLATFORM_HKS_BDS_UPDATE_MAC) (IN EFI_PLT_DEVS_UPDATE_= PROTOCOL *This); +typedef EFI_STATUS (*PLATFORM_HKS_ON_ENTER_SETUP) (IN EFI_PLT_DEVS_UPDATE_= PROTOCOL *This, OUT PLAT_NIC_SETUP_INFO **NicInfo, OUT UINT8 *NicNum); + +typedef struct _EFI_PLT_DEVS_UPDATE_PROTOCOL { + PLATFORM_HKS_GET_EMBEDED_OPTIONROM PlatformHooksOnGettingEmbed= OpRom; + PLATFORM_HKS_DISPATCH_OPTIONROM PlatformHooksOnDispatchOpRo= m; + PLATFORM_HKS_BDS_UPDATE_MAC PlatformHooksBdsUpdateMac; + PLATFORM_HKS_ON_ENTER_SETUP PlatformHooksGetNicInfo; +} EFI_PLT_DEVS_UPDATE_PROTOCOL; + +extern EFI_GUID gEfiPlatformDevsUpdateProtocolGuid; +extern EFI_GUID gEfiVMDDriverProtocolGuid; +extern EFI_GUID gEfiHfiPcieGen3ProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerPr= otocol.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerProt= ocol.h new file mode 100644 index 0000000000..31ad158860 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/UbaMakerProtocol.h @@ -0,0 +1,22 @@ +/** @file + GUID variable for multi-boards support in DXE phase. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __UBA_MAKER_PROTOCOL_H__ +#define __UBA_MAKER_PROTOCOL_H__ + + +extern EFI_GUID gEfiPlatformTypeNeonCityEPRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeHedtCRBProtocolGuid; +extern EFI_GUID gEfiPlatformTypeLightningRidgeEXRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid; +extern EFI_GUID gEfiPlatformTypeWilsonCityRPProtocolGuid; +extern EFI_GUID gEfiPlatformTypeWilsonCityModularProtocolGuid; +extern EFI_GUID gEfiPlatformTypeIsoscelesPeakProtocolGuid; + +#endif // #ifndef __UBA_MAKER_PROTOCOL_H__ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h b/Plat= form/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h new file mode 100644 index 0000000000..c3a8e931d5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SetupTable.h @@ -0,0 +1,25 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SETUP_TABLE_H_ +#define _SETUP_TABLE_H_ +#include +#include + +#include +#include +#include + +typedef struct { + SOCKET_CONFIGURATION SocketConfig; + SYSTEM_CONFIGURATION SystemConfig; + PCH_SETUP PchSetup; + MEM_BOOT_HEALTH_CONFIG MemBootHealthConfig; +} SETUP_DATA; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h b/Platfor= m/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..6f848d536d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,251 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +typedef struct { + UINT8 Index; + UINT8 Value; +} SIO_INDEX_DATA; + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +// +// COM (Serial) Port Base address +// +#define SIO_BASE_COM1 0x3F8 +#define SIO_BASE_COM2 0x2F8 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define PRIMARY_INTERRUPT_SELECT 0x70 +#define INTERRUPT_TYPE 0x71 + +// +//ASPEED AST2500 register +// +#define ASPEED2500_SIO_INDEX_PORT 0x2E +#define ASPEED2500_SIO_DATA_PORT (ASPEED2500_SIO_INDEX_PORT+1) + +#define ASPEED2500_SIO_UART1 0x02 +#define ASPEED2500_SIO_UART2 0x03 +#define ASPEED2500_SIO_SMI 0x0D +#define ASPEED2500_SIO_MAILBOX 0x0E + +#define SCU7C 0x1e6e207c + +#define ASPEED2500_SIO_UNLOCK 0xA5 +#define ASPEED2500_SIO_LOCK 0xAA + +// +// Port address for PILOT-IV +// +#define PILOTIV_CHIP_ID 0x03 +#define PILOTIV_SIO_INDEX_PORT 0x2E +#define PILOTIV_SIO_DATA_PORT (PILOTIV_SIO_INDEX_PORT+1) + +#define PILOTIV_SIO_UNLOCK 0x5A +#define PILOTIV_SIO_LOCK 0xA5 +#define PILOTIV_UNLOCK 0x5A +#define PILOTIV_LOCK 0xA5 + +#define PILOTIV_SIO_PSR 0x00 +#define PILOTIV_SIO_COM2 0x01 +#define PILOTIV_SIO_COM1 0x02 +#define PILOTIV_SIO_SWCP 0x03 +#define PILOTIV_SIO_GPIO 0x04 +#define PILOTIV_SIO_WDT 0x05 + +#define PILOTIV_SIO_KCS3 0x08 +#define PILOTIV_SIO_KCS4 0x09 +#define PILOTIV_SIO_KCS5 0x0A +#define PILOTIV_SIO_BT 0x0B +#define PILOTIV_SIO_SMIC 0x0C +#define PILOTIV_SIO_MAILBOX 0x0D +#define PILOTIV_SIO_RTC 0x0E +#define PILOTIV_SIO_SPI 0x0F +#define PILOTIV_SIO_TAP 0x10 + +// +// Register for Pilot IV +// +#define PILOTIV_CHIP_ID_REG 0x20 +#define PILOTIV_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PILOTIV_ACTIVATE ACTIVATE +#define PILOTIV_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PILOTIV_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PILOTIV_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1 +#define PILOTIV_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1 +#define PILOTIV_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT + + +// +// Port address for PC8374 +// +#define PC8374_CHIP_ID 0xF1 +#define PC8374_SIO_INDEX_PORT 0x02E +#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1) + +// +// Logical device in PC8374 +// +#define PC8374_SIO_FLOPPY 0x00 +#define PC8374_SIO_PARA 0x01 +#define PC8374_SIO_COM2 0x02 +#define PC8374_SIO_COM1 0x03 +#define PC8374_SIO_MOUSE 0x05 +#define PC8374_SIO_KYBD 0x06 +#define PC8374_SIO_GPIO 0x07 + +// +// Registers specific for PC8374 +// +#define PC8374_CLOCK_SELECT 0x2D +#define PC8374_CLOCK_CONFIG 0x29 + +// +// Registers for PC8374 +// +#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PC8374_ACTIVATE ACTIVATE +#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT +#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0 +#define PC8374_CHIP_ID_REG 0x20 + +#define PC87427_SERVERIO_CNF2 0x22 + + + +// +// Port address for NCT5104D +// +#define NCT5104D_SIO_INDEX_PORT 0x4E +#define NCT5104D_SIO_DATA_PORT (NCT5104D_SIO_INDEX_PORT+1) + +// +// Registers for NCT5104D +// +#define NCT5104D_CHIP_ID_REG 0x20 +#define NCT5104D_CHIP_ID 0xC4 +#define NCT5104D_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define NCT5104D_ACTIVATE ACTIVATE +#define NCT5104D_SIO_UARTA 2 +#define NCT5104D_SIO_COM1 3 +#define NCT5104D_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define NCT5104D_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define NCT5104D_WAKEUP_ON_IRQ_EN 0x70 +#define NCT5104D_ENTER_THE_EXTENDED_FUNCTION_MODE 0x87 +#define NCT5104D_EXIT_THE_EXTENDED_FUNCTION_MODE 0xAA +// +// Port address for W83527 +// +#define W83527_SIO_INDEX_PORT 0x02E +#define W83527_SIO_DATA_PORT (W83527_SIO_INDEX_PORT+1) + +// +// Logical device in W83527 +// +#define W83527_SIO_KYBD 0x05 +#define W83527_SIO_WDTO 0x08 +#define W83527_SIO_GPIO 0x09 +#define W83527_SIO_ACPI 0x0A +#define W83527_SIO_HWM 0x0B +#define W83527_SIO_PCEI 0x0C + +// +// Registers for W83527 +// +#define W83527_EXT_MODE_START 0x87 +#define W83527_EXT_MODE_STOP 0xAA +#define W83527_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define W83527_ACTIVATE_REG 0x30 +#define W83527_ACTIVATE ACTIVATE +#define W83527_CHIP_ID_REG 0x20 +#define W83527_CHIP_ID 0xB0 +#define W83527_CLOCK_REG 0x24 +#define W83527_KBC_BASE1_HI_ADDR_REG 0x60 +#define W83527_KBC_BASE1_LO_ADDR_REG 0x61 +#define W83527_KBC_BASE2_HI_ADDR_REG 0x62 +#define W83527_KBC_BASE2_LO_ADDR_REG 0x63 +#define W83527_KBC_BASE1_HI_ADDR 0x00 +#define W83527_KBC_BASE1_LO_ADDR 0x60 +#define W83527_KBC_BASE2_HI_ADDR 0x00 +#define W83527_KBC_BASE2_LO_ADDR 0x64 +#define W83527_KBC_KB_IRQ_REG 0x70 +#define W83527_KBC_KB_IRQ 0x01 +#define W83527_KBC_MS_IRQ_REG 0x72 +#define W83527_KBC_MS_IRQ 0x0C +#define W83527_KBC_CFG_REG 0xF0 +#define W83527_KBC_CFG 0x83 +#define W83527_KBC_CLOCK 0x01 +#define W83527_EXT_MODE_START 0x87 +#define W83527_EXT_MODE_END 0xAA + + +// +// Select Clock for W83527, 0 / 1 for 24MHz / 48MHz +// +#define W83527_CLOCK_BIT 0x06 +#define W83527_CLOCK 0x01 + +// +// Initialize Key Board Controller +// +#define W83527_KeyBoard 1 + + +// +// Pilot II Mailbox Data Register definitions +// +#define MBDAT00_OFFSET 0x00 +#define MBDAT01_OFFSET 0x01 +#define MBDAT02_OFFSET 0x02 +#define MBDAT03_OFFSET 0x03 +#define MBDAT04_OFFSET 0x04 +#define MBDAT05_OFFSET 0x05 +#define MBDAT06_OFFSET 0x06 +#define MBDAT07_OFFSET 0x07 +#define MBDAT08_OFFSET 0x08 +#define MBDAT09_OFFSET 0x09 +#define MBDAT10_OFFSET 0x0A +#define MBDAT11_OFFSET 0x0B +#define MBDAT12_OFFSET 0x0C +#define MBDAT13_OFFSET 0x0D +#define MBDAT14_OFFSET 0x0E +#define MBDAT15_OFFSET 0x0F +#define MBST0_OFFSET 0x10 +#define MBST1_OFFSET 0x11 + +// +// If both are there, use the default one +// + +#define ASPEED_EXIST BIT4 +#define NCT5104D_EXIST BIT3 +#define W83527_EXIST BIT2 +#define PC8374_EXIST BIT1 +#define PILOTIV_EXIST BIT0 +#define DEFAULT_SIO PILOTIV_EXIST +#define DEFAULT_KDB PC8374_EXIST + +#define IPMI_DEFAULT_SMM_IO_BASE 0xca2 +#define PILOTIV_SWC_BASE_ADDRESS 0xA00 +#define PILOTIV_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80 +#define PILOTIV_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84 +#define PILOTIV_GPE1_BLK_BASE_ADDRESS 0x0A86 +#define PILOTIV_KCS3_DATA_BASE_ADDRESS 0x0CA4 +#define PILOTIV_KCS3_CMD_BASE_ADDRESS 0x0CA5 +#define PILOTIV_KCS4_DATA_BASE_ADDRESS 0x0CA2 +#define PILOTIV_KCS4_CMD_BASE_ADDRESS 0x0CA3 +#define PILOTIV_MAILBOX_BASE_ADDRESS 0x0600 +#define PILOTIV_MAILBOX_MASK 0xFFE0 +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h b/Pla= tform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h new file mode 100644 index 0000000000..fda7ccf523 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/SystemBoard.h @@ -0,0 +1,75 @@ +/** @file + This protocol is EFI compatible. + + @copyright + Copyright 2005 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SYSTEM_BOARD_H_ +#define _DXE_SYSTEM_BOARD_H_ + +#include +#include +#include + +#define PCI_DEVICE_NUMBER_IMC0_CH_0 0x08 +#define PCI_FUNCTION_NUMBER_IMC0_CH_0 0 +#define PCI_DEVICE_ID_IMC0_CH_0 0x2014 +#define BIOSGUARD_SUPPORT_ENABLED BIT0 +#define OC_SUPPORT_ENABLED BIT1 + +#ifndef __AML_OFFSET_TABLE_H +#define __AML_OFFSET_TABLE_H + +typedef struct { + char *Pathname; /* Full pathname (from root) to= the object */ + unsigned short ParentOpcode; /* AML opcode for the parent ob= ject */ + unsigned long NamesegOffset; /* Offset of last nameseg in th= e parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (= as applicable) */ +} AML_OFFSET_TABLE_ENTRY; +#endif + +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ + { \ + 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00 } \ + } + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + +// +// System board information table +// +typedef struct { + // + // Pci option ROM data + // + PCI_OPTION_ROM_TABLE *PciOptionRomTable; + + // + // System CPU data + // + UINT32 CpuSocketCount; + + // + // System device and irq routing data + // + DEVICE_DATA *DeviceData; + PLATFORM_PIRQ_DATA *SystemPirqData; +} DXE_SYSTEM_BOARD_INFO; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h b/Platform= /Intel/WhitleyOpenBoardPkg/Include/UbaKti.h new file mode 100644 index 0000000000..c7802d6451 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/UbaKti.h @@ -0,0 +1,29 @@ +/** @file + UBA KTI header file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +#ifndef _UBA_KTI_H_ +#define _UBA_KTI_H_ + +#define PLATFORM_KTIEP_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'K', 'T', 'I') +#define PLATFORM_KTIEP_UPDATE_VERSION 01 + +typedef struct _PLATFORM_KTI_EPARAM_UPDATE_TABLE { + UINT32 Signature; + UINT32 Version; + ALL_LANES_EPARAM_LINK_INFO *AllLanesEparamTablePtr; + UINT32 SizeOfAllLanesEparamTable; + PER_LANE_EPARAM_LINK_INFO *PerLaneEparamTablePtr; + UINT32 SizeOfPerLaneEparamTable; +} PLATFORM_KTI_EPARAM_UPDATE_TABLE; +#endif //_UBA_KTI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/= DxeBoardAcpiTableLib.c new file mode 100644 index 0000000000..dfa0c994dc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.c @@ -0,0 +1,37 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + MtOlympusBoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLi= b/DxeBoardAcpiTableLib.inf new file mode 100644 index 0000000000..3186c6c91e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.inf @@ -0,0 +1,44 @@ +### @file +# Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxeBoardAcpiTableLib + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiTableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + PcdLib +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeMtOlympusAcpiTableLib.c + DxeBoardAcpiTableLib.c + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeMtO= lympusAcpiTableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpi= Lib/DxeMtOlympusAcpiTableLib.c new file mode 100644 index 0000000000..09b917083c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/DxeMtOlympusA= cpiTableLib.c @@ -0,0 +1,54 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM *mGlobalNvsArea; + +VOID +MtOlympusUpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + +} + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) { + MtOlympusUpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoa= rdAcpiEnableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..09a6b00877 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.c @@ -0,0 +1,51 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoa= rdAcpiEnableLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiL= ib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..fcbc94cc50 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.inf @@ -0,0 +1,48 @@ +### @file +# Platform Hook Library instance +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmBoardAcpiEnableLib + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + UefiBootServicesTableLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + +[Protocols] + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmSil= iconAcpiEnableLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiL= ib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..2b8a35c7e8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardAcpiLib/SmmSiliconAcp= iEnableLib.c @@ -0,0 +1,138 @@ +/** @file + Platform Hook Library instances + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 SmiEn; + UINT16 Pm1En; + UINT16 Pm1Cnt; + UINT16 PchPmBase; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Init Power Management I/O Base aka ACPI Base + // + PchPmBase =3D DynamicSiLibraryProtocol->PmcGetAcpiBase (); + + SmiEn =3D IoRead32 (PchPmBase + R_ACPI_IO_SMI_EN); + + // + // Disable SW SMI Timer and legacy USB + // + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB | = B_ACPI_IO_SMI_EN_LEGACY_USB2); + + // + // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when SLP_TYP is = written + // + SmiEn |=3D B_ACPI_IO_SMI_EN_ON_SLP_EN ; + IoWrite32 (PchPmBase + R_ACPI_IO_SMI_EN, SmiEn); + + // + // Disable PM sources except power button + // + Pm1En =3D B_ACPI_IO_PM1_EN_PWRBTN; + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_EN, Pm1En); + + // + // Enable SCI + // + Pm1Cnt =3D IoRead16 (PchPmBase + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 Pm1Cnt; + UINT16 PchPmBase; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Init Power Management I/O Base aka ACPI Base + // + PchPmBase =3D DynamicSiLibraryProtocol->PmcGetAcpiBase (); + + Pm1Cnt =3D IoRead16 (PchPmBase + R_ACPI_IO_PM1_CNT); + + // + // Disable SCI + // + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN; + + IoWrite16 (PchPmBase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Board= InitDxeLib.c new file mode 100644 index 0000000000..d31c9292a6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.c @@ -0,0 +1,299 @@ +/** @file +Library for Board Init. + +@copyright +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +IIO_UDS *mIioUds; + +/** + Connects Root Bridge +**/ +VOID +ConnectRootBridge ( + BOOLEAN Recursive + ); + + +VOID +ProgramDPRregs ( + VOID +); + +/** + A hook for board-specific initialization after PCI enumeration. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterPciEnumeration ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ReadyToBoot event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitReadyToBoot ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ExitBootServices event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitEndOfFirmware ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + This function will retrieve the DPR data from HOBs produced by MRC + and will use it to program the DPR registers in IIO and in PCH + + @param VOID + @retval VOID + +**/ +VOID +ProgramDprRegs ( + VOID + ) +{ + return; +} + +/** + Function to set the WPE bit of the BIOS Info Flags MSR to enable Anti-Fl= ash wearout + protection within BIOS Guard before booting to the OS + + @param[in] EFI_EVENT Event + @param[in] VOID *Context + + @retval None + +**/ +VOID +EFIAPI +EnableAntiFlashWearout ( + EFI_EVENT Event, + VOID *Context + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpServices =3D NULL; + SYSTEM_CONFIGURATION SetupData; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + CopyMem (&SetupData, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CONFIGURATION)); + + // + // First check if Anti-flash wearout feature is supported by platform an= d Setup variable is enabled + // + if (SetupData.AntiFlashWearoutSupported =3D=3D TRUE && SetupData.EnableA= ntiFlashWearout) { + Status =3D gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **) &MpServices + ); + ASSERT_EFI_ERROR(Status); + + // + // Set WPE on BSP, then all other APs + // + DynamicSiLibraryProtocol->SetBiosInfoFlagWpe(); + + MpServices->StartupAllAPs ( + MpServices, + (EFI_AP_PROCEDURE) DynamicSiLibraryProtocol->SetBiosIn= foFlagWpe, + FALSE, + NULL, + 0, + NULL, + NULL + ); + } +} + +/** + Before console after trusted console event callback + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the Even= t. +**/ +VOID +BdsBoardBeforeConsoleAfterTrustedConsoleCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *Interface; + + DEBUG ((DEBUG_INFO, "Board gBdsEventBeforeConsoleBeforeEndOfDxeGuid call= back starts\n")); + // + // make sure root bridge is already connected before EndOfDxe. + // Try to locate gEfiPciEnumerationCompleteProtocolGuid to see if PciBus= scan already executed. + // + Status =3D gBS->LocateProtocol ( + &gEfiPciEnumerationCompleteProtocolGuid, + NULL, + &Interface + ); + if (EFI_ERROR (Status)) { + ConnectRootBridge (FALSE); + } +} + +EFI_STATUS +EFIAPI +BoardNotificationInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + UINT32 BspCpuidSignature; + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *UdsHobPtr; + EFI_BOOT_MODE BootMode; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GU= ID; + EFI_EVENT BeforeConsoleAfterTrustedConsoleEvent; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG((DEBUG_INFO, "PlatformEarlyDxeEntry \n")); + + // + // Get the IIO_UDS data HOB + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT(GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + UdsHobPtr =3D GET_GUID_HOB_DATA(GuidHob); + // + // Allocate Memory Pool buffer for IIO_UDS data + // + Status =3D gBS->AllocatePool ( EfiBootServicesData, sizeof (IIO_UDS), (V= OID **) &mIioUds ); + ASSERT_EFI_ERROR (Status); + // + // Initialize the Memory Pool buffer with the data from the Hand-Off-Blo= ck + // + CopyMem(mIioUds, UdsHobPtr, sizeof(IIO_UDS)); + + // + // Get the boot mode that we are currently in + // + BootMode =3D GetBootModeHob(); + + // + // Program DPR registers with the range from Memory Init + // + ProgramDprRegs (); + + // + // Program the GenProtRange registers for BIOS Guard + // + DynamicSiLibraryProtocol->ProgramGenProtRangeRegs (mIioUds); + + // + // Program the IMR registers for ME IMR region + // + DynamicSiLibraryProtocol->ProgramImrRegs (mIioUds); + + // + // Program the IMR2 registers for CPM & nCPM IMR region + // + DynamicSiLibraryProtocol->ProgramImr2Regs (mIioUds); + + // + // Get BSP CPU ID + // Shift out the stepping + // + AsmCpuid (0x01, &RegEax, &RegEbx, &RegEcx, &RegEdx); + BspCpuidSignature =3D (RegEax >> 4) & 0x0000FFFF; + if ( (BspCpuidSignature =3D=3D CPU_FAMILY_SKX) && (BootMode !=3D BOOT_ON= _FLASH_UPDATE)) { + // + // Register event to set WPE bit in Bios Info Flags MSR to enable Anti= Flash wearout + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + EnableAntiFlashWearout, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + } + + // + // Create BeforeConsoleAfterTrustedConsole event callback + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + BdsBoardBeforeConsoleAfterTrustedConsoleCallback, + NULL, + &gBdsEventBeforeConsoleAfterTrustedConsoleGuid, + &BeforeConsoleAfterTrustedConsoleEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Boa= rdInitDxeLib.inf new file mode 100644 index 0000000000..219512566c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.inf @@ -0,0 +1,72 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitDxeLib + FILE_GUID =3D DDD75880-C38A-4D6B-B84E-FAC1122560BF + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + CONSTRUCTOR =3D BoardNotificationInit + +[Sources] + BoardInitDxeLib.c + BoardInitDxeLib.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + IoLib + PcdLib + HobLib + UefiLib + BaseMemoryLib + HiiLib + UefiBootManagerLib + BoardBdsHookLib + +[Guids] + gEfiPlatformTxtDeviceMemoryGuid + gEfiDprRegsProgrammedGuid + gEfiSetupVariableGuid + gEfiEndOfDxeEventGroupGuid + gEfiEventExitBootServicesGuid + gImr2BaseAddressHobGuid + gBdsEventBeforeConsoleAfterTrustedConsoleGuid + +[Protocols] + gEfiMpServiceProtocolGuid + gEfiPciEnumerationCompleteProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Pcd] + gPlatformTokenSpaceGuid.PcdImr0Enable + gPlatformTokenSpaceGuid.PcdImr0Base + gPlatformTokenSpaceGuid.PcdImr0Mask + gPlatformTokenSpaceGuid.PcdImr0Rac + gPlatformTokenSpaceGuid.PcdImr0Wac + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Enable + gEfiCpRcPkgTokenSpaceGuid.PcdImr2Size + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderLoad + gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderStart + gStructPcdTokenSpaceGuid.PcdSetup + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitDxeLib.uni b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Boa= rdInitDxeLib.uni new file mode 100644 index 0000000000..05fcfa3439 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitDxeL= ib.uni @@ -0,0 +1,29 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +//**/ + +/=3D# + +#langdef en-US "English" +#langdef fr-FR "Fran=C3=A7ais" + +#string STR_BOOT_PROMPT #language en-US "\n\n" + " Press [Enter= ] to directly boot.\n" + " Press [F2] = to enter setup and select boot options.\n" + " Press [F7] = to show boot menu options.\n\n" + " Copyright (c= ) 2006 - 2021, Intel Corporation.\n" + #language fr-FR "\n\n" + " Press [Enter= ] to directly boot.\n" + " Press [F2] = to enter setup and select boot options.\n" + " Press [F7] = to show boot menu options.\n\n" + " Copyright (c= ) 2006 - 2021, Intel Corporation.\n" +#string STR_START_BOOT_OPTION #language en-US "Start boot option" + #language fr-FR "l'option de botte= de D=C3=A9but" +#string STR_MFG_MODE_PROMPT #language en-US "\n\n\n" + " !!!Booting i= n Manufacturing Mode!!!\n" diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitPreMemLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/Bo= ardInitPreMemLib.c new file mode 100644 index 0000000000..5c186ce862 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitPreM= emLib.c @@ -0,0 +1,450 @@ +/** @file + Platform Hook Library instances + +@copyright +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfigurati= on, + IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCo= reConfig, + IN SOCKET_IIO_CONFIGURATION *SocketIioConfig + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +VOID +EarlyPlatformPchInit ( + VOID + ) +{ + UINT16 Data16; + UINT8 Data8; + UINTN LpcBaseAddress; + UINT8 TcoRebootHappened; + UINTN SpiBaseAddress; + UINTN P2sbBase; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - Start\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + SpiBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + + // + // Program bar + // + P2sbBase =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + + MmioWrite32 (P2sbBase + R_P2SB_CFG_SBREG_BAR, PCH_PCR_BASE_ADDRESS); + MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + // + // LPC I/O Configuration + // + DynamicSiLibraryPpi->PchLpcIoDecodeRangesSet ( + (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) | + (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) | + (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) + ); + + DynamicSiLibraryPpi->PchLpcIoEnableDecodingSet ( + B_LPC_CFG_IOE_ME2 | + B_LPC_CFG_IOE_SE | + B_LPC_CFG_IOE_ME1 | + B_LPC_CFG_IOE_KE | + B_LPC_CFG_IOE_HGE | + B_LPC_CFG_IOE_LGE | + B_LPC_CFG_IOE_FDE | + B_LPC_CFG_IOE_PPE | + B_LPC_CFG_IOE_CBE | + B_LPC_CFG_IOE_CAE + ); + // + // Enable the upper 128-byte bank of RTC RAM + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_RTC_HOST, R_RTC_PCR_CONF, (U= INT32)~0, B_RTC_PCR_CONF_UCMOS_EN); + + // + // Disable the Watchdog timer expiration from causing a system reset + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT3= 2)~0, B_ITSS_PCR_GIC_AME); + // + // Halt the TCO timer + // + Data16 =3D IoRead16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT); + Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT; + IoWrite16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT, Data16); + + // + // Read the Second TO status bit + // + Data8 =3D IoRead8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS); + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECON= D_TO) { + TcoRebootHappened =3D 1; + DEBUG ((EFI_D_INFO, "EarlyPlatformPchInit - TCO Second TO status bit i= s set. This might be a TCO reboot\n")); + } else { + TcoRebootHappened =3D 0; + } + + // + // Clear the Second TO status bit + // + Data8 |=3D (UINT8) B_TCO_IO_TCO2_STS_SECOND_TO; + Data8 &=3D (UINT8) ~B_TCO_IO_TCO2_STS_INTRD_DET; + IoWrite8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS, Data8); + + // + // Disable SERR NMI and IOCHK# NMI in port 61 + // + Data8 =3D IoRead8 (R_PCH_IO_NMI_SC); + Data8 |=3D (B_PCH_IO_NMI_SC_PCI_SERR_EN | B_PCH_IO_NMI_SC_IOCHK_NMI_EN); + IoWrite8 (R_PCH_IO_NMI_SC, Data8); + + DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT3= 2)~B_ITSS_PCR_GIC_AME, 0); + + // + // Clear EISS bit to allow for SPI use + // + MmioAnd8 (SpiBaseAddress + R_SPI_CFG_BC, (UINT8)~B_SPI_CFG_BC_EISS); + + // + // Enable LPC decode at 0xCA0 for BMC + // + DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IPMI_DEFAULT_SMM_IO_BASE & 0x= FF0), 0x10); + DEBUG ((EFI_D_INFO, "[IPMI_DEBUG]: PchLpcGenIoRangeSet 0x%x!\n", IPMI_DE= FAULT_SMM_IO_BASE)); + + DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - End\n")); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + SYSTEM_CONFIGURATION SysSetupData; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreSetupData; + SOCKET_IIO_CONFIGURATION SocketIioSetupData; + PCH_SETUP PchSetupData; + UINT16 ABase; + UINT16 Pm1Sts =3D 0; + UINT32 Pm1Cnt; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Get Setup Data + // + + ZeroMem (&SysSetupData, sizeof(SYSTEM_CONFIGURATION)); + ZeroMem (&SocketProcessorCoreSetupData, sizeof(SOCKET_PROCESSORCORE_CONF= IGURATION)); + ZeroMem (&SocketIioSetupData, sizeof(SOCKET_IIO_CONFIGURATION)); + ZeroMem (&PchSetupData, sizeof(PCH_SETUP)); + + CopyMem (&PchSetupData, PcdGetPtr(PcdPchSetup), sizeof(PCH_SETUP)); + CopyMem (&SysSetupData, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CONFIGURATION= )); + CopyMem (&SocketProcessorCoreSetupData, PcdGetPtr(PcdSocketProcessorCore= Config), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION)); + CopyMem (&SocketIioSetupData, PcdGetPtr(PcdSocketIioConfig), sizeof(SOCK= ET_IIO_CONFIGURATION)); + // + // Configure GPIO + // + Status =3D BoardInit (); + + EarlyPlatformPchInit (); + + /// + /// Set what state (S0/S5) to go to when power is re-applied after a pow= er failure (G3 state) + /// + DynamicSiLibraryPpi->PmcSetPlatformStateAfterPowerFailure (PchSetupData.= StateAfterG3); + + // + // Check PWR FLR + // + if (DynamicSiLibraryPpi->PmcIsPowerFailureDetected ()) { + DynamicSiLibraryPpi->PmcClearPowerFailureStatus (); + } + ///---------------------------------------------------------------------= ------------- + /// + /// Clear PWR_BTN_STS if set. BIOS should check the WAK_STS bit in PM1_S= TS[15] (PCH register ABASE+00h) before memory + /// initialization to determine if ME has reset the system while the Hos= t was in a sleep state. + /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is t= aken by overwriting + /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit. + /// + ABase =3D DynamicSiLibraryPpi->PmcGetAcpiBase (); + + Pm1Sts =3D IoRead16 (ABase + R_ACPI_IO_PM1_STS); + if ((Pm1Sts & B_ACPI_IO_PM1_STS_PWRBTN) =3D=3D B_ACPI_IO_PM1_STS_PWRBTN)= { + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN); + } + + if ((Pm1Sts & B_ACPI_IO_PM1_STS_WAK) =3D=3D 0) { + Pm1Cnt =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D V_ACPI_IO_PM1_CNT_S5; + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + // + // Update Platform Info + // + UpdatePlatformInfo (&SysSetupData,&SocketProcessorCoreSetupData,&SocketI= ioSetupData); + + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT16 Pm1Cnt; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Check if user wants to turn off in PEI phase + // + if (BootMode !=3D BOOT_ON_S3_RESUME) { + DynamicSiLibraryPpi->CheckPowerOffNow (); + } else { + Pm1Cnt =3D IoRead16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT); + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SLP_TYP; + IoWrite16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + + Initialize POC register by Variable. + + @param *SystemConfiguration - Pointer to SystemConfiguration variables. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfigurati= on, + IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCo= reConfig, + IN SOCKET_IIO_CONFIGURATION *SocketIioConfig + ) +{ + EFI_PLATFORM_INFO *PlatformInfo; + EFI_HOB_GUID_TYPE *GuidHob; + // + // Update the PCIE base and 32/64bit PCI resource support + // + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + PlatformInfo->SysData.SysIoApicEnable =3D PCH_IOAPIC; +#if MAX_SOCKET <=3D 4 + if (SocketIioConfig->DevPresIoApicIio[0]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC00_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[1]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC01_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[2]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC02_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[3]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC03_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[4]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC04_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[5]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC05_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[6]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC06_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[7]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC07_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[8]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC08_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[9]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC09_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[10]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC10_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[11]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC11_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[12]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC12_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[13]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC13_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[14]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC14_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[15]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC15_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[16]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC16_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[17]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC17_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[18]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC18_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[19]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC19_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[20]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC20_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[21]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC21_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[22]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC22_IOAPIC); + } + if (SocketIioConfig->DevPresIoApicIio[23]) { + PlatformInfo->SysData.SysIoApicEnable |=3D (PC23_IOAPIC); + } +#else + // Enable all 32 IOxAPIC + PlatformInfo->SysData.SysIoApicEnable =3D 0xFFFFFFFF; +#endif + // + // Check to make sure TsegSize is in range, if not use default. + // + if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) { + SocketProcessorCoreConfig->TsegSize =3D MAX_PROCESSOR_TSEG; // if out = of range make default 64M + } + PlatformInfo->MemData.MemTsegSize =3D (0x400000 << SocketProcessorCoreC= onfig->TsegSize); + PlatformInfo->MemData.MemIedSize =3D PcdGet32 (PcdCpuIEDRamSize); + + // + // Minimum SMM range in TSEG should be larger than 3M + // + ASSERT (PlatformInfo->MemData.MemTsegSize - PlatformInfo->MemData.MemIed= Size >=3D 0x300000); + + return EFI_SUCCESS; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardI= nitPreMemLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/= BoardInitPreMemLib.inf new file mode 100644 index 0000000000..3e1f966f32 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/BoardInitLib/BoardInitPreM= emLib.inf @@ -0,0 +1,66 @@ +## @file +# Component information file for PEI Board Init Pre-Mem Library +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitPreMemLib + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + PeiServicesLib + PeimEntryPoint + PciLib + PeiServicesTablePointerLib + PciExpressLib + BaseCryptLib + CmosAccessLib + PeiPlatformHookLib + ReportStatusCodeLib + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + HobLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + BoardInitPreMemLib.c + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gEfiPlatformInfoGuid + +[Pcd] + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdPchSetup + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupport.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatS= upportLib/MultiPlatSupport.h new file mode 100644 index 0000000000..76cea4cb38 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupport.h @@ -0,0 +1,48 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MULTI_PLATFORM_SUPPORT_H_ +#define _MULTI_PLATFORM_SUPPORT_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gDefaultDataFileGuid; +extern EFI_GUID gEfiVariableGuid; +extern EFI_GUID gEfiAuthenticatedVariableGuid; + +typedef struct { + UINT16 DefaultId; + UINT8 BoardId; +} DEFAULT_INFO; + +typedef struct { + // + // HeaderSize includes HeaderSize fields and DefaultInfo arrays + // + UINT16 HeaderSize; + // + // DefaultInfo arrays those have the same default setting. + // + DEFAULT_INFO DefaultInfo[1]; + // + // Default data is stored as variable storage. + // VARIABLE_STORE_HEADER VarStorageHeader; + // +} DEFAULT_DATA; + + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupportLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPl= atSupportLib/MultiPlatSupportLib.c new file mode 100644 index 0000000000..9f0af4b3e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupportLib.c @@ -0,0 +1,255 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +//notes +//1: security variable and non-security variable may have different implem= entation +//2. BP core variable sync may need update this module +//3 different generation need to sync base on RP variable and Generation v= ariable +// this library to use a lightweight get variable service to patch variabl= e hob before PEI variable service is ready + + + + + + +/** + Gets a vairable store header from FFS inserted by FCE + + Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + + + @return The start address of VARIABLE_STORE_HEADER *. Null if cannot fin= d it + +**/ + +VOID * FindDefaultHobinFfs ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ) +{ + EFI_PEI_SERVICES **PeiServices; + UINTN FvInstance; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_FFS_FILE_HEADER *FfsHeader; + UINT32 FileSize; + EFI_COMMON_SECTION_HEADER *Section; + UINT32 SectionLength; + BOOLEAN DefaultFileIsFound; + DEFAULT_DATA *DefaultData; + DEFAULT_INFO *DefaultInfo; + VARIABLE_STORE_HEADER *VarStoreHeader; + UINT32 FFSSize =3D 0; + + + + // + // Get PeiService pointer + // + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + + // + // Find the FFS file that stores all default data. + // + DefaultFileIsFound =3D FALSE; + FvInstance =3D 0; + FfsHeader =3D NULL; + while (((*PeiServices)->FfsFindNextVolume (PeiServices, FvInstance, &FvH= eader) =3D=3D EFI_SUCCESS) && + (!DefaultFileIsFound)) { + FfsHeader =3D NULL; + while ((*PeiServices)->FfsFindNextFile (PeiServices, EFI_FV_FILETYPE_F= REEFORM, FvHeader, &FfsHeader) =3D=3D EFI_SUCCESS) { + if (CompareGuid ((EFI_GUID *) FfsHeader, &gDefaultDataFileGuid)) { + DefaultFileIsFound =3D TRUE; + break; + } + } + FvInstance ++; + } + + // + // FFS file is not found. + // + if (!DefaultFileIsFound) { + + if(PcdGet32(PcdFailSafeVarFfsSize)!=3D0 ){ + //try to search other FVS + FfsHeader =3D (EFI_FFS_FILE_HEADER *) AllocatePool(PcdGet32(PcdFailS= afeVarFfsSize) ); + if(FfsHeader =3D=3D NULL) { + return NULL; + } + if(EFI_SUCCESS !=3D ReadFFSFile( (EFI_FIRMWARE_VOLUME_HEADER *) PcdG= et32(PcdFailSafeVarFvBase), gDefaultDataFileGuid, 0, FfsHeader, &FFSSize, F= ALSE)) { + return NULL; + } + ASSERT(PcdGet32(PcdFailSafeVarFfsSize) Size) & 0x00FFFFFF; + while (((UINTN) Section < (UINTN) FfsHeader + FileSize) && (VarStoreHead= er =3D=3D NULL)) { + DefaultData =3D (DEFAULT_DATA *) (Section + 1); + DefaultInfo =3D &(DefaultData->DefaultInfo[0]); + while ((UINTN) DefaultInfo < (UINTN) DefaultData + DefaultData->Header= Size) { + if (DefaultInfo->DefaultId =3D=3D DefaultId && DefaultInfo->BoardId = =3D=3D BoardId) { + VarStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINT8 *) DefaultDat= a + DefaultData->HeaderSize); + break; + } + DefaultInfo ++; + } + // + // Size is 24 bits wide so mask upper 8 bits. + // SectionLength is adjusted it is 4 byte aligned. + // Go to the next section + // + SectionLength =3D *(UINT32 *)Section->Size & 0x00FFFFFF; + SectionLength =3D (SectionLength + 3) & (~3); + ASSERT (SectionLength !=3D 0); + Section =3D (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLe= ngth); + } + + return VarStoreHeader; + +} + + +/** + This function searches the first instance of a HOB from the starting HOB= pointer. + Such HOB should satisfy two conditions: + its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to = the input Guid. + If there does not exist such HOB from the starting HOB pointer, it will = return NULL. + Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_S= IZE () + to extract the data section and its size info respectively. + In contrast with macro GET_NEXT_HOB(), this function does not skip the s= tarting HOB pointer + unconditionally: it returns HobStart back if HobStart itself meets the r= equirement; + caller is required to use GET_NEXT_HOB() if it wishes to skip current Ho= bStart. + If Guid is NULL, then ASSERT(). + If HobStart is NULL, then ASSERT(). + + @param Guid The GUID to match with in the HOB list. + @param HobStart A pointer to a Guid. + + @return The next instance of the matched GUID HOB from the starting HOB. + +**/ +VOID * +InternalGetNextGuidHob ( + IN CONST EFI_GUID *Guid, + IN CONST VOID *HobStart + ) +{ + EFI_PEI_HOB_POINTERS GuidHob; + + GuidHob.Raw =3D (UINT8 *) HobStart; + while (!END_OF_HOB_LIST (GuidHob)) { + if (GuidHob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION && Comp= areGuid (Guid, &GuidHob.Guid->Name)) { + break; + } + GuidHob.Raw =3D GET_NEXT_HOB (GuidHob); + } + return GuidHob.Raw; +} + +EFI_STATUS +CreateDefaultVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ) +/*++ +Description: + + This function finds the matched default data and create GUID hob for it. + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ +{ + VARIABLE_STORE_HEADER *VarStoreHeader; + VARIABLE_STORE_HEADER *VarStoreHeaderHob; + UINT8 *VarHobPtr; + UINT8 *VarPtr; + UINT32 VarDataOffset; + UINT32 VarHobDataOffset; + EFI_PEI_SERVICES **PeiServices; + + // + // Get PeiService pointer + // + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + + VarStoreHeader =3D (VARIABLE_STORE_HEADER*)FindDefaultHobinFfs( DefaultI= d, BoardId); + + // + // Matched default data is not found. + // + if (VarStoreHeader =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + // + // Create HOB to store defautl data so that Variable driver can use it. + // Allocate more data for header alignment. + // + VarStoreHeaderHob =3D (VARIABLE_STORE_HEADER *) BuildGuidHob (&VarStoreH= eader->Signature, VarStoreHeader->Size + HEADER_ALIGNMENT - 1); + if (VarStoreHeaderHob =3D=3D NULL) { + // + // No enough hob resource. + // + return EFI_OUT_OF_RESOURCES; + } + + // + // Copy variable storage header. + // + CopyMem (VarStoreHeaderHob, VarStoreHeader, sizeof (VARIABLE_STORE_HEADE= R)); + // + // Copy variable data. + // + VarPtr =3D (UINT8 *) HEADER_ALIGN ((UINTN) (VarStoreHeader + 1= )); + VarDataOffset =3D (UINT32) ((UINTN) VarPtr - (UINTN) VarStoreHeader); + VarHobPtr =3D (UINT8 *) HEADER_ALIGN ((UINTN) (VarStoreHeaderHob = + 1)); + VarHobDataOffset =3D (UINT32) ((UINTN) VarHobPtr - (UINTN) VarStoreHeade= rHob); + CopyMem (VarHobPtr, VarPtr, VarStoreHeader->Size - VarDataOffset); + // + // Update variable size. + // + VarStoreHeaderHob->Size =3D VarStoreHeader->Size - VarDataOffset + VarHo= bDataOffset; + + // SyncSetupVariable(PeiServices,VarStoreHeaderHob,FALSE); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib= /MultiPlatSupportLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Multi= PlatSupportLib/MultiPlatSupportLib.inf new file mode 100644 index 0000000000..ea8d853314 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/MultiPlatSupportLib/MultiP= latSupportLib.inf @@ -0,0 +1,49 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +#--*/ +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D MultiPlatSupportLib + FILE_GUID =3D EA5EEAF9-2EB4-4fbf-BB28-5B3A605B8665 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MultiPlatSupportLib|PEIM PEI_CORE + +[Sources] + MultiPlatSupportLib.c + + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PeiServicesTablePointerLib + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + IoLib + PciLib + PcdLib + ReadFfsLib + MemoryAllocationLib + +[Guids] + gDefaultDataFileGuid ## CONSUMES ## File + +[Pcd] + gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize + gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPro= cessLib/FspWrapperHobProcessLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Libr= ary/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c new file mode 100644 index 0000000000..19dc82d7a7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib= /FspWrapperHobProcessLib.c @@ -0,0 +1,722 @@ +/** @file + Provide FSP wrapper hob process related function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Additional pages are used by DXE memory manager. +// It should be consistent between RetrieveRequiredMemorySize() and GetPei= MemSize() +// +#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE) + +EFI_GUID mCpuVarDataHobGuid =3D {0x71dd88db, 0x1722, 0x48af, {0x96, 0x5b, = 0x5e, 0x15, 0xaf, 0xfe, 0x86, 0x56}}; +/** + Get the mem size in memory type infromation table. + + @param[in] PeiServices PEI Services table. + + @return the mem size in memory type infromation table. +**/ +UINT64 +GetMemorySizeInMemoryTypeInformation ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + EFI_MEMORY_TYPE_INFORMATION *MemoryData; + UINT8 Index; + UINTN TempPageNum; + + MemoryData =3D NULL; + Status =3D (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES**)Pei= Services, (VOID **) &Hob.Raw); + ASSERT_EFI_ERROR (Status); + + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION && + CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) { + MemoryData =3D (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EF= I_HOB_GENERIC_HEADER) + sizeof (EFI_GUID)); + break; + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + if (MemoryData =3D=3D NULL) { + return 0; + } + + TempPageNum =3D 0; + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= { + // + // Accumulate default memory size requirements + // + TempPageNum +=3D MemoryData[Index].NumberOfPages; + } + + return TempPageNum * EFI_PAGE_SIZE; +} + +/** + Get the mem size need to be reserved in PEI phase. + + @param[in] PeiServices PEI Services table. + + @return the mem size need to be reserved in PEI phase. +**/ +UINT64 +RetrieveRequiredMemorySize ( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + UINT64 Size; + + Size =3D GetMemorySizeInMemoryTypeInformation (PeiServices); + return Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +/** + Get the mem size need to be consumed and reserved in PEI phase. + + @param[in] PeiServices PEI Services table. + @param[in] BootMode Current boot mode. + + @return the mem size need to be consumed and reserved in PEI phase. +**/ +UINT64 +GetPeiMemSize ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 BootMode + ) +{ + UINT64 Size; + UINT64 MinSize; + + if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + return PcdGet32 (PcdPeiRecoveryMinMemSize); + } + + Size =3D GetMemorySizeInMemoryTypeInformation (PeiServices); + + MinSize =3D PcdGet32 (PcdPeiMinMemSize); + + return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +VOID +TransferHobData ( + VOID *HobStart, + EFI_GUID *InfoGuid, + UINT8 *Info + ) +{ + VOID *GuidHob; + VOID *Data; + UINTN DataSize; + VOID *Hob; + + GuidHob =3D GetNextGuidHob (InfoGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find %a\n", Info)); + return; + } + + Data =3D GET_GUID_HOB_DATA (GuidHob); + DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + Hob =3D BuildGuidDataHob ( + InfoGuid, + Data, + DataSize + ); + DEBUG ((DEBUG_INFO, "Create %a Hob at %x\n", Info, Hob)); +} + +VOID +CopyHobData ( + VOID *HobStart, + EFI_GUID *InfoGuid, + UINT8 *Info + ) +{ + VOID *GuidHob; + VOID *Data; + VOID *OrgGuidHob; + VOID *OrgData; + UINTN DataSize; + UINTN OrgDataSize; + + GuidHob =3D GetNextGuidHob (InfoGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find %a\n", Info)); + return; + } + + Data =3D GET_GUID_HOB_DATA (GuidHob); + DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + + OrgGuidHob =3D GetFirstGuidHob (InfoGuid); + if (OrgGuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Copy Hob Can't Find org %a\n", Info)); + } + + OrgData =3D GET_GUID_HOB_DATA (OrgGuidHob); + OrgDataSize =3D GET_GUID_HOB_DATA_SIZE (OrgGuidHob); + if (OrgDataSize !=3D DataSize) { + DEBUG ((EFI_D_ERROR, "%a Hob Size Don't Match Between FSP and BootLoad= er. FSP:%x vs BootLoader:%x\n", OrgDataSize, DataSize)); + ASSERT (FALSE); + } + CopyMem (OrgData, Data, DataSize); + + DEBUG ((EFI_D_ERROR, "CopyHobData %a Hob from %x to %x, Size: %x\n", Inf= o, Data, OrgData, DataSize)); +} + + +VOID +TransferPcd ( + VOID * HobStart + ) +{ + VOID *GuidHob; + EFI_PHYSICAL_ADDRESS *HobBuffer; + + GuidHob =3D GetNextGuidHob (&gSaveHostToMemoryGuid, HobStart); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Transfer Hob Can't Find gSaveHostToMemoryGuid\n"= )); + return; + } + + HobBuffer =3D (EFI_PHYSICAL_ADDRESS*) GET_GUID_HOB_DATA (GuidHob); + PcdSet64S (PcdSyshostMemoryAddress, (UINTN) HobBuffer[0]); + PcdSet64S (PcdMemMapHostMemoryAddress, (UINTN) HobBuffer[1]); + DEBUG ((DEBUG_INFO, "TransferPcd Set PcdSyshostMemoryAddress %x\n", (UIN= TN) HobBuffer[0])); + DEBUG ((DEBUG_INFO, "TransferPcd Set PcdMemMapHostMemoryAddress %x\n", (= UINTN) HobBuffer[1])); +} + + +/** + Post FSP-M HOB process for Memory Resource Descriptor. + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + + @return If platform process the FSP hob list successfully. +**/ +EFI_STATUS +EFIAPI +PostFspmHobProcess ( + IN VOID *FspHobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 PeiMemSize; + EFI_PHYSICAL_ADDRESS PeiMemBase; + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_PEI_CAPSULE_PPI *Capsule; + VOID *CapsuleBuffer; + UINTN CapsuleBufferLength; + UINT64 RequiredMemSize; + UINT64 ResourceLength; + EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D (EFI_PEI_SERVICES **) GetPeiServicesTablePointer (); + + PeiServicesGetBootMode (&BootMode); + + PeiMemBase =3D 0; + PeiMemSize =3D 0; + RequiredMemSize =3D 0; + ResourceLength =3D 0; + + // + // Parse the hob list from fsp + // Report all the resource hob except MMIO and IO resource Hob's + // + if (BootMode !=3D BOOT_ON_S3_RESUME) { + PeiMemSize =3D GetPeiMemSize (PeiServices, BootMode); + RequiredMemSize =3D RetrieveRequiredMemorySize (PeiServices); + Hob.Raw =3D (UINT8*)(UINTN) FspHobList; + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); + + // + // Find the largest available system Memory and use it for PeiMemory + // + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.= Raw)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength <=3D BASE_4GB) + && (Hob.ResourceDescriptor->PhysicalStart >=3D PeiMemBase) + && (Hob.ResourceDescriptor->ResourceLength >=3D PeiMemSize)) { + PeiMemBase =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Reso= urceDescriptor->ResourceLength - PeiMemSize; + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + } + + CopyHobData (FspHobList, &gSystemInfoVarHobGuid, (UINT8*) "gSystemInfoVa= rHobGuid"); + CopyHobData (FspHobList, &gIioSiPolicyHobGuid, (UINT8*) "gIioSiPolicyHob= Guid"); + TransferPcd (FspHobList); + + Hob.Raw =3D (UINT8 *)(UINTN) FspHobList; + + // + // Skip the MMIO and IO reource map from the FSP Hob list + // + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Ra= w)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_IO) || (= Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMORY_MAPPED_IO))= { + Hob.Raw =3D GET_NEXT_HOB (Hob); + continue; + } + ResourceLength =3D Hob.ResourceDescriptor->ResourceLength; + DEBUG ((DEBUG_INFO, "Resource start %lx resource length %lx resource t= ype %d\n", Hob.ResourceDescriptor->PhysicalStart, Hob.ResourceDescriptor->R= esourceLength, Hob.ResourceDescriptor->ResourceType)); + if (BootMode !=3D BOOT_ON_S3_RESUME) { + // + // If the system memory found in FSP Hob is determined for PeiMemory= . Split the Resource descriptor Hob + // + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart <=3D PeiMemBase) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength >=3D PeiMemBase + PeiMemSize) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor= ->ResourceLength <=3D BASE_4GB)) { + if ((CompareGuid (&Hob.ResourceDescriptor->Owner, &gZeroGuid))) { + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + PeiMemBase, + PeiMemSize + ); + } else { + BuildResourceDescriptorWithOwnerHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + PeiMemBase, + PeiMemSize, + &Hob.ResourceDescriptor->Owner + ); + } + ResourceLength =3D (Hob.ResourceDescriptor->ResourceLength) - (Pei= MemSize); + } + } + + // + // Report the resource hob + // + if ((CompareGuid (&Hob.ResourceDescriptor->Owner, &gZeroGuid))) { + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + ResourceLength + ); + } else { + BuildResourceDescriptorWithOwnerHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + ResourceLength, + &Hob.ResourceDescriptor->Owner + ); + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // @todo: It is a W/A for SetMemorySpaceAttribute issue in PchSpi and Pc= hReset drivers. + // We need to modify it instead of hard code here. Due to Install= EfiMemory is using hard code to + // describe memory resource, we have to hard code in here. Once I= nstallEfiMemory is merged, we should + // be able to remove this. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFFA00000, + 0x80000 + ); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFE000000, + 0x10000 + ); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | = EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE, + 0xFE010000, + 0x1000 + ); + + // + // Capsule mode + // + Capsule =3D NULL; + CapsuleBuffer =3D NULL; + CapsuleBufferLength =3D 0; + if (BootMode =3D=3D BOOT_ON_FLASH_UPDATE) { + Status =3D PeiServicesLocatePpi ( + &gEfiPeiCapsulePpiGuid, + 0, + NULL, + (VOID **) &Capsule + ); + ASSERT_EFI_ERROR (Status); + + if (Status =3D=3D EFI_SUCCESS) { + Status =3D PeiServicesGetHobList ((void**)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = Hob.Raw)) !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDes= criptor->ResourceLength <=3D BASE_4GB) + && (Hob.ResourceDescriptor->PhysicalStart >=3D BASE_1MB) + && (Hob.ResourceDescriptor->PhysicalStart !=3D PeiMemBase) + && (Hob.ResourceDescriptor->ResourceLength >=3D CapsuleBuff= erLength)) { + CapsuleBufferLength =3D (UINTN)Hob.ResourceDescriptor->Resour= ceLength; + CapsuleBuffer =3D (VOID*)(UINTN)Hob.ResourceDescriptor->Physi= calStart; + + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // Call the Capsule PPI Coalesce function to coalesce the capsule = data. + // + Status =3D Capsule->Coalesce (PeiServices, &CapsuleBuffer, &Capsul= eBufferLength); + } + } + + DEBUG ((DEBUG_INFO, "FSP wrapper PeiMemBase : 0x%08x\n", PeiMemBa= se)); + DEBUG ((DEBUG_INFO, "FSP wrapper PeiMemSize : 0x%08x\n", PeiMemSi= ze)); + DEBUG ((DEBUG_INFO, "FSP wrapper RequiredMemSize : 0x%08x\n", Required= MemSize)); + + // + // Install efi memory + // + Status =3D PeiServicesInstallPeiMemory ( + PeiMemBase, + PeiMemSize - RequiredMemSize + ); + ASSERT_EFI_ERROR (Status); + + if (Capsule !=3D NULL) { + Status =3D Capsule->CreateState ((EFI_PEI_SERVICES **) PeiServices, = CapsuleBuffer, CapsuleBufferLength); + } + + + // + // Create a memory allocation HOB at fixed location for MP Services PPI = AP wait loop. + // Report memory region used by FSP. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdFspCpuPeiApWakeupBufferAddr), + EFI_PAGE_SIZE, + EfiBootServicesData + ); + + return EFI_SUCCESS; +} + +/** + Process FSP HOB list + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + +**/ +VOID +ProcessFspHobList ( + IN VOID *FspHobList + ) +{ + UINT8 PhysicalAddressBits; + UINT32 RegEax; + EFI_PEI_HOB_POINTERS FspHob; + + FspHob.Raw =3D FspHobList; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8) RegEax; + } else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob (PhysicalAddressBits, 16); + + // + // Add all the HOBs from FSP binary to FSP wrapper + // + while (!END_OF_HOB_LIST (FspHob)) { + if (FspHob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + // + // Skip FSP binary creates PcdDataBaseHobGuid + // + if (!CompareGuid(&FspHob.Guid->Name, &gPcdDataBaseHobGuid)) { + BuildGuidDataHob ( + &FspHob.Guid->Name, + GET_GUID_HOB_DATA (FspHob), + GET_GUID_HOB_DATA_SIZE (FspHob) + ); + } + } + FspHob.Raw =3D GET_NEXT_HOB (FspHob); + } +} + +VOID +CheckFspGraphicsDeviceInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_INFO_HOB *FspGraphicsInfo =3D NULL; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *FspGraphicsDeviceInfo =3D NULL; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GraphicsDeviceInfo; + + Status =3D PeiServicesGetHobList ((VOID**) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsInfoHobGuid, Hob.Raw))= !=3D NULL) { + FspGraphicsInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + } + if (FspGraphicsInfo =3D=3D NULL) { + return ; + } + + Status =3D PeiServicesGetHobList ((VOID**) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsDeviceInfoHobGuid, Hob= .Raw)) !=3D NULL) { + FspGraphicsDeviceInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + } + if (FspGraphicsDeviceInfo !=3D NULL) { + return ; + } + + // + // FSP only publish FspGraphicsInfo, but no FspGraphicsDeviceInfo. + // + // Workaround: Need publish FspGraphicsDeviceInfo, because Intel Graphic= s BarIndex is 1. + // + GraphicsDeviceInfo.VendorId =3D MAX_UINT16; + GraphicsDeviceInfo.DeviceId =3D MAX_UINT16; + GraphicsDeviceInfo.SubsystemVendorId =3D MAX_UINT16; + GraphicsDeviceInfo.SubsystemId =3D MAX_UINT16; + GraphicsDeviceInfo.RevisionId =3D MAX_UINT8; + GraphicsDeviceInfo.BarIndex =3D 1; + BuildGuidDataHob ( + &gEfiGraphicsDeviceInfoHobGuid, + &GraphicsDeviceInfo, + sizeof(GraphicsDeviceInfo) + ); + + return ; +} + +/** + Dump FSP HOB list + +**/ +VOID +DumpFspHobList ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + DEBUG ((DEBUG_INFO, "FSP Extended GUID HOB: {%g}\n", &(Hob.Guid->= Name))); + } + if ((Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) && + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMORY_RE= SERVED)) { + DEBUG ((DEBUG_INFO, "FSP Reserved Resource HOB: %016lX ~ %016lX\n", \ + Hob.ResourceDescriptor->PhysicalStart, Hob.ResourceDescripto= r->PhysicalStart \ + + Hob.ResourceDescriptor->ResourceLength)); + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } +} + +/** + Dump FSP memory resource + +**/ +VOID +DumpFspMemoryResource ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "\nFSP Memory Resource\n")); + DEBUG ((DEBUG_INFO, " Resource Range Type Attribute= Owner\n")); + DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"= )); + while ((Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Ra= w)) !=3D NULL) { + if (!CompareGuid (&(Hob.ResourceDescriptor->Owner), &gZeroGuid)) { + DEBUG ((DEBUG_INFO, "%016lx-%016lx %4x %016x %g\n", + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescript= or->ResourceLength, + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + &(Hob.ResourceDescriptor->Owner) + )); + } else { + DEBUG ((DEBUG_INFO, "%016lx-%016lx %4x %016x \n", + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescript= or->ResourceLength, + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute + )); + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Dump FSP memory resource + +**/ +VOID +DumpFspGraphicsInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_INFO_HOB *FspGraphicsInfo =3D NULL; + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsInfoHobGuid, Hob.Raw))= !=3D NULL) { + FspGraphicsInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + if (FspGraphicsInfo !=3D NULL) { + DEBUG((DEBUG_INFO, "\nGraphicsInfo\n")); + DEBUG((DEBUG_INFO, " |-> FrameBufferBase : 0x%016lx\n", FspGraphics= Info->FrameBufferBase)); + DEBUG((DEBUG_INFO, " |-> FrameBufferSize : 0x%016lx\n", FspGraphics= Info->FrameBufferSize)); + DEBUG((DEBUG_INFO, " |-> GraphicsMode\n")); + DEBUG((DEBUG_INFO, " |-> Version : 0x%08x\n", FspGra= phicsInfo->GraphicsMode.Version)); + DEBUG((DEBUG_INFO, " |-> HorizontalResolution : %d\n", FspGraphic= sInfo->GraphicsMode.HorizontalResolution)); + DEBUG((DEBUG_INFO, " |-> VerticalResolution : %d\n", FspGraphic= sInfo->GraphicsMode.VerticalResolution)); + DEBUG((DEBUG_INFO, " |-> PixelFormat : %d\n", FspGraphic= sInfo->GraphicsMode.PixelFormat)); + DEBUG((DEBUG_INFO, " |-> PixelInformation : %d|%d|%d|%d\n", + FspGraphicsInfo->GraphicsMode.PixelInformation.RedMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.GreenMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.BlueMask, + FspGraphicsInfo->GraphicsMode.PixelInformation.ReservedMask + )); + DEBUG((DEBUG_INFO, " |-> PixelsPerScanLine : %d\n", FspGraphic= sInfo->GraphicsMode.PixelsPerScanLine)); + DEBUG((DEBUG_INFO, "\n")); + } else { + DEBUG((DEBUG_INFO, "\nNo GraphicsInfo\n")); + } + } +} + +VOID +DumpFspGraphicsDeviceInfoHob ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *FspGraphicsDeviceInfo =3D NULL; + + Status =3D PeiServicesGetHobList ((VOID **)&Hob.Raw); + if (!EFI_ERROR (Status)) { + if (Hob.Raw !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsDeviceInfoHobGuid, Hob= .Raw)) !=3D NULL) { + FspGraphicsDeviceInfo =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + if (FspGraphicsDeviceInfo !=3D NULL) { + DEBUG((DEBUG_INFO, "\nGraphicsDeviceInfo\n")); + DEBUG((DEBUG_INFO, " |-> VendorId : 0x%04x\n", FspGraphics= DeviceInfo->VendorId)); + DEBUG((DEBUG_INFO, " |-> DeviceId : 0x%04x\n", FspGraphics= DeviceInfo->DeviceId)); + DEBUG((DEBUG_INFO, " |-> SubsystemVendorId : 0x%04x\n", FspGraphics= DeviceInfo->SubsystemVendorId)); + DEBUG((DEBUG_INFO, " |-> SubsystemId : 0x%04x\n", FspGraphics= DeviceInfo->SubsystemId)); + DEBUG((DEBUG_INFO, " |-> RevisionId : 0x%02x\n", FspGraphics= DeviceInfo->RevisionId)); + DEBUG((DEBUG_INFO, " |-> BarIndex : 0x%02x\n", FspGraphics= DeviceInfo->BarIndex)); + DEBUG((DEBUG_INFO, "\n")); + } else { + DEBUG((DEBUG_INFO, "\nNo GraphicsDeviceInfo\n")); + } + } +} + +EFI_PEI_PPI_DESCRIPTOR mSiliconInitializedDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEdkiiSiliconInitializedPpiGuid, + NULL +}; + +/** + Post FSP-S HOB process (not Memory Resource Descriptor). + + @param[in] FspHobList Pointer to the HOB data structure produced by FSP. + + @return If platform process the FSP hob list successfully. +**/ +EFI_STATUS +EFIAPI +PostFspsHobProcess ( + IN VOID *FspHobList + ) +{ + EFI_STATUS Status; + + // + // Only in FSP API mode the wrapper has to build hobs basing on FSP outp= ut data. + // + ASSERT (FspHobList !=3D NULL); + ProcessFspHobList (FspHobList); + CheckFspGraphicsDeviceInfoHob (); + DEBUG_CODE_BEGIN (); + DumpFspGraphicsInfoHob (); + DumpFspGraphicsDeviceInfoHob (); + DumpFspHobList (); + DumpFspMemoryResource (); + DEBUG_CODE_END (); + + Status =3D PeiServicesInstallPpi (&mSiliconInitializedDesc); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPro= cessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf new file mode 100644 index 0000000000..f1dcc32147 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib= /PeiFspWrapperHobProcessLib.inf @@ -0,0 +1,99 @@ +## @file +# Provide FSP wrapper hob process related function. +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiFspWrapperHobProcessLib + FILE_GUID =3D C7B7070B-E5A8-4b86-9110-BDCA1095F496 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspWrapperHobProcessLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperHobProcessLib.c + + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + HobLib + DebugLib + FspWrapperPlatformLib + PeiServicesLib + PeiServicesTablePointerLib + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength + gMinPlatformPkgTokenSpaceGuid.PcdFspCpuPeiApWakeupBufferAddr + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize + gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress + gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress + +[Guids] + gFspReservedMemoryResourceHobGuid ## CONSUMES ## H= OB + gEfiMemoryTypeInformationGuid ## CONSUMES ## G= UID + gPcdDataBaseHobGuid + gZeroGuid + gEfiGraphicsInfoHobGuid + gEfiGraphicsDeviceInfoHobGuid + gCsrPseudoOffsetTableGuid + gReferenceCodePolicyHobGuid + gSaveHostToMemoryGuid + gEfiMemoryMapGuid + gRasRcPolicyHobGuid + gRasRcConfigHobGuid + gEfiSmmPeiSmramMemoryReserveGuid + gEfiAcpiVariableGuid + gEfiCpuPolicyDataHobGuid + gSystemInfoVarHobGuid + gIioSiPolicyHobGuid + +[Ppis] + gEfiPeiCapsulePpiGuid ## CONSUMES + gEdkiiSiliconInitializedPpiGuid ## PRODUCES diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/= PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatfo= rmHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..9adbfee4a1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/PeiPlat= formHooklib.c @@ -0,0 +1,43 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +/** + Configure GPIO + + @param[in] PlatformInfo +**/ +VOID +GpioInit ( +) +{ + EFI_STATUS Status; + Status =3D PlatformInitGpios(); +} + + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + ) +{ + + GpioInit(); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/= PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlat= formHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..4b40fbd9ad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiPlatformHookLib/PeiPlat= formHooklib.inf @@ -0,0 +1,34 @@ +## @file +# +# @copyright +# Copyright 1999 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D AD901798-B0DA-4b20-B90C-283F886E76D0 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[Sources] + PeiPlatformHooklib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + DebugLib + UbaGpioInitLib + +[Pcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/Pe= iReportFvLib.c new file mode 100644 index 0000000000..f0230642d2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.c @@ -0,0 +1,270 @@ +/** @file PeiReportFvLib.c + Source code file for Report Firmware Volume (FV) library + + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +ReportPreMemFv ( + VOID + ) +{ + UINTN Index =3D 0; + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; + EFI_BOOT_MODE BootMode =3D BOOT_WITH_FULL_CONFIG= URATION; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + DEBUG_CODE ( + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, &Ppi); + if (!EFI_ERROR (Status)) { + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength)); + } + } + ); + + // + // FvBspPreMemory and FvPreMemory are required for all stages. + // + + DEBUG ((DEBUG_INFO, "Install FlashFvBspPreMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvBspPreMemoryBase), PcdGet32 (PcdFlashFvBspPreMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvBspPreMem= oryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvBspPreMemoryBase), + PcdGet32 (PcdFlashFvBspPreMemorySize), + NULL, + NULL, + 0 + ); + + DEBUG ((DEBUG_INFO, "Install FlashFvPreMemory - 0x%x, 0x%x\n", PcdGet32 = (PcdFlashFvPreMemoryBase), PcdGet32 (PcdFlashFvPreMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvPreMemory= Base))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPreMemoryBase), + PcdGet32 (PcdFlashFvPreMemorySize), + NULL, + NULL, + 0 + ); + + // + // In API mode, do not publish FSP FV. + // + if (!PcdGetBool (PcdFspWrapperBootMode)) { + // + // FvFspT may be required for all stages + // + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (Pc= dFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspTBas= e))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase), + PcdGet32 (PcdFlashFvFspTSize), + NULL, + NULL, + 0 + ); + + // + // FvFspM required for stage 2 and above + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspMB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspMBase), + PcdGet32 (PcdFlashFvFspMSize), + NULL, + NULL, + 0 + ); + } + } + + // + // FvOprom may be required for most stages + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + DEBUG ((DEBUG_INFO, "Install PcdFlashFvOprom - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvOpromBase), PcdGet32 (PcdFlashFvOpromSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvOpromBa= se))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOpromBase), + PcdGet32 (PcdFlashFvOpromSize), + NULL, + NULL, + 0 + ); + } + + // + // FvAdvanced not needed until stage 6 + // + if (PcdGet8 (PcdBootStage) >=3D 6) { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvancedPreMemory - 0x%x, 0x%x\n",= PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), PcdGet32 (PcdFlashFvAdvancedPr= eMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvAdvance= dPreMemoryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), + PcdGet32 (PcdFlashFvAdvancedPreMemorySize), + NULL, + NULL, + 0 + ); + } +} + +VOID +ReportPostMemFv ( + VOID + ) +{ + UINTN Index =3D 0; + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; + + DEBUG_CODE ( + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, &Ppi); + if (!EFI_ERROR (Status)) { + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength)); + } + } + ); + + // + // FvFspS, FvPostMemory, and FvBsp may be required for completing stage 2 + // + if (PcdGet8 (PcdBootStage) >=3D 2) { + // + // In API mode, do not publish FSP FV. + // + if (!PcdGetBool (PcdFspWrapperBootMode)) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvFspSB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspSBase), + PcdGet32 (PcdFlashFvFspSSize), + NULL, + NULL, + 0 + ); + } + + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvPostMem= oryBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase), + PcdGet32 (PcdFlashFvPostMemorySize), + NULL, + NULL, + 0 + ); + + DEBUG ((DEBUG_INFO, "Install FlashFvBsp - 0x%x, 0x%x\n", PcdGet32 (Pcd= FlashFvBspBase), PcdGet32 (PcdFlashFvBspSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvBspBase= ))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvBspBase), + PcdGet32 (PcdFlashFvBspSize), + NULL, + NULL, + 0 + ); + } + + // + // FvUefiBoot required for completing stage 3 + // + if (PcdGet8 (PcdBootStage) >=3D 3) { + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvUefiBoo= tBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase), + PcdGet32 (PcdFlashFvUefiBootSize), + NULL, + NULL, + 0 + ); + } + + // + // FvOsBoot required for completing stage 4 + // + if (PcdGet8 (PcdBootStage) >=3D 4) { + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvOsBootB= ase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase), + PcdGet32 (PcdFlashFvOsBootSize), + NULL, + NULL, + 0 + ); + } + + // + // FvSecurity required for completing stage 5 + // + if (PcdGet8 (PcdBootStage) >=3D 5) { + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvSecurit= yBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase), + PcdGet32 (PcdFlashFvSecuritySize), + NULL, + NULL, + 0 + ); + } + + // + // FvAdvanced required for completing stage 6 + // + if (PcdGet8 (PcdBootStage) >=3D 6) { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) (UINTN) PcdGet32 (PcdFlashFvAdvance= dBase))->FileSystemGuid), + (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase), + PcdGet32 (PcdFlashFvAdvancedSize), + NULL, + NULL, + 0 + ); + } + + // + // Report resource related HOB for flash FV to reserve space in GCD and = memory map + // + + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize) + ); + + BuildMemoryAllocationHob ( + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + EfiMemoryMappedIO + ); +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/= PeiReportFvLib.inf new file mode 100644 index 0000000000..b02fac49cf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.inf @@ -0,0 +1,65 @@ +### @file +# Component information file for the Report Firmware Volume (FV) library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiReportFvLib + FILE_GUID =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D9 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D ReportFvLib + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Sources] + PeiReportFvLib.c + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSU= MES + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase ## CONSU= MES + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset ## CONSU= MES \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aGpioPlatformConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUb= aPlatLib/PeiUbaGpioPlatformConfigLib.c new file mode 100644 index 0000000000..6711de4fad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaGpioPl= atformConfigLib.c @@ -0,0 +1,518 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// UBA and GPIO headers +// +#include +#include + + +/** + +Function gets pointers to the UBA data installed by the right RP package + +@param[out] GpioParams The pointer to the platform GPIO parameters + + +@retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +PlatformGetGpioPlatformMappings ( + IN OUT PLATFORM_GPIO_CONFIG_TABLE *GpioParams + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi (&gUbaConfigDatabasePpiGuid, 0, NULL, &U= baConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + TableSize =3D sizeof(PLATFORM_GPIO_CONFIG_TABLE); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioPlatformConfigDataGuid, + GpioParams, + &TableSize + ); + + return Status; +} + +/** + + Reads GPIO pin to get Flash Security Override jumper status + + @param[out] Jumper - The pointer to the jumper output + + @retval Status - Success if GPIO's are read properly + Jumper - 0x0 if an error happened, otherwise the jumperl value + +**/ +EFI_STATUS +GpioGetFlashSecOvrdVal ( + OUT UINT32 *Jumper + ) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + *Jumper =3D 0x0; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FlashSecOverride =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fl= ashSecOverride, Jumper); + return Status; +} + +/** + + Reads GPIO pin to get recovery jumper status + + @param[out] RcvJumper - The pointer to the Recovery jumper input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetRcvPadVal ( + OUT UINT32 *RcvJumper +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.RcvJumper =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Rc= vJumper, RcvJumper); + return Status; +} + + +/** + + Reads GPIO pin to get FM ADR trigger pin + + @param[out] FmAdrTrigger - The pointer to the ADR trigger input + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetFmAdrTriggerPadVal ( + OUT UINT32 *FmAdrTrigger +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FmAdrTrigger =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fm= AdrTrigger, FmAdrTrigger); + return Status; +} + + +/** + + Sets GPIO pin to enable ADR on the board + + @param Set[in] - If TRUE means the pas should go 'high', otherwise 'lo= w' + + @retval Status - Success if GPIO set properly + +**/ +EFI_STATUS +GpioSetAdrEnablePadOutVal ( + IN BOOLEAN Set +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR(Status)) { + return Status; + } + + if (GpioPlatformConfig.AdrEnable =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + if (Set) { + Status =3D DynamicSiLibraryPpi->GpioSetOutputValue (GpioPlatformConfig= .AdrEnable, GpioOutHigh); + } + else { + Status =3D DynamicSiLibraryPpi->GpioSetOutputValue (GpioPlatformConfig= .AdrEnable, GpioOutLow); + } + return Status; +} + +/** + + Reads GPIO pin to Force to S1 config mode pad + + @param[out] ForceS1ConfigPad - Input value of the Froce S1 Config pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetForcetoS1ConfigModePadVal ( + OUT UINT32 *ForceS1ConfigPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.ForceTo1SConfigModePad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Fo= rceTo1SConfigModePad, ForceS1ConfigPad); + return Status; +} + +/** + + Reads GPIO pin related to QAT + + @param[out] QATPad - Input value of the QAT pad + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetQATPadVal ( + OUT UINT32 *QATPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.QATGpio =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.QA= TGpio, QATPad); + return Status; + +} + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 1 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad1 ( + OUT UINT32 *FpgaErrorPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FpgaErrorSingnalPad1 =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *FpgaErrorPad =3D (UINT32) GpioPlatformConfig.FpgaErrorSingnalPad1; + return EFI_SUCCESS; + +} + + +/** + + Get GPIO pin for FPGA error detection RAS functionality + + @param[out] FpgaErrorPad -The input value of the FPGA error 2 pad + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetFpgaErrorPad2 ( + OUT UINT32 *FpgaErrorPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.FpgaErrorSingnalPad2 =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *FpgaErrorPad =3D (UINT32) GpioPlatformConfig.FpgaErrorSingnalPad2; + return Status; + +} + + +/** + + Get GPIO pin for CPU HP SMI detection for RAS functionality + + @retval Status - Success if GPIO's pad read properly + +**/ +EFI_STATUS +GpioGetCpuHpSmiPad ( + OUT UINT32 *CpuHpSmiPad +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.CpuHpSmiPad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + *CpuHpSmiPad =3D (UINT32) GpioPlatformConfig.CpuHpSmiPad; + return Status; + +} + + +/** + + Reads GPIO pin that is first bit of the Board ID indication word + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId0PadVal ( + OUT UINT32 *BoardID0Gpio +) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.BoardID0Gpio =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Bo= ardID0Gpio, BoardID0Gpio); + return Status; + +} + +/** + + Sets GPIO's used for Boot Mode + + @param None + + @retval Status - Success if GPIO's are configured + +**/ +EFI_STATUS +GpioConfigForMFGMode ( + VOID + ) +{ + EFI_STATUS Status; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + if (GpioPlatformConfig.GpioMfgPad.GpioPad =3D=3D UNUSED_GPIO) { + return EFI_UNSUPPORTED; + } + + DEBUG ((EFI_D_INFO, "Start ConfigureGpio() for BootMode Detection.\n")); + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GpioPlatformConfig.Gpi= oMfgPad.GpioPad, &GpioPlatformConfig.GpioMfgPad.GpioConfig); + + ASSERT_EFI_ERROR (Status); + DEBUG ((EFI_D_INFO, "End ConfigureGpio() for BootMode Detection.\n")); + return Status; +} + +/** + + Checks whether the MDF jumper has been set + + @param None + + @retval ManufacturingMode - TRUE when MFG jumper is on, FALSE otherwise + +**/ +BOOLEAN +IsManufacturingMode ( + VOID +) +{ + + BOOLEAN ManufacturingMode =3D TRUE; + + EFI_STATUS Status; + UINT32 GpiValue; + PLATFORM_GPIO_CONFIG_TABLE GpioPlatformConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + Status =3D PlatformGetGpioPlatformMappings (&GpioPlatformConfig); + ASSERT_EFI_ERROR (Status); + + if (GpioPlatformConfig.GpioMfgPad.GpioPad =3D=3D UNUSED_GPIO) { + return FALSE; + } + + Status =3D GpioConfigForMFGMode (); + ASSERT_EFI_ERROR (Status); + + + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GpioPlatformConfig.Gp= ioMfgPad.GpioPad, &GpiValue); + + ASSERT_EFI_ERROR (Status); + + if (!GpiValue) { + ManufacturingMode =3D FALSE; + } + return ManufacturingMode; + +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aPlatLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Pei= UbaPlatLib.inf new file mode 100644 index 0000000000..5e911ba790 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaPlatLi= b.inf @@ -0,0 +1,60 @@ +## @file +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiUbaPlatLib + FILE_GUID =3D EBD8C6DC-8439-47f1-9B31-91464088F135 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D UbaPlatLib|PEIM PEI_CORE + +[sources] + UbaPchEarlyUpdateLib.c + UbaClkGenUpdateLib.c + UbaGpioUpdateLib.c + UbaPcdUpdateLib.c + UbaSoftStrapUpdateLib.c + UbaIioConfigLibPei.c + UbaSlotUpdateLibPei.c + UbaBoardSioInfoLib.c + UbaClocksConfigLib.c + UbaIioPortBifurcationInitLib.c + UbaPchPcieBifurcationLib.c + UbaHsioPtssTableConfigLib.c + PeiUbaUsbOcUpdateLib.c + PeiUbaGpioPlatformConfigLib.c + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + PeimEntryPoint + PeiServicesTablePointerLib + IoLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## ALWAYS_CONSUMES + +[Depex] + gUbaConfigDatabasePpiGuid AND + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUb= aUsbOcUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/PeiUbaUsbOcUpdateLib.c new file mode 100644 index 0000000000..6dbf9eb7eb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/PeiUbaUsbOcU= pdateLib.c @@ -0,0 +1,61 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetUsbOcMappings ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_USBOC_UPDATE_TABLE UsbOcUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(UsbOcUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &UsbOcUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (UsbOcUpdateTable.Signature =3D=3D PLATFORM_USBOC_UPDATE_SIGNATUR= E); + ASSERT (UsbOcUpdateTable.Version =3D=3D PLATFORM_USBOC_UPDATE_VERSION); + + UsbOcUpdateTable.CallUsbOcUpdate( Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaBo= ardSioInfoLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaBoardSioInfoLib.c new file mode 100644 index 0000000000..86c2a6ff4e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaBoardSioI= nfoLib.c @@ -0,0 +1,54 @@ +/** @file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetBoardSioInfo ( + OUT PEI_BOARD_SIO_INFO *BoardSioInfoData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PEI_BOARD_SIO_INFO); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformBoardSioInfoDataGuid, + BoardSioInfoData, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (BoardSioInfoData -> Signature =3D=3D BOARD_SIO_INFO_DATA_SIGNATU= RE); + ASSERT (BoardSioInfoData -> Version =3D=3D BOARD_SIO_INFO_DATA_VERSION); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaCl= kGenUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaClkGenUpdateLib.c new file mode 100644 index 0000000000..c0eb5df07a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaClkGenUpd= ateLib.c @@ -0,0 +1,134 @@ +/** @file + UbaClkGenUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#define CLOCK_GENERATOR_ADDRESS 0xD2 + +EFI_STATUS +PlatformUpdateClockgen ( + IN BOOLEAN EnableSpreadSpectrum +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_CLOCKGEN_UPDATE_TABLE ClockgenTable; + UINTN TableSize =3D 0; + + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 Buffer[PLATFORM_NUMBER_OF_CLOCKGEN= _DATA]; + UINTN Length =3D 0; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_PEI_SMBUS2_PPI *SmbusPpi =3D NULL; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiSmbus2PpiGuid, + 0, + NULL, + &SmbusPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Read the clock generator + // + SlaveAddress.SmbusDeviceAddress =3D CLOCK_GENERATOR_ADDRESS >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + do { + + TableSize =3D sizeof(ClockgenTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformClockgenConfigDataGuid, + &ClockgenTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (ClockgenTable.Signature =3D=3D PLATFORM_CLOCKGEN_UPDATE_SIGNAT= URE); + ASSERT (ClockgenTable.Version =3D=3D PLATFORM_CLOCKGEN_UPDATE_VERSION); + + if (ClockgenTable.Id !=3D PLATFORM_CLOCKGEN_NO_ID) { + if (ClockgenTable.Id !=3D Buffer[ClockgenTable.IdOffset]) { + continue; + } + } + + if (EnableSpreadSpectrum) { + ClockgenTable.Data[ClockgenTable.SpreadSpectrumByteOffset] =3D Clock= genTable.SpreadSpectrumValue; + } + + // + // Program clock generator + // + Command =3D 0; + Length =3D ClockgenTable.DataLength; + + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusWriteBlock, + FALSE, + &Length, //&ConfigurationTableLength, + &ClockgenTable.Data //ConfigurationTable + ); + if (EFI_ERROR(Status)) { + return Status; + } else { + break; + } + }while (!EFI_ERROR(Status)); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaCl= ocksConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaClocksConfigLib.c new file mode 100644 index 0000000000..dd7873522c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaClocksCon= figLib.c @@ -0,0 +1,59 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +ConfigurePlatformClock ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_CLOCKS_CONFIG_TABLE PlatformClocksConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PlatformClocksConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformClocksConfigDataGuid, + &PlatformClocksConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PlatformClocksConfigTable.Signature =3D=3D PLATFORM_CLOCKS_CONFI= G_SIGNATURE); + ASSERT (PlatformClocksConfigTable.Version =3D=3D PLATFORM_CLOCKS_CONFIG_= VERSION); + + Status =3D PlatformClocksConfigTable.CallUpdate(PeiServices, NotifyDescr= iptor, SmbusPpi); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaGp= ioUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Ub= aGpioUpdateLib.c new file mode 100644 index 0000000000..164302ba7b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaGpioUpdat= eLib.c @@ -0,0 +1,68 @@ +/** @file + UbaGpioUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +PlatformUpdateGpios ( + VOID +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_GPIO_UPDATE_TABLE GpioTable; + UINTN TableSize; + UINTN Index; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(GpioTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioConfigDataGuid, + &GpioTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (GpioTable.Signature =3D=3D PLATFORM_GPIO_UPDATE_SIGNATURE); + ASSERT (GpioTable.Version =3D=3D PLATFORM_GPIO_UPDATE_VERSION); + + for (Index =3D 0; GpioTable.Gpios[Index].Register !=3D PLATFORM_END_OF_G= PIO_LIST; Index++) { + + IoWrite32 (GpioTable.Gpios[Index].Register, GpioTable.Gpios[Index].Val= ue); + } + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaHs= ioPtssTableConfigLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaP= latLib/UbaHsioPtssTableConfigLib.c new file mode 100644 index 0000000000..35f67a013a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaHsioPtssT= ableConfigLib.c @@ -0,0 +1,58 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +InstallPlatformHsioPtssTable ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy + +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_HSIO_PTSS_CONFIG_TABLE PlatformHsioPtssConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PlatformHsioPtssConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformHsioPtssTableGuid, + &PlatformHsioPtssConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PlatformHsioPtssConfigTable.Signature =3D=3D PLATFORM_HSIO_PTSS_= TABLE_SIGNATURE); + ASSERT (PlatformHsioPtssConfigTable.Version =3D=3D PLATFORM_HSIO_PTSS_TA= BLE_VERSION); + + PlatformHsioPtssConfigTable.CallUpdate( PchSetup, PchPolicy ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIi= oConfigLibPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/= UbaIioConfigLibPei.c new file mode 100644 index 0000000000..e4ac30a962 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIioConfig= LibPei.c @@ -0,0 +1,219 @@ +/** @file + PeiUbaIioConfigLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformIioConfigInit ( + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + *BifurcationTable =3D IioConfigTable.IioBifurcationTablePtr; + *BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize/= sizeof(IIO_BIFURCATION_DATA_ENTRY)); + + *SlotTable =3D IioConfigTable.IioSlotTablePtr; + *SlotEntries =3D (UINT8)(IioConfigTable.IioSlotTableSize/sizeof(IIO_SLOT= _CONFIG_DATA_ENTRY)); + + return Status; +} + +EFI_STATUS +PlatformIioConfigInit2 ( + IN UINT8 SkuPersonalityType, + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + if (SkuPersonalityType =3D=3D 1) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 2) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 3) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + &IioConfigTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + *BifurcationTable =3D IioConfigTable.IioBifurcationTablePtr; + *BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize/= sizeof(IIO_BIFURCATION_DATA_ENTRY)); + + *SlotTable =3D IioConfigTable.IioSlotTablePtr; + *SlotEntries =3D (UINT8)(IioConfigTable.IioSlotTableSize/sizeof(IIO_SLOT= _CONFIG_DATA_ENTRY)); + + return Status; +} + +EFI_STATUS +PlatformUpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + Status =3D IioConfigTable.CallUpdate (IioGlobalData); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +EFI_STATUS +PlatformUpdateIioConfig_EX ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + + Status =3D IioConfigTable.CallUpdate (IioGlobalData); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIi= oPortBifurcationInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiU= baPlatLib/UbaIioPortBifurcationInitLib.c new file mode 100644 index 0000000000..41416adef1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaIioPortBi= furcationInitLib.c @@ -0,0 +1,55 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +IioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + IIO_PORT_BIFURCATION_INIT_TABLE IioPortBifurcationInitTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioPortBifurcationInitTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gIioPortBifurcationInitDataGuid, + &IioPortBifurcationInitTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioPortBifurcationInitTable.Signature =3D=3D IIO_PORT_BIFURCATIO= N_INIT_SIGNATURE); + ASSERT (IioPortBifurcationInitTable.Version =3D=3D IIO_PORT_BIFURCATION_= INIT_VERSION); + + IioPortBifurcationInitTable.CallUpdate(IioGlobalData); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= dUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/Uba= PcdUpdateLib.c new file mode 100644 index 0000000000..ce822faa2d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPcdUpdate= Lib.c @@ -0,0 +1,69 @@ +/** @file + UbaPcdUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + Function updates Platform Configuration Data (PCD) in Unified Board Abst= raction (UBA) + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS PCDs successfuly intialized + @return EFI_ERROR An error ocurs during PCDs initialization + +**/ +EFI_STATUS +PlatformUpdatePcds ( + VOID + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCD_UPDATE_TABLE PcdUpdateTable; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Size =3D sizeof(PcdUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &PcdUpdateTable, + &Size + ); + if (EFI_ERROR (Status)) { + return Status; + } + + ASSERT (PcdUpdateTable.Signature =3D=3D PLATFORM_PCD_UPDATE_SIGNATURE); + ASSERT (PcdUpdateTable.Version =3D=3D PLATFORM_PCD_UPDATE_VERSION); + + Status =3D PcdUpdateTable.CallUpdate (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= hEarlyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLi= b/UbaPchEarlyUpdateLib.c new file mode 100644 index 0000000000..dc7a044729 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPchEarlyU= pdateLib.c @@ -0,0 +1,108 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +PlatformPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_EARLY_UPDATE_TABLE PchEarlyUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PchEarlyUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &PchEarlyUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchEarlyUpdateTable.Signature =3D=3D PLATFORM_PCH_EARLY_UPDATE_S= IGNATURE); + ASSERT (PchEarlyUpdateTable.Version =3D=3D PLATFORM_PCH_EARLY_UPDATE_VER= SION); + + Status =3D PchEarlyUpdateTable.ConfigLan (SystemConfig); + + return Status; +} + +EFI_STATUS +PlatformInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_EARLY_UPDATE_TABLE PchEarlyUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(PchEarlyUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &PchEarlyUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchEarlyUpdateTable.Signature =3D=3D PLATFORM_PCH_EARLY_UPDATE_S= IGNATURE); + ASSERT (PchEarlyUpdateTable.Version =3D=3D PLATFORM_PCH_EARLY_UPDATE_VER= SION); + + if (PchEarlyUpdateTable.InitLateHook =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + Status =3D PchEarlyUpdateTable.InitLateHook (SystemConfig); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPc= hPcieBifurcationLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPl= atLib/UbaPchPcieBifurcationLib.c new file mode 100644 index 0000000000..53c913aa54 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaPchPcieBi= furcationLib.c @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetPchPcieBifurcationConfig ( + IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig, + IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE BifurcationUpdateTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(BifurcationUpdateTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformUbaPcieBifurcationGuid, + &BifurcationUpdateTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (BifurcationUpdateTable.Signature =3D=3D PLATFORM_PCH_PCIE_BIFURC= ATION_UPDATE_SIGNATURE); + ASSERT (BifurcationUpdateTable.Version =3D=3D PLATFORM_PCH_PCIE_BIFURCAT= ION_UPDATE_VERSION); + + BifurcationUpdateTable.CallPcieBifurcationUpdate(PchPcieBifurcationConfi= g, PchSlotConfig); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSl= otUpdateLibPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib= /UbaSlotUpdateLibPei.c new file mode 100644 index 0000000000..55ada7b3aa --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSlotUpdat= eLibPei.c @@ -0,0 +1,156 @@ +/** @file + UbaSlotUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +PlatformGetSlotTableData ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU2Setting, + IN OUT UINT8 *FlagValue +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_SLOT_UPDATE_TABLE IioSlotTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioSlotTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &IioSlotTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioSlotTable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (IioSlotTable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *BroadwayTable =3D IioSlotTable.BroadwayTablePtr; + *IOU2Setting =3D IioSlotTable.GetIOU2Setting (*IOU2Setting); + *FlagValue =3D IioSlotTable.FlagValue; + + return Status; +} + +EFI_STATUS +PlatformGetSlotTableData2 ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU0Setting, + IN OUT UINT8 *FlagValue, + IN OUT UINT8 *IOU2Setting, + IN UINT8 SkuPersonalityType +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_SLOT_UPDATE_TABLE2 IioSlotTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(IioSlotTable); + if ((SkuPersonalityType =3D=3D 1) || (SkuPersonalityType =3D=3D 3)) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2_1, + &IioSlotTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &IioSlotTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioSlotTable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (IioSlotTable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *BroadwayTable =3D IioSlotTable.BroadwayTablePtr; + *IOU0Setting =3D IioSlotTable.GetIOU0Setting (*IOU0Setting); + *FlagValue =3D IioSlotTable.FlagValue; + *IOU2Setting =3D IioSlotTable.GetIOU2Setting (SkuPersonalityType, *IOU= 2Setting); + + return Status; +} + +EFI_STATUS +PlatformPchGetPciSlotImplementedTableData ( + IN OUT UINT8 **SlotImplementedTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE SITable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + (VOID **)&UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + TableSize =3D sizeof(SITable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &SITable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (SITable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (SITable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *SlotImplementedTable =3D SITable.SlotImplementedTableDataPtr; + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSo= ftStrapUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatL= ib/UbaSoftStrapUpdateLib.c new file mode 100644 index 0000000000..a4042d2b37 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PeiUbaPlatLib/UbaSoftStrap= UpdateLib.c @@ -0,0 +1,95 @@ +/** @file + UbaSoftStrapUpdateLib implementation. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +EFI_STATUS +GetPchSoftSoftStrapTable ( + IN VOID **PchSoftStrapTable + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_SOFTSTRAP_UPDATE PchSoftStrapUpdate; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Size =3D sizeof(PchSoftStrapUpdate); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &PchSoftStrapUpdate, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (PchSoftStrapUpdate.Signature =3D=3D PLATFORM_SOFT_STRAP_UPDATE_S= IGNATURE); + ASSERT (PchSoftStrapUpdate.Version =3D=3D PLATFORM_SOFT_STRAP_UPDATE_VER= SION); + + *PchSoftStrapTable =3D PchSoftStrapUpdate.PchSoftStrapTablePtr; + + return Status; +} + +VOID +PlatformSpecificPchSoftStrapUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_PCH_SOFTSTRAP_UPDATE PchSoftStrapUpdate; + UINTN Size; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return; + } + + Size =3D sizeof(PchSoftStrapUpdate); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &PchSoftStrapUpdate, + &Size + ); + if (EFI_ERROR(Status)) { + return; + } + + ASSERT (PchSoftStrapUpdate.Signature =3D=3D PLATFORM_SOFT_STRAP_UPDATE_S= IGNATURE); + ASSERT (PchSoftStrapUpdate.Version =3D=3D PLATFORM_SOFT_STRAP_UPDATE_VER= SION); + + PchSoftStrapUpdate.PchSoftStrapPlatformSpecificUpdate (FlashDescriptorCo= py); +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/P= ei/PlatformClocksLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Platfor= mClocksLib/Pei/PlatformClocksLib.c new file mode 100644 index 0000000000..3cd48be906 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/Pei/Plat= formClocksLib.c @@ -0,0 +1,347 @@ +/** @file + Platform Clocks Lib file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SMBUS_RETRIES 10 + + +EFI_STATUS +ConfigureClockGeneratorOnSecondarySmbus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_SMBUS2_PPI *SmbusPpi, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN OUT UINT8 *ConfigurationTable + ); + +/** + + Configure the clock generator using the SMBUS PPI services. + + This function performs a block write, and dumps debug information. + + @param PeiServices - General purpose services available to= every PEIM. + @param ClockType - Clock generator's model name. + @param ClockAddress - SMBUS address of clock generator. + @param ConfigurationTableLength - Length of configuration table. + @param ConfigurationTable - Pointer of configuration table. + + @retval EFI_SUCCESS - Operation success. + +**/ +EFI_STATUS +ConfigureClockGenerator ( + IN EFI_PEI_SERVICES **PeiServices, + IN CLOCK_GENERATOR_TYPE ClockType, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN OUT UINT8 *ConfigurationTable, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN UINT8 SecondarySmbus + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH= ]; + UINTN Length; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_PEI_SMBUS2_PPI *SmbusPpi; + UINT8 SmbErrorsCounter; + + // + // Locate SmBus Ppi + // + Status =3D (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiSmbus2PpiGuid, + 0, + NULL, + &SmbusPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Verify input arguments + // + ASSERT (ConfigurationTableLength >=3D 8); + ASSERT (ConfigurationTableLength <=3D MAX_CLOCK_GENERATOR_BUFFER_LENGTH); + ASSERT (ClockType < ClockGeneratorMax); + ASSERT (ConfigurationTable !=3D NULL); + + // + // Init some local vars + // + SlaveAddress.SmbusDeviceAddress =3D ClockAddress >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + + if (SecondarySmbus =3D=3D TRUE) { + + return (ConfigureClockGeneratorOnSecondarySmbus(PeiServices, + SmbusPpi, + ClockAddress, + ConfigurationTableLength, + EnableSpreadSpectrum, + mSupportedClockGeneratorT, + ConfigurationTable + )); + } else { + // + // Not LightningRidge + // Read the clock generator on the primary SMBus + // + + SmbErrorsCounter =3D 0; + + do + { + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + if(Status !=3D EFI_SUCCESS) + { + DEBUG ((EFI_D_ERROR, "SMBUS reading error\n")); + + } + + SmbErrorsCounter ++; + } + while ((Status !=3D EFI_SUCCESS) && (SmbErrorsCounter < MAX_SMBUS_RETR= IES)); + + // + // Sanity check that the requested clock type is present in our suppor= ted clocks table + // + DEBUG ((DEBUG_INFO, "Expected Clock Generator ID is %x, populated %x\n= ", mSupportedClockGeneratorT->ClockId, Buffer[7])); + + if (EnableSpreadSpectrum) { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] |=3D mSu= pportedClockGeneratorT->SpreadSpectrumBitOffset; + + if (ClockType =3D=3D ClockGeneratorCk420) { + + // Ensure that the clock chip is operating in normal mode. + // + Buffer[10] &=3D ~BIT7; + } + } else { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] &=3D ~(m= SupportedClockGeneratorT->SpreadSpectrumBitOffset); + } + +#ifdef EFI_DEBUG + { + UINT8 i; + DEBUG ((DEBUG_INFO, "SlaveAddress.SmbusDeviceAddress %x: Size =3D%x\= n", SlaveAddress.SmbusDeviceAddress, Length)); + for (i =3D 0; i < ConfigurationTableLength; i++) { + DEBUG ((DEBUG_INFO, "Default Clock Generator Byte %d: %x\n", i, Bu= ffer[i])); + } + } +#endif + + // + // Program clock generator, using the platform default values + // + + SmbErrorsCounter =3D 0; + do + { + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusWriteBlock, + FALSE, + &Length, // &ConfigurationTableLength, + Buffer //ConfigurationTable + ); + // ASSERT_EFI_ERROR (Status); + + + if(Status !=3D EFI_SUCCESS) + { + DEBUG ((EFI_D_ERROR, "SMBUS writing error\n")); + } + + SmbErrorsCounter ++; + } + while ((Status !=3D EFI_SUCCESS) && (SmbErrorsCounter < MAX_SMBUS_RETRI= ES)); + + // + // Dump contents after write + // +#ifdef EFI_DEBUG + { + UINT8 i; + SlaveAddress.SmbusDeviceAddress =3D ClockAddress >> 1; + Length =3D sizeof (Buffer); + Command =3D 0; + Status =3D SmbusPpi->Execute ( + SmbusPpi, + SlaveAddress, + Command, + EfiSmbusReadBlock, + FALSE, + &Length, + Buffer + ); + + for (i =3D 0; i < ConfigurationTableLength; i++) { + DEBUG ((DEBUG_INFO, "Clock Generator Byte %d: %x\n", i, Buffer[i])= ); + } + } +#endif + + return EFI_SUCCESS; + } // else () +} + + +/** + + Configure clock generator on Kahuna + Clock gen is on a secondary SMBus + + @param IN EFI_PEI_SERVICES **PeiServices - Pointer to PEI Servic= es table + @param IN EFI_PEI_SMBUS2_PPI *SmbusPpi - Pointer to SMBUs services= PPI + @param IN UINT8 ClockAddress - SMBus address of clock= gen + @param IN UINT8 *Buffer - Pointer to buffer containin= g byte stream to send to clock gen + @param IN UINTN Length - Number of bytes in buffer + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The function cannot continue due to le= ngth is out of bound. + +**/ +EFI_STATUS +ConfigureClockGeneratorOnSecondarySmbus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_SMBUS2_PPI *SmbusPpi, + IN UINT8 ClockAddress, + IN UINTN ConfigurationTableLength, + IN BOOLEAN EnableSpreadSpectrum, + IN CLOCK_GENERATOR_DETAILS *mSupportedClockGeneratorT, + IN OUT UINT8 *ConfigurationTable + ) +{ + EFI_PEI_STALL_PPI *StallPpi; + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_SMBUS_DEVICE_COMMAND SmbusCommand; + UINTN SmbusLength; + UINT8 SmbusData[MAX_CLOCK_GENERATOR_BUFFER_LENGTH]; + UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH]; + UINT8 Length; + + ZeroMem (Buffer, sizeof(Buffer)); + + if (ConfigurationTableLength > MAX_CLOCK_GENERATOR_BUFFER_LENGTH) { + return EFI_INVALID_PARAMETER; + } + + // + // Locate Stall PPI + // + Status =3D (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiStallPpiGuid, + 0, + NULL, + &StallPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Get length of payload to send to clock gen + // + Length =3D (UINT8) ConfigurationTableLength; + + // + // Copy the default clock generator data into Buffer + // + CopyMem ((VOID*)Buffer, ConfigurationTable, Length); + + // + // Set spread spectrum bit in Buffer or clear it? + // + if (EnableSpreadSpectrum) { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] |=3D mSupp= ortedClockGeneratorT->SpreadSpectrumBitOffset; + + if (mSupportedClockGeneratorT->ClockType =3D=3D ClockGeneratorCk420) { + + // + // Ensure that the clock chip is operating in normal mode. + // + Buffer[10] &=3D ~BIT7; + } + } else { + Buffer[mSupportedClockGeneratorT->SpreadSpectrumByteOffset] &=3D ~(mSu= pportedClockGeneratorT->SpreadSpectrumBitOffset); + } + + // + // Now encapsulate the data for a Write Block command to the clock gen + // as the payload in a Write Block command to the SMBus bridge + // + // Segment address =3D 0xF2, this becomes slave address + // Slave address (clock gen) =3D ClockAddress, this becomes slave command + // + SlaveAddress.SmbusDeviceAddress =3D (0xF2 >> 1); + SmbusCommand =3D ClockAddress; + + // + // Set byte index in clock gen to start with, always 0 + // + SmbusData[0] =3D 0; + + // + // Set byte count clock gen wants to see + // + SmbusData[1] =3D (UINT8) Length; + + // + // Payload byte count for SMBus bridge + // + SmbusLength =3D Length + 2; + if (SmbusLength > MAX_CLOCK_GENERATOR_BUFFER_LENGTH) { + return EFI_INVALID_PARAMETER; + } + + // + // Copy the clock gen data to the SMBus buffer + // + CopyMem ((VOID *)(((UINT8*)SmbusData) + 2), (VOID *)Buffer, Length); + + // + // Use EfiSmbusWriteBlock to communicate with clock gen + // + Status =3D SmbusPpi->Execute( SmbusPpi, + SlaveAddress, + SmbusCommand, + EfiSmbusWriteBlock, + FALSE, + &SmbusLength, + &SmbusData ); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/P= ei/PlatformClocksLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Platf= ormClocksLib/Pei/PlatformClocksLib.inf new file mode 100644 index 0000000000..cbb5d53d98 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformClocksLib/Pei/Plat= formClocksLib.inf @@ -0,0 +1,40 @@ +## @file +# +# @copyright +# Copyright 2013 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformClocksLib + FILE_GUID =3D 09C4033A-CCD5-45BE-8846-BC7E4536489D + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformClocksLib | PEIM + +[Sources] + PlatformClocksLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib + HobLib + +[Protocols] + +[Guids] + +[Ppis] + gEfiPeiSmbus2PpiGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessL= ib/PlatformCmosAccessLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Pla= tformCmosAccessLib/PlatformCmosAccessLib.c new file mode 100644 index 0000000000..2169b3fadd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessLib/Plat= formCmosAccessLib.c @@ -0,0 +1,73 @@ +/** @file + Platform CMOS Access Library. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Return the platform CMOS entries. + + @param [out] EnryCount Number of platform CMOS entries. + + @return Platform CMOS entries. +**/ +CMOS_ENTRY * +EFIAPI +PlatformCmosGetEntry ( + OUT UINTN *EntryCount + ) +{ + + *EntryCount =3D 0; + return NULL; +} + + +/** + Return the NMI enable status. +**/ + +BOOLEAN +EFIAPI +PlatformCmosGetNmiState ( + VOID + ) +{ + volatile UINT32 Data32; + BOOLEAN Nmi; + Data32 =3D 0; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return FALSE; + } + + // + // Preserve NMI bit setting + // + + if ((DynamicSiLibraryPpi->ReadNmiEn ())& B_PCH_IO_NMI_EN_NMI_EN) { + Nmi =3D TRUE; + } + else + Nmi =3D FALSE; + + return Nmi; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessL= ib/PlatformCmosAccessLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/P= latformCmosAccessLib/PlatformCmosAccessLib.inf new file mode 100644 index 0000000000..c3d7532409 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformCmosAccessLib/Plat= formCmosAccessLib.inf @@ -0,0 +1,45 @@ +## @file +# Library producing CMOS access functionalities are relevant to platform. +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformCmosAccessLib + FILE_GUID =3D f4d9e039-d8c9-4981-a504-7e91715efbc5 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformCmosAccessLib | PEIM + +[Sources] + PlatformCmosAccessLib.c + +[LibraryClasses] + DebugLib + IoLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + BoardModulePkg/BoardModulePkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/Pl= atformHooks.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib= /PlatformHooks.c new file mode 100644 index 0000000000..fa695358bf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/PlatformH= ooks.c @@ -0,0 +1,203 @@ +/** @file + Platform Hooks file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +UINT8 +IsSimPlatform (VOID) +{ + return 0; +} + +/** + + Read Aspeed AHB register. + + @param RegIndex: register index of Aspeed. + + @retval value of register. + +**/ +UINT32 +ReadAHBDword ( + UINT32 RegIndex + ) +{ + UINT8 bValue; + UINT32 rdValue =3D 0; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, ASPEED2500_SIO_SMI); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0x30); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, 1); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf8); + bValue =3D IoRead8(ASPEED2500_SIO_DATA_PORT); + bValue &=3D 0xfc; + bValue |=3D 2; // 4 byte window. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, bValue); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf0); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf1); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf2); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf3); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (ASPEED2500_SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); + + // trigger read + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xfe); + IoRead8 (ASPEED2500_SIO_DATA_PORT); + + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf4); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf5); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf6); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + rdValue <<=3D 8; + + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, 0xf7); + rdValue +=3D IoRead8 (ASPEED2500_SIO_DATA_PORT); + + + return rdValue; + +} + +/** + * Checks for the presence of ASPEED SIO + * @return TRUE if its present. FALSE if not. + */ +BOOLEAN +IsAspeedPresent ( + VOID + ) +{ + BOOLEAN PresenceStatus =3D FALSE; + UINT32 DeviceID; + + // + //ASPEED AST2500/AST2600 + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (ASPEED2500_SIO_DATA_PORT, ASPEED2500_SIO_UART1); + if (IoRead8 (ASPEED2500_SIO_DATA_PORT) =3D=3D ASPEED2500_SIO_UART1) { + // + //right now, maybe it is ASPEED. to detect the device ID. + // + DeviceID =3D ReadAHBDword (SCU7C); + // + //There is a Aspeed card need to support as well. it's type is AST2500 A= 1 EVB. + // + //AST2300-A0 0x01000003 + //AST2300-A1 0x01010303 + //AST1300-A1 0x01010003 + //AST1050-A1 0x01010203 + //AST2400-A0 0x02000303 + //AST2400-A1 0x02010303 + //AST1400-A1 0x02010103 + //AST1250-A1 0x02010303 + //AST2500-A0 0x04000303 + //AST2510-A0 0x04000103 + //AST2520-A0 0x04000203 + //AST2530-A0 0x04000403 + //AST2500-A1 0x04010303 + //AST2510-A1 0x04010103 + //AST2520-A1 0x04010203 + //AST2530-A1 0x04010403 + // + if ((DeviceID & 0xff0000ff) =3D=3D 0x04000003) { + PresenceStatus =3D TRUE; + } + } + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_LOCK); + return PresenceStatus; +} + +/** + * Checks for the presence of Nuvoton SIO + * @return TRUE if its present. FALSE if not. + */ +BOOLEAN +IsNuvotonPresent ( + VOID + ) +{ + BOOLEAN PresenceStatus =3D FALSE; + + // + // Nuvoton NCT5104D + // + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_ENTER_THE_EXTENDED_FUNCTION_= MODE); + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_ENTER_THE_EXTENDED_FUNCTION_= MODE); + IoWrite8 (NCT5104D_SIO_INDEX_PORT, NCT5104D_CHIP_ID_REG); + if (IoRead8 (NCT5104D_SIO_DATA_PORT) =3D=3D NCT5104D_CHIP_ID) { + PresenceStatus =3D TRUE; + } + return PresenceStatus; +} + +/** + * Checks for the presence of the following SIO: + * -ASPEED AST2500 + * -Nuvoton NCT5104D + * + * @return An UINT32 with the corresponding bit set for each SIO. + * -ASPEED_EXIST BIT4 + * -NCT5104D_EXIST BIT3 + * -PC8374_EXIST BIT1 + * -PILOTIV_EXIST BIT0 + */ +UINT32 +IsSioExist ( + VOID + ) +{ + UINT32 SioExit =3D 0; + + if (IsAspeedPresent ()) { + SioExit |=3D ASPEED_EXIST; + } + + if (IsNuvotonPresent ()) { + SioExit |=3D NCT5104D_EXIST; + } + + DEBUG((DEBUG_INFO, "[SIO] Current system SIO exist bit:%x \n", SioExit)); + + return SioExit; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/Pl= atformHooksLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHoo= ksLib/PlatformHooksLib.inf new file mode 100644 index 0000000000..c1b18c4511 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformHooksLib/PlatformH= ooksLib.inf @@ -0,0 +1,28 @@ +## @file +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformHooksLib + FILE_GUID =3D 44497B44-55D0-48b2-8BF8-DDC633C52BF6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformHooksLib + +[Sources] + PlatformHooks.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PciLib + BaseLib + PciSegmentLib + BaseMemoryLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicy= LibNull/PlatformOpromPolicyLibNull.c b/Platform/Intel/WhitleyOpenBoardPkg/L= ibrary/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.c new file mode 100644 index 0000000000..fc466c1bda --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicyLibNull= /PlatformOpromPolicyLibNull.c @@ -0,0 +1,88 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Decide if BIOS embdded option roms should be loaded for a certain PCI de= vice. + + @param PciIo PCI device to return the ROM image for. + + @retval TRUE BIOS embedded option roms should not be run for the P= CI device. + @retval FALSE BIOS embedded option roms could be run for the PCI de= vice. +**/ + +BOOLEAN +PlatformOpromLoadDevicePolicy ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + return TRUE; +} + +/** + For devices that support multiple option roms like FCoE, PXE, iSCSI etc.= , this function decides if one of these BIOS embdded option roms should be = loaded for a certain PCI device based on platform choices. + + @param PciHandle PCI device to return the ROM image for. + @param TableIndex The index pointing to the option rom in the platf= orm option rom table for the PCI device. + + @retval FALSE The specific BIOS embedded option rom should not = be run for the PCI device. + @retval TRUE The specific BIOS embedded option rom could be ru= n for a certain PCI device. +**/ + +OPROM_LOAD_POLICY +PlatformOpromLoadTypePolicy ( + IN EFI_HANDLE PciHandle, + IN UINTN TableIndex + ) +{ + return INCLUSIVE_LOAD; +} + +/** + Decide if a PCIe device option rom should be dispacthed. + + @param PciHandle PCI device handle. + + @retval FALSE The specific PCIe option rom should not be dispat= ched for the PCI device. + @retval TRUE The specific PCIe option rom could be dispatched = for a certain PCI device. + +**/ + +BOOLEAN +PlatformOpromDispatchPolicy ( + IN EFI_HANDLE DeviceHandle +) +{ + return TRUE; +} + + +/** + Enable the legacy console redirection before dispatch the legacy ORPOM o= r disable the legacy console redirection after dispatch + the legacy ORPOM based on setup option and SOL status. + + @param Mode Subfunction. + @param CheckIsAhciRom If the device is legacy Ahci device. + + @retval + +**/ + +VOID +PlatformOpromLegacyCRPolicy ( + IN UINTN Mode, + IN BOOLEAN CheckIsAhciRom +) +{ + + return; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicy= LibNull/PlatformOpromPolicyLibNull.inf b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf new file mode 100644 index 0000000000..7b2f88cb32 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformOpromPolicyLibNull= /PlatformOpromPolicyLibNull.inf @@ -0,0 +1,29 @@ +## @file +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformOpromPolicyLib + FILE_GUID =3D 9FFE7727-A322-4957-BC66-76E25D85A069 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformOpromPolicyLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + PlatformOpromPolicyLibNull.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + DebugLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariab= leSyncLibNull/PlatformSetupVariableSyncLibNull.c b/Platform/Intel/WhitleyOp= enBoardPkg/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSy= ncLibNull.c new file mode 100644 index 0000000000..abe4f2872e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariableSyncL= ibNull/PlatformSetupVariableSyncLibNull.c @@ -0,0 +1,81 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + + +/*++ + Description: + + This function will parse the variable hob and find three vairables: + RP variable + PC common variable + PC generation variable + This is used to sync Pc variable to RP variable value + + Arguments: + PeiServices - PeiServices + Header - VARIABLE_STORE_HEADER + CreateHobDataForRpDefaults - will create a hob for RP defaults, + this is used in normal post case, + cannot be used in specicfic hob event + + + Returns: + + EFI_SUCCESS - Sync to RP variable Success + Other -Sync to RP variable Failure + + + --*/ + +EFI_STATUS SyncSetupVariable ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID* Header, + IN BOOLEAN CreateHobDataForRpDefaults +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + + + return Status; + +} + + + +/*++ +Description: + + This function finds the matched default data and create GUID hob only fo= r RP variable . + This is used to sync Pc variable to RP variable value + +Arguments: + + DefaultId - Specifies the type of defaults to retrieve. + BoardId - Specifies the platform board of defaults to retrieve. + +Returns: + + EFI_SUCCESS - The matched default data is found. + EFI_NOT_FOUND - The matched default data is not found. + EFI_OUT_OF_RESOURCES - No enough resource to create HOB. + +--*/ + +EFI_STATUS +CreateRPVariableHob ( + IN UINT16 DefaultId, + IN UINT16 BoardId + ){ + EFI_STATUS Status =3D EFI_SUCCESS; + + return Status; + + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariab= leSyncLibNull/PlatformSetupVariableSyncLibNull.inf b/Platform/Intel/Whitley= OpenBoardPkg/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariable= SyncLibNull.inf new file mode 100644 index 0000000000..a65305b1ea --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformSetupVariableSyncL= ibNull/PlatformSetupVariableSyncLibNull.inf @@ -0,0 +1,28 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformSetupVariableSyncLibNull + FILE_GUID =3D 260C4506-F632-4210-ABB8-6951C2D27AD1 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSetupVariableSyncLibNull|PEIM= PEI_CORE + +[Sources] + PlatformSetupVariableSyncLibNull.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + HobLib + PeiServicesTablePointerLib + PeiServicesLib diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHoo= kLibNull/PlatformVariableHookLibNull.c b/Platform/Intel/WhitleyOpenBoardPkg= /Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.c new file mode 100644 index 0000000000..dd1ec54051 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHookLibNul= l/PlatformVariableHookLibNull.c @@ -0,0 +1,55 @@ +/** @file + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + + + + +/*++ +Description: + + This function is a hook for PlatformVariableInitPeiEntry + +--*/ +VOID PlatformVariableHookForEntry( + VOID +){ + + +} + + +/*++ +Description: + + This function allow platform to generate variable hob base on different = event. + +Arguments: + IN VOID *Interface -point to EFI_PEI_READ_ONLY_VARIABL= E2_PPI + IN OUT UINT8 *phobdata, -pont to hob data + IN OUT UINT16 *pDefaultId -pointer to defautlID + +Returns: + TRUE:platform have its own variable hob that need be createn + FALSE:platform don;t need to create variable hob in this case + + +--*/ +BOOLEAN PlatformVariableHookForHobGeneration( + IN VOID *Interface, + IN OUT UINT8 *phobdata, + IN OUT UINT16 *pDefaultId +){ + + + + return FALSE; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHoo= kLibNull/PlatformVariableHookLibNull.inf b/Platform/Intel/WhitleyOpenBoardP= kg/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf new file mode 100644 index 0000000000..0b2c5ca795 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/PlatformVariableHookLibNul= l/PlatformVariableHookLibNull.inf @@ -0,0 +1,24 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVariableHookLibNull + FILE_GUID =3D 8DAB8601-7FE8-4a1d-A314-09F7D3789C5A + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformVariableHookLibNull +[sources] + PlatformVariableHookLibNull.c + +[LibraryClasses] + BaseLib + IoLib + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsL= ib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.c new file mode 100644 index 0000000000..d12c253846 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.c @@ -0,0 +1,446 @@ +/** @file + Read FFS Library + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// +//EFI_FIRMWARE_FILE_SYSTEM3_GUID indicates support for FFS_ATTRIB_LARGE_SI= ZE +//And thus support for files 16MB or larger. +// +UINT8 * +PreMemReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN BOOLEAN skipheader + ) +/*++ + +Routine Description: + + Read FFS file from specified FV in PreMem phase + +Arguments: + + FwVolHeader - FV Base Address + + FFSGuid - FFS to find & Read + + FFSDataSize - Data size to read.If this value equal 0, will read the w= hole FFS size + + skipheader - TRUE: skip to read the ffs and first section header,read= from data directly, for one data section only ffs + FALSE:read from header + +Returns: + + None + +--*/ +{ + EFI_FFS_FILE_HEADER *ffsHdr; + UINT64 FvSize; + UINT32 FileOccupiedSize; + UINT32 FFSDataOffset; + EFI_FIRMWARE_VOLUME_EXT_HEADER *FwVolExtHeader; + UINT32 FFSSize =3D 0; + + FvSize =3D 0; + FFSDataOffset =3D 0; + if (FwVolHeader->ExtHeaderOffset !=3D 0) { + // + // Searching for files starts on an 8 byte aligned boundary after the = end of the Extended Header if it exists. + // + FwVolExtHeader =3D (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINTN)FwVolHea= der + FwVolHeader->ExtHeaderOffset ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ((UINT8 *) FwVolExtHeader + FwVolEx= tHeader->ExtHeaderSize); + } else { + ffsHdr =3D (EFI_FFS_FILE_HEADER*)(((UINT8 *) FwVolHeader)+ FwVolHeade= r->HeaderLength); + } + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + + if(FwVolHeader->FvLength =3D=3D 0xFFFFFFFFFFFFFFFF) return NULL; + + FvSize =3D (UINTN)ffsHdr-(UINTN)FwVolHeader; + while((FvSize < FwVolHeader->FvLength)&&((UINTN)ffsHdr <((UINTN)FwVolHea= der+ (UINTN)FwVolHeader->FvLength))){ + if(CompareGuid (&ffsHdr->Name, &FFSGuid)) break; + + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + + FvSize+=3D FileOccupiedSize; + ffsHdr =3D (EFI_FFS_FILE_HEADER *)((UINT8 *)ffsHdr + FileOccupiedSize= ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + } + + if (FvSize < FwVolHeader->FvLength) { + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + FFSSize =3D FileOccupiedSize; + + if(FFSDataSize =3D=3D 0) + FFSDataSize=3D FFSSize; + + if(skipheader){ + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER2) + sizeof(EFI_COMMON= _SECTION_HEADER2); + } else { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_= SECTION_HEADER); + } + if(FFSDataSize =3D=3D 0) { + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER2) - siz= eof(EFI_COMMON_SECTION_HEADER2); + } else { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER) - size= of(EFI_COMMON_SECTION_HEADER); + } + } + } + } + + return (UINT8 *)ffsHdr + FFSDataOffset; +} + +EFI_STATUS +ReadFFSFile ( + IN EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader, + IN EFI_GUID FFSGuid, + IN UINT32 FFSDataSize, + IN OUT VOID *FFSData, + OUT UINT32 *FFSSize, + IN BOOLEAN skipheader + ) +/*++ + +Routine Description: + + Read FFS file from FV + +Arguments: + + FwVolHeader - FV Base Address + + FFSGuid - FFS to find & Read + + FFSDataSize - Data size to read.If this value equal 0, will read the w= hole FFS size + + FFSData - Pointer to buffer for read. + + FFSSize - FFS file size FYI for caller. + + skipheader - TRUE: skip to read the ffs and first section header,read fr= om data directly, for one data section only ffs + FALSE:read from header + +Returns: + + None + +--*/ +{ + EFI_FFS_FILE_HEADER *ffsHdr; + UINT64 FvSize; + UINT32 FileOccupiedSize; + UINT32 FFSDataOffset; + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME_EXT_HEADER *FwVolExtHeader; + + Status =3D EFI_NOT_FOUND; + *FFSSize =3D 0; + FvSize =3D 0; + FFSDataOffset =3D 0; + if (FwVolHeader->ExtHeaderOffset !=3D 0) { + // + // Searching for files starts on an 8 byte aligned boundary after the = end of the Extended Header if it exists. + // + FwVolExtHeader =3D (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINTN)FwVolHea= der + FwVolHeader->ExtHeaderOffset ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ((UINT8 *) FwVolExtHeader + FwVolEx= tHeader->ExtHeaderSize); + } else { + ffsHdr =3D (EFI_FFS_FILE_HEADER*)(((UINT8 *) FwVolHeader)+ FwVolHeade= r->HeaderLength); + } + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + + if(FwVolHeader->FvLength =3D=3D 0xFFFFFFFFFFFFFFFF) { + return EFI_VOLUME_CORRUPTED; + } + + FvSize =3D (UINTN)ffsHdr-(UINTN)FwVolHeader; + while((FvSize < FwVolHeader->FvLength)&&((UINTN)ffsHdr <((UINTN)FwVolHea= der+ (UINTN)FwVolHeader->FvLength))){ + if(CompareGuid (&ffsHdr->Name, &FFSGuid)){ + Status =3D EFI_SUCCESS; + break; + } + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + + FvSize+=3D FileOccupiedSize; + ffsHdr =3D (EFI_FFS_FILE_HEADER *)((UINT8 *)ffsHdr + FileOccupiedSize= ); + ffsHdr =3D (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (ffsHdr, 8); + } + + if (FvSize < FwVolHeader->FvLength) { + if (IS_FFS_FILE2 (ffsHdr)) { + FileOccupiedSize =3D FFS_FILE2_SIZE (ffsHdr) ; + } else { + FileOccupiedSize =3D FFS_FILE_SIZE (ffsHdr) ; + } + *FFSSize =3D FileOccupiedSize; + + if(FFSDataSize =3D=3D 0) { + FFSDataSize=3D *FFSSize; + } + + if(skipheader){ + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER2) + sizeof(EFI_COMMON_S= ECTION_HEADER2); + } else { + FFSDataOffset =3D sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_SE= CTION_HEADER); + } + if(FFSDataSize =3D=3D 0) { + if (IS_FFS_FILE2 (ffsHdr)) { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER2) - sizeo= f(EFI_COMMON_SECTION_HEADER2); + } else { + FFSDataSize =3D FFSDataSize - sizeof(EFI_FFS_FILE_HEADER) - sizeof= (EFI_COMMON_SECTION_HEADER); + } + } + } + + CopyMem(FFSData,(UINT8*)ffsHdr + FFSDataOffset,FFSDataSize); + } + return Status; +} + +BOOLEAN +NormalHobToCompressHob(IN OUT VOID* hobAddr,IN OUT UINTN* size) +{ + UINTN i,j,k; + COMPRESS_HOBO_DATA CompressHob; + COMPRESS_ITEM Hobitem[MAX_COMPRESS_ITEM]; + UINT16 TempBuffer[MAX_FFS_BUFFER_SIZE/4]; + UINTN offset=3D0; + UINTN RemainSize =3D 0; + + CompressHob.Signature =3D 0x5A45524F; + CompressHob.Count =3D0; + j=3D0; + i=3D0; + RemainSize =3D (*size % 2) + 2; + if(MAX_COMPRESS_ITEM*sizeof(COMPRESS_ITEM)+MAX_FFS_BUFFER_SIZE/4+sizeof(= COMPRESS_HOBO_DATA) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + if((*size) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + ZeroMem(TempBuffer,MAX_FFS_BUFFER_SIZE/2); + + while(i < (*size - RemainSize)){ + + if(j>=3DMAX_COMPRESS_ITEM) { + return FALSE; + } + + //search for duplicate array + if(*(UINT16*)((UINTN)hobAddr+i)=3D=3D*(UINT16*)((UINTN)hobAddr+i+2) ){ + + for(k=3D2;(i+k)<(*size- RemainSize);k+=3D2 ){ + if(*(UINT16*)((UINTN)hobAddr+i)!=3D*(UINT16*)((UINTN)hobAddr+i+k)= ){ + break; + } + } + + if(i+k>=3D *size - (*size % 2)) { + k -=3D2; + } + + Hobitem[j].Value =3D *(UINT16*)((UINTN)hobAddr+i); + Hobitem[j].Length =3D(UINT16) k; + Hobitem[j].Type =3D COMPRESS_DUPLICATE; + Hobitem[j].Offset =3D 0; + j++; + CompressHob.Count =3D(UINT32)j; + i+=3Dk; + + } + else{//single array + for(k=3D2;i+k+2 <=3D (*size- RemainSize);k+=3D2){ + if(offset >=3D MAX_FFS_BUFFER_SIZE/4) { + return FALSE; + } + TempBuffer[offset]=3D *(UINT16*)((UINTN)hobAddr+i+k-2); + offset +=3D1; + if(*(UINT16*)((UINTN)hobAddr+i+k)=3D=3D*(UINT16*)((UINTN)hobAddr+i+= k+2)){ + k +=3D 2; + break; + } + + } + + + Hobitem[j].Length =3D (UINT16) k - 2; + Hobitem[j].Type =3D COMPRESS_SINGLE; + Hobitem[j].Offset =3D (UINT16)(offset - (Hobitem[j].Length/2) ); + Hobitem[j].Value =3D0; + j++; + CompressHob.Count =3D(UINT32)j; + i+=3Dk - 2; + + } + + } + + if(j>=3DMAX_COMPRESS_ITEM) { + //not worth to compress + return FALSE; + } + + //process last one + CopyMem((UINT8*)(&TempBuffer[offset]), (UINT8*)((UINTN)hobAddr + *size -= RemainSize), RemainSize); + Hobitem[j].Length =3D (UINT16)RemainSize; + Hobitem[j].Type =3D COMPRESS_SINGLE; + Hobitem[j].Offset =3D (UINT16)offset; + Hobitem[j].Value =3D0; + j++; + CompressHob.Count =3D(UINT32)j; + + CopyMem(hobAddr,(VOID*)&CompressHob,sizeof(COMPRESS_HOBO_DATA)); + offset =3D sizeof(COMPRESS_HOBO_DATA); + for(i=3D0; i < CompressHob.Count;i++){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),(UINT8*)&Hobitem[i],sizeof(COM= PRESS_ITEM)); + offset +=3D sizeof(COMPRESS_ITEM); + if(Hobitem[i].Type =3D=3D COMPRESS_SINGLE){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),&TempBuffer[Hobitem[i].Offse= t],Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + } + } + + *size =3D offset; + + return TRUE; +} + +BOOLEAN +CompressHobToNormalHob(IN OUT VOID* hobAddr,OUT UINTN* size) +{ + UINTN i; + COMPRESS_HOBO_DATA CompressHob ; + COMPRESS_ITEM Hobitem[MAX_COMPRESS_ITEM]; + UINTN offset=3D0; + UINT16 TempBuffer[MAX_FFS_BUFFER_SIZE/4]; + + CopyMem((VOID*)&CompressHob,hobAddr,sizeof(COMPRESS_HOBO_DATA)); + + if(CompressHob.Signature !=3D 0x5A45524F) { + return FALSE; + } + + if(CompressHob.Count>MAX_COMPRESS_ITEM) { + //not worth to compress + return FALSE; + } + + if(*size > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + if(MAX_COMPRESS_ITEM*sizeof(COMPRESS_ITEM)+MAX_FFS_BUFFER_SIZE/4+sizeof(= COMPRESS_HOBO_DATA) > MAX_FFS_BUFFER_SIZE) { + return FALSE; + } + + offset =3D sizeof(COMPRESS_HOBO_DATA); + for(i=3D0; i < CompressHob.Count;i++){ + CopyMem((VOID*)&Hobitem[i],(UINT8*)((UINTN)hobAddr+offset),sizeof(COMP= RESS_ITEM)); + offset +=3D sizeof(COMPRESS_ITEM); + if(Hobitem[i].Type =3D=3D COMPRESS_SINGLE){ + CopyMem(&TempBuffer[Hobitem[i].Offset],(UINT8*)((UINTN)hobAddr+offse= t),Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + } + } + + offset =3D0; + for(i=3D0; i < CompressHob.Count;i++){ + if(Hobitem[i].Type =3D=3DCOMPRESS_DUPLICATE){ + SetMem16((VOID*)((UINTN)hobAddr+offset),Hobitem[i].Length,Hobitem[i].= Value); + offset +=3D Hobitem[i].Length; + } + else if(Hobitem[i].Type =3D=3DCOMPRESS_SINGLE){ + CopyMem((UINT8*)((UINTN)hobAddr+offset),&TempBuffer[Hobitem[i].Offset= ],Hobitem[i].Length); + offset +=3D Hobitem[i].Length; + + } + + } + + *size =3D offset; + + return TRUE; +} + +EFI_STATUS +ValidateCommonFvHeader ( + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ) +/*++ + +Routine Description: + Check the integrity of firmware volume header + +Arguments: + FwVolHeader - A pointer to a firmware volume header + +Returns: + EFI_SUCCESS - The firmware volume is consistent + EFI_NOT_FOUND - The firmware volume has corrupted. So it is not = an FV + +--*/ +{ + UINT16 *Ptr; + UINT16 HeaderLength; + UINT16 Checksum; + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) || + (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength =3D=3D ((UINTN) -1)) || + ((FwVolHeader->HeaderLength & 0x01) !=3D 0) + ) { + return EFI_NOT_FOUND; + } + // + // Verify the header checksum + // + HeaderLength =3D (UINT16) (FwVolHeader->HeaderLength / 2); + Ptr =3D (UINT16 *) FwVolHeader; + Checksum =3D 0; + while (HeaderLength > 0) { + Checksum =3D Checksum + (*Ptr); + Ptr++; + HeaderLength--; + } + + if (Checksum !=3D 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsL= ib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.i= nf new file mode 100644 index 0000000000..94f2cdbb5f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/ReadFfsLib/ReadFfsLib.inf @@ -0,0 +1,34 @@ +## @file +# Read FFS library +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ReadFfsLib + FILE_GUID =3D CD5BD27A-A122-41DE-B277-A258284BF35C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ReadFfslib + +[Sources] + ReadFfsLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + +[Pcd] + +[Protocols] + +[Guids] + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns165= 50.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns16550.h new file mode 100644 index 0000000000..77a1bdd849 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ns16550.h @@ -0,0 +1,46 @@ +/** @file + Header file of NS16550 hardware definition. + + @copyright + Copyright 6550 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __NS16550_H_ +#define __NS16550_H_ + +// +// --------------------------------------------- +// UART Register Offsets +// --------------------------------------------- +// +#define BAUD_LOW_OFFSET 0x00 +#define BAUD_HIGH_OFFSET 0x01 +#define IER_OFFSET 0x01 +#define LCR_SHADOW_OFFSET 0x01 +#define FCR_SHADOW_OFFSET 0x02 +#define IR_CONTROL_OFFSET 0x02 +#define FCR_OFFSET 0x02 +#define EIR_OFFSET 0x02 +#define BSR_OFFSET 0x03 +#define LCR_OFFSET 0x03 +#define MCR_OFFSET 0x04 +#define LSR_OFFSET 0x05 +#define MSR_OFFSET 0x06 + +// +// --------------------------------------------- +// UART Register Bit Defines +// --------------------------------------------- +// +#define LSR_TXRDY 0x20 +#define LSR_RXDA 0x01 +#define DLAB 0x01 + +#define UART_DATA 8 +#define UART_STOP 1 +#define UART_PARITY 0 +#define UART_BREAK_SET 0 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.c new file mode 100644 index 0000000000..28be8147c2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/SerialPortLi= b.c @@ -0,0 +1,1023 @@ +/** @file + Serial I/O Port library functions with no library constructor/destructor + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "Ns16550.h" +#include +#include +#include +#include +#include +#include + +// +// PCH I/O Port Defines +// +#define R_PCH_IOPORT_PCI_INDEX 0xCF8 +#define R_PCH_IOPORT_PCI_DATA 0xCFC + +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11= ) | (((Bus) & 0xFF) << 16) | (1 << 31)) + +#define PCH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(DEFAULT_PCI_BUS_NUMBER_PC= H, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, Offset) + +// +// PCI Defintions. +// +#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01 + +#define B_UART_FCR_FIFOE BIT0 +#define B_UART_FCR_FIFO64 BIT5 +#define R_UART_LCR 3 +#define R_UART_LSR 5 +#define B_UART_LSR_RXRDY BIT0 +#define R_UART_MCR 4 +#define B_UART_MCR_RTS BIT1 +#define B_UART_MCR_DTRC BIT0 +#define R_UART_MSR 6 +#define B_UART_MSR_CTS BIT4 +#define B_UART_MSR_DSR BIT5 +#define B_UART_MSR_RI BIT6 +#define B_UART_MSR_DCD BIT7 +#define B_UART_LSR_RXRDY BIT0 +#define B_UART_LSR_TXRDY BIT5 +#define B_UART_LSR_TEMT BIT6 +#define R_UART_BAUD_LOW 0 +#define R_UART_BAUD_HIGH 1 +#define B_UART_LCR_DLAB BIT7 + +// +// COM definitions +// +#define COM1_BASE 0x3f8 +#define COM2_BASE 0x2f8 + +UINT32 +IsSioExist ( + VOID + ); + +typedef struct { + UINT8 Index; + UINT8 Data; +} SIO_REG_TABLE; + + +STATIC SIO_REG_TABLE mASPEED2500Table [] =3D { + { REG_LOGICAL_DEVICE, ASPEED2500_SIO_UART1 }, + { ACTIVATE, 0x01 }, + { PRIMARY_INTERRUPT_SELECT, 0x04 }, // COMA IRQ routing + { INTERRUPT_TYPE, 0x01 }, // COMA Interrupt Type + { REG_LOGICAL_DEVICE, ASPEED2500_SIO_UART2 }, + { ACTIVATE, 0x01 }, + { PRIMARY_INTERRUPT_SELECT, 0x03 }, // COMB IRQ routing + { INTERRUPT_TYPE, 0x01 } // COMB Interrupt Type +}; + +UINT8 gData =3D 8; +UINT8 gStop =3D 1; +UINT8 gParity =3D 0; +UINT8 gBreakSet =3D 0; + +// +// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo +// +typedef struct { + UINT8 Device; + UINT8 Function; + UINT16 PowerManagementStatusAndControlRegister; +} PCI_UART_DEVICE_INFO; + +/** + + Check if Serial Port is enabled or not. + + @param none + + @retval TRUE Serial Port was enabled. + @retval FALSE Serial Port was disabled. + +**/ +BOOLEAN +EFIAPI +IsSerialPortEnabled ( +) +{ + return TRUE; +} + +UINT8 +SerialPortReadRegister ( + UINTN Base, + UINTN Offset + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } else { + return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride)); + } +} + +UINT8 +SerialPortWriteRegister ( + UINTN Base, + UINTN Offset, + UINT8 Value + ) +{ + if (PcdGetBool (PcdSerialUseMmio)) { + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),= Value); + } else { + return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), V= alue); + } +} + +/** + Update the value of an 32-bit PCI configuration register in a PCI device= . If the + PCI Configuration register specified by PciAddress is already programmed= with a + non-zero value, then return the current value. Otherwise update the PCI= configuration + register specified by PciAddress with the value specified by Value and r= eturn the + value programmed into the PCI configuration register. All values must b= e masked + using the bitmask specified by Mask. + + @param PciAddress PCI Library address of the PCI Configuration registe= r to update. + @param Value The value to program into the PCI Configuration Regi= ster. + @param Mask Bitmask of the bits to check and update in the PCI c= onfiguration register. + + @return The Secondary bus number that is actually programed into the PC= I to PCI Bridge device. + +**/ +UINT32 +SerialPortLibUpdatePciRegister32 ( + UINTN PciAddress, + UINT32 Value, + UINT32 Mask + ) +{ + UINT32 CurrentValue; + + CurrentValue =3D PciRead32 (PciAddress) & Mask; + if (CurrentValue !=3D 0) { + return CurrentValue; + } + return PciWrite32 (PciAddress, Value & Mask); +} + +/** + Retrieve the I/O or MMIO base address register for the PCI UART device. + + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO i= n PCI UART + Device if they are not already enabled. + + @return The base address register of the UART device. + +**/ +UINTN +GetSerialRegisterBase ( + VOID + ) +{ + UINTN PciLibAddress; + UINTN BusNumber; + UINTN SubordinateBusNumber; + UINT32 ParentIoBase; + UINT32 ParentIoLimit; + UINT16 ParentMemoryBase; + UINT16 ParentMemoryLimit; + UINT32 IoBase; + UINT32 IoLimit; + UINT16 MemoryBase; + UINT16 MemoryLimit; + UINTN SerialRegisterBase; + UINTN BarIndex; + UINT32 RegisterBaseMask; + PCI_UART_DEVICE_INFO *DeviceInfo; + + // + // Get PCI Device Info + // + DeviceInfo =3D (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInf= o); + + // + // If PCI Device Info is empty, then assume fixed address UART and retur= n PcdSerialRegisterBase + // + if (DeviceInfo->Device =3D=3D 0xff) { + return (UINTN)PcdGet64 (PcdSerialRegisterBase); + } + + // + // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB + // + ParentMemoryBase =3D 0 >> 16; + ParentMemoryLimit =3D 0xfff00000 >> 16; + ParentIoBase =3D 0 >> 12; + ParentIoLimit =3D 0xf000 >> 12; + + // + // Enable I/O and MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber =3D 0; (DeviceInfo + 1)->Device !=3D 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Devi= ceInfo->Function, 0); + + // + // Retrieve and verify the bus numbers in the PCI to PCI Bridge + // + BusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDAR= Y_BUS_REGISTER_OFFSET); + SubordinateBusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDIN= ATE_BUS_REGISTER_OFFSET); + if (BusNumber =3D=3D 0 || BusNumber > SubordinateBusNumber) { + return 0; + } + + // + // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI= Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + MemoryLimit =3D PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Br= idge.MemoryLimit)) & 0xfff0; + MemoryBase =3D PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Br= idge.MemoryBase)) & 0xfff0; + + // + // If PCI Bridge MMIO window is disabled, then return 0 + // + if (MemoryLimit < MemoryBase) { + return 0; + } + + // + // If PCI Bridge MMIO window is not in the address range decoded by = the parent PCI Bridge, then return 0 + // + if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit = || MemoryLimit > ParentMemoryLimit) { + return 0; + } + ParentMemoryBase =3D MemoryBase; + ParentMemoryLimit =3D MemoryLimit; + } else { + IoLimit =3D PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoLimit)); + if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) =3D=3D 0) { + IoLimit =3D IoLimit >> 4; + } else { + IoLimit =3D (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bri= dge.IoLimitUpper16)) << 4) | (IoLimit >> 4); + } + IoBase =3D PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase)); + if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) =3D=3D 0) { + IoBase =3D IoBase >> 4; + } else { + IoBase =3D (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Brid= ge.IoBaseUpper16)) << 4) | (IoBase >> 4); + } + + // + // If PCI Bridge I/O window is disabled, then return 0 + // + if (IoLimit < IoBase) { + return 0; + } + + // + // If PCI Bridge I/O window is not in the address range decoded by t= he parent PCI Bridge, then return 0 + // + if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > Par= entIoLimit) { + return 0; + } + ParentIoBase =3D IoBase; + ParentIoLimit =3D IoLimit; + } + } + + // + // Compute PCI Lib Address to PCI UART + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Device= Info->Function, 0); + + // + // Find the first IO or MMIO BAR + // + RegisterBaseMask =3D 0xFFFFFFF0; + for (BarIndex =3D 0; BarIndex < PCI_MAX_BAR; BarIndex ++) { + SerialRegisterBase =3D PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_= OFFSET + BarIndex * 4); + if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) =3D= =3D 0)) { + // + // MMIO BAR is found + // + RegisterBaseMask =3D 0xFFFFFFF0; + break; + } + + if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != =3D 0)) { + // + // IO BAR is found + // + RegisterBaseMask =3D 0xFFFFFFF8; + break; + } + } + + // + // MMIO or IO BAR is not found. + // + if (BarIndex =3D=3D PCI_MAX_BAR) { + return 0; + } + + // + // Program UART BAR + // + SerialRegisterBase =3D SerialPortLibUpdatePciRegister32 ( + PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarI= ndex * 4, + (UINT32)PcdGet64 (PcdSerialRegisterBase), + RegisterBaseMask + ); + + // + // Verify that the UART BAR is in the address range decoded by the paren= t PCI Bridge + // + if (PcdGetBool (PcdSerialUseMmio)) { + if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((Seri= alRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) { + return 0; + } + } else { + if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >= > 12) > ParentIoLimit) { + return 0; + } + } + + // + // Enable I/O and MMIO in PCI UART Device if they are not already enabled + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI= _COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specified + // + if (DeviceInfo->PowerManagementStatusAndControlRegister !=3D 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndCo= ntrolRegister) & (BIT0 | BIT1)) !=3D 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndContro= lRegister, (UINT16)~(BIT0 | BIT1)); + // + // If PCI UART was not in D0, then make sure FIFOs are enabled, but = do not reset FIFOs + // + SerialPortWriteRegister (SerialRegisterBase, FCR_OFFSET, (UINT8)(Pcd= Get8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64))); + } + } + + // + // Get PCI Device Info + // + DeviceInfo =3D (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInf= o); + + // + // Enable I/O or MMIO in PCI Bridge + // Assume Root Bus Numer is Zero. + // + for (BusNumber =3D 0; (DeviceInfo + 1)->Device !=3D 0xff; DeviceInfo++) { + // + // Compute PCI Lib Address to PCI to PCI Bridge + // + PciLibAddress =3D PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, Devi= ceInfo->Function, 0); + + // + // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge + // + PciOr16 ( + PciLibAddress + PCI_COMMAND_OFFSET, + PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_P= CI_COMMAND_IO_SPACE + ); + + // + // Force D0 state if a Power Management and Status Register is specifi= ed + // + if (DeviceInfo->PowerManagementStatusAndControlRegister !=3D 0x00) { + if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAnd= ControlRegister) & (BIT0 | BIT1)) !=3D 0x00) { + PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndCont= rolRegister, (UINT16)~(BIT0 | BIT1)); + } + } + + BusNumber =3D PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGIS= TER_OFFSET); + } + + return SerialRegisterBase; +} + + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +InitializeSio ( + VOID + ) +{ + + UINT32 SioExist; + UINT32 SioEnable; + UINT32 Index; + UINT32 Decode; + UINT32 Enable; + UINT32 SpiConfigValue; + + // + // Enable LPC decode + // Set COMA/COMB base + // + Decode =3D ((V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) | (V_LPC_CFG= _IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB)); + SpiConfigValue =3D MmioRead32 (PCH_PCR_ADDRESS (PID_ESPISPI, R_PCH_PCR_S= PI_CONF_VALUE)); + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + Enable =3D ( B_LPC_CFG_IOE_ME2 | B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_ME1= \ + | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE); + } else { + Enable =3D ( B_LPC_CFG_IOE_ME2 | B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_ME1= \ + | B_LPC_CFG_IOE_KE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE); + } + IoWrite32 (R_PCH_IOPORT_PCI_INDEX, (UINT32) (PCH_LPC_CF8_ADDR (R_LPC_CFG= _IOD))); + + IoWrite32 (R_PCH_IOPORT_PCI_DATA, Decode | (Enable << 16)); + + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_LPCIOD), (UINT16)Dec= ode); + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_DMI_PCR_LPCIOE), (UINT16)Ena= ble); + + SioExist =3D IsSioExist(); + + if ((SioExist & (PILOTIV_EXIST | PC8374_EXIST)) =3D=3D (PILOTIV_EXIST | = PC8374_EXIST) ) { + // + // Both are there, we use DEFAULT_SIO as debug port anyway + // + if (DEFAULT_SIO =3D=3D PILOTIV_EXIST) { + SioEnable =3D PILOTIV_EXIST; + } else { + SioEnable =3D PC8374_EXIST; + } + } else { + SioEnable =3D SioExist; + } + + // + // ASPEED AST2500/AST2600 UART init. + // + if (SioEnable =3D=3D ASPEED_EXIST) { + // + // Unlock SIO + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_UNLOCK); + + // + // COM1 & COM2 + // + for (Index =3D 0; Index < sizeof (mASPEED2500Table)/sizeof (SIO_REG_TA= BLE); Index++) { + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, mASPEED2500Table[Index].Index); + IoWrite8 (ASPEED2500_SIO_DATA_PORT, mASPEED2500Table[Index].Data); + } + + // + // Lock SIO + // + IoWrite8 (ASPEED2500_SIO_INDEX_PORT, ASPEED2500_SIO_LOCK); + } +} + +/** + + Initialize Serial Port + + The Baud Rate Divisor registers are programmed and the LCR + is used to configure the communications format. Hard coded + UART config comes from globals in DebugSerialPlatform lib. + + @param None + + @retval None + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINTN Divisor; + UINT8 OutputData; + UINT8 Data; + UINT16 ComBase; + + ComBase =3D (UINT16)PcdGet64 (PcdSerialRegisterBase); + InitializeSio(); + // + // Some init is done by the platform status code initialization. + // + // + // Map 5..8 to 0..3 + // + Data =3D (UINT8) (gData - (UINT8) 5); + + // + // Calculate divisor for baud generator + // + Divisor =3D 115200 / PcdGet32(PcdSerialBaudRate); + + // + // Set communications format + // + OutputData =3D (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3= ) | ((gStop << 2) | Data)))); + IoWrite8 (ComBase + LCR_OFFSET, OutputData); + + // + // Configure baud rate + // + IoWrite8 (ComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (ComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); + + // + // Switch back to bank 0 + // + OutputData =3D (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << = 3) | ((gStop << 2) | Data)))); + IoWrite8 (ComBase + LCR_OFFSET, OutputData); + + return RETURN_SUCCESS; +} + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes writed to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + UINT8 Data; + + if ((IsSerialPortEnabled() =3D=3D FALSE) || (NULL =3D=3D Buffer)) { + return 0; + } + + Result =3D NumberOfBytes; + + while (NumberOfBytes--) { + // + // Wait for the serail port to be ready. + // + do { + Data =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OF= FSET); + } while ((Data & LSR_TXRDY) =3D=3D 0); + IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++); + } + + return Result; +} + + +/* + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval 0 Read data failed. + @retval !0 Actual number of bytes raed to serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + UINT8 Data; + + if ((IsSerialPortEnabled() =3D=3D FALSE) || (NULL =3D=3D Buffer)) { + return 0; + } + + Result =3D NumberOfBytes; + + while (NumberOfBytes--) { + // + // Wait for the serail port to be ready. + // + do { + Data =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OF= FSET); + } while ((Data & LSR_RXDA) =3D=3D 0); + + *Buffer++ =3D IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase)); + } + + return Result; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINTN SerialRegisterBase; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return FALSE; + } + + // + // Read the serial port status + // + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LS= R_RXRDY) !=3D 0) { + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Clear RTS to prevent peer from sending data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Ser= ialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS)); + } + return TRUE; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + // + // Set RTS to let the peer send some data + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Seria= lPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS)); + } + + return FALSE; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the seria= l device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Mcr; + + // + // First determine the parameter is invalid. + // + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_= READY | + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) !=3D 0) { + return RETURN_UNSUPPORTED; + } + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + // + // Read the Modem Control Register. + // + Mcr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + Mcr &=3D (~(B_UART_MCR_DTRC | B_UART_MCR_RTS)); + + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) =3D=3D EFI_SERIAL_DATA_TE= RMINAL_READY) { + Mcr |=3D B_UART_MCR_DTRC; + } + + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) =3D=3D EFI_SERIAL_REQUEST_TO_= SEND) { + Mcr |=3D B_UART_MCR_RTS; + } + + // + // Write the Modem Control Register. + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr); + + return RETURN_SUCCESS; + +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial= device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + UINTN SerialRegisterBase; + UINT8 Msr; + UINT8 Mcr; + UINT8 Lsr; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + *Control =3D 0; + + // + // Read the Modem Status Register. + // + Msr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MSR); + + if ((Msr & B_UART_MSR_CTS) =3D=3D B_UART_MSR_CTS) { + *Control |=3D EFI_SERIAL_CLEAR_TO_SEND; + } + + if ((Msr & B_UART_MSR_DSR) =3D=3D B_UART_MSR_DSR) { + *Control |=3D EFI_SERIAL_DATA_SET_READY; + } + + if ((Msr & B_UART_MSR_RI) =3D=3D B_UART_MSR_RI) { + *Control |=3D EFI_SERIAL_RING_INDICATE; + } + + if ((Msr & B_UART_MSR_DCD) =3D=3D B_UART_MSR_DCD) { + *Control |=3D EFI_SERIAL_CARRIER_DETECT; + } + + // + // Read the Modem Control Register. + // + Mcr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_MCR); + + if ((Mcr & B_UART_MCR_DTRC) =3D=3D B_UART_MCR_DTRC) { + *Control |=3D EFI_SERIAL_DATA_TERMINAL_READY; + } + + if ((Mcr & B_UART_MCR_RTS) =3D=3D B_UART_MCR_RTS) { + *Control |=3D EFI_SERIAL_REQUEST_TO_SEND; + } + + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) { + *Control |=3D EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE; + } + + // + // Read the Line Status Register. + // + Lsr =3D SerialPortReadRegister (SerialRegisterBase, R_UART_LSR); + + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) =3D=3D (B_UART_LSR_TEMT= | B_UART_LSR_TXRDY)) { + *Control |=3D EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + + if ((Lsr & B_UART_LSR_RXRDY) =3D=3D 0) { + *Control |=3D EFI_SERIAL_INPUT_BUFFER_EMPTY; + } + + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + serial interface. A ReceiveFifoDepth value of = 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in microseconds. + This timeout applies to both the transmit and = receive side of the + interface. A Timeout value of 0 will use the d= evice's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A Parity value of + DefaultParity will use the device's default pa= rity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. A DataBits + vaule of 0 will use the device's default data = bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. A StopBits + value of DefaultStopBits will use the device's= default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + UINTN SerialRegisterBase; + UINT32 SerialBaudRate; + UINTN Divisor; + UINT8 Lcr; + UINT8 LcrData; + UINT8 LcrParity; + UINT8 LcrStop; + + SerialRegisterBase =3D GetSerialRegisterBase (); + if (SerialRegisterBase =3D=3D0) { + return RETURN_UNSUPPORTED; + } + + // + // Check for default settings and fill in actual values. + // + if (*BaudRate =3D=3D 0) { + *BaudRate =3D PcdGet32 (PcdSerialBaudRate); + } + SerialBaudRate =3D (UINT32) *BaudRate; + + if (*DataBits =3D=3D 0) { + LcrData =3D (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3); + *DataBits =3D LcrData + 5; + } else { + if ((*DataBits < 5) || (*DataBits > 8)) { + return RETURN_INVALID_PARAMETER; + } + // + // Map 5..8 to 0..3 + // + LcrData =3D (UINT8) (*DataBits - (UINT8) 5); + } + + if (*Parity =3D=3D DefaultParity) { + LcrParity =3D (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7); + switch (LcrParity) { + case 0: + *Parity =3D NoParity; + break; + + case 3: + *Parity =3D EvenParity; + break; + + case 1: + *Parity =3D OddParity; + break; + + case 7: + *Parity =3D SpaceParity; + break; + + case 5: + *Parity =3D MarkParity; + break; + + default: + break; + } + } else { + switch (*Parity) { + case NoParity: + LcrParity =3D 0; + break; + + case EvenParity: + LcrParity =3D 3; + break; + + case OddParity: + LcrParity =3D 1; + break; + + case SpaceParity: + LcrParity =3D 7; + break; + + case MarkParity: + LcrParity =3D 5; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + if (*StopBits =3D=3D DefaultStopBits) { + LcrStop =3D (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1); + switch (LcrStop) { + case 0: + *StopBits =3D OneStopBit; + break; + + case 1: + if (*DataBits =3D=3D 5) { + *StopBits =3D OneFiveStopBits; + } else { + *StopBits =3D TwoStopBits; + } + break; + + default: + break; + } + } else { + switch (*StopBits) { + case OneStopBit: + LcrStop =3D 0; + break; + + case OneFiveStopBits: + case TwoStopBits: + LcrStop =3D 1; + break; + + default: + return RETURN_INVALID_PARAMETER; + } + } + + // + // Calculate divisor for baud generator + // Ref_Clk_Rate / Baud_Rate / 16 + // + Divisor =3D PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16); + if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >=3D SerialB= audRate * 8) { + Divisor++; + } + + // + // Configure baud rate + // + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB= ); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (= Divisor >> 8)); + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (D= ivisor & 0xff)); + + // + // Clear DLAB and configure Data Bits, Parity, and Stop Bits. + // Strip reserved bits from line control value + // + Lcr =3D (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData); + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & = 0x3F)); + + return RETURN_SUCCESS; + +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Seria= lPortLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/Ser= ialPortLib.inf new file mode 100644 index 0000000000..df308e412e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SerialPortLib/SerialPortLi= b.inf @@ -0,0 +1,55 @@ +## @file +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SerialPortLib + FILE_GUID =3D 15B26F43-A389-4bae-BDE3-4BB0719B7D4F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + EDK_RELEASE_VERSION =3D 0x00020000 + UEFI_SPECIFICATION_VERSION =3D 0x00020000 + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[Sources.common] + SerialPortLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + PcdLib + PciLib + IoLib + DebugLib + PlatformHooksLib + +[FixedPcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMET= IMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSU= MES + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/Set= CacheMtrrLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib= /SetCacheMtrrLib.c new file mode 100644 index 0000000000..b67dafd366 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/SetCacheMt= rrLib.c @@ -0,0 +1,867 @@ +/** @file + SetCacheMtrr library functions. + + @copyright + Copyright 2006 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#define EFI_MAX_ADDRESS 0xFFFFFFFF + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance + /// + MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set + /// until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); + DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); + + /// + /// Assume size of main memory is multiple of 256MB + /// + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; + MemoryBase =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB + /// + if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer + /// + MtrrSetAllMtrrs (&MtrrSetting); + + return ; +} + +/** + + This function finds the start address and size of control or Block windo= w region in the system. + + @param Host - pointer to sysHost structure on stack + @param Memtype - Type of the memory range + @param RangeSize - pointer to the variable to store the StartAddress + @param RangeSize - pointer to the variable to store RangeSize + + @retval EFI_SUCCESS - success + EFI_NOT_FOUND - Region not found. + +**/ +EFI_STATUS +GetMemoryRegionRange( + struct SystemMemoryMapHob *systemMemoryMap, + UINT16 Memtype, + EFI_PHYSICAL_ADDRESS *StartAddress, + EFI_PHYSICAL_ADDRESS *RangeSize) +{ + UINT8 Index; + EFI_STATUS Status =3D EFI_NOT_FOUND; + UINT8 Socket =3D 0; + EFI_PHYSICAL_ADDRESS Limit =3D 0; + + *RangeSize =3D 0; + *StartAddress =3D 0; + + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + if (systemMemoryMap->Socket[Socket].SAD[0].Enable =3D=3D 0) { + continue; + } + + for (Index =3D 0; Index < MAX_SAD_RULES; Index++) { + if (systemMemoryMap->Socket[Socket].SAD[Index].Enable =3D=3D 0) { + continue; + } + if (systemMemoryMap->Socket[Socket].SAD[Index].type =3D=3D Memtype) { + if ((*StartAddress =3D=3D 0) && (Index > 0)) { + //Store the start address for the specified range in bytes + *StartAddress =3D (EFI_PHYSICAL_ADDRESS)MultU64x32 ((UINT64)syst= emMemoryMap->Socket[Socket].SAD[Index-1].Limit, CONVERT_64MB_TO_BYTE); + } + + if (MultU64x32((UINT64)systemMemoryMap->Socket[Socket].SAD[Index].= Limit, CONVERT_64MB_TO_BYTE) > Limit) { + //Store/Update the end address for the specified range in bytes = if greater than previous limit + Limit =3D (EFI_PHYSICAL_ADDRESS)MultU64x32 ((UINT64)systemMemory= Map->Socket[Socket].SAD[Index].Limit, CONVERT_64MB_TO_BYTE); + } + } + } + } + + if (Limit !=3D 0) { + *RangeSize =3D Limit - *StartAddress; + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + + MP programming MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN at socket level. + + @param PeiServices - Ptr of EFI_PEI_SERVICES ptr + @param mPeiMpServices - Ptr of EFI_PEI_MP_SERVICES_PPI + + @retval EFI_SUCCESS - Programming done + @retval EFI_UNSUPPORTED - Not support this platform + +**/ +EFI_STATUS +PkgMpEnableMcaOnCacheableMmio( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *mPeiMpServices +) +{ + UINT16 PackageDoneBitmap; + UINTN NumberOfProcessors; + UINTN NumberEnabledProcessors; + UINTN Index; + UINT8 TotalSockets =3D 0; + EFI_PROCESSOR_INFORMATION ProcInfo; + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (!DynamicSiLibraryPpi->IsCpuAndRevision (CPU_SKX, REV_ALL) && !Dynami= cSiLibraryPpi->IsCpuAndRevision (CPU_CLX, REV_ALL) && !DynamicSiLibraryPpi-= >IsCpuAndRevision (CPU_CPX, REV_ALL)) { + return EFI_UNSUPPORTED; + } + + PackageDoneBitmap =3D 0; + mPeiMpServices->GetNumberOfProcessors( + PeiServices, + mPeiMpServices, + &NumberOfProcessors, + &NumberEnabledProcessors + ); + + // + // Find total number of sockets present on the board + // + for (Index =3D 0; Index < MAX_SOCKET; Index++) { + if (DynamicSiLibraryPpi->SocketPresent (Index)) { + TotalSockets++; + } + } + + // + // Loop through all the enabled processors and find one thread per socke= t present + // to write the MSR. Remote sockets need to use StartupThisAP. + // + for (Index =3D 0; Index < NumberOfProcessors; Index++) { + mPeiMpServices->GetProcessorInfo( + PeiServices, + mPeiMpServices, + Index, + &ProcInfo + ); + + if (!(PackageDoneBitmap & (1 << ProcInfo.Location.Package)) && (ProcIn= fo.StatusFlag & PROCESSOR_ENABLED_BIT)) { + + PackageDoneBitmap |=3D (1 << ProcInfo.Location.Package); + TotalSockets--; + + if (ProcInfo.StatusFlag & PROCESSOR_AS_BSP_BIT) { + DynamicSiLibraryPpi->EnableMcaOnCacheableMmio(); + } else { + Status =3D mPeiMpServices->StartupThisAP ( + PeiServices, + mPeiMpServices, + (EFI_AP_PROCEDURE)DynamicSiLibraryPpi->EnableMcaOnCa= cheableMmio, + Index, + 0, + NULL + ); + } + + // + // All sockets are programmed, skip checking rest of threads + // + if (TotalSockets =3D=3D 0) { + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + + Function to set all MTRRs on the current thread to the MTRR set passed i= n. + + @param MtrrSettings - Pointer to MTRR Settings to use + + @retval None + +**/ +VOID +SetAllMtrrs( + VOID *MtrrSettings +) +{ + MtrrSetAllMtrrs((MTRR_SETTINGS*)MtrrSettings); +} + +/** + + Function that analyzes memory length passed in to see if there is an + appropriate address to perform a more efficient top down coverage of + the memory range. At this address bit, it is more efficient to overshoot + memory range with WB cache type and cover the gap with UC cache type. + + @param MemoryLength - Memory length of entire memory region + + @retval Zero - No efficient top down approaches found. More = efficient + to cover memory range conventional way (bottom= up). + PwrOfTwo Value - PowerOfTwo bit where the top down approach is = most efficient + +**/ +UINT64 +FindTopDownPowerOfTwo ( + IN UINT64 MemoryLength + ) +{ + UINT8 Index; + BOOLEAN FoundOne =3D FALSE; + UINT8 ZeroCount =3D 0; + UINT8 OnesCount =3D 0; + UINT64 TopDownBit =3D 0; + UINT8 MtrrSavings =3D 0; + + for (Index =3D 0; Index < 64; Index++){ + if (MemoryLength & LShiftU64(1, Index)) { + OnesCount++; + FoundOne =3D TRUE; + } else { + // + // If there are more 1's than 0's plus 2 between least significant b= it set + // and current bit under test, then top down approach is more effici= ent. + // Continue to loop through memory length to look for more efficienc= ies + // and compare them against previous efficiencies found to pick best= power of two. + // + if (((ZeroCount + 2) < OnesCount) && ((OnesCount - (ZeroCount + 2)) = > MtrrSavings)) { + TopDownBit =3D LShiftU64(1, (Index - 1)); + MtrrSavings =3D OnesCount - (ZeroCount + 2); + } + if (FoundOne) { + ZeroCount++; + } + } + } + + // + // MtrrLib can handle this case efficiently + // + if (TopDownBit =3D=3D GetPowerOfTwo64(MemoryLength)) { + TopDownBit =3D 0; + } + + return TopDownBit; +} + +/** + + Recalculate the memory length to prevent MTRR out of resource error. + + @param MemoryLength - Memory Length that we want to truncate + + @retval UINT64 - New truncated memory length + +**/ +UINT64 +MemLengthRecalculation ( + IN UINT64 MemoryLength + ) +{ + UINT8 BitIndex; + + for (BitIndex =3D 0;BitIndex < 64; BitIndex++) { + if ((RShiftU64(MemoryLength, BitIndex) & 1) =3D=3D 1) { + // + // Clear lowest power of two bit found + // + MemoryLength &=3D ~LShiftU64(1, BitIndex); + break; + } + } + return MemoryLength; +} + +/** + + Sets the uncached part of upper memory as reserved to prevent OS from us= ing. + The uncached region will always be at the top of high memory. + + @param OriginalMemoryLength - Original top of memory value + @param NewMemoryLength - New memory range used for successful pr= ogramming + + @retval None + +**/ +VOID +ReserveUncachedMemory ( + IN UINT64 OriginalMemoryLength, + IN UINT64 NewMemoryLength + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceHob; + VOID *HobStart; + UINT64 TempLength; + + HobStart =3D GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + // + // Scan resource descriptor hobs to set our required range attribute as = tested + // + for (Hob.Raw =3D HobStart; !END_OF_HOB_LIST(Hob); Hob.Raw =3D GET_NEXT_H= OB(Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + ResourceHob =3D Hob.ResourceDescriptor; + if ((ResourceHob->PhysicalStart >=3D NewMemoryLength) && + ((ResourceHob->PhysicalStart + ResourceHob->ResourceLength) <=3D O= riginalMemoryLength)) { + // + // Range is completely included in the uncached area, mark as test= ed + // + ResourceHob->ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } else if ((ResourceHob->PhysicalStart < NewMemoryLength) && + (ResourceHob->PhysicalStart + ResourceHob->ResourceLength > NewMem= oryLength)) { + // + // Shrink previous HOB to base of uncached region, create new hob = to cover uncached space + // + TempLength =3D ResourceHob->ResourceLength; + ResourceHob->ResourceLength =3D NewMemoryLength - ResourceHob->Phy= sicalStart; + BuildResourceDescriptorHob( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ), + ResourceHob->PhysicalStart + ResourceHob->ResourceLength, + TempLength - ResourceHob->ResourceLength + ); + if ((ResourceHob->PhysicalStart + ResourceHob->ResourceLength + + (TempLength - ResourceHob->ResourceLength)) =3D=3D OriginalMemor= yLength) { + break; + } + } + if (ResourceHob->PhysicalStart + ResourceHob->ResourceLength =3D=3D = OriginalMemoryLength) { + break; + } + } + } + + HobStart =3D GetFirstHob (EFI_HOB_TYPE_MEMORY_ALLOCATION); + // + // Scan memory allocation hobs to make sure this range is free + // + for (Hob.Raw =3D HobStart; !END_OF_HOB_LIST(Hob); Hob.Raw =3D GET_NEXT_H= OB(Hob)) { + if (GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_MEMORY_ALLOCATION) { + if ((Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress > NewMe= moryLength) && + (OriginalMemoryLength > Hob.MemoryAllocation->AllocDescriptor.Memo= ryBaseAddress)) { + // + // If hob range is above the range we want to reserve, set limit t= o that base. + // + OriginalMemoryLength =3D Hob.MemoryAllocation->AllocDescriptor.Mem= oryBaseAddress; + } else if ((Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress + + Hob.MemoryAllocation->AllocDescriptor.MemoryLength - 1) > NewMemor= yLength) { + // + // If there is a range allocated that starts below but comes into = the reserved range, + // adjust the base so it starts above previous allocation + // + NewMemoryLength =3D Hob.MemoryAllocation->AllocDescriptor.MemoryBa= seAddress + + Hob.MemoryAllocation->AllocDescriptor.MemoryLength; + } + } + } + + // + // Create hob to reserve the memory + // + if (NewMemoryLength < OriginalMemoryLength) { + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)NewMemoryLength, + OriginalMemoryLength - NewMemoryLength, + EfiReservedMemoryType + ); + } +} + +/** + Update MTRR setting in EndOfPei phase. + This function will clear temporary memory (CAR) phase MTRR settings + and configure MTRR to cover permanent memory. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 LowUncableBase; + UINT64 MemoryBase; + UINT64 TempQword; + UINT64 MemoryLength; + UINT64 TempMemoryLength; + UINT64 OriginalMemoryLength; + UINT64 TopDownBit; + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_INFO *PlatformInfo; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *IioUds; + MTRR_SETTINGS MtrrSettings; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA_GUID; + EFI_PEI_MP_SERVICES_PPI *mPeiMpServices =3D NULL; + EFI_BOOT_MODE BootMode; + CONST EFI_PEI_SERVICES ** PeiServices; + + + PeiServices =3D GetPeiServicesTablePointer(); + BootMode =3D GetBootModeHob(); + if (BootMode !=3D BOOT_ON_S3_RESUME) { + // + // Get required HOBs to be used to generate MTRR programming + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + if (GuidHob =3D=3D NULL) { + ASSERT(GuidHob !=3D NULL); + return EFI_NOT_FOUND; + } + IioUds =3D GET_GUID_HOB_DATA (GuidHob); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT(GuidHob !=3D NULL); + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + // + // Calculate the low uncacheable base address + // + if (IioUds->PlatformData.PciExpressBase < IioUds->PlatformData.PlatGlo= balMmio32Base) { + LowUncableBase =3D IioUds->PlatformData.PciExpressBase; + } else { + LowUncableBase =3D IioUds->PlatformData.PlatGlobalMmio32Base; + } + + LowUncableBase &=3D (0x0FFF00000); + + // + // Reset all Mtrrs to 0 including fixed MTRR and variable MTRR + // + ZeroMem(&MtrrSettings, sizeof(MTRR_SETTINGS)); + + // + // Set fixed cache for memory range below 1MB + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + 0, + 0xA0000, + EFI_CACHE_WRITEBACK + ); + ASSERT_EFI_ERROR(Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + 0xA0000, + 0x60000, + EFI_CACHE_UNCACHEABLE + ); + ASSERT_EFI_ERROR(Status); + + // + // Base set to 1mb due to MtrrLib programming method + // + MemoryBase =3D BASE_1MB; + MemoryLength =3D LowUncableBase; + + Status =3D (*PeiServices)->GetHobList (PeiServices, &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYST= EM_MEMORY) || + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMO= RY_MAPPED_IO && + (Hob.ResourceDescriptor->ResourceAttribute & EFI_RESOURCE_ATTR= IBUTE_WRITE_BACK_CACHEABLE)) || + (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMO= RY_RESERVED && + (Hob.ResourceDescriptor->ResourceAttribute & EFI_RESOURCE_ATT= RIBUTE_WRITE_BACK_CACHEABLE))) { + if (Hob.ResourceDescriptor->PhysicalStart > EFI_MAX_ADDRESS) { + TempQword =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Reso= urceDescriptor->ResourceLength; + if (TempQword > MemoryLength) { + MemoryLength =3D TempQword; + } + } + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + TempMemoryLength =3D MemoryLength; + OriginalMemoryLength =3D MemoryLength; + + DEBUG((DEBUG_ERROR, "Total Memory size: 0x%lx\n", MemoryLength)); + + Status =3D EFI_SUCCESS; + // + // Loop will continue until MTRR programming is successfully done. + // All regions reserved in this loop are considered essential regions + // If any of them fail to fit, memory is truncated by lowest power of + // two until all regions fit into the programming + // + do { + if (Status =3D=3D RETURN_OUT_OF_RESOURCES){ + // + // Ran out of MTRRs: lower top of high memory by lowest power of t= wo bit and retry + // + MemoryLength =3D MemLengthRecalculation (TempMemoryLength); + DEBUG((DEBUG_ERROR, "MTRR: %r, attempting: 0x%lx\n", Status, Memor= yLength)); + // + // Restore the MemoryBase to its original value, save MemoryLength + // + MemoryBase =3D BASE_1MB; + TempMemoryLength =3D MemoryLength; + ZeroMem(&(MtrrSettings.Variables), sizeof(MTRR_VARIABLE_SETTINGS)); + } + + TopDownBit =3D FindTopDownPowerOfTwo(MemoryLength); + + // + // If TopDownBit has a value, then we found a more efficient address= length + // to use a top down approach. We will walk through the full addres= s length to + // program MTRRs individually. BASE_1MB fixups are due to MtrrLib p= rogram method. + // + if(TopDownBit){ + DEBUG((DEBUG_INFO, "Efficient Top Down Power of Two =3D %lx\n\n", = TopDownBit)); + while (MemoryLength !=3D 0) { + if (GetPowerOfTwo64(MemoryLength) =3D=3D TopDownBit) { + // + // Overshoot address with WB and cover remaining gap with UC + // + TempQword =3D MemoryLength; + MemoryLength =3D LShiftU64(GetPowerOfTwo64 (MemoryLength), 1); + + if(MemoryBase =3D=3D BASE_1MB) { + MemoryLength -=3D BASE_1MB; + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + if(MemoryBase =3D=3D BASE_1MB) { + MemoryBase =3D 0; + MemoryLength +=3D BASE_1MB; + } + + MemoryBase +=3D TempQword; + MemoryLength -=3D TempQword; + + // + // Program UC region gap between top of memory and WB MTRR + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength, + EFI_CACHE_UNCACHEABLE + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + MemoryLength =3D 0; + } else { + // + // Grow next power of two upwards and adjust base and length + // + TempQword =3D GetPowerOfTwo64(MemoryLength); + MemoryLength -=3D TempQword; + + if(MemoryBase =3D=3D BASE_1MB) { + TempQword -=3D BASE_1MB; + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + TempQword, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + break; + } + + MemoryBase +=3D TempQword; + } + } + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + } else { + // + // Create a WB region for the entire memory region + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + MemoryBase, + MemoryLength - BASE_1MB, + EFI_CACHE_WRITEBACK + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + } + + // + // Punch UC hole for lower MMIO region + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + LowUncableBase, + EFI_MAX_ADDRESS - LowUncableBase + 1, + EFI_CACHE_UNCACHEABLE + ); + + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + continue; + } + + } while (Status =3D=3D RETURN_OUT_OF_RESOURCES); + // + // Assert if there was an error other than resource issue + // + ASSERT_EFI_ERROR (Status); + + // + // Set PSMI Trace Region to uncached + // + if (PlatformInfo->MemData.PsmiUcTraceRegionSize !=3D 0) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings( + &MtrrSettings, + PlatformInfo->MemData.PsmiUcTraceRegionBase, + PlatformInfo->MemData.PsmiUcTraceRegionSize, + EFI_CACHE_UNCACHEABLE + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "PSMI- Could not set Trace Region MemType to U= C\n")); + } + } + + // + // Set the calculated MTRR settings for the BSP + // + MtrrSetAllMtrrs (&MtrrSettings); + + // + // Need to mark the uncached memory as reserved + // + if (OriginalMemoryLength > TempMemoryLength) { + DEBUG((DEBUG_ERROR, "New TOHM: 0x%lx, Previous: 0x%lx\n", TempMemory= Length, OriginalMemoryLength)); + ReserveUncachedMemory (OriginalMemoryLength, TempMemoryLength); + } + } + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiMpServicesPpiGuid, + 0, + NULL, + &mPeiMpServices + ); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + if(!EFI_ERROR(Status)){ + // + // Sync all AP MTRRs with BSP + // + Status =3D mPeiMpServices->StartupAllAPs ( + PeiServices, + mPeiMpServices, + (EFI_AP_PROCEDURE)SetAllMtrrs, + FALSE, + 0, + (VOID*)&MtrrSettings + ); + } + } + + PkgMpEnableMcaOnCacheableMmio (PeiServices, mPeiMpServices); + + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/Set= CacheMtrrLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrL= ib/SetCacheMtrrLib.inf new file mode 100644 index 0000000000..6f21d1ea72 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SetCacheMtrrLib/SetCacheMt= rrLib.inf @@ -0,0 +1,55 @@ +## @file +# +# @copyright +# Copyright 2020 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 7E5407A1-0058-4617-AAEC-ACB0F74B4A1F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib|PEIM + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + HobLib + MtrrLib + PeiServicesLib + BaseMemoryLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + gEfiPlatformInfoGuid ## CONSUMES + +[Ppis] + gEfiPeiMpServicesPpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/PchPolicyUpdateUsb.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/Silic= onPolicyUpdateLib/PchPolicyUpdateUsb.c new file mode 100644 index 0000000000..c4c5d9aaba --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Pch= PolicyUpdateUsb.c @@ -0,0 +1,152 @@ +/** @file + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// EDK and EDKII have different GUID formats +// +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ) +/*++ + +Routine Description: + + This function performs PCH USB Platform Policy initialzation + +Arguments: + PchUsbConfig Pointer to PCH_USB_CONFIG data buffer + SetupVariables Pointer to Setup variable + PlatformType PlatformType specified + PlatformFlavor PlatformFlavor specified + BoardType BoardType specified + +Returns: + +--*/ +{ + UINTN PortIndex; +#ifdef TESTMENU_FLAG + UINT8 Index; +#endif + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + PchUsbConfig->UsbPrecondition =3D PchRcVariables->UsbPrecondition; + + for (PortIndex =3D 0; PortIndex < DynamicSiLibraryPpi->GetPchXhciMaxUs= b2PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbHsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb20[PortIndex].Enable =3D FALSE; + } + } + for (PortIndex =3D 0; PortIndex < DynamicSiLibraryPpi->GetPchXhciMaxUs= b3PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbSsPort[PortIndex] =3D=3D 1) { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } else { + PchUsbConfig->PortUsb30[PortIndex].Enable =3D FALSE; + } + } + + for (PortIndex =3D 0; PortIndex < PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS; Po= rtIndex++) { + PchUsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Petxiset); + PchUsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Txiset); + PchUsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Predeemp); + PchUsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D (UINT8)(((USB2_PH= Y_PARAMETERS *)Usb20AfeParams)[PortIndex].Pehalfbit); + } + + // + // xDCI (USB device) related settings from setup variable + // + if(PchRcVariables->PchXdciSupport =3D=3D 1) { + PchUsbConfig->XdciConfig.Enable=3D TRUE; + } else { + PchUsbConfig->XdciConfig.Enable=3D FALSE; + } + +#ifdef TESTMENU_FLAG + // + // Need to clear UsbEPTypeLockPolicy[8] and UsbEPTypeLockPolicy[16] sinc= e this is not assign in the setup + // + PchRcVariables->UsbEPTypeLockPolicy[8] =3D 0; + SetupPchRcVariablesVariables->UsbEPTypeLockPolicy[16] =3D 0; + + // + // Update USB EP Type Lock Policy Settings + // + for (Index =3D 0; Index < 24; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicy |=3D (UI= NT32) (PchRcVariables->UsbEPTypeLockPolicy[Index] << Index); + } + + for (Index =3D 0; Index < 16; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicyPortContr= ol1 |=3D (UINT32) (PchRcVariables->RootPortPolicyControl[Index] << Index *= 2); + } + + for (Index =3D 16; Index < 20; Index++) { + PchUsbConfig->Usb30EpTypeLockPolicySettings.EPTypeLockPolicyPortContr= ol2 |=3D (UINT32) (PchRcVariables->RootPortPolicyControl[Index] << (Index = - 16) * 2); + } + + // + // Remark: Can be disabled only for debugging process!!! + // + PchUsbConfig->TstMnuControllerEnabled =3D PchRcVariables->XhciEnabled; + // + // SSIC debug mode + // + PchUsbConfig->TstMnuSsicHalt =3D PchRcVariables->XhciSsicHalt; +#endif + // + // XHCI USB Over Current Pins disabled, update it based on setup option. + // + PchUsbConfig->XhciOcMapEnabled =3D PchRcVariables->XhciOcMapEnabled; + + // + // XHCI Wake On USB configured based on user input through setup option + // + PchUsbConfig->XhciWakeOnUsb =3D SetupVariables->XhciWakeOnUsbEnabled; + // + // XHCI option to disable MSIs + // + PchUsbConfig->XhciDisMSICapability =3D PchRcVariables->XhciDisMSICapabil= ity; + + // + // Platform Board programming per the layout of each port. + // + // OC Map for USB2 Ports + for (PortIndex=3D0;PortIndexPortUsb20[PortIndex].OverCurrentPin =3D (UINT8)((USB_OVE= RCURRENT_PIN *)Usb20OverCurrentMappings)[PortIndex]; + } + + // OC Map for USB3 Ports + for (PortIndex=3D0;PortIndexPortUsb30[PortIndex].OverCurrentPin =3D (UINT8)((USB_OVE= RCURRENT_PIN *)Usb30OverCurrentMappings)[PortIndex]; + } + +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/S= iliconPolicyUpdateLib/SiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..25a27eee39 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.c @@ -0,0 +1,778 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialz= ation. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +STATIC +EFI_STATUS +InstallPcieDeviceTable ( + IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable + ) +{ + EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc; + EFI_STATUS Status; + + DeviceTablePpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (size= of (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (DeviceTablePpiDesc !=3D NULL); + + if (DeviceTablePpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + DeviceTablePpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_D= ESCRIPTOR_TERMINATE_LIST; + DeviceTablePpiDesc->Guid =3D &gPchPcieDeviceTablePpiGuid; + DeviceTablePpiDesc->Ppi =3D DeviceTable; + + Status =3D PeiServicesInstallPpi (DeviceTablePpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the d= river + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 BmcRootPort; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + USB_OVERCURRENT_PIN *Usb20OverCurrentMappings =3D NULL; + USB_OVERCURRENT_PIN *Usb30OverCurrentMappings =3D NULL; + USB2_PHY_PARAMETERS *Usb20AfeParams =3D NULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_SETUP *PchRcVariables; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + SetupVariables =3D PcdGetPtr(PcdSetup); + PchRcVariables =3D PcdGetPtr(PcdPchSetup); + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route =3D PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable =3D TRUE; + PchPolicy->LanConfig.K1OffEnable =3D PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable =3D FALSE; + } + + PchPolicy->SataConfig.Enable =3D PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable =3D PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable =3D TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun =3D FALSE; + PchPolicy->PchConfig.Crid =3D PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm =3D PchRcVariables->PchSerm; + + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + PchPolicy->SmbusConfig.SmbusIoBase =3D PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode =3D PchRcVariables->SataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode =3D=3D TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D PchRcVariables-= >SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug =3D PchRcVa= riables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp =3D PchRcVa= riables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External =3D PchRcVa= riables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].InterlockSw =3D PchRcVa= riables->SataMechanicalSw[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp =3D PchRcVa= riables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcVa= riables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal =3D PchRcVa= riables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal =3D PchRcVa= riables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive =3D PchRcVa= riables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId =3D PchRcVariables->SataAlte= rnateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataRa= idLoadEfiDriver[0]; + } + PchPolicy->SataConfig.Rst.Raid0 =3D PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 =3D PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 =3D PchRcVariables->SataRaidR1= 0; + PchPolicy->SataConfig.Rst.Raid5 =3D PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt =3D PchRcVariables->SataRaidIr= rt; + PchPolicy->SataConfig.Rst.OromUiBanner =3D PchRcVariables->SataRaidOu= b; + PchPolicy->SataConfig.Rst.HddUnlock =3D PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate =3D PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly =3D PchRcVariables->SataRaidIo= oe; + PchPolicy->SataConfig.Rst.SmartStorage =3D PchRcVariables->SataRaidSr= t; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchRcVariables->SataRaidOr= omDelay; + + PchPolicy->SataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->SataConfig.SalpSupport =3D PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode =3D PchRcVariables->SataTestMode; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata =3D=3D TRUE) && (PchRcVariables->SataInte= rfaceMode =3D=3D PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = =3D PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode =3D PchRcVariables->sSataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxsSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode =3D=3D TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D PchRcVariables= ->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug =3D PchRcV= ariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp =3D PchRcV= ariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External =3D PchRcV= ariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp =3D PchRcV= ariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcV= ariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal =3D PchRcV= ariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal =3D PchRcV= ariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive =3D PchRcV= ariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId =3D PchRcVariables->sSataAl= ternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataR= aidLoadEfiDriver[1]; + } + PchPolicy->sSataConfig.Rst.Raid0 =3D PchRcVariables->sSataRaid= R0; + PchPolicy->sSataConfig.Rst.Raid1 =3D PchRcVariables->sSataRaid= R1; + PchPolicy->sSataConfig.Rst.Raid10 =3D PchRcVariables->sSataRaid= R10; + PchPolicy->sSataConfig.Rst.Raid5 =3D PchRcVariables->sSataRaid= R5; + PchPolicy->sSataConfig.Rst.Irrt =3D PchRcVariables->sSataRaid= Irrt; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D PchRcVariables->sSataRaid= Oub; + PchPolicy->sSataConfig.Rst.HddUnlock =3D PchRcVariables->sSataHddl= k; + PchPolicy->sSataConfig.Rst.LedLocate =3D PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D PchRcVariables->sSataRaid= Iooe; + PchPolicy->sSataConfig.Rst.SmartStorage =3D PchRcVariables->sSataRaid= Srt; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchRcVariables->sSataRaid= OromDelay; + + PchPolicy->sSataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->sSataConfig.SalpSupport =3D PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode =3D PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm !=3D PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm !=3D 0xFF) { + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm =3D FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =3D%x\n", PchPolicy->D= miConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating =3D SetupVariables= ->PcieClockGatingDisabled; + PchPolicy->PcieConfig.EnablePort8xhDecode =3D PchRcVariables->= PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex =3D PchRcVariables->= Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite =3D PchRcVariables->= PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode =3D PchRcVariables->= PcieComplianceTestMode; + + /// + /// Temporary WA: Force Link speed on BMC board to GEN1 + /// TODO: remove this WA together with Purley platforms support + /// + BmcRootPort =3D PcdGet8 (PcdOemSkuBmcPciePortNumber); + if ((BmcRootPort !=3D 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables-= >PcieRootPortSpeed))) { + DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRo= otPort)); + PchRcVariables->PcieRootPortSpeed[BmcRootPort] =3D 1; + } + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = =3D PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = =3D (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = =3D PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = =3D PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = =3D PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = =3D PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = =3D PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = =3D PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = =3D PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = =3D PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = =3D PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = =3D PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = =3D PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = =3D PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = =3D PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = =3D PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = =3D PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = =3D PchRcVariables->PcieRootPortEqPh3Method[Index]; + PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = =3D TRUE; + } + PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = =3D FALSE; + + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D PchRcVariables->Pc= ieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D PchRcVariables->Pc= ieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm =3D PchRcVariable= s->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp =3D PchRcVariable= s->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = =3D PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = =3D PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = =3D PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = =3D PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = =3D PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF= (SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = =3D VTdSupport; + if (DynamicSiLibraryPpi->X2ApicIdDetect (NULL)) { + PchPolicy->PcieConfig.VTdSupport =3D TRUE; + } + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable =3D PchRcVariables->PchHdA= udio; + PchPolicy->HdAudioConfig.DspEnable =3D FALSE; + PchPolicy->HdAudioConfig.Pme =3D PchRcVariables->PchHdA= udioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership =3D PchRcVariables->PchHdA= udioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage =3D PchRcVariables->PchHdA= udioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect =3D TRUE; //iDisp is perm= anently disabled + for(Index =3D 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |=3D (UINT32)(PchRcVariables->= PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index =3D 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |=3D (UINT32)(PchRcVariables-= >PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType =3D PchRcVariables->DfxHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock =3D PchRcVariables->PchRtcLoc= k; + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.GpioLockDown =3D PchRcVariables->PchGpioLo= ckDown; + PchPolicy->LockDownConfig.TcoLock =3D TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock =3D TRUE; + PchPolicy->P2sbConfig.PsfUnlock =3D TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock =3D FALSE; + PchPolicy->P2sbConfig.PsfUnlock =3D FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal =3D PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + + PchPolicy->PmConfig.PmcReadDisable =3D TRUE; + + if (PchRcVariables->PchAdrEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn =3D PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel =3D PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset =3D PchRcVariables->AdrHost= PartitionReset; + } + if (PchRcVariables->AdrTimerEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn =3D PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal !=3D ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal =3D PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal !=3D ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal =3D PchRcVariables->AdrMultiplie= rVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement !=3D FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard !=3D FALSE) || (PchRcVariables->= ExttsViaTsOnDimm !=3D FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pi= nSelection =3D 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pi= nSelection =3D 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable =3D FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D PchRcVariables->PchIoApic2= 4119Entries; + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_IOAPIC; + PchPolicy->IoApicConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_IOAP= IC; + PchPolicy->IoApicConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_IO= APIC; + + PchPolicy->HpetConfig.BdfValid =3D 1; + PchPolicy->HpetConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_HPET; + PchPolicy->HpetConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_HPET; + PchPolicy->HpetConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_HPET= 0; + + PchPolicy->PchInterruptConfig.ShutdownPolicySelect =3D PchRcVaria= bles->ShutdownPolicySelect; + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol =3D PchRcVaria= bles->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D PchRcVaria= bles->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable =3D PchRcVaria= bles->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable =3D PchRcVaria= bles->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx =3D PchRcVaria= bles->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc =3D PchRcVaria= bles->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D PchRcVaria= bles->PciePllSsc; + PchPolicy->PmConfig.Dwr_BmcRootPort =3D PchRcVaria= bles->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL =3D PchRcVaria= bles->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT =3D PchRcVaria= bles->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT =3D PchRcVaria= bles->DwrEn_IEWDT; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec =3D PchRcVariables->EnableCl= ockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + if (PchRcVariables->ThermalDeviceEnable =3D=3D PchThermalDeviceAuto) { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceEnabl= edPci; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchRcVariables->Therm= alDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = =3D TRUE; + + /// + ///Set PCHHOT# to 85C. + /// + PchPolicy->ThermalConfig.PchHotLevel =3D 0x10E; + + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn =3D DCI_DISABLE; + PchPolicy->DciConfig.DciAutoDetect =3D DCI_DISABLE; + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + if (PchRcVariables->PchSirqMode =3D=3D 0) { + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode =3D PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass =3D PchRcVariables->DmiLinkDo= wnHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D PchRcVariables->PcieDmiS= topAndScreamEnable; + + // + // Update Pch Usb Config + // + PlatformGetUsbOcMappings ( + (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings, + (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings, + (USB2_PHY_PARAMETERS **) &Usb20AfeParams + ); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + + // + // Install PCIe device override table + // + InstallPcieDeviceTable (mPcieDeviceTable); + + // + // Initialize PTSS board specyfic HSIO settings + // + InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy); + + + PchPolicy->PchTraceHubConfig.PchTraceHubHide =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library= /SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..5c9d1a5a06 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.inf @@ -0,0 +1,64 @@ +## @file +# Module Infomation file +# +# @copyright +# Copyright 2011 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLib.c + PchPolicyUpdateUsb.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + HobLib + IoLib + PcdLib + UbaPlatLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + +[Guids] + gEfiAcpiVariableGuid + +[Ppis] + gPchPcieDeviceTablePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLibFsp.c b/Platform/Intel/WhitleyOpenBoardPkg/Librar= y/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c new file mode 100644 index 0000000000..f9fa6dfe64 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.c @@ -0,0 +1,770 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialz= ation. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +STATIC +EFI_STATUS +InstallPcieDeviceTable ( + IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable + ) +{ + EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc; + EFI_STATUS Status; + + DeviceTablePpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (size= of (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (DeviceTablePpiDesc !=3D NULL); + + if (DeviceTablePpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + DeviceTablePpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_D= ESCRIPTOR_TERMINATE_LIST; + DeviceTablePpiDesc->Guid =3D &gPchPcieDeviceTablePpiGuid; + DeviceTablePpiDesc->Ppi =3D DeviceTable; + + Status =3D PeiServicesInstallPpi (DeviceTablePpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_SETUP *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings, + IN VOID *Usb20AfeParams + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the d= river + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 BmcRootPort; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + USB_OVERCURRENT_PIN *Usb20OverCurrentMappings=3DNULL; + USB_OVERCURRENT_PIN *Usb30OverCurrentMappings=3DNULL; + USB2_PHY_PARAMETERS *Usb20AfeParams =3D NULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_SETUP *PchRcVariables; + FSPM_UPD *FspmUpd; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + FspmUpd =3D (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress); + ASSERT (FspmUpd !=3D NULL); + SetupVariables =3D PcdGetPtr(PcdSetup); + PchRcVariables =3D PcdGetPtr(PcdPchSetup); + + LpcBaseAddress =3D DynamicSiLibraryPpi->MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route =3D PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable =3D TRUE; + PchPolicy->LanConfig.K1OffEnable =3D PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable =3D FALSE; + } + + PchPolicy->SataConfig.Enable =3D PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable =3D PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable =3D TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun =3D FALSE; + PchPolicy->PchConfig.Crid =3D PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm =3D PchRcVariables->PchSerm; + + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + PchPolicy->SmbusConfig.SmbusIoBase =3D PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode =3D PchRcVariables->SataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode =3D=3D TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable =3D PchRcVariables-= >SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug =3D PchRcVa= riables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp =3D PchRcVa= riables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External =3D PchRcVa= riables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp =3D PchRcVa= riables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcVa= riables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal =3D PchRcVa= riables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal =3D PchRcVa= riables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive =3D PchRcVa= riables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId =3D PchRcVariables->SataAlte= rnateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataRa= idLoadEfiDriver[0]; + } + PchPolicy->SataConfig.Rst.Raid0 =3D PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 =3D PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 =3D PchRcVariables->SataRaidR1= 0; + PchPolicy->SataConfig.Rst.Raid5 =3D PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt =3D PchRcVariables->SataRaidIr= rt; + PchPolicy->SataConfig.Rst.OromUiBanner =3D PchRcVariables->SataRaidOu= b; + PchPolicy->SataConfig.Rst.HddUnlock =3D PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate =3D PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly =3D PchRcVariables->SataRaidIo= oe; + PchPolicy->SataConfig.Rst.SmartStorage =3D PchRcVariables->SataRaidSr= t; + PchPolicy->SataConfig.Rst.OromUiDelay =3D PchRcVariables->SataRaidOr= omDelay; + + PchPolicy->SataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->SataConfig.SalpSupport =3D PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode =3D PchRcVariables->SataTestMode; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata =3D=3D TRUE) && (PchRcVariables->SataInte= rfaceMode =3D=3D PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = =3D PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = =3D FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode =3D PchRcVariables->sSataInterfaceMode; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxsSataPortNum (); + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode =3D=3D TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable =3D PchRcVariables= ->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug =3D PchRcV= ariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp =3D PchRcV= ariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External =3D PchRcV= ariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp =3D PchRcV= ariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig =3D PchRcV= ariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal =3D PchRcV= ariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal =3D PchRcV= ariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive =3D PchRcV= ariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode =3D=3D PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId =3D PchRcVariables->sSataAl= ternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad =3D PchRcVariables->SataR= aidLoadEfiDriver[0];; + } + PchPolicy->sSataConfig.Rst.Raid0 =3D PchRcVariables->sSataRaid= R0; + PchPolicy->sSataConfig.Rst.Raid1 =3D PchRcVariables->sSataRaid= R1; + PchPolicy->sSataConfig.Rst.Raid10 =3D PchRcVariables->sSataRaid= R10; + PchPolicy->sSataConfig.Rst.Raid5 =3D PchRcVariables->sSataRaid= R5; + PchPolicy->sSataConfig.Rst.Irrt =3D PchRcVariables->sSataRaid= Irrt; + PchPolicy->sSataConfig.Rst.OromUiBanner =3D PchRcVariables->sSataRaid= Oub; + PchPolicy->sSataConfig.Rst.HddUnlock =3D PchRcVariables->sSataHddl= k; + PchPolicy->sSataConfig.Rst.LedLocate =3D PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly =3D PchRcVariables->sSataRaid= Iooe; + PchPolicy->sSataConfig.Rst.SmartStorage =3D PchRcVariables->sSataRaid= Srt; + PchPolicy->sSataConfig.Rst.OromUiDelay =3D PchRcVariables->sSataRaid= OromDelay; + + PchPolicy->sSataConfig.EnclosureSupport =3D TRUE; + + PchPolicy->sSataConfig.SalpSupport =3D PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode =3D PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm !=3D PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm !=3D 0xFF) { + PchPolicy->DmiConfig.DmiAspm =3D TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm =3D FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =3D%x\n", PchPolicy->D= miConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating =3D SetupVariables= ->PcieClockGatingDisabled; + PchPolicy->PcieConfig.EnablePort8xhDecode =3D PchRcVariables->= PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex =3D PchRcVariables->= Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite =3D PchRcVariables->= PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode =3D PchRcVariables->= PcieComplianceTestMode; + + /// + /// Temporary WA: Force Link speed on BMC board to GEN1 + /// TODO: remove this WA together with Purley platforms support + /// + BmcRootPort =3D PcdGet8(PcdOemSkuBmcPciePortNumber); + if ((BmcRootPort !=3D 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables-= >PcieRootPortSpeed))) { + DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRo= otPort)); + PchRcVariables->PcieRootPortSpeed[BmcRootPort] =3D 1; + } + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = =3D PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = =3D (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = =3D PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = =3D PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = =3D PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = =3D PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = =3D PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = =3D PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = =3D PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = =3D PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = =3D PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = =3D PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = =3D PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = =3D PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = =3D PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = =3D PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = =3D PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = =3D PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = =3D PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = =3D PchRcVariables->PcieRootPortEqPh3Method[Index]; + PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = =3D TRUE; + } + PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = =3D FALSE; + + for (Index =3D 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); = ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm =3D PchRcVariables->Pc= ieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp =3D PchRcVariables->Pc= ieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm =3D PchRcVariable= s->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp =3D PchRcVariable= s->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = =3D PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = =3D PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = =3D PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = =3D PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = =3D PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF= (SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = =3D VTdSupport; + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable =3D PchRcVariables->PchHdA= udio; + PchPolicy->HdAudioConfig.DspEnable =3D FALSE; + PchPolicy->HdAudioConfig.Pme =3D PchRcVariables->PchHdA= udioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership =3D PchRcVariables->PchHdA= udioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage =3D PchRcVariables->PchHdA= udioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer =3D 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect =3D TRUE; //iDisp is perm= anently disabled + for(Index =3D 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |=3D (UINT32)(PchRcVariables->= PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index =3D 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |=3D (UINT32)(PchRcVariables-= >PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType =3D PchRcVariables->DfxHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock =3D PchRcVariables->PchRtcL= ock; + PchPolicy->LockDownConfig.SpiEiss =3D TRUE; + PchPolicy->LockDownConfig.GlobalSmi =3D TRUE; + PchPolicy->LockDownConfig.BiosInterface =3D TRUE; + PchPolicy->LockDownConfig.GpioLockDown =3D PchRcVariables->PchGpio= LockDown; + PchPolicy->LockDownConfig.TcoLock =3D TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock =3D TRUE; + PchPolicy->P2sbConfig.PsfUnlock =3D TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock =3D FALSE; + PchPolicy->P2sbConfig.PsfUnlock =3D FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal =3D PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + + PchPolicy->PmConfig.PmcReadDisable =3D TRUE; + + if (PchRcVariables->PchAdrEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn =3D PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel =3D PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset =3D PchRcVariables->AdrHost= PartitionReset; + } + if (PchRcVariables->AdrTimerEn !=3D PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn =3D PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal !=3D ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal =3D PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal !=3D ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal =3D PchRcVariables->AdrMultiplie= rVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement !=3D FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard !=3D FALSE) || (PchRcVariables->= ExttsViaTsOnDimm !=3D FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pm= syncEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0= TransmitEnable =3D TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].Pi= nSelection =3D 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].Pi= nSelection =3D 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable =3D FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 =3D PchRcVariables->PchIoApic2= 4119Entries; + PchPolicy->IoApicConfig.BdfValid =3D 1; + PchPolicy->IoApicConfig.BusNumber =3D PCI_BUS_NUMBER_PCH_IOAPIC; + PchPolicy->IoApicConfig.DeviceNumber =3D PCI_DEVICE_NUMBER_PCH_IOAP= IC; + PchPolicy->IoApicConfig.FunctionNumber =3D PCI_FUNCTION_NUMBER_PCH_IO= APIC; + + + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol =3D PchRcVaria= bles->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride =3D PchRcVaria= bles->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable =3D PchRcVaria= bles->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable =3D PchRcVaria= bles->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx =3D PchRcVaria= bles->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc =3D PchRcVaria= bles->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts =3D TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts =3D TRUE; + PchPolicy->PmConfig.PciePllSsc =3D PchRcVaria= bles->PciePllSsc; + PchPolicy->PmConfig.Dwr_BmcRootPort =3D PchRcVaria= bles->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL =3D PchRcVaria= bles->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT =3D PchRcVaria= bles->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT =3D PchRcVaria= bles->DwrEn_IEWDT; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId =3D V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec =3D PchRcVariables->EnableCl= ockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = =3D PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = =3D TRUE; + if (PchRcVariables->ThermalDeviceEnable =3D=3D PchThermalDeviceAuto) { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchThermalDeviceEnabl= edPci; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable =3D PchRcVariables->Therm= alDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = =3D TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = =3D TRUE; + + // + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn =3D DCI_DISABLE; + PchPolicy->DciConfig.DciAutoDetect =3D DCI_DISABLE; + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable =3D TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse =3D PchSfpw4Clk; + if (PchRcVariables->PchSirqMode =3D=3D 0) { + PchPolicy->SerialIrqConfig.SirqMode =3D PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode =3D PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable =3D TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass =3D PchRcVariables->DmiLinkDo= wnHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable =3D PchRcVariables->PcieDmiS= topAndScreamEnable; + + // + // Update Pch Usb Config + // + PlatformGetUsbOcMappings ( + (USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings, + (USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings, + (USB2_PHY_PARAMETERS **) &Usb20AfeParams + ); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings, + Usb20AfeParams + ); + + // + // Install PCIe device override table + // + InstallPcieDeviceTable (mPcieDeviceTable); + + // + // Initialize PTSS board specyfic HSIO settings + // + InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy); + + + PchPolicy->PchTraceHubConfig.PchTraceHubHide =3D TRUE; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLibFsp.inf b/Platform/Intel/WhitleyOpenBoardPkg/Libr= ary/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..344374a85f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.inf @@ -0,0 +1,68 @@ +## @file +# Module Infomation file +# +# @copyright +# Copyright 2011 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLibFsp.c + PchPolicyUpdateUsb.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec + +[LibraryClasses] + HobLib + IoLib + PcdLib + UbaPlatLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES + +[Guids] + gEfiAcpiVariableGuid + +[Ppis] + gPchPcieDeviceTablePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/Smm= SpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..a5bcb5e2f2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSp= iFlashCommonLib.inf @@ -0,0 +1,57 @@ +## @file +# SMM Library instance of Spi Flash Common Library Class +# +# @copyright +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + PciLib + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + gDynamicSiLibrarySmmProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid AND + gEfiSmmSwDispatch2ProtocolGuid AND + gDynamicSiLibrarySmmProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SpiFlashCommon.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlash= CommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..d28b453580 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFl= ashCommon.c @@ -0,0 +1,237 @@ +/** @file + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces + for module use. + + @copyright + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// FlashAreaBaseAddress and Size for boottime and runtime usage. +// +UINTN mFlashAreaBaseAddress =3D 0; +UINTN mFlashAreaSize =3D 0; + +/** + This function enable SPI.MSE(Memory Space Enable) Bit1 if it is disabled. + in some cases, the SPI.MSE will be disabled. For example, it is disabled= under PCI bus initialization. + + @param None. + + @retval None. + +**/ +VOID +SpiMemorySpaceCheckandEnable( + VOID + ) +{ + UINTN SpiMemAddress; + UINT32 SpiCmdData; + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_SMM_PROTOCOL *DynamicSiLibrarySmmProtocol =3D NULL; + + Status =3D gSmst->SmmLocateProtocol (&gDynamicSiLibrarySmmProtocolGuid, = NULL, &DynamicSiLibrarySmmProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + SpiMemAddress =3D DynamicSiLibrarySmmProtocol->MmPciBase ( DEFAULT_PCI_B= US_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI); + + SpiCmdData =3D MmioRead32 (SpiMemAddress + PCI_COMMAND_OFFSET); + + if (!(SpiCmdData & BIT1)) { //Bit1: Memory Space Enable + SpiCmdData |=3D BIT1; + MmioWrite32(SpiMemAddress + PCI_COMMAND_OFFSET, SpiCmdData); + } + +} + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + SpiMemorySpaceCheckandEnable(); + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + SpiMemorySpaceCheckandEnable(); + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLi= b/SpiFlashCommonSmmLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSp= iFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..de0b762f00 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFl= ashCommonSmmLib.c @@ -0,0 +1,55 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mFlashAreaBaseAddress; +extern UINTN mFlashAreaSize; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mFlashAreaBaseAddress =3D (UINTN)PcdGet32 (PcdFlashAreaBaseAddress); + mFlashAreaSize =3D (UINTN)PcdGet32 (PcdFlashAreaSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenc= eLibNull/DxeTcg2PhysicalPresenceLib.c b/Platform/Intel/WhitleyOpenBoardPkg/= Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.c new file mode 100644 index 0000000000..7eb37e232e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenceLibNul= l/DxeTcg2PhysicalPresenceLib.c @@ -0,0 +1,41 @@ +/** @file + NULL Tcg2PhysicalPresenceLib library instance + + @copyright + Copyright (c) 2018, Red Hat, Inc. + Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Check if the pending TPM request needs user input to confirm. + + The TPM request may come from OS. This API will check if TPM request exi= sts and need user + input to confirmation. + + @retval TRUE TPM needs input to confirm user physical presence. + @retval FALSE TPM doesn't need input to confirm user physical p= resence. + +**/ +BOOLEAN +EFIAPI +Tcg2PhysicalPresenceLibNeedUserConfirm ( + VOID + ) +{ + return FALSE; +} + +VOID +EFIAPI +Tcg2PhysicalPresenceLibProcessRequest ( + IN TPM2B_AUTH *PlatformAuth OPTIONAL + ) +{ + // + // do nothing + // +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenc= eLibNull/DxeTcg2PhysicalPresenceLib.inf b/Platform/Intel/WhitleyOpenBoardPk= g/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf new file mode 100644 index 0000000000..618917d2ff --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/Tcg2PhysicalPresenceLibNul= l/DxeTcg2PhysicalPresenceLib.inf @@ -0,0 +1,29 @@ +## @file +# NULL Tcg2PhysicalPresenceLib library instance +# +# Under SecurityPkg, the corresponding library instance will check and +# execute TPM 2.0 request from OS or BIOS; the request may ask for user +# confirmation before execution. This Null instance implements a no-op +# Tcg2PhysicalPresenceLibProcessRequest(), without user interaction. +# +# @copyright +# Copyright (C) 2018, Red Hat, Inc. +# Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeTcg2PhysicalPresenceLibNull + FILE_GUID =3D 2A6BA243-DC22-42D8-9C3D-AE3728DC7AFA + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D Tcg2PhysicalPresenceLib|DXE_DRIVER DX= E_RUNTIME_DRIVER UEFI_APPLICATION UEFI_DRIVER + +[Sources] + DxeTcg2PhysicalPresenceLib.c + +[Packages] + MdePkg/MdePkg.dec + SecurityPkg/SecurityPkg.dec diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaG= pioInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/Ub= aGpioInitLib.c new file mode 100644 index 0000000000..3fdcf2e18f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaGpioInit= Lib.c @@ -0,0 +1,145 @@ +/** @file + UbaGpioInitLib implementation. + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static GPIO_INIT_CONFIG meSPIConfig[] =3D +{ + { GPIO_SKL_H_GPP_A0, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLo= ck } },//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + { GPIO_SKL_H_GPP_A1, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_1_LAD_0_ESPI_IO_0 + { GPIO_SKL_H_GPP_A2, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_2_LAD_1_ESPI_IO_1 + { GPIO_SKL_H_GPP_A3, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_3_LAD_2_ESPI_IO_2 + { GPIO_SKL_H_GPP_A4, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadCon= figLock } },//GPP_A_4_LAD_3_ESPI_IO_3 + { GPIO_SKL_H_GPP_A5, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfi= gLock } },//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + { GPIO_SKL_H_GPP_A6, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigL= ock } },//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + { GPIO_SKL_H_GPP_A7, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLo= ck } },//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + { GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfi= gLock } },//GPP_A_8_FM_LPC_CLKRUN_N + { GPIO_SKL_H_GPP_A9, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K, GpioPadConfi= gLock } },//GPP_A_9_CLK_24M_66M_LPC0_ESPI + { GPIO_SKL_H_GPP_A10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigL= ock } },//GPP_A_10_TP_PCH_GPP_A_10 + { GPIO_SKL_H_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock= } },//GPP_A_11_FM_LPC_PME_N + { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone = } },//GPP_A_12_IRQ_PCH_SCI_WHEA_N + { GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLoc= k | GpioOutputStateLock } },//GPP_A_13_FM_EUP_LOT6_N + { GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfig= Lock } },//GPP_A_14_ESPI_RESET_N + { GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock= } },//GPP_A_15_SUSACK_N + { GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock |= GpioOutputStateLock } },// CLK_48MHZ_PCH [GPP_A_16_CLKOUT_LPC_2] +}; + + +VOID +UpdateeSPIConfiguration ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress +) +{ + UINT32 Index1; + UINT32 Index2; + + for(Index1 =3D 0; Index1 < sizeof (meSPIConfig)/sizeof (GPIO_INIT_CONFIG= ); Index1++) { + for (Index2 =3D 0; Index2 < NumberOfItems; Index2++) { + if (meSPIConfig[Index1].GpioPad =3D=3D (GpioInitTableAddress+Index2)= ->GpioPad){ + (GpioInitTableAddress + Index2)->GpioConfig =3D meSPIConfig[Index1= ].GpioConfig; + } + } + } +} + +EFI_STATUS +PlatformInitGpios ( + VOID +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + GPIO_INIT_CONFIG *GpioTable; + UINTN TableSize; + UINT32 SpiConfigValue; + GPIO_INIT_CONFIG *mPchGpioInitData =3D NULL; + VOID *HobPtr; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gUbaConfigDatabasePpiGuid, 0, NULL, &U= baConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + TableSize =3D PcdGet32(PcdOemSku_GPIO_TABLE_SIZE); + DEBUG ((DEBUG_INFO, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", Table= Size, (TableSize/sizeof (GPIO_INIT_CONFIG)) )); + Status =3D PeiServicesAllocatePool (TableSize, &GpioTable); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + GpioTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + SpiConfigValue =3D 0; + DynamicSiLibraryPpi->PchPcrRead32ByPchId (PCH_LEGACY_ID, PID_ESPISPI, R_= PCH_PCR_SPI_CONF_VALUE, &SpiConfigValue); + DEBUG((DEBUG_INFO, "SPI Config Value =3D %x; ", SpiConfigValue)); + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + DEBUG((DEBUG_INFO, "eSPI Mode\n")); + } else { + DEBUG((DEBUG_INFO, "LPC Mode\n")); + } + + if (SpiConfigValue & B_ESPI_ENABLE_STRAP) { + mPchGpioInitData =3D AllocateZeroPool((UINTN)TableSize); + if (mPchGpioInitData !=3D NULL){ + CopyMem(mPchGpioInitData, GpioTable, TableSize); + UpdateeSPIConfiguration((UINT32)(TableSize / sizeof(GPIO_INIT_CONFIG= )), mPchGpioInitData); + } else { + DEBUG ((DEBUG_ERROR, "\n*** ERROR!!!! AllocateZeroPool returned NULL= pointer when trying to allocate buffer for 'mPchGpioInitData'!!!! ***\n")); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return Status; + } + } else { + // Point to LPC config values + mPchGpioInitData =3D GpioTable; + } + + DEBUG ((DEBUG_INFO, "UBA: Start ConfigureGpio().\n")); + Status =3D DynamicSiLibraryPpi->GpioConfigurePadsByPchId (PCH_LEGACY_ID,= TableSize/sizeof (GPIO_INIT_CONFIG), mPchGpioInitData); + DEBUG ((DEBUG_INFO, "UBA: ConfigureGpio() end.\n")); + + HobPtr =3D BuildGuidDataHob ( + &gPlatformGpioConfigGuid, + mPchGpioInitData, + TableSize + ); + if (HobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PlatformInitGpios(): ERROR: BuildGuidDataHob fai= led!\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaG= pioInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/= UbaGpioInitLib.inf new file mode 100644 index 0000000000..cfcd4790e5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/UbaGpioInitLib/UbaGpioInit= Lib.inf @@ -0,0 +1,46 @@ +## @file +# +# @copyright +# Copyright 2016 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UbaGpioInitLib + FILE_GUID =3D C3597C66-784E-4215-BF24-71D8C7B5E3BE + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D UbaGpioInitLib|PEIM PEI_CORE + +[sources] + UbaGpioInitLib.c + +[LibraryClasses] + DebugLib + MemoryAllocationLib + PeiServicesLib + PcdLib + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioConfigGuid + gPlatformGpioInitDataGuid + +[Depex] + gUbaConfigDatabasePpiGuid AND + gDynamicSiLibraryPpiGuid --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 11/17] WhitleyOpenBoardPkg: Add Platform Modules Date: Mon, 12 Jul 2021 17:41:25 -0700 Message-Id: <20210713004131.1782-12-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: UUe2iO8vFry6c0Imvbt7pNUVx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136930; bh=Q3A748NaND6asUGThi18nrB1afyxcbx9h71TYw2k4Lw=; h=Cc:Date:From:Reply-To:Subject:To; b=q5gkL8xLZBRdyED6NqHtpEtqcUkoYYVuNYxDyBfmhggP/2j0cQigHNSBl5BIdoZpDrb TXEAJsgR+aRwB02Qh4ktpyN9Gu+Mw54lV+RNnhF3vUSvHc2d9nJoW+wHQVTrWTiiwdt5H KeblV9tDbJqLh57UpSkJZkV1I1EWhv1SWCM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136932212100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c | 104 +++ .../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h | 67 ++ .../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf | 70 ++ .../Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c | 704 ++++++++++++++++ .../PlatformCpuPolicy/PlatformCpuPolicy.inf | 81 ++ .../Dxe/PlatformType/PlatformType.inf | 58 ++ .../Platform/Dxe/PlatformType/PlatformTypes.c | 364 +++++++++ .../Platform/Dxe/PlatformType/PlatformTypes.h | 58 ++ .../Platform/Dxe/S3NvramSave/S3NvramSave.c | 157 ++++ .../Platform/Dxe/S3NvramSave/S3NvramSave.h | 40 + .../Platform/Dxe/S3NvramSave/S3NvramSave.inf | 52 ++ .../Platform/Pei/DummyPchSpi/DummyPchSpi.inf | 43 + .../Platform/Pei/DummyPchSpi/PchSpi.c | 383 +++++++++ .../EmulationPlatformInit.c | 124 +++ .../EmulationPlatformInit.inf | 46 ++ .../Platform/Pei/PlatformInfo/PlatformInfo.c | 761 ++++++++++++++++++ .../Platform/Pei/PlatformInfo/PlatformInfo.h | 89 ++ .../Pei/PlatformInfo/PlatformInfo.inf | 63 ++ .../ExSerialStatusCodeWorker.c | 194 +++++ .../ExStatusCodeHandlerPei.c | 111 +++ .../ExStatusCodeHandlerPei.h | 85 ++ .../ExStatusCodeHandlerPei.inf | 61 ++ .../ExReportStatusCodeRouterPei.c | 301 +++++++ .../ExReportStatusCodeRouterPei.h | 104 +++ .../ExReportStatusCodeRouterPei.inf | 51 ++ .../PeiInterposerToSvidMap.c | 136 ++++ .../PeiInterposerToSvidMap.inf | 53 ++ 27 files changed, 4360 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuP= olicy/PlatformCpuPolicy.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuP= olicy/PlatformCpuPolicy.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/Platfor= mType/PlatformType.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/Platfor= mType/PlatformTypes.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/Platfor= mType/PlatformTypes.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3Nvram= Save/S3NvramSave.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3Nvram= Save/S3NvramSave.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3Nvram= Save/S3NvramSave.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPc= hSpi/DummyPchSpi.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPc= hSpi/PchSpi.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/Emulati= onPlatformInit/EmulationPlatformInit.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/Emulati= onPlatformInit/EmulationPlatformInit.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/Platfor= mInfo/PlatformInfo.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/Platfor= mInfo/PlatformInfo.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/Platfor= mInfo/PlatformInfo.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeHandler/ExSerialStatusCodeWorker.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeHandler/ExStatusCodeHandlerPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeHandler/ExStatusCodeHandlerPei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeHandler/ExStatusCodeHandlerPei.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeRouter/ExReportStatusCodeRouterPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeRouter/ExReportStatusCodeRouterPei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatu= sCodeRouter/ExReportStatusCodeRouterPei.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterpo= serToSvidMap/PeiInterposerToSvidMap.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterpo= serToSvidMap/PeiInterposerToSvidMap.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c b/Platf= orm/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c new file mode 100644 index 0000000000..718bc14ffc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c @@ -0,0 +1,104 @@ +/** @file + Driver for BIOS Info support. + +@copyright + Copyright 2011 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo =3D { + { + BIOS_INFO_SIGNATURE, + BIOS_INFO_STRUCT_SIZE, + 0, + }, + { + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT, + 0x0100, + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFl= ashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), + FixedPcdGet32 (PcdFlashNvStorageVariableBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + 0, + 0x0100, + FixedPcdGet32 (PcdFlashFvPreMemorySize), + FixedPcdGet32 (PcdFlashFvPreMemoryBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + 0, + 0x0100, + FixedPcdGet32 (PcdFlashFvFspMSize), + FixedPcdGet32 (PcdFlashFvFspMBase) + }, + { + FIT_TYPE_01_MICROCODE, + BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION, + 0x0100, + FixedPcdGet32 (PcdFlashNvStorageMicrocodeSize), + FixedPcdGet32 (PcdFlashNvStorageMicrocodeBase) + }, + + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList =3D= { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gBiosInfoGuid, + &mBiosInfo +}; + +/** + Installs BiosInfo Ppi. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Install the BiosInfo Ppi successfully. + +**/ +EFI_STATUS +EFIAPI +BiosInfoEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + VOID *HobData; + + // + // Install PPI, so that other PEI module can add dependency. + // + Status =3D PeiServicesInstallPpi (&mBiosInfoPpiList); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Build hob, so that DXE module can also get the data. + // + HobData =3D BuildGuidHob (&gBiosInfoGuid, sizeof (BIOS_INFO)); + ASSERT (HobData !=3D NULL); + + if (HobData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (HobData, &mBiosInfo, sizeof (BIOS_INFO)); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h b/Platf= orm/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h new file mode 100644 index 0000000000..b849663766 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h @@ -0,0 +1,67 @@ +/** @file + + @copyright + Copyright 2011 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BIOS_INFO_H_ +#define _BIOS_INFO_H_ + +#undef BIOS_INFO_STRUCT_SIZE +#define BIOS_INFO_STRUCT_SIZE 4 +// +// BIOS INFO data structure +// This is self contained data structure for BIOS info for TXT +// +#pragma pack (1) + +#define BIOS_INFO_SIGNATURE SIGNATURE_64 ('$', 'B', 'I', 'O', 'S', 'I', '= F', '$') +typedef struct { + UINT64 Signature; + UINT32 EntryCount; + UINT32 Reserved; +} BIOS_INFO_HEADER; + +// +// BIOS_INFO_STRUCT attributes +// bits[0:3] means general attributes +// bits[4:7] means type specific attributes +// +#define BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT 0x01 +#define BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION 0x10 +#define BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB 0x10 +#define BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_NON_IBB 0x20 + +typedef struct { + // + // FitTable entry type + // + UINT8 Type; + // + // BIOS_INFO_STRUCT attributes + // + UINT8 Attributes; + // + // FitTable entry version + // + UINT16 Version; + // + // FitTable entry real size + // + UINT32 Size; + // + // FitTable entry address + // + UINT64 Address; +} BIOS_INFO_STRUCT; + +typedef struct { + BIOS_INFO_HEADER Header; + BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; +} BIOS_INFO; + +#pragma pack () + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf b/Pla= tform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf new file mode 100644 index 0000000000..b758e8d4e5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -0,0 +1,70 @@ +### @file +# Module Information description file for BIOS Info Driver +# +#@copyright +# Copyright 2011 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +# @par Glossary: +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BiosInfo + FILE_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D BiosInfoEntryPoint +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES IA32 X64 +# + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + HobLib + BaseMemoryLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSU= MES + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSU= MES + + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSU= MES + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase ## CONSU= MES + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize ## CONSU= MES + + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase ## CONSU= MES + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize ## CONSU= MES + +[Sources] + BiosInfo.c + +[Guids] + gBiosInfoGuid ## PRODU= CES + +[Depex] + gEfiPeiMasterBootModePpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/P= latformCpuPolicy.c b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpu= Policy/PlatformCpuPolicy.c new file mode 100644 index 0000000000..556dc1b0bf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/Platform= CpuPolicy.c @@ -0,0 +1,704 @@ +/** @file + CPU Policy Platform DXE Driver implementation. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +CHAR16 mCpuSocketStr[8][5] =3D {L"CPU0", L"CPU1", L"CPU2", L"CPU3", L"CPU4= ", L"CPU5", L"CPU6", L"CPU7"}; +CHAR16 mCpuAssetTagStr[] =3D L"UNKNOWN"; +IIO_UDS *mIioUds; +CPU_POLICY_CONFIGURATION mCpuPolicyConfiguration; +PPM_POLICY_CONFIGURATION mPpmPolicyConfiguration; + +/** + Set platform CPU data that related to SMBIOS. +**/ +VOID +PlatformCpuSmbiosData ( + VOID + ) +{ + UINT32 CpuSocketCount; + UINTN Index; + CHAR16 **CpuSocketNames; + CHAR16 **CpuAssetTags; + EFI_STATUS Status =3D EFI_SUCCESS; + + // + // Set the count of CPU sockets on the board. + // + CpuSocketCount =3D PcdGet32(PcdOemSkuBoardSocketCount); + + Status =3D PcdSet32S (PcdPlatformCpuSocketCount, CpuSocketCount); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return; + } + + CpuSocketNames =3D AllocatePool (CpuSocketCount * sizeof (UINTN)); + + if (CpuSocketNames =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "\nEFI_OUT_OF_RESOURCES!!! AllocatePool() returne= d NULL pointer.\n")); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return; + } + + CpuAssetTags =3D AllocatePool (CpuSocketCount * sizeof (UINTN)); + if (CpuAssetTags =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "\nEFI_OUT_OF_RESOURCES!!! AllocatePool() returne= d NULL pointer.\n")); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + gBS->FreePool (CpuSocketNames); + return; + } + + for (Index =3D 0; Index < CpuSocketCount; Index++) { + CpuSocketNames[Index] =3D mCpuSocketStr[Index]; + CpuAssetTags[Index] =3D mCpuAssetTagStr; + } + + mCpuPolicyConfiguration.PlatformCpuSocketNames =3D (UINT64) (UINTN) CpuS= ocketNames; + + mCpuPolicyConfiguration.PlatformCpuAssetTags =3D (UINT64) (UINTN) CpuAss= etTags; +} + + + +/** + + Re-assign socket id when both X2APIC and ForceX2Apic are enabled. + + @param None + + @retval None + +**/ +VOID +CheckAndReAssignSocketId( + VOID + ) +{ + CPU_SOCKET_ID_INFO *pcdSktIdPtr; + UINT32 i, IntraPackageIdBits; + UINTN PcdSize; + EFI_STATUS Status; + UINT32 MaxSocketCount; + + MaxSocketCount =3D FixedPcdGet32(PcdMaxCpuSocketCount); + DEBUG ((DEBUG_INFO, "::SocketCount %08x\n", MaxSocketCount)); + pcdSktIdPtr =3D (CPU_SOCKET_ID_INFO *)PcdGetPtr(PcdCpuSocketId); + PcdSize =3D LibPcdGetSize (PcdToken (PcdCpuSocketId)); //MAX_SOCKET * si= zeof(CPU_SOCKET_ID_INFO); + ASSERT(PcdSize =3D=3D (MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO))); + Status =3D PcdSetPtrS (PcdCpuSocketId, &PcdSize, (VOID *)pcdSktIdPtr); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return; + } + DEBUG ((EFI_D_INFO, "::SockeId Pcd at %08x, size %x\n", PcdGetPtr(PcdCpu= SocketId), PcdSize)); + + for(i =3D 0; i < MAX_SOCKET; i++) { + if (mIioUds->PlatformData.CpuQpiInfo[i].Valid) { + pcdSktIdPtr[i].DefaultSocketId =3D mIioUds->PlatformData.CpuQpiInfo[= i].SocId; + pcdSktIdPtr[i].NewSocketId =3D mIioUds->PlatformData.CpuQpiInfo[= i].SocId; + } else { + pcdSktIdPtr[i].DefaultSocketId =3D (UINT32)-1; //make sure Default= and New are same + pcdSktIdPtr[i].NewSocketId =3D (UINT32)-1; + } + } + + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &IntraPackageIdBits, NULL, NULL,= NULL); + //assign new socketId + for(i =3D 0; i < MAX_SOCKET; i++) { + + if (pcdSktIdPtr[i].DefaultSocketId =3D=3D (UINT32)-1) { + continue; + } + + switch(IntraPackageIdBits) { + case 4: //socket bit starts from bit4 of ApicId + case 5: //socket bit starts from bit5 of ApicId + if (MAX_SOCKET =3D=3D 4) { + pcdSktIdPtr[i].NewSocketId |=3D (APICID_MASK_BIT14_8 << (8 - Int= raPackageIdBits)); + } else { + //3bit in lower 8bit as skt field, to avoid ApicID=3D FFs, leave= bit8 untouched for 8S + pcdSktIdPtr[i].NewSocketId |=3D (0x7E << (8 - IntraPackageIdBits= )); //leave bit8 to 0 so we don't have FFs in ApicId + } + break; + + case 6: //socket bit starts from bit6 of ApicId + if (MAX_SOCKET =3D=3D 4) { + //only 2bit in lower 8bit as skt field, to avoid ApicID=3D FFs, = leave bit8 untouched for 4S + pcdSktIdPtr[i].NewSocketId |=3D (0x7E << (8 - IntraPackageIdBits= )); + } else { + //only 2bit in lower 8bit as skt field, to avoid ApicID=3D FFs, = leave bit9 untouched for 8S + pcdSktIdPtr[i].NewSocketId |=3D (0x7C << (8 - IntraPackageIdBits= )); + } + break; + + default: + DEBUG ((EFI_D_INFO, "::Need more info to make sure we can support!= !!\n")); + break; + + } //end switch + } +} + +/** + + This is the EFI driver entry point for the CpuPolicy Driver. This + driver is responsible for getting microcode patches from FV. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Protocol installed sucessfully. + +**/ +EFI_STATUS +EFIAPI +PlatformCpuPolicyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + EFI_HANDLE Handle; + UINT8 socket; + TURBO_POWRER_LIMIT *TurboPowerLimit; + EFI_PLATFORM_TYPE_PROTOCOL *PlatformType; + UINT32 CpuFamilyModelStepping; + BIOS_SCRATCHPAD7_STRUCT Sp7; + UINT64 i; + UINT8 PackageCStateSetting =3D 0; + UINT8 CpuCStateValue =3D 0; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DAT= A_GUID; + EFI_HOB_GUID_TYPE *GuidHob; + SYSTEM_MEMORY_MAP_HOB *SystemMemoryMap; + CPU_VAR_DATA *CpuVarDataPtr =3D NULL; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + CpuVarDataPtr =3D DynamicSiLibraryProtocol->GetCpuVarData (); + + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + mIioUds =3D GET_GUID_HOB_DATA(GuidHob); + + SystemMemoryMap =3D DynamicSiLibraryProtocol->GetSystemMemoryMapData (); + if (SystemMemoryMap =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + SetMem (&mCpuPolicyConfiguration, sizeof (CPU_POLICY_CONFIGURATION), 0x0= 0); + SetMem (&mPpmPolicyConfiguration, sizeof (PPM_POLICY_CONFIGURATION), 0x0= 0); + + AsmCpuid (1, &CpuFamilyModelStepping, NULL, NULL, NULL); + + PlatformCpuSmbiosData (); + + // + // Read the current system configuration variable store. + // + ZeroMem(&SetupData, sizeof(SETUP_DATA)); + CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfig= ), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketComm= onRcConfig), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.UpiConfig, PcdGetPtr(PcdSocketMpLinkCon= fig), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemory= Config), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSoc= ketPowerManagementConfig), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGe= tPtr(PcdSocketProcessorCoreConfig), sizeof(SOCKET_PROCESSORCORE_CONFIGURATI= ON)); + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CON= FIGURATION)); + CopyMem (&SetupData.PchSetup, PcdGetPtr(PcdPchSetup), sizeof(PCH_SETUP)); + + Sp7.Data =3D DynamicSiLibraryProtocol->ReadScratchpad7 (); + DEBUG ((EFI_D_INFO, "AYP Debug scratchpad7: %x Stepping %x\n", Sp7.Bits.= AepDimmPresent, CpuFamilyModelStepping & 0x0f)); + if ((Sp7.Bits.AepDimmPresent =3D=3D 1) && ((CpuFamilyModelStepping & 0x0= f) < 0x04) && ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_SKX)) { + SetupData.SocketConfig.PowerManagementConfig.PackageCState =3D 0; + } + + if (SetupData.SocketConfig.PowerManagementConfig.PackageCState =3D=3D PP= M_AUTO) { + PackageCStateSetting =3D C6_ENABLE; //POR Default =3D C6 + } else { + PackageCStateSetting =3D SetupData.SocketConfig.PowerManagementConfi= g.PackageCState; + } + + if (SetupData.SocketConfig.PowerManagementConfig.C6Enable =3D=3D PPM_AUT= O) { + CpuCStateValue |=3D C6_ENABLE; //POR Default =3D Enabled + } else { + CpuCStateValue |=3D (SetupData.SocketConfig.PowerManagementConfig.C6= Enable * C6_ENABLE); + } + + mCpuPolicyConfiguration.Policy.CpuCoreCStateValue =3D CpuCStateValue; + + // + // Update CpuMtoIWa from StructurePcd + // + if (DynamicSiLibraryProtocol->IsCpuAndRevision (CPU_ICXSP, REV_R0) || Dy= namicSiLibraryProtocol->IsCpuAndRevision (CPU_ICXSP, REV_L0) || DynamicSiLi= braryProtocol->IsCpuAndRevision (CPU_ICXSP, REV_C0)) { + mCpuPolicyConfiguration.Policy.CpuMtoIWa =3D SetupData.SocketConfig.So= cketProcessorCoreConfiguration.CpuMtoIWa; + } + // + // Verify that the value being set is within the valid range 0 to MAX_SO= CKET - 1 + // + if (SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection= > MAX_SOCKET) { + SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection= =3D 0xFF; + } + mCpuPolicyConfiguration.SbspSelection =3D SetupData.SocketConfig.SocketP= rocessorCoreConfiguration.BspSelection; + // + // Map CPU setup options to mCpuPolicyConfiguration + // + mCpuPolicyConfiguration.Policy.CpuEistEnable =3D SetupData.Soc= ketConfig.PowerManagementConfig.ProcessorEistEnable ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuVtEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.ProcessorVmxEnable ? TRUE : FALS= E; + mCpuPolicyConfiguration.Policy.CpuLtEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.ProcessorSmxEnable ? TRUE : FALS= E; + mCpuPolicyConfiguration.Policy.CpuFastStringEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.FastStringEnable ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuMaxCpuidValueLimitEnable =3D SetupData= .SocketConfig.SocketProcessorCoreConfiguration.CpuidMaxValue ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuMachineCheckEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.MachineCheckEnable ? TRUE : FALS= E; + mCpuPolicyConfiguration.Policy.CpuDcuPrefetcherEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.DCUStreamerPrefetcherEnable ? TR= UE : FALSE; + mCpuPolicyConfiguration.Policy.CpuIpPrefetcherEnable =3D SetupData.Soc= ketConfig.SocketProcessorCoreConfiguration.DCUIPPrefetcherEnable ? TRUE : F= ALSE; + mCpuPolicyConfiguration.Policy.CpuMonitorMwaitEnable =3D SetupData.Soc= ketConfig.PowerManagementConfig.MonitorMWait ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuTurboModeEnable =3D SetupData.Soc= ketConfig.PowerManagementConfig.TurboMode ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuThermalManagementEnable =3D SetupData.= SocketConfig.PowerManagementConfig.EnableThermalMonitor ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuTccActivationOffset =3D SetupData.Sock= etConfig.PowerManagementConfig.TCCActivationOffset; + mCpuPolicyConfiguration.Policy.CpuL1NextPagePrefetcherDisable =3D Setup= Data.SocketConfig.SocketProcessorCoreConfiguration.CpuL1NextPagePrefetcherD= isable ? TRUE : FALSE; + + if (SetupData.SocketConfig.PowerManagementConfig.TStateEnable && (SetupD= ata.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + mCpuPolicyConfiguration.Policy.CpuTStateEnable =3D SetupData.SocketCon= fig.PowerManagementConfig.TStateEnable ? TRUE : FALSE; + } + + mCpuPolicyConfiguration.Policy.CpuMlcStreamerPrefetecherEnable =3D Setu= pData.SocketConfig.SocketProcessorCoreConfiguration.MlcStreamerPrefetcherEn= able ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuMlcSpatialPrefetcherEnable =3D SetupD= ata.SocketConfig.SocketProcessorCoreConfiguration.MlcSpatialPrefetcherEnabl= e ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuThreeStrikeCounterEnable =3D SetupD= ata.SocketConfig.SocketProcessorCoreConfiguration.ThreeStrikeTimer ? TRUE := FALSE; + mCpuPolicyConfiguration.Policy.CpuEnergyPerformanceBiasEnable =3D TRUE; + mCpuPolicyConfiguration.Policy.CpuX2ApicEnable =3D (Setup= Data.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2apic || Dynam= icSiLibraryProtocol->X2ApicIdDetect (NULL)) ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuAesEnable =3D SetupD= ata.SocketConfig.SocketProcessorCoreConfiguration.AesEnable ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuPpinControlEnable =3D SetupD= ata.SocketConfig.SocketProcessorCoreConfiguration.PpinControl ? TRUE : FALS= E; + mCpuPolicyConfiguration.Policy.CpuPeciDownstreamWriteEnable =3D SetupD= ata.SocketConfig.SocketProcessorCoreConfiguration.PCIeDownStreamPECIWrite ?= TRUE : FALSE; + if ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_ICX) { + mCpuPolicyConfiguration.Policy.CpuC1AutoDemotionEnable =3D Setu= pData.SocketConfig.PowerManagementConfig.C1AutoDemotion ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuC1AutoUndemotionEnable =3D Setu= pData.SocketConfig.PowerManagementConfig.C1AutoUnDemotion ? TRUE : FALSE; + } + mCpuPolicyConfiguration.Policy.CpuCStateEnable =3D TRUE; + + mPpmPolicyConfiguration.OverclockingLock =3D SetupData.SocketConfig.Pow= erManagementConfig.OverclockingLock; + mPpmPolicyConfiguration.AvxSupport =3D SetupData.SocketConfig.Pow= erManagementConfig.AvxSupport; + mPpmPolicyConfiguration.AvxIccpLevel =3D SetupData.SocketConfig.Pow= erManagementConfig.AvxIccpLevel; + mPpmPolicyConfiguration.GpssTimer =3D SetupData.SocketConfig.Pow= erManagementConfig.GpssTimer; + + mPpmPolicyConfiguration.FastRaplDutyCycle =3D SetupData.SocketConfig.Pow= erManagementConfig.FastRaplDutyCycle; + + if (mIioUds->PlatformData.EVMode) { + mCpuPolicyConfiguration.Policy.CpuLtEnable =3D FALSE; + } + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable) { + mCpuPolicyConfiguration.Policy.CpuHwCoordinationEnable =3D SetupData.S= ocketConfig.PowerManagementConfig.ProcessorEistPsdFunc ? FALSE : TRUE; + mCpuPolicyConfiguration.Policy.CpuBootPState =3D SetupData.SocketConfi= g.PowerManagementConfig.BootPState; + } else { + mCpuPolicyConfiguration.Policy.CpuTurboModeEnable =3D FALSE; + } + + mCpuPolicyConfiguration.Policy.CpuAcpiLvl2Addr =3D PCH_ACPI_BASE_ADDRESS= + R_ACPI_LV2; + mCpuPolicyConfiguration.Policy.CpuPackageCStateLimit =3D PackageCStateSe= tting; + + if ((SetupData.SocketConfig.PowerManagementConfig.TStateEnable) && (Setu= pData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + mCpuPolicyConfiguration.Policy.CpuClockModulationDutyCycle =3D SetupDa= ta.SocketConfig.PowerManagementConfig.OnDieThermalThrottling; + } + + Status =3D PcdSetBoolS (PcdCpuSmmMsrSaveStateEnable, SetupData.SocketCon= fig.SocketProcessorCoreConfiguration.eSmmSaveState? TRUE : FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + + if (SetupData.SystemConfig.EmcaMsmiEn !=3D 0) { + Status =3D PcdSetBoolS (PcdCpuSmmProtectedModeEnable, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } else { + Status =3D PcdSetBoolS (PcdCpuSmmProtectedModeEnable, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } + + + mCpuPolicyConfiguration.Policy.CpuIioLlcWaysBitMask =3D SetupDat= a.SocketConfig.SocketProcessorCoreConfiguration.IioLlcWaysMask; + mCpuPolicyConfiguration.Policy.CpuExpandedIioLlcWaysBitMask =3D SetupDat= a.SocketConfig.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask; + mCpuPolicyConfiguration.Policy.CpuRemoteWaysBitMask =3D SetupDat= a.SocketConfig.SocketProcessorCoreConfiguration.RemoteWaysMask; + mCpuPolicyConfiguration.Policy.CpuRrqCountThreshold =3D mIioUds-= >PlatformData.RemoteRequestThreshold; + mCpuPolicyConfiguration.Policy.CpuCrashLogGprs =3D (SetupData.SocketConf= ig.SocketProcessorCoreConfiguration.CpuCrashLogGprs > 0) ? TRUE : FALSE; + + //CSR SAPM CTL + for( socket =3D 0; socket < MAX_SOCKET; socket++) { + mPpmPolicyConfiguration.SapmCtl[socket].Iio0PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Iio0PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Iio1PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Iio1PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Iio2PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Iio2PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Kti01PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Kti01PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Kti23PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Kti23PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Mc0PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Mc0PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1PkgcClkGateDis =3D SetupD= ata.SocketConfig.PowerManagementConfig.Mc1PkgcClkGateDis[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].P0pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.P0pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].P1pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.P1pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].P2pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.P2pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Kti01pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.Kti01pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Kti23pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.Kti23pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Mc0pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.Mc0pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1pllOffEna =3D SetupD= ata.SocketConfig.PowerManagementConfig.Mc1pllOffEna[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].SetvidDecayDisable =3D SetupD= ata.SocketConfig.PowerManagementConfig.SetvidDecayDisable[socket]; + mPpmPolicyConfiguration.SapmCtl[socket].SapmCtlLock =3D SetupD= ata.SocketConfig.PowerManagementConfig.SapmCtlLock[socket]; + + if (SetupData.SocketConfig.MemoryConfig.OppSrefEn =3D=3D 1) { + mPpmPolicyConfiguration.SapmCtl[socket].Mc0PkgcIoVolRedDis =3D 1; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1PkgcIoVolRedDis =3D 1; + mPpmPolicyConfiguration.SapmCtl[socket].Mc0PkgcDigVolRedDis =3D 1; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1PkgcDigVolRedDis =3D 1; + } + + if (Sp7.Bits.AepDimmPresent =3D=3D 1) { + mPpmPolicyConfiguration.SapmCtl[socket].Mc0pllOffEna =3D 0; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1pllOffEna =3D 0; + mPpmPolicyConfiguration.SapmCtl[socket].Mc0PkgcClkGateDis =3D 1; + mPpmPolicyConfiguration.SapmCtl[socket].Mc1PkgcClkGateDis =3D 1; + } + } + + // + // PMAX Detector Config + // + mPpmPolicyConfiguration.PmaxConfig.PmaxDetector =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxDetector; + mPpmPolicyConfiguration.PmaxConfig.PmaxAutoAdjustment =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxAutoAdjustment; + mPpmPolicyConfiguration.PmaxConfig.PmaxLoadLine =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxLoadLine; + mPpmPolicyConfiguration.PmaxConfig.PmaxSign =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxSign; + mPpmPolicyConfiguration.PmaxConfig.PmaxOffset =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxOffset; + mPpmPolicyConfiguration.PmaxConfig.PmaxTriggerSetup =3D SetupData.Sock= etConfig.PowerManagementConfig.PmaxTriggerSetup; + + // + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xE4) + // + mPpmPolicyConfiguration.PerPLimitCtl.PerfPLmtThshld =3D SetupDat= a.SocketConfig.PowerManagementConfig.PerfPLmtThshld; + mPpmPolicyConfiguration.PerPLimitCtl.PerfPLimitClipC =3D SetupDat= a.SocketConfig.PowerManagementConfig.PerfPLimitClipC; + mPpmPolicyConfiguration.PerPLimitCtl.PerfPlimitDifferential =3D SetupDat= a.SocketConfig.PowerManagementConfig.PerfPlimitDifferential; + mPpmPolicyConfiguration.PerPLimitCtl.PerfPLimitEn =3D SetupDat= a.SocketConfig.PowerManagementConfig.PerfPLimitEn; + + mPpmPolicyConfiguration.DynamicIss =3D SetupData.SocketConfig.PowerMan= agementConfig.DynamicIss; + mPpmPolicyConfiguration.IssCapableSystem =3D CpuVarDataPtr->IssCapable= System; + mPpmPolicyConfiguration.ConfigTDPLevel =3D CpuVarDataPtr->IssConfigTdp= CurrentLevel; + mPpmPolicyConfiguration.ConfigTDPLock =3D SetupData.SocketConfig.Power= ManagementConfig.ConfigTdpLock; + + for (socket =3D 0; socket < MAX_SOCKET; socket++) { + mPpmPolicyConfiguration.PmaxConfig.BasePackageTdp[socket] =3D CpuVar= DataPtr->IssConfigTdpPower[socket][0]; + mPpmPolicyConfiguration.CurrentPackageTdp[socket] =3D CpuVarDataPtr-= >IssConfigTdpPower[socket][mPpmPolicyConfiguration.ConfigTDPLevel]; + + if ((CpuFamilyModelStepping >> 4) !=3D CPU_FAMILY_SKX) { + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaKti[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Kti[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaRlink[socket]= =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Rlink[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaFxr[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Fxr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaMcddr[socket]= =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Mcddr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaHbm[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Hbm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaIio[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Iio[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaHqm[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Hqm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaNac[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Nac[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaTip[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Tip[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnablePkgCCriteriaMdfs[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnablePkgCCriteria= Mdfs[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaLogicalIpType[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaLogica= lIpType[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaLogicalIpTypeMcddr[= socket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaLogicalIpTypeIio[so= cket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoKti[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoKti[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnableLinkInL1Kti[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnableLinkInL1Kti[= socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoRlink[soc= ket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoRlink[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnableLinkInL1Rlink[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnableLinkInL1Rlin= k[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoFxr[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoFxr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteraPsMaskFxr[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteraPsMaskF= xr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaAllowedPsMaskFxr[so= cket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaAllowe= dPsMaskFxr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoMcddr[soc= ket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoMcddr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteriaPsOptionMcddr[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteriaPsOpti= onMcddr[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoHbm[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoHbm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteriaPsOptionHbm[socket]= =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteriaPsOpti= onHbm[socket]; + + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoIio[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoIio[socket]; + mPpmPolicyConfiguration.PkgcCriteria.EnableLinkInL1Iio[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.EnableLinkInL1Iio[= socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoHqm[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoHqm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteraPsMaskHqm[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteraPsMaskH= qm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaAllowedPsMaskHqm[so= cket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHqm[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoNac[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoNac[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteraPsMaskNac[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteraPsMaskN= ac[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaAllowedPsMaskNac[so= cket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaAllowe= dPsMaskNac[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoTip[socke= t] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoTip[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgcCriteraPsMaskTip[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.PkgcCriteraPsMaskT= ip[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaAllowedPsMaskTip[so= cket] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaAllowe= dPsMaskTip[socket]; + mPpmPolicyConfiguration.PkgcCriteria.PkgCCriteriaInstanceNoMdfs[sock= et] =3D SetupData.SocketConfig.PowerManagementConfig.PkgCCriteriaInstan= ceNoMdfs[socket]; + mPpmPolicyConfiguration.PkgcCriteria.AllowLpStateMdfs[socket] = =3D SetupData.SocketConfig.PowerManagementConfig.AllowLpStateMdfs[s= ocket]; + } + + if ((CpuFamilyModelStepping >> 4) =3D=3D CPU_FAMILY_SKX) { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskKti[socket] = =3D (SetupData.SocketConfig.PowerManagementConfig.Kti0In[socket] | + (SetupData.SocketConfig.PowerManagementConf= ig.Kti1In[socket] << 1) | + (SetupData.SocketConfig.PowerManagementConf= ig.Kti2In[socket] << 2) ); + + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio0In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D SET_PCIEx_MASK; + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio1In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D (SET_PCIEx_MASK << 4); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio2In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D (SET_PCIEx_MASK << 8); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio3In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D (SET_PCIEx_MASK << 12); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio4In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D (SET_PCIEx_MASK << 16); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio5In[socket])= { + mPpmPolicyConfiguration.PpmCst.PkgCstEntryCriteriaMaskPcie[socket]= |=3D (SET_PCIEx_MASK << 20); + } + } + } + + mPpmPolicyConfiguration.AdvPwrMgtCtl.SapmctlValCtl =3D SetupData.SocketC= onfig.PowerManagementConfig.SapmctlValCtl; + mPpmPolicyConfiguration.AdvPwrMgtCtl.MsrLock =3D 1; + mPpmPolicyConfiguration.AdvPwrMgtCtl.PkgCstEntryValCtl =3D SetupData.= SocketConfig.PowerManagementConfig.PkgCstEntryValCtl; + mPpmPolicyConfiguration.AdvPwrMgtCtl.CurrentConfig =3D SetupData.= SocketConfig.PowerManagementConfig.CurrentConfig; + mPpmPolicyConfiguration.TurboPowerLimit.TurboLimitCsrLock =3D 1; + mPpmPolicyConfiguration.AdvPwrMgtCtl.MsrPkgCstConfigControlLock =3D Setu= pData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorMsrPkgCstConfi= gControlLock ? 1 : 0; + + if ((PackageCStateSetting > 0) && SetupData.SocketConfig.PowerManagement= Config.DynamicL1) { + mPpmPolicyConfiguration.AdvPwrMgtCtl.DynamicL1Disable =3D 1; + } + + if (SetupData.SocketConfig.PowerManagementConfig.VccSAandVccIOdisable) { + mPpmPolicyConfiguration.AdvPwrMgtCtl.VccsaVccioDisable =3D 1; + } + + mPpmPolicyConfiguration.AdvPwrMgtCtl.SwLtrOvrdCtl =3D SetupData.SocketCo= nfig.PowerManagementConfig.SwLtrOvrdCtl; + mPpmPolicyConfiguration.AdvPwrMgtCtl.EnableLowerLatencyMode =3D SetupDat= a.SocketConfig.PowerManagementConfig.EnableLowerLatencyMode; + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable =3D= =3D 0) { + mPpmPolicyConfiguration.PowerCtl.EeTurboDisable =3D 1; + } + + mPpmPolicyConfiguration.PowerCtl.PkgCLatNeg =3D SetupData.SocketConf= ig.PowerManagementConfig.PkgCLatNeg; + mPpmPolicyConfiguration.PowerCtl.LtrSwInput =3D SetupData.SocketConf= ig.PowerManagementConfig.LTRSwInput; + mPpmPolicyConfiguration.PowerCtl.PwrPerfSwitch =3D SetupData.SocketConf= ig.PowerManagementConfig.PwrPerfSwitch; + mPpmPolicyConfiguration.PowerCtl.SapmControl =3D SetupData.SocketConf= ig.PowerManagementConfig.SAPMControl; + mPpmPolicyConfiguration.PowerCtl.EeTurboDisable =3D SetupData.SocketConf= ig.PowerManagementConfig.EETurboDisable; + mPpmPolicyConfiguration.PowerCtl.ProchotLock =3D 1; + mPpmPolicyConfiguration.PowerCtl.C1eEnable =3D SetupData.SocketConf= ig.PowerManagementConfig.ProcessorC1eEnable; + mPpmPolicyConfiguration.PowerCtl.SetvidDecayDisable =3D SetupData.Socket= Config.PowerManagementConfig.SetvidDecayDisable[0]; + + if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable = =3D=3D 3) && !SetupData.SocketConfig.PowerManagementConfig.PwrPerfTuning) { + // If hwp native w/o legacy then default value is "BIOS Controls EPB".= OS Control of EPB should not be allowed + mPpmPolicyConfiguration.PowerCtl.PwrPerfTuning =3D 1; + } else if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEn= able =3D=3D 2) && !SetupData.SocketConfig.PowerManagementConfig.PwrPerfTuni= ng) { + // if hwp oob mode then default value is "PECI Controls EPB". OS Contr= ol of EPB should not be allowed + mPpmPolicyConfiguration.PowerCtl.PwrPerfTuning =3D 2; + } else { + mPpmPolicyConfiguration.PowerCtl.PwrPerfTuning =3D SetupData.SocketCo= nfig.PowerManagementConfig.PwrPerfTuning; + } + + // From Setup: + // 0: Output only + // 1: Disable + // 2: Bi-Directional + // 3: Input Only + // + if ((SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 1) =3D= =3D 0) { + mPpmPolicyConfiguration.PowerCtl.ProchotOutputDisable =3D 0; + } else { + mPpmPolicyConfiguration.PowerCtl.ProchotOutputDisable =3D 1; + } + + if ((SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 2) =3D= =3D 0) { + mPpmPolicyConfiguration.PowerCtl.BidirProchotEnable =3D 0; + } else { + mPpmPolicyConfiguration.PowerCtl.BidirProchotEnable =3D 1; + } + + // + // PROCHOT_RESPONSE_RATIO (CSR 1:30:2:0xB0) + // + mPpmPolicyConfiguration.ProchotRatio =3D SetupData.SocketConfig.PowerMan= agementConfig.ProchotResponseRatio; + + mPpmPolicyConfiguration.PpoCurrentCfg.PpcccLock =3D SetupData.SocketConf= ig.PowerManagementConfig.PpcccLock; + mPpmPolicyConfiguration.PpoCurrentCfg.CurrentLimit =3D SetupData.SocketC= onfig.PowerManagementConfig.CurrentLimit; + + // MSR_PACKAGE_POWER_LIMIT 0x610 + // CSR_TURBO_POWER_LIMIT 1:30:0:0xe8 + TurboPowerLimit =3D &mPpmPolicyConfiguration.TurboPowerLimit; + TurboPowerLimit->TurboPowerLimitLock =3D SetupData.SocketConfig.PowerMa= nagementConfig.TurboPowerLimitLock; + TurboPowerLimit->PowerLimit1Power =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit1Power; + TurboPowerLimit->PowerLimit1Time =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit1Time; + TurboPowerLimit->PowerLimit1En =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit1En; + TurboPowerLimit->PowerLimit2Power =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit2Power; + TurboPowerLimit->PowerLimit2Time =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit2Time; + TurboPowerLimit->PowerLimit2En =3D SetupData.SocketConfig.PowerMa= nagementConfig.PowerLimit2En; + TurboPowerLimit->PkgClmpLim1 =3D 1; + TurboPowerLimit->PkgClmpLim2 =3D 1; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + mPpmPolicyConfiguration.DynamicPerPowerCtl.UncrPerfPlmtOvrdEn =3D Setu= pData.SocketConfig.PowerManagementConfig.UncrPerfPlmtOvrdEn; + mPpmPolicyConfiguration.DynamicPerPowerCtl.EetOverrideEn =3D Setu= pData.SocketConfig.PowerManagementConfig.EetOverrideEn; + mPpmPolicyConfiguration.DynamicPerPowerCtl.IoBwPlmtOvrdEn =3D Setu= pData.SocketConfig.PowerManagementConfig.IoBwPlmtOvrdEn; + mPpmPolicyConfiguration.DynamicPerPowerCtl.IomApmOvrdEn =3D Setu= pData.SocketConfig.PowerManagementConfig.IomApmOvrdEn; + mPpmPolicyConfiguration.DynamicPerPowerCtl.KtiApmOvrdEn =3D Setu= pData.SocketConfig.PowerManagementConfig.KtiApmOvrdEn; + + // + // CSR_PCIE_ILTR_OVRD (CSR 1:30:1:0xFC) + // SW_LTR_OVRD (MSR 0xa02) -- not used + // + mPpmPolicyConfiguration.PcieIltrOvrd.SnpLatVld =3D SetupData.SocketC= onfig.PowerManagementConfig.SnpLatVld; + mPpmPolicyConfiguration.PcieIltrOvrd.SnpLatOvrd =3D SetupData.SocketC= onfig.PowerManagementConfig.SnpLatOvrd; + mPpmPolicyConfiguration.PcieIltrOvrd.SnpLatMult =3D SetupData.SocketC= onfig.PowerManagementConfig.SnpLatMult; + mPpmPolicyConfiguration.PcieIltrOvrd.SnpLatVal =3D SetupData.SocketC= onfig.PowerManagementConfig.SnpLatVal; + mPpmPolicyConfiguration.PcieIltrOvrd.NonSnpLatVld =3D SetupData.SocketC= onfig.PowerManagementConfig.NonSnpLatVld; + mPpmPolicyConfiguration.PcieIltrOvrd.NonSnpLatOvrd =3D SetupData.SocketC= onfig.PowerManagementConfig.NonSnpLatOvrd; + mPpmPolicyConfiguration.PcieIltrOvrd.NonSnpLatMult =3D SetupData.SocketC= onfig.PowerManagementConfig.NonSnpLatMult; + mPpmPolicyConfiguration.PcieIltrOvrd.NonSnpLatVal =3D SetupData.SocketC= onfig.PowerManagementConfig.NonSnpLatVal; + + for(i =3D 0; i < 8; i++) { + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitRatio[i] =3D SetupDa= ta.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[i]; + + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitRatioMask[i] =3D 0xF= F; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[= i] > 0) { + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitRatioMask[i] =3D 0; + } + + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitCoresMask[i] =3D 0xF= F; + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitCores[i] =3D 0; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[= i] !=3D 0xFF) { + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitCoresMask[i] =3D 0; + mPpmPolicyConfiguration.TurboRatioLimit.RatioLimitCores[i] =3D Setup= Data.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[i]; + } + } + + // + // ENERGY_PERF_BIAS_CONFIG (MSR 0xA01) + // + mPpmPolicyConfiguration.PerfBiasConfig.EngAvgTimeWdw1 =3D SetupData.Sock= etConfig.PowerManagementConfig.EngAvgTimeWdw1; + mPpmPolicyConfiguration.PerfBiasConfig.P0TtlTimeLow1 =3D SetupData.Sock= etConfig.PowerManagementConfig.P0TtlTimeLow1; + mPpmPolicyConfiguration.PerfBiasConfig.P0TtlTimeHigh1 =3D SetupData.Sock= etConfig.PowerManagementConfig.P0TtlTimeHigh1; + mPpmPolicyConfiguration.PerfBiasConfig.AltEngPerfBIAS =3D SetupData.Sock= etConfig.PowerManagementConfig.AltEngPerfBIAS; + mPpmPolicyConfiguration.PerfBiasConfig.WorkLdConfig =3D SetupData.Sock= etConfig.PowerManagementConfig.WorkLdConfig; + + // + //ProcessorHWPM-init as disabled. + // + mPpmPolicyConfiguration.Hwpm.HWPMNative =3D 0; + mPpmPolicyConfiguration.Hwpm.HWPMOOB =3D 0; + mPpmPolicyConfiguration.Hwpm.HWPMEnable =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorHWPMEnable; + mPpmPolicyConfiguration.Hwpm.HWPMInterrupt =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorHWPMInterrupt; + mPpmPolicyConfiguration.Hwpm.EPPEnable =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorEPPEnable; + mPpmPolicyConfiguration.Hwpm.EPPProfile =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorEppProfile; + + if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable = =3D=3D 1) || + (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable =3D= =3D 3)) { + mPpmPolicyConfiguration.Hwpm.HWPMNative =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorHWPMEnable; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnab= le =3D=3D 2){ + mPpmPolicyConfiguration.Hwpm.HWPMOOB =3D SetupData.SocketConfig.Po= werManagementConfig.ProcessorHWPMEnable; + mPpmPolicyConfiguration.Hwpm.HWPMInterrupt =3D 0; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnab= le =3D=3D 0){ + mPpmPolicyConfiguration.Hwpm.HWPMNative =3D 0; + mPpmPolicyConfiguration.Hwpm.HWPMOOB =3D 0; + mPpmPolicyConfiguration.Hwpm.HWPMInterrupt =3D 0; + mPpmPolicyConfiguration.Hwpm.EPPEnable =3D 0; + } + + mPpmPolicyConfiguration.Hwpm.APSrocketing =3D SetupData.SocketC= onfig.PowerManagementConfig.ProcessorAPSrocketing; + mPpmPolicyConfiguration.Hwpm.Scalability =3D SetupData.SocketC= onfig.PowerManagementConfig.ProcessorScalability; + mPpmPolicyConfiguration.Hwpm.RaplPrioritization =3D SetupDat= a.SocketConfig.PowerManagementConfig.ProcessorRaplPrioritization; + mPpmPolicyConfiguration.Hwpm.OutofBandAlternateEPB =3D SetupData.SocketC= onfig.PowerManagementConfig.ProcessorOutofBandAlternateEPB; + + for (i =3D 0; i < NUM_CST_LAT_MSR; i++) { // CStateLatencyCtrl CSRs + mPpmPolicyConfiguration.PpmCst.LatencyCtrl[i].Valid =3D SetupData= .SocketConfig.PowerManagementConfig.CStateLatencyCtrlValid[i]; + mPpmPolicyConfiguration.PpmCst.LatencyCtrl[i].Multiplier =3D SetupData= .SocketConfig.PowerManagementConfig.CStateLatencyCtrlMultiplier[i]; + mPpmPolicyConfiguration.PpmCst.LatencyCtrl[i].Value =3D SetupData= .SocketConfig.PowerManagementConfig.CStateLatencyCtrlValue[i]; + } + + if (SetupData.SocketConfig.PowerManagementConfig.C2C3TT) { //if option i= s not AUTO + mPpmPolicyConfiguration.C2C3TT =3D SetupData.SocketConfig.PowerManagem= entConfig.C2C3TT; + } else { + mPpmPolicyConfiguration.C2C3TT =3D 0x10; + } + + // + // If Emulation flag set by InitializeDefaultData in MemoryQpiInit.c + // force X2APIC + // + Status =3D gBS->LocateProtocol ( + &gEfiPlatformTypeProtocolGuid, + NULL, + &PlatformType + ); + ASSERT_EFI_ERROR (Status); + + // allocate memory for IedTrace + if ((SetupData.SocketConfig.SocketProcessorCoreConfiguration.IedTraceSiz= e !=3D 0) && (PcdGet32 (PcdCpuIEDRamSize) !=3D 0)) { + DynamicSiLibraryProtocol->CheckAndPopulateIedTraceMemory(0x400000 << (= SetupData.SocketConfig.SocketProcessorCoreConfiguration.IedTraceSize - 1), = mIioUds); + } + + // + // Install CPU PPM Policy Protocol for platform PPM configuration + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gPpmPolicyProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPpmPolicyConfiguration + ); + ASSERT_EFI_ERROR (Status); + + // + // Install CPU Policy Protocol for platform configuration + // Cpu Driver could be dispatched after this protocol installed. + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiCpuPolicyProtocolGuid, + EFI_NATIVE_INTERFACE, + &mCpuPolicyConfiguration + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/P= latformCpuPolicy.inf b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformC= puPolicy/PlatformCpuPolicy.inf new file mode 100644 index 0000000000..e125017e1d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/Platform= CpuPolicy.inf @@ -0,0 +1,81 @@ +## @file +# Component description file for Platform CPU Policy DXE Driver. +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformCpuPolicy + FILE_GUID =3D 76A7B4FC-C8D5-462d-A4D2-6E88338A772A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint + +[Sources] + PlatformCpuPolicy.c + +[Packages] + UefiCpuPkg/UefiCpuPkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + PcdLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + MemoryAllocationLib + BaseMemoryLib + HobLib + IoLib + +[Protocols] + gEfiPlatformTypeProtocolGuid + gEfiCpuPolicyProtocolGuid + gPpmPolicyProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Guids] + gEfiSetupVariableGuid + gEfiSocketMemoryVariableGuid + gEfiSocketPowermanagementVarGuid + gEfiSocketProcessorCoreVarGuid + gEfiEndOfDxeEventGroupGuid + +[Pcd] + gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount + gCpuPkgTokenSpaceGuid.PcdCpuSocketId + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize + + gStructPcdTokenSpaceGuid.PcdSocketIioConfig + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig + gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig + gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig + gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig + gStructPcdTokenSpaceGuid.PcdSetup + gStructPcdTokenSpaceGuid.PcdPchSetup + gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig + + gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gEfiVariableArchProtocolGuid AND gEfiPlatformTypeProtocolGuid AND gDynam= icSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/P= latformType.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformT= ype/PlatformType.inf new file mode 100644 index 0000000000..a3ab0ecbe6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/Platform= Type.inf @@ -0,0 +1,58 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformType + FILE_GUID =3D 2E6A521C-F697-402d-9774-98B2B7E140F3 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformTypeInit + +[Sources] + PlatformTypes.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + PcdLib + BaseLib + HobLib + DebugLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + + [Protocols] + gEfiPlatformTypeProtocolGuid ## PRODUCES + gEfiIioUdsProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Guids] + gEfiPlatformInfoGuid + gEfiSetupVariableGuid + +[Pcd] + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/P= latformTypes.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformTy= pe/PlatformTypes.c new file mode 100644 index 0000000000..08396c3b7a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/Platform= Types.c @@ -0,0 +1,364 @@ +/** @file + Platform type driver to identify different platform. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Statements that include other files +// +#include "PlatformTypes.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#define STRING_WIDTH_40 40 + +CHAR16 PchName[STRING_WIDTH_40]; +CHAR16 IioName[STRING_WIDTH_40]; +CHAR16 *PlatformName; + +// +// Instantiation of Driver's private data. +// +EFI_PLATFORM_DATA_DRIVER_PRIVATE mPrivatePlatformData; +EFI_IIO_UDS_DRIVER_PRIVATE mIioUdsPrivateData; +IIO_UDS *IioUdsData; // Pointer to UD= S in Allocated Memory Pool + +EFI_GUID gEfiSmbusHcProtocolGuid =3D EFI_SMBUS_HC_PROTOCOL_GUID; +EFI_GUID gEfiMpServiceProtocolGuid =3D EFI_MP_SERVICES_PROTOCOL_GUID; +EFI_GUID mSystemConfigurationGuid =3D SYSTEM_CONFIGURATION_GUID; + + +/** + Get the PCH name. + + Concatenate the series, stepping, and SKU strings to initialize the modu= le + global variable "PchName". + + @param[in] PlatformInfoHobData Pointer to the platform info HOB. + + @retval EFI_INVALID_PARAMETER Pointer parameter was null on entry. + @retval EFI_SUCCESS PchName was initialized successfully. +**/ +EFI_STATUS +EFIAPI +GetPchName ( + IN EFI_PLATFORM_INFO *PlatformInfoHobData + ) +{ + CHAR8 AsciiBuffer[STRING_WIDTH_40]; + CHAR16 UnicodeBuffer[STRING_WIDTH_40]; + UINT32 BufferAsciiSize; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + EFI_STATUS Status; + + ASSERT (PlatformInfoHobData !=3D NULL); + if (PlatformInfoHobData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + BufferAsciiSize =3D sizeof (AsciiBuffer); + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + AsciiStrCpyS (AsciiBuffer, BufferAsciiSize, DynamicSiLibraryProtocol->Pc= hGetSeriesStr ()); + AsciiStrToUnicodeStrS (AsciiBuffer, UnicodeBuffer, STRING_WIDTH_40); + ZeroMem (AsciiBuffer, BufferAsciiSize); + StrCpyS (PchName, STRING_WIDTH_40, UnicodeBuffer); + + StrCatS (PchName, STRING_WIDTH_40, L" "); + + DynamicSiLibraryProtocol->PchGetSteppingStr (AsciiBuffer, BufferAsciiSiz= e); + AsciiStrToUnicodeStrS (AsciiBuffer, UnicodeBuffer, STRING_WIDTH_40); + ZeroMem (AsciiBuffer, BufferAsciiSize); + StrCatS (PchName, STRING_WIDTH_40, UnicodeBuffer); + + StrCatS (PchName, STRING_WIDTH_40, L" - "); + + AsciiStrCpyS (AsciiBuffer, BufferAsciiSize, DynamicSiLibraryProtocol->Pc= hGetSkuStr ()); + AsciiStrToUnicodeStrS (AsciiBuffer, UnicodeBuffer, STRING_WIDTH_40); + ZeroMem (AsciiBuffer, BufferAsciiSize); + StrCatS (PchName, STRING_WIDTH_40, UnicodeBuffer); + + mPrivatePlatformData.PlatformType.PchStringPtr =3D (UINT64)PchName; + + return EFI_SUCCESS; +} + + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +EFIAPI +GetIioName ( + VOID + ) +{ + + StrCpyS(IioName, STRING_WIDTH_40, L"Unknown"); + + mPrivatePlatformData.PlatformType.IioStringPtr =3D (UINT64)IioName; + return ; +} + + +/** + + Assert the POST complete GPIO + + @param Event Pointer to the event that triggered this Ccllback F= unction + @param Context VOID Pointer required for Ccllback functio + + @retval EFI_SUCCESS - Assertion successfully + + +**/ +VOID +EFIAPI +AssertPostGpio ( + EFI_EVENT Event, + VOID *Context + ) +{ + UINT32 GPIO_B20; + UINT32 Data32; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + GPIO_B20 =3D PcdGet32 (PcdOemSkuAssertPostGPIO); + Data32 =3D PcdGet32(PcdOemSkuAssertPostGPIOValue); + if (GPIO_B20 =3D=3D 0xFFFFFFFF) { + DEBUG ((EFI_D_ERROR, "GPIO Pcd is invalid, so abort the GPIO Set and j= ust return! \n")); + return; + } + DynamicSiLibraryProtocol->GpioSetOutputValue (GPIO_B20, Data32); + DEBUG ((EFI_D_INFO, "System Post Complete GPIO has been set ! \n")); +} + +/** + + Gets the CpuId and fills in the pointer with the value. + Needed for executing CpuId on other APs. + + @param RegEax - Pointer to be used to pass the CpuId value + + @retval None + +**/ +VOID +EFIAPI +PlatformGetProcessorID ( + IN OUT UINT32 *RegEax + ) +{ + + AsmCpuid (CPUID_VERSION_INFO, RegEax, NULL, NULL, NULL); +} + +// +// Define platform type check +// +/** + + Entry point for the driver. + + This routine reads the PlatformType GPI on FWH and produces a protocol + to be consumed by the chipset driver to effect those settings. + + @param ImageHandle - Image Handle. + @param SystemTable - EFI System Table. + + @retval EFI_SUCCESS - Function has completed successfully. + +**/ +EFI_STATUS +EFIAPI +PlatformTypeInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfoHobData =3D NULL; + IIO_UDS *UdsHobPtr; + EFI_GUID UniversalDataGuid =3D IIO_UNIVERSAL_DATA= _GUID; + EFI_EVENT ReadyToBootEvent; + CHAR16 *PcdPlatformName =3D NULL; + UINT32 PcdPlatformNameSize =3D 0; + UINT32 PlatformNameSize; + + // + // Initialize driver private data. + // Only one instance exists + // + ZeroMem (&mPrivatePlatformData, sizeof (mPrivatePlatformData)); + mPrivatePlatformData.Signature =3D EFI_PLATFORM_TYPE_DRIVER_P= RIVATE_SIGNATURE; + + PlatformNameSize =3D (STRING_WIDTH_40) * sizeof (CHAR16); + PlatformName =3D AllocateZeroPool (PlatformNameSize); + ASSERT (PlatformName !=3D NULL); + if (PlatformName =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Failed to allocate memory\n")); + return EFI_OUT_OF_RESOURCES; + } + // + // Search for the Platform Info PEIM GUID HOB. + // + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "gEfiPlatformInfoGuid not found\n")); + return EFI_NOT_FOUND; + } + PlatformInfoHobData =3D GET_GUID_HOB_DATA(GuidHob); + + CopyMem(&(mPrivatePlatformData.PlatformType.SystemUuid[0]), &PlatformInf= oHobData->SystemUuid[0], 16); + mPrivatePlatformData.PlatformType.Signature =3D PlatformInfoHobData->Sig= nature; + mPrivatePlatformData.PlatformType.Size =3D PlatformInfoHobData->Size; + mPrivatePlatformData.PlatformType.Revision =3D PlatformInfoHobData->Revi= sion; + mPrivatePlatformData.PlatformType.TypeRevisionId =3D PlatformInfoHobData= ->TypeRevisionId; + mPrivatePlatformData.PlatformType.ExtendedInfoValid =3D PlatformInfoHobD= ata->ExtendedInfoValid; + mPrivatePlatformData.PlatformType.Checksum =3D PlatformInfoHobData->Chec= ksum; + + CopyMem(&(mPrivatePlatformData.PlatformType.PciData), &PlatformInfoHobDa= ta->PciData, sizeof(EFI_PLATFORM_PCI_DATA)); + CopyMem(&(mPrivatePlatformData.PlatformType.CpuData), &PlatformInfoHobDa= ta->CpuData, sizeof(EFI_PLATFORM_CPU_DATA)); + CopyMem(&(mPrivatePlatformData.PlatformType.MemData), &PlatformInfoHobDa= ta->MemData, sizeof(EFI_PLATFORM_MEM_DATA)); + CopyMem(&(mPrivatePlatformData.PlatformType.SysData), &PlatformInfoHobDa= ta->SysData, sizeof(EFI_PLATFORM_SYS_DATA)); + CopyMem(&(mPrivatePlatformData.PlatformType.PchData), &PlatformInfoHobDa= ta->PchData, sizeof(EFI_PLATFORM_PCH_DATA)); + + mPrivatePlatformData.PlatformType.BoardId =3D PlatformInfoHobData->B= oardId; + mPrivatePlatformData.PlatformType.Type =3D mPrivatePlatformData.P= latformType.BoardId; + mPrivatePlatformData.PlatformType.IioSku =3D PlatformInfoHobData->I= ioSku; + mPrivatePlatformData.PlatformType.IioRevision =3D PlatformInfoHobData->I= ioRevision; + mPrivatePlatformData.PlatformType.PchSku =3D PlatformInfoHobData->P= chSku; + mPrivatePlatformData.PlatformType.PchRevision =3D PlatformInfoHobData->P= chRevision; + mPrivatePlatformData.PlatformType.PchType =3D PlatformInfoHobData->P= chType; //Include PCH SKU type + mPrivatePlatformData.PlatformType.CpuType =3D PlatformInfoHobData->C= puType; + mPrivatePlatformData.PlatformType.CpuStepping =3D PlatformInfoHobData->C= puStepping; + + mPrivatePlatformData.PlatformType.IioRiserId =3D PlatformInfoHobData->Ii= oRiserId; + mPrivatePlatformData.PlatformType.PcieRiser1Type =3D PlatformInfoHobData= ->PcieRiser1Type; + mPrivatePlatformData.PlatformType.PcieRiser2Type =3D PlatformInfoHobData= ->PcieRiser2Type; + mPrivatePlatformData.PlatformType.Emulation =3D 0x4; // = default is Simics + + PcdPlatformNameSize =3D PcdGet32(PcdOemSkuPlatformNameSize); + PcdPlatformName =3D PcdGetPtr (PcdOemSkuPlatformName); + ASSERT(PlatformNameSize >=3D PcdPlatformNameSize); + if (PlatformNameSize < PcdPlatformNameSize) { + DEBUG ((EFI_D_ERROR, "Invalid buffer size\n")); + return EFI_BUFFER_TOO_SMALL; + } + ASSERT(PcdPlatformName !=3D NULL); + if (PcdPlatformName =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Invalid PCD detected\n")); + return EFI_NOT_FOUND; + } + CopyMem (PlatformName, PcdPlatformName, PcdPlatformNameSize); + + mPrivatePlatformData.PlatformType.TypeStringPtr =3D (UINT64)PlatformName; + + Status =3D GetPchName (PlatformInfoHobData); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Failed to get PCH name: %r\n", Status)); + return Status; + } + + GetIioName(); + + // + // Install the PlatformType policy. + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mPrivatePlatformData.Handle, + &gEfiPlatformTypeProtocolGuid, + &mPrivatePlatformData.PlatformType, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "%s platform is detected!\n", PlatformName)); + + // + // Time to get the IIO_UDS HOB data stored in the PEI driver + // + GuidHob =3D GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "UniversalDataGuid not found\n")); + return EFI_NOT_FOUND; + } + UdsHobPtr =3D GET_GUID_HOB_DATA(GuidHob); + + // + // Allocate Memory Pool for Universal Data Storage so that protocol can = expose it + // + Status =3D gBS->AllocatePool ( EfiReservedMemoryType, sizeof (IIO_UDS), = (VOID **) &IioUdsData ); + ASSERT_EFI_ERROR (Status); + + // + // Initialize the Pool Memory with the data from the Hand-Off-Block + // + CopyMem(IioUdsData, UdsHobPtr, sizeof(IIO_UDS)); + + // + // Build the IIO_UDS driver instance for protocol publishing + // + ZeroMem (&mIioUdsPrivateData, sizeof (mIioUdsPrivateData)); + + mIioUdsPrivateData.Signature =3D EFI_IIO_UDS_DRIVER_PRIVATE_S= IGNATURE; + mIioUdsPrivateData.IioUds.IioUdsPtr =3D IioUdsData; + mIioUdsPrivateData.IioUds.EnableVc =3D NULL; + + // + // Install the IioUds Protocol. + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mIioUdsPrivateData.Handle, + &gEfiIioUdsProtocolGuid, + &mIioUdsPrivateData.IioUds, + NULL + ); + ASSERT_EFI_ERROR (Status); + + + // + // Set up callback to assert the POST Complete GPIO to the iBMC + // + Status =3D EfiCreateEventReadyToBootEx( + TPL_CALLBACK, + AssertPostGpio, + NULL, + &ReadyToBootEvent + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/P= latformTypes.h b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformTy= pe/PlatformTypes.h new file mode 100644 index 0000000000..a6dbe19c40 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/Platform= Types.h @@ -0,0 +1,58 @@ +/** @file + Platform Type Driver for Harwich. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_TYPES_H_ +#define _PLATFORM_TYPES_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + + + +#define EFI_PLATFORM_TYPE_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('T', 'Y'= , 'P', 'P') +#define EFI_IIO_UDS_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('S', 'D', 'U',= 'I') + + +typedef unsigned char BYTE; //!< 8-bit quantities +typedef unsigned short WORD; //!< 16-bit quantities +typedef unsigned long DWORD; //!< 32-bit quantities + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for = protocol this driver installs on + EFI_PLATFORM_TYPE_PROTOCOL PlatformType; // Policy prot= ocol this driver installs +} EFI_PLATFORM_DATA_DRIVER_PRIVATE; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for protoc= ol this driver installs on + EFI_IIO_UDS_PROTOCOL IioUds; // Policy protocol t= his driver installs +} EFI_IIO_UDS_DRIVER_PRIVATE; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3= NvramSave.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S= 3NvramSave.c new file mode 100644 index 0000000000..709c7ad479 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa= ve.c @@ -0,0 +1,157 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "S3NvramSave.h" +#include +#include +#include + +/** + Verify the SysHost structure size. + + Verifies that the size of the SysHost structure in PEI is + the same as the size of the SysHost structure and DXE and + ASSERT's is the size is not the same. + + This is typically caused by the use of pointers or UINTNs + in the SysHost structure, neither of those datatypes are + allowed in SysHost. + + @param None + + @retval None + +**/ + +VOID +VerifySysHostStructureSize ( + VOID + ) +{ + + if (PcdGet32 (PcdPeiSyshostMemorySize) !=3D sizeof (SYSHOST)) { + + DEBUG ((EFI_D_ERROR, "ERROR: In DXE sizeof SysHost =3D %d, in PEI size= of SysHost =3D %d\n", + sizeof (SYSHOST), + PcdGet32 (PcdPeiSyshostMemorySize) + )); + + DEBUG ((EFI_D_ERROR, "Size of SysHost must match in PEI and DXE\n")); + ASSERT (FALSE); + + } + + return; + +} // VerifySysHostStructureSize + +/** + Saves the FSP Non-Volatile Storage HOB to the UEFI Variable Services + + @param None + + @retval EFI_SUCCESS The FSP Non-Volatile Storage HOB was successful= ly saved. + @retval EFI_ERROR The FSP Non-Volatile Storage HOB was not succes= sfully saved. +**/ +EFI_STATUS +SaveFspNonVolatileStorageHob ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *HobData; + VOID *VariableData; + UINTN DataSize; + UINTN FspNvsBufferSize; + BOOLEAN DataIsIdentical; + + FspNvsBufferSize =3D 0; + DataSize =3D 0; + VariableData =3D NULL; + GuidHob =3D NULL; + HobData =3D NULL; + DataIsIdentical =3D FALSE; + Status =3D EFI_SUCCESS; + + DEBUG ((DEBUG_INFO, "Saving FSP / MRC Training Data\n")); + GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHobGuid); + if (GuidHob !=3D NULL) { + HobData =3D GET_GUID_HOB_DATA (GuidHob); + DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob); + if (DataSize > 0) { + + // + // Check if the presently saved data is identical to the data given = by MRC/FSP + // + Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorag= eHobGuid, &FspNvsBufferSize, NULL); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + if (FspNvsBufferSize =3D=3D DataSize) { + VariableData =3D AllocatePool (FspNvsBufferSize); + if (VariableData !=3D NULL) { + Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatile= StorageHobGuid, &FspNvsBufferSize, VariableData); + if (!EFI_ERROR (Status) && (FspNvsBufferSize =3D=3D DataSize) = && (0 =3D=3D CompareMem (HobData, VariableData, DataSize))) { + DataIsIdentical =3D TRUE; + } + FreePool (VariableData); + } + } + } + Status =3D EFI_SUCCESS; + + if (!DataIsIdentical) { + Status =3D SetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStor= ageHobGuid, TRUE, DataSize, HobData); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "Saved size of FSP / MRC Training Data: 0x%x\n= ", DataSize)); + } else { + DEBUG ((DEBUG_INFO, "FSP / MRC Training Data is identical to data = from last boot, no need to save.\n")); + } + } + } + + return Status; +} + +EFI_STATUS +EFIAPI +S3NvramSaveEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/** + + This is the main entry point of the S3 NVRAM Save module. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Module launched successfully. + +**/ +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + // + // Check that SysHost size in DXE is the same as PEI. + // + +#ifndef FSP_API_MODE + VerifySysHostStructureSize (); +#endif + + // + // Save structures into NVRAM if needed + // + Status =3D SaveFspNonVolatileStorageHob (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: FSP NVRAM Data NOT Saved! Status: %r\n", = Status)); + Status =3D EFI_SUCCESS; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3= NvramSave.h b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S= 3NvramSave.h new file mode 100644 index 0000000000..8b106a3445 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa= ve.h @@ -0,0 +1,40 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +#include "SysHost.h" + +extern EFI_GUID gEfiMemoryConfigDataHobGuid; +extern EFI_GUID gEfiMemoryConfigDataGuid; + +#define MAX_HOB_ENTRY_SIZE 60*1024 + +EFI_STATUS +EFIAPI +S3NvramSaveEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Saves the FSP Non-Volatile Storage HOB to the UEFI Variable Services + + @param None + + @retval EFI_SUCCESS The FSP Non-Volatile Storage HOB was successful= ly saved. + @retval EFI_ERROR The FSP Non-Volatile Storage HOB was not succes= sfully saved. +**/ +EFI_STATUS +SaveFspNonVolatileStorageHob ( + VOID + ); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3= NvramSave.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave= /S3NvramSave.inf new file mode 100644 index 0000000000..e62baa24c4 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa= ve.inf @@ -0,0 +1,52 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D S3NvramSave + FILE_GUID =3D 62DC08AC-A651-4EE9-AF81-EAA9261E9780 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D S3NvramSaveEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Sources] + S3NvramSave.h + S3NvramSave.c + +[LibraryClasses] + UefiDriverEntryPoint + MemoryAllocationLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + BaseMemoryLib + LargeVariableReadLib + LargeVariableWriteLib + +[Guids] + gFspNonVolatileStorageHobGuid # CONSUMES + +[Pcd] + gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize + +[Depex] + TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/Du= mmyPchSpi.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi= /DummyPchSpi.inf new file mode 100644 index 0000000000..6d0486fda7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchS= pi.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for PCH Reset Lib Pei Phase +# +# @copyright +# Copyright 2016 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PchSpiPei + FILE_GUID =3D FEB73B42-2B02-4D2E-B9E3-77015AF91879 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D DummySpiPpiEntryPoint + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] + DebugLib + PeiServicesLib + PeiServicesTablePointerLib + MemoryAllocationLib + PciSegmentLib + PeimEntryPoint + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[Sources] + PchSpi.c + +[Ppis] + gPchSpiPpiGuid ## PRODUCES + +[Depex] + TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/Pc= hSpi.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/PchSpi= .c new file mode 100644 index 0000000000..0d63044416 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/PchSpi.c @@ -0,0 +1,383 @@ +/** @file + PCH SPI PEI Library implements the SPI Host Controller Compatibility Int= erface. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; + SPI_INSTANCE SpiInstance; +} PEI_SPI_INSTANCE; + + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashRead ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWrite ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashErase ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadSfdp ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadJedecId ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWriteStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiProtocolGetRegionAddress ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadPchSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Initialize an SPI protocol instance. + + @param[in] PchId The PCH Id (0 - Legacy PCH, 1 ... n - No= n-Legacy PCH) + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +SpiProtocolConstructor ( + IN UINT8 PchId, + IN SPI_INSTANCE *SpiInstance + ) +{ + // + // Initialize the SPI protocol instance + // + SpiInstance->Signature =3D PCH_SPI_PRIVATE_DATA_SIGNA= TURE; + SpiInstance->Handle =3D NULL; + SpiInstance->SpiProtocol.Revision =3D PCH_SPI_SERVICES_REVISION; + SpiInstance->SpiProtocol.FlashRead =3D SpiProtocolFlashRead; + SpiInstance->SpiProtocol.FlashWrite =3D SpiProtocolFlashWrite; + SpiInstance->SpiProtocol.FlashErase =3D SpiProtocolFlashErase; + SpiInstance->SpiProtocol.FlashReadSfdp =3D SpiProtocolFlashReadSfdp; + SpiInstance->SpiProtocol.FlashReadJedecId =3D SpiProtocolFlashReadJedecI= d; + SpiInstance->SpiProtocol.FlashWriteStatus =3D SpiProtocolFlashWriteStatu= s; + SpiInstance->SpiProtocol.FlashReadStatus =3D SpiProtocolFlashReadStatus; + SpiInstance->SpiProtocol.GetRegionAddress =3D SpiProtocolGetRegionAddres= s; + SpiInstance->SpiProtocol.ReadPchSoftStrap =3D SpiProtocolReadPchSoftStra= p; + SpiInstance->SpiProtocol.ReadCpuSoftStrap =3D SpiProtocolReadCpuSoftStra= p; + return EFI_SUCCESS; +} + +/** + Installs PCH SPI PPI + + @retval EFI_SUCCESS PCH SPI PPI is installed successfully + @retval EFI_OUT_OF_RESOURCES Can't allocate pool +**/ +EFI_STATUS +EFIAPI +InstallPchSpi ( + VOID + ) +{ + EFI_STATUS Status; + PEI_SPI_INSTANCE *PeiSpiInstance; + SPI_INSTANCE *SpiInstance; + + DEBUG ((DEBUG_INFO, "InstallPchSpi() Start\n")); + + // + // PCI Enumeratuion is not done till later in DXE + // Initlialize SPI BAR0 to a default value till enumeration is done + // also enable memory space decoding for SPI + // + + + PeiSpiInstance =3D (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SP= I_INSTANCE)); + if (NULL =3D=3D PeiSpiInstance) { + return EFI_OUT_OF_RESOURCES; + } + + SpiInstance =3D &(PeiSpiInstance->SpiInstance); + SpiProtocolConstructor (PCH_LEGACY_ID, SpiInstance); + + PeiSpiInstance->PpiDescriptor.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI= _PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PeiSpiInstance->PpiDescriptor.Guid =3D &gPchSpiPpiGuid; + PeiSpiInstance->PpiDescriptor.Ppi =3D &(SpiInstance->SpiProtocol); + + + + /// + /// Install the SPI PPI + /// + Status =3D PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "SPI PPI Installed\n")); + + DEBUG ((DEBUG_INFO, "InstallPchSpi() End\n")); + + return Status; +} + +/** + Board Install Dummy SPI Ppi entry point. + + @param FileHandle Handle of the file being invoked. + Type EFI_PEI_FILE_HANDLE is defined in FfsFindNextF= ile(). + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +DummySpiPpiEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + + InstallPchSpi (); + + return EFI_SUCCESS; + +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatf= ormInit/EmulationPlatformInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Platfo= rm/Pei/EmulationPlatformInit/EmulationPlatformInit.c new file mode 100644 index 0000000000..d065225a92 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit= /EmulationPlatformInit.c @@ -0,0 +1,124 @@ +/** @file + EFI PEIM for Emulation Platform Initial + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_PEI_PPI_DESCRIPTOR mPpiListEmulation =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEmulationHobGuid, + NULL +}; + +#define CSR_EMULATION_FLAG_OFFSET 0xFC + +EFI_STATUS +EFIAPI +EmulationPlatformInitEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + EMULATION_DFX_CONFIGURATION EmulationVariable; + UINTN BufferSize =3D sizeof(EMULATION_DFX= _CONFIGURATION); + EMULATION_SETTING *EmulationSetting; + UINT32 RegEax; + UINT16 CpuFamily; + UINTN PciLibAddress; + UINT32 EmulationType; + + // + // Build the Emulation Hob + // + EmulationSetting =3D BuildGuidHob (&gEmulationHobGuid, sizeof (EMULATION= _SETTING)); + if (EmulationSetting =3D=3D NULL) { + DEBUG((EFI_D_ERROR, "Emulation BuildGuidDataHob fail!\n")); + return EFI_OUT_OF_RESOURCES; + } + + EmulationSetting->UbiosGenerationSetting =3D EMULATION_DISABLE; + EmulationSetting->HybridSystemLevelEmulationSetting =3D EMULATION_DISABL= E; + EmulationSetting->UbiosOutputMode =3D ASM_OUTPUT_ENABLE; + EmulationSetting->LoopBackLabelNumber =3D 0; + EmulationSetting->FnvAccessValue =3D FNV_ACCESS_DISABLE; + EmulationSetting->MsrTraceEnable =3D MSR_OUTPUT_DISABLE; + + // + // Store variable into the hob. + // + (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &PeiVariable + ); + + Status =3D PeiVariable->GetVariable (PeiVariable, EMULATION_DFX_CONFIGUR= ATION_NAME, &gEmulationDfxVariableGuid, NULL, &BufferSize, &EmulationVariab= le); + DEBUG ((DEBUG_INFO, "Emulation GetVariable status =3D %r !\n", Status)); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + EmulationSetting->UbiosGenerationSetting =3D EmulationVariable.DfxUbiosG= eneration; + EmulationSetting->HybridSystemLevelEmulationSetting =3D EmulationVariabl= e.DfxHybridSystemLevelEmulation; + EmulationSetting->MsrTraceEnable =3D EmulationVariable.DfxPmMsrTrace; + + // + // Check the override value + // + AsmCpuid (1, &RegEax, NULL, NULL, NULL); + CpuFamily =3D (UINT16) (RegEax >> 4); + + if (CpuFamily =3D=3D CPU_FAMILY_SKX) { + // + // Simics flag is at B0:D0:F0 offset 0xFC for SKX. + // + PciLibAddress =3D PCI_LIB_ADDRESS(0, 0, 0, CSR_EMULATION_FLAG_OFFSET); + } else { + // + // Simics flag is at B0:D3:F0 offset 0xFC for 10nm. + // + PciLibAddress =3D PCI_LIB_ADDRESS(0, 3, 0, CSR_EMULATION_FLAG_OFFSET); + } + + EmulationType =3D PciRead32 (PciLibAddress); + + if (EmulationType !=3D 0xFFFFFFFF) { + if ((EmulationType & UBIOS_GENERATION_EN) !=3D 0) { + EmulationSetting->UbiosGenerationSetting =3D EMULATION_ENABLE; + DEBUG ((DEBUG_INFO, "EmulationVariable.DfxUbiosGeneration =3D %d\n",= EmulationSetting->UbiosGenerationSetting)); + } + + if ((EmulationType & HYBRID_SYSTEM_LEVEL_EMULATION_EN) !=3D 0) { + EmulationSetting->HybridSystemLevelEmulationSetting =3D EMULATION_EN= ABLE; + DEBUG ((DEBUG_INFO, "EmulationSetting->HybridSystemLevelEmulationSet= ting =3D %d\n", EmulationSetting->HybridSystemLevelEmulationSetting)); + } + } + // + // Install gEmulationHobGuid PPI to inform the Emulation Hob is ready. + // + Status =3D PeiServicesInstallPpi (&mPpiListEmulation); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatf= ormInit/EmulationPlatformInit.inf b/Platform/Intel/WhitleyOpenBoardPkg/Plat= form/Pei/EmulationPlatformInit/EmulationPlatformInit.inf new file mode 100644 index 0000000000..ca22383a96 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit= /EmulationPlatformInit.inf @@ -0,0 +1,46 @@ +## @file +# Emulation PEIM +# +# @copyright +# Copyright 2017 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D EmulationPlatformInit + FILE_GUID =3D BD446386-7F8A-4ee1-A014-8D3BAB92B4E9 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D EmulationPlatformInitEntry + +[Sources] + EmulationPlatformInit.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + PciLib + BaseMemoryLib + +[Guids] + gEmulationHobGuid + gEmulationDfxVariableGuid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid AND + gPlatformVariableInitPpiGuid + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInf= o/PlatformInfo.c new file mode 100644 index 0000000000..3652695fba --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c @@ -0,0 +1,761 @@ +/** @file + Platform Info PEIM. + + @copyright + Copyright 1999 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PlatformInfo.h" +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#define TEMP_BUS_NUMBER (0x3F) + + +STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPlatformInfoGuid, + NULL + }; + +#define BOARD_ID_GPIO_PADS_NUMBER 6 +#define BOARD_REV_ID_GPIO_PADS_NUMBER 3 + +// +// These pads shall not be board specific as these are used for Board ID a= nd Rev ID detection +// Therefore can not be moved to UBA and are common for all Purley boards +// +GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] =3D { + // BoardId pads - PADCFG register for GPIO G12 + // WARNING: The pad number must be obtained from board schematics + GPIO_SKL_H_GPP_G12, + GPIO_SKL_H_GPP_G13, + GPIO_SKL_H_GPP_G14, + GPIO_SKL_H_GPP_G15, + GPIO_SKL_H_GPP_G16, + GPIO_SKL_H_GPP_B19 +}; + +GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] =3D { + // Board RevId pads - Start from pad C12 + // WARNING: This should be obtained from board schematics + GPIO_SKL_H_GPP_C12, + GPIO_SKL_H_GPP_C13, + GPIO_SKL_H_GPP_B9 +}; + +GPIO_CONFIG mBoardAndRevIdConfig =3D { + // Board and Revision ID pads configuration required for proper reading = the values + GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntD= efault, + GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default +}; + + +VOID +GpioConfigForBoardId ( + VOID + ) +{ + UINT8 i; + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; + PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; + PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; + PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; + PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; + PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; + PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; + PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; + PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadCon= fig); + ASSERT_EFI_ERROR (Status); + } +} + + +VOID +GpioConfigForBoardRevId ( + VOID + ) +{ + UINT8 i; + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; + PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; + PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; + PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; + PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; + PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; + PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; + PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; + PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &Pad= Config); + ASSERT_EFI_ERROR (Status); + } +} + +/** + + Reads GPIO pins to get Board ID value + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId ( + OUT UINT32 *BoardId + ) +{ + EFI_STATUS Status =3D EFI_DEVICE_ERROR; + UINT32 Data32; + UINT8 i; + UINT32 BdId; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + if (BoardId =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + BdId =3D 0; + + GpioConfigForBoardId (); + + for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data3= 2); + if (EFI_ERROR(Status)) { + break; + } + if (Data32) { + BdId =3D BdId | (1 << i); + } + } + if (Status !=3D EFI_SUCCESS) { + return Status; + } + *BoardId =3D BdId; + return EFI_SUCCESS; +} + +/** + + Reads GPIO pins to get Board Revision ID value + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardRevId ( + OUT UINT32 *BoardRevId + ) +{ + EFI_STATUS Status =3D EFI_DEVICE_ERROR; + UINT32 Data32; + UINT8 i; + UINT32 RevId; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + if (BoardRevId =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + RevId =3D 0; + + GpioConfigForBoardRevId (); + + for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){ + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &D= ata32); + if (EFI_ERROR(Status)) { + break; + } + if (Data32) { + RevId =3D RevId | (1 << i); + } + } + if (Status !=3D EFI_SUCCESS) { + return Status; + } + *BoardRevId =3D RevId; + return EFI_SUCCESS; + +} + +/** + + Returns the Model ID of the CPU. + Model ID =3D EAX[7:4] + +**/ +VOID +GetCpuInfo ( + UINT32 *CpuType, + UINT8 *CpuStepping + ) + +{ + UINT32 RegEax=3D0; + + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + + *CpuStepping =3D (UINT8) (RegEax & 0x0F); + *CpuType =3D (UINT32) (RegEax >> 4); +} + + +/** + + GC_TODO: add routine description + + @param BAR - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval None + +**/ +VOID +InitGSX( + UINT32 *BAR, + IN EFI_PEI_SERVICES **PeiServices +) +{ +} + +/** + + GC_TODO: add routine description + + @param Data - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + @retval EFI_UNSUPPORTED - GC_TODO: add retval description + +**/ +EFI_STATUS +GsxRead( + UINT32 *Data, + IN EFI_PEI_SERVICES **PeiServices +) +{ + return EFI_UNSUPPORTED; +} + +/** + + GC_TODO: add routine description + + @param Data - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval None + +**/ +VOID +GetGsxBoardID( + BOARD_ID *Data, + IN EFI_PEI_SERVICES **PeiServices +) +{ + + EFI_STATUS Status; + UINT32 GSXIN[2]; + UINT32 RetryCount; + + RetryCount =3D 0; + GSXIN[0] =3D 0; + GSXIN[1] =3D 0; + + do { + Status =3D GsxRead(GSXIN, PeiServices); + + if(Status){ + // if EFI_SUCCESS !=3D Success then retry one more time + RetryCount ++; + }else{ + // if EFI_SUCCESS read Board ID and exit + RetryCount =3D 0xFFFFFFFF; + } + + if (GSXIN[0] & BIT0) { + Data->BoardID.BoardID0 =3D 1; + } + + if (GSXIN[0] & BIT1) { + Data->BoardID.BoardID1 =3D 1; + } + + if (GSXIN[0] & BIT2) { + Data->BoardID.BoardID2 =3D 1; + } + + if (GSXIN[0] & BIT3) { + Data->BoardID.BoardID3 =3D 1; + } + + if (GSXIN[0] & BIT4) { + Data->BoardID.BoardID4 =3D 1; + } + + if (GSXIN[0] & BIT5) { + Data->BoardID.BoardRev0 =3D 1; + } + + if (GSXIN[0] & BIT6) { + Data->BoardID.BoardRev1 =3D 1; + } + + } while(RetryCount < 1); + + if(Status){ + // + // Unhable to read GSX HW error Hang the system + // + DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n")); + CpuDeadLoop (); + } +} + +/** + Get Platform Type by read Platform Data Region in SPI flash. + SPI Descriptor Mode Routines for Accessing Platform Info from Platform= Data Region (PDR) + + @param PeiServices - General purpose services available to every PEI= M. + @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob-= >BoardId + + @retval Status EFI_SUCCESS - PDR read success + @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid= Platform Type + +**/ +EFI_STATUS +PdrGetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + EFI_STATUS Status; + PCH_SPI_PROTOCOL *SpiPpi; + UINTN Size; + + // + // Locate the SPI PPI Interface + // + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gPchSpiPpiGuid, + 0, + NULL, + &SpiPpi + ); + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Read the PIT (Platform Info Table) from the SPI Flash Platform Data R= egion + // + Size =3D sizeof (EFI_PLATFORM_INFO); + Status =3D SpiPpi->FlashRead ( + SpiPpi, + FlashRegionPlatformData, + PDR_REGION_START_OFFSET, + (UINT32) Size, + (UINT8 *) PlatformInfoHob + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax)) { + // + // Valid Platform Identified + // + DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type =3D %x\n",PlatformIn= foHob->BoardId)); + } else { + // + // Reading PIT from SPI PDR Failed or a unknown platform identified + // + DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This= is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId)); + PlatformInfoHob->BoardId =3D TypePlatformUnknown; + Status =3D EFI_INCOMPATIBLE_VERSION; + } + return Status; +} + +VOID +GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob) +/** + + GC_TODO: add routine description + + @param None + + @ret None +**/ +{ + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + // Gpio programming to QAT board detection + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.HostSoftPadOwn =3D GpioHostOwnDefault; + PadConfig.Direction =3D GpioDirIn; + PadConfig.OutputState =3D GpioOutLow; + PadConfig.InterruptConfig =3D GpioIntDis; + PadConfig.PowerConfig =3D GpioResetPwrGood; + PadConfig.ElectricalConfig =3D GpioTermNone; + PadConfig.LockConfig =3D GpioPadConfigLock; + PadConfig.OtherSettings =3D 00; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &Pa= dConfig); + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &P= latformInfoHob->QATDis); + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &Pa= dConfig); + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &P= latformInfoHob->QATSel); +} + +EFI_STATUS +GetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +/** + + GC_TODO: add routine description + + @param PeiServices - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_UNSUPPORTED - GC_TODO: add retval description + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +{ + + + UINT32 BoardId; + UINT32 BoardRev; + EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; + EFI_STATUS Status; + + PciCfgPpi =3D (**PeiServices).PciCfg; + ASSERT (PciCfgPpi !=3D NULL); + + PlatformInfoHob->BoardId =3D TypeNeonCityEPRP; + DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n")); + + Status =3D GpioGetBoardId (&BoardId); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); + return Status; + } + Status =3D GpioGetBoardRevId (&BoardRev); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); + return Status; + } + PlatformInfoHob->TypeRevisionId =3D BoardRev; + + switch (BoardId) { + case 0x00: // for Simics + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + break; + case 0x01: + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + DEBUG ((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); + break; + case 0x12: + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); + break; + case 0x15: + PlatformInfoHob->BoardId =3D TypeWilsonCitySMT; + DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCitySMT\n")); + break; + case 0x17: + case 0x18: + PlatformInfoHob->BoardId =3D TypeCooperCityRP; + DEBUG((DEBUG_INFO, "Board ID =3D TypeCooperCityRP\n")); + break; + default: + PlatformInfoHob->BoardId =3D TypePlatformDefault; + DEBUG ((DEBUG_INFO, "Board ID =3D %2X Default set to TypePlatformDef= ault\n",BoardId)); + break; + } + + GatherQATInfo(PlatformInfoHob); + + DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev)); + return EFI_SUCCESS; +} + +/** + + This function initializes the board related flag to indicates if + PCH and Lan-On-Motherboard (LOM) devices is supported. + +**/ +VOID +GetPchLanSupportInfo( + IN EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + PlatformInfoHob->PchData.LomLanSupported =3D 0; +} + +/** + + GC_TODO: add routine description + + @param PeiVariable - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +EFIAPI +GetIioCommonRcPlatformSetupPolicy( + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) + { + UINT8 IsocEn; + + CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_O= F(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8)); + + PlatformInfoHob->SysData.IsocEn =3D IsocEn; // ISOC enabled + + return EFI_SUCCESS; +} +/** + + GC_TODO: add routine description + + @param PeiVariable - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +EFIAPI +GetIioPlatformSetupPolicy( + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + return EFI_SUCCESS; +} + + +/** + Platform Type detection. Because the PEI globle variable + is in the flash, it could not change directly.So use + 2 PPIs to distinguish the platform type. + + @param FfsHeader - Pointer to Firmware File System file header. + @param PeiServices - General purpose services available to every PEIM. + + @retval EFI_SUCCESS - Memory initialization completed successfully. + @retval Others - All other error conditions encountered result in= an ASSERT. + +**/ +EFI_STATUS +EFIAPI +PlatformInfoInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + EFI_PLATFORM_INFO PlatformInfoHob; + EFI_PLATFORM_INFO tempPlatformInfoHob; + UINT8 ChipId; + UINT32 Delay; + UINT32 CpuType; + UINT8 CpuStepping; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PciCfgPpi =3D (**PeiServices).PciCfg; + if (PciCfgPpi =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a N= ULL Pointer!!!\n")); + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + // + // Locate Variable PPI + // + Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, &PeiVariable); + + (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // -------------------------------------------------- + // + // Detect the iBMC SIO for CV/CRB Platforms + // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM. + // + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + ChipId =3D IoRead8 (PILOTIV_SIO_DATA_PORT); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + + if (EFI_ERROR (Status)) + { + DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n")); + } + + Status =3D GetIioPlatformSetupPolicy (&PlatformInfoHob); + ASSERT_EFI_ERROR (Status); + Status =3D GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob); + ASSERT_EFI_ERROR (Status); + + // + // Update PCH Type + // + PlatformInfoHob.PchType =3D DynamicSiLibraryPpi->GetPchSeries (); + PlatformInfoHob.PchSku =3D DynamicSiLibraryPpi->GetPchLpcDeviceId (); + PlatformInfoHob.PchRevision =3D (UINT8) DynamicSiLibraryPpi->PchStepping= (); + PlatformInfoHob.MaxNumOfPchs =3D 1; + Status =3D EFI_SUCCESS; + + if(!EFI_ERROR(Status)) { + Status =3D GetPlatformInfo (PeiServices, &PlatformInfoHob); + if(EFI_ERROR (Status)) { + Status =3D PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob); + PlatformInfoHob.BoardId =3D tempPlatformInfoHob.BoardId; + PlatformInfoHob.TypeRevisionId =3D tempPlatformInfoHob.TypeRevisio= nId; + if (EFI_ERROR(Status)) { + PlatformInfoHob.BoardId =3D TypePlatformUnknown; + } + } + } else { + PlatformInfoHob.BoardId =3D TypePlatformUnknown; + } + + // + // Update IIO Type + // + PlatformInfoHob.IioRevision =3D 0; + + + // + // Get Subtractive decode enable bit from descriptor + // + + if (DynamicSiLibraryPpi->PchIsGbeRegionValid () =3D=3D FALSE) { + PlatformInfoHob.PchData.GbeRegionInvalid =3D 1; + } else { + PlatformInfoHob.PchData.GbeRegionInvalid =3D 0; + } + GetPchLanSupportInfo (&PlatformInfoHob); + PlatformInfoHob.PchData.GbePciePortNum =3D 0xFF; + PlatformInfoHob.PchData.GbePciePortNum =3D (UINT8) DynamicSiLibraryPpi->= PchGetGbePortNumber (); + PlatformInfoHob.PchData.GbeEnabled =3D DynamicSiLibraryPpi->PchIsGbePre= sent (); + PlatformInfoHob.PchData.PchStepping =3D (UINT8) DynamicSiLibraryPpi->Pch= Stepping (); + + PlatformInfoHob.SysData.SysSioExist =3D (UINT8)IsSioExist(); + + GetCpuInfo (&CpuType, &CpuStepping); + PlatformInfoHob.CpuType =3D CpuType; + PlatformInfoHob.CpuStepping =3D CpuStepping; + + // + // Set default memory topology to DaisyChainTopology. This should be mod= ified in UBA board + // specific file. + // + (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (Platfor= mInfoHob.MemoryTopology), DaisyChainTopology); + + // + // Set default memory type connector to DimmConnectorPth. This should be= modified in UBA board + // specific file. + // + (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (Pl= atformInfoHob.MemoryConnectorType), DimmConnectorPth); + + // + // Build HOB for setup memory information + // + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfoHob), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi); + ASSERT_EFI_ERROR (Status); + + // + // Save PlatformInfoHob.BoardId in CMOS + // + IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO); + IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId); + + IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI); + IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2T= ype << 4) + (PlatformInfoHob.PcieRiser1Type))); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.h b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInf= o/PlatformInfo.h new file mode 100644 index 0000000000..5e46db8f0f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.h @@ -0,0 +1,89 @@ +/** @file + Platform Info Driver. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_INTERNAL_H_ +#define _PLATFORM_INFO_INTERNAL_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "SioRegs.h" +#include +#include +#include +#include +#include + +#define EFI_PLATFORMINFO_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('P', 'I', = 'N', 'F') + +// +// CPU Model +// +#define INVALID_MODEL 0x0 + +#define R_SB_SPI_FDOC 0xB0 +#define R_SB_SPI_FDOD 0xB4 +#define SPI_OPCODE_READ_INDEX 4 +#define PDR_REGION_START_OFFSET 0x0 + +typedef union BOARD_ID +{ + struct{ + UINT8 BoardID0 :1; + UINT8 BoardID1 :1; + UINT8 BoardID2 :1; + UINT8 BoardID3 :1; + UINT8 BoardID4 :1; + UINT8 BoardRev0 :1; + UINT8 BoardRev1 :1; + UINT8 Rsvd :1; + }BoardID; +}BOARD_ID; + +typedef union RISER_ID +{ + struct{ + UINT8 RiserID0 :1; + UINT8 RiserID1 :1; + UINT8 RiserID2 :1; + UINT8 RiserID3 :1; + UINT8 Rsvd :4; + }RiserID; +}RISER_ID; + + + +EFI_STATUS +PdrGetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ); + +EFI_STATUS +GPIOGetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob +); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformI= nfo/PlatformInfo.inf new file mode 100644 index 0000000000..69d926004d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.inf @@ -0,0 +1,63 @@ +## @file +# PlatformInfo PEIM +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformInfo + FILE_GUID =3D 34CC6167-7AE7-403e-8AB2-23837F398A30 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformInfoInit + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + PlatformInfo.c + PlatformInfo.h + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + PeimEntryPoint + PcdLib + DebugLib + HobLib + IoLib + PlatformHooksLib + PeiServicesLib + +[Pcd] + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + +[Guids] + gEfiPlatformInfoGuid + gEfiSetupVariableGuid + +[Ppis] + gPchSpiPpiGuid + gEfiPeiReadOnlyVariable2PpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gPchSpiPpiGuid AND + gEfiPeiReadOnlyVariable2PpiGuid AND + gDynamicSiLibraryPpiGuid + + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHa= ndler/ExSerialStatusCodeWorker.c b/Platform/Intel/WhitleyOpenBoardPkg/Unive= rsal/PeiExStatusCodeHandler/ExSerialStatusCodeWorker.c new file mode 100644 index 0000000000..4336f330e3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/E= xSerialStatusCodeWorker.c @@ -0,0 +1,194 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ExStatusCodeHandlerPei.h" + +/** + Convert status code value and extended data to readable ASCII string, se= nd string to serial I/O device. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation. + @param CodeType Indicates the type of status code being reporte= d. + @param Value Describes the current status of a hardware or + software entity. This includes information abou= t the class and + subclass that is used to classify the entity as= well as an operation. + For progress codes, the operation is the curren= t activity. + For error codes, it is the exception.For debug = codes,it is not defined at this time. + @param Instance The enumeration of a hardware or software entit= y within + the system. A system may contain multiple entit= ies that match a class/subclass + pairing. The instance differentiates between th= em. An instance of 0 indicates + that instance information is unavailable, not m= eaningful, or not relevant. + Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify= the caller. + This parameter allows the status code driver to= apply different rules to + different callers. + @param Data This optional parameter may be used to pass add= itional data. + + @retval EFI_SUCCESS Status code reported to serial I/O successfully. + +**/ +EFI_STATUS +EFIAPI +ExSerialStatusCodeReportWorker ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId, + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL + ) +{ + CHAR8 *Filename; + CHAR8 *Description; + CHAR8 *Format; + CHAR8 Buffer[MAX_EX_DEBUG_STR_LEN]; + CHAR8 *BufferPtr; + UINT32 ErrorLevel; + UINT32 LineNumber; + UINTN CharCount; + BASE_LIST Marker; + EX_DEBUG_INFO *ExDebugInfo =3D NULL; + + Buffer[0] =3D '\0'; + CharCount =3D 0; + + if (Data !=3D NULL && + CompareGuid (&Data->Type, &gStatusCodeDataTypeExDebugGuid)) { + ExDebugInfo =3D (EX_DEBUG_INFO*)(Data + 1); + } else if (Data !=3D NULL && + ReportStatusCodeExtractAssertInfo (CodeType, Value, Data, &Fi= lename, &Description, &LineNumber)) { + // + // Print ASSERT() information into output buffer. + // + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "\n\rPEI_ASSERT!: %a (%d): %a\n\r", + Filename, + LineNumber, + Description + ); + } else if (Data !=3D NULL && + ReportStatusCodeExtractDebugInfo (Data, &ErrorLevel, &Marker,= &Format)) { + // + // Print DEBUG() information into output buffer. + // + CharCount =3D AsciiBSPrint ( + Buffer, + sizeof (Buffer), + Format, + Marker + ); + } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) =3D=3D EFI_ERROR_CODE)= { + // + // Print ERROR information into output buffer. + // + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "ERROR: C%08x:V%08x I%x", + CodeType, + Value, + Instance + ); + + ASSERT(CharCount > 0); + + if (CallerId !=3D NULL) { + CharCount +=3D AsciiSPrint ( + &Buffer[CharCount], + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)), + " %g", + CallerId + ); + } + + if (Data !=3D NULL) { + CharCount +=3D AsciiSPrint ( + &Buffer[CharCount], + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)), + " %x", + Data + ); + } + + CharCount +=3D AsciiSPrint ( + &Buffer[CharCount], + (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)), + "\n\r" + ); + } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) =3D=3D EFI_PROGRESS_CO= DE) { + // + // Print PROGRESS information into output buffer. + // + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "PROGRESS CODE: V%08x I%x\n\r", + Value, + Instance + ); + } else if (Data !=3D NULL && + CompareGuid (&Data->Type, &gEfiStatusCodeDataTypeStringGuid) = && + ((EFI_STATUS_CODE_STRING_DATA *) Data)->StringType =3D=3D Efi= StringAscii) { + // + // EFI_STATUS_CODE_STRING_DATA + // + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "%a\n\r", + ((EFI_STATUS_CODE_STRING_DATA *) Data)->String.Ascii + ); + } else { + // + // Code type is not defined. + // + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "Undefined: C%08x:V%08x I%x\n\r", + CodeType, + Value, + Instance + ); + } + + // + // No EX info, just print and exit. + // + if (ExDebugInfo =3D=3D NULL) { + SerialPortWrite ((UINT8*)Buffer, CharCount); + return EFI_SUCCESS; + } + + // + // EX handling here - point at correct string and then take action. + // Acquire print, process buffer, write to serial, release print. + // Skip any if not requested. + // + CharCount =3D ExDebugInfo->DebugStringLen; + BufferPtr =3D ExDebugInfo->DebugString; + if (ExDebugInfo->PrintSyncAcquire !=3D NULL) { + ExDebugInfo->PrintSyncAcquire (); + } + if (ExDebugInfo->ProcessBuffer !=3D NULL) { + BufferPtr =3D ExDebugInfo->ProcessBuffer ( + ExDebugInfo->ProcessDataPtr, + Buffer, + &CharCount + ); + } + if (BufferPtr !=3D NULL) { + SerialPortWrite ((UINT8*)BufferPtr, CharCount); + } + if (ExDebugInfo !=3D NULL && ExDebugInfo->PrintSyncRelease !=3D NULL) { + ExDebugInfo->PrintSyncRelease (); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHa= ndler/ExStatusCodeHandlerPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Univers= al/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.c new file mode 100644 index 0000000000..5fe58d5d00 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/E= xStatusCodeHandlerPei.c @@ -0,0 +1,111 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ExStatusCodeHandlerPei.h" + +EFI_PEI_EX_RSC_HANDLER_PPI mExStatusCodeHandlerPpi =3D { + RegisterExStatusCodeHandler + }; + +EFI_PEI_PPI_DESCRIPTOR mExStatusCodeHandlerPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiExStatusCodeHandlerPpiGuid, + &mExStatusCodeHandlerPpi + } +}; + +/** + Registers ExSerialStatusCodeReportWorker as callback function for Report= StatusCode() notification. + + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +EFI_STATUS +EFIAPI +RegisterExStatusCodeHandler ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_RSC_HANDLER_PPI *RscHandlerPpi; + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiRscHandlerPpiGuid, + 0, + NULL, + (VOID **) &RscHandlerPpi + ); + ASSERT_EFI_ERROR (Status); + + if (PcdGetBool (PcdStatusCodeUseSerial)) { + Status =3D RscHandlerPpi->Register (ExSerialStatusCodeReportWorker); + if (Status !=3D EFI_ALREADY_STARTED) { + ASSERT_EFI_ERROR (Status); + } + } + return Status; +} + +/** + Entry point of EX Status Code PEIM. + + This function is the entry point of this EX Status Code PEIM. + It initializes serial port status code handler with policy features. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCESS The entry point of PEIM executes successfully. + +**/ +EFI_STATUS +EFIAPI +ExStatusCodeHandlerPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UINT32 DebugPrintErrorLevel; + + // + // Dispatch initialization request to sub-statuscode-devices. + // + Status =3D SerialPortInitialize(); + ASSERT_EFI_ERROR (Status); + + // + // If serial logging is disabled. set PcdStatusCodeUseSerial to FALSE. + // + + DebugPrintErrorLevel =3D GetDebugPrintErrorLevel (); + if (DebugPrintErrorLevel =3D=3D 0) { + Status =3D PcdSetBoolS (PcdStatusCodeUseSerial, FALSE); + ASSERT_EFI_ERROR (Status); + } + + Status =3D RegisterExStatusCodeHandler (PeiServices); + ASSERT_EFI_ERROR (Status); + + // + // Install Report Status Code Handler PPI + // + Status =3D PeiServicesInstallPpi (mExStatusCodeHandlerPpiList); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHa= ndler/ExStatusCodeHandlerPei.h b/Platform/Intel/WhitleyOpenBoardPkg/Univers= al/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.h new file mode 100644 index 0000000000..4d101a0c2d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/E= xStatusCodeHandlerPei.h @@ -0,0 +1,85 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __EX_STATUS_CODE_HANDLER_PEI_H__ +#define __EX_STATUS_CODE_HANDLER_PEI_H__ + + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Registers ExSerialStatusCodeReportWorker as callback function for Report= StatusCode() notification. + + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +EFI_STATUS +EFIAPI +RegisterExStatusCodeHandler ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + Convert status code value and extended data to readable ASCII string, se= nd string to serial I/O device. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation. + @param CodeType Indicates the type of status code being reporte= d. + @param Value Describes the current status of a hardware or + software entity. This includes information abou= t the class and + subclass that is used to classify the entity as= well as an operation. + For progress codes, the operation is the curren= t activity. + For error codes, it is the exception.For debug = codes,it is not defined at this time. + @param Instance The enumeration of a hardware or software entit= y within + the system. A system may contain multiple entit= ies that match a class/subclass + pairing. The instance differentiates between th= em. An instance of 0 indicates + that instance information is unavailable, not m= eaningful, or not relevant. + Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify= the caller. + This parameter allows the status code driver to= apply different rules to + different callers. + @param Data This optional parameter may be used to pass add= itional data. + + @retval EFI_SUCCESS Status code reported to serial I/O successfully. + +**/ +EFI_STATUS +EFIAPI +ExSerialStatusCodeReportWorker ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId, + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL + ); + +#endif // __EX_STATUS_CODE_HANDLER_PEI_H__ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHa= ndler/ExStatusCodeHandlerPei.inf b/Platform/Intel/WhitleyOpenBoardPkg/Unive= rsal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf new file mode 100644 index 0000000000..083de9850f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/E= xStatusCodeHandlerPei.inf @@ -0,0 +1,61 @@ +## @file +# Report Status Code Handler PEIM which produces general handlers and hoo= k them onto the PEI status code router. +# +# @copyright +# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ExStatusCodeHandlerPei + FILE_GUID =3D 75E78806-C68F-4839-8A68-B29084820659 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ExStatusCodeHandlerPeiEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is only for build) +# + +[Sources] + ExStatusCodeHandlerPei.c + ExStatusCodeHandlerPei.h + ExSerialStatusCodeWorker.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + PcdLib + HobLib + SerialPortLib + ReportStatusCodeLib + PrintLib + DebugLib + DebugPrintErrorLevelLib + BaseMemoryLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial ## CONSUMES + +[Guids] + gEfiStatusCodeDataTypeStringGuid ## SOMETIMES_CONSUMES + gStatusCodeDataTypeExDebugGuid ## SOMETIMES_CONSUMES + +[Ppis] + gEfiPeiRscHandlerPpiGuid ## CONSUMES + gEfiPeiExStatusCodeHandlerPpiGuid ## PRODUCES + +[Depex] + gEfiPeiRscHandlerPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRo= uter/ExReportStatusCodeRouterPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Uni= versal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.c new file mode 100644 index 0000000000..99dd891ccd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/Ex= ReportStatusCodeRouterPei.c @@ -0,0 +1,301 @@ +/** @file + Report Status Code Router PEIM which produces Report Stataus Code Handle= r PPI and Status Code PPI. + + @copyright + Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "ExReportStatusCodeRouterPei.h" + +EFI_PEI_RSC_HANDLER_PPI mRscHandlerPpi =3D { + Register, + Unregister + }; + +EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi =3D { + ReportDispatcher + }; + +EFI_PEI_PPI_DESCRIPTOR mRscHandlerPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiRscHandlerPpiGuid, + &mRscHandlerPpi + } +}; + +EFI_PEI_PPI_DESCRIPTOR mStatusCodePpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiStatusCodePpiGuid, + &mStatusCodePpi + } +}; + +/** + Worker function to create one memory status code GUID'ed HOB, + using PacketIndex to identify the packet. + + @param PacketIndex Index of records packet. + + @return Pointer to the memory status code packet. + +**/ +UINTN * +CreateRscHandlerCallbackPacket ( + VOID + ) +{ + UINTN *NumberOfEntries; + EFI_PEI_RSC_HANDLER_CALLBACK *CallbackEntry; + UINT16 Index; + + // + // Build GUID'ed HOB with PCD defined size. + // + NumberOfEntries =3D BuildGuidHob ( + &gStatusCodeCallbackGuid, + sizeof (EFI_PEI_RSC_HANDLER_CALLBACK) * 64 + sizeof = (UINTN) + ); + ASSERT (NumberOfEntries !=3D NULL); + if (NumberOfEntries =3D=3D NULL) { + return NumberOfEntries; + } + + *NumberOfEntries =3D 0; + CallbackEntry =3D (EFI_PEI_RSC_HANDLER_CALLBACK *) (NumberOfEntries + = 1); + + for (Index =3D 0; Index < 64; Index++) { + CallbackEntry[Index] =3D NULL; + } + + return NumberOfEntries; +} + +/** + Register the callback function for ReportStatusCode() notification. + + When this function is called the function pointer is added to an interna= l list and any future calls to + ReportStatusCode() will be forwarded to the Callback function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RS= C_HANDLER_CALLBACK that is called + when a call to ReportStatusCode() occurs. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +EFI_STATUS +EFIAPI +Register ( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_PEI_RSC_HANDLER_CALLBACK *CallbackEntry; + UINTN *NumberOfEntries; + UINTN Index; + + if (Callback =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Hob.Raw =3D GetFirstGuidHob (&gStatusCodeCallbackGuid); + if (Hob.Raw !=3D NULL) { + NumberOfEntries =3D GET_GUID_HOB_DATA (Hob); + CallbackEntry =3D (EFI_PEI_RSC_HANDLER_CALLBACK *) (NumberOfEntries = + 1); + if (*NumberOfEntries >=3D 64) { + // + // If current total number of handlers does exceed 64, bail + // + return EFI_OUT_OF_RESOURCES; + } + for (Index =3D 0; Index <=3D *NumberOfEntries; Index++) { + if (CallbackEntry[Index] =3D=3D Callback) { + // + // If the function was already registered. It can't be registered = again. + // + return EFI_ALREADY_STARTED; + } + if (CallbackEntry[Index] =3D=3D NULL) { + // + // If the total number of handlers in current packet is max value = 64, + // search an entry with NULL pointer and fill new handler into thi= s entry. + // + *NumberOfEntries +=3D 1; + CallbackEntry[Index] =3D Callback; + + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Remove a previously registered callback function from the notification l= ist. + + ReportStatusCode() messages will no longer be forwarded to the Callback = function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RS= C_HANDLER_CALLBACK that is to be + unregistered. + + @retval EFI_SUCCESS The function was successfully unregistered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_NOT_FOUND The callback function was not found to be = unregistered. + +**/ +EFI_STATUS +EFIAPI +Unregister ( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_PEI_RSC_HANDLER_CALLBACK *CallbackEntry; + UINTN *NumberOfEntries; + UINTN Index; + + if (Callback =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Hob.Raw =3D GetFirstGuidHob (&gStatusCodeCallbackGuid); + if (Hob.Raw !=3D NULL) { + NumberOfEntries =3D GET_GUID_HOB_DATA (Hob); + CallbackEntry =3D (EFI_PEI_RSC_HANDLER_CALLBACK *) (NumberOfEntries = + 1); + for (Index =3D 0; Index < *NumberOfEntries; Index++) { + if (CallbackEntry[Index] =3D=3D Callback) { + // + // Set removed entry as NULL. + // + CallbackEntry[Index] =3D NULL; + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Publishes an interface that allows PEIMs to report status codes. + + This function implements EFI_PEI_PROGRESS_CODE_PPI.ReportStatusCode(). + It publishes an interface that allows PEIMs to report status codes. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation. + @param CodeType Indicates the type of status code being reporte= d. + @param Value Describes the current status of a hardware or + software entity. This includes information abou= t the class and + subclass that is used to classify the entity as= well as an operation. + For progress codes, the operation is the curren= t activity. + For error codes, it is the exception.For debug = codes,it is not defined at this time. + @param Instance The enumeration of a hardware or software entit= y within + the system. A system may contain multiple entit= ies that match a class/subclass + pairing. The instance differentiates between th= em. An instance of 0 indicates + that instance information is unavailable, not m= eaningful, or not relevant. + Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify= the caller. + This parameter allows the status code driver to= apply different rules to + different callers. + @param Data This optional parameter may be used to pass add= itional data. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +ReportDispatcher ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId OPTIONAL, + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_PEI_RSC_HANDLER_CALLBACK *CallbackEntry; + UINTN *NumberOfEntries; + UINTN Index; + + Hob.Raw =3D GetFirstGuidHob (&gStatusCodeCallbackGuid); + if (Hob.Raw !=3D NULL) { + NumberOfEntries =3D GET_GUID_HOB_DATA (Hob); + CallbackEntry =3D (EFI_PEI_RSC_HANDLER_CALLBACK *) (NumberOfEntries = + 1); + for (Index =3D 0; Index < *NumberOfEntries; Index++) { + if (CallbackEntry[Index] !=3D NULL) { + CallbackEntry[Index]( + PeiServices, + CodeType, + Value, + Instance, + CallerId, + Data + ); + } + } + } + + return EFI_SUCCESS; +} + +/** + Entry point of Status Code PEIM. + + This function is the entry point of this Status Code Router PEIM. + It produces Report Stataus Code Handler PPI and Status Code PPI. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCESS The entry point of DXE IPL PEIM executes successfull= y. + +**/ +EFI_STATUS +EFIAPI +GenericStatusCodePeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; + EFI_PEI_PROGRESS_CODE_PPI *OldStatusCodePpi; + + CreateRscHandlerCallbackPacket (); + + // + // Install Report Status Code Handler PPI + // + Status =3D PeiServicesInstallPpi (mRscHandlerPpiList); + ASSERT_EFI_ERROR (Status); + + // + // Install Status Code PPI. PI spec specifies that there can be only one= instance + // of this PPI in system. So first check if other instance already exist= s. + // If no other instance exists, then just install the PPI. + // If other instance already exists, then reinstall it. + // + Status =3D PeiServicesLocatePpi ( + &gEfiPeiStatusCodePpiGuid, + 0, + &OldDescriptor, + (VOID **) &OldStatusCodePpi + ); + if (!EFI_ERROR (Status)) { + Status =3D PeiServicesReInstallPpi (OldDescriptor, mStatusCodePpiList); + } else { + Status =3D PeiServicesInstallPpi (mStatusCodePpiList); + } + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRo= uter/ExReportStatusCodeRouterPei.h b/Platform/Intel/WhitleyOpenBoardPkg/Uni= versal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.h new file mode 100644 index 0000000000..32b709ca15 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/Ex= ReportStatusCodeRouterPei.h @@ -0,0 +1,104 @@ +/** @file + Internal include file for Report Status Code Router PEIM. + + @copyright + Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PEI_REPORT_STATUS_CODE_ROUTER_H__ +#define __PEI_REPORT_STATUS_CODE_ROUTER_H__ + + +#include +#include + +#include + +#include +#include +#include +#include + +/** + Register the callback function for ReportStatusCode() notification. + + When this function is called the function pointer is added to an interna= l list and any future calls to + ReportStatusCode() will be forwarded to the Callback function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RS= C_HANDLER_CALLBACK that is called + when a call to ReportStatusCode() occurs. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No m= ore functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It ca= n't be registered again. + +**/ +EFI_STATUS +EFIAPI +Register ( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback + ); + +/** + Remove a previously registered callback function from the notification l= ist. + + ReportStatusCode() messages will no longer be forwarded to the Callback = function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RS= C_HANDLER_CALLBACK that is to be + unregistered. + + @retval EFI_SUCCESS The function was successfully unregistered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_NOT_FOUND The callback function was not found to be = unregistered. + +**/ +EFI_STATUS +EFIAPI +Unregister ( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback + ); + +/** + Publishes an interface that allows PEIMs to report status codes. + + This function implements EFI_PEI_PROGRESS_CODE_PPI.ReportStatusCode(). + It publishes an interface that allows PEIMs to report status codes. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation. + @param CodeType Indicates the type of status code being reporte= d. + @param Value Describes the current status of a hardware or + software entity. This includes information abou= t the class and + subclass that is used to classify the entity as= well as an operation. + For progress codes, the operation is the curren= t activity. + For error codes, it is the exception.For debug = codes,it is not defined at this time. + @param Instance The enumeration of a hardware or software entit= y within + the system. A system may contain multiple entit= ies that match a class/subclass + pairing. The instance differentiates between th= em. An instance of 0 indicates + that instance information is unavailable, not m= eaningful, or not relevant. + Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify= the caller. + This parameter allows the status code driver to= apply different rules to + different callers. + @param Data This optional parameter may be used to pass add= itional data. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +ReportDispatcher ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId OPTIONAL, + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL + ); + +#endif + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRo= uter/ExReportStatusCodeRouterPei.inf b/Platform/Intel/WhitleyOpenBoardPkg/U= niversal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf new file mode 100644 index 0000000000..b46775ab55 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/Ex= ReportStatusCodeRouterPei.inf @@ -0,0 +1,51 @@ +## @file +# Report Status Code Router PEIM which produces Report Stataus Code Handl= er PPI and Status Code PPI. +# +# @copyright +# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ExReportStatusCodeRouterPei + FILE_GUID =3D 1DDA5978-B29A-4EA7-AEFB-8B0BAA982E22 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D GenericStatusCodePeiEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC (EBC is only for bui= ld) +# + +[Sources] + ExReportStatusCodeRouterPei.c + ExReportStatusCodeRouterPei.h + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + DebugLib + HobLib + +[Guids] + ## PRODUCES ## HOB + ## CONSUMES ## HOB + gStatusCodeCallbackGuid + +[Ppis] + gEfiPeiRscHandlerPpiGuid ## PRODUCES + gEfiPeiStatusCodePpiGuid ## PRODUCES + + +[Depex] + TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSv= idMap/PeiInterposerToSvidMap.c b/Platform/Intel/WhitleyOpenBoardPkg/Univers= al/PeiInterposerToSvidMap/PeiInterposerToSvidMap.c new file mode 100644 index 0000000000..1fdefe9ef6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/P= eiInterposerToSvidMap.c @@ -0,0 +1,136 @@ +/** @file + File to update SVID values from Interposer mapping. + +@copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + After Memory policy installation need to map SVID in case of an Interpos= er is present. + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +MapInterposerToSvid ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + INTERPOSER_TYPE InterposerType; + EFI_PLATFORM_INFO *PlatformInfo; + EFI_HOB_GUID_TYPE *GuidHob; + UINT8 OriginalMcId =3D 0; + UINT8 CurrentMcId =3D 0; + UINT8 Socket =3D 0; + UINT8 SvidValue =3D 0; + MEM_SVID_MAP *MemSvidMap; + UINTN Size; + EFI_STATUS Status; + INTERPOSER_MAP *MemInterposerMap =3D NULL; + BOOLEAN InterposerPresent =3D FALSE; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + DEBUG ((EFI_D_INFO, "MapInterposerToSvid Entry\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + DEBUG ((EFI_D_INFO, "No Platform Info HOB Detected Exiting...\n")); + return EFI_SUCCESS; + } else { + MemInterposerMap =3D (INTERPOSER_MAP *) PcdGetPtr (PcdMemInterposerMap= ); + if (MemInterposerMap =3D=3D NULL) { + return EFI_SUCCESS; + } + Size =3D sizeof (MEM_SVID_MAP); + DEBUG ((EFI_D_INFO, "Allocate memory for MemSvidMap PCD\n")); + Status =3D (*PeiServices)->AllocatePool (PeiServices, Size, &MemSvidMa= p); + ASSERT_EFI_ERROR (Status); + ZeroMem (MemSvidMap, Size); + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + InterposerType =3D PlatformInfo->InterposerType[Socket]; + for (CurrentMcId =3D0; CurrentMcId < MAX_IMC; CurrentMcId++) { + if (InterposerType !=3D InterposerUnknown) { + OriginalMcId =3D MemInterposerMap->Interposer[InterposerType].Ma= ppedMcId[CurrentMcId]; + if (OriginalMcId < MAX_IMC) { + Status =3D DynamicSiLibraryPpi->GetSvidMap (Socket, OriginalMc= Id, &SvidValue); + + if(Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "PcdMemSrVidMap =3D NULL\n")); + } else { + DEBUG ((DEBUG_ERROR, "SocketId =3D %d, McId =3D %d, SvidValu= e =3D %d\n", Socket, OriginalMcId, SvidValue)); + } + + MemSvidMap->Socket[Socket].Mc[CurrentMcId] =3D SvidValue; + InterposerPresent =3D TRUE; + } + DEBUG ((EFI_D_INFO, "Current MC id =3D %d, Original MC id =3D %d= , SVID =3D %d\n", CurrentMcId, OriginalMcId, SvidValue)); + } + } + } + } + if (InterposerPresent) { + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); + } else { + DEBUG ((EFI_D_INFO, "No Interposer Present....\n")); + } + + DEBUG ((EFI_D_INFO, "MapInterposerToSvid Exit\n")); + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mMapInterposerToSvidNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gMemoryPolicyPpiGuid, + MapInterposerToSvid +}; + +/** + Initialize SVID PCD with Interposer mapping + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully +**/ +EFI_STATUS +EFIAPI +InterposerToSvidMapEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + DEBUG ((EFI_D_INFO, "InterposerToSvidMap Entry\n")); + + Status =3D PeiServicesNotifyPpi (&mMapInterposerToSvidNotifyList); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_INFO, "InterposerToSvidMap Exit\n")); + return EFI_SUCCESS;; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSv= idMap/PeiInterposerToSvidMap.inf b/Platform/Intel/WhitleyOpenBoardPkg/Unive= rsal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf new file mode 100644 index 0000000000..c311425846 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/P= eiInterposerToSvidMap.inf @@ -0,0 +1,53 @@ +## @file +# Component description file for PeiInterposerToSvidMap +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiInterposerToSvidMap + FILE_GUID =3D DF11893B-FAC7-4812-8DD7-F5DD56889040 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InterposerToSvidMapEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + + PeiInterposerToSvidMap.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[LibraryClasses] + DebugLib + PeimEntryPoint + PcdLib + BaseMemoryLib + +[Ppis] + gMemoryPolicyPpiGuid ## CONSUMES + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gEfiPlatformInfoGuid + +[Pcd] + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + +[Depex] + gDynamicSiLibraryPpiGuid --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 12/17] WhitleyOpenBoardPkg: Add Feature Modules Date: Mon, 12 Jul 2021 17:41:26 -0700 Message-Id: <20210713004131.1782-13-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: nz7V3qoddVOT72KmYojBTugrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136932; bh=ERNXZuV+/nWEasAJZW7GjjPV1KCwl3346hzVD9RO7kg=; h=Cc:Date:From:Reply-To:Subject:To; b=Xr8HttyIb9XzmLddfT+GxQVxqIN+NSnJm6N9YPIEIQBcWJAY7Y/xPsiyosl3tl3yzNJ 2Ibx+8VpDF2BA7l9XLz6p2O9roiMthWwvqBxjFwx3dmctFF+Tw0QCiyIosEjAxy/3PjXj TqOXB+0jbjW3Y1JOCK1JnRK+sH0pGOfC8A4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136934150100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Pci/Dxe/PciHostBridge/PciHostBridge.c | 1634 ++++++++++++++++ .../Pci/Dxe/PciHostBridge/PciHostBridge.h | 300 +++ .../Pci/Dxe/PciHostBridge/PciHostBridge.inf | 69 + .../Dxe/PciHostBridge/PciHostBridgeSupport.c | 127 ++ .../Pci/Dxe/PciHostBridge/PciHostResource.h | 62 + .../Pci/Dxe/PciHostBridge/PciRebalance.c | 1356 ++++++++++++++ .../Pci/Dxe/PciHostBridge/PciRebalance.h | 158 ++ .../Pci/Dxe/PciHostBridge/PciRebalanceIo.c | 218 +++ .../Dxe/PciHostBridge/PciRebalanceMmio32.c | 163 ++ .../Dxe/PciHostBridge/PciRebalanceMmio64.c | 204 ++ .../Pci/Dxe/PciHostBridge/PciRootBridge.h | 573 ++++++ .../Pci/Dxe/PciHostBridge/PciRootBridgeIo.c | 1664 +++++++++++++++++ .../Dxe/PciPlatform/PciIovPlatformPolicy.c | 99 + .../Dxe/PciPlatform/PciIovPlatformPolicy.h | 53 + .../Pci/Dxe/PciPlatform/PciPlatform.c | 541 ++++++ .../Pci/Dxe/PciPlatform/PciPlatform.h | 209 +++ .../Pci/Dxe/PciPlatform/PciPlatform.inf | 87 + .../Pci/Dxe/PciPlatform/PciPlatformHooks.c | 939 ++++++++++ .../Pci/Dxe/PciPlatform/PciPlatformHooks.h | 31 + .../Pci/Dxe/PciPlatform/PciSupportLib.c | 108 ++ .../Pci/Dxe/PciPlatform/PciSupportLib.h | 46 + .../Pei/PlatformVariableInitPei.c | 274 +++ .../Pei/PlatformVariableInitPei.h | 41 + .../Pei/PlatformVariableInitPei.inf | 58 + 24 files changed, 9014 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciHostBridge.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciHostBridge.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciHostBridge.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciHostBridgeSupport.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciHostResource.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRebalance.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRebalance.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRebalanceIo.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRebalanceMmio32.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRebalanceMmio64.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRootBridge.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= HostBridge/PciRootBridgeIo.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciIovPlatformPolicy.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciIovPlatformPolicy.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatform.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatform.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatform.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatformHooks.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatformHooks.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciSupportLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciSupportLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/Pl= atformVariable/Pei/PlatformVariableInitPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/Pl= atformVariable/Pei/PlatformVariableInitPei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/Pl= atformVariable/Pei/PlatformVariableInitPei.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciHostBridge.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/P= ciHostBridge/PciHostBridge.c new file mode 100644 index 0000000000..a15fff4817 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= HostBridge.c @@ -0,0 +1,1634 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "PciHostBridge.h" +#include "PciRootBridge.h" +#include "PciHostResource.h" + +#include +#include +#include +#include + +#include + +#include "PciRebalance.h" + + +/*************************************************************************= ***** + * Local definitions. + *************************************************************************= *****/ +typedef struct { + PCI_ROOT_BRIDGE_INSTANCE RootBridge; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH RootDevPath; +} PCI_ROOT_BRIDGE_WITH_PATH; + + +/*************************************************************************= ***** + * Variables. + *************************************************************************= *****/ +GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; +GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] =3D { + L"I/O", L"Mem32", L"PMem32", L"Mem64", L"PMem64", L"Bus" +}; + +// +// We can hardcode the following for a Simple IIO - +// Root Bridge Count within the Host bridge +// Root Bridge's device path +// Root Bridge's resource appeture +// + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePathTempl= ate =3D { + {{ACPI_DEVICE_PATH, + ACPI_DP, + {(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)}}, + EISA_PNP_ID(0x0A03), + 0}, + {END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + {END_DEVICE_PATH_LENGTH, + 0}} + }; + +STATIC EFI_HANDLE mDriverImageHandle; + +EDKII_IOMMU_PROTOCOL *mIoMmu; +EFI_EVENT mIoMmuEvent; +VOID *mIoMmuRegistration; + +EFI_IIO_UDS_PROTOCOL *mIioUds; +PCI_HOST_BRIDGE_INSTANCE *mHostBridge; + +/** + Event notification that is fired when IOMMU protocol is installed. + + @param Event The Event that is being processed. + @param Context Event Context. + +**/ +VOID +EFIAPI +IoMmuProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **= )&mIoMmu); + if (!EFI_ERROR(Status)) { + gBS->CloseEvent (mIoMmuEvent); + } +} + + +/** + + Entry point of this driver. + + @param ImageHandle Image handle of this driver. + @param SystemTable Pointer to standard EFI system table. + + @retval EFI_SUCCESS Succeed. + @retval EFI_DEVICE_ERROR Fail to install PCI_ROOT_BRIDGE_IO protocol. + +**/ +EFI_STATUS +EFIAPI +InitializePciHostBridge ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN IioIndex; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINTN IioStack; + UINT64 ResourceLength; + PCI_ROOT_BRIDGE_RESOURCE_APERTURE RbAperture; + + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *TempDevicePath; + STACK_RES *CurStackRes; + + mDriverImageHandle =3D ImageHandle; + // + // Located the IIO Protocol Interface + // + Status =3D gBS->LocateProtocol (&gEfiIioUdsProtocolGuid, NULL, &mIioUds); + ASSERT_EFI_ERROR (Status); + + // + // Most systems in the world including complex servers have only one Hos= t Bridge. + // + HostBridge =3D AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE)); + if (HostBridge =3D=3D NULL) { + ASSERT(FALSE); + return EFI_OUT_OF_RESOURCES; + } + HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; + HostBridge->RootBridgeCount =3D 0; + HostBridge->ResourceSubmited =3D FALSE; + HostBridge->CanRestarted =3D TRUE; + InitializeListHead (&HostBridge->RootBridges); + + HostBridge->ResAlloc.NotifyPhase =3D NotifyPhase; + HostBridge->ResAlloc.GetNextRootBridge =3D GetNextRootBridge; + HostBridge->ResAlloc.GetAllocAttributes =3D GetAttributes; + HostBridge->ResAlloc.StartBusEnumeration =3D StartBusEnumeration; + HostBridge->ResAlloc.SetBusNumbers =3D SetBusNumbers; + HostBridge->ResAlloc.SubmitResources =3D SubmitResources; + HostBridge->ResAlloc.GetProposedResources =3D GetProposedResources; + HostBridge->ResAlloc.PreprocessController =3D PreprocessController; + + Status =3D gBS->InstallProtocolInterface ( + &HostBridge->Handle, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + EFI_NATIVE_INTERFACE, + &HostBridge->ResAlloc + ); + if (EFI_ERROR (Status)) { + FreePool (HostBridge); + return EFI_DEVICE_ERROR; + } + + // + // Create Root Bridges in this Host Bridge. + // + for (IioIndex =3D 0; IioIndex < mIioUds->IioUdsPtr->PlatformData.numofII= O; IioIndex++) { + + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].Valid) { + continue; + } // No guarantee that the valid IIOs are sequential starting at 0! + + for (IioStack =3D 0; IioStack < MAX_IIO_STACK; IioStack++) { + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[IioIndex].stackPre= sentBitmap & (1 << IioStack))) { + continue; + } + // Skip stack which is disabled by resource limitation or DEBUG purp= ose! + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].StackRes= [IioStack].Personality >=3D TYPE_DISABLED) { + continue; + } + // + // Create Root Bridge Instance + // + RootBridge =3D AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_WITH_PATH)); + if (RootBridge =3D=3D NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + TempDevicePath =3D &((PCI_ROOT_BRIDGE_WITH_PATH*)RootBridge)->RootDe= vPath; + + RootBridge->Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; + RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL*)TempDevicePath; + CopyMem (TempDevicePath, &mEfiPciRootBridgeDevicePathTemplate, sizeo= f(*TempDevicePath)); + TempDevicePath->AcpiDevicePath.UID =3D (UINT32)(IioIndex * MAX_IIO_S= TACK + IioStack); + + ZeroMem(&RbAperture, sizeof(RbAperture)); + { + // + // Update Root Bridge with UDS resource information + // + RbAperture.BusBase =3D mIioUds->IioUdsPtr->PlatformData.IIO_resour= ce[IioIndex].StackRes[IioStack].BusBase; + RbAperture.BusLimit =3D mIioUds->IioUdsPtr->PlatformData.IIO_resou= rce[IioIndex].StackRes[IioStack].BusLimit; + RbAperture.Mem32Base =3D mIioUds->IioUdsPtr->PlatformData.IIO_reso= urce[IioIndex].StackRes[IioStack].PciResourceMem32Base; + RbAperture.Mem32Limit =3D mIioUds->IioUdsPtr->PlatformData.IIO_res= ource[IioIndex].StackRes[IioStack].PciResourceMem32Limit; + RbAperture.BusReserve =3D 0; + if ((mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].Stack= Res[IioStack].PciResourceMem64Limit > + mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].Stack= Res[IioStack].PciResourceMem64Base) && + (mIioUds->IioUdsPtr->PlatformData.Pci64BitResourceAllocation))= { + RbAperture.Mem64Base =3D mIioUds->IioUdsPtr->PlatformData.IIO_re= source[IioIndex].StackRes[IioStack].PciResourceMem64Base; + RbAperture.Mem64Limit =3D mIioUds->IioUdsPtr->PlatformData.IIO_r= esource[IioIndex].StackRes[IioStack].PciResourceMem64Limit; + } + RbAperture.IoBase =3D mIioUds->IioUdsPtr->PlatformData.IIO_resourc= e[IioIndex].StackRes[IioStack].PciResourceIoBase; + RbAperture.IoLimit =3D mIioUds->IioUdsPtr->PlatformData.IIO_resour= ce[IioIndex].StackRes[IioStack].PciResourceIoLimit; + + SimpleIioRootBridgeConstructor (&RootBridge->RootBridgeIo, HostBri= dge->Handle, &RbAperture, + mIioUds->IioUdsPtr->PlatformData.C= puQpiInfo[IioIndex].PcieSegment, + GetAllocAttributes (HostBridge->Ro= otBridgeCount)); + DEBUG ((DEBUG_INFO, "[PCI] Create Root Bridge for [%d.%d] in PCI s= egment %d with below resource:\n", IioIndex, IioStack, RootBridge->RootBrid= geIo.SegmentNumber)); + DEBUG ((DEBUG_INFO, " Bus: Base =3D 0x%08x, Limit =3D 0x%08= x, BusReserve =3D 0x%08x\n", RootBridge->Aperture.BusBase, RootBridge->Aper= ture.BusLimit, RootBridge->Aperture.BusReserve)); + DEBUG ((DEBUG_INFO, " IO: Base =3D 0x%08x, Limit =3D 0x%08= x\n", RootBridge->Aperture.IoBase, RootBridge->Aperture.IoLimit)); + DEBUG ((DEBUG_INFO, " Mem32: Base =3D 0x%08x, Limit =3D 0x%08= x\n", RootBridge->Aperture.Mem32Base, RootBridge->Aperture.Mem32Limit)); + DEBUG ((DEBUG_INFO, " Mem64: Base =3D 0x%lx, Limit =3D 0x%lx\= n", RootBridge->Aperture.Mem64Base, RootBridge->Aperture.Mem64Limit)); + // + // Insert Root Bridge Instance + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &RootBridge->Handle, + &gEfiDevicePathProtocolGuid, + RootBridge->DevicePath, + &gEfiPciRootBridgeIoProtocolGuid, + &RootBridge->RootBridgeIo, + NULL + ); + ASSERT_EFI_ERROR (Status); + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); + mPciRootBridgeTable[IioIndex][IioStack] =3D RootBridge; + HostBridge->RootBridgeCount++; + } + } // for (IioStack...) + } // for (IioIndex...) + // + // Add PCIE base into Runtime memory so that it can be reported in E820 = table + // + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + mIioUds->IioUdsPtr->PlatformData.PciExpressBase, + mIioUds->IioUdsPtr->PlatformData.PciExpressSize, + EFI_MEMORY_RUNTIME | EFI_MEMORY_UC + ); + ASSERT_EFI_ERROR(Status); + + BaseAddress =3D mIioUds->IioUdsPtr->PlatformData.PciExpressBase; + + Status =3D gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeMemoryMappedIo, + 0, + mIioUds->IioUdsPtr->PlatformData.PciExpressSize, + &BaseAddress, + ImageHandle, + NULL + ); + ASSERT_EFI_ERROR(Status); + + Status =3D gDS->SetMemorySpaceAttributes ( + mIioUds->IioUdsPtr->PlatformData.PciExpressBase, + mIioUds->IioUdsPtr->PlatformData.PciExpressSize, + EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + //s4030180 + for (IioIndex =3D 0; IioIndex < mIioUds->IioUdsPtr->PlatformData.numofII= O; IioIndex++) { + + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].Valid) { + continue; + } // No guarantee that the valid IIOs are sequential starting at 0! + for (IioStack =3D 0; IioStack < MAX_IIO_STACK; IioStack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[IioIndex].stackPre= sentBitmap & (1 << IioStack))) { + continue; + } + + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].StackRes= [IioStack].PciResourceIoLimit > + mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].StackRe= s[IioStack].PciResourceIoBase) { + // + // At present, we use up the first 4k for fixed ranges like + // ICH GPIO, ACPI and ISA devices. The first 4k is not + // tracked through GCD. It should be. + // + Status =3D gDS->AddIoSpace ( + EfiGcdIoTypeIo, + mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioI= ndex].StackRes[IioStack].PciResourceIoBase , + (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Iio= Index].StackRes[IioStack].PciResourceIoLimit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Iio= Index].StackRes[IioStack].PciResourceIoBase + 1) + ); + ASSERT_EFI_ERROR (Status); + } + + CurStackRes =3D &mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIn= dex].StackRes[IioStack]; + if (CurStackRes->PciResourceMem32Limit > CurStackRes->PciResourceMem= 32Base) { + // + // Shouldn't the capabilities be UC? + // + ResourceLength =3D CurStackRes->PciResourceMem32Limit - CurStackRe= s->PciResourceMem32Base + 1; + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + CurStackRes->PciResourceMem32Base, + ResourceLength, + 0 + ); + ASSERT_EFI_ERROR (Status); + // + // Track VT-d bar in GCD. + // + // We now have a region of memory x-z associated with this stack + // and there is also subregion y-z that is the VT-d space (x <=3D = y <=3D z) + BaseAddress =3D CurStackRes->VtdBarAddress; + ResourceLength =3D CurStackRes->PciResourceMem32Limit - BaseAddres= s + 1; + Status =3D gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeMemoryMappedIo, + 0, + ResourceLength, + &BaseAddress, + ImageHandle, + NULL + ); + ASSERT_EFI_ERROR(Status); + } + + if ((mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].StackRe= s[IioStack].PciResourceMem64Limit > + mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioIndex].Stack= Res[IioStack].PciResourceMem64Base) && + (mIioUds->IioUdsPtr->PlatformData.Pci64BitResourceAllocation)= ) { + + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + mIioUds->IioUdsPtr->PlatformData.IIO_resource[I= ioIndex].StackRes[IioStack].PciResourceMem64Base , + (mIioUds->IioUdsPtr->PlatformData.IIO_resource[= IioIndex].StackRes[IioStack].PciResourceMem64Limit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[= IioIndex].StackRes[IioStack].PciResourceMem64Base + 1), + 0 + ); + ASSERT_EFI_ERROR (Status); + } + } + } + + if (!EFI_ERROR (Status)) { + mIoMmuEvent =3D EfiCreateProtocolNotifyEvent ( + &gEdkiiIoMmuProtocolGuid, + TPL_CALLBACK, + IoMmuProtocolCallback, + NULL, + &mIoMmuRegistration + ); + } + mHostBridge =3D HostBridge; + return EFI_SUCCESS; +} + + +/** + Enter the EfiPciHostBridgeBeginEnumeration phase of the PCI(e) + numeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + + @retval EFI_SUCCESS + @retval EFI_NOT_READY +*/ +STATIC EFI_STATUS +BeginBridgeEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + LIST_ENTRY *List; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + PCI_RESOURCE_TYPE Index; + + Index =3D TypeMax; + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + + if (HostBridge->CanRestarted) { + // + // Reset Root Bridge + // + List =3D HostBridge->RootBridges.ForwardLink; + + while (List !=3D &HostBridge->RootBridges) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + for (Index =3D TypeIo; Index < TypeMax; Index++) { + RootBridge->ResAllocNode[Index].Type =3D Index; + RootBridge->ResAllocNode[Index].Base =3D 0; + RootBridge->ResAllocNode[Index].Length =3D 0; + RootBridge->ResAllocNode[Index].Status =3D ResNone; + } // for + + List =3D List->ForwardLink; + } // while + + HostBridge->ResourceSubmited =3D FALSE; + HostBridge->CanRestarted =3D TRUE; + } else { + // + // Can not restart + // + return EFI_NOT_READY; + } // if + + return EFI_SUCCESS; +} + + +/** + Enter the EfiPciHostBridgeAllocateResources phase of the + PCI(e) numeration process. + + @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ins= tance. + + @retval EFI_SUCCESS + @retval EFI_NOT_READY + @retval EFI_OUT_OF_RESOURCES +*/ +STATIC EFI_STATUS +BridgeAllocateResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + PCI_RESOURCE_TYPE Index; + LIST_ENTRY *List; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 AddrLen; + UINTN BitsOfAlignment; + UINT64 Alignment; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + PCI_RESOURCE_TYPE Index1; + PCI_RESOURCE_TYPE Index2; + BOOLEAN ResNodeHandled[TypeMax]; + UINT64 MaxAlignment; + SOCKET_RESOURCE_ADJUSTMENT_RESULT RatioAdjustResult; + UINT8 Socket; + UINT8 Stack; + + Index =3D TypeMax; + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + + ReturnStatus =3D EFI_SUCCESS; + if (HostBridge->ResourceSubmited) { + + List =3D HostBridge->RootBridges.ForwardLink; + while (List !=3D &HostBridge->RootBridges) { + + for (Index1 =3D TypeIo; Index1 < TypeBus; Index1++) { + ResNodeHandled[Index1] =3D FALSE; + } + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + Socket =3D Stack =3D (UINT8)-1; + PciRootBridge2SocketStack (RootBridge, &Socket, &Stack); + for (Index1 =3D TypeIo; Index1 < TypeBus; Index1++) { + + if (RootBridge->ResAllocNode[Index1].Status =3D=3D ResNone) { + + ResNodeHandled[Index1] =3D TRUE; + + } else { + // + // Allocate the resource node with max alignment at first + // + MaxAlignment =3D 0; + Index =3D TypeMax; + for (Index2 =3D TypeIo; Index2 < TypeBus; Index2++) { + + if (ResNodeHandled[Index2]) { + continue; + } + if (MaxAlignment <=3D RootBridge->ResAllocNode[Index2].Alignme= nt) { + MaxAlignment =3D RootBridge->ResAllocNode[Index2].Alignment; + Index =3D Index2; + } + } // for + + if (Index < TypeMax) { + + ResNodeHandled[Index] =3D TRUE; + Alignment =3D RootBridge->ResAllocNode[Index].Alignment; + // + // Get the number of '1' in Alignment. + // + for (BitsOfAlignment =3D 0; Alignment !=3D 0; BitsOfAlignment+= +) { + Alignment =3D RShiftU64 (Alignment, 1); + } + + AddrLen =3D RootBridge->ResAllocNode[Index].Length; + Alignment =3D RootBridge->ResAllocNode[Index].Alignment; + + DEBUG ((DEBUG_INFO, "\n[%d.%d] Resource Type to assign : %= s\n", Socket, Stack, mPciResourceTypeStr[Index])); + DEBUG ((DEBUG_INFO, " Length to allocate: %lx\n= ", RootBridge->ResAllocNode[Index].Length)); + DEBUG ((DEBUG_INFO, " Alignment: %lx\n= ", Alignment)); + DEBUG ((DEBUG_INFO, " Base Address: %lx\n= ", RootBridge->ResAllocNode[Index].Base)); + + switch (Index) { + case TypeIo: + if (RootBridge->Aperture.IoBase < RootBridge->Aperture.IoLim= it) { + // + // It is impossible for 0xFFFF Alignment for IO16 + // + if (BitsOfAlignment >=3D 16) { + Alignment =3D 0; + } + BaseAddress =3D RootBridge->Aperture.IoBase; + // + // Have to make sure Alignment is handled seeing we are do= ing direct address allocation + // + if ((BaseAddress & ~(Alignment)) !=3D BaseAddress) { + BaseAddress =3D ((BaseAddress + Alignment) & ~(Alignment= )); + } + + while((BaseAddress + AddrLen) <=3D RootBridge->Aperture.Io= Limit + 1) { + Status =3D gDS->AllocateIoSpace (EfiGcdAllocateAddress, = EfiGcdIoTypeIo, BitsOfAlignment, + AddrLen, &BaseAddress, mDriverImageHandle, NULL ); + + if (!EFI_ERROR (Status)) { + RootBridge->ResAllocNode[Index].Base =3D (UINT64) B= aseAddress; + RootBridge->ResAllocNode[Index].Status =3D ResAllocat= ed; + goto TypeIoFound; + } + + BaseAddress +=3D (Alignment + 1); + } // while + } // if + + TypeIoFound: + if (RootBridge->ResAllocNode[Index].Status !=3D ResAllocate= d) { + // + // No Room at the Inn for this resources request + // + ReturnStatus =3D EFI_OUT_OF_RESOURCES; + } // if + break; + + case TypeMem32: + if (RootBridge->Aperture.Mem32Base < RootBridge->Aperture.= Mem32Limit) { + + BaseAddress =3D RootBridge->Aperture.Mem32Base; + // + // Have to make sure Alignment is handled seeing we are = doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) !=3D BaseAddress) { + BaseAddress =3D ((BaseAddress + Alignment) & ~(Alignme= nt)); + } + + while ((BaseAddress + AddrLen) <=3D RootBridge->Aperture= .Mem32Limit + 1) { + DEBUG ((DEBUG_INFO, " Attempting %s allocation at= 0x%llX.....", + mPciResourceTypeStr[Index], BaseAddress)); + Status =3D gDS->AllocateMemorySpace (EfiGcdAllocateAdd= ress, EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, Ad= drLen, &BaseAddress, mDriverImageHandle, NULL); + if (!EFI_ERROR (Status)) { + RootBridge->ResAllocNode[Index].Base =3D (UINT64)= BaseAddress; + RootBridge->ResAllocNode[Index].Status =3D ResAlloc= ated; + DEBUG ((DEBUG_INFO, "Passed\n")); + goto TypeMem32Found; + } // if + DEBUG ((DEBUG_INFO, "Failed\n")); + BaseAddress +=3D (Alignment + 1); + } // while + } // if + + TypeMem32Found: + if (RootBridge->ResAllocNode[Index].Status !=3D ResAlloca= ted) { + // + // No Room at the Inn for this resources request + // + ReturnStatus =3D EFI_OUT_OF_RESOURCES; + } + break; + + case TypePMem32: + StartTypePMem32: + if (RootBridge->Aperture.Mem32Base < RootBridge->Aperture.= Mem32Limit) { + BaseAddress =3D RootBridge->Aperture.Mem32Limit + 1; + BaseAddress -=3D AddrLen; + + // + // Have to make sure Alignment is handled seeing we are = doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) !=3D BaseAddress) { + BaseAddress =3D ((BaseAddress) & ~(Alignment)); + } + + while (RootBridge->Aperture.Mem32Base <=3D BaseAddress) { + + DEBUG ((DEBUG_INFO, " Attempting %s allocation at= 0x%llX.....", + mPciResourceTypeStr[Index], BaseAddress)); + Status =3D gDS->AllocateMemorySpace (EfiGcdAllocateAdd= ress, EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, Ad= drLen, &BaseAddress, mDriverImageHandle, NULL); + if (!EFI_ERROR (Status)) { + RootBridge->ResAllocNode[Index].Base =3D (UINT64)= BaseAddress; + RootBridge->ResAllocNode[Index].Status =3D ResAlloc= ated; + DEBUG ((DEBUG_INFO, "Passed\n")); + goto TypePMem32Found; + } + DEBUG ((DEBUG_INFO, "Failed\n")); + BaseAddress -=3D (Alignment + 1); + } // while + } // if + + TypePMem32Found: + if (RootBridge->ResAllocNode[Index].Status !=3D ResAlloca= ted) { + // + // No Room at the Inn for this resources request + // + ReturnStatus =3D EFI_OUT_OF_RESOURCES; + } + break; + + case TypeMem64: + case TypePMem64: + if ((RootBridge->Aperture.Mem64Limit > RootBridge->Apertur= e.Mem64Base) && + (mIioUds->IioUdsPtr->PlatformData.Pci64BitResourceAllo= cation)) { + + if (RootBridge->Aperture.Mem64Limit < AddrLen) { + RootBridge->ResAllocNode[Index].Status =3D ResNone; + goto TypeMem64Found; + } + BaseAddress =3D RootBridge->Aperture.Mem64Limit + 1; + BaseAddress -=3D AddrLen; + + // + // Have to make sure Alignment is handled seeing we are = doing direct address allocation + // + if ((BaseAddress & ~(Alignment)) !=3D BaseAddress) { + BaseAddress =3D ((BaseAddress) & ~(Alignment)); + } + + while (RootBridge->Aperture.Mem64Base <=3D BaseAddress) { + + DEBUG ((DEBUG_INFO, " Attempting %s allocation at= 0x%llX.....", + mPciResourceTypeStr[Index], BaseAddress)); + Status =3D gDS->AllocateMemorySpace (EfiGcdAllocateAdd= ress, EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, Ad= drLen, &BaseAddress, mDriverImageHandle, NULL); + if (!EFI_ERROR (Status)) { + RootBridge->ResAllocNode[Index].Base =3D (UINT64)= BaseAddress; + RootBridge->ResAllocNode[Index].Status =3D ResAlloc= ated; + DEBUG ((DEBUG_INFO, "Passed\n")); + goto TypeMem64Found; + } + DEBUG ((DEBUG_INFO, "Failed\n")); + BaseAddress -=3D (Alignment + 1); + } // while + + TypeMem64Found: + if (RootBridge->ResAllocNode[Index].Status !=3D ResAlloc= ated) { + // + // No Room at the Inn for this resources request + // + ReturnStatus =3D EFI_OUT_OF_RESOURCES; + } + } else { + // + // If 64-bit resourcing is not available, and the reques= ted size is not greater than the Mem32Limit, then try as PMem32 + // + if (AddrLen >=3D RootBridge->Aperture.Mem32Limit + 1) { + + DEBUG((DEBUG_ERROR, " 64-bit resource length 0x%l= lX > Mem32Limit (0x%llX). Failed!!\n", AddrLen, RootBridge->Aperture.Mem32L= imit + 1)); + goto TypeMem64Found; // Let it handle out-of-resources= case, try MMIO rebalance + + } else { + + DEBUG((DEBUG_ERROR, " 64-bit resourcing not avail= able. Try as PMem32\n")); + goto StartTypePMem32; + } + } + break; + + default: + DEBUG ((EFI_D_ERROR, "[PCI] ERROR: Unhandled resource type= (%d)\n", Index)); + break; + } // End switch (Index) + + DEBUG ((DEBUG_INFO, "Resource Type Assigned: %s\n", mPciReso= urceTypeStr[Index])); + if (RootBridge->ResAllocNode[Index].Status =3D=3D ResAllocated= ) { + DEBUG ((DEBUG_INFO, " Base Address Assigned: %lx\n", RootBr= idge->ResAllocNode[Index].Base)); + DEBUG ((DEBUG_INFO, " Length Assigned: %lx\n", RootBr= idge->ResAllocNode[Index].Length)); + } else { + DEBUG ((DEBUG_ERROR, " Resource Allocation failed! There w= as no room at the inn\n")); + } + } else { + // + // Index >=3D TypeMax + // + ASSERT (FALSE); + } + } + } + List =3D List->ForwardLink; + } + + if (ReturnStatus =3D=3D EFI_OUT_OF_RESOURCES) { + + DEBUG ((DEBUG_ERROR, "[PCI] Resource allocation failed, rebalance re= source allocation and reboot\n")); + AdjustResourceAmongRootBridges (HostBridge, &RatioAdjustResult); + if (RatioAdjustResult =3D=3D SocketResourceRatioChanged) { + DEBUG ((DEBUG_WARN, "[PCI] WARNING: Resource allocation failed. Ad= justed the resource requests and resetting the system.\n")); + gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL); + + } else { + + DEBUG ((DEBUG_WARN, "[PCI] WARNING: Resource allocation failed, re= balance not possible, continue boot\n")); + } + } + + // + // Set resource to zero for nodes where allocation fails + // + List =3D HostBridge->RootBridges.ForwardLink; + while (List !=3D &HostBridge->RootBridges) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + for (Index =3D TypeIo; Index < TypeBus; Index++) { + if (RootBridge->ResAllocNode[Index].Status !=3D ResAllocated) { + RootBridge->ResAllocNode[Index].Length =3D 0; + } + } + List =3D List->ForwardLink; + } + return ReturnStatus; + } else { + return EFI_NOT_READY; + } + // + // HostBridge->CanRestarted =3D FALSE; + // +} + + +/** + Enter the EfiPciHostBridgeFreeResources phase of the + PCI(e) numeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @retval EFI_SUCCESS Things worked out + @retval other Failures as reported by functions leveraged +*/ +STATIC EFI_STATUS +BridgeFreeResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + PCI_RESOURCE_TYPE Index; + LIST_ENTRY *List; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 AddrLen; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + ReturnStatus =3D EFI_SUCCESS; + List =3D HostBridge->RootBridges.ForwardLink; + + while (List !=3D &HostBridge->RootBridges) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + for (Index =3D TypeIo; Index < TypeBus; Index++) { + if (RootBridge->ResAllocNode[Index].Status =3D=3D ResAllocated) { + AddrLen =3D RootBridge->ResAllocNode[Index].Length; + BaseAddress =3D (EFI_PHYSICAL_ADDRESS) RootBridge->ResAllocNode[In= dex].Base; + + switch (Index) { + case TypeIo: + Status =3D gDS->FreeIoSpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus =3D Status; + } + break; + + case TypeMem32: + Status =3D gDS->FreeMemorySpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus =3D Status; + } + break; + + case TypePMem32: + break; + + case TypeMem64: + break; + + case TypePMem64: + Status =3D gDS->FreeMemorySpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus =3D Status; + } + break; + + default: + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Invalid resource type %d\n", = Index)); + break; + } + + RootBridge->ResAllocNode[Index].Type =3D Index; + RootBridge->ResAllocNode[Index].Base =3D 0; + RootBridge->ResAllocNode[Index].Length =3D 0; + RootBridge->ResAllocNode[Index].Status =3D ResNone; + } + } + + List =3D List->ForwardLink; + } + + HostBridge->ResourceSubmited =3D FALSE; + HostBridge->CanRestarted =3D TRUE; + return ReturnStatus; +} + + +/** + Enter the EfiPciHostBridgeEndResourceAllocation phase of the + PCI(e) numeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @retval EFI_SUCCESS Things worked out +*/ +STATIC EFI_STATUS +PciHostBridgeEndResourceAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + + +/** + + Enter a certain phase of the PCI enumeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL insta= nce. + @param Phase The phase during enumeration. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER Wrong phase parameter passed in. + @retval EFI_NOT_READY Resources have not been submitted yet. + +**/ +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + + switch (Phase) { + case EfiPciHostBridgeBeginEnumeration: + return BeginBridgeEnumeration (This); + + case EfiPciHostBridgeEndEnumeration: + return EFI_SUCCESS; + + case EfiPciHostBridgeBeginBusAllocation: + // + // No specific action is required here, can perform any chipset specif= ic programing + // + HostBridge->CanRestarted =3D FALSE; + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // No specific action is required here, can perform any chipset specif= ic programing + // + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // No specific action is required here, can perform any chipset specif= ic programing + // + break; + + case EfiPciHostBridgeAllocateResources: + return BridgeAllocateResources (This); + + case EfiPciHostBridgeSetResources: + // + // HostBridgeInstance->CanRestarted =3D FALSE; + // + break; + + case EfiPciHostBridgeFreeResources: + return BridgeFreeResources (This); + + case EfiPciHostBridgeEndResourceAllocation: + return PciHostBridgeEndResourceAllocation (This); + + default: + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + + Return the device handle of the next PCI root bridge that is associated = with + this Host Bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle Returns the device handle of the next PCI Root = Bridge. + On input, it holds the RootBridgeHandle returne= d by the most + recent call to GetNextRootBridge().The handle f= or the first + PCI Root Bridge is returned if RootBridgeHandle= is NULL on input. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND Next PCI root bridge not found. + @retval EFI_INVALID_PARAMETER Wrong parameter passed in. + +**/ +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle + ) +{ + BOOLEAN NoRootBridge; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + NoRootBridge =3D TRUE; + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + + while (List !=3D &HostBridge->RootBridges) { + NoRootBridge =3D FALSE; + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (*RootBridgeHandle =3D=3D NULL) { + // + // Return the first Root Bridge Handle of the Host Bridge + // + *RootBridgeHandle =3D RootBridge->Handle; + return EFI_SUCCESS; + } else { + if (*RootBridgeHandle =3D=3D RootBridge->Handle) { + // + // Get next if have + // + List =3D List->ForwardLink; + if (List !=3D &HostBridge->RootBridges) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + *RootBridgeHandle =3D RootBridge->Handle; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } + } + } + + List =3D List->ForwardLink; + // + // end while + // + } + + if (NoRootBridge) { + return EFI_NOT_FOUND; + } else { + return EFI_INVALID_PARAMETER; + } +} + +/** + + Returns the attributes of a PCI Root Bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The device handle of the PCI Root Bridge + that the caller is interested in. + @param Attributes The pointer to attributes of the PCI Root Bridg= e. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER Attributes parameter passed in is NULL or + RootBridgeHandle is not an EFI_HANDLE + that was returned on a previous call to + GetNextRootBridge(). + +**/ +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ) +{ + LIST_ENTRY *Link; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Attributes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + for (Link =3D GetFirstNode (&HostBridge->RootBridges) + ; !IsNull (&HostBridge->RootBridges, Link) + ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) + ) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (Link); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + *Attributes =3D RootBridge->AllocationAttributes; + return EFI_SUCCESS; + } + } + + return EFI_INVALID_PARAMETER; +} + +/** + + This is the request from the PCI enumerator to set up + the specified PCI Root Bridge for bus enumeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The PCI Root Bridge to be set up. + @param Configuration Pointer to the pointer to the PCI bus resource = descriptor. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Not enough pool to be allocated. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + VOID *Buffer; + UINT8 *Temp; + EFI_STATUS Status; + UINTN BusStart; + UINTN BusEnd; + UINT64 BusReserve; + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + + while (List !=3D &HostBridge->RootBridges) { + + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + // + // Set up the Root Bridge for Bus Enumeration + // + BusStart =3D RootBridge->Aperture.BusBase; + BusEnd =3D RootBridge->Aperture.BusLimit; + BusReserve =3D RootBridge->Aperture.BusReserve; + // + // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR + // + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof = (EFI_ACPI_END_TAG_DESCRIPTOR), + &Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + Temp =3D (UINT8 *) Buffer; + + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Desc = =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Len = =3D 0x2B; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->ResType = =3D ACPI_ADDRESS_SPACE_TYPE_BUS; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->GenFlag = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->SpecificFlag = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrSpaceGranularity = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMin = =3D BusStart; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMax = =3D BusReserve; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrTranslationOffset = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrLen = =3D BusEnd - BusStart + 1; + + Temp =3D Temp + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc =3D ACPI_END_TAG_DESCRI= PTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum =3D 0x0; + + *Configuration =3D Buffer; + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + + This function programs the PCI Root Bridge hardware so that + it decodes the specified PCI bus range. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The PCI Root Bridge whose bus range is to be pr= ogrammed. + @param Configuration The pointer to the PCI bus resource descriptor. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER Wrong parameters passed in. + +**/ +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT8 *Ptr; + UINTN BusStart; + UINTN BusEnd; + UINTN BusLen; + + if (Configuration =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Ptr =3D Configuration; + + // + // Check the Configuration is valid + // + if (*Ptr !=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->ResType !=3D ACPI_ADDRE= SS_SPACE_TYPE_BUS) { + return EFI_INVALID_PARAMETER; + } + + Ptr +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + if (*Ptr !=3D ACPI_END_TAG_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + Ptr =3D Configuration; + + while (List !=3D &HostBridge->RootBridges) { + + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + BusStart =3D (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->A= ddrRangeMin; + BusLen =3D (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->A= ddrLen; + BusEnd =3D BusStart + BusLen - 1; + + if (BusStart > BusEnd) { + return EFI_INVALID_PARAMETER; + } + + if ((BusStart < RootBridge->Aperture.BusBase) || (BusEnd > RootBridg= e->Aperture.BusLimit)) { + return EFI_INVALID_PARAMETER; + } + // + // Update the Bus Range + // + RootBridge->ResAllocNode[TypeBus].Base =3D BusStart; + RootBridge->ResAllocNode[TypeBus].Length =3D BusLen + RootBridge->A= perture.BusReserve; + RootBridge->ResAllocNode[TypeBus].Status =3D ResAllocated; + RootBridge->BusScanCount++; + if (RootBridge->BusScanCount > 0) { + // + // Only care about the 2nd PCI bus scanning + // + RootBridge->BusNumberAssigned =3D TRUE; + } + + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + + +/** + + Submits the I/O and memory resource requirements for the specified PCI R= oot Bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The PCI Root Bridge whose I/O and memory resour= ce requirements. + are being submitted. + @param Configuration The pointer to the PCI I/O and PCI memory resou= rce descriptor. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER Wrong parameters passed in. +**/ +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr; + UINT64 AddrLen; + UINT64 Alignment; + UINT64 Value; + + // + // Check the input parameter: Configuration + // + if (Configuration =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + + Temp =3D (UINT8 *) Configuration; + while (List !=3D &HostBridge->RootBridges) { + + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + // + // Check the resource descriptors. + // If the Configuration includes one or more invalid resource descri= ptors, all the resource + // descriptors are ignored and the function returns EFI_INVALID_PARA= METER. + // + for (; *Temp =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Temp +=3D sizeof = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)) { + + ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + //DEBUG ((DEBUG_ERROR, " ptr->ResType:%x", ptr->ResType)); + //DEBUG ((DEBUG_ERROR, " ptr->AddrLen:0x%llX AddrRangeMin:0x%llX A= ddrRangeMax:0x%llX\n",ptr->AddrLen,ptr->AddrRangeMin,ptr->AddrRangeMax)); + // + // A zero-length resource request indicates the PCI root bridge do= esn't require + // any resources. Skip the check and proceed to the next descripto= r. + // + if (ptr->AddrLen =3D=3D 0) { + continue; + } + + switch (ptr->ResType) { + case ACPI_ADDRESS_SPACE_TYPE_MEM: + if (ptr->AddrSpaceGranularity !=3D 32 && ptr->AddrSpaceGranula= rity !=3D 64) { + + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Inavlid granularity %d fo= r resource type %d\n", + ptr->AddrSpaceGranularity, ptr->ResType)); + return EFI_INVALID_PARAMETER; + } + if (ptr->AddrSpaceGranularity =3D=3D 32 && ptr->AddrLen > 0xff= ffffff) { + + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Inavlid granularity %d fo= r resource type %d of size 0x%llX\n", + ptr->AddrSpaceGranularity, ptr->ResType, ptr->AddrLe= n)); + return EFI_INVALID_PARAMETER; + } + // + // If the PCI root bridge does not support separate windows fo= r nonprefetchable and + // prefetchable memory, then the PCI bus driver needs to inclu= de requests for + // prefetchable memory in the nonprefetchable memory pool. + // + if ((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_CO= MBINE_MEM_PMEM) !=3D 0 && + ((ptr->SpecificFlag & (BIT2 | BIT1)) !=3D 0)) { + return EFI_INVALID_PARAMETER; + } + case ACPI_ADDRESS_SPACE_TYPE_IO: + // + // Check alignment, it should be of the form 2^n-1 + // + Value =3D Power2MaxMemory (ptr->AddrRangeMax + 1); + if (Value !=3D (ptr->AddrRangeMax + 1)) { + CpuDeadLoop(); + return EFI_INVALID_PARAMETER; + } + break; + case ACPI_ADDRESS_SPACE_TYPE_BUS: + default: + return EFI_INVALID_PARAMETER; + } + } + if (*Temp !=3D ACPI_END_TAG_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + Temp =3D (UINT8 *) Configuration; + for (; *Temp =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Temp +=3D sizeof = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)) { + ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + + // + // If a PCI root bridge does not require any resources, a zero-len= gth resource + // request must be explicitly submitted. + // + if (ptr->AddrLen =3D=3D 0) { + HostBridge->ResourceSubmited =3D TRUE; + continue; + } + + switch (ptr->ResType) { + case ACPI_ADDRESS_SPACE_TYPE_MEM: + AddrLen =3D (UINT64) ptr->AddrLen; + Alignment =3D (UINT64) ptr->AddrRangeMax; + if (ptr->AddrSpaceGranularity =3D=3D 32) { + if (ptr->SpecificFlag =3D=3D 0x06) { + // + // Apply from GCD + // + RootBridge->ResAllocNode[TypePMem32].Status =3D ResSubmitted; + } else { + RootBridge->ResAllocNode[TypeMem32].Length =3D AddrLen; + RootBridge->ResAllocNode[TypeMem32].Alignment =3D Alignment; + RootBridge->ResAllocNode[TypeMem32].Status =3D ResRequest= ed; + HostBridge->ResourceSubmited =3D TRUE; + } + } + + if (ptr->AddrSpaceGranularity =3D=3D 64) { + if (ptr->SpecificFlag =3D=3D 0x06) { + RootBridge->ResAllocNode[TypePMem64].Status =3D ResSubmitted; + } else { + RootBridge->ResAllocNode[TypeMem64].Length =3D AddrLen; + RootBridge->ResAllocNode[TypeMem64].Alignment =3D Alignment; + RootBridge->ResAllocNode[TypeMem64].Status =3D ResSubmitt= ed; + HostBridge->ResourceSubmited =3D TRUE; + } + } + break; + + case ACPI_ADDRESS_SPACE_TYPE_IO: + AddrLen =3D (UINT64) ptr->AddrLen; + Alignment =3D (UINT64) ptr->AddrRangeMax; + RootBridge->ResAllocNode[TypeIo].Length =3D AddrLen; + RootBridge->ResAllocNode[TypeIo].Alignment =3D Alignment; + RootBridge->ResAllocNode[TypeIo].Status =3D ResRequested; + HostBridge->ResourceSubmited =3D TRUE; + break; + + default: + break; + } + } + + return EFI_SUCCESS; + } + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + + This function returns the proposed resource settings for the specified + PCI Root Bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The PCI Root Bridge handle. + @param Configuration The pointer to the pointer to the PCI I/O + and memory resource descriptor. + + @retval EFI_SUCCESS Succeed. + @retval EFI_OUT_OF_RESOURCES Not enough pool to be allocated. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINTN Index; + UINTN Number; + VOID *Buffer; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr; + EFI_STATUS Status; + UINT64 ResStatus; + + Buffer =3D NULL; + Number =3D 0; + // + // Get the Host Bridge Instance from the resource allocation protocol + // + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + + // + // Enumerate the root bridges in this Host bridge + // + while (List !=3D &HostBridge->RootBridges) { + + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + for (Index =3D 0; Index < TypeBus; Index++) { + if (RootBridge->ResAllocNode[Index].Status !=3D ResNone) { + Number++; + } + } + + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + Number * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) = + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), + &Buffer + ); + + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (Buffer, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Number= + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + + Temp =3D Buffer; + for (Index =3D 0; Index < TypeBus; Index++) { + if (RootBridge->ResAllocNode[Index].Status !=3D ResNone) { + ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp; + ResStatus =3D RootBridge->ResAllocNode[Index].Status; + + switch (Index) { + + case TypeIo: + // + // Io + // + ptr->Desc =3D 0x8A; + ptr->Len =3D 0x2B; + ptr->ResType =3D 1; + ptr->GenFlag =3D 0; + ptr->SpecificFlag =3D 0; + ptr->AddrRangeMin =3D RootBridge->ResAllocNode[Index= ].Base; + ptr->AddrRangeMax =3D 0; + ptr->AddrTranslationOffset =3D (ResStatus =3D=3D ResAllocated= ) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen =3D RootBridge->ResAllocNode[Index= ].Length; + break; + + case TypeMem32: + // + // Memory 32 + // + ptr->Desc =3D 0x8A; + ptr->Len =3D 0x2B; + ptr->ResType =3D 0; + ptr->GenFlag =3D 0; + ptr->SpecificFlag =3D 0; + ptr->AddrSpaceGranularity =3D 32; + ptr->AddrRangeMin =3D RootBridge->ResAllocNode[Index= ].Base; + ptr->AddrRangeMax =3D 0; + ptr->AddrTranslationOffset =3D (ResStatus =3D=3D ResAllocated= ) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen =3D RootBridge->ResAllocNode[Index= ].Length; + break; + + case TypePMem32: + // + // Prefetch memory 32 + // + ptr->Desc =3D 0x8A; + ptr->Len =3D 0x2B; + ptr->ResType =3D 0; + ptr->GenFlag =3D 0; + ptr->SpecificFlag =3D 6; + ptr->AddrSpaceGranularity =3D 32; + ptr->AddrRangeMin =3D 0; + ptr->AddrRangeMax =3D 0; + ptr->AddrTranslationOffset =3D EFI_RESOURCE_NONEXISTENT; + ptr->AddrLen =3D 0; + break; + + case TypeMem64: + // + // Memory 64 + // + ptr->Desc =3D 0x8A; + ptr->Len =3D 0x2B; + ptr->ResType =3D 0; + ptr->GenFlag =3D 0; + ptr->SpecificFlag =3D 0; + ptr->AddrSpaceGranularity =3D 64; + ptr->AddrRangeMin =3D RootBridge->ResAllocNode[Index= ].Base; + ptr->AddrRangeMax =3D 0; + ptr->AddrTranslationOffset =3D (ResStatus =3D=3D ResAllocated= ) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; + ptr->AddrLen =3D RootBridge->ResAllocNode[Index= ].Length; + break; + + case TypePMem64: + // + // Prefetch memory 64 + // + ptr->Desc =3D 0x8A; + ptr->Len =3D 0x2B; + ptr->ResType =3D 0; + ptr->GenFlag =3D 0; + ptr->SpecificFlag =3D 6; + ptr->AddrSpaceGranularity =3D 64; + ptr->AddrRangeMin =3D 0; + ptr->AddrRangeMax =3D 0; + ptr->AddrTranslationOffset =3D EFI_RESOURCE_NONEXISTENT; + ptr->AddrLen =3D 0; + break; + default: + DEBUG ((EFI_D_INFO, "default case.\n")); //Auto added. Plea= se review. + break; + } + + Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + } + + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc =3D 0x79; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum =3D 0x0; + + *Configuration =3D Buffer; + + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle The PCI Root Bridge handle. + @param PciAddress Address of the controller on the PCI bus. + @param Phase The Phase during resource allocation. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridge= Handle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + BOOLEAN RootBridgeFound; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (RootBridgeHandle =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + RootBridgeFound =3D FALSE; + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS (This); + List =3D HostBridge->RootBridges.ForwardLink; + + while (List !=3D &HostBridge->RootBridges) { + + RootBridge =3D ROOT_BRIDGE_FROM_LINK (List); + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + RootBridgeFound =3D TRUE; + break; + } + // + // Get next if have + // + List =3D List->ForwardLink; + } + + if (RootBridgeFound =3D=3D FALSE) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + + Calculate maximum memory length that can be fit to a mtrr. + + @param MemoryLength - Input memory length. + + @retval Returned Maximum length. + +**/ +UINT64 +Power2MaxMemory ( + IN UINT64 MemoryLength + ) +{ + UINT64 Result; + + if (RShiftU64 (MemoryLength, 32)) { + Result =3D LShiftU64 ((UINT64) GetPowerOfTwo64 ((UINT32) RShiftU64 (Me= moryLength, 32)), 32); + } else { + Result =3D (UINT64) GetPowerOfTwo64 ((UINT32) MemoryLength); + } + + return Result; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciHostBridge.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/P= ciHostBridge/PciHostBridge.h new file mode 100644 index 0000000000..4c1b757952 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= HostBridge.h @@ -0,0 +1,300 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_HOST_BRIDGE_H_ +#define _PCI_HOST_BRIDGE_H_ + + +#include +#include +#include +#include +#include +#include +#include + +#include "PciRootBridge.h" + +#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('p', 'h', 'b', 'g') +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + UINTN RootBridgeCount; + LIST_ENTRY RootBridges; + BOOLEAN ResourceSubmited; + BOOLEAN CanRestarted; + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; +} PCI_HOST_BRIDGE_INSTANCE; + +#define PCI_HOST_BRIDGE_FROM_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResA= lloc, PCI_HOST_BRIDGE_SIGNATURE) + +// +// Driver Entry Point +// +/** + + Entry point of this driver. + + @param ImageHandle - Image handle of this driver. + @param SystemTable - Pointer to standard EFI system table. + + @retval EFI_SUCCESS - Succeed. + @retval EFI_DEVICE_ERROR - Fail to install PCI_ROOT_BRIDGE_IO protocol. + +**/ +EFI_STATUS +EFIAPI +InitializePciHostBridge ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +// +// HostBridge Resource Allocation interface +// +/** + + Enter a certain phase of the PCI enumeration process. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL insta= nce. + @param Phase The phase during enumeration. + + @retval EFI_SUCCESS Succeed. + @retval EFI_INVALID_PARAMETER Wrong phase parameter passed in. + @retval EFI_NOT_READY Resources have not been submitted yet. + +**/ +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ); + +/** + + Return the device handle of the next PCI root bridge that is associated = with + this Host Bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PR= OTOCOL instance. + @param RootBridgeHandle Returns the device handle of the next PCI Root = Bridge. + On input, it holds the RootBridgeHandle returne= d by the most + recent call to GetNextRootBridge().The handle f= or the first + PCI Root Bridge is returned if RootBridgeHandle= is NULL on input. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND Next PCI root bridge not found. + @retval EFI_INVALID_PARAMETER Wrong parameter passed in. + +**/ +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle + ); + +/** + + Returns the attributes of a PCI Root Bridge. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance + @param RootBridgeHandle - The device handle of the PCI Root Bridge + that the caller is interested in + @param Attributes - The pointer to attributes of the PCI Root Br= idge + + @retval EFI_SUCCESS - Succeed. + @retval EFI_INVALID_PARAMETER - Attributes parameter passed in is NULL= or + @retval RootBridgeHandle is not an EFI_HANDLE + @retval that was returned on a previous call to + @retval GetNextRootBridge(). + +**/ +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ); + +/** + + This is the request from the PCI enumerator to set up + the specified PCI Root Bridge for bus enumeration process. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance. + @param RootBridgeHandle - The PCI Root Bridge to be set up. + @param Configuration - Pointer to the pointer to the PCI bus resour= ce descriptor. + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + @retval EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + + This function programs the PCI Root Bridge hardware so that + it decodes the specified PCI bus range. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance. + @param RootBridgeHandle - The PCI Root Bridge whose bus range is to be= programmed. + @param Configuration - The pointer to the PCI bus resource descript= or. + + @retval EFI_SUCCESS - Succeed. + @retval EFI_INVALID_PARAMETER - Wrong parameters passed in. + +**/ +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + + Submits the I/O and memory resource requirements for the specified PCI R= oot Bridge. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance + @param RootBridgeHandle - The PCI Root Bridge whose I/O and memory res= ource requirements + are being submitted + @param Configuration - The pointer to the PCI I/O and PCI memory re= source descriptor + + @retval EFI_SUCCESS - Succeed. + @retval EFI_INVALID_PARAMETER - Wrong parameters passed in. + +**/ +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + + This function returns the proposed resource settings for the specified + PCI Root Bridge. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance. + @param RootBridgeHandle - The PCI Root Bridge handle. + @param Configuration - The pointer to the pointer to the PCI I/O + and memory resource descriptor. + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough pool to be allocated. + @retval EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + + @param This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL instance. + @param RootBridgeHandle - The PCI Root Bridge handle. + @param PciAddress - Address of the controller on the PCI bus. + @param Phase - The Phase during resource allocation. + + @retval EFI_SUCCESS - Succeed. + @retval EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle. + +**/ +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeH= andle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ); + +// +// Host Bridge Silicon specific hooks +// +/** + + Returns the Allocation attributes for the BNB Root Bridge. + + @param RootBridgeIndex - The root bridge number. 0 based. + + @retval EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64= _DECODE + +**/ +UINT64 +GetAllocAttributes ( + IN UINTN RootBridgeIndex + ) +; + +/** + + Returns memory apertures for the BNB Root Bridge. + + @param PciRootBridgeIo - Pointer to Efi Pci root bridge Io protocol in= terface instance. + @param Mem32Base - Pointer to 32 bit memory base. This is the lo= west 32 bit memory address + that is decoded by the Host Bridge. + @param Mem32Limit - Pointer to 32 bit memory limit.This is the hi= ghest 32 bit memory address + that is decoded by the Host Bridge. The size = of the 32 bit window is + (Mem32Limit - Mem32base + 1). + @param Mem64Base - Pointer to 64 bit memory base. This is the lo= west 64 bit memory address + that is decoded by the Host Bridge. + @param Mem64Limit - Pointer to 64 bit memory limit.This is the hi= ghest 64 bit memory address + that is decoded by the Host Bridge. The size = of the 64 bit window is + (Mem64Limit - Mem64base + 1). Set Mem64Limit = < Mem64Base if the Host bridge + does not support 64 bit memory addresses. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +GetHostBridgeMemApertures ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + OUT UINT32 *Mem32Base, + OUT UINT32 *Mem32Limit, + OUT UINT64 *Mem64Base, + OUT UINT64 *Mem64Limit + ); + +/** + + Calculate maximum memory length that can be fit to a mtrr. + + @param MemoryLength - Input memory length. + + @retval Returned Maximum length. + +**/ +UINT64 +Power2MaxMemory ( + IN UINT64 MemoryLength + ); + +extern EDKII_IOMMU_PROTOCOL *mIoMmu; + +#endif // _PCI_HOST_BRIDGE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciHostBridge.inf b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe= /PciHostBridge/PciHostBridge.inf new file mode 100644 index 0000000000..faea9726f7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= HostBridge.inf @@ -0,0 +1,69 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciHostBridge + FILE_GUID =3D D58EBCE1-AF26-488d-BE66-C164417F8C13 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePciHostBridge + +[Sources] + PciHostBridge.h + PciRootBridge.h + PciHostBridge.c + PciRootBridgeIo.c + PciHostBridgeSupport.c + PciHostResource.h + PciRebalance.c + PciRebalanceIo.c + PciRebalanceMmio32.c + PciRebalanceMmio64.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + DxeServicesTableLib + DevicePathLib + BaseMemoryLib + BaseLib + UefiLib + TimerLib + SetupLib + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + gEfiDevicePathProtocolGuid ## BY_START + gEfiPciRootBridgeIoProtocolGuid ## BY_START + gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START + gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES + gEfiIioUdsProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Guids] + gEfiSocketPciResourceDataGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gEfiCpuIo2ProtocolGuid AND + gEfiIioUdsProtocolGuid AND + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciHostBridgeSupport.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pc= i/Dxe/PciHostBridge/PciHostBridgeSupport.c new file mode 100644 index 0000000000..fe3f274f1f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= HostBridgeSupport.c @@ -0,0 +1,127 @@ +/** @file + Do platform initialization for PCI bridge. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PciHostBridge.h" + +// +// The default latency for controllers +// +#define DEFAULT_PCI_LATENCY 0x20 + + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo; + +/** + + This function is called for all the PCI controllers that the PCI + bus driver finds. Can be used to Preprogram the controller. + + @param This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ = PROTOCOL instance + @param RootBridgeHandle -- The PCI Root Bridge handle + @param PciBusAddress -- Address of the controller on the PCI bus + @param Phase -- The Phase during resource allocation + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +ChipsetPreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridge= Handle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + + EFI_STATUS Status; + UINT8 Latency; + UINT8 CacheLineSize; + + if (mPciRootBridgeIo =3D=3D NULL) { + // + // Get root bridge in the system. + // + Status =3D gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIo= ProtocolGuid, &mPciRootBridgeIo); + ASSERT_EFI_ERROR (Status); + } + + if (Phase =3D=3D EfiPciBeforeResourceCollection) { + // + // Program the latency register, CLS register + // + PciAddress.Register =3D PCI_LATENCY_TIMER_OFFSET; + mPciRootBridgeIo->Pci.Read ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &Latency + ); + + // + // PCI-x cards come up with a default latency of 0x40. Don't touch the= m. + // + if (Latency =3D=3D 0) { + Latency =3D DEFAULT_PCI_LATENCY; + mPciRootBridgeIo->Pci.Write ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &Latency + ); + } + // + // Program Cache Line Size as 64bytes + // 16 of DWORDs =3D 64bytes (0x10) + // + PciAddress.Register =3D PCI_CACHELINE_SIZE_OFFSET; + CacheLineSize =3D 0x10; + mPciRootBridgeIo->Pci.Write ( + mPciRootBridgeIo, + EfiPciWidthUint8, + *((UINT64 *) &PciAddress), + 1, + &CacheLineSize + ); + + } + + return EFI_SUCCESS; +} + +/** + + Returns the Allocation attributes for the BNB Root Bridge. + + @param RootBridgeIndex - The root bridge number. 0 based. + + @retval EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64= _DECODE + +**/ +UINT64 +GetAllocAttributes ( + IN UINTN RootBridgeIndex + ) +{ + // + // Cannot have more than one Root bridge + // + //ASSERT (RootBridgeIndex =3D=3D 0); + + // + // PCI Root Bridge does not support separate windows for Non-prefetchable + // and Prefetchable memory. A PCI bus driver needs to include requests f= or + // Prefetchable memory in the Non-prefetchable memory pool. + // Further TNB does not support 64 bit memory apertures for PCI. BNB + // can only have system memory above 4 GB, + // + + return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM6= 4_DECODE; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciHostResource.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe= /PciHostBridge/PciHostResource.h new file mode 100644 index 0000000000..dd95e9773f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= HostResource.h @@ -0,0 +1,62 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_HOST_RESOURCE_H_ +#define _PCI_HOST_RESOURCE_H_ + +#include +#include + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFF +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFE + +typedef struct { + UINTN BusBase; + UINTN BusLimit; + UINTN BusReserve; + + UINT32 Mem32Base; + UINT32 Mem32Limit; + + UINT64 Mem64Base; + UINT64 Mem64Limit; + + UINTN IoBase; + UINTN IoLimit; +} PCI_ROOT_BRIDGE_RESOURCE_APERTURE; + +typedef enum { + TypeIo =3D 0, + TypeMem32, + TypePMem32, + TypeMem64, + TypePMem64, + TypeBus, + TypeMax +} PCI_RESOURCE_TYPE; + +typedef enum { + ResNone, + ResSubmitted, + ResRequested, + ResAllocated, + ResStatusMax +} RES_STATUS; + +typedef struct { + PCI_RESOURCE_TYPE Type; + // + // Base is a host address + // + UINT64 Base; + UINT64 Length; + UINT64 Alignment; + RES_STATUS Status; +} PCI_RES_NODE; + +#endif // _PCI_HOST_RESOURCE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalance.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pc= iHostBridge/PciRebalance.c new file mode 100644 index 0000000000..b32f0bf835 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= Rebalance.c @@ -0,0 +1,1356 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "PciHostBridge.h" +#include "PciRootBridge.h" +#include +#include +#include + +#include "PciRebalance.h" + + +/*************************************************************************= ***** + * Local definitions. + *************************************************************************= *****/ +extern CHAR16 *mAcpiAddressSpaceTypeStr[]; +extern CHAR16 *mPciResourceTypeStr[]; + +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + +/*************************************************************************= ***** + * Variables. + *************************************************************************= *****/ +/** + * The table below is a cache with pointers to protocol instances created = at + * Host Bridge initialization. It also provides mapping of protocol instan= ce + * to the PCI stack. + */ +PCI_ROOT_BRIDGE_INSTANCE *mPciRootBridgeTable[MAX_SOCKET][MAX_LOGIC_IIO_ST= ACK] =3D {0}; +PCI_ROOT_BRIDGE_INSTANCE *mPciRootBridgeTableReserved[MAX_SOCKET][IIO_RESE= RVED_1] =3D {0}; + + +/*************************************************************************= ***** + * Functions. + *************************************************************************= *****/ + +/** + Find socket and stack index for given PCI Root Bridge protocol pointer. + + @param[out] PciResConfigPtr - Buffer for the resource configuration varia= ble. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to= a hardware error. + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to= an authentication failure. +**/ +EFI_STATUS +PciRootBridge2SocketStack ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridgePtr, + OUT UINT8 *SocketPtr, + OUT UINT8 *StackPtr + ) +{ + UINT8 Socket; + UINT8 Stack; + + if (RootBridgePtr !=3D NULL) { + + for (Socket =3D 0; Socket < NELEMENTS(mPciRootBridgeTable); Socket++) { + + for (Stack =3D 0; Stack < NELEMENTS(mPciRootBridgeTable[Socket]); St= ack++) { + + if (mPciRootBridgeTable[Socket][Stack] =3D=3D RootBridgePtr) { + if (SocketPtr !=3D NULL) { + *SocketPtr =3D Socket; + } + if (StackPtr !=3D NULL) { + *StackPtr =3D Stack; + } + return EFI_SUCCESS; + } + } + } + } + return EFI_NOT_FOUND; +} + +/** + Determine the last stack for a given socket + + @param Socket the socket for which the last socket is desired + + @return the number of the last socket +*/ +UINT8 +LastStackOfSocket ( + UINT8 Socket + ) +{ + UINT8 LastStack; + BOOLEAN FoundEnabledStack; + UINT8 Stack; + + ASSERT (Socket < ARRAY_SIZE(mIioUds->IioUdsPtr->PlatformData.IIO_resourc= e)); + ASSERT (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid); + + FoundEnabledStack =3D FALSE; + LastStack =3D 0; + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBi= tmap & (1 << Stack)) { + LastStack =3D Stack; + FoundEnabledStack =3D TRUE; + } + } + + ASSERT (FoundEnabledStack); + return LastStack; +} + + +/** + Determine the last stack for a given socket with resources + + @param SocketResources - CPU_RESOURCE structure pointer that stores al= l resources need per stack + @param Socket - Index of the Socket + @param ResourceType - Type of resource that requires alignment + @param LastStack - Pointer that will store the value of the last= stack with resources allocated to it + @param ResourceSize - Pointer that will store the sum of the reques= ted resource type + + @return The last stack with resources allocated to it and the + total amount of resoures requested of the type + requested. +*/ +VOID +LastStackWithResources ( + IN CPU_RESOURCE *SocketResources, + IN UINT8 Socket, + IN PCI_RESOURCE_TYPE ResourceType, + OUT UINT8 *LastStack, + OUT UINT64 *ResourceSize + ) +{ + UINT8 Stack; + + *LastStack =3D 0; + *ResourceSize =3D 0; + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresent= Bitmap & (1 << Stack))) { + continue; + } + + switch (ResourceType) { + case TypeIo: + if (SocketResources->StackRes[Stack].NumIoPortsDesired !=3D 0) { + *ResourceSize +=3D SocketResources->StackRes[Stack].NumIoPortsDe= sired + 1; + *LastStack =3D Stack; + } + break; + case TypeMem32: + if (SocketResources->StackRes[Stack].MmiolLength !=3D 0) { + *ResourceSize +=3D SocketResources->StackRes[Stack].MmiolLength = + 1; + *LastStack =3D Stack; + } + break; + case TypeMem64: + if (SocketResources->StackRes[Stack].MmiohLength !=3D 0) { + *ResourceSize +=3D SocketResources->StackRes[Stack].MmiohLength = + 1; + *LastStack =3D Stack; + } + break; + default: + break; + } + } +} + + +/** + Visit all stacks in this socket and recalculate the resource ranges per = stack based on resource + needs from PCI/PCIe device/functions. + + @param SocketResources - CPU_RESOURCE structure pointer that stores a= ll resources need per stack + @param Socket - Index of the Socket + @param ResourceType - type of resource that requires alignment + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to be adjusted wi= thin the socket. +**/ +EFI_STATUS +AdjustResources ( + CPU_RESOURCE *SocketResources, + UINT8 Socket, + UINT8 ResourceType + ) +{ + UINT8 Stack; + UINT64 NewLength; + CONST UINT8 LastStack =3D LastStackOfSocket (Socket); + UINT64 PreviousLimit; + BOOLEAN FirstStack =3D TRUE; + + switch (ResourceType) { + case TypeIo: + // Return if IoResourceNeeds is not zero which indicates a socket ad= justment is needed + if(SocketResources->IoResourceNeeds !=3D 0){ + return EFI_OUT_OF_RESOURCES; + } + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))){ + continue; + } + // + // For the first enabled stack, use the base I/O address for the s= ocket, otherwise + // calculate the new base based off the last enabled stack + // + if (FirstStack) { + // stackPresentBitmap doesn't cover if a valid stack was disable= due to resource adjustments. + // Start with valid resources for current socket + SocketResources->StackRes[Stack].IoBase =3D mIioUds->IioUdsPtr->= PlatformData.IIO_resource[Socket].PciResourceIoBase; + FirstStack =3D FALSE; + } else { + // Check to see if the previous stack is disabled by checking fo= r equal base and limit + if (SocketResources->StackRes[Stack-1].IoBase =3D=3D SocketResou= rces->StackRes[Stack-1].IoLimit) { + if (PreviousLimit % 2 =3D=3D 1) { + PreviousLimit +=3D 1; + } + SocketResources->StackRes[Stack].IoBase =3D (UINT16) PreviousL= imit; + } else { + SocketResources->StackRes[Stack].IoBase =3D (UINT16) PreviousL= imit + 1; + } + } + + NewLength =3D SocketResources->StackRes[Stack].NumIoPortsDesired; + + // + //assign the left space to the last IIO stack. Reserved for across= socket resource adjustment. + //make adjustments if NewLength is zero + // + if (Stack =3D=3D LastStack) { + if (NewLength !=3D 0) { + if (SocketResources->IoResourcesLeft !=3D 0) { + NewLength +=3D SocketResources->IoResourcesLeft + 1; + } + } else { + NewLength =3D SocketResources->IoResourcesLeft; + } + } + + SocketResources->StackRes[Stack].NeedIoUpdate =3D TRUE; + SocketResources->StackRes[Stack].IoLimit =3D (UINT16)(SocketResour= ces->StackRes[Stack].IoBase + NewLength); + PreviousLimit =3D SocketResources->StackRes[Stack].IoLimit; + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].IoBase =3D%x = newLength =3D %x\n",Socket,Stack,SocketResources->StackRes[Stack].IoBase,= NewLength)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].IoLimit =3D%x= \n",Socket,Stack,SocketResources->StackRes[Stack].IoLimit)); + } + break; + + case TypeMem32: + // + // Return if MmiolResourceNeeds is not zero which indicates a socket= adjustment is needed + // + if (SocketResources->MmiolResourceNeeds !=3D 0) { + return EFI_OUT_OF_RESOURCES; + } + // + // Visit all Stacks in this Socket and recalculate the New Mem32 R= anges per Stack + // + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++){ + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackP= resentBitmap & (1 << Stack))) { + continue; + } + // + // For the first enabled stack, use the base low mmio address fo= r the socket, otherwize + // calculate the new base based off the last enabled stack + // + if (FirstStack) { + // stackPresentBitmap doesn't cover if a valid stack was disab= le due to resource adjustments. + // Start with valid resources for current socket + SocketResources->StackRes[Stack].MmiolBase =3D mIioUds->IioUds= Ptr->PlatformData.IIO_resource[Socket].Mmio32Base; + FirstStack =3D FALSE; + } else { + // Check to see if the previous stack is disabled by checking = for equal base and limit + if (SocketResources->StackRes[Stack-1].MmiolBase =3D=3D Socket= Resources->StackRes[Stack-1].MmiolLimit) { + if (PreviousLimit % 2 =3D=3D 1) { + PreviousLimit +=3D 1; + } + SocketResources->StackRes[Stack].MmiolBase =3D (UINT32) Prev= iousLimit; + } else { + SocketResources->StackRes[Stack].MmiolBase =3D (UINT32) Prev= iousLimit + 1; + } + } + // + // Verify if this Stack is the one that requires an update and c= alculate the new Limit + // otherwise assign the new limit based on the Chunk and Extra C= hunk calculation and assign the Newlength + // + NewLength =3D SocketResources->StackRes[Stack].MmiolLength; + // + //assign the left space to the last IIO stack. Reserved for acro= ss socket resource adjustment. + //make adjustments if NewLength is zero + // + if (Stack =3D=3D LastStack) { + if (NewLength !=3D 0) { + if (SocketResources->MmiolResourcesLeft){ + NewLength +=3D SocketResources->MmiolResourcesLeft + 1; + } + } else { + NewLength =3D SocketResources->MmiolResourcesLeft; + } + } + + SocketResources->StackRes[Stack].MmiolUpdate =3D 1; + SocketResources->StackRes[Stack].MmiolLimit =3D (UINT32)(Socket= Resources->StackRes[Stack].MmiolBase + NewLength); + PreviousLimit =3D SocketResources->StackRes[Stack].MmiolLimit; + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiolBase = =3D%x newLength =3D %x\n",Socket,Stack,SocketResources->StackRes[Stack].M= miolBase,NewLength)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiolLimit = =3D%x\n",Socket,Stack,SocketResources->StackRes[Stack].MmiolLimit)); + } + break; + + case TypeMem64: + // Return if MmiohResourceNeeds is not zero which indicates a socket= adjustment is needed + if (SocketResources->MmiohResourceNeeds !=3D 0){ + return EFI_OUT_OF_RESOURCES; + } + // + // Visit all Stacks in this Socket and recalculate the New Mem64 Ran= ges per Stack + // + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + + if(!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPres= entBitmap & (1 << Stack))){ + continue; + } + // + // For the first enabled stack, use the base high mmio address for= the socket, otherwise + // calculate the new base based off the last enabled stack + // + if (FirstStack) { + // stackPresentBitmap doesn't cover if a valid stack was disable= due to resource adjustments. + // Start with valid resources for current socket + SocketResources->StackRes[Stack].MmiohBase =3D mIioUds->IioUdsPt= r->PlatformData.IIO_resource[Socket].Mmio64Base; + FirstStack =3D FALSE; + } else { + // Check to see if the previous stack is disabled by checking f= or equal base and limit + if (SocketResources->StackRes[Stack-1].MmiohBase =3D=3D SocketRe= sources->StackRes[Stack-1].MmiohLimit) { + if (PreviousLimit % 2 =3D=3D 1) { + PreviousLimit +=3D 1; + } + SocketResources->StackRes[Stack].MmiohBase =3D PreviousLimit; + } else { + SocketResources->StackRes[Stack].MmiohBase =3D PreviousLimit += 1; + } + } + + // + // Verify if this Stack is the one that requires an update and cal= culate the new Limit + // otherwise assign the new limit based on the Chunk and Extra Chu= nk calculation and assign the Newlength + // + + NewLength =3D SocketResources->StackRes[Stack].MmiohLength; + + // + //assign the left space to the last IIO stack. Reserved for across= socket resource adjustment. + //make adjustments if NewLength is zero + // + if (Stack =3D=3D LastStack) { + if (NewLength !=3D 0) { + if (SocketResources->MmiohResourcesLeft) { + NewLength +=3D SocketResources->MmiohResourcesLeft + 1; + } + } else { + NewLength =3D SocketResources->MmiohResourcesLeft; + } + } + + SocketResources->StackRes[Stack].MmiohUpdate =3D 1; + SocketResources->StackRes[Stack].MmiohLimit =3D (SocketResources-= >StackRes[Stack].MmiohBase + NewLength); + PreviousLimit =3D SocketResources->StackRes[Stack].MmiohLimit; + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiohBase =3D= %lx newLength =3D %lx\n",Socket,Stack,SocketResources->StackRes[Stack].Mm= iohBase,NewLength)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiohLimit = =3D%lx\n",Socket,Stack,SocketResources->StackRes[Stack].MmiohLimit)); + + } // for Stack + break; + default: + DEBUG((DEBUG_ERROR, "[PCI] ERROR: Resource Type Unknown =3D %x\n",= ResourceType)); + break; + }// switch + + return EFI_SUCCESS; +} + + +/** + Adjust resource ratio assignment among sockets to fit the resource needs= from PCI devices. + + @param SocketResources - CPU_RESOURCE structure pointer that stores a= ll resources need per socket + @param ResourceType - type of resource that requires alignment + @param ValidSockets - Number of Valid Sockets, need it to calcula= te how resources need to be splitted + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to be adjusted wi= thin the socket. +**/ +EFI_STATUS +AdjustSocketResources ( + CPU_RESOURCE *SocketResources, + UINT8 ResourceType, + UINT8 ValidSockets + ) +{ + EFI_STATUS Status; + + switch(ResourceType){ + case TypeIo: + Status =3D AdjustSocketIo (SocketResources, ResourceType, ValidSocke= ts); + break; + case TypeMem32: + Status =3D AdjustSocketMmioL (SocketResources, ResourceType, ValidSo= ckets); + break; + case TypeMem64: + Status =3D AdjustSocketMmioH (SocketResources, ResourceType, ValidSo= ckets); + break; + default: + DEBUG((DEBUG_ERROR, "ERROR: Resource Type Unknown =3D %x\n",Resource= Type)); + Status =3D EFI_INVALID_PARAMETER; + break; + } // switch + + return Status; +} + + +/** + Calculate current system resource map with retrieved NVRAM variable to s= ee if stored settings were applied + + @param[in] SocketPciResourceData - Pointer to stored CPU resource map + + @retval TRUE - SYSTEM_PCI_BASE_LIMITS has been rejected and was not ap= plied or not initialized + @retval FALSE - SYSTEM_PCI_BASE_LIMITS has been applied and still has r= elevant data +**/ +BOOLEAN +IsResourceMapRejected ( + SYSTEM_PCI_BASE_LIMITS *SocketPciResourceData + ) +{ + UINT8 Socket; + UINT8 Stack; + BOOLEAN Rejected =3D FALSE; + PCI_BASE_LIMITS *StackLimits; + PCI_BASE_LIMITS *UboxStackLimits; + PCI_BASE_LIMITS *SocketLimits; + STACK_RES *IioUdsUboxStackLimits; + STACK_RES *IioUdsStackLimits; + IIO_RESOURCE_INSTANCE *IioUdsSocketLimits; + + if (SocketPciResourceData =3D=3D NULL) { + return TRUE; + } + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + + IioUdsSocketLimits =3D &mIioUds->IioUdsPtr->PlatformData.IIO_resourc= e[Socket]; + SocketLimits =3D &SocketPciResourceData->Socket[Socket].SocketLimits; + IioUdsUboxStackLimits =3D &mIioUds->IioUdsPtr->PlatformData.IIO_reso= urce[Socket].StackRes[UBOX_STACK]; + UboxStackLimits =3D &SocketPciResourceData->Socket[Socket].StackLimi= ts[UBOX_STACK]; + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + + if (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack)) { + + IioUdsStackLimits =3D &mIioUds->IioUdsPtr->PlatformData.IIO_reso= urce[Socket].StackRes[Stack]; + StackLimits =3D &SocketPciResourceData->Socket[Socket].StackLimi= ts[Stack]; + // + // Per stack + // + if (Socket =3D=3D 0 && Stack =3D=3D 0) { + // First base starts at zero, mIioUds struct reserves 4K of Io= for legacy purposes + if (StackLimits->Io.Base !=3D 0) { + Rejected =3D TRUE; + } + } else { + if (IioUdsStackLimits->PciResourceIoBase !=3D StackLimits->Io.= Base && StackLimits->Io.Base !=3D 0) { + Rejected =3D TRUE; + } + } + if (IioUdsStackLimits->PciResourceIoLimit !=3D StackLimits->Io.L= imit && StackLimits->Io.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d.%d] Current I/O: 0x%04X..0x%04X\n", Socket, Stack, + IioUdsStackLimits->PciResourceIoBase, IioUdsStackLimit= s->PciResourceIoLimit); + PCIDEBUG ("[%d.%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket, St= ack, + StackLimits->Io.Base, StackLimits->Io.Limit, Rejected ?= "rejected" : ""); + + if (IioUdsStackLimits->Mmio32Base !=3D StackLimits->LowMmio.Base= && StackLimits->LowMmio.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsStackLimits->Mmio32Limit !=3D StackLimits->LowMmio.Lim= it && StackLimits->LowMmio.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d.%d] Current MMIOL: 0x%08X..0x%08X\n", Socket, Sta= ck, + IioUdsStackLimits->Mmio32Base, IioUdsStackLimits->Mmio= 32Limit); + PCIDEBUG ("[%d.%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket, = Stack, + StackLimits->LowMmio.Base, StackLimits->LowMmio.Limit,= Rejected ? "rejected" : ""); + + if (IioUdsStackLimits->Mmio64Base !=3D StackLimits->HighMmio.Bas= e && StackLimits->HighMmio.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsStackLimits->Mmio64Limit !=3D StackLimits->HighMmio.Li= mit && StackLimits->HighMmio.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d.%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socke= t, Stack, + IioUdsStackLimits->Mmio64Base, IioUdsStackLimits->Mmio= 64Limit); + PCIDEBUG ("[%d.%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", So= cket, Stack, + StackLimits->HighMmio.Base, StackLimits->HighMmio.Limi= t, Rejected ? "rejected" : ""); + } + } + // + // Per socket + // + if (IioUdsSocketLimits->PciResourceIoBase !=3D SocketLimits->Io.Base= && SocketLimits->Io.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsSocketLimits->PciResourceIoLimit !=3D SocketLimits->Io.Lim= it && SocketLimits->Io.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG("[%d] Current I/O: 0x%04X..0x%04X\n", Socket, + IioUdsSocketLimits->PciResourceIoBase, IioUdsSocketLimits->= PciResourceIoLimit); + PCIDEBUG("[%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket, + SocketLimits->Io.Base, SocketLimits->Io.Limit, Rejected ? "= rejected" : ""); + + if (IioUdsSocketLimits->Mmio32Base !=3D SocketLimits->LowMmio.Base &= & SocketLimits->LowMmio.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsSocketLimits->Mmio32Limit !=3D SocketLimits->LowMmio.Limit= && SocketLimits->LowMmio.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d] Current MMIOL: 0x%08X..0x%08X\n", Socket, + IioUdsSocketLimits->Mmio32Base, IioUdsSocketLimits->Mmio32L= imit); + PCIDEBUG ("[%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket, + SocketLimits->LowMmio.Base, SocketLimits->LowMmio.Limit, R= ejected ? "rejected" : ""); + + if (IioUdsSocketLimits->Mmio64Base !=3D SocketLimits->HighMmio.Base = && SocketLimits->HighMmio.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsSocketLimits->Mmio64Limit !=3D SocketLimits->HighMmio.Limi= t && SocketLimits->HighMmio.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socket, + IioUdsSocketLimits->Mmio64Base, IioUdsSocketLimits->Mmio64L= imit); + PCIDEBUG ("[%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", Socket, + SocketLimits->HighMmio.Base, SocketLimits->HighMmio.Limit,= Rejected ? "rejected" : ""); + + if (IioUdsUboxStackLimits->Mmio64Base !=3D UboxStackLimits->HighMmio= .Base && UboxStackLimits->HighMmio.Base !=3D 0) { + Rejected =3D TRUE; + } + if (IioUdsUboxStackLimits->Mmio64Limit !=3D UboxStackLimits->HighMmi= o.Limit && UboxStackLimits->HighMmio.Limit !=3D 0) { + Rejected =3D TRUE; + } + PCIDEBUG ("[%d] Current UBOX: 0x%08X..0x%08X\n", Socket, + IioUdsUboxStackLimits->Mmio64Base, IioUdsUboxStackLimits->= Mmio64Limit); + PCIDEBUG ("[%d] Saved UBOX: 0x%08X..0x%08X %a\n", Socket, + UboxStackLimits->HighMmio.Base, UboxStackLimits->HighMmio.= Limit, Rejected ? "rejected" : ""); + } + } + DEBUG ((DEBUG_INFO, "[PCI] Resource rebalance rejected ? %a\n", Rejected= ? "TRUE" : "FALSE")); + return Rejected; +} + + +/** + Read SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME variable from flash and = verify its content. + + If the variable does not exist, or is not valid for current system config= uration + the buffer at *PciResConfigPtr is just cleared. + + @param[out] PciResConfigPtr - Buffer for the resource configuration varia= ble. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to= a hardware error. + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to= an authentication failure. +**/ +EFI_STATUS +PciHostReadResourceConfig ( + OUT SYSTEM_PCI_BASE_LIMITS *PciResConfigPtr + ) +{ + UINTN VarSize; + EFI_STATUS Status; + UINT8 Socket; + + VarSize =3D sizeof(*PciResConfigPtr); + Status =3D gRT->GetVariable (SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME= , &gEfiSocketPciResourceDataGuid, + NULL, &VarSize, PciResConfigPtr); + if (EFI_ERROR (Status) && Status !=3D EFI_BUFFER_TOO_SMALL) { + goto ErrExit; + } + if (Status =3D=3D EFI_BUFFER_TOO_SMALL || VarSize !=3D sizeof(*PciResCon= figPtr)) { + + PCIDEBUG ("Got variable '%s' of unexpected size %d (expect %d) - overw= rite\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, VarSize, sizeof= (*PciResConfigPtr)); + Status =3D EFI_NOT_FOUND; + goto ErrExit; + } + // + // If any of the below checks fails clear the buffer and return EFI_NOT_= FOUND. + // + Status =3D EFI_NOT_FOUND; + if (PciResConfigPtr->MmioHBase !=3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalMmio64Base || + PciResConfigPtr->MmioHLimit !=3D mIioUds->IioUdsPtr->PlatformData.Pl= atGlobalMmio64Limit) { + + PCIDEBUG ("%s: Memory map changed (MMIOH %012llX..%012llX !=3D %012llX= ..%012llX) - overwrite\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->MmioHBase, PciResConfigPtr->MmioHLimit, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit); + goto ErrExit; + } + if (PciResConfigPtr->MmioLBase !=3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalMmio32Base || + PciResConfigPtr->MmioLLimit !=3D mIioUds->IioUdsPtr->PlatformData.Pl= atGlobalMmio32Limit) { + + PCIDEBUG ("%s: Memory map changed (MMIOL %08X..%08X !=3D %08X..%08X) -= overwrite\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->MmioLBase, PciResConfigPtr->MmioLLimit, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit); + goto ErrExit; + } + if (PciResConfigPtr->IoBase !=3D mIioUds->IioUdsPtr->PlatformData.PlatGl= obalIoBase || + PciResConfigPtr->IoLimit !=3D mIioUds->IioUdsPtr->PlatformData.PlatG= lobalIoLimit) { + + PCIDEBUG ("%s: Memory map changed (I/O %04X..%04X !=3D %04X..%04X) - o= verwrite\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->IoBase, PciResConfigPtr->IoLimit, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit); + goto ErrExit; + } + for (Socket =3D 0; Socket < NELEMENTS (PciResConfigPtr->Socket); Socket+= +) { + + if (PciResConfigPtr->StackPresentBitmap[Socket] !=3D + mIioUds->IioUdsPtr->Platform= Data.CpuQpiInfo[Socket].stackPresentBitmap) { + + PCIDEBUG ("%s: Stack bitmap mismach (%04X !=3D %04X) in socket %d - = overwrite\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, PciResConfigP= tr->StackPresentBitmap[Socket], + mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackP= resentBitmap, Socket); + goto ErrExit; + } + } + return EFI_SUCCESS; + + ErrExit: + ZeroMem (PciResConfigPtr, sizeof(*PciResConfigPtr)); + return Status; +} // PciHostReadResourceConfig() + + +/** + Adjust resource ratio assignment among CPU sockets to fit the resource n= eeds from PCI devices. + Update Setup variable if there are changes from the existing ratio reque= sts for this boot. + + @param[in] HostBridgeInstance - The Host Bridge Instance where the = resource adjustment happens. + @param[out] Result - Output parameter. Indicates whether= changes have been made. +**/ +VOID +AdjustResourceAmongRootBridges ( + IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance, + OUT SOCKET_RESOURCE_ADJUSTMENT_RESULT *Result + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + LIST_ENTRY *List; + CPU_RESOURCE SocketResources[MAX_SOCKET]; + UINT64 SocketIoLength; + UINT64 SocketMem32Length; + UINT64 SocketMem64Length; + UINT64 SocketIoBase; + UINT64 SocketMem32Base; + UINT64 SocketMem64Base; + UINT64 RsvLenAtBegin; + UINT64 RsvLenAtEnd; + UINT64 StackLength; + UINT64 NewLength; + UINT64 Alignment; + UINT64 Remainder; + UINT8 Socket; + UINT8 ValidSockets; + BOOLEAN ChangedType[TypeMax]; + BOOLEAN ChangedTypeOOR[TypeMax]; // Chang= e type for out of resources + UINT8 TypeIndex; + UINT8 ChangedBitMap; + EFI_STATUS Status; + SYSTEM_PCI_BASE_LIMITS SocketPciResourceData; + UINT8 Stack; + UINT8 LastStack; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64 MmiohGranularity; + BOOLEAN OutOfResources; + UINT32 UboxMmioSize; + BOOLEAN IsVirtualRootBridge; + PCI_BASE_LIMITS *CurStackLimits; + PCI_BASE_LIMITS *UboxStackLimits; + PCI_BASE_LIMITS *CurSocketLimits; + UINT32 PlatGlobalMmiolBase; + UINT32 VtdBarSize; + + *Result =3D SocketResourceRatioNotChanged; + SetMem (ChangedType, TypeMax, FALSE); + SetMem (ChangedTypeOOR, TypeMax, FALSE); + ChangedBitMap =3D 0; + OutOfResources =3D FALSE; + IsVirtualRootBridge =3D FALSE; + + IoGranularity =3D mIioUds->IioUdsPtr->PlatformData.IoGranularity; + MmiolGranularity =3D mIioUds->IioUdsPtr->PlatformData.MmiolGranularity; + MmiohGranularity =3D (UINT64) mIioUds->IioUdsPtr->PlatformData.MmiohGran= ularity.lo; + MmiohGranularity |=3D ((UINT64)mIioUds->IioUdsPtr->PlatformData.MmiohGra= nularity.hi) << 32; + ZeroMem (&SocketResources[0], sizeof(SocketResources)); + // + // Read the system resource cfg from NVRAM. If the variable does not exi= st, or is + // not valid for current system configuration the buffer SocketPciResour= ceData + // is just cleared. + // + Status =3D PciHostReadResourceConfig (&SocketPciResourceData); + if (EFI_ERROR (Status)) { + + if (Status !=3D EFI_NOT_FOUND) { + + ASSERT_EFI_ERROR (Status); + return; + } + // + // Variable is not initialized yet, go with empty structure. + // + } else if (IsResourceMapRejected (&SocketPciResourceData)) { + // + // If variable is already initialized, but rejected by KTI do not rebo= ot to avoid loop. + // + return; + } + + UboxMmioSize =3D mIioUds->IioUdsPtr->PlatformData.UboxMmioSize; + PlatGlobalMmiolBase =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio3= 2Base; + ValidSockets =3D 0; + for (List =3D HostBridgeInstance->RootBridges.ForwardLink, Socket =3D 0;= Socket < MAX_SOCKET; Socket ++) { + + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + continue; + } + ValidSockets++; + // + // Calculate the length of resources available per socket + // + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].PciResourceI= oBase >=3D + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].PciResourceI= oLimit) { + SocketIoBase =3D 0; + SocketIoLength =3D 0; + } else { + SocketIoBase =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socke= t].PciResourceIoBase; + SocketIoLength =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Soc= ket].PciResourceIoLimit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socke= t].PciResourceIoBase; + } + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Mmio32Base >= =3D + mIioUds->IioUdsPtr->Pla= tformData.IIO_resource[Socket].Mmio32Limit) { + SocketMem32Base =3D 0; + SocketMem32Length =3D 0; + } else { + SocketMem32Base =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].Mmio32Base; + SocketMem32Length =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[= Socket].Mmio32Limit - + mIioUds->IioUdsPtr->= PlatformData.IIO_resource[Socket].Mmio32Base; + // Reserve 8M for ubox mmio + SocketMem32Length =3D SocketMem32Length - UboxMmioSize; + } + + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Mmio64Base >= =3D + mIioUds->IioUdsPtr->Pla= tformData.IIO_resource[Socket].Mmio64Limit) { + SocketMem64Base =3D 0; + SocketMem64Length =3D 0; + } else{ + SocketMem64Base =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].Mmio64Base; + SocketMem64Length =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[= Socket].Mmio64Limit - + mIioUds->IioUdsPtr->= PlatformData.IIO_resource[Socket].Mmio64Base; + } + + // Get all the resources that are in this socket + SocketResources[Socket].IoResourcesLeft =3D (UINT16)SocketIoLength; + SocketResources[Socket].MmiolResourcesLeft =3D (UINT32)SocketMem32Leng= th; + SocketResources[Socket].MmiohResourcesLeft =3D (UINT64)SocketMem64Leng= th; + + LastStack =3D LastStackOfSocket (Socket); + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack))) { + continue; + } + RootBridgeInstance =3D ROOT_BRIDGE_FROM_LINK (List); + // + // Check IO Resource + // + Alignment =3D RootBridgeInstance->ResAllocNode[TypeIo].Alignment + 1; + NewLength =3D RootBridgeInstance->ResAllocNode[TypeIo].Length; + + if (IsVirtualRootBridge) { + NewLength +=3D NewLength; + } + // IoTrap allocates 256 byte range from GCD for common pool usage + // For device to fit move to the next available alignment + if ((Socket =3D=3D 0) && (Stack =3D=3D 0)) { + NewLength +=3D Alignment; + } + + if (NewLength !=3D 0) { + // + // At least 2KB align per KTI requirement. Add the length requeste= d with given alignment. + // If the sum is not 2KB aligned add on the remainder that would m= ake it align. + // Bump up to 4KB for root bridge requirements + // Have to make sure Alignment is handled for direct address alloc= ation + // + Remainder =3D SocketIoBase & (Alignment - 1); + if (Remainder !=3D 0) { + NewLength +=3D Alignment - Remainder; + } + if (NewLength % (IoGranularity * 2)) { + Remainder =3D (IoGranularity * 2) - (NewLength % (IoGranularity = * 2)); + NewLength +=3D Remainder; + } + // + // Store length as length - 1 for handling + // + NewLength -=3D 1; + + // Zero StackLength if its disable or negative + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes= [Stack].PciResourceIoBase >=3D + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes= [Stack].PciResourceIoLimit) { + StackLength =3D 0; + } else { + StackLength =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].StackRes[Stack].PciResourceIoLimit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Sock= et].StackRes[Stack].PciResourceIoBase; + } + SocketResources[Socket].StackRes[Stack].NumIoPortsDesired =3D (UIN= T16)NewLength; + // Check if new length can fit in the socket or stack + if (SocketResources[Socket].IoResourcesLeft > (UINT16)NewLength) { + SocketResources[Socket].IoResourcesLeft -=3D (UINT16)NewLengt= h + 1; + } else if (SocketResources[Socket].IoResourcesLeft =3D=3D (UINT16)= NewLength) { + SocketResources[Socket].IoResourcesLeft -=3D (UINT16)NewLengt= h; + } else { + // If there are resources left consume them + if (SocketResources[Socket].IoResourcesLeft !=3D 0) { + NewLength =3D NewLength - SocketResources[Socket].IoResourcesL= eft - 1; + SocketResources[Socket].IoResourcesLeft =3D 0; + } + + SocketResources[Socket].IoResourceNeeds +=3D (UINT16)NewLength += 1; + OutOfResources =3D TRUE; + ChangedTypeOOR[TypeIo] =3D TRUE; + } + SocketResources[Socket].StackRes[Stack].IoAlignment =3D Alignment; + if (NewLength > StackLength) { + SocketResources[Socket].StackRes[Stack].NeedIoUpdate =3D TRUE; + + //IoResourcesLeft is UINT16 type, not 2's-complement value. + if (SocketResources[Socket].IoResourcesLeft > SocketIoLength) { + DEBUG ((DEBUG_ERROR, "[PCI] Out of Resources for Socket =3D %x= Stack =3D %x Type =3D %x\n", + Socket, Stack, TypeIo)); + SocketResources[Socket].IoResourcesLeft =3D 0; + } + ChangedType[TypeIo] =3D TRUE; + } + SocketIoBase +=3D SocketResources[Socket].StackRes[Stack].NumIoPor= tsDesired + 1; + DEBUG ((DEBUG_INFO, "SocketResources[%x].IoResourceLeft =3D %x\n", + Socket, SocketResources[Socket].IoResourcesLeft)); + DEBUG ((DEBUG_INFO, "SocketResources[%x].StackRes[%x].IoAlignment = =3D %x\n", + Socket, Stack, SocketResources[Socket].StackRes[Stack].IoAl= ignment)); + } else { + SocketResources[Socket].StackRes[Stack].NumIoPortsDesired =3D 0; + } + // + // Check Mmem32 resource. This Host bridge does not support separate= d MEM / PMEM requests, + // so only count MEM requests here. + // + Alignment =3D RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = + 1; + NewLength =3D RootBridgeInstance->ResAllocNode[TypeMem32].Length; + // + // Account for reserved regions at begin and end of the stack MMIO32= region. + // + RsvLenAtBegin =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Sock= et].StackRes[Stack].PciResourceMem32Base - + mIioUds->IioUdsPtr->PlatformData.IIO= _resource[Socket].StackRes[Stack].Mmio32Base; + + RsvLenAtEnd =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket= ].StackRes[Stack].Mmio32Limit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[S= ocket].StackRes[Stack].PciResourceMem32Limit; + NewLength +=3D RsvLenAtBegin + RsvLenAtEnd; + if (Alignment < RsvLenAtBegin) { + Alignment =3D RsvLenAtBegin; + } + if (Alignment < RsvLenAtEnd) { + Alignment =3D RsvLenAtEnd; + } + // + // Always account for VT-d reserved resource ranges. + // TODO: Remove when VTd BAR is included in RsvLenAtEnd. + // + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes[S= tack].VtdBarAddress !=3D 0) { + + VtdBarSize =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socke= t].StackRes[Stack].PciResourceMem32Limit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket]= .StackRes[Stack].VtdBarAddress + 1; + NewLength +=3D VtdBarSize; + if (Alignment < VtdBarSize) { + Alignment =3D VtdBarSize; + } + } + + if (IsVirtualRootBridge) { + NewLength +=3D NewLength; + } + // PCH Allocates reserved MMIO for Sx SMI handler use + // For device to fit move to the next available alignment + if ((Socket =3D=3D 0) && (Stack =3D=3D 0)) { + NewLength +=3D Alignment; + } + + if (NewLength !=3D 0) { + // + // At least 4MB align per KTI requirement. Add the length requeste= d with given alignment. + // If the sum is not 4MB aligned add on the remainder that would m= ake it align. + // Have to make sure Alignment is handled for direct address alloc= ation + // + Remainder =3D SocketMem32Base & (Alignment - 1); + if (Remainder !=3D 0) { + NewLength +=3D Alignment - Remainder; + } + if (NewLength % MmiolGranularity) { + + Remainder =3D MmiolGranularity - (NewLength % MmiolGranularity); + NewLength +=3D Remainder; + } + + if (Stack =3D=3D LastStack) { + // + // Ubox address must be 8MB aligned for the base address on most= processors; skip check + // if uboxMmioSize is 0 (avoid divide by zero exception). + // At this point the requested resource has already been calcula= ted to be satisfied. + // Add granularity padding if necessary to satisfy Ubox requirem= ent. + // + if (UboxMmioSize !=3D 0 && (SocketMem32Base + NewLength) % UboxM= mioSize) { + Remainder =3D UboxMmioSize - (NewLength % UboxMmioSize); + NewLength +=3D Remainder; + } + } + // + // Store length as length - 1 for handling + // + NewLength -=3D 1; + + // Zero StackLength if its disable or negative + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes= [Stack].Mmio32Base >=3D + mIioUds->IioUdsPtr->PlatformData.IIO_re= source[Socket].StackRes[Stack].Mmio32Limit) { + StackLength =3D 0; + } else { + StackLength =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].StackRes[Stack].Mmio32Limit - + mIioUds->IioUdsPtr->PlatformData.IIO= _resource[Socket].StackRes[Stack].Mmio32Base; + } + SocketResources[Socket].StackRes[Stack].MmiolLength =3D (UINT32)Ne= wLength; + + // Check if new length can fit in the socket or stack + if (SocketResources[Socket].MmiolResourcesLeft > (UINT32)NewLength= ) { + SocketResources[Socket].MmiolResourcesLeft -=3D (UINT32)NewLe= ngth + 1; + } else if (SocketResources[Socket].MmiolResourcesLeft =3D=3D (UINT= 32)NewLength) { + SocketResources[Socket].MmiolResourcesLeft -=3D (UINT32)NewLe= ngth; + } else { + // If there are resources left consume them + if (SocketResources[Socket].MmiolResourcesLeft) { + NewLength =3D NewLength - SocketResources[Socket].MmiolRes= ourcesLeft - 1; + SocketResources[Socket].MmiolResourcesLeft =3D 0; + } + + SocketResources[Socket].MmiolResourceNeeds +=3D (UINT32)NewLen= gth + 1; + OutOfResources =3D TRUE; + ChangedTypeOOR[TypeMem32] =3D TRUE; + } + SocketResources[Socket].StackRes[Stack].MmiolAlignment =3D Alignme= nt; + + if (NewLength > StackLength) { + SocketResources[Socket].StackRes[Stack].MmiolUpdate =3D 1; + + //MmiolResourcesLeft is UINT32 type, not 2's-complement value. + if (SocketResources[Socket].MmiolResourcesLeft > SocketMem32Leng= th) { + DEBUG ((DEBUG_ERROR, "Out of Resources for Socket =3D %x Stac= k =3D %x Type =3D %x\n", + Socket, Stack, TypeMem32)); + SocketResources[Socket].MmiolResourcesLeft =3D 0; + } + ChangedType[TypeMem32] =3D TRUE; + } + SocketMem32Base +=3D SocketResources[Socket].StackRes[Stack].Mmiol= Length + 1; + DEBUG ((DEBUG_INFO, "SocketResources[%x].MmiolResourceLeft =3D %x\= n", + Socket, SocketResources[Socket].MmiolResourcesLeft)); + DEBUG ((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiolAlignme= nt =3D %x\n", + Socket, Stack, SocketResources[Socket].StackRes[Stack].Mmio= lAlignment)); + } else { + SocketResources[Socket].StackRes[Stack].MmiolLength =3D 0; + } + // + // Check Mem64 resource. This Host bridge does not support separated= MEM / PMEM requests, so only count MEM requests here. + // + Alignment =3D RootBridgeInstance->ResAllocNode[TypeMem64].Alignment = + 1; + NewLength =3D RootBridgeInstance->ResAllocNode[TypeMem64].Length; + // + // Account for reserved regions at begin and end of the stack MMIO32= region. + // + RsvLenAtBegin =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Sock= et].StackRes[Stack].PciResourceMem64Base - + mIioUds->IioUdsPtr->PlatformData.IIO= _resource[Socket].StackRes[Stack].Mmio64Base; + + RsvLenAtEnd =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket= ].StackRes[Stack].Mmio64Limit - + mIioUds->IioUdsPtr->PlatformData.IIO_resource[S= ocket].StackRes[Stack].PciResourceMem64Limit; + NewLength +=3D RsvLenAtBegin + RsvLenAtEnd; + if (Alignment < RsvLenAtBegin) { + Alignment =3D RsvLenAtBegin; + } + if (Alignment < RsvLenAtEnd) { + Alignment =3D RsvLenAtEnd; + } + if (IsVirtualRootBridge) { + NewLength +=3D NewLength; + } + + if (NewLength !=3D 0) { + // + // At least 1GB align per KTI requirement. Add the length requeste= d with given alignment. + // If the sum is not 1GB aligned add on the remainder that would m= ake it align. + // Have to make sure Alignment is handled for direct address alloc= ation + // + Remainder =3D SocketMem64Base & (Alignment - 1); + if (Remainder !=3D 0) { + NewLength +=3D Alignment - Remainder; + } + if (NewLength % MmiohGranularity) { + Remainder =3D MmiohGranularity - (NewLength % MmiohGranularity); + NewLength +=3D Remainder; + } + // + // Store length as length - 1 for handling + // + NewLength -=3D 1; + + // Zero StackLength if it's disable or negative + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes= [Stack].Mmio64Base >=3D + mIioUds->IioUdsPtr->PlatformData.IIO_re= source[Socket].StackRes[Stack].Mmio64Limit) { + StackLength =3D 0; + } else { + StackLength =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].StackRes[Stack].Mmio64Limit - + mIioUds->IioUdsPtr->PlatformData.IIO= _resource[Socket].StackRes[Stack].Mmio64Base; + } + SocketResources[Socket].StackRes[Stack].MmiohLength =3D NewLength; + + // Check if new length can fit in the socket or stack + if (SocketResources[Socket].MmiohResourcesLeft > NewLength) { + SocketResources[Socket].MmiohResourcesLeft -=3D NewLength + 1; + } else if (SocketResources[Socket].MmiohResourcesLeft =3D=3D NewLe= ngth) { + SocketResources[Socket].MmiohResourcesLeft -=3D NewLength; + } else { + // If there are resources left consume them + if (SocketResources[Socket].MmiohResourcesLeft !=3D 0) { + NewLength =3D NewLength - SocketResources[Socket].MmiohResourc= esLeft - 1; + SocketResources[Socket].MmiohResourcesLeft =3D 0; + } + + SocketResources[Socket].MmiohResourceNeeds +=3D NewLength + 1; + OutOfResources =3D TRUE; + ChangedTypeOOR[TypeMem64] =3D TRUE; + } + SocketResources[Socket].StackRes[Stack].MmiohAlignment =3D Alignme= nt; + + if (NewLength > StackLength) { + SocketResources[Socket].StackRes[Stack].MmiohUpdate =3D 1; + + //MmiohResourcesLeft is UINT64 type, not 2's-complement value. + if (SocketResources[Socket].MmiohResourcesLeft > SocketMem64Leng= th) { + DEBUG ((DEBUG_ERROR, "Out of Resources for Socket =3D %x Stac= k =3D %x Type =3D %x\n", + Socket, Stack, TypeMem64)); + SocketResources[Socket].MmiohResourcesLeft =3D 0; + } + ChangedType[TypeMem64] =3D TRUE; + } + SocketMem64Base +=3D SocketResources[Socket].StackRes[Stack].Mmioh= Length + 1; + DEBUG ((DEBUG_INFO, "SocketResources[%x].MmiohResourceLeft =3D %lx= \n", + Socket, SocketResources[Socket].MmiohResourcesLeft)); + DEBUG ((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiohAlignme= nt =3D %lx\n", + Socket, Stack, SocketResources[Socket].StackRes[Stack].Mmio= hAlignment)); + } else { + SocketResources[Socket].StackRes[Stack].MmiohLength =3D 0; + } + + List =3D List->ForwardLink; + + } // for Stack + + // Check and update all resource types in socket that needs adjustment + for (TypeIndex =3D 0; TypeIndex < TypeMax; TypeIndex++) { + + if (ChangedType[TypeIndex]) { + + DEBUG ((DEBUG_INFO, "[%d] Adjust stack %s resources...\n", Socket,= mPciResourceTypeStr[TypeIndex])); + Status =3D AdjustResources (&SocketResources[Socket], Socket, Type= Index); + ChangedType[TypeIndex] =3D FALSE; + if (Status =3D=3D EFI_SUCCESS) { + ChangedBitMap |=3D (1 << TypeIndex); + } else { + ChangedBitMap &=3D ~(1 << TypeIndex); + } + } + } + // + // Account for Ubox resources to accurately calculate new alignments f= or the next socket + // + SocketMem32Base +=3D UboxMmioSize; + } // for Socket .. + + ASSERT (List =3D=3D &HostBridgeInstance->RootBridges); + + // + // If a socket is out of resources, try to adjusting sockets for more ro= om. + // + if (OutOfResources && (MAX_SOCKET > 1) && (ValidSockets > 1)) { + + for (TypeIndex =3D 0; TypeIndex < TypeMax; TypeIndex++) { + + if (ChangedTypeOOR[TypeIndex]) { + + DEBUG ((DEBUG_INFO, "Adjust socket %s resources...\n", mPciResourc= eTypeStr[TypeIndex])); + Status =3D AdjustSocketResources (SocketResources, TypeIndex, Vali= dSockets); + if (Status =3D=3D EFI_SUCCESS) { + ChangedBitMap |=3D (1 << TypeIndex); + } else { + ChangedBitMap &=3D ~(1 << TypeIndex); + } + } + } + } else if (OutOfResources && ChangedTypeOOR[TypeMem64]){ + // + // Allow mmioh to be adjusted to access max available physical address= range. + // + Status =3D AdjustSocketResources (SocketResources, TypeMem64, ValidSoc= kets); + if (Status =3D=3D EFI_SUCCESS) { + ChangedBitMap |=3D (1 << TypeIndex); + } else { + ChangedBitMap &=3D ~(1 << TypeIndex); + } + } + + // Update changed resource type. + // OemGetResourceMapUpdate() will only update changed resource type so i= t is alright if data is zero. + if (ChangedBitMap !=3D 0) { + + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + + SocketPciResourceData.StackPresentBitmap[Socket] =3D mIioUds->IioUds= Ptr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap; + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + CurStackLimits =3D &SocketPciResourceData.Socket[Socket].StackLimi= ts[Stack]; + + // + // Disable stacks that have no resources and are assigned none. + // Reaching this far means the stack is valid and should be disabl= ed if base equals limit and + // length is zero. + // Assigned address will be none zero at this point because CSTACK= takes the first 4K in legacy + // IO space. + // + if ((SocketResources[Socket].StackRes[Stack].NeedIoUpdate) && + (SocketResources[Socket].StackRes[Stack].IoLimit - + SocketResources[Socket].StackRes[Stack].IoBase =3D=3D 0)) { + SocketResources[Socket].StackRes[Stack].IoBase =3D (UINT16)(-1); + SocketResources[Socket].StackRes[Stack].IoLimit =3D 0; + } + + if ((SocketResources[Socket].StackRes[Stack].MmiolUpdate) && + (SocketResources[Socket].StackRes[Stack].MmiolLimit - + SocketResources[Socket].StackRes[Stack].MmiolBase =3D=3D 0)) { + SocketResources[Socket].StackRes[Stack].MmiolBase =3D (UINT32)(-= 1); + SocketResources[Socket].StackRes[Stack].MmiolLimit =3D 0; + } + + if ((SocketResources[Socket].StackRes[Stack].MmiohUpdate) && + (SocketResources[Socket].StackRes[Stack].MmiohLimit - + SocketResources[Socket].StackRes[Stack].MmiohBase =3D=3D 0)) { + SocketResources[Socket].StackRes[Stack].MmiohBase =3D (UINT64)(-= 1); + SocketResources[Socket].StackRes[Stack].MmiohLimit =3D 0; + } + + // Zero base if 4K because mIioUds struct reserves 4K of Io for le= gacy purposes + // Remove if mIioUds first base starts at zero + if (SocketResources[Socket].StackRes[Stack].IoBase =3D=3D 0x1000){ + SocketResources[Socket].StackRes[Stack].IoBase =3D 0; + } + + if (SocketResources[Socket].StackRes[Stack].NeedIoUpdate) { + CurStackLimits->Io.Base =3D SocketResources[Socket].StackRes[Sta= ck].IoBase; + CurStackLimits->Io.Limit =3D SocketResources[Socket].StackRes[St= ack].IoLimit; + } + + if (SocketResources[Socket].StackRes[Stack].MmiolUpdate) { + if ((Socket =3D=3D 0) && (Stack =3D=3D 0)) { + CurStackLimits->LowMmio.Base =3D PlatGlobalMmiolBase; + } else { + CurStackLimits->LowMmio.Base =3D SocketResources[Socket].Stack= Res[Stack].MmiolBase; + } + CurStackLimits->LowMmio.Limit =3D SocketResources[Socket].StackR= es[Stack].MmiolLimit; + } + + if (SocketResources[Socket].StackRes[Stack].MmiohUpdate) { + CurStackLimits->HighMmio.Base =3D SocketResources[Socket].StackR= es[Stack].MmiohBase; + CurStackLimits->HighMmio.Limit =3D SocketResources[Socket].Stack= Res[Stack].MmiohLimit; + } + + DEBUG((DEBUG_INFO, "\nSocketResources[%x].StackRes[%x].IoBase =3D%= x\n",Socket,Stack,SocketResources[Socket].StackRes[Stack].IoBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].IoLimit =3D%x= \n",Socket,Stack,SocketResources[Socket].StackRes[Stack].IoLimit)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiolBase =3D= %x\n",Socket,Stack,SocketResources[Socket].StackRes[Stack].MmiolBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiolLimit = =3D%x\n",Socket,Stack,SocketResources[Socket].StackRes[Stack].MmiolLimit)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiohBase =3D= %lx\n",Socket,Stack,SocketResources[Socket].StackRes[Stack].MmiohBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].StackRes[%x].MmiohLimit = =3D%lx\n",Socket,Stack,SocketResources[Socket].StackRes[Stack].MmiohLimit)); + } // for Stack + + // Initialize to disabled + SocketResources[Socket].IoBase =3D (UINT16)(-1); + SocketResources[Socket].IoLimit =3D 0; + SocketResources[Socket].MmiolBase =3D (UINT32)(-1); + SocketResources[Socket].MmiolLimit =3D 0; + SocketResources[Socket].MmiohBase =3D (UINT64)(-1); + SocketResources[Socket].MmiohLimit =3D 0; + + // Search backwards to find the beginning valid stack + for (Stack =3D MAX_IIO_STACK - 1; Stack < MAX_IIO_STACK ; Stack--) { + CurSocketLimits =3D &SocketPciResourceData.Socket[Socket].SocketLi= mits; + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + + if (SocketResources[Socket].StackRes[Stack].IoBase !=3D (UINT16)(-= 1)) { + SocketResources[Socket].IoBase =3D SocketResources[Socket].Stack= Res[Stack].IoBase; + } + + if (SocketResources[Socket].StackRes[Stack].MmiolBase !=3D (UINT32= )(-1)) { + SocketResources[Socket].MmiolBase =3D SocketResources[Socket].St= ackRes[Stack].MmiolBase; + } + + if (SocketResources[Socket].StackRes[Stack].MmiohBase !=3D (UINT64= )(-1)) { + SocketResources[Socket].MmiohBase =3D SocketResources[Socket].St= ackRes[Stack].MmiohBase; + } + } // for Stack + + // Search to find the last valid limit + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + + if (SocketResources[Socket].StackRes[Stack].IoLimit !=3D 0) { + SocketResources[Socket].IoLimit =3D SocketResources[Socket].Stac= kRes[Stack].IoLimit; + } + + if (SocketResources[Socket].StackRes[Stack].MmiolLimit) { + SocketResources[Socket].MmiolLimit =3D SocketResources[Socket].S= tackRes[Stack].MmiolLimit; + } + + if (SocketResources[Socket].StackRes[Stack].MmiohLimit) { + SocketResources[Socket].MmiohLimit =3D SocketResources[Socket].S= tackRes[Stack].MmiohLimit; + } + } // for Stack + + // Update socket level resource range + if (SocketResources[Socket].StackRes[0].NeedIoUpdate) { + CurSocketLimits->Io.Base =3D SocketResources[Socket].IoBase; + CurSocketLimits->Io.Limit =3D SocketResources[Socket].IoLimit; + } + + if (SocketResources[Socket].StackRes[0].MmiolUpdate) { + // + // Apply stolen 8M for ubox mmio per socket + // + if (UboxMmioSize !=3D 0) { + UboxStackLimits =3D &SocketPciResourceData.Socket[Socket].StackL= imits[UBOX_STACK]; + + UboxStackLimits->LowMmio.Base =3D SocketResources[Socket].MmiolL= imit + 1; + SocketResources[Socket].MmiolLimit =3D (UINT32)UboxStackLimits->= LowMmio.Base + UboxMmioSize - 1; + UboxStackLimits->LowMmio.Limit =3D SocketResources[Socket].Mmiol= Limit; + } + CurSocketLimits->LowMmio.Base =3D SocketResources[Socket].MmiolBas= e; + CurSocketLimits->LowMmio.Limit =3D SocketResources[Socket].MmiolLi= mit; + } + + if (SocketResources[Socket].StackRes[0].MmiohUpdate) { + CurSocketLimits->HighMmio.Base =3D SocketResources[Socket].MmiohB= ase; + CurSocketLimits->HighMmio.Limit =3D SocketResources[Socket].MmiohL= imit; + } + + DEBUG((DEBUG_INFO, "\nSocketResources[%x].UboxBase =3D%x\n",Socket,U= boxStackLimits->LowMmio.Base)); + DEBUG((DEBUG_INFO, "SocketResources[%x].UboxLimit =3D%x\n",Socket,Ub= oxStackLimits->LowMmio.Limit)); + DEBUG((DEBUG_INFO, "\nSocketResources[%x].IoBase =3D%x\n",Socket,Soc= ketResources[Socket].IoBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].IoLimit =3D%x\n",Socket,Sock= etResources[Socket].IoLimit)); + DEBUG((DEBUG_INFO, "SocketResources[%x].MmiolBase =3D%x\n",Socket,So= cketResources[Socket].MmiolBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].MmiolLimit =3D%x\n",Socket,S= ocketResources[Socket].MmiolLimit)); + DEBUG((DEBUG_INFO, "SocketResources[%x].MmiohBase =3D%lx\n",Socket,S= ocketResources[Socket].MmiohBase)); + DEBUG((DEBUG_INFO, "SocketResources[%x].MmiohLimit =3D%lx\n",Socket,= SocketResources[Socket].MmiohLimit)); + } // for Socket + SocketPciResourceData.MmioHBase =3D mIioUds->IioUdsPtr->PlatformData.P= latGlobalMmio64Base; + SocketPciResourceData.MmioHLimit =3D mIioUds->IioUdsPtr->PlatformData.= PlatGlobalMmio64Limit; + SocketPciResourceData.MmioLBase =3D mIioUds->IioUdsPtr->PlatformData.P= latGlobalMmio32Base; + SocketPciResourceData.MmioLLimit =3D mIioUds->IioUdsPtr->PlatformData.= PlatGlobalMmio32Limit; + SocketPciResourceData.IoBase =3D mIioUds->IioUdsPtr->PlatformData.Plat= GlobalIoBase; + SocketPciResourceData.IoLimit =3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalIoLimit; + + PCIDEBUG("Writing resource rebalance request '%s':\n", SYSTEM_PCI_RESO= URCE_CONFIGURATION_DATA_NAME); + PCIDEBUG("System I/O : %04X..%04X\n", SocketPciResourceData.IoBase, S= ocketPciResourceData.IoLimit); + PCIDEBUG("System MMIOL: %08X..%08X\n", SocketPciResourceData.MmioLBase= , SocketPciResourceData.MmioLLimit); + PCIDEBUG("System MMIOH: %012llX..%012llX\n", SocketPciResourceData.Mmi= oHBase, SocketPciResourceData.MmioHLimit); + for (Socket =3D 0; Socket < NELEMENTS (SocketPciResourceData.Socket); = Socket++) { + + PCIDEBUG("[%d] StackPresent: 0x%04X\n", Socket, SocketPciResourceDat= a.StackPresentBitmap[Socket]); + PCIDEBUG("[%d] I/O : %04X..%04X\n", Socket, + SocketPciResourceData.Socket[Socket].SocketLimits.Io.Base, + SocketPciResourceData.Socket[Socket].SocketLimits.Io.Limit); + PCIDEBUG("[%d] MMIOL: %08X..%08X\n", Socket, + SocketPciResourceData.Socket[Socket].SocketLimits.LowMmio.B= ase, + SocketPciResourceData.Socket[Socket].SocketLimits.LowMmio.L= imit); + PCIDEBUG("[%d] MMIOH: %012llX..%012llX\n", Socket, + SocketPciResourceData.Socket[Socket].SocketLimits.HighMmio.= Base, + SocketPciResourceData.Socket[Socket].SocketLimits.HighMmio.= Limit); + for (Stack =3D 0; Stack < NELEMENTS (SocketPciResourceData.Socket[S= ocket].StackLimits); Stack++) { + + PCIDEBUG("[%d.%d] I/O : %04X..%04X\n", Socket, Stack, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].I= o.Base, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].I= o.Limit); + PCIDEBUG("[%d.%d] MMIOL: %08X..%08X\n", Socket, Stack, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].L= owMmio.Base, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].L= owMmio.Limit); + PCIDEBUG("[%d.%d] MMIOH: %012llX..%012llX\n", Socket, Stack, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].H= ighMmio.Base, + SocketPciResourceData.Socket[Socket].StackLimits[Stack].H= ighMmio.Limit); + } + } + + *Result =3D SocketResourceRatioChanged; + Status =3D gRT->SetVariable( + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + &gEfiSocketPciResourceDataGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof(SocketPciResourceData), + &SocketPciResourceData + ); + ASSERT_EFI_ERROR(Status); + } + + return; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalance.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pc= iHostBridge/PciRebalance.h new file mode 100644 index 0000000000..85a9192c12 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= Rebalance.h @@ -0,0 +1,158 @@ +/** @file + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIREBALANCE_H_ +#define _PCIREBALANCE_H_ + +/*************************************************************************= ***** + * Definitions. + *************************************************************************= *****/ +/** + Uncomment the PCIDEBUG macro to enable tracing the library activity in a= test build. + **/ +#define PCIDEBUG(...) // { DEBUG((DEBUG_INFO, "[PCI] " __VA_ARGS__)); } + +typedef enum { + SocketResourceRatioChanged, + SocketResourceRatioNotChanged, + SocketResourceAdjustMax +} SOCKET_RESOURCE_ADJUSTMENT_RESULT; + +typedef struct { + UINT16 IoBase; // IO base of each stack + UINT16 IoLimit; // IO limit for each stack + UINT16 NumIoPortsDesired; + UINT64 IoAlignment; + BOOLEAN NeedIoUpdate; // Resource allocation required. + UINT32 MmiolBase; // Mmiol base of each stack + UINT32 MmiolLimit; // Mmiol limit of each stack + UINT32 MmiolLength; + UINT64 MmiolAlignment; + UINT8 MmiolUpdate; // Resource allocation required. + UINT64 MmiohBase; // Mmioh base of each stack + UINT64 MmiohLimit; // Mmioh limit of each stack + UINT64 MmiohLength; + UINT64 MmiohAlignment; + UINT8 MmiohUpdate; // Resource allocation required. +} STACK_RESOURCE; + +typedef struct{ + UINT16 IoBase; // Io base of each socket + UINT16 IoLimit; // Io limit for each socket + UINT16 IoResourcesLeft; // Io resources left over in socket + UINT16 IoResourceNeeds; // Io resources lacking in socket + UINT32 MmiolBase; // Mmiol base of each socket + UINT32 MmiolLimit; // Mmiol limit of each socket + UINT32 MmiolResourcesLeft; // Mmiol resources left over in socket + UINT32 MmiolResourceNeeds; // Mmiol resources lacking in socket + UINT64 MmiohBase; // Mmioh base of each socket + UINT64 MmiohLimit; // Mmioh limit of each socket + UINT64 MmiohResourcesLeft; // Mmioh resources left over in socket + UINT64 MmiohResourceNeeds; // Mmioh resources lacking in socket + STACK_RESOURCE StackRes[MAX_LOGIC_IIO_STACK]; +} CPU_RESOURCE; + + +/*************************************************************************= ***** + * Function prototypes. + *************************************************************************= *****/ +extern PCI_ROOT_BRIDGE_INSTANCE *mPciRootBridgeTable[MAX_SOCKET][MAX_LOGIC= _IIO_STACK]; +extern PCI_ROOT_BRIDGE_INSTANCE *mPciRootBridgeTableReserved[MAX_SOCKET][I= IO_RESERVED_1]; + + +/*************************************************************************= ***** + * Function prototypes. + *************************************************************************= *****/ + +/** + Adjust resource ratio assignment among CPU sockets to fit the resource n= eeds from PCI devices. + Update Setup variable if there are changes from the existing ratio reque= sts for this boot. + + @param HostBridgeInstance - The Host Bridge Instance where the resou= rce adjustment happens. + @param Result - Output parameter. Indicates whether chan= ges have been made. +**/ +VOID +AdjustResourceAmongRootBridges ( + IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance, + OUT SOCKET_RESOURCE_ADJUSTMENT_RESULT *Result + ); + +EFI_STATUS +AdjustSocketIo ( + IN OUT CPU_RESOURCE *SocketResources, + IN UINT8 ResourceType, + IN UINT8 ValidSockets + ); + +EFI_STATUS +AdjustSocketMmioH ( + IN OUT CPU_RESOURCE *SocketResources, + IN UINT8 ResourceType, + IN UINT8 ValidSockets + ); + +EFI_STATUS +AdjustSocketMmioL ( + IN OUT CPU_RESOURCE *SocketResources, + IN UINT8 ResourceType, + IN UINT8 ValidSockets + ); + +/** + Determine the last stack for a given socket + + @param Socket the socket for which the last socket is desired + + @return The number of the last stack is returned. +*/ +UINT8 +LastStackOfSocket ( + IN UINT8 Socket + ); + +/** + Determine the last stack for a given socket with resources + + @param SocketResources - CPU_RESOURCE structure pointer that stores al= l resources need per stack + @param Socket - Index of the Socket + @param ResourceType - Type of resource that requires alignment + @param LastStack - Pointer that will store the value of the last= stack with resources allocated to it + @param ResourceSize - Pointer that will store the sum of the reques= ted resource type + + @return The last stack with resources allocated to it and the + total amount of resoures requested of the type + requested. +*/ +VOID +LastStackWithResources ( + IN CPU_RESOURCE *SocketResources, + IN UINT8 Socket, + IN PCI_RESOURCE_TYPE ResourceType, + OUT UINT8 *LastStack, + OUT UINT64 *ResourceSize + ); + +/** + Find socket and stack index for given PCI Root Bridge protocol pointer. + + @param[out] PciResConfigPtr - Buffer for the resource configuration varia= ble. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to= a hardware error. + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to= an authentication failure. +**/ +EFI_STATUS +PciRootBridge2SocketStack ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridgePtr, + OUT UINT8 *SocketPtr, + OUT UINT8 *StackPtr + ); + +#endif // _PCIREBALANCE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalanceIo.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/= PciHostBridge/PciRebalanceIo.c new file mode 100644 index 0000000000..cc0fd2b562 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= RebalanceIo.c @@ -0,0 +1,218 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#include "PciHostBridge.h" +#include "PciRootBridge.h" +#include "PciRebalance.h" + + +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + +/** + Return TRUE if the specified socket/stack combination exists, + otherwise return FALSE + + @param Socket - the socket to be checked + @param Stack - the stack of the socket to be checked + + @retval TRUE - the socket/stack combination exists + @retval FALSE - the socket/stack combination does not exist +*/ +STATIC BOOLEAN +IsStackPresent ( + UINT8 Socket, + UINT8 Stack + ) +{ + BOOLEAN Result; + UINT64 Mask; + + ASSERT (Socket < ARRAY_SIZE (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo= )); // simple overrun check + if (Socket >=3D ARRAY_SIZE (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo)= ) { + Result =3D FALSE; + goto err_exit; + } + + // + // if the StackPresentBitmap is a single byte, then we can track 8 stack= s, + // the sizeof will tell us how many bytes we have, we scale by 8 to + // determine the maximum number of stacks we can track. Stacks larger + // than this are not present essentially by definition, but could also + // be a sign that we need a wider type to store the information; hence we + // assert + // + ASSERT (Stack < 8 * sizeof(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[0= ].stackPresentBitmap)); + if (Stack >=3D 8 * sizeof(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[0]= .stackPresentBitmap)) { + Result =3D FALSE; + goto err_exit; + } + + Mask =3D 1; + Mask <<=3D Stack; + Result =3D (Mask & mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].s= tackPresentBitmap) !=3D 0; + +err_exit: + return Result; +} + + +/** + Adjust resource assignment among sockets to fit the IO + resources from the PCI() devices in the system + + @param SocketResources - CPU_RESOURCE structure pointer that stores a= ll resources need per socket + @param ResourceType - type of resource that requires alignment + @param ValidSockets - Number of Valid Sockets, need it + to calculate how resources need to + be split + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to be adjusted wi= thin the socket. +**/ +EFI_STATUS +AdjustSocketIo ( + CPU_RESOURCE *SocketResources, + UINT8 ResourceType, + UINT8 ValidSockets +) +{ + UINT64 Base; ///< Next base I/O port = number to use + UINT64 Limit; ///< Most recent limit f= or I/O port numbers + CONST UINT64 MaxLimit =3D ((UINT64)1 << 16) - 1; ///< Maximum value for= limit; used to ensure we don't overflow + CPU_RESOURCE *CurSocketResources; ///< Pointer to the CPU_= RESOURE structure for the CPU we + ///< are examining + STACK_RESOURCE *CurStackResources; ///< Pointer to the STAC= K_RESOURCE structure for the CPU/Stack + ///< we are examining + UINT16 NumFreePorts; ///< Number of i/o ports= allocated to sockets that are not used + UINT8 LastStack; ///< Last enabled stack = of the last enabled socket + CONST UINT8 LastSocketIndex =3D ValidSockets - 1; ///< Index of the last= socket + UINT64 TotalResourceSize; + UINT64 ResourceSize; + UINT8 Socket; ///< Loop variable used = to iterate over the sockets + UINT8 Stack; ///< Loop variable used = to iterate over the stacks of a given socket + + NumFreePorts =3D 0; + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + CurSocketResources =3D &SocketResources[Socket]; + if (CurSocketResources->IoResourceNeeds =3D=3D 0 && CurSocketResources= ->IoResourcesLeft !=3D 0) { + ASSERT (NumFreePorts < NumFreePorts + CurSocketResources->IoResource= sLeft + 1); // check for overflow + NumFreePorts +=3D CurSocketResources->IoResourcesLeft + 1; + CurSocketResources->IoResourcesLeft =3D 0; + } + } + + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + CurSocketResources =3D &SocketResources[Socket]; + if (CurSocketResources->IoResourceNeeds !=3D 0 && NumFreePorts >=3D Cu= rSocketResources->IoResourceNeeds) { + ASSERT (NumFreePorts > NumFreePorts - CurSocketResources->IoResource= Needs); // check for underflow + NumFreePorts -=3D CurSocketResources->IoResourceNeeds; + CurSocketResources->IoResourceNeeds =3D 0; + } + } + + LastStack =3D LastStackOfSocket (LastSocketIndex); + + if (NumFreePorts > 0) { + CurStackResources =3D &SocketResources[LastSocketIndex].StackRes[LastS= tack]; + if (CurStackResources->NumIoPortsDesired !=3D 0) { + CurStackResources->NumIoPortsDesired +=3D NumFreePorts; + } else { + CurStackResources->NumIoPortsDesired +=3D NumFreePorts - 1; + } + } + + // + // Verify all resource requested can fit into the systems address range. + // + TotalResourceSize =3D 0; + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + LastStackWithResources (&SocketResources[Socket], Socket, ResourceType= , &LastStack, &ResourceSize); + TotalResourceSize +=3D ResourceSize; + } + DEBUG ((DEBUG_INFO, "Total Request IO Range =3D %xh\n", TotalResourceSiz= e)); + DEBUG ((DEBUG_INFO, "Total System IO Range =3D %xh\n", MaxLimit)); + if (TotalResourceSize > MaxLimit) { + // + // Not enough system resources to support the request. + // Remove all request to update NVRAM variable for this resource type. + // + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + SocketResources[Socket].StackRes[Stack].NeedIoUpdate =3D 0; + } + } + DEBUG ((DEBUG_ERROR, "ERROR: Out of adjustable IO resources. Can't adj= ust across sockets\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG((DEBUG_ERROR, "Assigning new socket i/o range...\n")); + + Base =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[0].PciResourceIoB= ase; + Limit =3D Base; // assume no resources are allocated + for (Socket =3D 0, CurSocketResources =3D SocketResources; Socket < Vali= dSockets; Socket++, CurSocketResources++) { + DEBUG ((DEBUG_INFO, "socket =3D %d, Base =3D %x, Limit =3D%x, MaxLimit= =3D %x\n", Socket, Base, Limit, MaxLimit)); + ASSERT (Base < MaxLimit); + CurSocketResources->IoBase =3D (UINT16)Base; + DEBUG ((DEBUG_INFO, "set socket io base to %x\n", Base)); + + for (Stack =3D 0, CurStackResources =3D CurSocketResources->StackRes; + Stack < MAX_IIO_STACK; + Stack++, CurStackResources++) { + if (!IsStackPresent (Socket, Stack)) { + DEBUG ((DEBUG_INFO, " Stack %d not present, setting base/limit to= 0xffff/0\n", Stack)); + CurStackResources->IoBase =3D 0xffff; + CurStackResources->IoLimit =3D 0; + continue; + } + + if (CurStackResources->NumIoPortsDesired =3D=3D 0) { + DEBUG ((DEBUG_INFO, " Stack %d doesn't need i/o resources, settin= g base/limit to 0xffff/0\n", Stack)); + CurStackResources->IoBase =3D 0xffff; + CurStackResources->IoLimit =3D 0; + CurStackResources->NeedIoUpdate =3D TRUE; + continue; + } + + DEBUG((DEBUG_INFO, " Stack %d setting i/o base to %x, ports desired= was %x\n", + Stack, Base, CurStackResources->NumIoPortsDesired)); + ASSERT (Base < MaxLimit); + CurStackResources->IoBase =3D (UINT16)Base; + Limit =3D Base + CurStackResources->NumIoPortsDesired; + DEBUG ((DEBUG_INFO, " limit set to %x (var and stack)\n", Limit)); + ASSERT (Base <=3D Limit); + ASSERT (Limit <=3D MaxLimit); + CurStackResources->IoLimit =3D (UINT16)Limit; + CurStackResources->NeedIoUpdate =3D TRUE; + Base =3D Limit + 1; + DEBUG ((DEBUG_INFO, " Base variable updated to %x\n", Base)); + } + ASSERT (Limit <=3D MaxLimit); + DEBUG ((DEBUG_INFO, " Socket %d limit set to %x\n", Socket, Limit)); + CurSocketResources->IoLimit =3D (UINT16)Limit; + } + + DEBUG ((DEBUG_INFO, "Dumping new I/O requests\n")); + for (Socket =3D 0, CurSocketResources =3D SocketResources; Socket < Vali= dSockets; Socket++, CurSocketResources++) { + DEBUG((DEBUG_INFO, "socket %d %x/%x\n", Socket, CurSocketResources->Io= Base, CurSocketResources->IoLimit)); + for (Stack =3D 0, CurStackResources =3D CurSocketResources->StackRes; + Stack < MAX_IIO_STACK; + Stack++, CurStackResources++) { + DEBUG ((DEBUG_INFO, "%d/%d: %x/%x\n", Socket, Stack, CurStackResourc= es->IoBase, CurStackResources->IoLimit)); + } + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalanceMmio32.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/= Dxe/PciHostBridge/PciRebalanceMmio32.c new file mode 100644 index 0000000000..41975dee6f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= RebalanceMmio32.c @@ -0,0 +1,163 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#include "PciHostBridge.h" +#include "PciRootBridge.h" +#include "PciRebalance.h" + +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + + +/** + Adjust resource assignments among sockets to fit the low + MMIO resources (32-bit addresses) from the PCI(e) devices in the system + + @param[in,out] SocketResources - CPU_RESOURCE structure pointer that sto= res all resources need per socket + @param[in] ResourceType - Type of resource that requires alignment + @param[in] ValidSockets - Number of Valid Sockets, need it to cal= culate how resources need to be splitted + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to be adjusted wi= thin the socket. + */ +EFI_STATUS +AdjustSocketMmioL ( + IN OUT CPU_RESOURCE *SocketResources, + IN UINT8 ResourceType, + IN UINT8 ValidSockets + ) +{ + CONST UINT8 LastSocket =3D ValidSockets - 1; + UINT8 Socket; + UINT8 Stack; + UINT8 LastStack; + UINT64 Take; + UINT32 UboxMmioSize; + UINT64 ResourceSize; + UINT64 TotalResourceSize; + UINT32 TempMmioBase; + UINT32 TempMmioLimit; + + Take =3D 0; + UboxMmioSize =3D mIioUds->IioUdsPtr->PlatformData.UboxMmioSize; + // + // Get first and last MMIOL address + // + TempMmioBase =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base; + TempMmioLimit =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit; + // + // Find all the extra space left + // + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + if ((SocketResources[Socket].MmiolResourceNeeds =3D=3D 0) && (SocketRe= sources[Socket].MmiolResourcesLeft !=3D 0)) { + + Take +=3D SocketResources[Socket].MmiolResourcesLeft + 1; + SocketResources[Socket].MmiolResourcesLeft =3D 0; + } + } + // + // Give space to sockets that needs more space favoring first come first= served + // + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + if ((SocketResources[Socket].MmiolResourceNeeds !=3D 0) && (Take >=3D = SocketResources[Socket].MmiolResourceNeeds)) { + + Take -=3D SocketResources[Socket].MmiolResourceNeeds; + DEBUG((DEBUG_ERROR, "SocketResources[%x].MmiolResourceNeeds =3D %x\n= ", Socket, SocketResources[Socket].MmiolResourceNeeds)); + SocketResources[Socket].MmiolResourceNeeds =3D 0; + } + } + // + // Give away leftover resources + // + LastStack =3D LastStackOfSocket (LastSocket); + if (Take !=3D 0) { + if (SocketResources[LastSocket].StackRes[LastStack].MmiolLength !=3D 0= ) { + SocketResources[LastSocket].StackRes[LastStack].MmiolLength +=3D (UI= NT32)Take; + } else{ + SocketResources[LastSocket].StackRes[LastStack].MmiolLength +=3D ((U= INT32)Take - 1); + } + } + // + // Verify all resource requested can fit into the systems address range. + // + TotalResourceSize =3D 0; + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + LastStackWithResources (&SocketResources[Socket], Socket, ResourceType= , &LastStack, &ResourceSize); + TotalResourceSize +=3D ResourceSize + UboxMmioSize; + } + DEBUG ((DEBUG_INFO, "Total Request MMIOL Range =3D %08Xh\n", TotalResour= ceSize)); + DEBUG ((DEBUG_INFO, "Total System MMIOL Range =3D %08Xh\n", (TempMmioLi= mit - TempMmioBase + 1))); + if (TotalResourceSize > (TempMmioLimit - TempMmioBase + 1)) { + // + // Not enough system resources to support the request. + // Remove all request to update NVRAM variable for this resource type. + // + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + SocketResources[Socket].StackRes[Stack].MmiolUpdate =3D 0; + } + } + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Out of adjustable MMIOL resources. = Can't adjust across sockets\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_ERROR, "Assigning new socket MMIOL range...\n")); + for (Socket =3D 0, TempMmioLimit =3D TempMmioBase - 1; Socket < ValidSoc= kets; Socket ++) { + + SocketResources[Socket].MmiolBase =3D TempMmioLimit + 1; + // + // Update the stacks base and limit values. + // + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack))) { + + SocketResources[Socket].StackRes[Stack].MmiolBase =3D 0; + SocketResources[Socket].StackRes[Stack].MmiolLimit =3D 0; + + } else { + + SocketResources[Socket].StackRes[Stack].MmiolBase =3D TempMmioLimi= t + 1; + if (SocketResources[Socket].StackRes[Stack].MmiolLength !=3D 0) { + // + // MmiolLength is actually length-1, so we should move TempMmioL= imit by MmiolLength+1, + // but only when it is >0, i.e. only for stack that has resource= s. + // + TempMmioLimit +=3D SocketResources[Socket].StackRes[Stack].Mmiol= Length + 1; + SocketResources[Socket].StackRes[Stack].MmiolLimit =3D TempMmioL= imit; + + } else { + + SocketResources[Socket].StackRes[Stack].MmiolLimit =3D SocketRes= ources[Socket].StackRes[Stack].MmiolBase; + } + SocketResources[Socket].StackRes[Stack].MmiolUpdate =3D 1; + } + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiolBase = =3D %X newLength =3D %x\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiolBase, SocketRes= ources[Socket].StackRes[Stack].MmiolLength)); + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiolLimit = =3D %X\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiolLimit)); + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiolUpdate= =3D %d\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiolUpdate)); + } // for (Stack...) + // + // In the socket resources there can be UBOX, unfortunatelly not expos= ed in stackPresentBitmap + // so it has to be handled with such uguly hacks. + // + TempMmioLimit +=3D UboxMmioSize; + SocketResources[Socket].MmiolLimit =3D TempMmioLimit; + } // for (Socket...) + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalanceMmio64.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/= Dxe/PciHostBridge/PciRebalanceMmio64.c new file mode 100644 index 0000000000..0101904285 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= RebalanceMmio64.c @@ -0,0 +1,204 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#include "PciHostBridge.h" +#include "PciRootBridge.h" +#include "PciRebalance.h" + + +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + + +/** + Adjust resource assignments among sockets to fit the high + MMIO resources (64-bit addresses, typically above 4GB) from + the PCI(e) devices in the system + + @param[in,out] SocketResources - CPU_RESOURCE structure pointer that sto= res all resources need per socket + @param[in] ResourceType - Type of resource that requires alignment + @param[in] ValidSockets - Number of Valid Sockets, need it to cal= culate how resources need to be splitted + + @retval EFI_SUCCESS - Succeed. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to be adjusted wi= thin the socket. + */ +EFI_STATUS +AdjustSocketMmioH ( + IN OUT CPU_RESOURCE *SocketResources, + IN UINT8 ResourceType, + IN UINT8 ValidSockets + ) +{ + CONST UINT8 LastSocket =3D ValidSockets - 1; + UINT8 Socket; + UINT8 Stack; + UINT8 LastStack; + UINT64 Take; + UINT32 UboxMmioSize; + UINT64 UnAllocatedMmioh; + UINT64 MaxMmioh; + UINT64 ResourceSize; + UINT64 TotalResourceSize; + UINT64 TempMmioBase; + UINT64 TempMmioLimit; + + Take =3D 0; + UboxMmioSize =3D mIioUds->IioUdsPtr->PlatformData.UboxMmioSize; + UnAllocatedMmioh =3D 0; + // + // Get first and last IO base address + // + TempMmioBase =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base; + TempMmioLimit =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit; + + // Find all the extra space left + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + if ((SocketResources[Socket].MmiohResourceNeeds =3D=3D 0) && (SocketRe= sources[Socket].MmiohResourcesLeft !=3D 0)) { + + Take +=3D SocketResources[Socket].MmiohResourcesLeft + 1; + SocketResources[Socket].MmiohResourcesLeft =3D 0; + } + } + + MaxMmioh =3D (UINT64) mIioUds->IioUdsPtr->PlatformData.MmiohGranularity.= lo; + MaxMmioh |=3D ((UINT64) mIioUds->IioUdsPtr->PlatformData.MmiohGranularit= y.hi) << 32; + // + // Maximum chunk accessible in the system based on the given granularity + // + if (UboxMmioSize =3D=3D 0) { + MaxMmioh =3D MaxMmioh * 32; //for 14nm + } else { + MaxMmioh =3D ((UINT64) 1 << mIioUds->IioUdsPtr->PlatformData.MaxAddres= sBits); + } + + // + // Find out how much MMIOH has not been allocated + // + if (MaxMmioh > (TempMmioLimit - TempMmioBase)) { + UnAllocatedMmioh =3D MaxMmioh - (TempMmioLimit - TempMmioBase) - 1; + } else { + // + // Extra MMIOH is not enough to close the gap for a successful adjustm= ent. + // Use all extra MMIOH in case if only a small amount is needed for ad= justment or + // the granularity was reduced due to MMIOH base. + // (14nm only) or remove if map is rejected for this case to start ove= r with correct values. + // (10nm only) does not have this problem and doesn't need the code be= low because the limit is removed and we can use max address lines. + // + Take +=3D MaxMmioh; + } + + // Give space to sockets that needs more space favoring first come first= served + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + if ((SocketResources[Socket].MmiohResourceNeeds !=3D 0) && (Take >=3D = SocketResources[Socket].MmiohResourceNeeds)) { + // + // The socket requesting additional resources can be granted by usin= g the already + // allocated range given to the whole system originally. + // + Take -=3D SocketResources[Socket].MmiohResourceNeeds; + DEBUG ((DEBUG_ERROR, "SocketResources[%x].MmiohResourceNeeds =3D %ll= X\n",Socket, SocketResources[Socket].MmiohResourceNeeds)); + SocketResources[Socket].MmiohResourceNeeds =3D 0; + } else if ((SocketResources[Socket].MmiohResourceNeeds !=3D 0) && + (Take < SocketResources[Socket].MmiohResourceNeeds) && + ((UnAllocatedMmioh + Take) >=3D SocketResources[Socket].Mmi= ohResourceNeeds)) { + // + // Apply unallocated Mmioh to the socket that requires more to satis= fy its request + // that's outside the allocated range given to the whole system orig= inally. + // + SocketResources[Socket].MmiohResourceNeeds -=3D Take; + UnAllocatedMmioh -=3D SocketResources[Socket].MmiohResourceNeeds; + DEBUG ((DEBUG_INFO, "SocketResources[%x].MmiohResourceNeeds =3D %llX= \n", Socket, SocketResources[Socket].MmiohResourceNeeds)); + DEBUG ((DEBUG_INFO, "Unallocated MMIOH left =3D %llX\n", UnAllocated= Mmioh)); + SocketResources[Socket].MmiohResourceNeeds =3D 0; + } + } + // + // Give away leftover resources + // + LastStack =3D LastStackOfSocket (LastSocket); + if (Take !=3D 0) { + if (SocketResources[LastSocket].StackRes[LastStack].MmiohLength !=3D 0= ) { + SocketResources[LastSocket].StackRes[LastStack].MmiohLength +=3D Tak= e; + } else{ + SocketResources[LastSocket].StackRes[LastStack].MmiohLength +=3D (Ta= ke - 1); + } + } + // + // Verify all resource requested can fit into the systems address range. + // + TotalResourceSize =3D 0; + for (Socket =3D 0; Socket < ValidSockets; Socket++) { + LastStackWithResources (&SocketResources[Socket], Socket, ResourceType= , &LastStack, &ResourceSize); + TotalResourceSize +=3D ResourceSize; + } + DEBUG ((DEBUG_INFO, "MaxMmioh =3D %016llXh\n", MaxMmioh)= ); + DEBUG ((DEBUG_INFO, "Total Request MMIOH Range=3D %016llXh\n", TotalReso= urceSize)); + DEBUG ((DEBUG_INFO, "Total System MMIOH Range =3D %016llXh\n", (MaxMmioh= - TempMmioBase))); + if (TotalResourceSize > MaxMmioh) { + // + // Not enough system resources to support the request. + // Remove all request to update NVRAM variable for this resource type. + // + for (Socket =3D 0; Socket < ValidSockets; Socket ++) { + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack ++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { + continue; + } + SocketResources[Socket].StackRes[Stack].MmiohUpdate =3D 0; + } + } + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Out of adjustable MMIOH resources. = Can't adjust across sockets\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_ERROR, "Assigning new socket MMIOH range...\n")); + for (Socket =3D 0, TempMmioLimit =3D TempMmioBase - 1; Socket < ValidSoc= kets; Socket++) { + + SocketResources[Socket].MmiohBase =3D TempMmioLimit + 1; + // + // Update the stacks base and limit values. + // + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack))) { + + SocketResources[Socket].StackRes[Stack].MmiohBase =3D 0; + SocketResources[Socket].StackRes[Stack].MmiohLimit =3D 0; + + } else { + + SocketResources[Socket].StackRes[Stack].MmiohBase =3D TempMmioLimi= t + 1; + if (SocketResources[Socket].StackRes[Stack].MmiohLength !=3D 0) { + // + // MmiohLength is actually length-1, so we should move TempMmioL= imit by MmiohLength+1, + // but only when it is >0, i.e. only for stack that has resource= s. + // + TempMmioLimit +=3D SocketResources[Socket].StackRes[Stack].Mmioh= Length + 1; + SocketResources[Socket].StackRes[Stack].MmiohLimit =3D TempMmioL= imit; + + } else { + + SocketResources[Socket].StackRes[Stack].MmiohLimit =3D SocketRes= ources[Socket].StackRes[Stack].MmiohBase; + } + SocketResources[Socket].StackRes[Stack].MmiohUpdate =3D 1; + } + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiohBase = =3D %llX newLength =3D %llX\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiohBase, SocketRes= ources[Socket].StackRes[Stack].MmiohLength)); + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiohLimit = =3D %llX\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiohLimit)); + DEBUG ((DEBUG_ERROR, "SocketResources[%x].StackRes[%x].MmiohUpdate= =3D %d\n", Socket, Stack, + SocketResources[Socket].StackRes[Stack].MmiohUpdate)); + } // for (Stack...) + + SocketResources[Socket].MmiohLimit =3D TempMmioLimit; + } // for (Socket...) + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRootBridge.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/P= ciHostBridge/PciRootBridge.h new file mode 100644 index 0000000000..54faf82e98 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= RootBridge.h @@ -0,0 +1,573 @@ +/** @file + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_ROOT_BRIDGE_H_ +#define _PCI_ROOT_BRIDGE_H_ + +#include +#include +#include + +// +// Driver Consumed Protocol Prototypes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PciHostResource.h" + + +// +// Define resource status constant +// +typedef struct { + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS MappedHostAddress; +} MAP_INFO; + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_HANDLE Handle; + UINT64 AllocationAttributes; + UINT64 Attributes; + UINT64 Supports; + PCI_RES_NODE ResAllocNode[TypeMax]; + PCI_ROOT_BRIDGE_RESOURCE_APERTURE Aperture; + EFI_LOCK PciLock; + UINTN PciAddress; + UINTN PciData; + UINT32 HecBase; + UINT32 HecLen; + UINTN BusScanCount; + BOOLEAN BusNumberAssigned; + BOOLEAN DmaAbove4G; + VOID *ConfigBuffer; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL RootBridgeIo; +} PCI_ROOT_BRIDGE_INSTANCE; + +#define ROOT_BRIDGE_FROM_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, RootBrid= geIo, PCI_ROOT_BRIDGE_SIGNATURE) + +#define ROOT_BRIDGE_FROM_LINK(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PC= I_ROOT_BRIDGE_SIGNATURE) + +/** + Construct the Pci Root Bridge Io protocol. + + @param[out] Protocol - Protocol to initialize. + @param[in] HostBridgeHandle - Handle to the HostBridge. + @param[in] ResAperture - Resource apperture of the root bridge. + @param[in] SegmentNumber - PCI segment of this root bridge + @param[in] AllocAttributes - Attribute of resouce allocated. + + @retval EFI_SUCCESS - Success. + @retval Others - Fail. +**/ +EFI_STATUS +SimpleIioRootBridgeConstructor ( + OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture, + IN UINT16 SegmentNumber, + IN UINT64 AllocAttributes + ); + +// +// Protocol Member Function Prototypes +// +/** + + Poll an address in memory mapped space until an exit condition is met + or a timeout occurs. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param Width - Width of the memory operation. + @param Address - The base address of the memory operation. + @param Mask - Mask used for polling criteria. + @param Value - Comparison value used for polling exit criteria. + @param Delay - Number of 100ns units to poll. + @param Result - Pointer to the last value read from memory location. + + @retval EFI_SUCCESS - Success. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + @retval EFI_TIMEOUT - Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +; + +/** + + Poll an address in I/O space until an exit condition is met + or a timeout occurs. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param Width - Width of I/O operation. + @param Address - The base address of the I/O operation. + @param Mask - Mask used for polling criteria. + @param Value - Comparison value used for polling exit criteria. + @param Delay - Number of 100ns units to poll. + @param Result - Pointer to the last value read from memory location. + + @retval EFI_SUCCESS - Success. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + @retval EFI_TIMEOUT - Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +; + +/** + + Allow read from memory mapped I/O space. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param Width - The width of memory operation. + @param Address - Base address of the memory operation. + @param Count - Number of memory opeartion to perform. + @param Buffer - The destination buffer to store data. + + @retval EFI_SUCCESS - Success. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + @retval EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +; + +/** + + Allow write to memory mapped I/O space. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param Width - The width of memory operation. + @param Address - Base address of the memory operation. + @param Count - Number of memory opeartion to perform. + @param Buffer - The source buffer to write data from. + + @retval EFI_SUCCESS - Success. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + @retval EFI_OUT_OF_RESOURCES - Fail due to lack of resources. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +; + +/** + + Enable a PCI driver to read PCI controller registers in the + PCI root bridge I/O space. + + @param This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width - Signifies the width of the memory operation. + @param UserAddress - The base address of the I/O operation. + @param Count - The number of I/O operations to perform. + @param UserBuffer - The destination buffer to store the results. + + @retval EFI_SUCCESS - The data was read from the PCI root br= idge. + @retval EFI_INVALID_PARAMETER - Invalid parameters found. + @retval EFI_OUT_OF_RESOURCES - The request could not be completed due= to a lack of + @retval resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +; + +/** + + Enable a PCI driver to write to PCI controller registers in the + PCI root bridge I/O space. + + @param This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width - Signifies the width of the memory operation. + @param UserAddress - The base address of the I/O operation. + @param Count - The number of I/O operations to perform. + @param UserBuffer - The source buffer to write data from. + + @retval EFI_SUCCESS - The data was written to the PCI root b= ridge. + @retval EFI_INVALID_PARAMETER - Invalid parameters found. + @retval EFI_OUT_OF_RESOURCES - The request could not be completed due= to a lack of + @retval resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +; + +/** + + Copy one region of PCI root bridge memory space to be copied to + another region of PCI root bridge memory space. + + @param This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL inst= ance. + @param Width - Signifies the width of the memory operation. + @param DestAddress - Destination address of the memory operation. + @param SrcAddress - Source address of the memory operation. + @param Count - Number of memory operations to perform. + + @retval EFI_SUCCESS - The data was copied successfully. + @retval EFI_INVALID_PARAMETER - Invalid parameters found. + @retval EFI_OUT_OF_RESOURCES - The request could not be completed due= to a lack of + @retval resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ) +; + +/** + + Allows read from PCI configuration space. + + @param This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width - Signifies the width of the memory operation. + @param Address - The address within the PCI configuration space + for the PCI controller. + @param Count - The number of PCI configuration operations + to perform. + @param Buffer - The destination buffer to store the results. + + @retval EFI_SUCCESS - The data was read from the PCI root br= idge. + @retval EFI_INVALID_PARAMETER - Invalid parameters found. + @retval EFI_OUT_OF_RESOURCES - The request could not be completed due= to a lack of + @retval resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +; + +/** + + Allows write to PCI configuration space. + + @param This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width - Signifies the width of the memory operation. + @param Address - The address within the PCI configuration space + for the PCI controller. + @param Count - The number of PCI configuration operations + to perform. + @param Buffer - The source buffer to get the results. + + @retval EFI_SUCCESS - The data was written to the PCI root b= ridge. + @retval EFI_INVALID_PARAMETER - Invalid parameters found. + @retval EFI_OUT_OF_RESOURCES - The request could not be completed due= to a lack of + @retval resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +; + +/** + Provides the PCI controller-specific address needed to access + system memory for DMA. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Operation Indicate if the bus master is going to read or wri= te + to system memory. + @param HostAddress The system memory address to map on the PCI contro= ller. + @param NumberOfBytes On input the number of bytes to map. + On output the number of bytes that were mapped. + @param DeviceAddress The resulting map address for the bus master PCI + controller to use to access the system memory's Ho= stAddress. + @param Mapping The value to pass to Unmap() when the bus master D= MA + operation is complete. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameters found. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a com= mon buffer. + @retval EFI_DEVICE_ERROR The System hardware could not map the req= uested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +; + +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any + corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target sys= tem + memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target = system memory. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ) +; + +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonB= uffer + or EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of = the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated + range. Only the attributes + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, + EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and + EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with= this + function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal + attribute bits are MEMORY_WRITE_COMBINE, + MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +; + +/** + + Free memory allocated in AllocateBuffer. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + @param Pages - Number of pages to free. + @param HostAddress - The base system memory address of the + allocated range. + + @retval EFI_SUCCESS - Requested memory pages were freed. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ) +; + +/** + + Flushes all PCI posted write transactions from a PCI host + bridge to system memory. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + + @retval EFI_SUCCESS - PCI posted write transactions were flushed + @retval from PCI host bridge to system memory. + @retval EFI_DEVICE_ERROR - Fail due to hardware error. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ) +; + +/** + Gets the attributes that a PCI root bridge supports setting with + SetAttributes(), and the attributes that a PCI root bridge is currently + using. + + The GetAttributes() function returns the mask of attributes that this PCI + root bridge supports and the mask of attributes that the PCI root bridge= is + currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root + bridge supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root + bridge is currently using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attribu= tes + that the PCI root bridge supports is retu= rned + in Supports. If Attributes is not NULL, t= hen + the attributes that the PCI root bridge is + currently using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ) +; + +/** + + Sets the attributes for a resource range on a PCI root bridge. + + @param This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL ins= tance. + @param Attributes - The mask of attributes to set. + @param ResourceBase - Pointer to the base address of the resource ra= nge + to be modified by the attributes specified by = Attributes. + @param ResourceLength - Pointer to the length of the resource range to= be modified. + + @retval EFI_SUCCESS - Success. + @retval EFI_INVALID_PARAMETER - Invalid parameter found. + @retval EFI_OUT_OF_RESOURCES - Not enough resources to set the attrib= utes upon. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ) +; + +/** + + Retrieves the current resource settings of this PCI root bridge + in the form of a set of ACPI resource descriptor. + + @param This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL inst= ance. + @param Resources - Pointer to the resource descriptor that + describe the current configuration of this PCI root + bridge. + + @retval EFI_SUCCESS - Success. + @retval EFI_UNSUPPORTED - Current configuration of the PCI root bridge + @retval could not be retrieved. + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ) +; + +extern EFI_CPU_IO2_PROTOCOL *mCpuIo; +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRootBridgeIo.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe= /PciHostBridge/PciRootBridgeIo.c new file mode 100644 index 0000000000..ed5fb7e4a3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= RootBridgeIo.c @@ -0,0 +1,1664 @@ +/** @file + IIO PCI Root Bridge Io Protocol code. Generic enough to work for all IIO= s. + Does not support configuration accesses to the extended PCI Express regi= sters yet. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PciHostBridge.h" +#include "PciRootBridge.h" + +#include +#include + +#include "PciRebalance.h" + +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + + +// +// Pci Root Bridge Io Module Variables +// +EFI_CPU_IO2_PROTOCOL *mCpuIo; +STATIC DYNAMIC_SI_LIBARY_PROTOCOL *mDynamicSiLibraryProtocol; + +/** + Construct the Pci Root Bridge Io protocol. + + @param[out] Protocol - Protocol to initialize. + @param[in] HostBridgeHandle - Handle to the HostBridge. + @param[in] ResAperture - Resource apperture of the root bridge. + @param[in] SegmentNumber - PCI segment of this root bridge + @param[in] AllocAttributes - Attribute of resouce allocated. + + @retval EFI_SUCCESS - Success. + @retval Others - Fail. +**/ +EFI_STATUS +SimpleIioRootBridgeConstructor ( + OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture, + IN UINT16 SegmentNumber, + IN UINT64 AllocAttributes + ) +{ + EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + PCI_RESOURCE_TYPE Index; + UINT32 HecBase; + UINT32 HecSize; + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (Protocol); + + // + // Initialize the apertures with default values + // + CopyMem ( + &RootBridge->Aperture, + ResAperture, + sizeof (PCI_ROOT_BRIDGE_RESOURCE_APERTURE) + ); + + for (Index =3D TypeIo; Index < TypeMax; Index++) { + RootBridge->ResAllocNode[Index].Type =3D Index; + RootBridge->ResAllocNode[Index].Base =3D 0; + RootBridge->ResAllocNode[Index].Length =3D 0; + RootBridge->ResAllocNode[Index].Status =3D ResNone; + } + + EfiInitializeLock (&RootBridge->PciLock, TPL_HIGH_LEVEL); + RootBridge->PciAddress =3D 0xCF8; + RootBridge->PciData =3D 0xCFC; + + RootBridge->AllocationAttributes =3D AllocAttributes; + RootBridge->Attributes =3D 0; + RootBridge->Supports =3D EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_MEMORY | + EFI_PCI_ATTRIBUTE_VGA_IO_16; + + // + // Don't support BASE above 4GB currently + // Position to bit 39:28 + // + HecBase =3D (UINT32) mIioUds->IioUdsPtr->PlatformData.PciExpressBase; + HecSize =3D (UINT32) mIioUds->IioUdsPtr->PlatformData.PciExpressSize; + ASSERT (HecBase !=3D 0); + + RootBridge->HecBase =3D HecBase; + RootBridge->HecLen =3D HecSize; + + RootBridge->BusNumberAssigned =3D FALSE; + RootBridge->BusScanCount =3D 0; + + Protocol->ParentHandle =3D HostBridgeHandle; + + Protocol->PollMem =3D RootBridgeIoPollMem; + Protocol->PollIo =3D RootBridgeIoPollIo; + + Protocol->Mem.Read =3D RootBridgeIoMemRead; + Protocol->Mem.Write =3D RootBridgeIoMemWrite; + + Protocol->Io.Read =3D RootBridgeIoIoRead; + Protocol->Io.Write =3D RootBridgeIoIoWrite; + + Protocol->CopyMem =3D RootBridgeIoCopyMem; + + Protocol->Pci.Read =3D RootBridgeIoPciRead; + Protocol->Pci.Write =3D RootBridgeIoPciWrite; + + Protocol->Map =3D RootBridgeIoMap; + Protocol->Unmap =3D RootBridgeIoUnmap; + + Protocol->AllocateBuffer =3D RootBridgeIoAllocateBuffer; + Protocol->FreeBuffer =3D RootBridgeIoFreeBuffer; + + Protocol->Flush =3D RootBridgeIoFlush; + + Protocol->GetAttributes =3D RootBridgeIoGetAttributes; + Protocol->SetAttributes =3D RootBridgeIoSetAttributes; + + Protocol->Configuration =3D RootBridgeIoConfiguration; + + Protocol->SegmentNumber =3D SegmentNumber; + + Status =3D gBS->LocateProtocol ( + &gEfiCpuIo2ProtocolGuid, + NULL, + &mCpuIo + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &m= DynamicSiLibraryProtocol); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + Return the result of (Multiplicand * Multiplier / Divisor). + + @param Multiplicand A 64-bit unsigned value. + @param Multiplier A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + @param Remainder A pointer to a 32-bit unsigned value. This parameter= is + optional and may be NULL. + + @return Multiplicand * Multiplier / Divisor. +**/ +UINT64 +MultThenDivU64x64x32 ( + IN UINT64 Multiplicand, + IN UINT64 Multiplier, + IN UINT32 Divisor, + OUT UINT32 *Remainder OPTIONAL + ) +{ + UINT64 Uint64; + UINT32 LocalRemainder; + UINT32 Uint32; + if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) { + // + // Make sure Multiplicand is the bigger one. + // + if (Multiplicand < Multiplier) { + Uint64 =3D Multiplicand; + Multiplicand =3D Multiplier; + Multiplier =3D Uint64; + } + // + // Because Multiplicand * Multiplier overflows, + // Multiplicand * Multiplier / Divisor + // =3D (2 * Multiplicand' + 1) * Multiplier / Divisor + // =3D 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divis= or + // + Uint64 =3D MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multipli= er, Divisor, &LocalRemainder); + Uint64 =3D LShiftU64 (Uint64, 1); + Uint32 =3D 0; + if ((Multiplicand & 0x1) =3D=3D 1) { + Uint64 +=3D DivU64x32Remainder (Multiplier, Divisor, &Uint32); + } + return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder= , 1), Divisor, Remainder); + } else { + return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divi= sor, Remainder); + } +} + +/** + Return the elapsed tick count from CurrentTick. + + @param CurrentTick On input, the previous tick count. + On output, the current tick count. + @param StartTick The value the performance counter starts with when = it + rolls over. + @param EndTick The value that the performance counter ends with be= fore + it rolls over. + + @return The elapsed tick count from CurrentTick. +**/ +UINT64 +GetElapsedTick ( + UINT64 *CurrentTick, + UINT64 StartTick, + UINT64 EndTick + ) +{ + UINT64 PreviousTick; + + PreviousTick =3D *CurrentTick; + *CurrentTick =3D GetPerformanceCounter(); + if (StartTick < EndTick) { + return *CurrentTick - PreviousTick; + } else { + return PreviousTick - *CurrentTick; + } +} + +/** + Polls an address in memory mapped I/O space until an exit condition is m= et, + or a timeout occurs. + + This function provides a standard way to poll a PCI memory location. A P= CI + memory read operation is performed at the PCI memory address specified by + Address for the width specified by Width. The result of this PCI memory = read + operation is stored in Result. This PCI memory read operation is repeated + until either a timeout of Delay 100 ns units has expired, or (Result & M= ask) + is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the memory operations. The ca= ller + is responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above W= idth + in Mask are ignored. The bits in the bytes below = Width + which are zero in Mask are ignored when polling t= he + memory address. + @param[in] Value The comparison value used for the polling exit + criteria. + @param[in] Delay The number of 100 ns units to poll. Note that tim= er + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory + location. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + UINT64 StartTick; + UINT64 EndTick; + UINT64 CurrentTick; + UINT64 ElapsedTick; + UINT64 Frequency; + + if (Result =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ((UINT32)Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + // + // No matter what, always do a single poll. + // + Status =3D This->Mem.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + if (Delay =3D=3D 0) { + return EFI_SUCCESS; + + } else { + // + // NumberOfTicks =3D Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1) + // + Frequency =3D GetPerformanceCounterProperties (&StartTick, &EndTic= k); + NumberOfTicks =3D MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_= TIMER_PERIOD_SECONDS(1), &Remainder); + if (Remainder >=3D (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) { + NumberOfTicks++; + } + for ( ElapsedTick =3D 0, CurrentTick =3D GetPerformanceCounter() + ; ElapsedTick <=3D NumberOfTicks + ; ElapsedTick +=3D GetElapsedTick (&CurrentTick, StartTick, EndTic= k) + ) { + Status =3D This->Mem.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + } + } + return EFI_TIMEOUT; +} + +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the + polling exit criteria is satisfied or after a defined duration. + + This function provides a standard way to poll a PCI I/O location. A PCI = I/O + read operation is performed at the PCI I/O address specified by Address = for + the width specified by Width. + The result of this PCI I/O read operation is stored in Result. This PCI = I/O + read operation is repeated until either a timeout of Delay 100 ns units = has + expired, or (Result & Mask) is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller = is + responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Wid= th in + Mask are ignored. The bits in the bytes below Width + which are zero in Mask are ignored when polling the= I/O + address. + @param[in] Value The comparison value used for the polling exit crit= eria. + @param[in] Delay The number of 100 ns units to poll. Note that timer + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory loca= tion. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + UINT64 StartTick; + UINT64 EndTick; + UINT64 CurrentTick; + UINT64 ElapsedTick; + UINT64 Frequency; + + // + // No matter what, always do a single poll. + // + + if (Result =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ((UINT32)Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + Status =3D This->Io.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + if (Delay =3D=3D 0) { + return EFI_SUCCESS; + + } else { + // + // NumberOfTicks =3D Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1) + // + Frequency =3D GetPerformanceCounterProperties (&StartTick, &EndTic= k); + NumberOfTicks =3D MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_= TIMER_PERIOD_SECONDS(1), &Remainder); + if (Remainder >=3D (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) { + NumberOfTicks++; + } + for ( ElapsedTick =3D 0, CurrentTick =3D GetPerformanceCounter() + ; ElapsedTick <=3D NumberOfTicks + ; ElapsedTick +=3D GetElapsedTick (&CurrentTick, StartTick, EndTic= k) + ) { + Status =3D This->Io.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + } + } + return EFI_TIMEOUT; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 ||Width >=3D EfiPciWidthMaximum ) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + // + // Check memory access limit + // + if (RootBridge->Aperture.Mem64Limit > RootBridge->Aperture.Mem64Base) { + if (Address > RootBridge->Aperture.Mem64Limit) { + return EFI_INVALID_PARAMETER; + } + } else { + if (Address > RootBridge->Aperture.Mem32Limit) { + return EFI_INVALID_PARAMETER; + } + } + + return mCpuIo->Mem.Read ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >=3D EfiPciWidthMaximum ) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // + // Check memory access limit + // + if (RootBridge->Aperture.Mem64Limit > RootBridge->Aperture.Mem64Base) { + if (Address > RootBridge->Aperture.Mem64Limit) { + return EFI_INVALID_PARAMETER; + } + } else { + if (Address > RootBridge->Aperture.Mem32Limit) { + return EFI_INVALID_PARAMETER; + } + } + return mCpuIo->Mem.Write ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINTN AlignMask; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >=3D EfiPciWidthMaximum ) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // + // AlignMask =3D (1 << Width) - 1; + // + AlignMask =3D (1 << (Width & 0x03)) - 1; + + // + // check Io access limit + // + if (Address > RootBridge->Aperture.IoLimit) { + return EFI_INVALID_PARAMETER; + } + + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + return mCpuIo->Io.Read ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); + +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINTN AlignMask; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >=3D EfiPciWidthMaximum ) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // + // AlignMask =3D (1 << Width) - 1; + // + AlignMask =3D (1 << (Width & 0x03)) - 1; + + // + // Check Io access limit + // + if (Address > RootBridge->Aperture.IoLimit) { + return EFI_INVALID_PARAMETER; + } + + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + return mCpuIo->Io.Write ( + mCpuIo, + (EFI_CPU_IO_PROTOCOL_WIDTH) Width, + Address, + Count, + Buffer + ); + +} + +/** + Enables a PCI driver to copy one region of PCI root bridge memory space = to + another region of PCI root bridge memory space. + + The CopyMem() function enables a PCI driver to copy one region of PCI ro= ot + bridge memory space to another region of PCI root bridge memory space. T= his + is especially useful for video scroll operation on a memory mapped video + buffer. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI root bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] DestAddress The destination address of the memory operation. = The + caller is responsible for aligning the DestAddres= s if + required. + @param[in] SrcAddress The source address of the memory operation. The c= aller + is responsible for aligning the SrcAddress if + required. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at DestAddr= ess + and SrcAddress. + + @retval EFI_SUCCESS The data was copied from one memory reg= ion + to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ) +{ + EFI_STATUS Status; + BOOLEAN Forward; + UINTN Stride; + UINTN Index; + UINT64 Result; + + if ((UINT32) Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + if (DestAddress =3D=3D SrcAddress) { + return EFI_SUCCESS; + } + + Stride =3D (UINTN)1 << Width; + + Forward =3D TRUE; + if ((DestAddress > SrcAddress) && + (DestAddress < (SrcAddress + Count * Stride))) { + Forward =3D FALSE; + SrcAddress =3D SrcAddress + (Count - 1) * Stride; + DestAddress =3D DestAddress + (Count - 1) * Stride; + } + + for (Index =3D 0; Index < Count; Index++) { + Status =3D RootBridgeIoMemRead ( + This, + Width, + SrcAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D RootBridgeIoMemWrite ( + This, + Width, + DestAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + if (Forward) { + SrcAddress +=3D Stride; + DestAddress +=3D Stride; + } else { + SrcAddress -=3D Stride; + DestAddress -=3D Stride; + } + } + return EFI_SUCCESS; +} + + +/** + +Arguments: + +**/ +STATIC +EFI_STATUS +RootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +{ + PCI_CONFIG_ACCESS_CF8 Pci; + PCI_CONFIG_ACCESS_CF8 PciAligned; + UINT32 Stride; + UINTN PciData; + UINTN PciDataStride; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Width >=3D EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + ASSERT (((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*)&UserAddress)->Ex= tendedRegister =3D=3D 0x00); + + Stride =3D 1 << Width; + + Pci.Bits.Reg =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAd= dress)->Register; + Pci.Bits.Func =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserA= ddress)->Function; + Pci.Bits.Dev =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAd= dress)->Device; + Pci.Bits.Bus =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAd= dress)->Bus; + Pci.Bits.Reserved =3D 0; + Pci.Bits.Enable =3D 1; + + // + // PCI Configure access are all 32-bit aligned, but by accessing the + // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types + // are possible on PCI. + // + // To read a byte of PCI configuration space you load 0xcf8 and + // read 0xcfc, 0xcfd, 0xcfe, 0xcff + // + PciDataStride =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserA= ddress)->Register & 0x03; + + while (Count) { + PciAligned =3D Pci; + PciAligned.Bits.Reg &=3D 0xfc; + PciData =3D RootBridge->PciData + PciDataStride; + EfiAcquireLock(&RootBridge->PciLock); + This->Io.Write (This, EfiPciWidthUint32, \ + RootBridge->PciAddress, 1, &PciAligned); + if (Write) { + This->Io.Write (This, Width, PciData, 1, UserBuffer); + } else { + This->Io.Read (This, Width, PciData, 1, UserBuffer); + } + EfiReleaseLock(&RootBridge->PciLock); + UserBuffer =3D ((UINT8 *)UserBuffer) + Stride; + PciDataStride =3D (PciDataStride + Stride) % 4; + Count -=3D 1; + + // + // Only increment the PCI address if Width is not a FIFO. + // + if (Width >=3D EfiPciWidthUint8 && Width <=3D EfiPciWidthUint64) { + Pci.Bits.Reg +=3D Stride; + } + } + return EFI_SUCCESS; +} + +/** + Allows read from PCI configuration space. + + @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width Signifies the width of the memory operation. + @param Address The address within the PCI configuration space + for the PCI controller. + @param Count The number of PCI configuration operations + to perform. + @param Buffer The destination buffer to store the results. + + @retval EFI_SUCCESS The data was read from the PCI root bridge. + @retval EFI_INVALID_PARAMETER Invalid parameters found. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFn; + UINT32 PciExtReg; + USRA_ADDRESS EndPointPciAddress; + UINT8 *pData8 =3D Buffer; + UINT8 Size; + + Size =3D 1 << (Width & 0x3); + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >=3D EfiPciWidthMaximum ) { + return EFI_INVALID_PARAMETER; + } + + // + // Read Pci configuration space + // + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + if (RootBridge->HecBase =3D=3D 0) { + return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); + } + + if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Extende= dRegister) { + PciExtReg =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addres= s)->Register; + } else { + PciExtReg =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addres= s)->ExtendedRegister & 0x0FFF; + } + + PciBus =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Bus; + PciDev =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Device; + PciFn =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Function; + + USRA_BLOCK_PCIE_ADDRESS (EndPointPciAddress, Width, Count, This->Segment= Number, PciBus, PciDev, PciFn, PciExtReg); + mDynamicSiLibraryProtocol->RegisterRead (&EndPointPciAddress, pData8); + return EFI_SUCCESS; +} + +/** + Allows write to PCI configuration space. + + @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + @param Width Signifies the width of the memory operation. + @param Address The address within the PCI configuration space + for the PCI controller. + @param Count The number of PCI configuration operations + to perform. + @param Buffer The source buffer to get the results. + + @retval EFI_SUCCESS The data was written to the PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Invalid parameters found. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFn; + UINT32 PciExtReg; + USRA_ADDRESS EndPointPciAddress; + UINT8 *pData8 =3D Buffer; + UINT8 Size; + + Size =3D 1 << (Width & 0x3); + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Width < 0 || Width >=3D EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // Write Pci configuration space + // + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + if (RootBridge->HecBase =3D=3D 0) { + return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); + } + + if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Extende= dRegister) { + PciExtReg =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addres= s)->Register; + } else { + PciExtReg =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addres= s)->ExtendedRegister & 0x0FFF; + } + + PciBus =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Bus; + PciDev =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Device; + PciFn =3D ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Addr= ess)->Function; + + USRA_BLOCK_PCIE_ADDRESS (EndPointPciAddress, Width, Count, This->Segment= Number, PciBus, PciDev, PciFn, PciExtReg); + mDynamicSiLibraryProtocol->RegisterWrite (&EndPointPciAddress, pData8); + + return EFI_SUCCESS; +} + +/** + Provides the PCI controller-specific address needed to access + system memory for DMA. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Operation Indicate if the bus master is going to read or wri= te + to system memory. + @param HostAddress The system memory address to map on the PCI contro= ller. + @param NumberOfBytes On input the number of bytes to map. + On output the number of bytes that were mapped. + @param DeviceAddress The resulting map address for the bus master PCI + controller to use to access the system memory's Ho= stAddress. + @param Mapping The value to pass to Unmap() when the bus master D= MA + operation is complete. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER Invalid parameters found. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a com= mon buffer. + @retval EFI_DEVICE_ERROR The System hardware could not map the req= uested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + MAP_INFO *MapInfo; + + if (NumberOfBytes =3D=3D NULL || Mapping =3D=3D NULL || DeviceAddress = =3D=3D NULL || HostAddress =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Initialize the return values to their defaults + // + *Mapping =3D NULL; + + // + // Make sure that Operation is valid + // + if ((UINT32) Operation >=3D EfiPciOperationMaximum) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + if (mIoMmu !=3D NULL) { + if (!RootBridge->DmaAbove4G) { + // + // Clear 64bit support + // + if (Operation > EfiPciOperationBusMasterCommonBuffer) { + Operation =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operati= on - EfiPciOperationBusMasterRead64); + } + } + Status =3D mIoMmu->Map ( + mIoMmu, + (EDKII_IOMMU_OPERATION) Operation, + HostAddress, + NumberOfBytes, + DeviceAddress, + Mapping + ); + return Status; + } + // + // Most PCAT like chipsets can not handle performing DMA above 4GB. + // If any part of the DMA transfer being mapped is above 4GB, then + // map the DMA transfer to a buffer below 4GB. + // + PhysicalAddress =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; + if ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB) { + // + // Common Buffer operations can not be remapped. If the common buffer + // if above 4GB, then it is not possible to generate a mapping, so ret= urn + // an error. + // + if (Operation =3D=3D EfiPciOperationBusMasterCommonBuffer || Operation= =3D=3D EfiPciOperationBusMasterCommonBuffer64) { + return EFI_INVALID_PARAMETER; + } + // + // Allocate a MAP_INFO structure to remember the mapping when Unmap() = is + // called later. + // + MapInfo =3D AllocatePool (sizeof (MAP_INFO)); + if (MapInfo =3D=3D NULL) { + *NumberOfBytes =3D 0; + return EFI_OUT_OF_RESOURCES; + } + // + // Return a pointer to the MAP_INFO structure in Mapping + // + *Mapping =3D MapInfo; + + // + // Initialize the MAP_INFO structure + // + MapInfo->Operation =3D Operation; + MapInfo->NumberOfBytes =3D *NumberOfBytes; + MapInfo->NumberOfPages =3D EFI_SIZE_TO_PAGES (*NumberOfBytes); + MapInfo->HostAddress =3D PhysicalAddress; + MapInfo->MappedHostAddress =3D SIZE_4GB - 1; + + // + // Allocate a buffer below 4GB to map the transfer to. + // + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiBootServicesData, + MapInfo->NumberOfPages, + &MapInfo->MappedHostAddress + ); + if (EFI_ERROR (Status)) { + FreePool (MapInfo); + *NumberOfBytes =3D 0; + return Status; + } + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if (Operation =3D=3D EfiPciOperationBusMasterRead || Operation =3D=3D = EfiPciOperationBusMasterRead64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->MappedHostAddress, + (VOID *) (UINTN) MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + // + // The DeviceAddress is the address of the maped buffer below 4GB + // + *DeviceAddress =3D MapInfo->MappedHostAddress; + } else { + // + // The transfer is below 4GB, so the DeviceAddress is simply the HostA= ddress + // + *DeviceAddress =3D PhysicalAddress; + } + + return EFI_SUCCESS; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any + corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target sys= tem + memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target = system memory. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + EFI_STATUS Status; + MAP_INFO *MapInfo; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->Unmap ( + mIoMmu, + Mapping + ); + return Status; + } + // + // See if the Map() operation associated with this Unmap() required a ma= pping buffer. + // If a mapping buffer was not required, then this function simply retur= ns EFI_SUCCESS. + // + if (Mapping !=3D NULL) { + // + // Get the MAP_INFO structure from Mapping + // + MapInfo =3D (MAP_INFO *) Mapping; + + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if ((MapInfo->Operation =3D=3D EfiPciOperationBusMasterWrite) || + (MapInfo->Operation =3D=3D EfiPciOperationBusMasterWrite64) + ) { + CopyMem ( + (VOID *) (UINTN) MapInfo->HostAddress, + (VOID *) (UINTN) MapInfo->MappedHostAddress, + MapInfo->NumberOfBytes + ); + } + // + // Free the mapped buffer and the MAP_INFO structure. + // + gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages); + FreePool (Mapping); + } + + return EFI_SUCCESS; +} + +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonB= uffer + or EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of = the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated + range. Only the attributes + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, + EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and + EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with= this + function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal + attribute bits are MEMORY_WRITE_COMBINE, + MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + // + // Validate Attributes + // + if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) !=3D 0)= { + return EFI_UNSUPPORTED; + } + + // + // Check for invalid inputs + // + if (HostAddress =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // The only valid memory types are EfiBootServicesData and + // EfiRuntimeServicesData + // + if (MemoryType !=3D EfiBootServicesData && + MemoryType !=3D EfiRuntimeServicesData) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + if (mIoMmu !=3D NULL) { + + if (!RootBridge->DmaAbove4G) { + // + // Clear DUAL_ADDRESS_CYCLE + // + Attributes &=3D ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE); + } + Status =3D mIoMmu->AllocateBuffer ( + mIoMmu, + Type, + MemoryType, + Pages, + HostAddress, + Attributes + ); + return Status; + } + + // + // Limit allocations to memory below 4GB + // + PhysicalAddress =3D SIZE_4GB - 1; + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + MemoryType, + Pages, + &PhysicalAddress + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *HostAddress =3D (VOID *) (UINTN) PhysicalAddress; + + return EFI_SUCCESS; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with + AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress= and + Pages was not allocated with AllocateBuff= er(). +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ) +{ + EFI_STATUS Status; + + if (mIoMmu !=3D NULL) { + Status =3D mIoMmu->FreeBuffer ( + mIoMmu, + Pages, + HostAddress + ); + return Status; + } + + return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages= ); +} + +/** + Flushes all PCI posted write transactions from a PCI host bridge to syst= em + memory. + + The Flush() function flushes any PCI posted write transactions from a PCI + host bridge to system memory. Posted write transactions are generated by= PCI + bus masters when they perform write transactions to target addresses in + system memory. + This function does not flush posted write transactions from any PCI brid= ges. + A PCI controller specific action must be taken to guarantee that the pos= ted + write transactions have been flushed from the PCI controller and from al= l the + PCI bridges into the PCI host bridge. This is typically done with a PCI = read + transaction from the PCI controller prior to calling Flush(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed + from the PCI host bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not fl= ushed + from the PCI host bridge due to a hardware er= ror. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Gets the attributes that a PCI root bridge supports setting with + SetAttributes(), and the attributes that a PCI root bridge is currently + using. + + The GetAttributes() function returns the mask of attributes that this PCI + root bridge supports and the mask of attributes that the PCI root bridge= is + currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root + bridge supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root + bridge is currently using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attribu= tes + that the PCI root bridge supports is retu= rned + in Supports. If Attributes is not NULL, t= hen + the attributes that the PCI root bridge is + currently using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + if (Attributes =3D=3D NULL && Supported =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + // + // Set the return value for Supported and Attributes + // + if (Supported !=3D NULL) { + *Supported =3D RootBridge->Supports; + } + + if (Attributes !=3D NULL) { + *Attributes =3D RootBridge->Attributes; + } + + return EFI_SUCCESS; +} + +/** + Sets attributes for a resource range on a PCI root bridge. + + The SetAttributes() function sets the attributes specified in Attributes= for + the PCI root bridge on the resource range specified by ResourceBase and + ResourceLength. Since the granularity of setting these attributes may va= ry + from resource type to resource type, and from platform to platform, the + actual resource range and the one passed in by the caller may differ. As= a + result, this function may set the attributes specified by Attributes on a + larger resource range than the caller requested. The actual range is ret= urned + in ResourceBase and ResourceLength. The caller is responsible for verify= ing + that the actual range for which the attributes were set is acceptable. + + @param This A pointer to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Attributes The mask of attributes to set. If the + attribute bit MEMORY_WRITE_COMBINE, + MEMORY_CACHED, or MEMORY_DISABLE is set, + then the resource range is specified by + ResourceBase and ResourceLength. If + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and + MEMORY_DISABLE are not set, then + ResourceBase and ResourceLength are ignored, + and may be NULL. + @param ResourceBase A pointer to the base address of the + resource range to be modified by the + attributes specified by Attributes. + @param ResourceLength A pointer to the length of the resource + range to be modified by the attributes + specified by Attributes. + + @retval EFI_SUCCESS The current configuration of this PCI roo= t bridge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI roo= t bridge + could not be retrieved. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + if ((Attributes & (~RootBridge->Supports)) !=3D 0) { + return EFI_UNSUPPORTED; + } + + RootBridge->Attributes =3D Attributes; + return EFI_SUCCESS; +} + +/** + Retrieves the current resource settings of this PCI root bridge in the f= orm + of a set of ACPI resource descriptors. + + There are only two resource descriptor types from the ACPI Specification= that + may be used to describe the current resources allocated to a PCI root br= idge. + These are the QWORD Address Space Descriptor, and the End Tag. The QWORD + Address Space Descriptor can describe memory, I/O, and bus number ranges= for + dynamic or fixed resources. The configuration of a PCI root bridge is de= scribed + with one or more QWORD Address Space Descriptors followed by an End Tag. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[out] Resources A pointer to the resource descriptors that + describe the current configuration of this PCI = root + bridge. The storage for the resource + descriptors is allocated by this function. The + caller must treat the return buffer as read-only + data, and the buffer must not be freed by the + caller. + + @retval EFI_SUCCESS The current configuration of this PCI root brid= ge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root brid= ge + could not be retrieved. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ) +{ + EFI_STATUS Status; + UINTN Idx; + + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + PCI_RES_NODE *ResAllocNode; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Config; + + // + // Get this instance of the Root Bridge. + // + RootBridge =3D ROOT_BRIDGE_FROM_THIS (This); + + // + // If the pointer is not NULL, it points to a buffer already allocated. + // + if (RootBridge->ConfigBuffer =3D=3D NULL) { + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) += sizeof (EFI_ACPI_END_TAG_DESCRIPTOR), + &RootBridge->ConfigBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + } + + Config =3D RootBridge->ConfigBuffer; + + ZeroMem (Config, TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + = sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + + for (Idx =3D 0; Idx < TypeMax; Idx++) { + + ResAllocNode =3D &RootBridge->ResAllocNode[Idx]; + + if (ResAllocNode->Status !=3D ResAllocated) { + continue; + } + + switch (ResAllocNode->Type) { + + case TypeIo: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)= - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode->Length = - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + case TypeMem32: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DES= CRIPTOR) - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->AddrSpaceGranularity =3D 32; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode-= >Length - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + case TypePMem32: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DES= CRIPTOR) - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag =3D 6; + Config->AddrSpaceGranularity =3D 32; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode-= >Length - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + case TypeMem64: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DES= CRIPTOR) - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag =3D 6; + Config->AddrSpaceGranularity =3D 64; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode-= >Length - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + case TypePMem64: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DES= CRIPTOR) - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + Config->SpecificFlag =3D 6; + Config->AddrSpaceGranularity =3D 64; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode-= >Length - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + case TypeBus: + Config->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + Config->Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)= - 3; + Config->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS; + Config->AddrRangeMin =3D ResAllocNode->Base; + Config->AddrRangeMax =3D ResAllocNode->Base + ResAllocNode->Length = - 1; + Config->AddrLen =3D ResAllocNode->Length; + break; + + default: + break; + } + + Config++; + } + // + // Terminate the entries. + // + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Desc =3D ACPI_END_TAG_DES= CRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Checksum =3D 0x0; + + *Resources =3D RootBridge->ConfigBuffer; + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciIovPlatformPolicy.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/= Dxe/PciPlatform/PciIovPlatformPolicy.c new file mode 100644 index 0000000000..32775fafe7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciIo= vPlatformPolicy.c @@ -0,0 +1,99 @@ +/** @file + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include "PciPlatform.h" +#include + +#ifdef EFI_PCI_IOV_SUPPORT + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +{ + UINT8 SystemPageSizeOption; + + CopyMem (&SystemPageSizeOption, (((UINT8*) PcdGetPtr (PcdSetup)) + OFFSE= T_OF (SYSTEM_CONFIGURATION, SystemPageSize)), sizeof (UINT8)); + + if (SystemLowestPageSize !=3D NULL) { + // + // Convert page size option to page size + // Option is n in 2^n + // Page size is number of 4KiB pages + // + + *SystemLowestPageSize =3D (UINT32) (1 << SystemPageSizeOption); + } + return EFI_SUCCESS; +} + +/** + + The GetIovPlatformPolicy() function retrieves the platform policy rega= rding PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +EFI_STATUS +EFIAPI +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +{ + UINT8 PolicyEnable; + UINT8 ARIEnable; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; + + PolicyEnable =3D 0; + + CopyMem (&ARIEnable, (((UINT8*) PcdGetPtr (PcdSetup)) + OFFSET_OF (SYS= TEM_CONFIGURATION, ARIEnable)), sizeof (UINT8)); + CopyMem (&SRIOVEnable, (((UINT8*) PcdGetPtr (PcdSetup)) + OFFSET_OF (SYS= TEM_CONFIGURATION, SRIOVEnable)), sizeof (UINT8)); + CopyMem (&MRIOVEnable, (((UINT8*) PcdGetPtr (PcdSetup)) + OFFSET_OF (SYS= TEM_CONFIGURATION, MRIOVEnable)), sizeof (UINT8)); + + if (ARIEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_ARI; + } + + if (SRIOVEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_SRIOV; + } + + if (MRIOVEnable =3D=3D TRUE) { + PolicyEnable =3D PolicyEnable | EFI_PCI_IOV_POLICY_MRIOV; + } + + if (PciIovPolicy !=3D NULL) { + //*PciIovPolicy =3D EFI_PCI_IOV_POLICY_ARI | EFI_PCI_IOV_POLICY_SRIOV; + *PciIovPolicy =3D PolicyEnable; + } + return EFI_SUCCESS; +} + +#endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciIovPlatformPolicy.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/= Dxe/PciPlatform/PciIovPlatformPolicy.h new file mode 100644 index 0000000000..ecd57292e2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciIo= vPlatformPolicy.h @@ -0,0 +1,53 @@ +/** @file + Include file for PciIovPlatformPolicy.c + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_IOV_PLATFORM_POLICY_H_ +#define _PCI_IOV_PLATFORM_POLICY_H_ + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest pag= e size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROT= OCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This syste= m supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +; + + +/** + + The GetPlatformPolicy() function retrieves the platform policy regardi= ng PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL ins= tance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +EFI_STATUS +EFIAPI +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciPlatform.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPl= atform/PciPlatform.c new file mode 100644 index 0000000000..8584c0f330 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPl= atform.c @@ -0,0 +1,541 @@ +/** @file + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include "PciPlatform.h" +#include +#include +#include +#include +#ifdef EFI_PCI_IOV_SUPPORT +#include "PciIovPlatformPolicy.h" +#endif + +#include + +PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; + +BOOLEAN FirstCall =3D TRUE; +UINT8 sSataRaidLoadEfiDriverOption; +UINT8 SataRaidLoadEfiDriverOption[PCH_MAX_SATA_CONTROL= LERS]; +UINT8 BootNetworkOption; + +STATIC +BOOLEAN +InternalPlatformCheckPcieRootPort ( + IN UINTN Bus, + IN UINT32 PcieSlotOpromBitMap +) +{ + EFI_STATUS Status; + + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + UINTN DataLength =3D 0; + PLATFORM_OPTION_ROM_UPDATE_DATA OptionRomUpdateTable; + + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO," InternalPlatformCheckPcieRootPort fail!\n")); + return TRUE; + } + + DataLength =3D sizeof (OptionRomUpdateTable); + Status =3D UbaConfigProtocol->GetData ( + UbaConfigProtocol, + &gPlatformOptionRomUpdateConfigDataGuid, + &OptionRomUpdateTable, + &DataLength + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO,"InternalPlatformCheckPcieRootPort fail!\n")); + return TRUE; + } + + ASSERT (OptionRomUpdateTable.Signature =3D=3D PLATFORM_OPTION_ROM_UPDATE= _SIGNATURE); + ASSERT (OptionRomUpdateTable.Version =3D=3D PLATFORM_OPTION_ROM_UPDATE_V= ERSION); + + return OptionRomUpdateTable.CallCheckRootPort (Bus, PcieSlotOpromBitMap); +} + +STATIC +EFI_STATUS +InternalGetSystemBoardInfo ( + IN OUT DXE_SYSTEM_BOARD_INFO **SystemboardInfoTableBuffer + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + UINTN DataLength =3D 0; + SYSTEM_BOARD_INFO_DATA SystemBoardInfoData; + + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR," [GetSystemBoardInfo] Locate UbaConfigProtocol f= ail!\n")); + return Status; + } + + DataLength =3D sizeof(SystemBoardInfoData); + Status =3D UbaConfigProtocol->GetData ( + UbaConfigProtocol, + &gSystemBoardInfoConfigDataGuid, + &SystemBoardInfoData, + &DataLength + ); + + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR," [GetSystemBoardInfo] Get Data fail!\n")); + return Status; + } + + ASSERT (SystemBoardInfoData.Signature =3D=3D SYSTEM_SYSTEM_BOARD_INFO_SI= GNATURE); + ASSERT (SystemBoardInfoData.Version =3D=3D SYSTEM_SYSTEM_BOARD_INFO_VE= RSION); + + *SystemboardInfoTableBuffer =3D SystemBoardInfoData.CallUpdate (); + + return Status; +} + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO= _ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + if (PciPolicy =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +/** + + Get an indicated image in raw sections. + + @param NameGuid - NameGuid of the image to get. + @param Buffer - Buffer to store the image get. + @param Size - size of the image get. + + @retval EFI_NOT_FOUND - Could not find the image. + @retval EFI_LOAD_ERROR - Error occurred during image loading. + @retval EFI_SUCCESS - Image has been successfully loaded. + +**/ +EFI_STATUS +GetRawImage( + IN EFI_GUID *NameGuid, + IN OUT VOID **Buffer, + IN OUT UINTN *Size + ) { + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINT32 AuthenticationStatus; + + Status =3D gBS->LocateHandleBuffer( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR(Status) || HandleCount =3D=3D 0) { + return EFI_NOT_FOUND; + } + // + // Find desired image in all Fvs + // + for (Index =3D 0; Index < HandleCount; Index++) { + Status =3D gBS->HandleProtocol( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + &Fv + ); + if (EFI_ERROR(Status)) { + return EFI_LOAD_ERROR; + } + // + // Try a raw file + // + *Buffer =3D NULL; + *Size =3D 0; + Status =3D Fv->ReadSection( + Fv, + NameGuid, + EFI_SECTION_RAW, + 0, + Buffer, + Size, + &AuthenticationStatus + ); + if (!EFI_ERROR(Status)) { + DEBUG((EFI_D_INFO, "Read the OROM successfully!\n")); + break; + } + } + + if (Index >=3D HandleCount) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; + UINT16 DeviceClass; + UINTN TableIndex; + UINTN RomImageNumber; + VOID *OpRomBase; + UINTN OpRomSize; + EFI_PCI_ROM_HEADER RomHeader; + PCI_DATA_STRUCTURE *Pcir; + OPROM_LOAD_POLICY OpromPolicy; + BOOLEAN SlotOptionRomDisabled; + DXE_SYSTEM_BOARD_INFO *SystemBoardInfo =3D NULL; + UINT32 Index; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + OpRomBase =3D NULL; + OpRomSize =3D 0; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Get System Board Info + // + Status =3D InternalGetSystemBoardInfo (&SystemBoardInfo); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "[GetPciRom] Get system board info fail!\n")); + return Status; + } + + Status =3D gBS->HandleProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + if (FirstCall =3D=3D TRUE) { + Status =3D GetOptionData (&gEfiSetupVariableGuid, OFFSET_OF(SYSTEM_CON= FIGURATION, BootNetwork), &BootNetworkOption, sizeof(BootNetworkOption)); + if (EFI_ERROR (Status)) { + BootNetworkOption =3D 0; + } + Status =3D GetOptionData (&gPchSetupVariableGuid, + OFFSET_OF(PCH_SETUP, SataRaidLoadEfiDriver), + &SataRaidLoadEfiDriverOption, + sizeof(SataRaidLoadEfiDriverOption) * PCH_MAX_SA= TA_CONTROLLERS); + if (EFI_ERROR (Status)) { + for (Index =3D 0; Index < DynamicSiLibraryProtocol->MaxSataControlle= rNum(); Index++) { + SataRaidLoadEfiDriverOption[Index] =3D 0; + } + } + + FirstCall =3D FALSE; + } + + PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_CLASSCODE_OFFSET + 1, 1= , &DeviceClass); + + // + // Run PXE ROM only if Boot network is enabled + // + if ((BootNetworkOption =3D=3D 0) && + (DeviceClass =3D=3D ((PCI_CLASS_NETWORK << 8) | PCI_CLASS_NETWORK_ET= HERNET)) + ) { + return EFI_NOT_FOUND; + } + + // + // Run each PCI-E slot ROM only if PCI-E Slot Oprom is enabled. + // + if ( Bus !=3D 0 ) { + SlotOptionRomDisabled =3D InternalPlatformCheckPcieRootPort (Bus, PcdG= et32(PcdOemSkuPcieSlotOpromBitMap)); + + if (SlotOptionRomDisabled) { + return EFI_NOT_FOUND; + } + } + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &V= endorId); + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &D= eviceId); + + //DEBUG ((EFI_D_INFO, "GetPciRom - VenID:DevID: %04x:%04x\n", (UINTN)Ven= dorId, (UINTN)DeviceId)); + + // + // Fix MS-HD5770 video adapter can not work: + // This device is not a OPROM 3.0 and does not have device id list as we= ll. + // It only have 1 device id in OPROM. + // Device Id in OpROM is not same with the value in PCI configuration sp= ace + // it will cause VBIOS fails to start + // + if ((VendorId =3D=3D 0x1002) && (DeviceId =3D=3D 0x68BE)) { + DEBUG ((DEBUG_INFO, "MS-HD5770 video adapter\n")); + RomHeader.Raw =3D PciIo->RomImage; + if (RomHeader.Raw !=3D NULL) { + Pcir =3D (PCI_DATA_STRUCTURE *)(RomHeader.Raw + RomHeader.Generic->P= cirOffset); + if ((Pcir->VendorId =3D=3D 0x1002) && (Pcir->DeviceId =3D=3D 0x68B8)= ) { + // + // Assign same device id in PCI configuration space + // + Pcir->DeviceId =3D DeviceId; + } + } else { + DEBUG ((EFI_D_ERROR, "MS-HD5770 video adapter detected but PciIo->Ro= mImage =3D=3D NULL!\n")); + } + } + + //Check if user disables the option rom loading for this device. + if (!PlatformOpromLoadDevicePolicy(PciIo)) { + return EFI_NOT_FOUND; + } + + // If setup value requested EFI, we don't load the RAID OROM. + if (VendorId =3D=3D V_SATA_CFG_VENDOR_ID) { + for (Index =3D 0; Index < DynamicSiLibraryProtocol->MaxSataControllerN= um(); Index++) { + if (Bus =3D=3D DEFAULT_PCI_BUS_NUMBER_PCH && + Device =3D=3D DynamicSiLibraryProtocol->SataDevNumber (Index) && + Function =3D=3D DynamicSiLibraryProtocol->SataFuncNumber (Index)= && + SataRaidLoadEfiDriverOption[Index] =3D=3D 1) { + return EFI_NOT_FOUND; + } + } + } + + // + // Loop through table of video option rom descriptions + // + RomImageNumber =3D 0; + for (TableIndex =3D 0; SystemBoardInfo->PciOptionRomTable[TableIndex].Ve= ndorId !=3D 0xffff; TableIndex++) { + // + // See if the PCI device specified by PciHandle matches at device in m= PciOptionRomTable + // + if (VendorId !=3D SystemBoardInfo->PciOptionRomTable[TableIndex].Vendo= rId || + DeviceId !=3D SystemBoardInfo->PciOptionRomTable[TableIndex].Devic= eId || + Device !=3D SystemBoardInfo->PciOptionRomTable[TableIndex].Device = || + Function !=3D SystemBoardInfo->PciOptionRomTable[TableIndex].Funct= ion + ) { + continue; + } + + //Check if user wants to exclusively run this option rom for the devic= e. + OpromPolicy =3D PlatformOpromLoadTypePolicy(PciHandle, TableIndex); + if(OpromPolicy =3D=3D DONT_LOAD) { + continue; + } + + Status =3D GetRawImage ( + &SystemBoardInfo->PciOptionRomTable[TableIndex].FileName, + &OpRomBase, + &OpRomSize + ); + + if (EFI_ERROR (Status)) { + continue; + } else { + RomImageNumber++; + if (RomImageNumber =3D=3D PcdGet8(PcdMaxOptionRomNumber) || OpromPol= icy =3D=3D EXCLUSIVE_LOAD) { + break; + } + } + } + + if (RomImageNumber =3D=3D 0) { + + return EFI_NOT_FOUND; + + } else { + + *RomImage =3D OpRomBase; + *RomSize =3D OpRomSize; + + return EFI_SUCCESS; + } +} + +/** + + GC_TODO: Add function description + + @param This - GC_TODO: add argument description + @param Function - GC_TODO: add argument description + @param Phase - GC_TODO: add argument description + + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_UNSUPPORTED - GC_TODO: Add description for return value + @retval EFI_SUCCESS - GC_TODO: Add description for return value + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +{ + LIST_ENTRY *NodeEntry; + PCI_CALLBACK_DATA *PciCallbackData; + + if (Function =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ( (Phase & (EfiPciEnumerationDeviceScanning | EfiPciEnumerationBusNu= mberAssigned \ + | EfiPciEnumerationResourceAssigned)) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + // + // Check if the node has been added + // + NodeEntry =3D GetFirstNode (&mPciPrivateData.PciCallbackList); + while (!IsNull (&mPciPrivateData.PciCallbackList, NodeEntry)) { + PciCallbackData =3D PCI_CALLBACK_DATA_FROM_LINK (NodeEntry); + if (PciCallbackData->Function =3D=3D Function) { + return EFI_UNSUPPORTED; + } + + NodeEntry =3D GetNextNode (&mPciPrivateData.PciCallbackList, NodeEntry= ); + } + + PciCallbackData =3D NULL; + PciCallbackData =3D AllocateZeroPool (sizeof (PCI_CALLBACK_DATA)); + ASSERT (PciCallbackData !=3D NULL); + + if(PciCallbackData !=3D NULL){ + PciCallbackData->Signature =3D PCI_CALLBACK_DATA_SIGNATURE; + PciCallbackData->Function =3D Function; + PciCallbackData->Phase =3D Phase; + InsertTailList (&mPciPrivateData.PciCallbackList, &PciCallbackData->Li= nk); + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + + +/** + + Main Entry point of the Pci Platform Driver. + + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + mPciPrivateData.PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + //EDK2_TODO Check if clearing mPciPrivateData.PlatformInfo (got above) i= s intended. + ZeroMem (&mPciPrivateData, sizeof (mPciPrivateData)); + InitializeListHead (&mPciPrivateData.PciCallbackList); + + mPciPrivateData.PciPlatform.PlatformNotify =3D PhaseNotify; + mPciPrivateData.PciPlatform.PlatformPrepController =3D PlatformPrepCont= roller; + mPciPrivateData.PciPlatform.GetPlatformPolicy =3D GetPlatformPolic= y; + mPciPrivateData.PciPlatform.GetPciRom =3D GetPciRom; + mPciPrivateData.PciCallback.RegisterPciCallback =3D RegisterPciCallb= ack; +#ifdef EFI_PCI_IOV_SUPPORT + mPciPrivateData.PciIovPlatform.GetSystemLowestPageSize =3D GetSystemLowe= stPageSize; + mPciPrivateData.PciIovPlatform.GetPlatformPolicy =3D GetIovPlatfor= mPolicy; +#endif + + // + // Install on a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mPciPrivateData.PciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + &mPciPrivateData.PciPlatform, + &gEfiPciCallbackProtocolGuid, + &mPciPrivateData.PciCallback, +#ifdef EFI_PCI_IOV_SUPPORT + &gEfiPciIovPlatformProtocolGuid, + &mPciPrivateData.PciIovPlatform, +#endif + NULL + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciPlatform.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPl= atform/PciPlatform.h new file mode 100644 index 0000000000..45d9c38b16 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPl= atform.h @@ -0,0 +1,209 @@ +/** @file + This is PCI platform initialization code. + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_PLATFORM_MODULE_H_ +#define _PCI_PLATFORM_MODULE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifndef NELEMENTS +#define NELEMENTS(Array) (sizeof(Array)/sizeof((Array)[0])) +#endif +// +// Global variables for Option ROMs +// + +#define INVALID 0xBD + +#define PCI_CALLBACK_DATA_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'c') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_PCI_CALLBACK_FUNC Function; + EFI_PCI_ENUMERATION_PHASE Phase; +} PCI_CALLBACK_DATA; + +typedef struct { + EFI_HANDLE PciPlatformHandle; + EFI_HANDLE RootBridgeHandle; + EFI_PCI_PLATFORM_PROTOCOL PciPlatform; + EFI_PCI_CALLBACK_PROTOCOL PciCallback; +#ifdef EFI_PCI_IOV_SUPPORT + EFI_PCI_IOV_PLATFORM_PROTOCOL PciIovPlatform; +#endif + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo[MAX_SOCKET][MAX_IIO_STA= CK]; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_LIST_ENTRY PciCallbackList; + EFI_PCI_CALLBACK_CONTEXT Context; + EFI_PCI_ENUMERATION_PHASE PciEnumerationPhase; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 BusAssignedTime; +} PCI_PLATFORM_PRIVATE_DATA; + +#define PCI_CALLBACK_DATA_FROM_LINK(_node) \ + CR ( \ + _node, \ + PCI_CALLBACK_DATA, \ + Link, \ + PCI_CALLBACK_DATA_SIGNATURE \ + ) + +extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; +extern EFI_GUID gPchSataEfiLoadProtocolGuid; + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI Host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + The PlatformPrepController() function can be used to notify the platform= driver so that + it can perform platform-specific actions. No specific actions are requir= ed. + Several notification points are defined at this time. More synchronizati= on points may be + added as required in the future. The PCI bus driver calls the platform d= river twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation= Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Prot= ocol driver has + been notified. + This member function may not perform any error checking on the input par= ameters. It also + does not return any error codes. If this member function detects any err= or condition, it + needs to handle those errors on its own because there is no way to surfa= ce any errors to + the caller. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI Host bridge handle. + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO= _ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +; + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +; + +/** + + Register a callback during PCI bus enumeration + + @param This - Protocol instance pointer. + @param Function - Callback function pointer. + @param Phase - PCI enumeration phase. + + @retval EFI_SUCCESS - Function has registed successfully + @retval EFI_UNSUPPORTED - The function has been regisered + @retval EFI_InVALID_PARAMETER - The parameter is incorrect + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciPlatform.inf b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciPlatform.inf new file mode 100644 index 0000000000..4121ea8982 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPl= atform.inf @@ -0,0 +1,87 @@ +## @file +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciPlatform + FILE_GUID =3D E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciPlatformDriverEntry + +[Sources] + PciPlatform.c + PciPlatform.h + PciPlatformHooks.c + PciPlatformHooks.h + PciIovPlatformPolicy.c + PciIovPlatformPolicy.h + PciSupportLib.c + PciSupportLib.h + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/Cpu/CpuRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + IoLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + S3PciLib + SetupLib + PcdLib + PlatformOpromPolicyLib + +[Protocols] + gEfiPciCallbackProtocolGuid + gEfiCpuIo2ProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiPciIoProtocolGuid + gEfiPciPlatformProtocolGuid + gEfiIioUdsProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiPciIovPlatformProtocolGuid + gEfiIioSystemProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gUbaConfigDatabaseProtocolGuid + gDynamicSiLibraryProtocolGuid ## CONSUMES + +[Guids] + gEfiPlatformInfoGuid + gEfiSetupVariableGuid + gPchSetupVariableGuid + gSystemBoardInfoConfigDataGuid + +[Pcd] + gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap + gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport + gStructPcdTokenSpaceGuid.PcdSetup + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gSystemBoardInfoConfigDataGuid AND + gEfiPciHostBridgeResourceAllocationProtocolGuid AND + gUbaConfigDatabaseProtocolGuid AND + gDynamicSiLibraryProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciPlatformHooks.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/= PciPlatform/PciPlatformHooks.c new file mode 100644 index 0000000000..89154cb6e1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPl= atformHooks.c @@ -0,0 +1,939 @@ +/** @file + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../PciHostBridge/PciRootBridge.h" +#include "../PciHostBridge/PciHostBridge.h" + + +/*************************************************************************= ***** + * Local definitions. + *************************************************************************= *****/ +/** + Uncomment the PCIDEBUG macro to enable tracing the library activity in a= test build. + **/ +#define PCIDEBUG(...) // { DEBUG((DEBUG_INFO, "[PCI] " __VA_ARGS__)); } + + +/*************************************************************************= ***** + * Variables. + *************************************************************************= *****/ +SYSTEM_CONFIGURATION mSystemConfiguration; +EFI_IIO_UDS_PROTOCOL *mIioUds =3D NULL; + + +/*************************************************************************= ***** + * Functions. + *************************************************************************= *****/ +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + IN EFI_PCI_CALLBACK_CONTEXT *ContextPtr + ) +{ + EFI_LIST_ENTRY *NodePtr; + PCI_CALLBACK_DATA *CallbackDataPtr; + + // + // Check if the node has been added + // + for (NodePtr =3D GetFirstNode (&mPciPrivateData.PciCallbackList); + !IsNull (&mPciPrivateData.PciCallbackList, NodePtr); + NodePtr =3D GetNextNode (&mPciPrivateData.PciCallbackList, NodePtr)= ) { + CallbackDataPtr =3D PCI_CALLBACK_DATA_FROM_LINK (NodePtr); + if (CallbackDataPtr->Phase & Phase) { + (CallbackDataPtr->Function) (RootBridgeHandle, PciAddress, Phase, Co= ntextPtr); + } + } +} + +/** + + GC_TODO: add routine description + + @param StartBus - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +PciTreeTraverse ( + IN UINT8 Socket, + IN UINT8 Stack, + IN UINT8 StartBus + ) +{ + UINT64 PciAddress; + UINT8 Device; + UINT8 Func; + UINT8 SecondaryBus; + BOOLEAN MultiFunc; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + + if (Socket >=3D NELEMENTS (mPciPrivateData.PciRootBridgeIo) || + Stack >=3D NELEMENTS (mPciPrivateData.PciRootBridgeIo[Socket]) || + mPciPrivateData.PciRootBridgeIo[Socket][Stack] =3D=3D NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PciRootBridgeIo =3D mPciPrivateData.PciRootBridgeIo[Socket][Stack]; + + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) { + MultiFunc =3D FALSE; + for (Func =3D 0; Func <=3D PCI_MAX_FUNC; Func++) { + if (IsPciDevicePresent ( + PciRootBridgeIo, + &mPciPrivateData.Context.PciHeader, + StartBus, + Device, + Func + )) { + if ((Func =3D=3D 0) && IS_PCI_MULTI_FUNC(&mPciPrivateData.Context.= PciHeader)) { + MultiFunc =3D TRUE; + } + PciAddress =3D EFI_PCI_ADDRESS (StartBus, Device, Func, 0); + mPciPrivateData.Context.PciRootBridgeIo =3D PciRootBridgeIo; + ChipsetCallback ( + mPciPrivateData.RootBridgeHandle, + *(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &PciAddress, + mPciPrivateData.PciEnumerationPhase, + &(mPciPrivateData.Context) + ); + if (IS_PCI_BRIDGE (&(mPciPrivateData.Context.PciHeader))) { + PciAddress =3D EFI_PCI_ADDRESS (StartBus, Device, Func, PCI_BRID= GE_SECONDARY_BUS_REGISTER_OFFSET); + PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint8, + *(UINT64 *) &PciAddress, + 1, + &SecondaryBus + ); + if ((SecondaryBus > 0) && (SecondaryBus < 0xFF)) { + // + // Recursive call for next bus in this stack + // + PciTreeTraverse (Socket, Stack, SecondaryBus); + } + } + } + + if (!MultiFunc) { + // + // Skip sub functions, this is not a multi function device + // + Func =3D PCI_MAX_FUNC; + } + } + } + + return EFI_SUCCESS; +} + +/** + + Program Io Apic Id + + @param IoApicAddress and IoApicId + + @retval None + +**/ +VOID +ProgramIoApicId ( + IN UINT32 IoApicAddress, + IN UINT8 IoApicId + ) +{ + + UINT32 Data; + + mPciPrivateData.CpuIo->Mem.Read ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + // + // IOAPIC is not there + // + if (Data =3D=3D (UINT32) -1) { + return ; + } + // + // Set up IO APIC ID and enable FSB delivery + // Use CPU IO protocol since the IO APIC ranges + // are not included in PCI apertures + // + Data =3D EFI_IO_APIC_ID_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data =3D IoApicId << EFI_IO_APIC_ID_BITSHIFT; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); + + Data =3D EFI_IO_APIC_BOOT_CONFIG_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data =3D EFI_IO_APIC_FSB_INT_DELIVERY; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); +} + +#ifdef EFI_PCI_IOV_SUPPORT +/** + + Initialize the Pci Iov Platform Data. + + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformInitPciIovData ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PCI_IOV_PLATFORM_POLICY PciIovPolicy; + UINT32 SystemPageSize; + EFI_PCI_IOV_PLATFORM_PROTOCOL *gPciIovPlatformProtocol; + + Status =3D gBS->LocateProtocol ( + &gEfiPciIovPlatformProtocolGuid, + NULL, + &gPciIovPlatformProtocol + ); + if (!EFI_ERROR (Status)) { + Status =3D gPciIovPlatformProtocol->GetSystemLowestPageSize ( + gPciIovPlatformProtocol, + &SystemPageSize + ); + if (!EFI_ERROR (Status)) { + Status =3D PcdSet32S (PcdSrIovSystemPageSize, SystemPageSize); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } else { + return Status; + } + Status =3D gPciIovPlatformProtocol->GetPlatformPolicy ( + gPciIovPlatformProtocol, + &PciIovPolicy + ); + if (!EFI_ERROR (Status)) { + if (PciIovPolicy & EFI_PCI_IOV_POLICY_ARI) { + Status =3D PcdSetBoolS (PcdAriSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } else { + Status =3D PcdSetBoolS (PcdAriSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_SRIOV) { + Status =3D PcdSetBoolS (PcdSrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } else { + Status =3D PcdSetBoolS (PcdSrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_MRIOV) { + Status =3D PcdSetBoolS (PcdMrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } else { + Status =3D PcdSetBoolS (PcdMrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + } + } else { + return Status; + } + DEBUG (( + EFI_D_INFO, + " Initialized SR-IOV Platform Data: PCIIovPolicy =3D 0x%x; Syste= mPageSize =3D 0x%x;\n", + PciIovPolicy, SystemPageSize + )); + } else { + DEBUG (( + EFI_D_INFO, + " Using default values for SystemPageSize;\n" + )); + } + return Status; +} +#endif + +/** + + Platform Pci Express init. + + @param HostBridgeInstance - Pointer to Host Bridge private data + does not support 64 bit memory addresses. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +PciPlatformEarlyInit ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + +#ifdef EFI_PCI_IOV_SUPPORT + Status =3D PciPlatformInitPciIovData(); // Update IOV PCD values +#endif + return Status; +} + +/** + + Attempts to set the XHCI controller's PCI CMD.MSE and CMD.BME bits to en= able OS kernel debugging over XHCI. + +**/ +VOID +AttemptToSetXhciMse ( + ) + +{ + UINT32 XhciBar; + UINT16 Command; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + // + // Step 1. Make sure the XHCI BAR is initialized. + // Check if lower 32 bits of 64-bit BAR are configured. + // + XhciBar =3D MmioRead32 (DynamicSiLibraryProtocol->MmPciBase (DEFAULT_PCI= _BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI) = + R_XHCI_CFG_BAR0) & ~(0xF); + if (XhciBar =3D=3D 0xFFFFFFF0) { + return; + } + if ((XhciBar & 0xFFFF0000) =3D=3D 0) { + // + // If lower 32 bits are not configured, check upper 32 bits. + // + XhciBar =3D MmioRead32 (DynamicSiLibraryProtocol->MmPciBase (DEFAULT_P= CI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI= ) + R_XHCI_CFG_BAR0 + 4); + if (XhciBar =3D=3D 0) { + return; + } + } + + // + // Step 2. If XHCI's MSE (Memory Space Enable) or BME (Bus Master Enable= ) bits are cleared, set them. + // + Command =3D MmioRead16 (DynamicSiLibraryProtocol->MmPciBase (DEFAULT_PCI= _BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI) = + PCI_COMMAND_OFFSET); + if ((Command & (EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTE= R)) !=3D (EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER)) { + MmioOr16 (DynamicSiLibraryProtocol->MmPciBase (DEFAULT_PCI_BUS_NUMBER_= PCH, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI) + PCI_COMMAN= D_OFFSET, (EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER)); + } +} + + +/** + + Init pci device registers after the device resources have been allocated= , so + that devices behind a bus could be accessed. + + @param HostBridgeInstance - PCI_HOST_BRIDGE_INSTANCE. + + @retval EFI_SUCCESS - Function has completed successfully. + +**/ +EFI_STATUS +PciPlatformPostInit ( + VOID + ) +{ + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + EFI_STATUS Status; + + // + // Program all the IOAPIC in system + // + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + UINT8 Socket, Stack, IoApicId, ApicIndex =3D 0; + CPU_CSR_ACCESS_VAR *CpuCsrAccessVarPtr =3D NULL; + Stack =3D 0; + IoApicId =3D 0; + CpuCsrAccessVarPtr =3D DynamicSiLibraryProtocol->GetSysCpuCsrAccessVar (= ); + DEBUG ((DEBUG_INFO, "PciPlatformPostInit: setting up IOAPIC for PCH\n")); + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[0].StackR= es[0].IoApicBase, PCH_IOAPIC_ID); + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + if (!(CpuCsrAccessVarPtr->socketPresentBitMap & (1 << Socket))) { + continue; + } + + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++, ApicIndex++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPrese= ntBitmap & (1 << Stack))) { + continue; + } + switch (ApicIndex) { + case 0: + IoApicId =3D PC00_IOAPIC_ID; + break; + case 1: + IoApicId =3D PC01_IOAPIC_ID; + break; + case 2: + IoApicId =3D PC02_IOAPIC_ID; + break; + case 3: + IoApicId =3D PC03_IOAPIC_ID; + break; + case 4: + IoApicId =3D PC04_IOAPIC_ID; + break; + case 5: + IoApicId =3D PC05_IOAPIC_ID; + break; + case 6: + IoApicId =3D PC06_IOAPIC_ID; + break; + case 7: + IoApicId =3D PC07_IOAPIC_ID; + break; + case 8: + IoApicId =3D PC08_IOAPIC_ID; + break; + case 9: + IoApicId =3D PC09_IOAPIC_ID; + break; + case 10: + IoApicId =3D PC10_IOAPIC_ID; + break; + case 11: + IoApicId =3D PC11_IOAPIC_ID; + break; + case 12: + IoApicId =3D PC12_IOAPIC_ID; + break; + case 13: + IoApicId =3D PC13_IOAPIC_ID; + break; + case 14: + IoApicId =3D PC14_IOAPIC_ID; + break; + case 15: + IoApicId =3D PC15_IOAPIC_ID; + break; + case 16: + IoApicId =3D PC16_IOAPIC_ID; + break; + case 17: + IoApicId =3D PC17_IOAPIC_ID; + break; + case 18: + IoApicId =3D PC18_IOAPIC_ID; + break; + case 19: + IoApicId =3D PC19_IOAPIC_ID; + break; + case 20: + IoApicId =3D PC20_IOAPIC_ID; + break; + case 21: + IoApicId =3D PC21_IOAPIC_ID; + break; + case 22: + IoApicId =3D PC22_IOAPIC_ID; + break; + case 23: + IoApicId =3D PC23_IOAPIC_ID; + break; + case 24: + IoApicId =3D PC24_IOAPIC_ID; + break; + case 25: + IoApicId =3D PC25_IOAPIC_ID; + break; + case 26: + IoApicId =3D PC26_IOAPIC_ID; + break; + case 27: + IoApicId =3D PC27_IOAPIC_ID; + break; + case 28: + IoApicId =3D PC28_IOAPIC_ID; + break; + case 29: + IoApicId =3D PC29_IOAPIC_ID; + break; + case 30: + IoApicId =3D PC30_IOAPIC_ID; + break; + case 31: + IoApicId =3D PC31_IOAPIC_ID; + break; + case 32: + IoApicId =3D PC32_IOAPIC_ID; + break; + case 33: + IoApicId =3D PC33_IOAPIC_ID; + break; + case 34: + IoApicId =3D PC34_IOAPIC_ID; + break; + case 35: + IoApicId =3D PC35_IOAPIC_ID; + break; + case 36: + IoApicId =3D PC36_IOAPIC_ID; + break; + case 37: + IoApicId =3D PC37_IOAPIC_ID; + break; + case 38: + IoApicId =3D PC38_IOAPIC_ID; + break; + case 39: + IoApicId =3D PC39_IOAPIC_ID; + break; + case 40: + IoApicId =3D PC40_IOAPIC_ID; + break; + case 41: + IoApicId =3D PC41_IOAPIC_ID; + break; + case 42: + IoApicId =3D PC42_IOAPIC_ID; + break; + case 43: + IoApicId =3D PC43_IOAPIC_ID; + break; + case 44: + IoApicId =3D PC44_IOAPIC_ID; + break; + case 45: + IoApicId =3D PC45_IOAPIC_ID; + break; + case 46: + IoApicId =3D PC46_IOAPIC_ID; + break; + case 47: + IoApicId =3D PC47_IOAPIC_ID; + break; + default: + break; + } + if ((Socket =3D=3D 0) && (Stack =3D=3D 0)) { + ProgramIoApicId ((mIioUds->IioUdsPtr->PlatformData.IIO_resource[So= cket].StackRes[Stack].IoApicBase + 0x1000), IoApicId); + } else { + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Soc= ket].StackRes[Stack].IoApicBase, IoApicId); + } + } + } + + AttemptToSetXhciMse (); + + return EFI_SUCCESS; +} + +/** + + The PlatformPrepController() function can be used to notify the platform= driver so that + it can perform platform-specific actions. No specific actions are requir= ed. + Several notification points are defined at this time. More synchronizati= on points may be + added as required in the future. The PCI bus driver calls the platform d= river twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation= Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Prot= ocol driver has + been notified. + This member function may not perform any error checking on the input par= ameters. It also + does not return any error codes. If this member function detects any err= or condition, it + needs to handle those errors on its own because there is no way to surfa= ce any errors to + the caller. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI Host bridge handle. + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_UNSUPPORTED - Not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo; + PCI_TYPE00 Pci0; + UINT64 Address; + UINT8 SecBus; + UINT8 Device; + UINT8 Func; + UINT64 DummyData =3D 0xFFFFFFFF; + UINT32 DidVid; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProtocol =3D NULL; + + if (mPciPrivateData.RootBridgeHandle =3D=3D NULL) { + mPciPrivateData.RootBridgeHandle =3D RootBridge; + } + + Status =3D gBS->HandleProtocol ( + mPciPrivateData.RootBridgeHandle, + &gEfiPciRootBridgeIoProtocolGuid, + (VOID **) &RootBridgeIo + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + +// Workaround for PCI devices under Pilot IV, this video controller can on= ly be exposed if write 0xFFFFFFFF to it and read back + if (Phase =3D=3D EfiPciBeforeChildBusEnumeration && ChipsetPhase =3D=3D = ChipsetExit ) { + +// Read the entire config header + Address =3D EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAdd= ress.Function, 0); + Status =3D RootBridgeIo->Pci.Read ( + RootBridgeIo, + EfiPciWidthUint32, + Address, + sizeof (PCI_TYPE00) / sizeof (UINT32), + &Pci0 + ); + + if (!EFI_ERROR (Status) && IS_PCI_BRIDGE(&Pci0)) { + + // Read the secondary bus number + Address =3D EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciA= ddress.Function, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + Status =3D RootBridgeIo->Pci.Read ( + RootBridgeIo, + EfiPciWidthUint8, + Address, + 1, + &SecBus + ); + + if (!EFI_ERROR (Status)) { + + // + // For this bridge with existing secondary bus apply PCI Intel WAs + // + DidVid =3D ((Pci0.Hdr).DeviceId << 16) | (Pci0.Hdr).VendorId; + DynamicSiLibraryProtocol->IioPciHookBeforeEnumeration ((UINT8)Root= BridgeIo->SegmentNumber, PciAddress.Bus, PciAddress.Device, PciAddress.Func= tion, DidVid); + + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) { + for (Func =3D 0; Func <=3D PCI_MAX_FUNC; Func++) { + Address =3D EFI_PCI_ADDRESS (SecBus, Device, Func, 0); + Status =3D RootBridgeIo->Pci.Read ( + RootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + &Pci0 + ); + + if ( !EFI_ERROR (Status) && (Pci0.Hdr).VendorId =3D=3D 0xffff)= { + + Status =3D RootBridgeIo->Pci.Write( + RootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + &DummyData + ); + PCIDEBUG ("%a: For B(0x%x)-D(0x%x)-F(0x%x),Pci.Write() retur= ns with %r\n", + __FUNCTION__, SecBus, Device, Func, Status); + + if (EFI_ERROR (Status)) { + // + // If error, go to next function + // + continue; + } else { + Func =3D PCI_MAX_FUNC; // skip the remaining function + } + } + } + } + } + } + } + + return EFI_SUCCESS; +} + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instanc= e. + @param HostBridge - The associated PCI Host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset d= river. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UINT16 StackBit; + UINT8 Socket; + UINT8 Stack; + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *HostResAllocPtr; + PCI_HOST_BRIDGE_INSTANCE *HostBridgePtr; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgePtr; + LIST_ENTRY *NodePtr; + CPU_CSR_ACCESS_VAR *CpuCsrAccessVarPtr; + DYNAMIC_SI_LIBARY_PROTOCOL *DynamicSiLibraryProto= col =3D NULL; + + static CHAR8 *NotifyPhase2Name[] =3D {"EfiPciHostBridgeBeginEnumeration", + "EfiPciHostBridgeBeginBusAllocation", + "EfiPciHostBridgeEndBusAllocation", + "EfiPciHostBridgeBeginResourceAlloca= tion", + "EfiPciHostBridgeAllocateResources", + "EfiPciHostBridgeSetResources", + "EfiPciHostBridgeFreeResources", + "EfiPciHostBridgeEndResourceAllocati= on", + "EfiPciHostBridgeEndEnumeration"}; + + if (Phase < NELEMENTS (NotifyPhase2Name)) { + DEBUG ((DEBUG_INFO, "[PCI] %a phase notified (execution %d)\n", Notify= Phase2Name[Phase], ChipsetPhase)); + } else { + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Unknown phase %d notified (executio= n %d)\n", Phase, ChipsetPhase)); + } + + Status =3D gBS->LocateProtocol (&gDynamicSiLibraryProtocolGuid, NULL, &D= ynamicSiLibraryProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + CpuCsrAccessVarPtr =3D DynamicSiLibraryProtocol->GetSysCpuCsrAccessVar (= ); + + if (ChipsetPhase =3D=3D ChipsetEntry) { + return EFI_SUCCESS; + } + // + // If for multiple Host bridges, need special consideration + // + switch (Phase) { + + case EfiPciHostBridgeBeginEnumeration: + // + // Pre-initialization before PCI bus enumeration + // No bus number and no PCI resource + // Locate the IIO Protocol Interface + // + Status =3D gBS->LocateProtocol ( + &gEfiIioUdsProtocolGuid, + NULL, + &mIioUds + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol ( + &gEfiCpuIo2ProtocolGuid, + NULL, + &mPciPrivateData.CpuIo + ); + ASSERT_EFI_ERROR (Status); + + mPciPrivateData.Context.CpuIo =3D mPciPrivateData.CpuIo; + DEBUG ((DEBUG_INFO, "[PCI] Platform Pre-Initialization (Before bus sca= nning)\n")); + // + // Locate gEfiPciRootBridgeIoProtocolGuid instance created for each II= O stack. + // They were created by host bridge driver and linked to the + // gEfiPciHostBridgeResourceAllocationProtocolGuid protocol. + // + Status =3D gBS->LocateProtocol ( + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + NULL, + &HostResAllocPtr + ); + ASSERT_EFI_ERROR (Status); + + HostBridgePtr =3D CR (HostResAllocPtr, PCI_HOST_BRIDGE_INSTANCE, ResAl= loc, PCI_HOST_BRIDGE_SIGNATURE); + for (NodePtr =3D GetFirstNode (&HostBridgePtr->RootBridges); + !IsNull (&HostBridgePtr->RootBridges, NodePtr); + NodePtr =3D GetNextNode (&HostBridgePtr->RootBridges, NodePtr)) { + RootBridgePtr =3D CR (NodePtr, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_R= OOT_BRIDGE_SIGNATURE); + for (Socket =3D 0; Socket < NELEMENTS (mPciPrivateData.PciRootBridge= Io); Socket++) { + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + continue; + } + for (StackBit =3D 1, Stack =3D 0; + Stack < NELEMENTS (mPciPrivateData.PciRootBridgeIo[Socket]); + StackBit <<=3D 1, Stack++) { + if ((CpuCsrAccessVarPtr->stackPresentBitmap[Socket] & StackBit) = && + CpuCsrAccessVarPtr->StackBus[Socket][Stack] =3D=3D RootBridg= ePtr->Aperture.BusBase) { + // + // This is the stack handled by this instance of root bridge I= O protocol. Store it for future use. + // + mPciPrivateData.PciRootBridgeIo[Socket][Stack] =3D &RootBridge= Ptr->RootBridgeIo; + Socket =3D NELEMENTS (mPciPrivateData.PciRootBridgeIo); + break; + } + } + } + } + PciPlatformEarlyInit (); + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // There are two rounds PCI bus scanning + // First round will initilize the PCI hotplug device + // Second round will be the final one + // + if (mPciPrivateData.BusAssignedTime =3D=3D 0) { + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationDeviceScann= ing; + for (Socket =3D 0; Socket < NELEMENTS (mPciPrivateData.PciRootBridge= Io); Socket++) { + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + continue; + } + for (Stack =3D 0; Stack < NELEMENTS (mPciPrivateData.PciRootBridge= Io[Socket]); Stack ++) { + if (mPciPrivateData.PciRootBridgeIo[Socket][Stack] =3D=3D NULL) { + continue; + } + PciTreeTraverse (Socket, Stack, CpuCsrAccessVarPtr->StackBus[Soc= ket][Stack]); + } + } + mPciPrivateData.BusAssignedTime++; + DEBUG ((DEBUG_INFO, "[PCI] Platform bus assigned\n")); + } + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // PCI bus number has been assigned, but resource is still empty + // + DEBUG ((DEBUG_INFO, "[PCI] Platform Mid-Initialization (After bus numb= er assignment)\n")); + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationBusNumberAssi= gned; + for (Socket =3D 0; Socket < NELEMENTS (mPciPrivateData.PciRootBridgeIo= ); Socket++) { + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + continue; + } + for (Stack =3D 0; Stack < NELEMENTS (mPciPrivateData.PciRootBridgeIo= [Socket]); Stack ++) { + if (mPciPrivateData.PciRootBridgeIo[Socket][Stack] =3D=3D NULL) { + continue; + } + PciTreeTraverse (Socket, Stack, CpuCsrAccessVarPtr->StackBus[Socke= t][Stack]); + } + } + //PciPlatformMidInit (); + break; + + case EfiPciHostBridgeEndResourceAllocation: + // + // Resource enumeration is done. + // Both bus number and resource have been assigned + // Do any post initialization. + // + DEBUG ((DEBUG_INFO, "[PCI] Platform Post-Initialization (After resourc= e alloction)\n")); + mPciPrivateData.PciEnumerationPhase =3D EfiPciEnumerationResourceAssig= ned; + for (Socket =3D 0; Socket < NELEMENTS (mPciPrivateData.PciRootBridgeIo= ); Socket++) { + if (!mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].Valid) { + continue; + } + for (Stack =3D 0; Stack < NELEMENTS (mPciPrivateData.PciRootBridgeIo= [Socket]); Stack ++) { + if (mPciPrivateData.PciRootBridgeIo[Socket][Stack] =3D=3D NULL) { + continue; + } + PciTreeTraverse (Socket, Stack, CpuCsrAccessVarPtr->StackBus[Socke= t][Stack]); + } + } + PciPlatformPostInit (); + break; + + default: + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciPlatformHooks.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/= PciPlatform/PciPlatformHooks.h new file mode 100644 index 0000000000..b52b5de16e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPl= atformHooks.h @@ -0,0 +1,31 @@ +/** @file + This code supports a the private implementation + of the Legacy BIOS Platform protocol + + @copyright + Copyright 2004 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_PLATFORM_HOOKS_H_ +#define _PCI_PLATFORM_HOOKS_H_ + +#include + +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + EFI_PCI_CALLBACK_CONTEXT *Context + ); + +EFI_STATUS +PciTreeTraverse ( + IN UINT8 Socket, + IN UINT8 Stack, + IN UINT8 StartBus + ); + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciSupportLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciSupportLib.c new file mode 100644 index 0000000000..7b5d45711d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciSu= pportLib.c @@ -0,0 +1,108 @@ +/** @file + Support PCI chipset initialization. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PiDxe.h" +#include +#include +#include +#include +#include +#include "IndustryStandard/Pci.h" +#include "PciSupportLib.h" + +PCIE_STACK mPcieStack; + + +/** + + This routine is used to check whether the pci device is present + + @retval None + +**/ +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + OUT PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ) +// TODO: PciRootBridgeIo - add argument and description to function com= ment +// TODO: Pci - add argument and description to function comment +// TODO: Bus - add argument and description to function comment +// TODO: Device - add argument and description to function comment +// TODO: Func - add argument and description to function comment +// TODO: EFI_SUCCESS - add return value to function comment +// TODO: EFI_NOT_FOUND - add return value to function comment +{ + UINT64 Address; + UINT32 Dummy; + EFI_STATUS Status; + + Dummy =3D 0xFFFFFFFF; + // + // Create PCI address map in terms of Bus, Device and Func + // + Address =3D EFI_PCI_ADDRESS (Bus, Device, Func, 0); + + // + // Read the Vendor Id register + // + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + if ((Pci->Hdr).VendorId =3D=3D 0xFFFF) { + // + // The PCIe card could have been assigned a temporary bus number earli= er in + // the boot flow. Performing a write cycle can be used to cause the PC= Ie + // card to latch the new bus number. Try to writing the Vendor Id regi= ster, + // then recheck if the card is present. + // + Status =3D PciRootBridgeIo->Pci.Write( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + &Dummy + ); + + // + // Retry the previous read after the PCI write cycle. + // + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + } + + if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId !=3D 0xFFFF) { + // + // Read the entire config header for the device + // + Status =3D PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + sizeof (PCI_TYPE00) / sizeof (UINT32), + Pci + ); + + return TRUE; + } + + return FALSE; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatfor= m/PciSupportLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pci= Platform/PciSupportLib.h new file mode 100644 index 0000000000..e173125c97 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciSu= pportLib.h @@ -0,0 +1,46 @@ +/** @file + Support PCI chipset initialization. + + @copyright + Copyright 1999 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_PCI_SUPPORT_H_ +#define _EFI_PCI_SUPPORT_H_ + +#include + +#include + +typedef struct { + UINT8 PcieCapPtr; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT16 PcieLnkCap; + UINT16 PcieDevCap; + //Added to Support AtomicOp Request-->Start + UINT16 PcieDevCap2; + //Added to Support AtomicOp Request-->End +} PCIE_CAP_INFO; + +typedef struct { + INTN Top; + PCIE_CAP_INFO PcieCapInfo[FixedPcdGet32(PcdMaxNestedLevel)]; +} PCIE_STACK; + +extern PCIE_STACK mPcieStack; + +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + OUT PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ); + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformV= ariable/Pei/PlatformVariableInitPei.c b/Platform/Intel/WhitleyOpenBoardPkg/= Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.c new file mode 100644 index 0000000000..003787a163 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable= /Pei/PlatformVariableInitPei.c @@ -0,0 +1,274 @@ +/** @file + Platform variable initialization PEIM. + + This PEIM determines whether to load variable defaults. Ordinarily, the + decision is based on the boot mode, but an OEM hook is provided to overr= ide + that. The appropriate HOBs and PCDs are created to signal DXE code to up= date + the variable default values. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PlatformVariableInitPei.h" +#include +#include + +UINT16 BoardId =3D BOARD_ID_DEFAULT; + +EFI_PEI_PPI_DESCRIPTOR mPpiListPlatformVariableInit =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPlatformVariableInitPpiGuid, + NULL +}; + +/** +Apply platform variable defaults. + +Create HOBs and set PCDs to prompt the (re-)loading of variable defaults. +Each step is attempted regardless of whether the previous steps succeeded. +If multiple errors occur, only the last error code is returned. + +@param[in] Events Bitmap of events that occurred. +@param[in] DefaultId Default store ID, STANDARD or MANUFACTURING. + +@retval EFI_SUCCESS All steps completed successfully. +@retval EFI_OUT_OF_RESOURCES One of the HOBs could not be created. +@retval EFI_NOT_FOUND The default data could not be found in FFS. +**/ + +EFI_STATUS +ApplyPlatformVariableDefaults( + IN UINT8 Events, + IN UINT16 DefaultId + ) +{ + VOID *Hob; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + DEBUG((DEBUG_INFO, "Applying platform variable defaults:\n")); + DEBUG((DEBUG_INFO, " Events =3D 0x%02x\n", Events)); + DEBUG((DEBUG_INFO, " DefaultId =3D 0x%04x\n", DefaultId)); + + // + // Assume success up front. This will be overwritten if errors occur. + // + ReturnStatus =3D EFI_SUCCESS; + + // + // Send the bitmap of events to the platform variable DXE driver. + // + Hob =3D BuildGuidDataHob(&gPlatformVariableHobGuid, &Events, sizeof(Even= ts)); + if (Hob =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Create platform var event HOB: %r!\n", EFI_OUT_OF= _RESOURCES)); + ReturnStatus =3D EFI_OUT_OF_RESOURCES; + } + + // + // Locate variable default data in FFS and send it to the core variable = DXE + // driver to write. + // + Status =3D CreateDefaultVariableHob(DefaultId, BoardId); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "create default var HOB: %r!\n", Status)); + ReturnStatus =3D Status; + } + + // + // Set the PCD SKU ID. + // + LibPcdSetSku(BoardId); + + // + // Set the PCD default store ID. + // + Status =3D PcdSet16S(PcdSetNvStoreDefaultId, DefaultId); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "setNVstore default ID PCD: %r!\n", Status)); + ReturnStatus =3D Status; + } + + return ReturnStatus; +} + +/** +Perform the default variable initializations after variable service is rea= dy. + +@param[in] PeiServices General purpose services available to every = PEIM. +@param[in] NotifyDescriptor Pointer to Notify PPI descriptor. +@param[in] Interface Pointer to PPI. + +@retval EFI_SUCCESS Default setting is initialized into variable. +@retval Other values Can't find the matched default setting. +**/ +EFI_STATUS +EFIAPI +PlatformVariablePeiInit( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Interface +) +{ + EFI_STATUS Status; + UINT8 *SystemConfiguration; + EFI_GUID *SystemConfigurationGuid; + UINTN DataSize; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINT8 Events; + UINT16 DefaultId; + BOOLEAN ApplyDefaults; + + SystemConfigurationGuid =3D PcdGetPtr(PcdSetupVariableGuid); + Events =3D 0; + DefaultId =3D EFI_HII_DEFAULT_CLASS_STANDARD; + + if (PlatformVariableHookForHobGeneration(Interface, &Events, &DefaultId)= ) { + // + // Use events bitmap and default ID returned by PlatformVariableHook. + // + ApplyDefaults =3D TRUE; + } + else { + // + // If the setup variable does not exist (yet), defaults should be appl= ied. + // + VariableServices =3D (EFI_PEI_READ_ONLY_VARIABLE2_PPI *)Interface; + SystemConfiguration =3D NULL; + DataSize =3D 0; + Status =3D VariableServices->GetVariable( + VariableServices, + PLATFORM_SETUP_VARIABLE_NAME, + SystemConfigurationGuid, + NULL, + &DataSize, + SystemConfiguration + ); + // + // Setup variable is not found. So, set the default setting. + // + if (Status =3D=3D EFI_NOT_FOUND) { + Events =3D NULL_VARIABLE_EVENT; + DefaultId =3D EFI_HII_DEFAULT_CLASS_STANDARD; + ApplyDefaults =3D TRUE; + } + else { + ApplyDefaults =3D FALSE; + } + } + + + if (ApplyDefaults) { + Status =3D ApplyPlatformVariableDefaults(Events, DefaultId); + } + else { + // + // Normal case boot flow + // + Events =3D 0; // no events occurred + BuildGuidDataHob (&gPlatformVariableHobGuid, &Events, sizeof (UINT8)); + + // + // Patch RP variable value with PC variable in the begining of PEI + // + Status =3D CreateRPVariableHob (EFI_HII_DEFAULT_CLASS_STANDARD, BoardI= d); + } + + PeiServicesInstallPpi (&mPpiListPlatformVariableInit); + return Status; +} + + +/** +Variable Init BootMode CallBack +Prepare Knob values based on boot mode +Execute after discovering BootMode + +@param[in] PeiServices General purpose services available to every = PEIM. +@param[in] NotifyDescriptor Pointer to Notify PPI descriptor. +@param[in] Interface Pointer to PPI. + +@retval EFI_SUCCESS Knob Values. +@retval Other values +**/ +EFI_STATUS +EFIAPI +VariableInitBootModeCallBack( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Interface +) { + EFI_BOOT_MODE BootMode; + BOOLEAN ApplyDefaults; + UINT8 Events; + UINT16 DefaultId; + EFI_STATUS Status; + + Events =3D 0; + DefaultId =3D EFI_HII_DEFAULT_CLASS_STANDARD; + ApplyDefaults =3D FALSE; + + // + // Certain boot modes require defaults to be (re-)applied. + // + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + BootMode =3D BOOT_WITH_DEFAULT_SETTINGS; + } + if (BootMode =3D=3D BOOT_WITH_MFG_MODE_SETTINGS) { + Events =3D MFG_MODE_EVENT; + DefaultId =3D EFI_HII_DEFAULT_CLASS_MANUFACTURING; + ApplyDefaults =3D TRUE; + } + else if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + Events =3D RECOVERY_MODE_EVENT; + DefaultId =3D EFI_HII_DEFAULT_CLASS_STANDARD; + ApplyDefaults =3D TRUE; + } + else if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Events =3D CMOS_CLEAR_EVENT; + DefaultId =3D EFI_HII_DEFAULT_CLASS_STANDARD; + ApplyDefaults =3D TRUE; + } + if (ApplyDefaults) { + Status =3D ApplyPlatformVariableDefaults(Events, DefaultId); + } + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mVariableNotifyList[] =3D { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK), + &gEfiPeiReadOnlyVariable2PpiGuid, + PlatformVariablePeiInit + }, + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMI= NATE_LIST), + &gUpdateBootModePpiGuid, + VariableInitBootModeCallBack + } +}; + +EFI_STATUS +EFIAPI +PlatformVariableInitPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +/*++ + +--*/ +{ + EFI_STATUS Status; + + PlatformVariableHookForEntry(); + + // Register notify to set default variable once variable service is read= y. + // + Status =3D PeiServicesNotifyPpi(&mVariableNotifyList[0]); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformV= ariable/Pei/PlatformVariableInitPei.h b/Platform/Intel/WhitleyOpenBoardPkg/= Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.h new file mode 100644 index 0000000000..f4701426ff --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable= /Pei/PlatformVariableInitPei.h @@ -0,0 +1,41 @@ +/** @file + Platform variable initialization PEIM. + + This PEIM determines whether to load variable defaults. Ordinarily, the + decision is based on the boot mode, but an OEM hook is provided to overr= ide + that. The appropriate HOBs and PCDs are created to signal DXE code to up= date + the variable default values. + + @copyright + Copyright 2012 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_VARIABLE_INIT_PEI_H_ +#define _PLATFORM_VARIABLE_INIT_PEI_H_ + +#include + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// We only have one ID for all the platforms. +// +#define BOARD_ID_DEFAULT 0 + +#endif // #ifndef _PLATFORM_VARIABLE_INIT_PEI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformV= ariable/Pei/PlatformVariableInitPei.inf b/Platform/Intel/WhitleyOpenBoardPk= g/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf new file mode 100644 index 0000000000..02d216206e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable= /Pei/PlatformVariableInitPei.inf @@ -0,0 +1,58 @@ +## @file +# Platform variable initialization PEIM. +# +# This PEIM determines whether to load variable defaults. Ordinarily, the +# decision is based on the boot mode, but an OEM hook is provided to overr= ide +# that. The appropriate HOBs and PCDs are created to signal DXE code to up= date +# the variable default values. +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVariableInitPei + FILE_GUID =3D B88303F6-2E0E-41cc-8510-F5892BF1D9D9 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D PlatformVariableInitPeiEntry + +[Sources] + PlatformVariableInitPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + IoLib + PciLib + PcdLib + MultiPlatSupportLib + PlatformVariableHookLib + PlatformSetupVariableSyncLib + +[Pcd] + gPlatformTokenSpaceGuid.PcdSetupVariableGuid ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNvStoreDefaultId ## PRODUCES + +[Guids] + gPlatformVariableHobGuid ## PRODUCES = ## HOB + +[Ppis] + gPlatformVariableInitPpiGuid ## PRODUCES + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSU= MES ## NOTIFY + gUpdateBootModePpiGuid ## CONSUMES + +[Depex] + TRUE --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 13/17] WhitleyOpenBoardPkg: Add UBA Modules Date: Mon, 12 Jul 2021 17:41:27 -0700 Message-Id: <20210713004131.1782-14-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: p6KIKJpGAuYUwqooiwVgWNfYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136938; bh=tHmdVNA57N+AOpLNbwCkowMlLPRJ+AHSh6NSUtRRBY0=; h=Cc:Date:From:Reply-To:Subject:To; b=WhVtJYjAsMNrfKHKXKFEuTuUjYmuqDDfcu2+l7N6eDElbefarbSJrGaz57XngpBks/J 1Uih2GVNPsYtNcp04zkI1kFQP01z/4qKiuOM8rcRIQWw7jGVhKl2gYBt9T+QU0q/aQAd1 uXqncUNTT/EbPDdZZf8iAPiTfYIn57bIulc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136940730100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../Uba/BoardInit/Dxe/BoardInitDxe.c | 87 ++ .../Uba/BoardInit/Dxe/BoardInitDxe.h | 30 + .../Uba/BoardInit/Dxe/BoardInitDxe.inf | 70 + .../Uba/BoardInit/Pei/BoardInitPei.c | 48 + .../Uba/BoardInit/Pei/BoardInitPei.h | 20 + .../Uba/BoardInit/Pei/BoardInitPei.inf | 55 + .../Uba/CfgDb/Dxe/CfgDbDxe.c | 518 +++++++ .../Uba/CfgDb/Dxe/CfgDbDxe.h | 32 + .../Uba/CfgDb/Dxe/CfgDbDxe.inf | 54 + .../Uba/CfgDb/Pei/CfgDbPei.c | 803 ++++++++++ .../Uba/CfgDb/Pei/CfgDbPei.h | 33 + .../Uba/CfgDb/Pei/CfgDbPei.inf | 54 + .../WhitleyOpenBoardPkg/Uba/UbaCommon.dsc | 29 + .../WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf | 16 + .../Uba/UbaDxeRpBoards.fdf | 22 + .../SystemBoardInfoDxe/SystemBoardInfoDxe.c | 206 +++ .../SystemBoardInfoDxe/SystemBoardInfoDxe.h | 33 + .../SystemBoardInfoDxe/SystemBoardInfoDxe.inf | 45 + .../SystemConfigUpdateDxe.c | 94 ++ .../SystemConfigUpdateDxe.h | 30 + .../SystemConfigUpdateDxe.inf | 48 + .../Uba/UbaMain/Common/Pei/BoardInfo.c | 69 + .../Uba/UbaMain/Common/Pei/Clockgen.c | 27 + .../Uba/UbaMain/Common/Pei/ClocksConfig.c | 177 +++ .../UbaMain/Common/Pei/GpioPlatformConfig.c | 166 ++ .../UbaMain/Common/Pei/HsioPtssTableConfig.c | 460 ++++++ .../Common/Pei/IioBifurcationSlotTable.h | 156 ++ .../UbaMain/Common/Pei/IioPortBifurcation.c | 913 +++++++++++ .../Common/Pei/IioPortBifurcationVer1.c | 1356 +++++++++++++++++ .../UbaMain/Common/Pei/PchHsioPtssTables.h | 51 + .../Common/Pei/PchLbgHsioPtssTablesBx.c | 44 + .../Common/Pei/PchLbgHsioPtssTablesBx.h | 18 + .../Common/Pei/PchLbgHsioPtssTablesBx_Ext.c | 44 + .../Common/Pei/PchLbgHsioPtssTablesBx_Ext.h | 20 + .../Common/Pei/PchLbgHsioPtssTablesSx.c | 27 + .../Common/Pei/PchLbgHsioPtssTablesSx.h | 21 + .../Common/Pei/PchLbgHsioPtssTablesSx_Ext.c | 44 + .../Common/Pei/PchLbgHsioPtssTablesSx_Ext.h | 21 + .../Common/Pei/PeiCommonBoardInitLib.c | 75 + .../Common/Pei/PeiCommonBoardInitLib.h | 55 + .../Common/Pei/PeiCommonBoardInitLib.inf | 76 + .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 107 ++ .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 161 ++ .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 + .../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 108 ++ .../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 + .../SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 + .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 124 ++ .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 + .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 + .../TypeCooperCityRP/Pei/AcpiTablePcds.c | 51 + .../UbaMain/TypeCooperCityRP/Pei/GpioTable.c | 297 ++++ .../TypeCooperCityRP/Pei/IioBifurInit.c | 393 +++++ .../UbaMain/TypeCooperCityRP/Pei/KtiEparam.c | 241 +++ .../UbaMain/TypeCooperCityRP/Pei/PcdData.c | 259 ++++ .../TypeCooperCityRP/Pei/PchEarlyUpdate.c | 81 + .../TypeCooperCityRP/Pei/PeiBoardInit.h | 96 ++ .../TypeCooperCityRP/Pei/PeiBoardInitLib.c | 224 +++ .../TypeCooperCityRP/Pei/PeiBoardInitLib.inf | 163 ++ .../UbaMain/TypeCooperCityRP/Pei/SlotTable.c | 164 ++ .../TypeCooperCityRP/Pei/SoftStrapFixup.c | 110 ++ .../Uba/UbaMain/TypeCooperCityRP/Pei/UsbOC.c | 123 ++ .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 99 ++ .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 118 ++ .../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 47 + .../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 115 ++ .../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 + .../SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 47 + .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 127 ++ .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 + .../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 + .../TypeWilsonCityRP/Pei/AcpiTablePcds.c | 53 + .../UbaMain/TypeWilsonCityRP/Pei/GpioTable.c | 287 ++++ .../TypeWilsonCityRP/Pei/IioBifurInit.c | 387 +++++ .../UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c | 107 ++ .../UbaMain/TypeWilsonCityRP/Pei/PcdData.c | 274 ++++ .../TypeWilsonCityRP/Pei/PchEarlyUpdate.c | 92 ++ .../TypeWilsonCityRP/Pei/PeiBoardInit.h | 77 + .../TypeWilsonCityRP/Pei/PeiBoardInitLib.c | 156 ++ .../TypeWilsonCityRP/Pei/PeiBoardInitLib.inf | 166 ++ .../UbaMain/TypeWilsonCityRP/Pei/SlotTable.c | 171 +++ .../TypeWilsonCityRP/Pei/SoftStrapFixup.c | 120 ++ .../Uba/UbaMain/TypeWilsonCityRP/Pei/UsbOC.c | 126 ++ .../Intel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf | 24 + .../WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 44 + .../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.c | 43 + .../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.h | 20 + .../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.inf | 50 + 88 files changed, 11951 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/Bo= ardInitDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/Bo= ardInitDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/Bo= ardInitDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/Bo= ardInitPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/Bo= ardInitPei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/Bo= ardInitPei.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbD= xe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbD= xe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbD= xe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbP= ei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbP= ei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbP= ei.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaCommon.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.f= df create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemBoardInfoDxe/SystemBoardInfoDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemBoardInfoDxe/SystemBoardInfoDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemBoardInfoDxe/SystemBoardInfoDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/D= xe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/BoardInfo.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/Clockgen.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/ClocksConfig.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/GpioPlatformConfig.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/HsioPtssTableConfig.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/IioBifurcationSlotTable.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/IioPortBifurcation.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/IioPortBifurcationVer1.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchHsioPtssTables.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesBx.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesBx.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesBx_Ext.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesBx_Ext.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesSx.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesSx.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesSx_Ext.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PchLbgHsioPtssTablesSx_Ext.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PeiCommonBoardInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PeiCommonBoardInitLib.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/PeiCommonBoardInitLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/AcpiTablePcds.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/GpioTable.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/IioBifurInit.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/KtiEparam.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/PcdData.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/PchEarlyUpdate.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/PeiBoardInit.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/PeiBoardInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/PeiBoardInitLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/SlotTable.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/SoftStrapFixup.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/UsbOC.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/AcpiTablePcds.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/GpioTable.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/IioBifurInit.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/KtiEparam.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/PcdData.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/PchEarlyUpdate.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/PeiBoardInit.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/PeiBoardInitLib.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/PeiBoardInitLib.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/SlotTable.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/SoftStrapFixup.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/UsbOC.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pe= i/UpdatePcdsPei.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pe= i/UpdatePcdsPei.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pe= i/UpdatePcdsPei.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c new file mode 100644 index 0000000000..d8274fa7ad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c @@ -0,0 +1,87 @@ +/** @file + BOARD INIT DXE Driver. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitDxe.h" +#include + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +BoardInitDxeDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + UINT32 PlatformType =3D 0; + EFI_HANDLE Handle =3D NULL; + + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->GetSku( + UbaConfigProtocol, + &PlatformType, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=3D%d\n", PlatformT= ype)); + + //according to the platform type to install different dummy maker. + //later, the PEIM will be loaded by the dependency. + switch(PlatformType) + { + case TypeWilsonCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeWilsonCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeCooperCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeCooperCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + default: + // CAN'T GO TO HERE. + ASSERT_EFI_ERROR (FALSE); + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.h new file mode 100644 index 0000000000..f9825eafb5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.h @@ -0,0 +1,30 @@ +/** @file + BOARD INIT DXE Driver. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_INIT_DXE_H_ +#define _BOARD_INIT_DXE_H_ + +#include +#include +#include // For Hob + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#endif // _BOARD_INIT_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe= .inf new file mode 100644 index 0000000000..206d95658a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf @@ -0,0 +1,70 @@ +## @file +# Uba init for multi-boards support in DXE phase. +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitDxe + FILE_GUID =3D 69E6DD6D-F09E-485f-9627-EB70E9CFC82A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D BoardInitDxeDriverEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + BoardInitDxe.c + BoardInitDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + + +[LibraryClasses] + DebugLib + IoLib + HobLib + UefiLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + PrintLib + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid #CONSUMER + gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER + gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER + gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER + gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + gUbaConfigDatabaseProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInit= Pei.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei.c new file mode 100644 index 0000000000..9200e84023 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei.c @@ -0,0 +1,48 @@ +/** @file + Board Init PEIM. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitPei.h" + +EFI_PEI_PPI_DESCRIPTOR mPpiListBoardInit =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardInitGuid, + NULL +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +BoardInitPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices +) +{ + EFI_STATUS Status; + DEBUG ((DEBUG_INFO, "UBA :UbaMainPeimEntry!\n")); + + // + // Inform board init ready, then peims which will use board init data su= ch as + // pcd data in uba database can take gBoardInitGuid as dependency. + // + Status =3D PeiServicesInstallPpi (&mPpiListBoardInit); + if (Status !=3D EFI_SUCCESS) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInit= Pei.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei.h new file mode 100644 index 0000000000..9e0a7343c6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei.h @@ -0,0 +1,20 @@ +/** @file + Board Init PEIM. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_INIT_PEI_PEIM_H_ +#define _BOARD_INIT_PEI_PEIM_H_ + +#include +#include +#include +#include +#include +#include + +#endif // _BOARD_INIT_PEI_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInit= Pei.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei= .inf new file mode 100644 index 0000000000..f09a3934a2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Pei/BoardInitPei.inf @@ -0,0 +1,55 @@ +## @file +# Board Init for multi-boards support in PEI phase. +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitPeim + FILE_GUID =3D 64980BB9-7BA3-4cb0-AA83-FE396A7F6724 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D BoardInitPeimEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + BoardInitPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[LibraryClasses] + BaseLib + PeiServicesLib + PeimEntryPoint + DebugLib + +[Guids] + gEfiPlatformInfoGuid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gBoardInitGuid ## PRODUCES + +[Pcd] + +[FixedPcd] + +[Depex] + gUbaConfigDatabasePpiGuid AND + gEfiPeiReadOnlyVariable2PpiGuid AND + gEfiPlatformInfoGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.c b/= Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.c new file mode 100644 index 0000000000..9a524a0d00 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.c @@ -0,0 +1,518 @@ +/** @file + UbaConfigDatabaseDxe Driver. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "CfgDbDxe.h" + +#include // For Hob + +#include +#include +#include +#include +#include +#include +#include + +/** + Internal function for getting the platform record node in the database. + + @param This uba Protocol instance. + @param SkuNode The pointer to pointer of Platform record = node. + + @retval EFI_NOT_FOUND Platform record not found. + @retval EFI_SUCCESS Platform found. +**/ +EFI_STATUS +InternalGetSkuNode ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + OUT UBA_BOARD_NODE **SkuNode + ) +{ + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + UbaDxePrivate =3D NULL; + + UbaDxePrivate =3D PRIVATE_DATA_FROM_PROTOCOL (This); + *SkuNode =3D UbaDxePrivate->CurrentSku; + + return EFI_SUCCESS; +} + +/** + Internal function for init the platform record to database. + Create the connections between UBA_BOARD_NODE and UBA_DXE_PRIVATE_DATA + + @param This UBA Protocol instance. + @param BoardId The platform type. + @param BoardGuid The platform GUID. + @param BoardName The platform user friendly name. + @param SkuNode The pointer to pointer of Platform record = node. + + @retval EFI_ALREADY_STARTED Platform record already exist. + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalInitSkuDxe ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN UINT32 BoardId, + IN EFI_GUID *BoardGuid, OPTIONAL + IN CHAR8 *BoardName, OPTIONAL + OUT UBA_BOARD_NODE **SkuNode OPTIONAL + ) +{ + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + UBA_BOARD_NODE *NewSkuNode; + UbaDxePrivate =3D NULL; + NewSkuNode =3D NULL; + + UbaDxePrivate =3D PRIVATE_DATA_FROM_PROTOCOL (This); + + NewSkuNode =3D AllocateZeroPool (sizeof (UBA_BOARD_NODE)); + if (NewSkuNode =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NewSkuNode->Signature =3D UBA_BOARD_SIGNATURE; + NewSkuNode->Version =3D UBA_BOARD_VERSION; + NewSkuNode->BoardId =3D BoardId; + + if (BoardName !=3D NULL) { + AsciiStrnCpyS (NewSkuNode->BoardName, AsciiStrSize (BoardName) / sizeo= f (CHAR8), BoardName, sizeof (NewSkuNode->BoardName) - 1); + } + + if (BoardGuid !=3D NULL) { + CopyMem (&NewSkuNode->BoardGuid, BoardGuid, sizeof (EFI_GUID)); + } + + // Initialize the list head for Datalink. + InitializeListHead (&NewSkuNode->DataLinkHead); + + if (SkuNode !=3D NULL) { + // Output the point of sku node. + *SkuNode =3D NewSkuNode; + // Pass the point to CurrentSku in UbaDxePrivate. + UbaDxePrivate->CurrentSku =3D NewSkuNode; + } + + return EFI_SUCCESS; +} + +/** + Internal function for adding new configuration data record to database. + + @param This uba Protocol instance. + @param ResId The resource ID. + @param Data Data pointer. + @param DataSize Data size. + + @retval EFI_INVALID_PARAMETER Parameter invalid. + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalAddNewConfigData ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + UBA_CONFIG_NODE *NewDataNode; + UBA_BOARD_NODE *SkuNode; + UbaDxePrivate =3D NULL; + NewDataNode =3D NULL; + SkuNode =3D NULL; + + if ((ResId =3D=3D NULL) || (Data =3D=3D NULL) || (DataSize <=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + UbaDxePrivate =3D PRIVATE_DATA_FROM_PROTOCOL (This); + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + NewDataNode =3D AllocateZeroPool (sizeof (UBA_CONFIG_NODE)); + if (NewDataNode =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NewDataNode->Signature =3D UBA_BOARD_SIGNATURE; + NewDataNode->Version =3D UBA_BOARD_VERSION; + NewDataNode->Handle =3D (EFI_HANDLE) (UINTN) UbaDxePrivate->Hand= leCount; + NewDataNode->Data =3D AllocateCopyPool (DataSize, Data); + NewDataNode->Size =3D (UINT32) DataSize; + + CopyMem (&NewDataNode->ResId, ResId, sizeof (EFI_GUID)); + + InsertTailList (&SkuNode->DataLinkHead, &NewDataNode->DataLink); + SkuNode->DataCount ++; + UbaDxePrivate->ConfigDataCount ++; + UbaDxePrivate->HandleCount ++; + + // + // This Protocol just install for Protocol notify + // The Protocol instance UbaCfgDbProtocol should not used + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &NewDataNode->ResId, + EFI_NATIVE_INTERFACE, + &UbaDxePrivate->UbaCfgDbProtocol + ); + ASSERT_EFI_ERROR (Status); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + + return EFI_SUCCESS; +} + +/** + Internal function for Getting configuration data from database. + + @param This uba Protocol instance. + @param SkuNode The platform node record. + @param ResId The resource ID. + @param Data Data pointer. + @param DataSize Data size pointer. + + @retval EFI_INVALID_PARAMETER Parameter invalid. + @retval EFI_NOT_FOUND Resource not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to copy the data. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalGetConfigData ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN UBA_BOARD_NODE *SkuNode, + IN EFI_GUID *ResId, + OUT VOID *Data, OPTIONAL + OUT UINTN *DataSize OPTIONAL + ) +{ + LIST_ENTRY *ListHead; + LIST_ENTRY *Link; + UBA_CONFIG_NODE *DataNode; + ListHead =3D NULL; + Link =3D NULL; + DataNode =3D NULL; + + if ((SkuNode =3D=3D NULL) || (ResId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ListHead =3D &SkuNode->DataLinkHead; + if (IsListEmpty (ListHead)) { + return EFI_NOT_FOUND; + } + + for (Link =3D GetFirstNode (ListHead); !IsNull (ListHead, Link); Link = =3D GetNextNode (ListHead, Link)) { + + DataNode =3D CONFIG_NODE_INSTANCE_FROM_THIS (Link); + ASSERT (DataNode !=3D NULL); + if (DataNode =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + if (CompareGuid (ResId, &DataNode->ResId)) { + + if (DataSize !=3D NULL) { + + if (*DataSize < DataNode->Size) { + *DataSize =3D DataNode->Size; + return EFI_BUFFER_TOO_SMALL; + } + + *DataSize =3D DataNode->Size; + + if (Data !=3D NULL) { + CopyMem (Data, DataNode->Data, DataNode->Size); + } + } + + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Get platform's GUID and user friendly name by BoardId. + + This is used when you need a BoardGuid to Add/Get platform data + + Core will create a new platform for you if the BoardId is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Protocol instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +DxeUbaGetPlatformSku ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + OUT UINT32 *BoardId, + OUT EFI_GUID *BoardGuid, OPTIONAL + OUT CHAR8 *BoardName OPTIONAL + ) +{ + EFI_STATUS Status; + UBA_BOARD_NODE *SkuNode; + SkuNode =3D NULL; + + Status =3D InternalGetSkuNode (This, &SkuNode); + + if (!EFI_ERROR (Status)) { + if (BoardId !=3D NULL) { + *BoardId =3D SkuNode->BoardId; + } + if (BoardName !=3D NULL) { + AsciiStrCpyS (BoardName, AsciiStrSize (SkuNode->BoardName) / sizeof = (CHAR8) , SkuNode->BoardName); + } + + if (BoardGuid !=3D NULL) { + CopyMem (BoardGuid, &SkuNode->BoardGuid, sizeof (EFI_GUID)); + } + + return EFI_SUCCESS; + } + + return Status; +} + +/** + Add configuration data to uba configuration database. + + @param This uba Protocol instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +DxeUbaAddData ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + UBA_BOARD_NODE *SkuNode; + SkuNode =3D NULL; + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InternalAddNewConfigData (This, ResId, Data, DataSize); + + return Status; +} + +/** + Get configuration data from uba configuration database. + + @param This uba Protocol instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +DxeUbaGetData ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + OUT UINTN *DataSize + ) +{ + EFI_STATUS Status; + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + UBA_BOARD_NODE *SkuNode; + UbaDxePrivate =3D NULL; + SkuNode =3D NULL; + + if ((ResId =3D=3D NULL) || (Data =3D=3D NULL) || (DataSize =3D=3D NULL))= { + return EFI_INVALID_PARAMETER; + } + + UbaDxePrivate =3D PRIVATE_DATA_FROM_PROTOCOL (This); + + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InternalGetConfigData (This, SkuNode, ResId, Data, DataSize); + if (!EFI_ERROR (Status)) { + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** + Internal function for getting current platform's configuration data from= HOB, which passed by PEIM. + + @param This uba Protocol instance. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalGetConfigDataFromHob ( + IN UBA_CONFIG_DATABASE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + UINT8 *HobDataStart; + UBA_CONFIG_HOB_HEADER *HobHeader; + UBA_CONFIG_HOB_FIELD *HobDataFieldStart; + UINTN Index; + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + UBA_BOARD_NODE *SkuNode; + HobHeader =3D NULL; + HobDataFieldStart =3D NULL; + UbaDxePrivate =3D NULL; + SkuNode =3D NULL; + + UbaDxePrivate =3D PRIVATE_DATA_FROM_PROTOCOL (This); + + Hob.Raw =3D GetFirstGuidHob (&gUbaCurrentConfigHobGuid); + ASSERT (Hob.Raw !=3D NULL); + if (Hob.Raw =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "UbaConfigDatabasedxeEntry: get first hob!\n")); + + HobDataStart =3D GET_GUID_HOB_DATA (Hob); + + HobHeader =3D (UBA_CONFIG_HOB_HEADER *) HobDataStart; + HobDataFieldStart =3D HobHeader->HobField; + + //Call internal function for SKU init, accroding to hob data. + Status =3D InternalInitSkuDxe (This, HobHeader->BoardId, &HobHeader->Boa= rdGuid, HobHeader->BoardName, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + // Obtain all data stored in the hob from PEI phase. + for (Index =3D 0; Index < HobHeader->DataCount; Index ++) { + Status =3D This->AddData ( + This, + &HobDataFieldStart[Index].ResId, + (VOID *) ((UINTN) HobDataFieldStart[Index].DataOffset= + (UINTN) HobHeader), + HobDataFieldStart[Index].Size + ); + ASSERT_EFI_ERROR (Status); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources +**/ +EFI_STATUS +EFIAPI +UbaConfigDatabaseEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UBA_DXE_PRIVATE_DATA *UbaDxePrivate; + EFI_HANDLE Handle; + UbaDxePrivate =3D NULL; + + UbaDxePrivate =3D AllocateZeroPool (sizeof (UBA_DXE_PRIVATE_DATA)); + ASSERT (UbaDxePrivate !=3D NULL); + if (UbaDxePrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + DEBUG ((DEBUG_INFO, "UbaConfigDatabasedxeEntry: after allocate Memory!\n= ")); + UbaDxePrivate->Signature =3D UBA_BOARD_SIGNATURE; + UbaDxePrivate->Version =3D UBA_BOARD_VERSION; + + UbaDxePrivate->ConfigDataCount =3D 0; + UbaDxePrivate->HandleCount =3D 0; + + UbaDxePrivate->UbaCfgDbProtocol.Signature =3D UBA_CONFIG_PROTOCOL_S= IGNATURE; + UbaDxePrivate->UbaCfgDbProtocol.Version =3D UBA_CONFIG_PROTOCOL_V= ERSION; + + UbaDxePrivate->UbaCfgDbProtocol.GetSku =3D DxeUbaGetPlatformSku; + UbaDxePrivate->UbaCfgDbProtocol.AddData =3D DxeUbaAddData; + UbaDxePrivate->UbaCfgDbProtocol.GetData =3D DxeUbaGetData; + + // + // Just produce our Protocol + // + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gUbaConfigDatabaseProtocolGuid, + EFI_NATIVE_INTERFACE, + &UbaDxePrivate->UbaCfgDbProtocol + ); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "UbaConfigDatabasedxeEntry: before get data from hob= !\n")); + // Init sku dxe and get configuration data from hob passed by PEIM. + Status =3D InternalGetConfigDataFromHob (&UbaDxePrivate->UbaCfgDbProtoco= l); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.h b/= Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.h new file mode 100644 index 0000000000..fdd958ca5a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.h @@ -0,0 +1,32 @@ +/** @file + UbaConfigDatabase Dxe Driver head file. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_DXE_H_ +#define _UBA_CONFIG_DATABASE_DXE_H_ + +#include +#include +#include +#include + +typedef struct _UBA_DXE_PRIVATE_DATA { + UINT32 Signature; + UINT32 Version; + + UINTN ConfigDataCount; //for AllC= onfigDataSize + UINTN HandleCount; + UBA_BOARD_NODE *CurrentSku; + + UBA_CONFIG_DATABASE_PROTOCOL UbaCfgDbProtocol; +} UBA_DXE_PRIVATE_DATA; + +#define PRIVATE_DATA_FROM_PROTOCOL(p) CR(p, UBA_DXE_PRIVATE_DATA, UbaCf= gDbProtocol, UBA_BOARD_SIGNATURE) + +#endif // _UBA_CONFIG_DATABASE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.inf = b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.inf new file mode 100644 index 0000000000..72e7e8ee71 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Dxe/CfgDbDxe.inf @@ -0,0 +1,54 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UbaConfigDatabaseDxe + FILE_GUID =3D E0471A15-76DC-4203-8B27-6DB4F8BA644A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D UbaConfigDatabaseEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + CfgDbDxe.c + CfgDbDxe.h + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + HobLib + UefiLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + +[Guids] + gUbaCurrentConfigHobGuid + +[Ppis] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + TRUE + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.c b/= Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.c new file mode 100644 index 0000000000..0a37d49998 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.c @@ -0,0 +1,803 @@ +/** @file + UbaConfigDatabase Peim. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "CfgDbPei.h" + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Internal function for getting the platform record node in the database. + + @param This uba Ppi instance. + @param SkuNode The pointer to pointer of Platform record = node. + + @retval EFI_NOT_FOUND Platform record not found. + @retval EFI_SUCCESS Platform found. +**/ +EFI_STATUS +InternalGetSkuNode ( + IN UBA_CONFIG_DATABASE_PPI *This, + OUT UBA_BOARD_NODE **SkuNode + ) +{ + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UbaPeimPrivate =3D NULL; + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + *SkuNode =3D UbaPeimPrivate->CurrentSku; + + return EFI_SUCCESS; +} + +/** + Internal function for init the platform record to database. + Create the connections between UBA_BOARD_NODE and UBA_PEIM_PRIVATE_DATA + + @param This uba Ppi instance. + @param BoardId The platform type. + @param BoardGuid The platform GUID. + @param BoardName The platform user friendly name. + @param SkuNode The pointer to pointer of Platform record = node. + + @retval EFI_ALREADY_STARTED Platform record already exist. + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalInitSku ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN UINT32 BoardId, + IN EFI_GUID *BoardGuid, OPTIONAL + IN CHAR8 *BoardName, OPTIONAL + OUT UBA_BOARD_NODE **SkuNode OPTIONAL + ) +{ + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UBA_BOARD_NODE *NewSkuNode; + UbaPeimPrivate =3D NULL; + NewSkuNode =3D NULL; + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + + NewSkuNode =3D AllocateZeroPool (sizeof (UBA_BOARD_NODE)); + if (NewSkuNode =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NewSkuNode->Signature =3D UBA_BOARD_SIGNATURE; + NewSkuNode->Version =3D UBA_BOARD_VERSION; + NewSkuNode->BoardId =3D BoardId; + + if (BoardName !=3D NULL) { + AsciiStrnCpyS (NewSkuNode->BoardName, sizeof (NewSkuNode->BoardName), = BoardName, sizeof (NewSkuNode->BoardName) - 1); + } + + if (BoardGuid !=3D NULL) { + CopyMem (&NewSkuNode->BoardGuid, BoardGuid, sizeof (EFI_GUID)); + } + + //Initialize the list head for Datalink. + InitializeListHead (&NewSkuNode->DataLinkHead); + + + if (SkuNode !=3D NULL) { + *SkuNode =3D NewSkuNode; + UbaPeimPrivate->CurrentSku =3D NewSkuNode; + } + + return EFI_SUCCESS; +} + +/** + Internal function for adding new configuration data record to database. + + @param This uba Ppi instance. + @param ResId The resource ID. + @param Data Data pointer. + @param DataSize Data size. + + @retval EFI_INVALID_PARAMETER Parameter invalid. + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalAddNewConfigData ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UBA_CONFIG_NODE *NewDataNode; + UBA_BOARD_NODE *SkuNode; + EFI_PEI_PPI_DESCRIPTOR *ConfigDataPpi; + UbaPeimPrivate =3D NULL; + NewDataNode =3D NULL; + SkuNode =3D NULL; + ConfigDataPpi =3D NULL; + + if ((ResId =3D=3D NULL) || (Data =3D=3D NULL) || (DataSize <=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + NewDataNode =3D AllocateZeroPool (sizeof (UBA_CONFIG_NODE)); + if (NewDataNode =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + NewDataNode->Signature =3D UBA_BOARD_SIGNATURE; + NewDataNode->Version =3D UBA_BOARD_VERSION; + NewDataNode->Handle =3D (EFI_HANDLE) (UINTN) UbaPeimPrivate->Han= dleCount; + NewDataNode->Data =3D AllocateCopyPool (DataSize, Data); + NewDataNode->Size =3D (UINT32) DataSize; + + CopyMem (&NewDataNode->ResId, ResId, sizeof (EFI_GUID)); + + InsertTailList (&SkuNode->DataLinkHead, &NewDataNode->DataLink); + SkuNode->DataCount ++; + UbaPeimPrivate->ConfigDataCount ++; + UbaPeimPrivate->HandleCount ++; + + // + // This PPI just install for NotifyPpi + // The PPI instance UbaCfgDbPpi should not used + // + ConfigDataPpi =3D AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (ConfigDataPpi =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ConfigDataPpi->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRI= PTOR_TERMINATE_LIST; + ConfigDataPpi->Guid =3D &NewDataNode->ResId; + ConfigDataPpi->Ppi =3D &UbaPeimPrivate->UbaCfgDbPpi; + + Status =3D PeiServicesInstallPpi (ConfigDataPpi); + ASSERT_EFI_ERROR (Status); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + + return EFI_SUCCESS; +} + +/** + Internal function for Getting configuration data from database. + + @param This uba Ppi instance. + @param SkuNode The platform node record. + @param ResId The resource ID. + @param Data Data pointer. + @param DataSize Data size pointer. + + @retval EFI_INVALID_PARAMETER Parameter invalid. + @retval EFI_NOT_FOUND Resource not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to copy the data. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalGetConfigData ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN UBA_BOARD_NODE *SkuNode, + IN EFI_GUID *ResId, + OUT VOID *Data, OPTIONAL + OUT UINTN *DataSize OPTIONAL + ) +{ + LIST_ENTRY *ListHead; + LIST_ENTRY *Link; + UBA_CONFIG_NODE *DataNode; + ListHead =3D NULL; + Link =3D NULL; + DataNode =3D NULL; + + if ((SkuNode =3D=3D NULL) || (ResId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ListHead =3D &SkuNode->DataLinkHead; + if (IsListEmpty (ListHead)) { + return EFI_NOT_FOUND; + } + + for (Link =3D GetFirstNode (ListHead); !IsNull (ListHead, Link); Link = =3D GetNextNode (ListHead, Link)) { + + DataNode =3D CONFIG_NODE_INSTANCE_FROM_THIS (Link); + ASSERT (DataNode !=3D NULL); + if (DataNode =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + if (CompareGuid (ResId, &DataNode->ResId)) { + + if (DataSize !=3D NULL) { + + if (*DataSize < DataNode->Size) { + *DataSize =3D DataNode->Size; + return EFI_BUFFER_TOO_SMALL; + } + + *DataSize =3D DataNode->Size; + + if (Data !=3D NULL) { + CopyMem (Data, DataNode->Data, DataNode->Size); + } + } + + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Covert the LIST_ENTRY pointer from CAR to RAM after memory init. + + @param Link The LIST_ENTRY pointer want to convert. + @param PtrPositive The pointer need positive fix. + @param PtrDelta The pointer delta value after memory init. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +PeiConvertListPointer ( + IN LIST_ENTRY *Link, + IN BOOLEAN PtrPositive, + IN UINTN PtrDelta + ) +{ + if (PtrPositive) { + Link->ForwardLink =3D (LIST_ENTRY *) ((UINTN) Link->ForwardLink + PtrD= elta); + Link->BackLink =3D (LIST_ENTRY *) ((UINTN) Link->BackLink + PtrDelt= a); + } else { + Link->ForwardLink =3D (LIST_ENTRY *) ((UINTN) Link->ForwardLink - PtrD= elta); + Link->BackLink =3D (LIST_ENTRY *) ((UINTN) Link->BackLink - PtrDelt= a); + } + + return EFI_SUCCESS; +} + +/** + Covert general pointer from CAR to RAM after memory init. + + @param Ptr The VOID pointer want to convert. + @param PtrPositive The pointer need positive fix. + @param PtrDelta The pointer delta value after memory init. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +PeiConvertVoidPointer ( + IN VOID **Ptr, + IN BOOLEAN PtrPositive, + IN UINTN PtrDelta + ) +{ + if (PtrPositive) { + *Ptr =3D (VOID *) ((UINTN)*Ptr + PtrDelta); + } else { + *Ptr =3D (VOID *) ((UINTN)*Ptr - PtrDelta); + } + + return EFI_SUCCESS; +} + +/** + Covert all pointers from CAR to RAM after memory init. + + @param This The uba Ppi pointer. + @param PtrPositive The pointer need positive fix. + @param PtrDelta The pointer delta value after memory init. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +PeiConvertDataPointer ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN BOOLEAN PtrPositive, + IN UINTN PtrDelta + ) +{ + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UBA_BOARD_NODE *SkuNode; + UBA_CONFIG_NODE *DataNode; + LIST_ENTRY *DataListHead; + LIST_ENTRY *DataLink; + UbaPeimPrivate =3D NULL; + SkuNode =3D NULL; + DataNode =3D NULL; + DataListHead =3D NULL; + DataLink =3D NULL; + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + if (UbaPeimPrivate->ThisAddress =3D=3D (UINTN) This) { + return EFI_SUCCESS; + } + + PeiConvertVoidPointer ((VOID**) &UbaPeimPrivate->CurrentSku, PtrPositive= , PtrDelta); + + SkuNode =3D UbaPeimPrivate->CurrentSku; + DataListHead =3D &SkuNode->DataLinkHead; + + PeiConvertListPointer (DataListHead, PtrPositive, PtrDelta); + + DataLink =3D DataListHead->ForwardLink; + while (DataListHead !=3D DataLink) { + + PeiConvertListPointer (DataLink, PtrPositive, PtrDelta); + DataNode =3D CONFIG_NODE_INSTANCE_FROM_THIS (DataLink); + PeiConvertVoidPointer (&DataNode->Data, PtrPositive, PtrDelta); + + DataLink =3D DataLink->ForwardLink; + } + + UbaPeimPrivate->ThisAddress =3D (UINTN) This; + + return EFI_SUCCESS; +} + +/** + Check whether the This pointer have been relocated after memory init, + if true, we need also relocate our own pointers in the heap, because cor= e won't + do it for us. + + @param This The uba Ppi pointer. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +PeiCheckPointerRelocated ( + IN UBA_CONFIG_DATABASE_PPI *This + ) +{ + EFI_STATUS Status; + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + BOOLEAN PtrPositive; + UINTN PtrDelta; + Status =3D EFI_SUCCESS; + UbaPeimPrivate =3D NULL; + PtrPositive =3D FALSE; + PtrDelta =3D 0; + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + if (UbaPeimPrivate->ThisAddress !=3D (UINTN) This) { + if ((UINTN) This > UbaPeimPrivate->ThisAddress) { + PtrPositive =3D TRUE; + PtrDelta =3D (UINTN) This - UbaPeimPrivate->ThisAddress; + } else { + PtrPositive =3D FALSE; + PtrDelta =3D UbaPeimPrivate->ThisAddress - (UINTN) This; + } + Status =3D PeiConvertDataPointer (This, PtrPositive, PtrDelta); + } + + return Status; +} + +/** + Set platform's GUID and user friendly name by BoardId. + + If the BoardId is not exist in database, it will create a new platform. + + @param This UBA Ppi instance. + @param BoardId The platform type, same define as Platform= .h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +PeiUbaInit ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN UINT32 BoardId, + IN EFI_GUID *BoardGuid, OPTIONAL + IN CHAR8 *BoardName OPTIONAL + ) +{ + EFI_STATUS Status; + UBA_BOARD_NODE *SkuNode; + Status =3D EFI_SUCCESS; + SkuNode =3D NULL; + + PeiCheckPointerRelocated (This); + Status =3D InternalInitSku (This, BoardId, BoardGuid, BoardName, &SkuNod= e); + return Status; +} + +/** + Get platform's GUID and user friendly name by BoardId. + + This is used when you need a BoardGuid to Add/Get platform data + + Core will create a new platform for you if the BoardId is not + recorded in database, and assgin a unique GUID for this platform. + + @param This uba Ppi instance. + @param BoardId The platform type, same define as Platform.h. + @param BoardGuid The GUID for this platform. + @param BoardName The user friendly name for this platform. + + @retval EFI_ALREADY_STARTED Create new for an exist platform. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +PeiUbaGetSku ( + IN UBA_CONFIG_DATABASE_PPI *This, + OUT UINT32 *BoardId, + OUT EFI_GUID *BoardGuid, OPTIONAL + OUT CHAR8 *BoardName OPTIONAL + ) +{ + EFI_STATUS Status; + UBA_BOARD_NODE *SkuNode; + SkuNode =3D NULL; + + PeiCheckPointerRelocated (This); + + Status =3D InternalGetSkuNode (This, &SkuNode); + + if (!EFI_ERROR (Status)) { + if (BoardId !=3D NULL) { + *BoardId =3D SkuNode->BoardId; + } + if (BoardName !=3D NULL) { + AsciiStrCpyS (BoardName, AsciiStrSize (SkuNode->BoardName) / sizeof = (CHAR8), SkuNode->BoardName); + } + + if (BoardGuid !=3D NULL) { + CopyMem (BoardGuid, &SkuNode->BoardGuid, sizeof (EFI_GUID)); + } + + return EFI_SUCCESS; + } + + return Status; +} + +/** + Add configuration data to uba configuration database. + + @param This uba Ppi instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize Size of data want to add into database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +PeiUbaAddData ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + IN VOID *Data, + IN UINTN DataSize + ) +{ + EFI_STATUS Status; + UBA_BOARD_NODE *SkuNode; + SkuNode =3D NULL; + + PeiCheckPointerRelocated (This); + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InternalAddNewConfigData (This, ResId, Data, DataSize); + return Status; +} + +/** + Get configuration data from uba configuration database. + + @param This uba Ppi instance. + @param ResId The configuration data resource id. + @param Data The data buffer pointer. + @param DataSize IN:Size of data want to get, OUT: Size of = data in database. + + @retval EFI_INVALID_PARAMETER Required parameters not correct. + @retval EFI_BUFFER_TOO_SMALL The DataSize of Data buffer is too small t= o get this configuration data + @retval EFI_OUT_OF_RESOURCES Resource not enough. + @retval EFI_NOT_FOUND Platform or data not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +PeiUbaGetData ( + IN UBA_CONFIG_DATABASE_PPI *This, + IN EFI_GUID *ResId, + OUT VOID *Data, + OUT UINTN *DataSize + ) +{ + EFI_STATUS Status; + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UBA_BOARD_NODE *SkuNode; + UbaPeimPrivate =3D NULL; + SkuNode =3D NULL; + + if ((ResId =3D=3D NULL) || (Data =3D=3D NULL) || (DataSize =3D=3D NULL))= { + return EFI_INVALID_PARAMETER; + } + + PeiCheckPointerRelocated (This); + + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (This); + + Status =3D InternalGetSkuNode (This, &SkuNode); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D InternalGetConfigData (This, SkuNode, ResId, Data, DataSize); + if (!EFI_ERROR (Status)) { + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** + Internal function for creating a HOB for platform data, + and copy all the platform information and configuration data to the HOB, + it will be passed to DXE driver. + + @param SkuNode The platform node in database. + @param HobGuid The Hob GUID want to build. + + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +InternalCreateHobForSkuNode ( + IN UBA_BOARD_NODE *SkuNode, + IN EFI_GUID *HobGuid + ) +{ + UINT8 *HobData; + UBA_CONFIG_HOB_HEADER *HobHeader; + UBA_CONFIG_HOB_FIELD *HobDataFieldStart; + UINT8 *ConfigDataHobPtr; + UINTN DataLength; + UINTN Index; + LIST_ENTRY *ListHead; + LIST_ENTRY *Link; + UBA_CONFIG_NODE *DataNode; + HobData =3D NULL; + HobHeader =3D NULL; + HobDataFieldStart =3D NULL; + ConfigDataHobPtr =3D NULL; + DataLength =3D 0; + ListHead =3D NULL; + Link =3D NULL; + DataNode =3D NULL; + + if (SkuNode->DataCount !=3D 0) { + DataLength =3D sizeof (UBA_CONFIG_HOB_HEADER) + + sizeof (UBA_CONFIG_HOB_FIELD) * (SkuNode->DataCount - 1); + + // + // Get config data size + // + ListHead =3D &SkuNode->DataLinkHead; + for (Link =3D GetFirstNode (ListHead); !IsNull (ListHead, Link); Link = =3D GetNextNode (ListHead, Link)) { + DataNode =3D CONFIG_NODE_INSTANCE_FROM_THIS (Link); + DataLength +=3D DataNode->Size; + } + + HobData =3D BuildGuidHob (HobGuid, DataLength); + ASSERT (HobData !=3D NULL); + if (HobData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + HobHeader =3D (UBA_CONFIG_HOB_HEADER *) HobData; + HobDataFieldStart =3D HobHeader->HobField; + ConfigDataHobPtr =3D (UINT8 *) HobDataFieldStart + (sizeof (UBA_CONFI= G_HOB_FIELD) * SkuNode->DataCount); + + // + // Copy our HOB header + // + HobHeader->Signature =3D UBA_CONFIG_HOB_SIGNATURE; + HobHeader->Version =3D UBA_CONFIG_HOB_VERSION; + HobHeader->HobLength =3D DataLength; + CopyGuid (&HobHeader->DataGuid, HobGuid); + + HobHeader->BoardId =3D SkuNode->BoardId; + HobHeader->DataCount =3D SkuNode->DataCount; + CopyGuid (&HobHeader->BoardGuid, &SkuNode->BoardGuid); + CopyMem (HobHeader->BoardName, SkuNode->BoardName, AsciiStrSize (SkuNo= de->BoardName)); + + // + // Copy N * (UBA_CONFIG_HOB_NODE & UBA_CONFIG_HOB_NODE->Data) + // + Index =3D 0; + ListHead =3D &SkuNode->DataLinkHead; + for (Link =3D GetFirstNode (ListHead); !IsNull (ListHead, Link); Link = =3D GetNextNode (ListHead, Link)) { + DataNode =3D CONFIG_NODE_INSTANCE_FROM_THIS (Link); + ASSERT (DataNode !=3D NULL); + if (DataNode =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + HobDataFieldStart[Index].Size =3D DataNode->Size; + HobDataFieldStart[Index].Signature =3D DataNode->Signature; + HobDataFieldStart[Index].Version =3D DataNode->Version; + CopyGuid (&HobDataFieldStart[Index].ResId, &DataNode->ResId); + + CopyMem (ConfigDataHobPtr, DataNode->Data, DataNode->Size); + + // + // Fix the config data pointer after memory copy + // Set the pointer address into memory in HOB + // + HobDataFieldStart[Index].DataOffset =3D ((UINTN) ConfigDataHobPtr - = (UINTN) HobHeader); + + Index ++; + ConfigDataHobPtr +=3D DataNode->Size; + } + } + + return EFI_SUCCESS; +} + +/** + End of PEI phase callback, we need build configuration data HOB in this = callback, + it will pass to DXE driver. + + @param PeiServices The PEI service pointer. + @param NotifyDescriptor The notify descriptor. + @param Ppi The PPI was notified. + + @retval EFI_OUT_OF_RESOURCES No enough resource. + @retval EFI_NOT_FOUND Platform/data not found. + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EndOfPeiPpiNotifyCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UBA_BOARD_NODE *SkuNode; + UbaPeimPrivate =3D NULL; + SkuNode =3D NULL; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + (VOID**) &UbaConfigPpi + ); + ASSERT_EFI_ERROR (Status); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + + PeiCheckPointerRelocated (UbaConfigPpi); + + // + // Build GUID data HOB for current platform configuration data + // + UbaPeimPrivate =3D PRIVATE_DATA_FROM_PPI (UbaConfigPpi); + if (UbaPeimPrivate->CurrentSku !=3D NULL) { + SkuNode =3D UbaPeimPrivate->CurrentSku; + Status =3D InternalCreateHobForSkuNode (SkuNode, &gUbaCurrentConfigHob= Guid); + ASSERT_EFI_ERROR (Status); + if (Status !=3D EFI_SUCCESS) { + return Status; + } + } + + // + // Other will not pass to DXE because it's useless + // + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMIN= ATE_LIST, + &gEfiEndOfPeiSignalPpiGuid, + EndOfPeiPpiNotifyCallback + } +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI +**/ +EFI_STATUS +EFIAPI +UbaConfigDatabasePeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UBA_PEIM_PRIVATE_DATA *UbaPeimPrivate; + UbaPeimPrivate =3D NULL; + + UbaPeimPrivate =3D AllocateZeroPool (sizeof (UBA_PEIM_PRIVATE_DATA)); + if (UbaPeimPrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "UbaConfigDatabasePeimEntry!\n")); + UbaPeimPrivate->Signature =3D UBA_BOARD_SIGNATURE; + UbaPeimPrivate->Version =3D UBA_BOARD_VERSION; + + UbaPeimPrivate->ConfigDataCount =3D 0; + UbaPeimPrivate->HandleCount =3D 0; + UbaPeimPrivate->ThisAddress =3D (UINTN) &UbaPeimPrivate->UbaCfg= DbPpi; + + UbaPeimPrivate->UbaPeimPpiList.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EF= I_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + UbaPeimPrivate->UbaPeimPpiList.Guid =3D &gUbaConfigDatabasePpiGuid; + UbaPeimPrivate->UbaPeimPpiList.Ppi =3D &UbaPeimPrivate->UbaCfgDbPpi; + + UbaPeimPrivate->UbaCfgDbPpi.Signature =3D UBA_CONFIG_PPI_SIGNATURE; + UbaPeimPrivate->UbaCfgDbPpi.Version =3D UBA_CONFIG_PPI_VERSION; + + UbaPeimPrivate->UbaCfgDbPpi.InitSku =3D PeiUbaInit; + UbaPeimPrivate->UbaCfgDbPpi.GetSku =3D PeiUbaGetSku; + + UbaPeimPrivate->UbaCfgDbPpi.AddData =3D PeiUbaAddData; + UbaPeimPrivate->UbaCfgDbPpi.GetData =3D PeiUbaGetData; + + // + // Just produce our PPI + // + Status =3D PeiServicesInstallPpi (&UbaPeimPrivate->UbaPeimPpiList); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D PeiServicesNotifyPpi (&mNotifyList[0]); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.h b/= Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.h new file mode 100644 index 0000000000..4a517c734c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.h @@ -0,0 +1,33 @@ +/** @file + UbaConfigDatabase Peim head file. + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UBA_CONFIG_DATABASE_PEIM_H_ +#define _UBA_CONFIG_DATABASE_PEIM_H_ + +#include +#include +#include +#include + +typedef struct _UBA_PEIM_PRIVATE_DATA { + UINT32 Signature; + UINT32 Version; + + UINTN ConfigDataCount; //for AllConfigDat= aSize + UINTN HandleCount; + UBA_BOARD_NODE *CurrentSku; + UINTN ThisAddress; + + UBA_CONFIG_DATABASE_PPI UbaCfgDbPpi; + EFI_PEI_PPI_DESCRIPTOR UbaPeimPpiList; +} UBA_PEIM_PRIVATE_DATA; + +#define PRIVATE_DATA_FROM_PPI(p) CR(p, UBA_PEIM_PRIVATE_DATA, UbaCfgDbP= pi, UBA_BOARD_SIGNATURE) + +#endif // _UBA_CONFIG_DATABASE_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.inf = b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.inf new file mode 100644 index 0000000000..454651e8c1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/CfgDb/Pei/CfgDbPei.inf @@ -0,0 +1,54 @@ +## @file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UbaConfigDatabasePei + FILE_GUID =3D 2C181BE1-8BAC-4433-873C-E5074CB5A723 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D UbaConfigDatabasePeimEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + CfgDbPei.c + CfgDbPei.h + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + HobLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + PeimEntryPoint + DebugLib + PeiServicesTablePointerLib + +[Guids] + gUbaCurrentConfigHobGuid + +[Ppis] + gUbaConfigDatabasePpiGuid + gEfiEndOfPeiSignalPpiGuid + +[Pcd] + +[Depex] + TRUE + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaCommon.dsc b/Platfor= m/Intel/WhitleyOpenBoardPkg/Uba/UbaCommon.dsc new file mode 100644 index 0000000000..a3e961aa76 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaCommon.dsc @@ -0,0 +1,29 @@ +## @file UbaCommon.dsc +# UBA DSC include file containing common build items. +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[LibraryClasses.IA32] + UbaPlatLib|$(RP_PKG)/Library/PeiUbaPlatLib/PeiUbaPlatLib.inf + UbaGpioInitLib|$(RP_PKG)/Library/UbaGpioInitLib/UbaGpioInitLib.inf + +[Components.IA32] + $(RP_PKG)/Uba/CfgDb/Pei/CfgDbPei.inf + $(RP_PKG)/Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.inf + +[Components.X64] + # + # Requires a board specific library port + # + $(RP_PKG)/Uba/BoardInit/Dxe/BoardInitDxe.inf + $(RP_PKG)/Uba/CfgDb/Dxe/CfgDbDxe.inf + + # + # Common + # + $(RP_PKG)/Uba/UbaMain/Common/Dxe/SystemBoardInfoDxe/SystemBoardInfoDxe.i= nf + $(RP_PKG)/Uba/UbaMain/Common/Dxe/SystemConfigUpdateDxe/SystemConfigUpdat= eDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf b/Plat= form/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf new file mode 100644 index 0000000000..73dba1dad8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf @@ -0,0 +1,16 @@ +## @file UbaDxeCommon.fdf +# UBA common DXE component FDF include file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# Common +# +INF $(RP_PKG)/Uba/CfgDb/Dxe/CfgDbDxe.inf +INF $(RP_PKG)/Uba/BoardInit/Dxe/BoardInitDxe.inf +INF $(RP_PKG)/Uba/UbaMain/Common/Dxe/SystemBoardInfoDxe/SystemBoardInfoDx= e.inf +INF $(RP_PKG)/Uba/UbaMain/Common/Dxe/SystemConfigUpdateDxe/SystemConfigUp= dateDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Pl= atform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf new file mode 100644 index 0000000000..cb40d6da78 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf @@ -0,0 +1,22 @@ +## @file UbaDxeRpBoards.fdf +# UBA DXE components for Intel reference boards +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# Platform TypeWilsonCityRP +# +INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdate= Dxe.inf +INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpda= teDxe.inf +INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotData= UpdateDxe.inf + +# +# Platform TypeCooperCityRP +# +INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdate= Dxe.inf +INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpda= teDxe.inf +INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotData= UpdateDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emBoardInfoDxe/SystemBoardInfoDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Ub= a/UbaMain/Common/Dxe/SystemBoardInfoDxe/SystemBoardInfoDxe.c new file mode 100644 index 0000000000..f19fa7d61c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemBoard= InfoDxe/SystemBoardInfoDxe.c @@ -0,0 +1,206 @@ +/** @file + System Board Info. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SystemBoardInfoDxe.h" + + +// +// Describes Local APICs' connections. +// +STATIC DEVICE_DATA_HW_LOCAL_INT DeviceDataHwLocalInt1[] =3D { + { + {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}}, + 0x00, + 0xff, + 0x00, + EfiLegacyMpTableEntryLocalIntTypeExtInt, + EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec, + EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec + }, + { + {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}}, + 0x00, + 0xff, + 0x01, + EfiLegacyMpTableEntryLocalIntTypeInt, + EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec, + EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec + }, +}; + +// +// Describes system's address space mapping, specific to the system. +// +STATIC DEVICE_DATA_HW_ADDR_SPACE_MAPPING DeviceDataHwAddrSpace1[] =3D { + // + // Legacy IO addresses. + // + { {0}, EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo, 0x0000, = 0x1000 }, + /* + { {0}, EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory, 0xXXXXXXXX, = 0xXXXXXXXX}, + { {0}, EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch, 0xXXXXXXXX, = 0xXXXXXXXX}, + */ +}; + +// +// IRQ priority +// +STATIC EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY IrqPriorityTable1[] =3D { + {11, 0}, + {10, 0}, + {9, 0}, + {5, 0}, + {0, 0}, + {0, 0}, + {0, 0} +}; + +// +// Note : UpdateBusNumbers updates the bus numeber +// +STATIC EFI_LEGACY_PIRQ_TABLE PirqTableHead1 [] =3D { + { + { + EFI_PIRQ_TABLE_SIGNATURE, + 00, + 01, + 0000, + 00, + 00, + 0000, + V_INTEL_VID, + 30, + 00000000, + { + 00, + 00, + 00, + 00, + 00, + 00, + 00, + 00, + 00, + 00, + 00 + }, + 00 + } + } +}; + +// +// Instantiation of the system device data. +// +DEVICE_DATA mDeviceData =3D { + DeviceDataHwLocalInt1, sizeof (DeviceDataHwLocalInt1) / sizeof (Device= DataHwLocalInt1[0]), + DeviceDataHwAddrSpace1, sizeof (DeviceDataHwAddrSpace1)/ sizeof (Device= DataHwAddrSpace1[0]) +}; + +// +// Instantiation of platform PIRQ data. +// +PLATFORM_PIRQ_DATA mPlatformPirqData =3D { + IrqPriorityTable1, sizeof(IrqPriorityTable1) / sizeof(IrqPriorityTabl= e1[0]), + PirqTableHead1, sizeof(PirqTableHead1) / sizeof(PirqTableHead1[0]) +}; + + +PCI_OPTION_ROM_TABLE mPciOptionRomTable[] =3D { + // + // End of OptionROM Entries + // + { + NULL_ROM_FILE_GUID, // Guid + 0, // Segment + 0, // Bus Number + 0, // Device Number + 0, // Function Number + 0xffff, // Vendor ID + 0xffff // Device ID + } +}; + +// +// system board information structure +// +DXE_SYSTEM_BOARD_INFO SystemBoardInfoTable =3D { + // + // System board configuration data + // + mPciOptionRomTable, + + // + // System board CPU data + // + 2, // Cpu socket count + + // + // System board legacy data + // + &mDeviceData, + &mPlatformPirqData +}; + +DXE_SYSTEM_BOARD_INFO *SystemBoardInfoCallback () +{ + return (DXE_SYSTEM_BOARD_INFO*) &SystemBoardInfoTable; +} + +SYSTEM_BOARD_INFO_DATA SystemBoardInfoData =3D { + SYSTEM_SYSTEM_BOARD_INFO_SIGNATURE, + SYSTEM_SYSTEM_BOARD_INFO_VERSION, + SystemBoardInfoCallback +}; +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SystemBoardInfoEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((EFI_D_INFO, "UBA:System Board Info Table.\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gSystemBoardInfoConfigDataGuid, + &SystemBoardInfoData, + sizeof(SystemBoardInfoData) + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emBoardInfoDxe/SystemBoardInfoDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Ub= a/UbaMain/Common/Dxe/SystemBoardInfoDxe/SystemBoardInfoDxe.h new file mode 100644 index 0000000000..32c16ff911 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemBoard= InfoDxe/SystemBoardInfoDxe.h @@ -0,0 +1,33 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SYSTEM_BOARD_INFO_DXE_H_ +#define _SYSTEM_BOARD_INFO_DXE_H_ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +// Protocol +#include +#include + +#include +#include + +#endif //_SYSTEM_BOARD_INFO_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emBoardInfoDxe/SystemBoardInfoDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/= Uba/UbaMain/Common/Dxe/SystemBoardInfoDxe/SystemBoardInfoDxe.inf new file mode 100644 index 0000000000..0baf387b38 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemBoard= InfoDxe/SystemBoardInfoDxe.inf @@ -0,0 +1,45 @@ +## @file +# +# @copyright +# Copyright 2017 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SystemBoardInfo + FILE_GUID =3D 9826a826-004e-4197-b179-9f489af1e3c9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SystemBoardInfoEntry + +[Sources] + SystemBoardInfoDxe.c + SystemBoardInfoDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + + +[Guids] + gSystemBoardInfoConfigDataGuid + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gUbaConfigDatabaseProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emConfigUpdateDxe/SystemConfigUpdateDxe.c b/Platform/Intel/WhitleyOpenBoard= Pkg/Uba/UbaMain/Common/Dxe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.c new file mode 100644 index 0000000000..18205d16c8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemConfi= gUpdateDxe/SystemConfigUpdateDxe.c @@ -0,0 +1,94 @@ +/** @file + System Congfig Update. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SystemConfigUpdateDxe.h" +#include + +EFI_PLATFORM_INFO *mPlatformInfo =3D NULL; + +/** + + Update the IioDefaults + + @param *SYSTEM_CONFIGURATION Pointer to the SystemConfiguration stru= cture + + @retval None + +**/ +VOID +IioDefaultConfigUpdateCallback ( + IN SYSTEM_CONFIGURATION *Default + ) +{ + UINT8 BoardId; + + BoardId =3D mPlatformInfo->BoardId; + Default->PlatformOCSupport =3D 0; + if (BoardId =3D=3D TypeHedtCRB) { + Default->PlatformOCSupport =3D 1; + } +} + +SYSTEM_CONFIG_UPDATE_DATA SystemConfigUpdateTable =3D { + SYSTEM_CONFIG_UPDATE_SIGNATURE, + SYSTEM_CONFIG_UPDATE_VERSION, + IioDefaultConfigUpdateCallback +}; + + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SystemConfigUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + mPlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + DEBUG((DEBUG_INFO, "UBA:System Config Update Table.\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gSystemConfigUpdateDataGuid, + &SystemConfigUpdateTable, + sizeof(SystemConfigUpdateTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emConfigUpdateDxe/SystemConfigUpdateDxe.h b/Platform/Intel/WhitleyOpenBoard= Pkg/Uba/UbaMain/Common/Dxe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.h new file mode 100644 index 0000000000..f7daaa9212 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemConfi= gUpdateDxe/SystemConfigUpdateDxe.h @@ -0,0 +1,30 @@ +/** @file + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UPDATE_SYSTEM_CONFIG_DXE_H_ +#define _UPDATE_SYSTEM_CONFIG_DXE_H_ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#endif //_UPDATE_SYSTEM_CONFIG_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/Syst= emConfigUpdateDxe/SystemConfigUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoa= rdPkg/Uba/UbaMain/Common/Dxe/SystemConfigUpdateDxe/SystemConfigUpdateDxe.inf new file mode 100644 index 0000000000..3490dbef21 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Dxe/SystemConfi= gUpdateDxe/SystemConfigUpdateDxe.inf @@ -0,0 +1,48 @@ +## @file +# +# @copyright +# Copyright 2017 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SystemConfigUpdate + FILE_GUID =3D 9f048812-a546-4c85-a5cf-a0785423705d + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SystemConfigUpdateEntry + +[sources] + SystemConfigUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + PcdLib + HobLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Guids] + gEfiPlatformInfoGuid + +[Pcd] + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gUbaConfigDatabaseProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Boar= dInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/BoardIn= fo.c new file mode 100644 index 0000000000..63acdbaf56 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/BoardInfo.c @@ -0,0 +1,69 @@ +/** @file + Install Board Info Data. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" +#include +#include +#include +#include + +STATIC SIO_INDEX_DATA mSioInitTable[] =3D { + // + // Init GPIO + // + { + PILOTIV_LOGICAL_DEVICE, + PILOTIV_SIO_GPIO + }, + { + PILOTIV_ACTIVATE, + 0x01 + }, + { + PILOTIV_BASE_ADDRESS_HIGH0, + (UINT8) ((UINT16) SIO_GPIO_BASE_ADDRESS >> 8) + }, + { + PILOTIV_BASE_ADDRESS_LOW0, + (UINT8) (SIO_GPIO_BASE_ADDRESS & 0x00ff) + } +}; + +// +// Platform board sio information structure +// +static PEI_BOARD_SIO_INFO BoardSioInfoData =3D { + BOARD_SIO_INFO_DATA_SIGNATURE, + BOARD_SIO_INFO_DATA_VERSION, + // + // SIO Initialization table + // + PILOTIV_SIO_INDEX_PORT, // SIO Index port + PILOTIV_SIO_DATA_PORT, // SIO Data port + mSioInitTable, // mSioInitTable - contains th= e settings for initializing the SIO. + sizeof(mSioInitTable)/sizeof(SIO_INDEX_DATA) // NumSioItems - Number of = items in the SIO init table. +}; + + +EFI_STATUS +InstallBoardInfoData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformBoardSioInfoDataGuid, + &BoardSioInfoData, + sizeof(PEI_BOARD_SIO_INFO) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Cloc= kgen.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Clockgen= .c new file mode 100644 index 0000000000..f65e762702 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Clockgen.c @@ -0,0 +1,27 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" + +#include + +// +// No External clockgen, Use ICC Hybrid mode +// + +EFI_STATUS +InstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Cloc= ksConfig.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Cloc= ksConfig.c new file mode 100644 index 0000000000..196164ad9b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/ClocksConfi= g.c @@ -0,0 +1,177 @@ +/** @file + Install Platform Clocks Config Data. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" +#include +#include +#include +#include +#include +#include + +// +// Table providing details on clocks supported by this library +// +// It is critical that this table be properly constructed. +// The table entries must line up with the clock generatory types +// +CLOCK_GENERATOR_DETAILS mSupportedClockGeneratorTable[] =3D { +{ + ClockGeneratorCk410, + CK410_GENERATOR_ID, + CK410_GENERATOR_SPREAD_SPECTRUM_BYTE, + CK410_GENERATOR_SPREAD_SPECTRUM_BIT + }, +{ + ClockGeneratorCk420, + CK420_GENERATOR_ID, + CK420_GENERATOR_SPREAD_SPECTRUM_BYTE, + CK420_GENERATOR_SPREAD_SPECTRUM_BIT + }, +{ + ClockGeneratorCk440, + CK440_GENERATOR_ID, + CK440_GENERATOR_SPREAD_SPECTRUM_BYTE, + CK440_GENERATOR_SPREAD_SPECTRUM_BIT + }, +{ + ClockGeneratorCk505, + CK505_GENERATOR_ID, + CK505_GENERATOR_SPREAD_SPECTRUM_BYTE, + CK505_GENERATOR_SPREAD_SPECTRUM_BIT + } +}; + +/** + + Configure the clock generator and enable Spread Spectrum if applicable. + + @param None + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_UNSUPPORTED Clock generator configuration is not supported + +**/ +EFI_STATUS +PlatformClocksConfigCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + CLOCKING_MODES ClockingMode; + UINT8 *ConfigurationTable; + UINT8 ConfigurationTablePlatformSRP[] = =3D CLOCK_GENERATOR_SETTINGS_PLATFORMSRP; + UINT8 ConfigurationTableCK505[] =3D CLOC= K_GENERATOR_SETTINGS_CK505; + UINTN Length; + CLOCK_GENERATOR_TYPE ClockType; + BOOLEAN SecondarySmbus =3D FALSE; + BOOLEAN EnableSpreadSpectrum; + PCH_POLICY_PPI *PchPolicyPpi; + UINT8 ClockGeneratorAddress =3D 0; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "ConfigurePlatformClocks. Can not read gDynamicSi= LibraryPpiGuid\n")); + return Status; + } + + ClockGeneratorAddress =3D PcdGet8 (PcdOemSkuClockGeneratorAddress); + + ClockingMode =3D InternalAlternate; + Status =3D EFI_SUCCESS; + if (EFI_ERROR (Status)) { + if (Status !=3D EFI_UNSUPPORTED) { + DEBUG ((DEBUG_ERROR, "ConfigurePlatformClocks. Can't read clock mode= ! EFI_STATUS =3D %r\n", Status)); + } + return Status; + } + + if (External =3D=3D ClockingMode) + { + DEBUG ((DEBUG_INFO, "ConfigurePlatformClocks. Clock Mode: External\n")= ); + + // + // If the clocking mode is external and CPX is present, then no furthe= r configuration of the + // clock is supported at this time. + // + if (DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CPX, REV_ALL)) { + return EFI_UNSUPPORTED; + } + + if (DynamicSiLibraryPpi->IsSimicsEnvironment()) { + // + // Simics implements CK505 model + // + ConfigurationTable =3D ConfigurationTableCK505; + Length =3D sizeof (ConfigurationTableCK505); + ClockType =3D ClockGeneratorCk505; + } + else { + // + // SRP/DVP configuration + // + ConfigurationTable =3D ConfigurationTablePlatformSRP; + Length =3D sizeof (ConfigurationTablePlatformSRP); + ClockType =3D ClockGeneratorCk420; + } + Status =3D (*PeiServices)->LocatePpi (PeiServices, + &gPchPlatformPolicyPpiGuid, + 0, + NULL, + (VOID **)&PchPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + EnableSpreadSpectrum =3D (BOOLEAN) PchPolicyPpi->PchConfig.EnableClock= SpreadSpec; + if (1 =3D=3D EnableSpreadSpectrum) { + ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSp= ectrumByteOffset] |=3D mSupportedClockGeneratorTable[ClockType].SpreadSpect= rumBitOffset; + } else { + ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSp= ectrumByteOffset] &=3D ~(mSupportedClockGeneratorTable[ClockType].SpreadSpe= ctrumBitOffset); + } + Status =3D ConfigureClockGenerator (PeiServices, + ClockType, + ClockGeneratorAddress, + Length, + ConfigurationTable, + EnableSpreadSpectrum, + &mSupportedClockGeneratorTable[Clock= Type], + SecondarySmbus + ); + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} + +PLATFORM_CLOCKS_CONFIG_TABLE PlatformClocksConfigTable =3D +{ + PLATFORM_CLOCKS_CONFIG_SIGNATURE, + PLATFORM_CLOCKS_CONFIG_VERSION, + PlatformClocksConfigCallback +}; + +EFI_STATUS +InstallPlatformClocksConfigData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformClocksConfigDataGuid, + &PlatformClocksConfigTable, + sizeof(PlatformClocksConfigTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Gpio= PlatformConfig.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pe= i/GpioPlatformConfig.c new file mode 100644 index 0000000000..d18a3038ef --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/GpioPlatfor= mConfig.c @@ -0,0 +1,166 @@ +/** @file + + @copyright + Copyright 2013 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" +#include +#include +#include +#include +#include + +STATIC PLATFORM_GPIO_CONFIG_TABLE mGpioPlatformConfig =3D { + + PLATFORM_GPIO_CONFIG_SIGNATURE, + PLATFORM_GPIO_CONFIG_VERSION, + + //MFG pad + { + GPIO_SKL_H_GPP_C9, //To be verified with the Board schematics + {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntD= is, GpioPlatformReset, GpioTermNone} + }, + + GPIO_SKL_H_GPP_A18, + + //Recovery jumper pad + GPIO_SKL_H_GPP_B14, + + //FM ADR Trigger + GPIO_SKL_H_GPP_E3, + + //ADR enable GPIO output + GPIO_SKL_H_GPP_D4, + + // Force to S1 config mode pad + GPIO_SKL_H_GPP_A17, + + // + // Used by PC Platforms + // + GPIO_SKL_H_GPP_B3, + // + // Used by PC platforms. This is the first GPIO pad of the pad series to= indicate Board ID + // + GPIO_SKL_H_GPP_G12, + + // + // WHEA SCI generation pad + // + GPIO_SKL_H_GPP_A12, + + // + // Used to generate CPU HP SMI + // + GPIO_SKL_H_GPP_E6, + + // + // FPGA error indicator + // + GPIO_SKL_H_GPP_E4, + + // + // FPGA error indicator + // + GPIO_SKL_H_GPP_E5, + + // Flash Security + UNUSED_GPIO, +}; + +STATIC PLATFORM_GPIO_CONFIG_TABLE mGpioMiniPchPlatformConfig =3D { + + PLATFORM_GPIO_CONFIG_SIGNATURE, + PLATFORM_GPIO_CONFIG_VERSION, + + //MFG pad + { + UNUSED_GPIO, //To be verified with the Board schematics + {0, 0, 0, 0, 0, 0, 0} + }, + + UNUSED_GPIO, + + //Recovery jumper pad + UNUSED_GPIO, + + //FM ADR Trigger + UNUSED_GPIO, + + //ADR enable GPIO output + UNUSED_GPIO, + + // Force to S1 config mode pad + UNUSED_GPIO, + + // + // Used by PC Platforms + // + UNUSED_GPIO, + // + // Used by PC platforms. This is the first GPIO pad of the pad series to= indicate Board ID + // + UNUSED_GPIO, + + // + // WHEA SCI generation pad + // + UNUSED_GPIO, + + // + // Used to generate CPU HP SMI + // + UNUSED_GPIO, + + // + // FPGA error indicator + // + UNUSED_GPIO, + + // + // FPGA error indicator + // + UNUSED_GPIO, + +}; + + +EFI_STATUS +InstallGpioPlatformData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (DynamicSiLibraryPpi->GetPchSeries () =3D=3D PchMini) { + return UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioPlatformConfigDataGuid, + &mGpioMiniPchPlatformConfig, + sizeof(mGpioMiniPchPlatformConfig) + ); + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioPlatformConfigDataGuid, + &mGpioPlatformConfig, + sizeof(mGpioPlatformConfig) + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/Hsio= PtssTableConfig.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/P= ei/HsioPtssTableConfig.c new file mode 100644 index 0000000000..75abf28d8c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/HsioPtssTab= leConfig.c @@ -0,0 +1,460 @@ +/** @file + Install Platform Hsio Ptss Table Data. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "PchLbgHsioPtssTablesBx.h" +#include "PchLbgHsioPtssTablesBx_Ext.h" +#include "PchLbgHsioPtssTablesSx.h" +#include "PchLbgHsioPtssTablesSx_Ext.h" +#include +#include +#include +#include +#include + + +VOID +InstallPlatformHsioPtssTableCallback ( + IN PCH_SETUP *PchSetup, + IN OUT PCH_POLICY_PPI *PchPolicy + ) +{ + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxsSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + EFI_STATUS Status; + UINT16 BoardId; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + switch (DynamicSiLibraryPpi->PchStepping ()) { + case LbgA0: + case LbgB0: + case LbgB1: + case LbgB2: + case LbgB3: + { + PtssTables =3D PchLbgHsioPtss_Bx; + TableSize =3D PchLbgHsioPtss_Bx_Size; + } + if (DynamicSiLibraryPpi->HybridSystemLevelEmulationEnabled ()) { + PtssTables =3D PchLbgHsioPtss_Bx; + TableSize =3D PchLbgHsioPtss_Bx_Size; + } + break; + case LbgS0: + case LbgS1: + case LbgS2: + { + PtssTables =3D PchLbgHsioPtss_Sx; + TableSize =3D PchLbgHsioPtss_Sx_Size; + } + if (DynamicSiLibraryPpi->HybridSystemLevelEmulationEnabled ()) { + PtssTables =3D PchLbgHsioPtss_Sx; + TableSize =3D PchLbgHsioPtss_Sx_Size; + } + break; + default: + PtssTables =3D NULL; + TableSize =3D 0; + DEBUG ((DEBUG_ERROR, "Cannot find PTSS table for this PCH Stepping\n= ")); + ASSERT (FALSE); + } + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT(GuidHob !=3D NULL); + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + BoardId =3D PlatformInfo->BoardId; + PtssTableIndex =3D 0; + MaxSataPorts =3D DynamicSiLibraryPpi->GetPchMaxSataPortNum (); + MaxsSataPorts =3D DynamicSiLibraryPpi->GetPchMaxsSataPortNum (); + MaxPciePorts =3D DynamicSiLibraryPpi->GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + //Populate PCIe topology based on lane configuration + + CopyMem ( + PcieTopologyReal, + PchSetup->PcieTopology, + sizeof (PcieTopologyReal) + ); + for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) { + Status =3D DynamicSiLibraryPpi->GetPchPcieRpDevFunByPchId (PCH_LEGACY_= ID, PciePort, &RpDevice, &RpFunction); + RpBase =3D DynamicSiLibraryPpi->MmPciBase (0, (UINT32) RpDevice, (UINT= 32) RpFunction); + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_= RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", PciePo= rt, PcieControllerCfg)); + PcieTopologyReal[PciePort] =3D PchSetup->PcieTopology[PciePort]; + if (PcieControllerCfg !=3D V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1) { + PcieTopologyReal[PciePort + 1] =3D PchSetup->PcieTopology[PciePort]; + } + if (PcieControllerCfg =3D=3D V_PCH_PCIE_STRPFUSECFG_RPC_4) { + PcieTopologyReal[PciePort + 2] =3D PchSetup->PcieTopology[PciePort]; + PcieTopologyReal[PciePort + 3] =3D PchSetup->PcieTopology[PciePort]; + } + if (PcieControllerCfg =3D=3D V_PCH_PCIE_STRPFUSECFG_RPC_2_2) { + PcieTopologyReal[PciePort + 2] =3D PchSetup->PcieTopology[PciePort += 2]; + PcieTopologyReal[PciePort + 3] =3D PchSetup->PcieTopology[PciePort += 2]; + } + if (PcieControllerCfg =3D=3D V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1) { + PcieTopologyReal[PciePort + 2] =3D PchSetup->PcieTopology[PciePort += 2]; + PcieTopologyReal[PciePort + 3] =3D PchSetup->PcieTopology[PciePort += 3]; + } + } + for (Index =3D 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Setup RP %d Topology =3D %d\n", Index, = PchSetup->PcieTopology[Index])); + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", Inde= x, PcieTopologyReal[Index])); + } + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (DynamicSiLibraryPpi->PchGetSataLaneNumByPchId (PCH_LEGACY_ID, Inde= x, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE_O= WN_SATA) && + (PchSetup->SataTopology[Index] =3D=3D PtssTables[Entry].Topology= ) && + (BoardId =3D=3D PtssTables[Entry].BoardId)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO_P= CR_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMag= Enable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMag= =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssT= able.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE00MARGIN_5_0) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1Downscal= eAmpEnable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1Downscal= eAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8= _ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0; + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE01MARGIN_5_0) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2Downscal= eAmpEnable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2Downscal= eAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8= _ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0; + } + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table = offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + //Case 1a continued: Secondary SATA + for (Index =3D 0; Index < MaxsSataPorts; Index++) { + if (DynamicSiLibraryPpi->PchGetsSataLaneNumByPchId (PCH_LEGACY_ID, Ind= ex, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE_O= WN_SATA) && + (PchSetup->sSataTopology[Index] =3D=3D PtssTables[Entry].Topolog= y) && + (BoardId =3D=3D PtssTables[Entry].BoardId)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO_P= CR_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMa= gEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMa= g =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Ptss= Table.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE00MARGIN_5_0) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1Downsca= leAmpEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1Downsca= leAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0; + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE01MARGIN_5_0) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2Downsca= leAmpEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2Downsca= leAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD= 8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0; + } + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table = offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + //Case 1b: PCIe + for (Index =3D 0; Index < MaxPciePorts; Index++) { + if (DynamicSiLibraryPpi->PchGetPcieLaneNumByPchId (PCH_LEGACY_ID, Inde= x, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + // Skip matching Lanes when the table record has settings for WM20= FIA + if ((PtssTables[Entry].PtssTable.SbPortID =3D=3D PID_MODPHY4) || + (PtssTables[Entry].PtssTable.SbPortID =3D=3D PID_MODPHY5)){ + continue; + } + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE_O= WN_PCIEDMI) && + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology) && + (BoardId =3D=3D PtssTables[Entry].BoardId)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO_P= CR_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtleEnable =3D = TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtle =3D (PtssT= ables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMas= k) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0; + } + else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_H= SIO_PCR_RX_DWORD39) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD39_ICFG_ADJ_LIMITL0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_= LIMITL0)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLoEnable= =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLo =3D (= PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.B= itMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD40) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD40_SAMP_OFFST_EVEN_ERRSP) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP= _OFFST_EVEN_ERRSP)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSpEn= able =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSp = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTa= ble.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD41) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD41_REMAINING_SAMP_OFFSTS) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD41_REMA= INING_SAMP_OFFSTS)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOffE= nable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOff = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTa= ble.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD7) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD7_VGA_GAIN_CAL) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCalEnable =3D= TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCal =3D (Ptss= Tables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMa= sk) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL; + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table = offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + //Case 1b Continued: PCIe for WM20 FIA + for (Index =3D 0; Index < PCH_MAX_WM20_LANES_NUMBER; Index++) { + LaneNum =3D Index; + for (Entry =3D 0; Entry < TableSize; Entry++) { + // Skip entries which are not for WM20 FIA + if ((PtssTables[Entry].PtssTable.SbPortID !=3D PID_MODPHY4) && + (PtssTables[Entry].PtssTable.SbPortID !=3D PID_MODPHY5)){ + continue; + } + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE_O= WN_PCIEDMI) && + (BoardId =3D=3D PtssTables[Entry].BoardId)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO_P= CR_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtleEnab= le =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtle =3D= (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable= .BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD39) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD39_ICFG_ADJ_LIMITL0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_= LIMITL0)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitL= oEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitL= o =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Ptss= Table.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD40) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD40_SAMP_OFFST_EVEN_ERRSP) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP= _OFFST_EVEN_ERRSP)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEven= ErrSpEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEven= ErrSp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].= PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD41) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD41_REMAINING_SAMP_OFFSTS) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD41_REMA= INING_SAMP_OFFSTS)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamp= lerOffEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamp= lerOff =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry]= .PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _HSIO_PCR_RX_DWORD7) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_R= X_DWORD7_VGA_GAIN_CAL) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCalEna= ble =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCal = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTa= ble.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL; + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table = offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + + //Case 2: BoardId is unknown, Topology is known/unknown + if (PtssTableIndex =3D=3D 0) { + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (DynamicSiLibraryPpi->PchGetSataLaneNumByPchId (PCH_LEGACY_ID, In= dex, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA) && + (PchSetup->SataTopology[Index] =3D=3D PtssTables[Entry].Topolo= gy) && + (PtssTables[Entry].BoardId =3D=3D TypePlatformUnknown)) { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO= _PCR_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostM= agEnable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostM= ag =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Pts= sTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_HSIO_PCR_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE00MARGIN_5_0) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1Downsc= aleAmpEnable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1Downsc= aleAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWOR= D8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0; + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE01MARGIN_5_0) { + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2Downsc= aleAmpEnable =3D TRUE; + PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2Downsc= aleAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWOR= D8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0; + } + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS tabl= e offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + // Case 2 Continued secondary SATA when BoardId is unknown, Topology i= s known/unknown + for (Index =3D 0; Index < MaxsSataPorts; Index++) { + if (DynamicSiLibraryPpi->PchGetsSataLaneNumByPchId (PCH_LEGACY_ID, I= ndex, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA) && + (PchSetup->sSataTopology[Index] =3D=3D PtssTables[Entry].Topol= ogy) && + (PtssTables[Entry].BoardId =3D=3D TypePlatformUnknown)) { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO= _PCR_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoost= MagEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoost= Mag =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Pt= ssTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_HSIO_PCR_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE00MARGIN_5_0) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1Downs= caleAmpEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1Downs= caleAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0; + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE01MARGIN_5_0) { + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2Downs= caleAmpEnable =3D TRUE; + PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2Downs= caleAmp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWO= RD8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0; + } + } + else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS tabl= e offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + for (Index =3D 0; Index < MaxPciePorts; Index++) { + if (DynamicSiLibraryPpi->PchGetPcieLaneNumByPchId (PCH_LEGACY_ID, In= dex, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + // Skip matching Lanes when the table record has settings for WM= 20 FIA + if ((PtssTables[Entry].PtssTable.SbPortID =3D=3D PID_MODPHY4) || + (PtssTables[Entry].PtssTable.SbPortID =3D=3D PID_MODPHY5)){ + continue; + } + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) && + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology) && + (PtssTables[Entry].BoardId =3D=3D TypePlatformUnknown)) { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO= _PCR_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtleEnable = =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtle =3D (Pts= sTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitM= ask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD39) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD39_ICFG_ADJ_LIMITL0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_AD= J_LIMITL0)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLoEnab= le =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLo =3D= (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable= .BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD40) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD40_SA= MP_OFFST_EVEN_ERRSP)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSp= Enable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSp= =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssT= able.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD41) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD41_REMAINING_SAMP_OFFSTS) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD41_RE= MAINING_SAMP_OFFSTS)) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOf= fEnable =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOf= f =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Ptss= Table.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD7) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD7_VGA_GAIN_CAL) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)= ) { + PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCalEnable = =3D TRUE; + PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCal =3D (Pt= ssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.Bit= Mask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL; + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS tabl= e offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } + + //Continued for PCIe ports in WM20 FIA + for (Index =3D 0; Index < PCH_MAX_WM20_LANES_NUMBER; Index++) { + LaneNum =3D Index; + for (Entry =3D 0; Entry < TableSize; Entry++) { + // Skip entries which are not for WM20 FIA + if ((PtssTables[Entry].PtssTable.SbPortID !=3D PID_MODPHY4) && + (PtssTables[Entry].PtssTable.SbPortID !=3D PID_MODPHY5)){ + continue; + } + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) && + (PtssTables[Entry].BoardId =3D=3D TypePlatformUnknown)) { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_HSIO= _PCR_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtleEn= able =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtle = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTa= ble.BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD39) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD39_ICFG_ADJ_LIMITL0) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_AD= J_LIMITL0)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimi= tLoEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimi= tLo =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].Pt= ssTable.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD40) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD40_SA= MP_OFFST_EVEN_ERRSP)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEv= enErrSpEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEv= enErrSp =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry= ].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD41) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD41_REMAINING_SAMP_OFFSTS) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD41_RE= MAINING_SAMP_OFFSTS)) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSa= mplerOffEnable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSa= mplerOff =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entr= y].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32)= R_HSIO_PCR_RX_DWORD7) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR= _RX_DWORD7_VGA_GAIN_CAL) =3D=3D (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)= ) { + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCalE= nable =3D TRUE; + PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCal = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTa= ble.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL; + } else { + DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS tabl= e offset and/or mask are not compatible with the BIOS Code.\n")); + } + } + } + } + } +} + +PLATFORM_HSIO_PTSS_CONFIG_TABLE PlatformHsioPtssConfigTable =3D +{ + PLATFORM_HSIO_PTSS_TABLE_SIGNATURE, + PLATFORM_HSIO_PTSS_TABLE_VERSION, + InstallPlatformHsioPtssTableCallback +}; + +EFI_STATUS +InstallPlatformHsioPtssTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (DynamicSiLibraryPpi->GetPchSeries() =3D=3D PchMini) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformHsioPtssTableGuid, + &PlatformHsioPtssConfigTable, + sizeof(PlatformHsioPtssConfigTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioB= ifurcationSlotTable.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Comm= on/Pei/IioBifurcationSlotTable.h new file mode 100644 index 0000000000..b3a265b664 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioBifurcat= ionSlotTable.h @@ -0,0 +1,156 @@ +/** @file + Contains several definitions for table structures used for Bifurcation a= nd slot configuration + on the different platforms. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOBIFURCATIONSLOTTABLE_H_ +#define _IIOBIFURCATIONSLOTTABLE_H_ + +#include "IioPlatformData.h" + +#define QAT_ENABLED 0 // QAT is active-low +#define RISER_PRESENT 0 +#define RISER_NOT_PRESENT 1 +#define RISER_HP_EN 1 +#define RISER_WINGED_IN 0 +#define RISER_SLOT9_DISABLE 1 + +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 BroadwayAddress; // 0xff, no override bifurcation settings. + // 0-2 BW5 card can be present +} IIO_BROADWAY_ADDRESS_ENTRY; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +typedef union { + struct { + UINT8 PresentSignal:1; + UINT8 HPConf:1; + UINT8 WingConf:1; + UINT8 Slot9En:1; + } Bits; + UINT8 Data; +} PCIE_RISER_ID; + +enum { + Iio_PortA =3D 0, + Iio_PortB =3D 1, + Iio_PortC =3D 2, + Iio_PortD =3D 3 +}; +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORTS; +/// +/// Platform Port/Socket assignments. +/// + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +// +// BW5 SMbus slave address +// +#define BW5_SMBUS_ADDRESS 0x4C +#define PCA9555_COMMAND_CONFIG_PORT0_REG 0x06 +#define PCA9555_COMMAND_INPUT_PORT0_REG 0x00 +#define NUM_OF_RETRIES 0x03 +#define BW5_0_ID_MASK 0x0007 +#define BW5_1_ID_MASK 0x0070 +#define BW5_2_ID_MASK 0x0700 +#define BW5_3_ID_MASK 0x7000 +#define BW5_CONFIG_REG_MASK 0xFF +#define BW5_CARDS_PRESENT 0x04 +#define BW5_CARD_NOT_PRESENT 0x07 + + +// Bifurcation read from MCU +#define BW5_BIFURCATE_x4x4x4x4 0 +#define BW5_BIFURCATE_xxx8x4x4 1 +#define BW5_BIFURCATE_x4x4xxx8 2 +#define BW5_BIFURCATE_xxx8xxx8 3 + +#define BW4_DATA_OFFSET 0 +#define BW4_CONFIG_OFFSET 3 + +typedef union { + struct { + UINT8 BifBits:3; + UINT8 ExtPresent:1; + UINT8 HotPlugEna:1; + UINT8 Rsvd:2; + UINT8 ExtId:1; + } Bits; + UINT8 Data; +} BW5_BIFURCATION_DATA_STRUCT; + +/** + This function prepare the data for silicon initialization based on + bifuraction and slots table + + This function is for tables in version PLATFORM_IIO_CONFIG_UPDATE_VERSIO= N =3D 1 + */ +VOID +IioPortBifurcationInitVer1 ( + IN IIO_GLOBALS *IioGlobalData + ); + +/** + Function returns the board ID from running HW + + @return BoardId +**/ +UINT8 +EFIAPI +SystemBoardIdValue ( + VOID + ); + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioP= ortBifurcation.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pe= i/IioPortBifurcation.c new file mode 100644 index 0000000000..4f23abc1e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioPortBifu= rcation.c @@ -0,0 +1,913 @@ +/** @file + Install Iio Port Bifurcation Init Data. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "PeiCommonBoardInitLib.h" +#include "IioBifurcationSlotTable.h" + + +#define IIO_D_UBALOG(...) { DEBUG((DEBUG_ERROR, "[IIO](UBA) " __VA_ARGS__= )); } // Important log always printed +#define IIO_D_UBADBG(...) { DEBUG((DEBUG_INFO, "[IIO](UBA) " __VA_ARGS__= )); } // Debug log, printed with BIOS debug jumper +#define IIO_D_UBAWARN(...) { DEBUG((DEBUG_ERROR, "[IIO](UBA) WARNING: " __= VA_ARGS__)); } // Warning log, not necessary error +#define IIO_D_UBAERR(...) { DEBUG((DEBUG_ERROR, "[IIO](UBA) ERROR: " __VA= _ARGS__)); } // Errorneous situation, probably bug or hw problem + +EFI_PLATFORM_INFO* +GetPlatformInfoFromHob ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT (FALSE); + return NULL; + } + return GET_GUID_HOB_DATA (GuidHob); +} + +/** + Check if QAT-UPLINK override is needed + + @param[in] Socket Socket index + @param[in] Iou IOU index + @param[out] Bifurcation Buffer for bifurcation needed to support QAT + + @return TRUE if custom bifurcation is necessary + */ +BOOLEAN +IsQatUplinkOverrideNeeded ( + IN UINT8 Socket, + IN UINT8 Iou, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi, + OUT UINT8 *Bifurcation + ) +{ + EFI_PLATFORM_INFO *PlatformInfo; + UINT32 Gpio; + EFI_STATUS Status; + + PlatformInfo =3D GetPlatformInfoFromHob (); + if (PlatformInfo =3D=3D NULL) { + return FALSE; + } + + switch (PlatformInfo->BoardId) { + case TypeWilsonCityRP: + case TypeWilsonCityModular: + case TypeWilsonCitySMT: + case TypeWilsonCityPPV: + case TypeWilsonPointRP: + case TypeWilsonPointModular: + case TypeCooperCityRP: + if (Socket %2 =3D=3D 0 && Iou =3D=3D 3) { + // + // It is possible that special bifurcation for QAT-UPLINK if needed + // It can be recognized by GPIO D8: 0 means that there is no UPLINK + // + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY= _ID, GPIO_SKL_H_GPP_D8, &Gpio); + if (EFI_ERROR (Status)) { + return FALSE; + } + if (Gpio !=3D 0) { + *Bifurcation =3D IIO_BIFURCATE_xxx8xxx8; + return TRUE; + } else { + return FALSE; + } + } + break; + } + + // + // By default there is no QAT-UPLINK support + // + return FALSE; +} + +/** + Check if QAT-CABLE override is needed + + @param[in] Socket Socket index + @param[in] Iou IOU index + @param[out] Bifurcation Buffer for bifurcation needed to support QAT + + @return TRUE if custom bifurcation is necessary + */ +BOOLEAN +IsQatCableOverrideNeeded ( + IN UINT8 Socket, + IN UINT8 Iou, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi, + OUT UINT8 *Bifurcation + ) +{ + EFI_PLATFORM_INFO *PlatformInfo; + UINT32 Gpio; + EFI_STATUS Status; + + PlatformInfo =3D GetPlatformInfoFromHob (); + if (PlatformInfo =3D=3D NULL) { + return FALSE; + } + + switch (PlatformInfo->BoardId) { + case TypeWilsonCityRP: + case TypeWilsonCityModular: + case TypeWilsonCitySMT: + case TypeWilsonCityPPV: + case TypeWilsonPointRP: + case TypeWilsonPointModular: + if (Iou =3D=3D 4) { + // + // It is possible that special bifurcation for Oculink QAT cable is = needed + // Then cable is used to connect oculinks ports with QAT + // To determine it if cable is needed GPIO-B3 needs to be examined + // GPIO-B3 =3D=3D 0 means that cable is present + // + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY= _ID, GPIO_SKL_H_GPP_B3, &Gpio); + if (EFI_ERROR (Status)) { + return FALSE; + } + + if (Gpio !=3D 0) { + // + // There is no cable + // + return FALSE; + } + + // + // Cable is present to check which MEZZ IOU is used GPIO B4 needs to= be examined + // GPIO-B4 =3D=3D 1: MEZZ IOU from Socket0 is used; + // GPIO-B4 =3D=3D 0: MEZZ IOU from Socket1 is used; + // + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY= _ID, GPIO_SKL_H_GPP_B4, &Gpio); + if (EFI_ERROR (Status)) { + return FALSE; + } + + if ((Socket =3D=3D 0 && Gpio =3D=3D 1) || (Socket =3D=3D 1 && Gpio = =3D=3D 0)) { + *Bifurcation =3D IIO_BIFURCATE_xxx8x4x4; + return TRUE; + } + } + } //switch: Board-Id + + // + // By default there is no QAT-cable support + // + return FALSE; +} + +/** + Check if QAT override is needed. + There are two possible QAT variants: + - QAT uplink + - QAT cable + If LBG with QAT is detected (by GPIO read) custom bifurcation should be = set. + + @param[in] IioGlobalData Pointer to IioGlobalData + */ +VOID +CheckQatBifurcationOverrides ( + IN IIO_GLOBALS *IioGlobalData, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ) +{ + UINT8 Socket; + UINT8 Iou; + UINT8 Bifurcation; + UINT8 StackIndex; + + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + for (Iou =3D 0; Iou < MAX_IOU_PER_SOCKET; Iou++) { + + StackIndex =3D Iou+1; + + if (!DynamicSiLibraryPpi->IioIsSocketPresent (Socket)) { + // + // Skip sockets which are not present on the platform + // + continue; + } + + if (!DynamicSiLibraryPpi->IioIsStackPresent (Socket, StackIndex)) { + // + // Skips stacks which are not present on the platform + // + continue; + } + // + // Override if QAT is enabled + // + if (IsQatUplinkOverrideNeeded (Socket, Iou, DynamicSiLibraryPpi, &Bi= furcation)) { + if (IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D=3D IIO_BIF= URCATE_AUTO) { + IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D Bifurcation; + IIO_D_UBALOG ("[%d.%d] QAT-uplink detected; bif=3D%d\n", Socket,= StackIndex, Bifurcation); + } + } else if (IsQatCableOverrideNeeded (Socket, Iou, DynamicSiLibraryPp= i, &Bifurcation)) { + if (IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D=3D IIO_BIF= URCATE_AUTO) { + IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D Bifurcation; + IIO_D_UBALOG ("[%d.%d] QAT-cable detected; bif=3D%d\n", Socket, = StackIndex, Bifurcation); + } + } + } // for each Iou + } // for each Socket +} + +/** + Check if MRL sensor is present for given port. + It depends on board architecture. + Sometimes slot doesn't support it in contrast to Ext.Card. + + @param[in] TotalPortIndex Index of the port (across all ports on platf= orm) + @param[in] ExtCardPresent TRUE if Ext. card presence was detected + + @return TRUE if MRL sensor presence is expected + */ +BOOLEAN +IsMrlSensorPresent ( + IN UINT16 TotalPortIndex, + IN BOOLEAN ExtCardPresent + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + // + // This data should be read from platform specific config (slot table II= O_BIFURCATION_DATA_ENTRY_EX) + // but for now there is no such information + // Let this be a temp. workaround until the update of UBA slot configs + // + + if (ExtCardPresent) { + // + // MRL sensor is always present for Ext. Cards + // + return TRUE; + } + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT (FALSE); + return FALSE; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + switch (PlatformInfo->BoardId) { + case TypeWilsonCityRP: + // + // This is version for ICX + // + switch (TotalPortIndex) { + case SOCKET_1_INDEX + PORT_1A_INDEX: + case SOCKET_1_INDEX + PORT_1B_INDEX: + case SOCKET_1_INDEX + PORT_1C_INDEX: + case SOCKET_1_INDEX + PORT_1D_INDEX: + // + // only one slot on WilsonCity supports MRL + // + return TRUE; + default: + return FALSE; + } + break; + + case TypeCooperCityRP: + // + // Let's assume that MRL is supported by all slots on CooperCity - whe= re HP is enabled! + // + return TRUE; + default: + // + // For the rest of platforms the situation is unknown for now + // + return FALSE; + } +} + +/** + Verify if VMD is enabled and override Slot configuration + based on the VMD settings + + @param[in] IioGlobalData Pointer to Iio Globals. + @param[in] Slot Slot configuration settings + @param[in] SlotEntries Number of slot entries + @param[in] ExtCardPresent Table with results of Ext. Card dete= ction +**/ +#define SLOT_NUM_OFFSET_FOR_EXT_CARD_SLOT 0x50 + +VOID +ConfigureSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_DATA_ENTRY_EX *Slot, + IN UINT8 SlotEntries, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi, + IN BOOLEAN ExtCardPresent[MAX_SOCKET][MAX_IOU_PE= R_SOCKET] + ) +{ + UINT8 Index; + UINT16 TotalPortIndex; + UINT8 IioIndex =3D 0; + UINT8 Stack; + UINT8 PortIndex =3D 0; + UINT8 Iou; + BOOLEAN IsHpSupportedBySlot; + BOOLEAN IsVmdEnabledForSlot =3D TRUE; + BOOLEAN IsExtCardInSlot =3D TRUE; + BOOLEAN AreLanesAssignedToPort =3D TRUE; + + for (Index =3D 0; Index < SlotEntries; Index ++) { + + TotalPortIndex =3D Slot[Index].PortIndex; + if (DynamicSiLibraryPpi->GetMaxPortNumPerSocket() =3D=3D 0 || DynamicS= iLibraryPpi->GetMaxPortNumPerSocket() =3D=3D 0) { + return; + } + IioIndex =3D (UINT8) (TotalPortIndex / DynamicSiLibraryPpi->GetMaxPort= NumPerSocket ()); + PortIndex =3D (UINT8) (TotalPortIndex - (IioIndex * DynamicSiLibraryPp= i->GetMaxPortNumPerSocket ())); + Stack =3D IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][PortIn= dex]; + Iou =3D Stack - 1; + IsHpSupportedBySlot =3D FALSE; + IsVmdEnabledForSlot =3D DynamicSiLibraryPpi->IsVMDEnabledForPort (IioI= ndex, PortIndex); + IsExtCardInSlot =3D (Slot[Index].ExtensionCardSupport && ExtCardPresen= t[IioIndex][Iou]); + AreLanesAssignedToPort =3D DynamicSiLibraryPpi->IioAreLanesAssignedToP= ort (IioGlobalData, IioIndex, PortIndex); + + if (Slot[Index].Hidden || !AreLanesAssignedToPort) { + // + // Hide rootports which are hidden in slots table or don't have any = lanes assigned + // + IioGlobalData->SetupData.HidePEXPMenu[TotalPortIndex] =3D HIDE; + IioGlobalData->SetupData.PEXPHIDE[TotalPortIndex] =3D HIDE; + } else { + // + // Unhide active rootports (hided by default) + // + IioGlobalData->SetupData.HidePEXPMenu[TotalPortIndex] =3D NOT_HIDE; + IioGlobalData->SetupData.PEXPHIDE[TotalPortIndex] =3D NOT_HIDE; + } + + if (Slot[Index].SlotPowerLimitScale !=3D PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[TotalPortIndex] =3D Slot[Index].Sl= otPowerLimitScale; + IioGlobalData->SetupData.SLOTSPLV[TotalPortIndex] =3D Slot[Index].Sl= otPowerLimitValue; + } + + if (Slot[Index].SlotNumber !=3D NO_SLT_IMP) { + IioGlobalData->SetupData.SLOTIMP[TotalPortIndex] =3D SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[TotalPortIndex] =3D Slot[Index].Sl= otNumber; + } else if (AreLanesAssignedToPort) { + // + // If slot is not marked as implemented yet, but is exposed in curre= nt bifurcation + // assume that there will be a slot + // + IioGlobalData->SetupData.SLOTIMP[TotalPortIndex] =3D 1; + IioGlobalData->SetupData.SLOTPSP[TotalPortIndex] =3D SLOT_NUM_OFFSET= _FOR_EXT_CARD_SLOT + TotalPortIndex; + } + + if (IsVmdEnabledForSlot) { + // + // Disable Electromechanical Interlock presence for VMD + // + IioGlobalData->SetupData.SLOTEIP[TotalPortIndex] =3D DISABLE; + } else { + IioGlobalData->SetupData.SLOTEIP[TotalPortIndex] =3D Slot[Index].Int= erLockPresent; + } + + // + // HotPlug related settings: + // - first check the presence of Ext. Card in the slot and apply spec= ific setting + // - next apply common settings for HotPlug + // + if (IsExtCardInSlot && Slot[Index].ExtnCardHotPlugCapable) { + IsHpSupportedBySlot =3D TRUE; + // + // Apply specific overrides for HP with Ext. Card + // + if (Slot[Index].ExtnCardHPVppPort !=3D VPP_PORT_MAX) { + IioGlobalData->SetupData.VppEnabled[TotalPortIndex] =3D TRUE; + IioGlobalData->SetupData.VppPort[TotalPortIndex] =3D Slot[Index= ].ExtnCardHPVppPort; + IioGlobalData->SetupData.VppAddress[TotalPortIndex] =3D Slot[Index= ].ExtnCardHPVppAddress; + } + } else if (Slot[Index].HotPlugCapable) { + // + // HP settings when there is no Ext. Card + // + IsHpSupportedBySlot =3D TRUE; + + if (Slot[Index].VppPort !=3D VPP_PORT_MAX) { + IioGlobalData->SetupData.VppEnabled[TotalPortIndex] =3D TRUE; + IioGlobalData->SetupData.VppPort[TotalPortIndex] =3D Slot[Index= ].VppPort; + IioGlobalData->SetupData.VppAddress[TotalPortIndex] =3D Slot[Index= ].VppAddress; + } + } + + if (IsHpSupportedBySlot) { + // + // There are common setting for HP + // + IioGlobalData->SetupData.SLOTHPCAP[TotalPortIndex] =3D ENABLE; + IioGlobalData->SetupData.SLOTAIP[TotalPortIndex] =3D ENABLE; // = Attention Indicator Present + IioGlobalData->SetupData.SLOTPIP[TotalPortIndex] =3D ENABLE; // = Power Indicator Present + + if (IsVmdEnabledForSlot) { + IioGlobalData->SetupData.SLOTHPSUP[TotalPortIndex] =3D ENABLE; // = HotPlug Surprise is always enabled for VMD + } + + if (!IsVmdEnabledForSlot && IsMrlSensorPresent (TotalPortIndex, IsEx= tCardInSlot)) { + // + // Let's assume that if MRL sensor is present Attention button and= Power Controller is also present + // + IioGlobalData->SetupData.SLOTMRLSP[TotalPortIndex] =3D ENABLE; + IioGlobalData->SetupData.SLOTABP[TotalPortIndex] =3D ENABLE; + IioGlobalData->SetupData.SLOTPCP[TotalPortIndex] =3D ENABLE; + } else { + IioGlobalData->SetupData.SLOTMRLSP[TotalPortIndex] =3D DISABLE; + IioGlobalData->SetupData.SLOTABP[TotalPortIndex] =3D DISABLE; + IioGlobalData->SetupData.SLOTPCP[TotalPortIndex] =3D DISABLE; + } + } + } // for each slot entry +} + +/** + Check if lanes are reversed for given IOU - this is important when non-s= ymetrical + bifurcation is requested. + + @param[in] BifurcationTable record from bifurcation table + + @return TRUE if lanes are in reversed order + */ +BOOLEAN +IsLaneReversed ( + IN IIO_BIFURCATION_DATA_ENTRY_EX *BifurcationTable + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + // + // This data should be read from platform specific config - but for now = we don't have this information there + // Let this be a temp. workaround until the update of biffurcation confi= g. + // + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + if (GuidHob =3D=3D NULL) { + ASSERT (FALSE); + return FALSE; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + switch (PlatformInfo->BoardId) { + case TypeCooperCityRP: + // + // For CooperCityRP lane reversed are: + // - on even sockets: on IOU4 + // - on odd sockets: on IOU1 + // + return ((BifurcationTable->Socket&1) =3D=3D 1 && BifurcationTable->Iou= Number =3D=3D Iio_Iou1); + default: + // + // Let's assume that WilsonCity config is a default one. + // + // + // This is version for ICX (default) + // + return (BifurcationTable->Socket =3D=3D 1 && + (BifurcationTable->IouNumber =3D=3D Iio_Iou0 || Bifurca= tionTable->IouNumber =3D=3D Iio_Iou4)); + } +} + +/** + Read the bifurcation info stored at I/O Expander (PCA9554) which BIOS + can get through Smbus. + To communicate with IO Expander first MUX PCA9545 needs to be configured. + + The bifurcation encoding is [3:0]: + BW5_BIFURCATE_x4x4x4x4 1 0 0 0 + BW5_BIFURCATE_x4x4xxx8 1 0 0 1 Lanes to port ACD on board + BW5_BIFURCATE_xxx8x4x4 1 0 1 0 Lanes to port ABC on board + BW5_BIFURCATE_xxx8xxx8 1 0 1 1 Lanes to port AC on board + No BW5 1 1 x x + + @param IioGlobalData - Pointer to IioGlobals + @param BroadwayTablePtr - Pointer to BroadwayTable + + @retval IIO_BIFURCATE_xxxxxxxx BW communication failure + @retval IIO_BIFURCATE_x4x4x4x4 Requested bifurcation x4x4x4x4 + @retval IIO_BIFURCATE_x4x4xxx8 Requested bifurcation x4x4xxx8 + @retval IIO_BIFURCATE_xxx8x4x4 Requested bifurcation xxx8x4x4 + @retval IIO_BIFURCATE_xxx8xxx8 Requested bifurcation xxx8xxx8 +**/ +UINT8 +GetBw5Bifurcation ( + IN IIO_BIFURCATION_DATA_ENTRY_EX *BifurcationTable, + IN IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SmbDevAddr; + EFI_PEI_SMBUS2_PPI *SmbPpi =3D NULL; + UINT16 SmbData =3D 0; + UINT8 SmbByteData =3D 0; + UINT8 RetryCount; + UINTN SmbLen =3D 2; + UINTN SmbByteLen =3D 1; + + if (BifurcationTable->ExtnCardSMBusAddress =3D=3D SMB_ADDR_MAX ) { + return IIO_BIFURCATE_xxxxxxxx; + } + + Status =3D PeiServicesLocatePpi (&gEfiPeiSmbus2PpiGuid, 0, NULL, &SmbPpi= ); + + // Initialize Bw5Id to not present + + if (Status !=3D EFI_SUCCESS || SmbPpi =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[Iio] Get SMBus protocol error %x\n", Status)); + return IIO_BIFURCATE_xxxxxxxx; + } + + for (RetryCount =3D 0; RetryCount < NUM_OF_RETRIES; RetryCount++) { + + // + // Configure through the smbus MUX PCA9545 to start communicate to GPI= O expander + // + SmbDevAddr.SmbusDeviceAddress =3D BifurcationTable->MuxSMBusAddress >>= 1; + SmbByteData =3D BifurcationTable->MuxSMBusChannel; + Status =3D SmbPpi->Execute (SmbPpi, SmbDevAddr, 0, EfiSmbusSendByte, F= ALSE, &SmbByteLen, &SmbByteData); + if (EFI_ERROR (Status)) { + continue; + } + + // + // Read the current I/O pins configuration for Port0 + // + SmbDevAddr.SmbusDeviceAddress =3D BifurcationTable->ExtnCardSMBusAddre= ss >> 1; + Status =3D SmbPpi->Execute (SmbPpi, SmbDevAddr, BW4_CONFIG_OFFSET, Efi= SmbusReadWord, FALSE, &SmbLen, &SmbData); + if (!EFI_ERROR (Status)) { + // + // Configure the direction of I/O pins for Port0/Port1 as Input. + // + SmbData =3D SmbData | BW5_CONFIG_REG_MASK; + Status =3D SmbPpi->Execute (SmbPpi, SmbDevAddr, BW4_CONFIG_OFFSET, E= fiSmbusWriteWord, FALSE, &SmbLen, &SmbData); + if (!EFI_ERROR (Status)) { + // + // Read Input Port0/Port1 register to identify BW5 Id + // + Status =3D SmbPpi->Execute (SmbPpi, SmbDevAddr, BW4_DATA_OFFSET, E= fiSmbusReadWord, FALSE, &SmbLen, &SmbData); + if (!EFI_ERROR (Status)){ + // + // Mask the Input Port0/1 register data [15:0] to get BW5 ID [3:= 0]. + // + // The bifurcation encoding is [3:0]: + // BW5_BIFURCATE_x4x4x4x4 1 0 0 0 + // BW5_BIFURCATE_x4x4xxx8 1 0 0 1 Lanes to port ACD on board + // BW5_BIFURCATE_xxx8x4x4 1 0 1 0 Lanes to port ABC on board + // BW5_BIFURCATE_xxx8xxx8 1 0 1 1 Lanes to port AC on board + // No BW5 1 1 x x + // + switch (SmbData & 0xF) { + case 0x8: + return IIO_BIFURCATE_x4x4x4x4; + break; + case 0x9: + if (IsLaneReversed (BifurcationTable)) { + return IIO_BIFURCATE_xxx8x4x4; + } else { + return IIO_BIFURCATE_x4x4xxx8; + } + break; + case 0xA: + if (IsLaneReversed (BifurcationTable)) { + return IIO_BIFURCATE_x4x4xxx8; + } else { + return IIO_BIFURCATE_xxx8x4x4; + } + break; + case 0xB: + return IIO_BIFURCATE_xxx8xxx8; + break; + default: + return IIO_BIFURCATE_xxxxxxxx; + break; + } + } // Read Port0 + } // Configure Port0 + } // Read Port0 Config + + // + // Configure through the smbus MUX PCA9545 to end communicate to GPIO = expander + // + SmbDevAddr.SmbusDeviceAddress =3D BifurcationTable->MuxSMBusAddress >>= 1; + SmbByteData &=3D ~BifurcationTable->MuxSMBusChannel; + Status =3D SmbPpi->Execute (SmbPpi, SmbDevAddr, 0, EfiSmbusSendByte, F= ALSE, &SmbByteLen, &SmbByteData); + if (EFI_ERROR (Status)) { + continue; + } + } //RetryCount + + return IIO_BIFURCATE_xxxxxxxx; +} + +/** + Set bifurcation base of default settings and Ext. Card presence + (detected by BW) + + @param[in] IioGlobalData Pointer to Iio Globals. + @param[in] BifurcationTable Bifurcation configuration settings + @param[in] BifurcationEntries Number of bif. table entries + @param[in] ExtCardPresent Table with results of Ext. Card dete= ction +**/ +VOID +DetectExtCards ( + IN IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_DATA_ENTRY_EX *BifurcationTable, + IN UINT8 BifurcationEntries, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi, + OUT BOOLEAN ExtCardPresent[MAX_SOCKET][MAX_IOU_P= ER_SOCKET] + ) +{ + UINT8 Index; + UINT8 BwBifurcation; + UINT8 Socket; + UINT8 Iou; + + // + // Try to communicate with Ext.Card which can request custom bifurcation= on the stack + // + for (Index =3D 0; Index < BifurcationEntries; Index++){ + + Socket =3D BifurcationTable[Index].Socket; + Iou =3D BifurcationTable[Index].IouNumber; + + ExtCardPresent[Socket][Iou] =3D FALSE; // by default + + if (BifurcationTable[Index].ExtnCardSMBusAddress !=3D SMB_ADDR_MAX) { + // + // ExtCard can be supported at this stack - try to detect it + // + BwBifurcation =3D GetBw5Bifurcation (&BifurcationTable[Index], Dynam= icSiLibraryPpi); + if (BwBifurcation !=3D IIO_BIFURCATE_xxxxxxxx) { + // + // Ext. Card is detected on this IOU + // + IIO_D_UBALOG ("[%d.%d] Ext. Card detected; bif=3D%d\n", Socket, Io= u+1, BwBifurcation); + ExtCardPresent[Socket][Iou] =3D TRUE; + } + } + + // + // Set custom bifurcation requested by Ext. Card + // + if (IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D=3D IIO_BIFURCA= TE_AUTO) { + // + // There are no overrides for this IOU + // + if (ExtCardPresent[Socket][Iou]) { + // + // Set bifurcation requested by Ext. Card + // + IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D BwBifurcation; + } else { + // + // Set the default bifurcation for this IOU + // + IioGlobalData->SetupData.ConfigIOU[Socket][Iou] =3D BifurcationTab= le[Index].Bifurcation; + } + } + + IIO_D_UBADBG ("[%d.%d] final bifurcation =3D %X\n", Socket, Iou+1, Iio= GlobalData->SetupData.ConfigIOU[Socket][Iou]); + + } // for bifurcation table entry +} + +/** + Dump prepared configuration to log. + + @param[in] SetupData Pointer to SetupData structure +**/ +VOID +DumpConfiguration ( + IN IIO_CONFIG *SetupData, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ) +{ + UINT8 IioIndex; + UINT8 StackIndex =3D 0; + UINT8 Iou; + UINT8 PortIndex =3D 0; + UINT8 PortInStackIndex =3D 0; + UINT16 TotalPortIndex =3D0; + + for (IioIndex =3D 0; IioIndex < MAX_SOCKET ; IioIndex++) { + + if (!DynamicSiLibraryPpi->IioIsSocketPresent (IioIndex)) { + // + // Skips sockets which are not present on the platform + // + continue; + } + for (StackIndex =3D 0; StackIndex < DynamicSiLibraryPpi->GetMaxStackN= umPerSocket (); StackIndex++) { + + if (DynamicSiLibraryPpi->IsDmiStack (StackIndex)) { + // + // Skip DMI stacks in dump + // + continue; + } + + if (!DynamicSiLibraryPpi->IioIsStackPresent (IioIndex, StackIndex)) { + // + // Skips stacks which are not present on the platform + // + continue; + } + + if (StackIndex >=3D MAX_IIO_STACK) { + break; + } + Iou =3D StackIndex - 1; + + IIO_D_UBALOG("[%d.%d] Bifurcation =3D %X\n", IioIndex, StackIndex, S= etupData->ConfigIOU[IioIndex][Iou]); + IIO_D_UBALOG (" [ IDX ], PortHide, SlotImpl, SlotNumber, HotPlug, = Vpp, Interlock\n"); + + for (PortInStackIndex =3D 0; PortInStackIndex < DynamicSiLibraryPpi-= >GetMaxPortNumPerStack (StackIndex); PortInStackIndex++) { + PortIndex =3D DynamicSiLibraryPpi->GetPortIndexbyStack (StackIndex= , PortInStackIndex); + TotalPortIndex =3D (IioIndex * DynamicSiLibraryPpi->GetMaxPortNumP= erSocket ()) + PortIndex; + IIO_D_UBALOG (" [%d p%02d] %2d | %2d | %3d | %= 3d | 0x%02x | %2d \n", + IioIndex, PortIndex, + SetupData->PEXPHIDE[TotalPortIndex], + SetupData->SLOTIMP[TotalPortIndex], + SetupData->SLOTPSP[TotalPortIndex], + SetupData->SLOTHPCAP[TotalPortIndex], + SetupData->VppAddress[TotalPortIndex] | SetupData->= VppPort[TotalPortIndex], + SetupData->SLOTEIP[TotalPortIndex]); + } // foreach PortInStack + } //foreach StackIndex + } // foreach IioIndex +} + +/** + This function prepare the data for silicon initialization based on + bifurcations and slots table + + This function is for tables in version PLATFORM_IIO_CONFIG_UPDATE_VERSIO= N =3D 2 + + @param[in] IioGlobalData IIO Global data structure + @param[in] IioConfigTable + */ +VOID +IioPortBifurcationInitVer2 ( + IN IIO_GLOBALS *IioGlobalData, + IN PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX IioConfigTable, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ) +{ + IIO_BIFURCATION_DATA_ENTRY_EX *BifurcationTableEx; + UINT8 BifurcationEntries; + IIO_SLOT_CONFIG_DATA_ENTRY_EX *SlotTableEx; + UINT8 SlotEntries; + BOOLEAN ExtCardDetected[MAX_SOCKET][MAX_IOU_PER_= SOCKET]; + + // + // Init bifurcation and slots tables + // + BifurcationTableEx =3D IioConfigTable.IioBifurcationTablePtr; + BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize /= sizeof (IIO_BIFURCATION_DATA_ENTRY_EX)); + SlotTableEx =3D IioConfigTable.IioSlotTablePtr; + SlotEntries =3D (UINT8) (IioConfigTable.IioSlotTableSize / sizeof (IIO_S= LOT_CONFIG_DATA_ENTRY_EX)); + + // + // Set the bifurcations for each IOU: + // - if any override is set in setup menu - stay bifurcation not changed + // - next check if QAT is detected (this is LBG specific) - QAT require= s special bifurcation + // - next try to detect ext. cards with BW bifurcation + // - at the end set default bifurcation if no other options wer applied= before + + if (DynamicSiLibraryPpi->IsCpuAndRevision (CPU_ICXSP, REV_ALL) || + DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CPX, REV_ALL) || + DynamicSiLibraryPpi->IsCpuAndRevision (CPU_SKX, REV_ALL) || + DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CLX, REV_ALL) + ) { + // + // This is important only for programs with LBG PCH + // + CheckQatBifurcationOverrides (IioGlobalData, DynamicSiLibraryPpi); + } + DetectExtCards (IioGlobalData, BifurcationTableEx, BifurcationEntries, D= ynamicSiLibraryPpi, ExtCardDetected); + + // + // Set each rootport settings based on slots table + // + ConfigureSlots (IioGlobalData, SlotTableEx, SlotEntries, DynamicSiLibrar= yPpi, ExtCardDetected); + + // + // Configuration is ready - dump the config to log + // + DumpConfiguration (&IioGlobalData->SetupData, DynamicSiLibraryPpi); +} + +/** + + Program the IIO_GLOBALS data structure with OEM IIO init values for SLOT= s and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS data structure. + + @retval EFI_SUCCESS +**/ +VOID +IioPortBifurcationInitCallback ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX IioConfigTable; + UINTN TableSize; + + // + // Locate PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX + // + Status =3D PeiServicesLocatePpi (&gUbaConfigDatabasePpiGuid, 0, NULL, &U= baConfigPpi); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + TableSize =3D sizeof (IioConfigTable); + Status =3D UbaConfigPpi->GetData (UbaConfigPpi, &gPlatformIioConfigDataG= uid, &IioConfigTable, &TableSize); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + + // + // Call the right version of bifurcation init procedure + // + switch (IioConfigTable.Version) { + case PLATFORM_IIO_CONFIG_UPDATE_VERSION_2: + IioPortBifurcationInitVer2 (IioGlobalData, IioConfigTable, DynamicSiLi= braryPpi); + break; + case PLATFORM_IIO_CONFIG_UPDATE_VERSION: + IioPortBifurcationInitVer1 (IioGlobalData); + break; + default: + ASSERT (FALSE); + break; + } +} + +IIO_PORT_BIFURCATION_INIT_TABLE IioPortBifurcationInitTable =3D + { + IIO_PORT_BIFURCATION_INIT_SIGNATURE, + IIO_PORT_BIFURCATION_INIT_VERSION, + IioPortBifurcationInitCallback + }; + +EFI_STATUS +InstallIioPortBifurcationInitData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + return UbaConfigPpi->AddData ( + UbaConfigPpi, + &gIioPortBifurcationInitDataGuid, + &IioPortBifurcationInitTable, + sizeof (IioPortBifurcationInitTable) + ); +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioP= ortBifurcationVer1.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Commo= n/Pei/IioPortBifurcationVer1.c new file mode 100644 index 0000000000..8666717a8d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/IioPortBifu= rcationVer1.c @@ -0,0 +1,1356 @@ +/** @file + Install Iio Port Bifurcation Init Data. + This is depreciated version of the code used for PLATFORM_IIO_CONFIG_UPD= ATE_VERSION =3D=3D 1 + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCommonBoardInitLib.h" +#include +#include +#include +#include +#include +#include +#include +#include "IioBifurcationSlotTable.h" +#include +#include +#include +#include +#include +#include +#include + +/** + Function returns the board ID from running HW + + @return BoardId +**/ +UINT8 +EFIAPI +SystemBoardIdValue ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *mPlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return TypePlatformUnknown; + } + mPlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + return mPlatformInfo->BoardId; +} + + +/** + DVP/Neon City platform support BW5 bifurcation card in socket0 and socke= t1 + Lightning Ridge platform support BW5 bifurcation card in socket1, socket= 2 and socket3 + The bifurcation info stored at I/O Expander (PCA9555) which BIOS + can get through Smbus read. + + PCA9555 SMBus slave Address: 0x4C + +---------------------------------- + Neon +---------------------------------- + data0 =3D BW5 socket0 iio2 + data1 =3D BW5 socket1 iio0 + data2 =3D BW5 socket1 iio3 +---------------------------------- + Lighting Ridge +---------------------------------- + data1 =3D BW5 socket1 iio2 + data2 =3D BW5 socket2 iio1 + data3 =3D BW5 socket3 iio3 + + The bifurcation encoding is [2:0]: + BW5_BIFURCATE_x4x4x4x4 x 0 0 0 + BW5_BIFURCATE_xxx8x4x4 x 0 0 1 + BW5_BIFURCATE_x4x4xxx8 x 0 1 0 + BW5_BIFURCATE_xxx8xxx8 x 0 1 1 + No BW5 x 1 1 1 + + @param IioGlobalData - Pointer to IioGlobals + @param Bw5Id - Pointer to BW5ID + + @retval None + +**/ +VOID +GetBw5Id ( + IN IIO_GLOBALS *IioGlobalData, + IN OUT BW5_BIFURCATION_DATA_STRUCT *Bw5Id + ) +{ + CONST EFI_PEI_SERVICES **PeiServices; + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress; + EFI_SMBUS_DEVICE_COMMAND SmbusCommand; + EFI_PEI_SMBUS2_PPI *Smbus =3D NULL; + UINT16 SmbusData =3D 0; + UINT8 RetryCount; + UINTN SmbusLength =3D 2; + UINT8 Index; + + PeiServices =3D GetPeiServicesTablePointer (); + + Status =3D (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiSmbus2PpiGuid, + 0, + NULL, + &Smbus + ); + + // Initialize Bw5Id to not present + for (Index =3D 0; Index < BW5_CARDS_PRESENT; Index++){ + Bw5Id[Index].Data =3D BW5_CARD_NOT_PRESENT; + } + + if (Status !=3D EFI_SUCCESS || Smbus =3D=3D NULL) { + DEBUG ((EFI_D_INFO, "!!!!Get SMBus protocol error %x\n", Status)); + } else { + + // Read Socket 0 HP Controller + SmbusDeviceAddress.SmbusDeviceAddress =3D (BW5_SMBUS_ADDRESS >> 1); + + for (RetryCount =3D 0; RetryCount < NUM_OF_RETRIES; RetryCount++) { + // + // Read the current I/O pins Config for Port0 + // + SmbusCommand =3D PCA9555_COMMAND_CONFIG_PORT0_REG; + Status =3D Smbus->Execute ( + Smbus, + SmbusDeviceAddress, + SmbusCommand, + EfiSmbusReadWord, + FALSE, + &SmbusLength, + &SmbusData + ); + if (!EFI_ERROR(Status)) { + // + // Configure the direction of I/O pins for Port0/Port1 as Input. + // + SmbusData =3D SmbusData | BW5_CONFIG_REG_MASK; + Status =3D Smbus->Execute ( + Smbus, + SmbusDeviceAddress, + SmbusCommand, + EfiSmbusWriteWord, + FALSE, + &SmbusLength, + &SmbusData + ); + if (!EFI_ERROR(Status)) { + // + // Read Input Port0/Port1 register to identify BW5 Id + // + SmbusCommand =3D PCA9555_COMMAND_INPUT_PORT0_REG; + Status =3D Smbus->Execute( Smbus, + SmbusDeviceAddress, + SmbusCommand, + EfiSmbusReadWord, + FALSE, + &SmbusLength, + &SmbusData ); + if (!EFI_ERROR(Status)){ + DEBUG ((EFI_D_INFO, "SmbusData Port0/1 %x\n", SmbusData)); + // + // Mask the Input Port0/1 register data [15:0] to get BW5 ID. + // + Bw5Id[0].Data =3D (SmbusData & BW5_0_ID_MASK); + Bw5Id[1].Data =3D (SmbusData & BW5_1_ID_MASK) >> 4; + Bw5Id[2].Data =3D (SmbusData & BW5_2_ID_MASK) >> 8; + Bw5Id[3].Data =3D (SmbusData & BW5_3_ID_MASK) >> 12; + break; // Break Loop if read was successfully. + } // Read Port0 + } // Configure Port0 + } // Read Port0 Config + } //RetryCount + } // (Status !=3D EFI_SUCCESS || Smbus =3D=3D NULL) + + return; +} + +EFI_STATUS +InternalPlatformGetSlotTableData2 ( + IN OUT IIO_BROADWAY_ADDRESS_DATA_ENTRY **BroadwayTable, + IN OUT UINT8 *IOU0Setting, + IN OUT UINT8 *FlagValue, + IN OUT UINT8 *IOU2Setting, + IN UINT8 SkuPersonalityType + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_SLOT_UPDATE_TABLE2 IioSlotTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + TableSize =3D sizeof(IioSlotTable); + if ((SkuPersonalityType =3D=3D 1) || (SkuPersonalityType =3D=3D 3)) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2_1, + &IioSlotTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &IioSlotTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioSlotTable.Signature =3D=3D PLATFORM_SLOT_UPDATE_SIGNATURE); + ASSERT (IioSlotTable.Version =3D=3D PLATFORM_SLOT_UPDATE_VERSION); + + *BroadwayTable =3D IioSlotTable.BroadwayTablePtr; + *IOU0Setting =3D IioSlotTable.GetIOU0Setting (*IOU0Setting); + *FlagValue =3D IioSlotTable.FlagValue; + *IOU2Setting =3D IioSlotTable.GetIOU2Setting (SkuPersonalityType, *IOU= 2Setting); + + return Status; +} + +EFI_STATUS +InternalPlatformIioConfigInit2 ( + IN UINT8 SkuPersonalityType, + IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + if (SkuPersonalityType =3D=3D 1) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 2) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + &IioConfigTable, + &TableSize + ); + } else if (SkuPersonalityType =3D=3D 3) { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + &IioConfigTable, + &TableSize + ); + } else { + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + } + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + *BifurcationTable =3D IioConfigTable.IioBifurcationTablePtr; + *BifurcationEntries =3D (UINT8) (IioConfigTable.IioBifurcationTableSize = / sizeof(IIO_BIFURCATION_DATA_ENTRY)); + + *SlotTable =3D IioConfigTable.IioSlotTablePtr; + *SlotEntries =3D (UINT8) (IioConfigTable.IioSlotTableSize / sizeof(IIO_S= LOT_CONFIG_DATA_ENTRY)); + + return Status; +} + +VOID +EnableHotPlug_SKX ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port, + IN UINT8 VppPort, + IN UINT8 VppAddress, + IN UINT8 PortOwnership + ) +{ + IioGlobalData->SetupData.SLOTHPCAP[Port]=3D ENABLE; + IioGlobalData->SetupData.SLOTAIP[Port] =3D ENABLE; // Attention Indica= tor Present + IioGlobalData->SetupData.SLOTPIP[Port] =3D ENABLE; // Power Indicator = Present + IioGlobalData->SetupData.SLOTMRLSP[Port]=3D ENABLE; // MRL Sensor Present + IioGlobalData->SetupData.SLOTABP[Port] =3D ENABLE; // Attention Button = Present + IioGlobalData->SetupData.SLOTPCP[Port] =3D ENABLE; // Power Controlled = Present + + if (PortOwnership =3D=3D PCIEAIC_OCL_OWNERSHIP){ + IioGlobalData->SetupData.SLOTAIP[Port] =3D DISABLE; // Attention Ind= icator Present + IioGlobalData->SetupData.SLOTPIP[Port] =3D DISABLE; // Power Indicat= or Present + } + if (PortOwnership =3D=3D VMD_OWNERSHIP){ + IioGlobalData->SetupData.SLOTABP[Port] =3D DISABLE; + IioGlobalData->SetupData.SLOTPCP[Port] =3D DISABLE; + IioGlobalData->SetupData.SLOTMRLSP[Port]=3D DISABLE; + } + // + // Set SLTCAP settings based on VMD/PCIe SSD Ownership + // + if ((PortOwnership =3D=3D PCIEAIC_OCL_OWNERSHIP) || + (PortOwnership =3D=3D VMD_OWNERSHIP)){ + IioGlobalData->SetupData.SLOTHPSUP[Port]=3D ENABLE; // HotPlug Surpr= ise + } + + if (VppPort!=3D VPP_PORT_MAX) { + IioGlobalData->SetupData.VppEnabled[Port]=3D TRUE; + IioGlobalData->SetupData.VppPort[Port]=3D VppPort; + IioGlobalData->SetupData.VppAddress[Port] =3D VppAddress; + } else { + DEBUG((EFI_D_ERROR, "PCIE HOT Plug. Missing VPP values on slot table= \n")); + } +} + +/** + Auto determine which PCIe Root port to be hidden if its + lanes are assigned to its preceding root port...use the + Setup option variable of ConfigIOU to determine which ports + are to be hidden on each IOU for corresponding IIO + + @param IOUx - IOUx Index + @param IioIndex - Index to Iio + @param IioGlobalData Pointer to Iio Globals. +**/ +VOID +CalculatePEXPHideFromIouBif_SKX ( + IN UINT8 Iou, + IN UINT8 IioIndex, + IN OUT IIO_GLOBALS *IioGlobalData + ) +{ + UINT8 *PXPHide, *HidePEXPMenu; + UINT8 CurrentIOUConfigValue; + UINT8 PXPOffset; + UINT8 MaxPortNumberPerSocket; + + if (IioIndex >=3D MaxIIO || Iou >=3D NELEMENTS (IioGlobalData->SetupData= .ConfigIOU[IioIndex])) { + + DEBUG ((DEBUG_ERROR, "[IIO] ERROR: %a: IIO instance %d or IOU %d out o= f range", __FUNCTION__, IioIndex, Iou)); + ASSERT (FALSE); + return; + } + PXPHide =3D IioGlobalData->SetupData.PEXPHIDE; + HidePEXPMenu =3D IioGlobalData->SetupData.HidePEXPMenu; + MaxPortNumberPerSocket =3D IioGlobalData->IioVar.IioOutData.MaxPciePortN= umberPerSocket[IioIndex]; + + PXPOffset =3D IioIndex * MaxPortNumberPerSocket; + + CurrentIOUConfigValue =3D IioGlobalData->SetupData.ConfigIOU[IioIndex][I= ou]; + switch (Iou) { + case Iio_Iou0: + PXPOffset +=3D PORT_1A_INDEX; + break; + case Iio_Iou1: + PXPOffset +=3D PORT_2A_INDEX; + break; + case Iio_Iou2: + PXPOffset +=3D PORT_3A_INDEX; + break; + case Iio_Iou3: + PXPOffset +=3D PORT_4A_INDEX; + break; + case Iio_Iou4: + PXPOffset +=3D PORT_5A_INDEX; + break; + default: + break; + } + switch (CurrentIOUConfigValue) { + case IIO_BIFURCATE_xxxxxxxx: + PXPHide[PXPOffset + Iio_PortA] =3D HIDE; // hide A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D HIDE; // hide the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D HIDE; // hide the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_x4x4xxx8: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for D + HidePEXPMenu[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show the Setu= p menu for B + break; + case IIO_BIFURCATE_xxx8x4x4: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide port D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_xxx8xxx8: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + case IIO_BIFURCATE_xxxxxx16: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] =3D HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] =3D HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D HIDE; // hide the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D HIDE; // hide the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D HIDE; // hide the Setu= p menu for D + break; + default: + PXPHide[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show port D + HidePEXPMenu[PXPOffset + Iio_PortA] =3D NOT_HIDE; // show the Setu= p menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] =3D NOT_HIDE; // show the Setu= p menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] =3D NOT_HIDE; // show the Setu= p menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] =3D NOT_HIDE; // show the Setu= p menu for D + break; + } + // + // Change PEXPHIDE setting to hide all PCIe port of a IOU if IIO_BIFURCA= TE_xxxxxxxx is set. + // And set ConfigIOU/ConfigMCPx to default bifucation control value + // Bifurcation_Control[2:0] in IOU Bifurcation Control (PCIE_IOU_BIF_CTR= L) register should be 000b ~ 100b. + // + if (CurrentIOUConfigValue =3D=3D IIO_BIFURCATE_xxxxxxxx) { + + IioGlobalData->SetupData.ConfigIOU[IioIndex][Iou] =3D IIO_BIFURCATE_x4= x4x4x4; + } +} + +VOID +DumpPort_SKX( + IIO_GLOBALS *IioGlobalData, + UINT8 Port, + UINT8 NumberOfPorts +) +{ + UINT8 Index; + DEBUG((EFI_D_INFO, "IDX, Port Hide, Slot Impl, Slot Number, HotPlug, Pci= eSSD, VppPort, VppAddress, Interlock\n")); + for (Index =3D Port; Index < (Port + NumberOfPorts); Index++ ) { + DEBUG((EFI_D_INFO, "%3d| %2d | %2d | %3d | %3d | %= 3d | 0x%02x | 0x%02x | %2d \n", \ + Index, \ + IioGlobalData->SetupData.PEXPHIDE[Index], \ + IioGlobalData->SetupData.SLOTIMP[Index], \ + IioGlobalData->SetupData.SLOTPSP[Index], \ + IioGlobalData->SetupData.SLOTHPCAP[Index], \ + IioGlobalData->IioVar.IioOutData.PciePortOwnership[= Index], \ + IioGlobalData->SetupData.VppPort[Index], \ + IioGlobalData->SetupData.VppAddress[Index],\ + IioGlobalData->SetupData.SLOTEIP[Index])); + } +} + + +/// Dump iio configuration. Dump the current IIO configuration to the seri= al +/// log. +VOID +DumpIioConfiguration_SKX( + IN UINT8 iio, + IN IIO_GLOBALS *IioGlobalData +) +{ + UINT8 Iou; + UINT8 PortIndex; + UINT8 MaxPortNumberPerSocket; + UINT8 Bifurcation; + UINT8 IouPorts; + + MaxPortNumberPerSocket =3D IioGlobalData->IioVar.IioOutData.MaxPciePortN= umberPerSocket[iio]; + PortIndex =3D iio * MaxPortNumberPerSocket; + /// First dump the socket number; + DEBUG((EFI_D_INFO, "Socket number: %d \n", iio)); + + /// Dump DMI configuration: + if ((iio =3D=3D 0) && (PortIndex =3D=3D 0)){ + DEBUG((EFI_D_INFO, "PORT 0: DMI Port\n")); + } else { + DEBUG((EFI_D_INFO, "PORT 0: DMI Port working as PCIE\n")); + DumpPort_SKX(IioGlobalData, PortIndex, 1); + } + IouPorts=3D4; + /// Dump IOU bifurcations: + for (Iou =3D Iio_Iou0; Iou< Iio_IouMax; Iou ++) { + /// Reset port index. + PortIndex =3D iio * MaxPortNumberPerSocket; + // Get the bifurcation + switch (Iou) { + case Iio_Iou0: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU[iio][0]; + PortIndex +=3D PORT_1A_INDEX; + DEBUG((EFI_D_INFO, "IUO0: Root Port 1, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Iou1: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU[iio][1]; + PortIndex +=3D PORT_2A_INDEX; + DEBUG((EFI_D_INFO, "IUO1: Root Port 2, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Iou2: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU[iio][2]; + PortIndex +=3D PORT_3A_INDEX; + DEBUG((EFI_D_INFO, "IUO2: Root Port 3, Bifurcation: %d\n", Bifur= cation)); + break; + case Iio_Iou3: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU[iio][3]; + PortIndex +=3D PORT_4A_INDEX; + DEBUG((EFI_D_INFO, "IOU3, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Iou4: + Bifurcation =3D IioGlobalData->SetupData.ConfigIOU[iio][4]; + PortIndex +=3D PORT_5A_INDEX; + DEBUG((EFI_D_INFO, "IOU4, Bifurcation: %d\n", Bifurcation)); + break; + default: + DEBUG((EFI_D_INFO, "Iou no detected =3D %d",Iou)); + break; + } + DumpPort_SKX(IioGlobalData, PortIndex, IouPorts); + } +} + + +VOID +SystemHideIioPortsCommon_SKX( + IIO_GLOBALS *IioGlobalData, + UINT8 IioIndex + ) +{ + CalculatePEXPHideFromIouBif_SKX(Iio_Iou0, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif_SKX(Iio_Iou1, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif_SKX(Iio_Iou2, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif_SKX(Iio_Iou3, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif_SKX(Iio_Iou4, IioIndex, IioGlobalData); + DumpIioConfiguration_SKX(IioIndex, IioGlobalData); +} + +/** + Verify if and Slot should be implemented based on IOUX bifurcation set= tings. + + @param IioGlobalData Pointer to Iio Globals. + @param Port - Port Index + + @retval TRUE/FALSE to determine if an slot should be implement= ed or not + based on the IOUX bifurcation settings in c= ase user want to do an + override and VMD is enabled. + +**/ +BOOLEAN +SlotImplemented_SKX ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port + ) +{ + UINT8 IioIndex; + UINT8 MaxPortNumberPerSocket; + UINT8 PortIndex; + UINT8 Stack; + BOOLEAN SlotImp =3D FALSE; + + MaxPortNumberPerSocket =3D IioGlobalData->IioVar.IioOutData.MaxPciePortN= umberPerSocket[0]; + IioIndex =3D Port/MaxPortNumberPerSocket; + PortIndex =3D (Port - (MaxPortNumberPerSocket * IioIndex)); + Stack =3D IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][PortInde= x]; + DEBUG ((DEBUG_INFO, "SlotImplemented_SKX:IioIndex =3D %x, Stack =3D %x, = Port =3D %x, PortIndex =3D%x\n", IioIndex, Stack, Port, PortIndex)); + + switch (Stack) { + case IIO_PSTACK0: + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D IIO_BIFUR= CATE_x4x4x4x4) { + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D II= O_BIFURCATE_x4x4xxx8){ + if ((PortIndex =3D=3D PORT_1D_INDEX) || (PortIndex =3D=3D PORT_1C_= INDEX) || (PortIndex =3D=3D PORT_1A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D II= O_BIFURCATE_xxx8x4x4) { + if ((PortIndex =3D=3D PORT_1C_INDEX) || (PortIndex =3D=3D PORT_1B_= INDEX) || (PortIndex =3D=3D PORT_1A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D II= O_BIFURCATE_xxx8xxx8) { + if ((PortIndex =3D=3D PORT_1C_INDEX) || (PortIndex =3D=3D PORT_1A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D II= O_BIFURCATE_xxxxxx16) { + if (PortIndex =3D=3D PORT_1A_INDEX) { + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK1: + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D IIO_BIFUR= CATE_x4x4x4x4) { + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D II= O_BIFURCATE_x4x4xxx8) { + if ((PortIndex =3D=3D PORT_2D_INDEX) || (PortIndex =3D=3D PORT_2C_= INDEX) || (PortIndex =3D=3D PORT_2A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D II= O_BIFURCATE_xxx8x4x4){ + if ((PortIndex =3D=3D PORT_2C_INDEX) || (PortIndex =3D=3D PORT_2B_= INDEX) || (PortIndex =3D=3D PORT_2A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D II= O_BIFURCATE_xxx8xxx8) { + if ((PortIndex =3D=3D PORT_2C_INDEX) || (PortIndex =3D=3D PORT_2A_= INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D II= O_BIFURCATE_xxxxxx16) { + if (PortIndex =3D=3D PORT_2A_INDEX) { + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK2: + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D IIO_BIFUR= CATE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D II= O_BIFURCATE_x4x4xxx8) { + if ((PortIndex =3D=3D PORT_3D_INDEX) || (PortIndex =3D=3D PORT_3C_= INDEX) || (PortIndex =3D=3D PORT_3A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D II= O_BIFURCATE_xxx8x4x4) { + if ((PortIndex =3D=3D PORT_3C_INDEX) || (PortIndex =3D=3D PORT_3B_= INDEX) || (PortIndex =3D=3D PORT_3A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D II= O_BIFURCATE_xxx8xxx8) { + if ((PortIndex =3D=3D PORT_3C_INDEX) || (PortIndex =3D=3D PORT_3A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D II= O_BIFURCATE_xxxxxx16) { + if (PortIndex =3D=3D PORT_3A_INDEX) { + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK3: + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D IIO_BIFUR= CATE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D II= O_BIFURCATE_x4x4xxx8) { + if ((PortIndex =3D=3D PORT_4D_INDEX) || (PortIndex =3D=3D PORT_4C_= INDEX) || (PortIndex =3D=3D PORT_4A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D II= O_BIFURCATE_xxx8x4x4) { + if ((PortIndex =3D=3D PORT_4C_INDEX) || (PortIndex =3D=3D PORT_4B_= INDEX) || (PortIndex =3D=3D PORT_4A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D II= O_BIFURCATE_xxx8xxx8) { + if ((PortIndex =3D=3D PORT_4C_INDEX) || (PortIndex =3D=3D PORT_4A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D II= O_BIFURCATE_xxxxxx16) { + if (PortIndex =3D=3D PORT_4A_INDEX) { + SlotImp =3D TRUE; + } + } + break; + case IIO_PSTACK4: + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D IIO_BIFUR= CATE_x4x4x4x4){ + SlotImp =3D TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D II= O_BIFURCATE_x4x4xxx8) { + if ((PortIndex =3D=3D PORT_5D_INDEX) || (PortIndex =3D=3D PORT_5C_= INDEX) || (PortIndex =3D=3D PORT_5A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D II= O_BIFURCATE_xxx8x4x4) { + if ((PortIndex =3D=3D PORT_5C_INDEX) || (PortIndex =3D=3D PORT_5B_= INDEX) || (PortIndex =3D=3D PORT_5A_INDEX)) { + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D II= O_BIFURCATE_xxx8xxx8) { + if ((PortIndex =3D=3D PORT_5C_INDEX) || (PortIndex =3D=3D PORT_5A_= INDEX)){ + SlotImp =3D TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D II= O_BIFURCATE_xxxxxx16) { + if (PortIndex =3D=3D PORT_5A_INDEX) { + SlotImp =3D TRUE; + } + } + break; + default: + DEBUG ((EFI_D_INFO, "default case.\n")); //Auto added. Please revie= w. + break; + } + DEBUG ((DEBUG_INFO, "SlotImplemented_SKX: =3D %x\n", SlotImp)); + return SlotImp; +} + + +VOID +ConfigSlots_SKX ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_DATA_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + + for (Index =3D0; Index < SlotEntries; Index ++) { + Port=3DSlot[Index].PortIndex; + if (Slot[Index].Hidden !=3D NOT_HIDE) { + IioGlobalData->SetupData.HidePEXPMenu[Port] =3D HIDE; + IioGlobalData->SetupData.PEXPHIDE[Port]=3D HIDE; + } + /// Check if slot is assigned. + if (Slot[Index].SlotNumber!=3D NO_SLT_IMP){ + IioGlobalData->SetupData.SLOTIMP[Port]=3D SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port]=3DSlot[Index].SlotNumber; + IioGlobalData->SetupData.SLOTEIP[Port]=3DSlot[Index].InterLockPrese= nt; + if (Slot[Index].SlotPowerLimitScale!=3D PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] =3D Slot[Index].SlotPower= LimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] =3D Slot[Index].SlotPower= LimitValue; + } + if (Slot[Index].HotPlugCapable !=3D DISABLE) { + EnableHotPlug_SKX(IioGlobalData, Port, Slot[Index].VppPort, Slot[= Index].VppAddress, REGULAR_PCIE_OWNERSHIP); + } + } + } +} + + +EFI_STATUS +PlatformUpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi =3D NULL; + PLATFORM_IIO_CONFIG_UPDATE_TABLE IioConfigTable; + UINTN TableSize; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + TableSize =3D sizeof(IioConfigTable); + Status =3D UbaConfigPpi->GetData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &IioConfigTable, + &TableSize + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + ASSERT (IioConfigTable.Signature =3D=3D PLATFORM_IIO_CONFIG_UPDATE_SIGNA= TURE); + ASSERT (IioConfigTable.Version =3D=3D PLATFORM_IIO_CONFIG_UPDATE_VERSION= ); + + Status =3D IioConfigTable.CallUpdate (IioGlobalData); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +VOID +OverrideDefaultBifSlots_SKX ( + IN IIO_GLOBALS *IioGlobalData, + IN UINT8 BoardId, + IN BOOLEAN *AutoBifEnable +) +{ + EFI_STATUS Status; + UINT32 QATGpio; + PCIE_RISER_ID RightRiser; + PCIE_RISER_ID LeftRiser; + UINT32 RiserBit; + UINT8 Index; + BW5_BIFURCATION_DATA_STRUCT Bw5id[4]=3D {{{0,0,0,0,0}}, {{0,0,0,0,0,= }}, {{0,0,0,0,0}}, {{0,0,0,0,0}}}; // Default, no BW card. + IIO_BROADWAY_ADDRESS_ENTRY *BroadwayTable; + IIO_BROADWAY_ADDRESS_DATA_ENTRY *BroadwayTableTemp; + UINT8 IOU0Setting; + UINT8 IOU2Setting; + UINT8 FlagValue =3D 0; + UINT8 SkuPersonality =3D 0; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + BroadwayTable =3D NULL; + IOU0Setting =3D IioGlobalData->SetupData.ConfigIOU[Iio_Socket0][0]; + IOU2Setting =3D IioGlobalData->SetupData.ConfigIOU[Iio_Socket0][2]; + + // + // Specific platform overrides. + // + // Changes because GPIO (QAT, Riser Cards, etc). + // Read QAT and riser card GPIOs. + // + // Purley platforms need to read the QAT bit + // + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_ID,= GPIO_SKL_H_GPP_B3, &QATGpio); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_B3 Failed\n")); + return; + } + DEBUG ((EFI_D_INFO, "QAT GPIO: %d\n", QATGpio)); + + if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] =3D=3D TYPE_FPGA) = &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] =3D=3D TYPE_FPGA))= { + SkuPersonality =3D 1; + } else if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] =3D=3D TYPE= _FPGA) &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] !=3D TYPE_FPGA)) { + SkuPersonality =3D 2; + } else if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] !=3D TYPE_F= PGA) &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] =3D=3D TYPE_FPGA))= { + SkuPersonality =3D 3; + } else { + SkuPersonality =3D 0; + } + DEBUG((DEBUG_INFO, "SKU Personality Type: %d\n", SkuPersonality)); + + BroadwayTableTemp =3D (IIO_BROADWAY_ADDRESS_DATA_ENTRY *) BroadwayTable; + InternalPlatformGetSlotTableData2 (&BroadwayTableTemp, &IOU0Setting, &Fl= agValue, &IOU2Setting, SkuPersonality); + BroadwayTable =3D (IIO_BROADWAY_ADDRESS_ENTRY *)BroadwayTableTemp; //= if no platform definition, BroadwayTable will be NULL + + if (AutoBifEnable[(Iio_Socket0 * Iio_IouMax) + Iio_Iou2] =3D=3D TRUE) { + IioGlobalData->SetupData.ConfigIOU[Iio_Socket0][2] =3D IOU2Setting; + } + + if (FlagValue =3D=3D 1) { + // + // Right riser + // + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_B4, &RiserBit); // PresentSignal + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_B4 Failed\n")); + return; + } + RightRiser.Bits.PresentSignal =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_C15, &RiserBit); // HotPlugConf + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_C15 Failed\n")); + return; + } + RightRiser.Bits.HPConf =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_C16, &RiserBit); // WingConf + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_C16 Failed\n")); + return; + } + RightRiser.Bits.WingConf =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_C17, &RiserBit); // Slot9En + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_C17 Failed\n")); + return; + } + RightRiser.Bits.Slot9En =3D (UINT8) RiserBit; + + DEBUG ((EFI_D_INFO, "GPIO Right riser information: PresentSignal=3D%x,= HotPlugConf=3D%x, WingConf=3D%x, Slot9En=3D%x\n", + RightRiser.Bits.PresentSignal, RightRiser.Bits.HPConf, RightRi= ser.Bits.WingConf, RightRiser.Bits.Slot9En)); + + // + // Left riser + // + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_B5, &RiserBit); // PresentSignal + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_B5 Failed\n")); + return; + } + LeftRiser.Bits.PresentSignal =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_C18, &RiserBit); // HotPlugConf + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_C18 Failed\n")); + return; + } + LeftRiser.Bits.HPConf =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_C19, &RiserBit); // WingConf + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_C19 Failed\n")); + return; + } + LeftRiser.Bits.WingConf =3D (UINT8) RiserBit; + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_I= D, GPIO_SKL_H_GPP_B21, &RiserBit); // Slot9En + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Get GPIO_SKL_H_GPP_B21 Failed\n")); + return; + } + LeftRiser.Bits.Slot9En =3D (UINT8) RiserBit; + + DEBUG ((EFI_D_INFO, "GPIO Left riser information: PresentSignal=3D%x, = HotPlugConf=3D%x, WingConf=3D%x, Slot9En=3D%x\n", + LeftRiser.Bits.PresentSignal, LeftRiser.Bits.HPConf, LeftRiser= .Bits.WingConf, LeftRiser.Bits.Slot9En)); + } + + if (QATGpio =3D=3D QAT_ENABLED) { + // So Configuration of IUO0 is: + // 1A-1B - QAT xxx8 + // 1C - SSD x4 + // 1D - SSD x4 + if (AutoBifEnable[(Iio_Socket0 * Iio_IouMax) + Iio_Iou0] =3D=3D TRUE) { + IioGlobalData->SetupData.ConfigIOU[Iio_Socket0][0] =3D IOU0Setting; + } + } + + if (FlagValue =3D=3D 1) { + if (QATGpio !=3D QAT_ENABLED) { + if ((RightRiser.Bits.Slot9En =3D=3D RISER_SLOT9_DISABLE) && + (LeftRiser.Bits.Slot9En =3D=3D RISER_SLOT9_DISABLE)) { + // + // SLOT 9 is disabled. SSDs are present. + // Change configuration to x4x4x4x4. + // + if (AutoBifEnable[(Iio_Socket0 * Iio_IouMax) + Iio_Iou0] =3D=3D TR= UE) { + IioGlobalData->SetupData.ConfigIOU[Iio_Socket0][0] =3D IIO_BIFU= RCATE_x4x4x4x4; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[SOCKET_0_INDE= X + PORT_1A_INDEX] =3D PCIEAIC_OCL_OWNERSHIP; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[SOCKET_0_INDE= X + PORT_1B_INDEX] =3D PCIEAIC_OCL_OWNERSHIP; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[SOCKET_0_INDE= X + PORT_1C_INDEX] =3D PCIEAIC_OCL_OWNERSHIP; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[SOCKET_0_INDE= X + PORT_1D_INDEX] =3D PCIEAIC_OCL_OWNERSHIP; + } + } else if (RightRiser.Bits.PresentSignal =3D=3D RISER_PRESENT) { + // + // Slot 9 is enabled. Keep the xxxxxx16 configuration (default) and + // enable slot 9. Slot 9 supports HP. + // + IioGlobalData->SetupData.SLOTIMP[SOCKET_0_INDEX + PORT_1A_INDEX] = =3D 1; + IioGlobalData->SetupData.SLOTPSP[SOCKET_0_INDEX + PORT_1A_INDEX] = =3D 9; + } // End of RISER_PRESENT + } // End of QAT_ENABLED + + if (RightRiser.Bits.PresentSignal =3D=3D RISER_PRESENT) { + IioGlobalData->SetupData.SLOTIMP[SOCKET_0_INDEX + PORT_3A_INDEX] =3D= 1; +#if MAX_SOCKET > 2 + IioGlobalData->SetupData.SLOTIMP[SOCKET_3_INDEX + PORT_2A_INDEX] =3D= 1; + IioGlobalData->SetupData.SLOTIMP[SOCKET_3_INDEX + PORT_3A_INDEX] =3D= 1; +#endif // MAX_SOCKET > 2 + if (RightRiser.Bits.WingConf =3D=3D RISER_WINGED_IN) { + IioGlobalData->SetupData.SLOTPSP[SOCKET_0_INDEX + PORT_3A_INDEX] = =3D 1; +#if MAX_SOCKET > 2 + IioGlobalData->SetupData.SLOTPSP[SOCKET_3_INDEX + PORT_2A_INDEX] = =3D 4; + IioGlobalData->SetupData.SLOTPSP[SOCKET_3_INDEX + PORT_3A_INDEX] = =3D 2; +#endif // MAX_SOCKET > 2 + } else { // RISER_WINGED_OUT + IioGlobalData->SetupData.SLOTPSP[SOCKET_0_INDEX + PORT_3A_INDEX] = =3D 2; +#if MAX_SOCKET > 2 + IioGlobalData->SetupData.SLOTPSP[SOCKET_3_INDEX + PORT_2A_INDEX] = =3D 3; + IioGlobalData->SetupData.SLOTPSP[SOCKET_3_INDEX + PORT_3A_INDEX] = =3D 1; +#endif // MAX_SOCKET > 2 + if (RightRiser.Bits.HPConf =3D=3D RISER_HP_EN) { + // + // PCIe Hot Plug is supported on Winged-out riser only + // + EnableHotPlug_SKX(IioGlobalData, SOCKET_0_INDEX + PORT_3A_INDEX,= VPP_PORT_0, 0x40, REGULAR_PCIE_OWNERSHIP); +#if MAX_SOCKET > 2 + EnableHotPlug_SKX(IioGlobalData, SOCKET_3_INDEX + PORT_2A_INDEX,= VPP_PORT_1, 0x40, REGULAR_PCIE_OWNERSHIP); + EnableHotPlug_SKX(IioGlobalData, SOCKET_3_INDEX + PORT_3A_INDEX,= VPP_PORT_0, 0x40, REGULAR_PCIE_OWNERSHIP); +#endif // MAX_SOCKET > 2 + } // End of RISER_HP_EN + } // End of RISER_WINGED_IN + } // End of RISER_PRESENT + + if (LeftRiser.Bits.PresentSignal =3D=3D RISER_PRESENT) { + IioGlobalData->SetupData.SLOTIMP[SOCKET_1_INDEX + PORT_1A_INDEX] =3D= 1; + IioGlobalData->SetupData.SLOTIMP[SOCKET_1_INDEX + PORT_2A_INDEX] =3D= 1; + IioGlobalData->SetupData.SLOTIMP[SOCKET_2_INDEX + PORT_1A_INDEX] =3D= 1; + IioGlobalData->SetupData.SLOTIMP[SOCKET_2_INDEX + PORT_3A_INDEX] =3D= 1; + if (LeftRiser.Bits.WingConf =3D=3D RISER_WINGED_IN) { + IioGlobalData->SetupData.SLOTPSP[SOCKET_1_INDEX + PORT_1A_INDEX] = =3D 7; + IioGlobalData->SetupData.SLOTPSP[SOCKET_1_INDEX + PORT_2A_INDEX] = =3D 5; + IioGlobalData->SetupData.SLOTPSP[SOCKET_2_INDEX + PORT_1A_INDEX] = =3D 6; + IioGlobalData->SetupData.SLOTPSP[SOCKET_2_INDEX + PORT_3A_INDEX] = =3D 8; + } else { // RISER_WINGED_OUT + IioGlobalData->SetupData.SLOTPSP[SOCKET_1_INDEX + PORT_1A_INDEX] = =3D 5; + IioGlobalData->SetupData.SLOTPSP[SOCKET_1_INDEX + PORT_2A_INDEX] = =3D 7; + IioGlobalData->SetupData.SLOTPSP[SOCKET_2_INDEX + PORT_1A_INDEX] = =3D 8; + IioGlobalData->SetupData.SLOTPSP[SOCKET_2_INDEX + PORT_3A_INDEX] = =3D 6; + if (LeftRiser.Bits.HPConf =3D=3D RISER_HP_EN) { + // + // PCIe Hot Plug is supported on Winged-out riser only + // + EnableHotPlug_SKX(IioGlobalData, SOCKET_1_INDEX + PORT_1A_INDEX,= VPP_PORT_0, 0x42, REGULAR_PCIE_OWNERSHIP); + EnableHotPlug_SKX(IioGlobalData, SOCKET_1_INDEX + PORT_2A_INDEX,= VPP_PORT_1, 0x42, REGULAR_PCIE_OWNERSHIP); + EnableHotPlug_SKX(IioGlobalData, SOCKET_2_INDEX + PORT_1A_INDEX,= VPP_PORT_1, 0x42, REGULAR_PCIE_OWNERSHIP); + EnableHotPlug_SKX(IioGlobalData, SOCKET_2_INDEX + PORT_3A_INDEX,= VPP_PORT_0, 0x42, REGULAR_PCIE_OWNERSHIP); + } // End of RISER_HP_EN + } // End of RISER_WINGED_IN + } // End of RISER_PRESENT + } // End of FlagValue =3D=3D 1 + + /// Broadway overrides. + if (BroadwayTable !=3D NULL) { + GetBw5Id (IioGlobalData, Bw5id); + DEBUG ((EFI_D_INFO,"Broadway Config: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n"= , Bw5id[Bw5_Addr_0].Data, Bw5id[Bw5_Addr_1].Data, Bw5id[Bw5_Addr_2].Data, B= w5id[Bw5_Addr_3].Data)); + for (Index =3D 0; Index < 3; Index ++) { + // + // Check if BW5 is present before override IOUx Bifurcation + // + if (BroadwayTable->BroadwayAddress =3D=3D Bw5_Addr_Max) { + break; + } + if (Bw5id[BroadwayTable->BroadwayAddress].Bits.BifBits !=3D BW5_CARD= _NOT_PRESENT){ + if (AutoBifEnable[(BroadwayTable->Socket * Iio_IouMax) + BroadwayT= able->IouNumber] =3D=3D TRUE) { + switch (BroadwayTable->IouNumber) { + case Iio_Iou0: + IioGlobalData->SetupData.ConfigIOU[BroadwayTable->Socket][0]= =3D Bw5id[BroadwayTable->BroadwayAddress].Bits.BifBits; + DEBUG ((DEBUG_ERROR,"IioGlobalData->SetupData.ConfigIOU[%x][= 0] =3D %x\n",BroadwayTable->Socket, IioGlobalData->SetupData.ConfigIOU[Broa= dwayTable->Socket][0])); + break; + case Iio_Iou1: + IioGlobalData->SetupData.ConfigIOU[BroadwayTable->Socket][1]= =3D Bw5id[BroadwayTable->BroadwayAddress].Bits.BifBits; + DEBUG ((DEBUG_ERROR,"IioGlobalData->SetupData.ConfigIOU[%x][= 1] =3D %x\n",BroadwayTable->Socket, IioGlobalData->SetupData.ConfigIOU[Broa= dwayTable->Socket][1])); + break; + case Iio_Iou2: + IioGlobalData->SetupData.ConfigIOU[BroadwayTable->Socket][2]= =3D Bw5id[BroadwayTable->BroadwayAddress].Bits.BifBits; + DEBUG ((DEBUG_ERROR,"IioGlobalData->SetupData.ConfigIOU[%x][= 2] =3D %x\n",BroadwayTable->Socket,IioGlobalData->SetupData.ConfigIOU[Broad= wayTable->Socket][2])); + break; + default: + break; + } // BroadwayTable->IouNumber + } // AutoBifEnable =3D=3D TRUE + } // No BW5 present + BroadwayTable ++; + } // for Index + } // BroadwayTable !=3D NULL + + if (DynamicSiLibraryPpi->IsCpuAndRevision (CPU_SKX, REV_ALL) || + DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CLX, REV_ALL) || + DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CPX, REV_ALL) + ) { + PlatformUpdateIioConfig (IioGlobalData); + } +} + + +/** + Verify if VMD is enabled and override Slot configuration + based on the VMD settings + + @param IioGlobalData Pointer to Iio Globals. + @param Slot - Slot configuration settings + @param SlotEntries - Number of slot entries + + @retval None + +**/ +VOID +OverrideConfigSlots_SKX ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_DATA_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + UINT8 MaxPortNumberPerSocket; + UINT8 IioIndex; + UINT8 Stack; + UINT8 PortIndex; + + MaxPortNumberPerSocket =3D IioGlobalData->IioVar.IioOutData.MaxPciePortN= umberPerSocket[0]; + for (Index =3D0; Index < SlotEntries; Index ++) { + Port =3D Slot[Index].PortIndex; + // + // Check if Slot is capable of PcieSSD Solution and override the SLOT = Config values + // + if (Slot[Index].PcieSSDCapable) { + IioIndex =3D Port/MaxPortNumberPerSocket; + PortIndex =3D (Port - (MaxPortNumberPerSocket * IioIndex)); + Stack =3D IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][Port= Index]; + DEBUG ((DEBUG_INFO, "Stack =3D %x, Port =3D %x, PortIndex =3D %x\n",= Stack, Port, PortIndex)); + + // + // check if VMD will own Pcie Root Port + // + if (IioGlobalData->SetupData.VMDEnabled[IioIndex][Stack]) { + if (IioGlobalData->SetupData.VMDPortEnable[IioIndex][PortIndex]) { + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] =3D VMD= _OWNERSHIP; + } + } else { + + DEBUG ((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICEnabled[%x] = =3D %x\n", Stack, IioGlobalData->SetupData.PcieAICEnabled[(IioIndex * MAX_S= TACKS_PER_SOCKET) + Stack])); + // + // Check if Pcie AIC Card will be present on Pcie Root Port + // + if (IioGlobalData->SetupData.PcieAICEnabled[(IioIndex * MAX_STACKS= _PER_SOCKET) + Stack]) { + // + // Force to have this port enabled by default for hot-plug. + // + IioGlobalData->SetupData.IioPcieConfig.PciePortEnable[(IioIndex = * MaxPortNumberPerSocket) + Port] =3D ENABLE; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] =3D PCI= EAIC_OCL_OWNERSHIP; + DEBUG ((DEBUG_ERROR, "Port =3D %x, PciePortEnable =3D %x\n", Por= t, IioGlobalData->SetupData.IioPcieConfig.PciePortEnable[(IioIndex * MaxPor= tNumberPerSocket) + Port])); + } + } // No _VMD Ownership + + DEBUG ((DEBUG_INFO, "PciePortOwnerShip[%x] =3D %x\n",Port, IioGlobal= Data->IioVar.IioOutData.PciePortOwnership[Port])); + + // if PcieSSDSupport required do slot override settings accordingly + if ((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] !=3D R= EGULAR_PCIE_OWNERSHIP) && + (SlotImplemented_SKX(IioGlobalData, Port) =3D=3D TRUE)) { + IioGlobalData->SetupData.SLOTIMP[Port] =3D SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port] =3D 0x50 + Port; // Just p= rogram a value for PCIEACI_OCL/VMD + IioGlobalData->SetupData.SLOTEIP[Port] =3D DISABLE; + + if (Slot[Index].SlotPowerLimitScale !=3D PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] =3D Slot[Index].SlotPowe= rLimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] =3D Slot[Index].SlotPowe= rLimitValue; + } + DEBUG ((DEBUG_INFO,"Slot[Index].PcieSSDVppPort =3D %x\n", Slot[Ind= ex].PcieSSDVppPort)); + // Enable hot-plug if slot/port supports it + if (Slot[Index].PcieSSDVppPort !=3D VPP_PORT_MAX) { + DEBUG ((DEBUG_INFO, "IioGlobalData->SetupData.VMDHotPlugEnable[%d]= [%x] =3D %x\n", IioIndex, Stack, IioGlobalData->SetupData.VMDHotPlugEnable[= IioIndex][Stack])); + DEBUG ((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICHotPlugEnable= [%x] =3D %x\n",Stack,IioGlobalData->SetupData.PcieAICHotPlugEnable[(IioInde= x * MAX_STACKS_PER_SOCKET) + Stack])); + // Check if hot-plug is enabled for VMD or PCIeAIC case. + if (((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = =3D=3D VMD_OWNERSHIP) && + (IioGlobalData->SetupData.VMDHotPlugEnable[IioIndex][Stack]= )) || + ((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = =3D=3D PCIEAIC_OCL_OWNERSHIP) && + (IioGlobalData->SetupData.PcieAICHotPlugEnable[(IioIndex * = MAX_STACKS_PER_SOCKET) + Stack]))) { + EnableHotPlug_SKX(IioGlobalData, Port, Slot[Index].PcieSSDVppP= ort, Slot[Index].PcieSSDVppAddress, IioGlobalData->IioVar.IioOutData.PciePo= rtOwnership[Port]); + DEBUG((DEBUG_INFO,"Enable HotPlug Done\n")); + } + } + // + // Unhide the port in order to get configured and it will be hide = later for VMDLateSetup if MD own the Pcie Root Port + // + IioGlobalData->SetupData.PEXPHIDE[Port] =3D NOT_HIDE; + }// PcieSSDSupport + }// PcieSSDCapable + }// Per Slot +} + +VOID +SetBifurcations_SKX( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_DATA_ENTRY *BifurcationTable, + IN UINT8 BifurcationEntries, + IN BOOLEAN *AutoBifEnable +) +{ + UINT8 Socket; + UINT8 Iou; + UINT8 Index; + + for (Index =3D 0; Index < BifurcationEntries ; Index++) { + Socket =3D BifurcationTable[Index].Socket; + Iou =3D BifurcationTable[Index].IouNumber; + + if (AutoBifEnable[(Socket * Iio_IouMax) + Iou] =3D=3D TRUE) { + switch (Iou) { + case Iio_Iou0: + IioGlobalData->SetupData.ConfigIOU[Socket][0] =3D BifurcationTab= le[Index].Bifurcation; + break; + case Iio_Iou1: + IioGlobalData->SetupData.ConfigIOU[Socket][1] =3D BifurcationTab= le[Index].Bifurcation; + break; + case Iio_Iou2: + IioGlobalData->SetupData.ConfigIOU[Socket][2] =3D BifurcationTab= le[Index].Bifurcation; + break; + case Iio_Iou3: + IioGlobalData->SetupData.ConfigIOU[Socket][3] =3D BifurcationTab= le[Index].Bifurcation; + break; + case Iio_Iou4: + IioGlobalData->SetupData.ConfigIOU[Socket][4] =3D BifurcationTab= le[Index].Bifurcation; + break; + default: + DEBUG ((EFI_D_ERROR, "Invalid bifurcation table: Bad Iou (%d)", = Iou)); + ASSERT(Iou); + break; + } + } + } +} + + +/** + + SystemIioPortBifurcationInit - Program the UDS data structure with OEM I= IO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +SystemIioPortBifurcationInitCommon_SKX ( + UINT8 BoardId, + IIO_GLOBALS *IioGlobalData, + IIO_BIFURCATION_DATA_ENTRY **BifurcationTable, + UINT8 *BifurcationEntries, + IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable, + UINT8 *SlotEntries +) +{ + + UINT8 PortIndex;//, iio; + IIO_BIFURCATION_DATA_ENTRY **BifurcationTableTemp; + IIO_SLOT_CONFIG_DATA_ENTRY **SlotTableTemp; + UINT8 SkuPersonalityType =3D 0; + UINT8 MaxPortNumberPerSocket; + + /// This function outline: + //// 1 Based on platform apply the default bifurcation and slot configur= ation. + //// 2 Apply dynamic overrides based on GPIO and other configurations. + //// 3 Hide unused ports due bifurcation. + + MaxPortNumberPerSocket =3D IioGlobalData->IioVar.IioOutData.MaxPciePortN= umberPerSocket[0]; + for (PortIndex =3D 0; PortIndex < MAX_SOCKET*MaxPortNumberPerSocket; Por= tIndex++) { + IioGlobalData->SetupData.PEXPHIDE[PortIndex] =3D 0; + IioGlobalData->SetupData.HidePEXPMenu[PortIndex] =3D 0; + } + + *BifurcationEntries =3D 0; + *SlotEntries =3D 0; + + BifurcationTableTemp =3D (IIO_BIFURCATION_DATA_ENTRY **) BifurcationTabl= e; + SlotTableTemp =3D (IIO_SLOT_CONFIG_DATA_ENTRY **) SlotTable; + + if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] =3D=3D TYPE_FPGA) = &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] =3D=3D TYPE_FPGA))= { + SkuPersonalityType =3D 1; + } else if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] =3D=3D TYPE= _FPGA) &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] !=3D TYPE_FPGA)) { + SkuPersonalityType =3D 2; + } else if ((IioGlobalData->IioVar.IioVData.SkuPersonality[0] !=3D TYPE_F= PGA) &&\ + (IioGlobalData->IioVar.IioVData.SkuPersonality[1] =3D=3D TYPE_FPGA))= { + SkuPersonalityType =3D 3; + } else { + SkuPersonalityType =3D 0; + } + + InternalPlatformIioConfigInit2 (SkuPersonalityType, BifurcationTableTemp= , BifurcationEntries, SlotTableTemp, SlotEntries); + + BifurcationTable =3D (IIO_BIFURCATION_DATA_ENTRY **) BifurcationTableTem= p; + SlotTable =3D (IIO_SLOT_CONFIG_DATA_ENTRY **) SlotTableTemp; + +} + + +/** + This function prepare the data for silicon initialization based on + bifuraction and slots table + + This function is for tables in version PLATFORM_IIO_CONFIG_UPDATE_VERSIO= N =3D 1 + */ +VOID +IioPortBifurcationInitVer1 ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + UINT8 IioIndex; + IIO_BIFURCATION_DATA_ENTRY *BifurcationTable =3D NULL; + UINT8 BifurcationEntries; + IIO_SLOT_CONFIG_DATA_ENTRY *SlotTable =3D NULL; + UINT8 SlotEntries; + BOOLEAN AutoBifEnable[MaxIIO * Iio_IouMax]; + UINT8 BoardId; + + BoardId =3D SystemBoardIdValue(); + + SetMem ((VOID *)AutoBifEnable, MaxIIO * Iio_IouMax, FALSE); + + for (IioIndex =3D Iio_Socket0; IioIndex < MaxIIO; IioIndex++) { + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][0] =3D=3D IIO_BIFURCA= TE_AUTO) { + AutoBifEnable[(IioIndex * Iio_IouMax) + Iio_Iou0] =3D TRUE; + } + + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][1] =3D=3D IIO_BIFURCA= TE_AUTO) { + AutoBifEnable[(IioIndex * Iio_IouMax) + Iio_Iou1] =3D TRUE; + } + + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][2] =3D=3D IIO_BIFURCA= TE_AUTO) { + AutoBifEnable[(IioIndex * Iio_IouMax) + Iio_Iou2] =3D TRUE; + } + + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][3] =3D=3D IIO_BIFURCA= TE_AUTO) { + AutoBifEnable[(IioIndex * Iio_IouMax) + Iio_Iou3] =3D TRUE; + } + + if (IioGlobalData->SetupData.ConfigIOU[IioIndex][4] =3D=3D IIO_BIFURCA= TE_AUTO) { + AutoBifEnable[(IioIndex * Iio_IouMax) + Iio_Iou4] =3D TRUE; + } + } + + // This function outline: + // 1. Based on platform apply the default bifurcation and slot configura= tion. + // 2. Apply dynamic overrides based on GPIO and other configurations. + // 3. Hide unused ports due bifurcation. + + // Set the default bifurcations for this platform. + SystemIioPortBifurcationInitCommon_SKX (BoardId, IioGlobalData, &Bifurca= tionTable, &BifurcationEntries, &SlotTable, &SlotEntries); + SetBifurcations_SKX (IioGlobalData, BifurcationTable, BifurcationEntries= , AutoBifEnable); + ConfigSlots_SKX (IioGlobalData, SlotTable, SlotEntries); + if (BoardId <=3D TypePlatformMax) { + OverrideDefaultBifSlots_SKX (IioGlobalData, BoardId, AutoBifEnable); + } + OverrideConfigSlots_SKX (IioGlobalData, SlotTable, SlotEntries); + + + // All overrides have been applied now. + // Hide root ports whose lanes are assigned preceding ports. + for (IioIndex =3D Iio_Socket0; IioIndex < MaxIIO; IioIndex++) { + if (IioGlobalData->IioVar.IioVData.SocketPresent[IioIndex]) { + SystemHideIioPortsCommon_SKX (IioGlobalData, IioIndex); + } + } +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchH= sioPtssTables.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei= /PchHsioPtssTables.h new file mode 100644 index 0000000000..2c5d3da968 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchHsioPtss= Tables.h @@ -0,0 +1,51 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HSIO_PTSSTABLES_H_ +#define _PCH_HSIO_PTSSTABLES_H_ + +#include +#include +#include + +/// +/// SATA PTSS Topology Types +/// +typedef enum { + PchSataTopoUnknown =3D 0x00, + PchSataTopoIsata, + PchSataTopoDirectConnect, + PchSataTopoFlex, + PchSataTopoM2 +} PCH_SATA_TOPOLOGY; + +/// +/// PCIe PTSS Topology Types +/// +typedef enum { + PchPcieTopoUnknown =3D 0x00, + PchPcieTopox1, + PchPcieTopox4, + PchPcieTopoSataE, + PchPcieTopoM2 +} PCH_PCIE_TOPOLOGY; + +/// +/// DMI PTSS Topology Types +/// +typedef enum { + PchDmiTopoUnknown =3D 0x00, +} PCH_DMI_TOPOLOGY; + +typedef struct { + PCH_SBI_PTSS_HSIO_TABLE PtssTable; + UINT16 Topology; + UINT16 BoardId; +} HSIO_PTSS_TABLES; + +#endif // _PCH_HSIO_PTSSTABLES_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesBx.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Commo= n/Pei/PchLbgHsioPtssTablesBx.c new file mode 100644 index 0000000000..173ca7276e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesBx.c @@ -0,0 +1,44 @@ +/** @file + LbgPchH Bx HSIO PTSS C File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchLbgHsioPtssTablesBx.h" +#include + +HSIO_PTSS_TABLES PchLbgHsioPtss_Bx[] =3D { + {{0xA9, 12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 18, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 19, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 20, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 21, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, +}; + +UINT32 PchLbgHsioPtss_Bx_Size =3D sizeof (PchLbgHsioPtss_Bx) / sizeof (Pch= LbgHsioPtss_Bx[0]); + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesBx.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Commo= n/Pei/PchLbgHsioPtssTablesBx.h new file mode 100644 index 0000000000..b63b198d36 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesBx.h @@ -0,0 +1,18 @@ +/** @file + LbgPchH Bx HSIO PTSS Header File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LBG_HSIO_PTSSTABLES_BX_H_ +#define _PCH_LBG_HSIO_PTSSTABLES_BX_H_ + +#include "PchHsioPtssTables.h" + +extern HSIO_PTSS_TABLES PchLbgHsioPtss_Bx[69]; +extern UINT32 PchLbgHsioPtss_Bx_Size; + +#endif // _PCH_LBG_HSIO_PTSSTABLES_BX_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesBx_Ext.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/C= ommon/Pei/PchLbgHsioPtssTablesBx_Ext.c new file mode 100644 index 0000000000..65c777a4b7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesBx_Ext.c @@ -0,0 +1,44 @@ +/** @file + LbgPchH Bx HSIO PTSS C File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchLbgHsioPtssTablesBx_Ext.h" +#include + +HSIO_PTSS_TABLES PchLbgHsioPtss_Bx_Ext[] =3D { + {{0xA9, 12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 18, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 19, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 20, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 21, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, +}; + +UINT32 PchLbgHsioPtss_Bx_Size_Ext =3D sizeof (PchLbgHsioPtss_Bx_Ext) / siz= eof (PchLbgHsioPtss_Bx_Ext[0]); + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesBx_Ext.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/C= ommon/Pei/PchLbgHsioPtssTablesBx_Ext.h new file mode 100644 index 0000000000..dea47126a2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesBx_Ext.h @@ -0,0 +1,20 @@ +/** @file + LbgPchH Bx HSIO PTSS Header File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LBG_HSIO_PTSSTABLES_BX_H_EXT_ +#define _PCH_LBG_HSIO_PTSSTABLES_BX_H_EXT_ + + + +#include "PchHsioPtssTables.h" + +extern HSIO_PTSS_TABLES PchLbgHsioPtss_Bx_Ext[69]; +extern UINT32 PchLbgHsioPtss_Bx_Size_Ext; + +#endif // _PCH_LBG_HSIO_PTSSTABLES_BX_H_EXT_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesSx.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Commo= n/Pei/PchLbgHsioPtssTablesSx.c new file mode 100644 index 0000000000..e44807d640 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesSx.c @@ -0,0 +1,27 @@ +/** @file + LbgPchH Sx HSIO PTSS C File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchLbgHsioPtssTablesSx.h" +#include + +HSIO_PTSS_TABLES PchLbgHsioPtss_Sx[] =3D { + {{0xA9, 12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 18, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 19, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 20, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 21, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, +}; + +UINT32 PchLbgHsioPtss_Sx_Size =3D sizeof (PchLbgHsioPtss_Sx) / sizeof (Pch= LbgHsioPtss_Sx[0]); + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesSx.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Commo= n/Pei/PchLbgHsioPtssTablesSx.h new file mode 100644 index 0000000000..52e6a1f7ac --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesSx.h @@ -0,0 +1,21 @@ +/** @file + LbgPchH Sx HSIO PTSS Header File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LBG_HSIO_PTSSTABLES_SX_H_ +#define _PCH_LBG_HSIO_PTSSTABLES_SX_H_ + + + +#include "PchHsioPtssTables.h" + + +extern HSIO_PTSS_TABLES PchLbgHsioPtss_Sx[69]; +extern UINT32 PchLbgHsioPtss_Sx_Size; + +#endif // _PCH_LBG_HSIO_PTSSTABLES_SX_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesSx_Ext.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/C= ommon/Pei/PchLbgHsioPtssTablesSx_Ext.c new file mode 100644 index 0000000000..4f4dd4496e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesSx_Ext.c @@ -0,0 +1,44 @@ +/** @file + LbgPchH Sx HSIO PTSS C File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchLbgHsioPtssTablesSx_Ext.h" +#include + +HSIO_PTSS_TABLES PchLbgHsioPtss_Sx_Ext[] =3D { + {{0xA9, 12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 18, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 19, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 20, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 21, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x02000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPRP}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 0, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 1, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 2, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x48000000, (UINT32) ~= 0xF8000000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xEB, 3, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~= 0x1F0000}, PchDmiTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x= 3F000000}, PchSataTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 22, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 23, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 24, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x11c, 0x28000000, (UINT32) = ~0xF8000000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, + {{0xA9, 25, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) = ~0x1F0000}, PchPcieTopoUnknown, TypeNeonCityEPECB}, +}; + +UINT32 PchLbgHsioPtss_Sx_Size_Ext =3D sizeof (PchLbgHsioPtss_Sx_Ext) / siz= eof (PchLbgHsioPtss_Sx_Ext[0]); + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchL= bgHsioPtssTablesSx_Ext.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/C= ommon/Pei/PchLbgHsioPtssTablesSx_Ext.h new file mode 100644 index 0000000000..a80d530b27 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PchLbgHsioP= tssTablesSx_Ext.h @@ -0,0 +1,21 @@ +/** @file + LbgPchH Sx HSIO PTSS Header File + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LBG_HSIO_PTSSTABLES_SX_H_EXT_ +#define _PCH_LBG_HSIO_PTSSTABLES_SX_H_EXT_ + + + +#include "PchHsioPtssTables.h" + + +extern HSIO_PTSS_TABLES PchLbgHsioPtss_Sx_Ext[69]; +extern UINT32 PchLbgHsioPtss_Sx_Size_Ext; + +#endif // _PCH_LBG_HSIO_PTSSTABLES_SX_H_EXT_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiC= ommonBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common= /Pei/PeiCommonBoardInitLib.c new file mode 100644 index 0000000000..d65bc28b1d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiCommonBo= ardInitLib.c @@ -0,0 +1,75 @@ +/** @file + Common Board Init Lib. + + @copyright + Copyright 2017 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiCommonBoardInitLib.h" + +EFI_STATUS +EFIAPI +CommonPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallClockgenData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallGpioPlatformData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallBoardInfoData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallPlatformClocksConfigData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallPlatformHsioPtssTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D InstallIioPortBifurcationInitData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiC= ommonBoardInitLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common= /Pei/PeiCommonBoardInitLib.h new file mode 100644 index 0000000000..91e68d52f6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiCommonBo= ardInitLib.h @@ -0,0 +1,55 @@ +/** @file + Common Board Init. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_COMMON_BOARD_PEI_H_ +#define _PEI_COMMON_BOARD_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLOCK_GENERATOR_SETTINGS_CK505 {0x00, 0xF3, 0x0F, 0xFE, 0x98= , 0x02, 0x08, 0x26, 0x7C, 0xE7, 0x0F, 0xFE, 0x08} + +EFI_STATUS +InstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +InstallGpioPlatformData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +InstallBoardInfoData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +InstallPlatformClocksConfigData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +InstallPlatformHsioPtssTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +InstallIioPortBifurcationInitData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +#endif // _PEI_COMMON_BOARD_PEI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiC= ommonBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Comm= on/Pei/PeiCommonBoardInitLib.inf new file mode 100644 index 0000000000..a0e2f6056c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Common/Pei/PeiCommonBo= ardInitLib.inf @@ -0,0 +1,76 @@ +## @file +# Board Init for multi-boards support in PEI phase. +# +# @copyright +# Copyright 2015 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CommonPeiBoardInitLib + FILE_GUID =3D 46BF553E-2C76-41C6-A0E8-E242F46BBD5F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D CommonPeiBoardInitLibConstructor + + +[Sources] + PeiCommonBoardInitLib.c + Clockgen.c + GpioPlatformConfig.c + BoardInfo.c + ClocksConfig.c + HsioPtssTableConfig.c + IioPortBifurcation.c + IioPortBifurcationVer1.c + PchLbgHsioPtssTablesBx.c + PchLbgHsioPtssTablesBx_Ext.c + PchLbgHsioPtssTablesSx.c + PchLbgHsioPtssTablesSx_Ext.c + IioBifurcationSlotTable.h + PchHsioPtssTables.h + PchLbgHsioPtssTablesBx.h + PchLbgHsioPtssTablesBx_Ext.h + PchLbgHsioPtssTablesSx.h + PchLbgHsioPtssTablesSx_Ext.h + PeiCommonBoardInitLib.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + PeiServicesLib + PeimEntryPoint + DebugLib + PlatformClocksLib + HobLib + PciLib + IoLib + PeiServicesTablePointerLib + +[Guids] + gPlatformKtiEparamUpdateDataGuid + gEfiPlatformInfoGuid + +[Ppis] + gPchPlatformPolicyPpiGuid + gUbaConfigDatabasePpiGuid + gEfiPeiSmbus2PpiGuid + gEfiPeiStallPpiGuid + gPchHsioPtssTablePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Pcd] + gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c new file mode 100644 index 0000000000..5d8862ea6e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,107 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateCooperCityRPIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeCooperCityRPIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateCooperCityRPIioConfig, + IioSlotTable, + sizeof(IioSlotTable) + +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeCooperCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h new file mode 100644 index 0000000000..9e6a7c9b3a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,161 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =3D +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket2, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket2, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket2, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket2, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket2, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket3, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket3, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket3, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket3, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket3, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +#if MAX_SOCKET > 4 + { Iio_Socket4, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket4, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket4, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket4, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket4, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket5, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket5, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket5, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket5, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket5, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket6, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket6, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket6, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket6, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket6, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket7, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket7, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket7, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket7, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket7, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +#endif +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | Hot = | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD |= Hidden + // Index | | lock | Scale | Value | Plug = | Port | Addr | Cap | VppPort | VppAddr | + /// Socket 0: Iuo2 Connected to SLOT 9 or SSDs: read values of QAT and r= iser. + /// Iuo0 Uplink + /// Iuo3 Connected to SLOT 1 or 2, and might be HP. Read value= s of QAT and riser. + { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C ,= HIDE }, //Oculink + { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C ,= HIDE }, //Oculink + { PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4E ,= HIDE }, //Oculink + { PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4E ,= HIDE }, //Oculink + { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, // Uplink + { PORT_3A_INDEX, 1 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + /// Socket 1: DMI no connected on all boards. + /// Iuo2 Slot 7 or 5 based on riser information. Might be HP. + /// Iuo0 Slot 5 or 7 based on riser information. Might be HP. + /// Iuo1, Not connected for RP. + { SOCKET_1_INDEX + + PORT_0_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, + { SOCKET_1_INDEX + + PORT_1A_INDEX, 5 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, + /// Socket 2: DMI Port, not connected on RP + /// Iuo2 Slot 6 or 8 based on riser information. Might be HP. + /// Iuo1 Slot 6 or 8 based on riser information. Might be HP. + /// Iuo0, Not connected for RP. + { SOCKET_2_INDEX + + PORT_0_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, + { SOCKET_2_INDEX + + PORT_1A_INDEX, 6 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_2_INDEX + + PORT_3A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_2_INDEX + + PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, + /// Socket 3: DMI not connected. + /// Iuo2 Not Connected for RP. + /// Iuo0 Slot 4 or 3 based on riser information. Might be HP. + /// Iuo1 Slot 4 or 3 based on riser information. Might be HP. + { SOCKET_3_INDEX + + PORT_0_INDEX , NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, + { SOCKET_3_INDEX + + PORT_2A_INDEX, 3 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_3_INDEX + + PORT_3A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE }, + { SOCKET_3_INDEX + + PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= HIDE }, +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoard= Pkg/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf new file mode 100644 index 0000000000..3f7268b527 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,48 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioCfgUpdateDxeCooperCityRP + FILE_GUID =3D 073018E2-4A0A-3D61-8EA7-B08321C9364B + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioCfgUpdateEntry + +[Sources] + IioCfgUpdateDxe.h + IioCfgUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeCooperCityRPProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoa= rdPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c new file mode 100644 index 0000000000..bbc90ede3e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,108 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeCooperCityRPIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as x4x4 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8x4x4; + return IOU0Data; +} + +UINT8 +GetTypeCooperCityRPIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +PLATFORM_SLOT_UPDATE_TABLE TypeCooperCityRPSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + NULL, + GetTypeCooperCityRPIOU0Setting, + 1 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeCooperCityRPSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + NULL, + GetTypeCooperCityRPIOU0Setting, + 1, + GetTypeCooperCityRPIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeCooperCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeCooperCityRPSlotTable, + sizeof(TypeCooperCityRPSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataGuid2, + &TypeCooperCityRPSlotTable2, + sizeof(TypeCooperCityRPSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoa= rdPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h new file mode 100644 index 0000000000..9be882b09e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenB= oardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDx= e.inf new file mode 100644 index 0000000000..77ba1697eb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,48 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SlotDataUpdateDxeCooperCityRP + FILE_GUID =3D 3C26C91F-4CEB-E798-59EC-05B15E9C5919 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SlotDataUpdateEntry + +[Sources] + SlotDataUpdateDxe.h + SlotDataUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeCooperCityRPProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/= Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..fa5c21e4f4 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,124 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeCooperCityRPUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPinSkip, //Port00: BMC + UsbOverCurrentPinSkip, //Port01: BMC + UsbOverCurrentPin0, //Port02: Rear Panel + UsbOverCurrentPin1, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPinSkip, //Port05: NC + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPin4, //Port07: Type A intern= al + UsbOverCurrentPinSkip, //Port08: NC + UsbOverCurrentPinSkip, //Port09: NC + UsbOverCurrentPin6, //Port10: Front Panel + UsbOverCurrentPinSkip, //Port11: NC + UsbOverCurrentPin6, //Port12: Front Panel + UsbOverCurrentPin4 //Port13: NC + }; + +USB_OVERCURRENT_PIN TypeCooperCityRPUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin6, //Port01: Front Panel + UsbOverCurrentPin6, //Port02: Front Panel + UsbOverCurrentPin0, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPin1, //Port05: Rear Panel + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeCooperCityRPUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {7, 0, 2, 1}, // PP0 + {7, 0, 2, 1}, // PP1 + {7, 0, 2, 1}, // PP2 + {7, 0, 2, 1}, // PP3 + {7, 0, 2, 1}, // PP4 + {7, 0, 2, 1}, // PP5 + {7, 0, 2, 1}, // PP6 + {7, 0, 2, 1}, // PP7 + {7, 0, 2, 1}, // PP8 + {7, 0, 2, 1}, // PP9 + {7, 0, 2, 1}, // PP10 + {7, 0, 2, 1}, // PP11 + {7, 0, 2, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeCooperCityRPPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeCooperCityRPUsb20OverCurrentMappin= gs[0]; + *Usb30OverCurrentMappings =3D &TypeCooperCityRPUsb30OverCurrentMappin= gs[0]; + *Usb20AfeParams =3D TypeCooperCityRPUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeCooperCityRPUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeCooperCityRPPlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeCooperCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeCooperCityRPUsbOcUpdate, + sizeof(TypeCooperCityRPUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/= Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..4f9341b2ba --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + + +#endif //_USBOC_UPDATE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf new file mode 100644 index 0000000000..87d5c3d711 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,44 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UsbOcUpdateDxeCooperCityRP + FILE_GUID =3D 001EE0B2-4F5B-59A9-6CDB-F893FBC4D029 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeCooperCityRPProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Type= CooperCityRP/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..98ed9275e5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/A= cpiTablePcds.c @@ -0,0 +1,51 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include + +EFI_STATUS +TypeCooperCityRPPlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiNameCpx[] =3D "CPXXEPRP"; // Identifies DSDT on CP= X builds + CHAR8 OemTableIdXhci[] =3D "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + //# + //#ACPI items + //# + Size =3D AsciiStrSize (AcpiNameCpx); + Status =3D PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiNameCpx); + DEBUG ((DEBUG_INFO, "PlatformUpdateAcpiTablePcds TypeCooperCityRP CPX\n"= )); + ASSERT_EFI_ERROR (Status); + + Size =3D AsciiStrSize (OemTableIdXhci); + Status =3D PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/GpioTable.c new file mode 100644 index 0000000000..906c2efe28 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/G= pioTable.c @@ -0,0 +1,297 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +#include +#include +#include +#include + +static GPIO_INIT_CONFIG mGpioTableCooperCityRP[] =3D + { + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N + {GPIO_SKL_H_GPP_A13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_15_FM_SUSACK_N + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS +// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23 + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N +// GPIO_SKL_H_GPP_B3 - Not Owned by BIOS +// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7 + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N +// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, G= pioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N +// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS +// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP +// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS +// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N +// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS +// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},/= /GPP_C_10_FM_PCH_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_19_RST_SMB_HOST_PCH_MUX_N +// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9 + {GPIO_SKL_H_GPP_D10, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11 + {GPIO_SKL_H_GPP_D12, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 + {GPIO_SKL_H_GPP_D13, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL + {GPIO_SKL_H_GPP_D14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21 + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22 + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23 + {GPIO_SKL_H_GPP_E0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone,= GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//FM_CPU_ONOFF_INT_N - Used for the CPU online/offline fe= ature. + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N + {GPIO_SKL_H_GPP_F0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N + {GPIO_SKL_H_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0 + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N +// GPIO_SKL_H_GPP_G20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N + {GPIO_SKL_H_GPP_G22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23 + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 +// GPIO_SKL_H_GPP_H5 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 + {GPIO_SKL_H_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 +// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS +// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE +// GPIO_SKL_H_GPP_H13 - Not Owned by BIOS +// GPIO_SKL_H_GPP_H14 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N +// GPIO_SKL_H_GPP_H16 - Not Owned by BIOS +// GPIO_SKL_H_GPP_H17 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_H20, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_H22, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23 + {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//RST_DO_RST_IN_NODE + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//RST_DO_RST_OUT_NODE + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//RST_RESET_DONE_NODE + {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 +// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS +// GPIO_SKL_H_GPD0 - Not Owned by BIOS + {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_1_PU_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_6_FM_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_9_TP_GPD_9_SLP + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2 + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3 + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4 + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5 + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6 + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7 + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8 + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9 + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10 + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11 + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12 + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13 + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14 + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15 + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17 + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19 + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21 + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23 + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK + }; + + +EFI_STATUS +TypeCooperCityRPInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTableCooperCityRP, + sizeof(mGpioTableCooperCityRP) + ); + Status =3D PcdSet32S(PcdOemSku_GPIO_TABLE_SIZE,sizeof(mGpioTableCooperCi= tyRP)); + ASSERT_EFI_ERROR(Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeC= ooperCityRP/Pei/IioBifurInit.c new file mode 100644 index 0000000000..06245aebbe --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/I= ioBifurInit.c @@ -0,0 +1,393 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + + + +// +// config file : Cooper_City_PCIe_Slot_Config.xlsx +// config sheet : Whitley_SKX_PrePO_IntA +// +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =3D +{ + + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket2, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + + { Iio_Socket3, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket3, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket3, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket3, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + +#if MAX_SOCKET > 4 + { Iio_Socket4, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket4, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket4, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket4, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + + { Iio_Socket5, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket5, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket5, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket5, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket6, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket6, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket6, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket6, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + + { Iio_Socket7, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket7, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket7, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket7, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, +#endif // MAX_SOCKET > 4 +}; + + +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] =3D { + // Port Index | Slot |Interlock |power |Power |Hotpl= ug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |= Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard |ExtnCard |Ex= tnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard= Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap = | | |Cap |Port |Address |= |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SM= Bus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port= |Vpp Address | | + + {SOCKET_0_INDEX + + PORT_1A_INDEX, 2 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4A_INDEX, 7 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + + {SOCKET_1_INDEX + + PORT_1A_INDEX, 8 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x0 }, + {SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x0 }, + {SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x0 }, + {SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x0 }, + {SOCKET_1_INDEX + + PORT_2A_INDEX, 4 , DISABLE , 0 , 200 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + {SOCKET_1_INDEX + + PORT_4A_INDEX, 9 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_2_INDEX + + PORT_1A_INDEX, 2 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_2A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_2_INDEX + + PORT_4A_INDEX, 7 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_2_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_2_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_2_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + + {SOCKET_3_INDEX + + PORT_1A_INDEX, 8 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x0 }, + {SOCKET_3_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x0 }, + {SOCKET_3_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x0 }, + {SOCKET_3_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x0 }, + {SOCKET_3_INDEX + + PORT_2A_INDEX, 4 , DISABLE , 0 , 200 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_3_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_3_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_3_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + {SOCKET_3_INDEX + + PORT_4A_INDEX, 9 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_3_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_3_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_3_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + +#if MAX_SOCKET > 4 + {SOCKET_4_INDEX + + PORT_1A_INDEX, 2 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_2A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_4_INDEX + + PORT_4A_INDEX, 7 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_4_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_4_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_4_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + + {SOCKET_5_INDEX + + PORT_1A_INDEX, 8 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x0 }, + {SOCKET_5_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x0 }, + {SOCKET_5_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x0 }, + {SOCKET_5_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x0 }, + {SOCKET_5_INDEX + + PORT_2A_INDEX, 4 , DISABLE , 0 , 200 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_5_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_5_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_5_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + {SOCKET_5_INDEX + + PORT_4A_INDEX, 9 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_5_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_5_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_5_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_6_INDEX + + PORT_1A_INDEX, 2 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_2A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_6_INDEX + + PORT_4A_INDEX, 7 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_6_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_6_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_6_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + + {SOCKET_7_INDEX + + PORT_1A_INDEX, 8 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x0 }, + {SOCKET_7_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x0 }, + {SOCKET_7_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x0 }, + {SOCKET_7_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x0 }, + {SOCKET_7_INDEX + + PORT_2A_INDEX, 4 , DISABLE , 0 , 200 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x0 }, + {SOCKET_7_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x0 }, + {SOCKET_7_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x0 }, + {SOCKET_7_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , DISABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x0 }, + {SOCKET_7_INDEX + + PORT_4A_INDEX, 9 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_7_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_7_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_7_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, +#endif // MAX_SOCKET > 4 +}; + + +EFI_STATUS +UpdateCooperCityRPIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeCooperCityRPIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateCooperCityRPIioConfig, + IioSlotTable, + sizeof(IioSlotTable) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeCooperCityRPIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + &TypeCooperCityRPIioConfigTable, + sizeof(TypeCooperCityRPIioConfigTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/KtiEparam.c new file mode 100644 index 0000000000..19f9720a3b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/K= tiEparam.c @@ -0,0 +1,241 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO CooperCityRP2SAllLanesEparamTable[] =3D { + // + //SocketID, Freq, Link, TXEQ, CTLEPEAK + // + + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2C33383F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D37353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2D37353F, ADAPTIVE_CTLE}, // temporary data + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2D37353F, ADAPTIVE_CTLE}, // temporary data + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2C35363F, ADAPTIVE_CTLE}, // temporary data + + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2C33383F, ADAPTIVE_CTLE}, // temporary data + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2B35353F, ADAPTIVE_CTLE}, // temporary data + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D35373F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2D35373F, ADAPTIVE_CTLE}, // temporary data + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A2F3A3F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2C35363F, ADAPTIVE_CTLE} +}; + +ALL_LANES_EPARAM_LINK_INFO CooperCityRP4SAllLanesEparamTable[] =3D { + // + //SocketID, Freq, Link, TXEQ, CTLEPEAK + // + + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A30393F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D37353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2A34353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2D35373F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2C34373F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2C32393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 2 + // + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2B31393F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D36363F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B34363F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 3 + // + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A31383F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2C36353F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A2F3A3F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE} +}; + +ALL_LANES_EPARAM_LINK_INFO CooperCityRP8SAllLanesEparamTable[] =3D { + // + //SocketID, Freq, Link, TXEQ, CTLEPEAK + // + + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A30393F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D37353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2A34353F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2D35373F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2C34373F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2C32393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 2 + // + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2B31393F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D36363F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B34363F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 3 + // + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A31383F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2C36353F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A2F3A3F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 4 + // + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A30393F, ADAPTIVE_CTLE}, + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D37353F, ADAPTIVE_CTLE}, + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2A34353F, ADAPTIVE_CTLE}, + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2B33373F, ADAPTIVE_CTLE}, + {0x4, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 5 + // + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2D35373F, ADAPTIVE_CTLE}, + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A33363F, ADAPTIVE_CTLE}, + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2C34373F, ADAPTIVE_CTLE}, + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2C32393F, ADAPTIVE_CTLE}, + {0x5, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 6 + // + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2B31393F, ADAPTIVE_CTLE}, + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2D36363F, ADAPTIVE_CTLE}, + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B34363F, ADAPTIVE_CTLE}, + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x6, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE}, + + // + // Socket 7 + // + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), = 0x2A31383F, ADAPTIVE_CTLE}, + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), = 0x2C36353F, ADAPTIVE_CTLE}, + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), = 0x2A32373F, ADAPTIVE_CTLE}, + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), = 0x2B35353F, ADAPTIVE_CTLE}, + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), = 0x2A2F3A3F, ADAPTIVE_CTLE}, + {0x7, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), = 0x2A33363F, ADAPTIVE_CTLE} +}; + +//PER_LANE_EPARAM_LINK_INFO KtiCooperCityRPPerLaneEparamTable[] =3D { 0 }; +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeCooperCityRP2SKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + CooperCityRP2SAllLanesEparamTable, + sizeof (CooperCityRP2SAllLanesEparamTable), + NULL, + 0 +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeCooperCityRP4SKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + CooperCityRP4SAllLanesEparamTable, + sizeof (CooperCityRP4SAllLanesEparamTable), + NULL, + 0 +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeCooperCityRP8SKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + CooperCityRP8SAllLanesEparamTable, + sizeof (CooperCityRP8SAllLanesEparamTable), + NULL, + 0 +}; + + +EFI_STATUS +TypeCooperCityRPInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi, + IN UINT8 PlatformCapabilities + ) +{ + EFI_STATUS Status; + PLATFORM_KTI_EPARAM_UPDATE_TABLE *KtiEparamTable; + UINTN KtiEparamTableSize; + + switch (PlatformCapabilities) { + case PLATFORM_CAPABILITY_2_SOCKET: + KtiEparamTable =3D &TypeCooperCityRP2SKtiEparamUpdate; + KtiEparamTableSize =3D sizeof (TypeCooperCityRP2SKtiEparamUpdate); + break; + + case PLATFORM_CAPABILITY_4_SOCKET: + KtiEparamTable =3D &TypeCooperCityRP4SKtiEparamUpdate; + KtiEparamTableSize =3D sizeof (TypeCooperCityRP4SKtiEparamUpdate); + break; + + case PLATFORM_CAPABILITY_8_SOCKET: + default: + KtiEparamTable =3D &TypeCooperCityRP8SKtiEparamUpdate; + KtiEparamTableSize =3D sizeof (TypeCooperCityRP8SKtiEparamUpdate); + break; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + KtiEparamTable, + KtiEparamTableSize + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooper= CityRP/Pei/PcdData.c new file mode 100644 index 0000000000..27c5a36944 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/P= cdData.c @@ -0,0 +1,259 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_SKL_H_GPP_B20 0x01010014 + +VOID TypeCooperCityRPPlatformUpdateVrIdAddress (VOID); + +/** + Update CooperCity VR ID SVID Information + + retval N/A +**/ +VOID +TypeCooperCityRPPlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (MEM_SVID_MAP); + MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D NULL= \n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14,= and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs = (VR ID's 0x10 and 0x12). + */ + + MemSvidMap->Socket[0].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeCooperCityRPPlatformPcdUpdateCallback ( + VOID + ) +{ + CHAR8 FamilyName[] =3D "WildcatPass"; + + CHAR8 BoardName[] =3D "S2600WT "; + + UINTN Size; + UINT32 Data32; + CHAR16 PlatformName[] =3D L"TypeCooperCityRP"; + UINTN PlatformNameSize =3D 0; + UINTN PlatformFeatureFlag =3D 0; + UINT8 SKUType =3D 0; + UINT8 SKUTypeSockets =3D 0; + + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status =3D PcdSet16S (PcdOemSkuBoardID , TypeCooper= CityRP); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet16S (PcdOemSkuBoardFamily , 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + GetPlatformCapabilitiesInfo(&SKUType, DynamicSiLibraryPpi); + DEBUG ((DEBUG_INFO, " PcdOemSkuBoardSocketCount sku type %d\n", SKUType)= ); + if (SKUType =3D=3D PLATFORM_CAPABILITY_2_SOCKET) { + SKUTypeSockets =3D 2; + } else { + SKUTypeSockets =3D (SKUType =3D=3D PLATFORM_CAPABILITY_4_SOCKET) ? 4: = 8; + } + //# Number of Sockets on Board. + Status =3D PcdSet32S (PcdOemSkuBoardSocketCount , SKUTypeSoc= kets); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status =3D PcdSet32S (PcdOemSkuMaxChannel , 6); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status =3D PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size =3D AsciiStrSize (FamilyName); + Status =3D PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyNa= me); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size =3D AsciiStrSize (BoardName); + Status =3D PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardNam= e); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + PlatformNameSize =3D sizeof (PlatformName); + Status =3D PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)Plat= formNameSize); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNam= eSize, PlatformName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)P= latformFeatureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 =3D 0; + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\= n")); + Status =3D TypeCooperCityRPPlatformUpdateAcpiTablePcds (); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, 0); + ASSERT_EFI_ERROR(Status); + + if (DynamicSiLibraryPpi->IsCpuAndRevision (CPU_CPX, REV_ALL)) { + // Update VR ID Address + TypeCooperCityRPPlatformUpdateVrIdAddress (); + } + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeCooperCityRPPcdUpdateTable =3D +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeCooperCityRPPlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeCooperCityRPInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeCooperCityRPPcdUpdateTable, + sizeof(TypeCooperCityRPPcdUpdateTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Typ= eCooperCityRP/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..ca57086394 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/P= chEarlyUpdate.c @@ -0,0 +1,81 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include + +#include +#include +#include +#include + +EFI_STATUS +TypeCooperCityRPPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->PchDisableGbe (); + + return EFI_SUCCESS; +} + +EFI_STATUS +TypeCooperCityRPOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeCooperCityRPPchEarlyUpdateTable =3D +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeCooperCityRPPchLanConfig, + TypeCooperCityRPOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeCooperCityRPPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeCooperCityRPPchEarlyUpdateTable, + sizeof(TypeCooperCityRPPchEarlyUpdateTable) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeC= ooperCityRP/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..8cdc0cfb53 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/P= eiBoardInit.h @@ -0,0 +1,96 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLATFORM_CAPABILITY_UNDEFINED 0 +#define PLATFORM_CAPABILITY_2_SOCKET 1 +#define PLATFORM_CAPABILITY_4_SOCKET 2 +#define PLATFORM_CAPABILITY_8_SOCKET 3 + +STATIC CHAR8 *PlatformCapabilitiesStr[] =3D { + "Unknown", // PLATFORM_CAPABILITY_UNDEFINED + "2-Socket", // PLATFORM_CAPABILITY_2_SOCKET + "4-Socket", // PLATFORM_CAPABILITY_4_SOCKET + "8-Socket" // PLATFORM_CAPABILITY_8_SOCKET +}; + +//TypeCooperCityRP +EFI_STATUS +GetPlatformCapabilitiesInfo ( + IN OUT UINT8 *PlatformCapabilities, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ); + +EFI_STATUS +TypeCooperCityRPPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeCooperCityRPPlatformUpdateAcpiTablePcds ( + VOID +); + +EFI_STATUS +TypeCooperCityRPInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) ; + +EFI_STATUS +TypeCooperCityRPInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeCooperCityRPInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeCooperCityRPInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeCooperCityRPIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeCooperCityRPInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); +EFI_STATUS +TypeCooperCityRPInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi, + IN UINT8 PlatformCapabilities +); + +EFI_STATUS +EFIAPI +TypeCooperCityRPPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Ty= peCooperCityRP/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..d76e2f29a3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/P= eiBoardInitLib.c @@ -0,0 +1,224 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include +#include +#include + + +/** + + Identifies platform capabilites if the platform is a 2-socket standalone + modular board, or a 4-socket modular boards, or 8-socket modular boards. + + @param[in,out] PlatformCapabilities Holds the information about platf= orm being + a standalone 2S, or 4S/8S modular= boards. + + @retval EFI_SUCCESS Platform Capabilities is updated. + +**/ +EFI_STATUS +GetPlatformCapabilitiesInfo ( + IN OUT UINT8 *PlatformCapabilities, + IN DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi + ) +{ + GPIO_CONFIG PadConfig; + UINT32 GpioState; + EFI_STATUS Status =3D EFI_SUCCESS; + + *PlatformCapabilities =3D PLATFORM_CAPABILITY_UNDEFINED; + + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + PadConfig.Direction =3D GpioDirIn; + PadConfig.OutputState =3D GpioOutDefault; + PadConfig.InterruptConfig =3D GpioIntDefault; + PadConfig.PowerConfig =3D GpioResetDefault; + PadConfig.ElectricalConfig =3D GpioTermDefault; + PadConfig.LockConfig =3D GpioLockDefault; + PadConfig.OtherSettings =3D GpioRxRaw1Default; + + // + // GPP_D6 is standalone signal. GPP_D7 is 4S/8S signal. + // GPP_D7 | GPP_D6 + // =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // Don't care | 0 (2-socket) + // 1 | 1 (4-socket) + // 0 | 1 (8-socket) + // + + if (DynamicSiLibraryPpi->IsSimicsEnvironment ()) { + // + // Workaround until GPIO pins new definition are implemented in Simics + // + *PlatformCapabilities =3D PLATFORM_CAPABILITY_8_SOCKET; + return EFI_SUCCESS; + } + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfigByPchId (PCH_LEGACY_ID, = GPIO_SKL_H_GPP_D6, &PadConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_ID,= GPIO_SKL_H_GPP_D6, &GpioState); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "GPP_D6:%d\n", GpioState)); + + if (GpioState =3D=3D 0) { + *PlatformCapabilities =3D PLATFORM_CAPABILITY_2_SOCKET; + return Status; + } + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfigByPchId (PCH_LEGACY_ID, = GPIO_SKL_H_GPP_D7, &PadConfig); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY_ID,= GPIO_SKL_H_GPP_D7, &GpioState); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "GPP_D7:%d\n", GpioState)); + + *PlatformCapabilities =3D (GpioState =3D=3D 1) ? PLATFORM_CAPABILITY_4_S= OCKET : PLATFORM_CAPABILITY_8_SOCKET; + + return Status; +} + + +EFI_STATUS +EFIAPI +TypeCooperCityRPPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + CONST CHAR8 *Str; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + if (PlatformInfo->BoardId =3D=3D TypeCooperCityRP) { + + DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: CooperCityRP\n", Platf= ormInfo->BoardId)); + + PlatformInfo->MaxNumOfPchs =3D 4; + ASSERT (PlatformInfo->MaxNumOfPchs <=3D PCH_MAX); + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &= DynamicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D TypeCooperCityRPInstallGpioData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPInstallPcdData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPPchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPPlatformUpdateUsbOcMappings (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeCooperCityRPInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Set default memory type connector to DimmConnectorSmt + // + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType, sizeof (Pl= atformInfo->MemoryConnectorType), DimmConnectorSmt); + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown; + } + + GetPlatformCapabilitiesInfo (&PlatformInfo->PlatformCapabilities, Dyna= micSiLibraryPpi); + + Str =3D (PlatformInfo->PlatformCapabilities <=3D PLATFORM_CAPABILITY_8= _SOCKET) ? \ + PlatformCapabilitiesStr[PlatformInfo->PlatformCapabilities] : Pl= atformCapabilitiesStr[PLATFORM_CAPABILITY_UNDEFINED]; + DEBUG ((DEBUG_INFO, "PlatformCapabilities =3D %a\n", Str)); + + Status =3D TypeCooperCityRPInstallKtiEparamData (UbaConfigPpi, Platfor= mInfo->PlatformCapabilities); + if (EFI_ERROR(Status)) { + return Status; + } + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/= TypeCooperCityRP/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..1d85e045c6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/P= eiBoardInitLib.inf @@ -0,0 +1,163 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TypeCooperCityRPPeiBoardInitLib + FILE_GUID =3D 25C91D0F-42ED-7D06-B96D-89A13AA3D02E + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D TypeCooperCityRPPeiBoardInitLibConstr= uctor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInit.h + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCoop= erCityRP/Pei/SlotTable.c new file mode 100644 index 0000000000..63a8fcdb15 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/S= lotTable.c @@ -0,0 +1,164 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeCooperCityRPPchPciSlotImpementedTableData[] =3D { + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeCooperCityRPIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1C-1D as x4x4 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_x4x4xxx8; + return IOU0Data; +} + +UINT8 +GetTypeCooperCityRPIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +PLATFORM_SLOT_UPDATE_TABLE TypeCooperCityRPSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + NULL, + GetTypeCooperCityRPIOU0Setting, + 1 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeCooperCityRPSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + NULL, + GetTypeCooperCityRPIOU0Setting, + 1, + GetTypeCooperCityRPIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeCooperCityRPPchPciSlotI= mplementedTable =3D { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeCooperCityRPPchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeCooperCityRPInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeCooperCityRPSlotTable, + sizeof(TypeCooperCityRPSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeCooperCityRPSlotTable2, + sizeof(TypeCooperCityRPSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeCooperCityRPPchPciSlotImplementedTab= le, + sizeof(TypeCooperCityRPPchPciSlotImplemen= tedTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Typ= eCooperCityRP/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..a972309937 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/S= oftStrapFixup.c @@ -0,0 +1,110 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeCooperCityRPSoftStrapTable[] =3D +{ +// SoftStrapNumber, LowBit, BitLength, Value + +/// +/// Lignhtning Ridge 4S RP platform (Board ID=3D0x10 - TypeCooperCityRP) +/// +// SoftStrapNumber, LowBit, BitLength, Value + {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary M= ux Select + {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control + {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2) + {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3) + {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select b= etween sSATA Port 2 and PCIe Port 8) + {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_G= P2) + {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_G= P3) + {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled + {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2 + {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3 + {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0 + {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1 + {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2 + {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3 + {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4 + {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2 + {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5 + {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6 + {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7 + {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address + {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address + {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable + {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect + {88, 8, 2, 0x3 }, // Root Port Configuration 0 + {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between S= ATA Port 0 and PCIe Port 12 + {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between S= ATA Port 1 and PCIe Port 13 + {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between S= ATA Port 2 and PCIe Port 14 + {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between S= ATA Port 3 and PCIe Port 15 + {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between S= ATA Port 4 and PCIe Port 16 + {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between S= ATA Port 5 and PCIe Port 17 + {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between S= ATA Port 6 and PCIe Port 18 + {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between S= ATA Port 7 and PCIe Port 19 + {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0= and PCIe Port 12 + {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1= and PCIe Port 13 + {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2= and PCIe Port 14 + {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3= and PCIe Port 15 + {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4= and PCIe Port 16 + {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5= and PCIe Port 17 + {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6= and PCIe Port 18 + {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7= and PCIe Port 19 + {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection + {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled + {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled + {133, 1, 1, 0x1 }, // Dual I/O Read Enabled + {133, 2, 1, 0x1 }, // Quad Output Read Enabled + {133, 3, 1, 0x1 }, // Quad I/O Read Enabled + {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode + {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable + {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency + {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode + +// +// END OF LIST +// + {0, 0, 0, 0} +}; + +VOID +TypeCooperCityRPPlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ + +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeCooperCityRPSoftStrapUpdate =3D +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeCooperCityRPSoftStrapTable, + TypeCooperCityRPPlatformSpecificUpdate +}; + +EFI_STATUS +TypeCooperCityRPInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeCooperCityRPSoftStrapUpdate, + sizeof(TypeCooperCityRPSoftStrapUpdate) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityR= P/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCi= tyRP/Pei/UsbOC.c new file mode 100644 index 0000000000..018d725164 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeCooperCityRP/Pei/U= sbOC.c @@ -0,0 +1,123 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + + +#include +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeCooperCityRPUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPin0, //Port00: Zepher = ,OC0# + UsbOverCurrentPin1, //Port01: Read Connecto= r,OC1# + UsbOverCurrentPinSkip, //Port02: User bay = ,OC0# + UsbOverCurrentPinSkip, //Port03: iBMC USB 1.1 = ,no OCn# + UsbOverCurrentPinSkip, //Port04: NONE = ,no OCn# + UsbOverCurrentPin2, //Port05: Read Connecto= r,OC2# + UsbOverCurrentPin1, //Port06: Read Connecto= r,OC1# + UsbOverCurrentPin2, //Port07: Read Connecto= r,OC2# + UsbOverCurrentPinSkip, //Port08: NONE = ,no OCn# + UsbOverCurrentPinSkip, //Port09: NONE = ,no OCn# + UsbOverCurrentPinSkip, //Port10: iBMC USB 2.0 = ,no OCn# + UsbOverCurrentPin4, //Port11: Front Panel = ,OC4# + UsbOverCurrentPinSkip, //Port12: NONE = ,no OCn# + UsbOverCurrentPin4 //Port13: Front Panel = ,OC4# + }; + +USB_OVERCURRENT_PIN TypeCooperCityRPUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeCooperCityRPUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {7, 0, 2, 1}, // PP0 + {7, 0, 2, 1}, // PP1 + {7, 0, 2, 1}, // PP2 + {7, 0, 2, 1}, // PP3 + {7, 0, 2, 1}, // PP4 + {7, 0, 2, 1}, // PP5 + {7, 0, 2, 1}, // PP6 + {7, 0, 2, 1}, // PP7 + {7, 0, 2, 1}, // PP8 + {7, 0, 2, 1}, // PP9 + {7, 0, 2, 1}, // PP10 + {7, 0, 2, 1}, // PP11 + {7, 0, 2, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeCooperCityRPPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeCooperCityRPUsb20OverCurrentMappin= gs[0]; + *Usb30OverCurrentMappings =3D &TypeCooperCityRPUsb30OverCurrentMappin= gs[0]; + *Usb20AfeParams =3D TypeCooperCityRPUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeCooperCityRPUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeCooperCityRPPlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeCooperCityRPPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + //# + //# USB, see PG 104 in GZP SCH + //# + +// USB2 USB3 Port OC +// +//Port00: PORT5 Back Panel ,OC0# +//Port01: PORT2 Back Panel ,OC0# +//Port02: PORT3 Back Panel ,OC1# +//Port03: PORT0 NOT USED ,NA +//Port04: BMC1.0 ,NA +//Port05: INTERNAL_2X5_A ,OC2# +//Port06: INTERNAL_2X5_A ,OC2# +//Port07: NOT USED ,NA +//Port08: EUSB (AKA SSD) ,NA +//Port09: INTERNAL_TYPEA ,OC6# +//Port10: PORT1 Front Panel ,OC5# +//Port11: NOT USED ,NA +//Port12: BMC2.0 ,NA +//Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeCooperCityRPUsbOcUpdate, + sizeof(TypeCooperCityRPUsbOcUpdate) + ); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeWilsonCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c new file mode 100644 index 0000000000..72c55bc1c9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,99 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateWilsonCityRPIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeWilsonCityRPIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateWilsonCityRPIioConfig, + IioSlotTable, + sizeof(IioSlotTable) + +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeWilsonCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeWilsonCityRPIioConfigTable, + sizeof(TypeWilsonCityRPIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeWilsonCityRPIioConfigTable, + sizeof(TypeWilsonCityRPIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeWilsonCityRPIioConfigTable, + sizeof(TypeWilsonCityRPIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeWilsonCityRPIioConfigTable, + sizeof(TypeWilsonCityRPIioConfigTable) + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeWilsonCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h new file mode 100644 index 0000000000..662fa2c650 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,118 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =3D +{ + // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev= 0.6) + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | H= ot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD = | Hidden + // Index | | lock | Scale | Value | P= lug | Port | Addr | Cap | VppPort | VppAddr = | + { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C = , HIDE },//Oculink + { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C = , HIDE },//Oculink + { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 11= 8 (MRL in J65) + { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 12= 1 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoard= Pkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf new file mode 100644 index 0000000000..82840c9a24 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,47 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioCfgUpdateDxeWilsonCityRP + FILE_GUID =3D 4983CB47-56FD-4341-88EC-F0C95B36DF12 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioCfgUpdateEntry + +[sources] + IioCfgUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeWilsonCityRPProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoa= rdPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c new file mode 100644 index 0000000000..31676bdeb6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,115 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeWilsonCityRPIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeWilsonCityRPIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeWilsonCityRPBroadwayTable= [] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeWilsonCityRPSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeWilsonCityRPBroadwayTable, + GetTypeWilsonCityRPIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeWilsonCityRPSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeWilsonCityRPBroadwayTable, + GetTypeWilsonCityRPIOU0Setting, + 0, + GetTypeWilsonCityRPIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeWilsonCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeWilsonCityRPSlotTable, + sizeof(TypeWilsonCityRPSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeWilsonCityRPSlotTable2, + sizeof(TypeWilsonCityRPSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoa= rdPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h new file mode 100644 index 0000000000..9be882b09e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenB= oardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDx= e.inf new file mode 100644 index 0000000000..a0e61e210f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,47 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SlotDataUpdateDxeWilsonCityRP + FILE_GUID =3D A29C22DA-2EE0-4a36-A4E5-CCBCEAD1DB8F + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SlotDataUpdateEntry + +[sources] + SlotDataUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeWilsonCityRPProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/= Uba/UbaMain/TypeWilsonCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..0ec35ad330 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,127 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeWilsonCityRPUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPinSkip, //Port00: BMC + UsbOverCurrentPinSkip, //Port01: BMC + UsbOverCurrentPin0, //Port02: Rear Panel + UsbOverCurrentPin1, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPinSkip, //Port05: NC + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPin4, //Port07: Type A intern= al + UsbOverCurrentPinSkip, //Port08: NC + UsbOverCurrentPinSkip, //Port09: NC + UsbOverCurrentPin6, //Port10: Front Panel + UsbOverCurrentPinSkip, //Port11: NC + UsbOverCurrentPin6, //Port12: Front Panel + UsbOverCurrentPinSkip, //Port13: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeWilsonCityRPUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin6, //Port01: Front Panel + UsbOverCurrentPin6, //Port02: Front Panel + UsbOverCurrentPin0, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPin1, //Port05: Rear Panel + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeWilsonCityRPUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeWilsonCityRPPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeWilsonCityRPUsb20OverCurrentMapping= s[0]; + *Usb30OverCurrentMappings =3D &TypeWilsonCityRPUsb30OverCurrentMapping= s[0]; + + *Usb20AfeParams =3D TypeWilsonCityRPUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeWilsonCityRPUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeWilsonCityRPPlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((EFI_D_INFO, "UBA:UsbOcUpdate-TypeWilsonCityRP\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeWilsonCityRPUsbOcUpdate, + sizeof(TypeWilsonCityRPUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/= Uba/UbaMain/TypeWilsonCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..3813eadae9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + + +#endif //_USBOC_UPDATE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPk= g/Uba/UbaMain/TypeWilsonCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf new file mode 100644 index 0000000000..03b966cdfc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,44 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UsbOcUpdateDxeWilsonCityRP + FILE_GUID =3D C92F1DF7-206C-46A7-B7D4-0F9B18E0E70A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeWilsonCityRPProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Type= WilsonCityRP/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..c1c022a62e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/A= cpiTablePcds.c @@ -0,0 +1,53 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include + +EFI_STATUS +TypeWilsonCityRPPlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiName10nm[] =3D "EPRP10NM"; // USED for identify ACP= I table for 10nm in systmeboard dxe driver + CHAR8 OemTableIdXhci[] =3D "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + DEBUG ((EFI_D_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n= ")); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + //# + //#ACPI items + //# + Size =3D AsciiStrSize (AcpiName10nm); + Status =3D PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm); + DEBUG ((DEBUG_INFO, "%a TypeWilsonCityRP ICX\n", __FUNCTION__)); + ASSERT_EFI_ERROR (Status); + + Size =3D AsciiStrSize (OemTableIdXhci); + Status =3D PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/GpioTable.c new file mode 100644 index 0000000000..59dc256041 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/G= pioTable.c @@ -0,0 +1,287 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +#include +#include +#include +#include + +// +// Board : Wilson City RP +// +static GPIO_INIT_CONFIG mGpioTableWilsonCityRP [] =3D + { + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N + {GPIO_SKL_H_GPP_A13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_15_FM_SUSACK_N + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23 + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N +// GPIO_SKL_H_GPP_B3 - Not Owned by BIOS +// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7 + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N +// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, G= pioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N + {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},/= /GPP_C_10_FM_PCH_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_19_RST_SMB_HOST_PCH_MUX_N +// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9 + {GPIO_SKL_H_GPP_D10, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11 + {GPIO_SKL_H_GPP_D12, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 + {GPIO_SKL_H_GPP_D13, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL + {GPIO_SKL_H_GPP_D14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21 + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22 + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23 + {GPIO_SKL_H_GPP_E0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone,= GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N + {GPIO_SKL_H_GPP_F0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N + {GPIO_SKL_H_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0 + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N +// GPIO_SKL_H_GPP_G20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N + {GPIO_SKL_H_GPP_G22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23 + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 + {GPIO_SKL_H_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 + {GPIO_SKL_H_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 +// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS +// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_H20, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_H22, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23 + {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4 + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5 + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6 + {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 +// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS +// GPIO_SKL_H_GPD0 - Not Owned by BIOS + {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_1_PU_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_6_FM_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_9_TP_GPD_9_SLP + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2 + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3 + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4 + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5 + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6 + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7 + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8 + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9 + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10 + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11 + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12 + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13 + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14 + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15 + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17 + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19 + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21 + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23 + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK +}; + +EFI_STATUS +TypeWilsonCityRPInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTableWilsonCityRP, + sizeof(mGpioTableWilsonCityRP) + ); + Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableWilso= nCityRP)); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeW= ilsonCityRP/Pei/IioBifurInit.c new file mode 100644 index 0000000000..c9e1be13ec --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/I= ioBifurInit.c @@ -0,0 +1,387 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 + + +// +// config file : Wilson_City_PCIe_Slot_Config_1p70.xlsx +// config sheet : WilsonCity_ICX +// +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =3D +{ + + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, 0 , 0x74 = , 0xE2 , 4 } +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] =3D { + // Port Index | Slot |Interlock |power |Power |Hotpl= ug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |= Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard |ExtnCard |Ex= tnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard= Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap = | | |Cap |Port |Address |= |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SM= Bus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port= |Vpp Address | | + {SOCKET_0_INDEX + + PORT_1A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2A_INDEX, 7 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4A_INDEX, 2 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 }, + {SOCKET_0_INDEX + + PORT_5A_INDEX, 10 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5B_INDEX, 11 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5C_INDEX, 12 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5D_INDEX, 13 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + + {SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2A_INDEX, 9 , DISABLE , 0 , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x1 }, + {SOCKET_1_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4A_INDEX, 8 , DISABLE , 0 , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5A_INDEX, 14 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5B_INDEX, 15 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5C_INDEX, 16 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5D_INDEX, 17 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 } +}; + + +// +// Tables below are generated by script. Please do not change it directly. +// +// config file: Wilson_City_PCIe_Slot_Config_1p71.xlsx +// config sheet: WilsonCity_CPX +// sheet notes: WilsonCity for CPX4 Rev0.5, 11/07/2019 +// +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable_CPX[] =3D +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0 , 0= x76, 0xE2 , 4 }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket2, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0= x7C, 0xE2 , 4 }, + { Iio_Socket2, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket2, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket3, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket3, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0= x70, 0xE2 , 4 }, + { Iio_Socket3, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket3, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, 0 , 0= x74, 0xE2 , 4 }, + { Iio_Socket3, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX } +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable_CPX[] =3D { + // Port Index | Slot |Inter |Power |Power= |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD= |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCar= d |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hot= plug|Max | + // | |lock |Limit Scale |Limit= Value |Cap | | |Cap |Port |Address= | |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SMBus A= ddr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Addre= ss |Retimer| + { SOCKET_0_INDEX + PORT_1A_INDEX, 7 , DISABLE, 0 , 75 = , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_4A_INDEX, 2 , DISABLE, 0 , 200 = , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 = , 0x1 }, + { SOCKET_0_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 = , 0x1 }, + { SOCKET_0_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 = , 0x1 }, + { SOCKET_0_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 = , 0x1 }, + { SOCKET_0_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_0_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + // Port Index | Slot |Inter |Power |Power= |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD= |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCar= d |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hot= plug|Max | + // | |lock |Limit Scale |Limit= Value |Cap | | |Cap |Port |Address= | |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SMBus A= ddr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Addre= ss |Retimer| + { SOCKET_1_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_2A_INDEX, 6 , DISABLE, 0 , 75 = , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_4A_INDEX, 10 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_0 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x1 }, + { SOCKET_1_INDEX + PORT_4B_INDEX, 11 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_1 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x1 }, + { SOCKET_1_INDEX + PORT_4C_INDEX, 12 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_0 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x1 }, + { SOCKET_1_INDEX + PORT_4D_INDEX, 13 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_1 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x1 }, + { SOCKET_1_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_1_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + // Port Index | Slot |Inter |Power |Power= |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD= |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCar= d |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hot= plug|Max | + // | |lock |Limit Scale |Limit= Value |Cap | | |Cap |Port |Address= | |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SMBus A= ddr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Addre= ss |Retimer| + { SOCKET_2_INDEX + PORT_1A_INDEX, 9 , DISABLE, 0 , 25 = , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x44 = , 0x1 }, + { SOCKET_2_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x44 = , 0x1 }, + { SOCKET_2_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x46 = , 0x1 }, + { SOCKET_2_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x46 = , 0x1 }, + { SOCKET_2_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_4A_INDEX, 8 , DISABLE, 0 , 25 = , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_2_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + // Port Index | Slot |Inter |Power |Power= |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD= |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCar= d |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hot= plug|Max | + // | |lock |Limit Scale |Limit= Value |Cap | | |Cap |Port |Address= | |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SMBus A= ddr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Addre= ss |Retimer| + { SOCKET_3_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_2A_INDEX, 4 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 = , 0x1 }, + { SOCKET_3_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 = , 0x1 }, + { SOCKET_3_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 = , 0x1 }, + { SOCKET_3_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 = , 0x1 }, + { SOCKET_3_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_4A_INDEX, 14 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_0 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 = , 0x1 }, + { SOCKET_3_INDEX + PORT_4B_INDEX, 15 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_1 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 = , 0x1 }, + { SOCKET_3_INDEX + PORT_4C_INDEX, 16 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_0 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 = , 0x1 }, + { SOCKET_3_INDEX + PORT_4D_INDEX, 17 , DISABLE, 0 , 25 = , ENABLE , VPP_PORT_1 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 = , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 = , 0x1 }, + { SOCKET_3_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 }, + { SOCKET_3_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_= VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_AD= DR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DAT= A_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_AD= DR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR= _MAX, 0x0 } + // Port Index | Slot |Inter |Power |Power= |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD= |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCar= d |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hot= plug|Max | + // | |lock |Limit Scale |Limit= Value |Cap | | |Cap |Port |Address= | |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SMBus A= ddr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Addre= ss |Retimer| +}; + + +EFI_STATUS +UpdateWilsonCityRPIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeWilsonCityRPIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateWilsonCityRPIioConfig, + IioSlotTable, + sizeof(IioSlotTable) +}; + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeWilsonCityRPIioConfigTable_CPX = =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable_CPX, + sizeof(IioBifurcationTable_CPX), + UpdateWilsonCityRPIioConfig, + IioSlotTable_CPX, + sizeof(IioSlotTable_CPX) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeWilsonCityRPIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr; + UINTN PlatformIioInfoSize; + + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + // + // This is config for ICX + // + PlatformIioInfoPtr =3D &TypeWilsonCityRPIioConfigTable; + PlatformIioInfoSize =3D sizeof(TypeWilsonCityRPIioConfigTable); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/KtiEparam.c new file mode 100644 index 0000000000..dd67a65a54 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/K= tiEparam.c @@ -0,0 +1,107 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO KtiWilsonCityRPIcxAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA K= tiEparam tables + // + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE}, + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE} +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeWilsonCityRPIcxKtiEparamUpdate =3D { + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiWilsonCityRPIcxAllLanesEparamTable, + sizeof (KtiWilsonCityRPIcxAllLanesEparamTable), + NULL, + 0 +}; + + +ALL_LANES_EPARAM_LINK_INFO KtiWilsonCityRPCpxAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE}, + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE}, + + // + // Socket 2 + // + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE}, + {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE}, + + // + // Socket 3 + // + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE}, + {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE} +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeWilsonCityRPCpxKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiWilsonCityRPCpxAllLanesEparamTable, + sizeof (KtiWilsonCityRPCpxAllLanesEparamTable), + NULL, + 0 +}; + + +EFI_STATUS +TypeWilsonCityRPInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + &TypeWilsonCityRPIcxKtiEparamUpdate, + sizeof(TypeWilsonCityRPIcxKtiEparamUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilson= CityRP/Pei/PcdData.c new file mode 100644 index 0000000000..8565b3c761 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/P= cdData.c @@ -0,0 +1,274 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_SKL_H_GPP_B20 0x01010014 + +VOID TypeWilsonCityRPPlatformUpdateVrIdAddress (VOID); + +/** + Update WilsonCity IMON SVID Information + + retval N/A +**/ +VOID +TypeWilsonCityRPPlatformUpdateImonAddress ( + VOID + ) +{ + VCC_IMON *VccImon =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (VCC_IMON); + VccImon =3D (VCC_IMON *) PcdGetPtr (PcdImonAddr); + if (VccImon =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "UpdateImonAddress() - PcdImonAddr =3D=3D NULL\n"= )); + return; + } + + VccImon->VrSvid[0] =3D PcdGet8 (PcdWilsonCitySvidVrP1V8); + VccImon->VrSvid[1] =3D PcdGet8 (PcdWilsonCitySvidVrVccAna); + VccImon->VrSvid[2] =3D IMON_ADDR_LIST_END; // End array with 0xFF + + PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon); +} + +/** + Update WilsonCity VR ID SVID Information + + retval N/A +**/ +VOID +TypeWilsonCityRPPlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (MEM_SVID_MAP); + MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D NULL= \n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14,= and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs = (VR ID's 0x10 and 0x12). + Those are typically shared such that MC0/MC2 share the same DDR VR (as= they are on the same side of the CPU) + and MC1/MC3 share the other. Depending on motherboard layout and other= design constraints, this could change + BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + BIT 0:3 =3D> SVID ADDRESS + */ + + MemSvidMap->Socket[0].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeWilsonCityRPPlatformPcdUpdateCallback ( + VOID +) +{ + CHAR8 FamilyName[] =3D "Whitley"; + + CHAR8 BoardName[] =3D "EPRP"; + UINT32 Data32; + UINTN Size; + UINTN PlatformFeatureFlag =3D 0; + + CHAR16 PlatformName[] =3D L"TypeWilsonCityRP"; + UINTN PlatformNameSize =3D 0; + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status =3D PcdSet16S (PcdOemSkuBoardID , TypeWilson= CityRP); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet16S (PcdOemSkuBoardFamily , 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Number of Sockets on Board. + Status =3D PcdSet32S (PcdOemSkuBoardSocketCount, 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status =3D PcdSet32S (PcdOemSkuMaxChannel , 8); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status =3D PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size =3D AsciiStrSize (FamilyName); + Status =3D PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyNa= me); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size =3D AsciiStrSize (BoardName); + Status =3D PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardNam= e); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + PlatformNameSize =3D sizeof (PlatformName); + Status =3D PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)Plat= formNameSize); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNam= eSize, PlatformName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)P= latformFeatureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 =3D 0; + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\= n")); + Status =3D TypeWilsonCityRPPlatformUpdateAcpiTablePcds (); + //# BMC Pcie Port Number + PcdSet8S (PcdOemSkuBmcPciePortNumber, 5); + ASSERT_EFI_ERROR(Status); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4)= ); + ASSERT_EFI_ERROR(Status); + + //Update IMON Address + TypeWilsonCityRPPlatformUpdateImonAddress (); + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeWilsonCityRPPcdUpdateTable =3D +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeWilsonCityRPPlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeWilsonCityRPInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeWilsonCityRPPcdUpdateTable, + sizeof(TypeWilsonCityRPPcdUpdateTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Typ= eWilsonCityRP/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..a2ee2322c3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/P= chEarlyUpdate.c @@ -0,0 +1,92 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include + +#include +#include +#include +#include + +EFI_STATUS +TypeWilsonCityRPPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)Syst= emConfig->LomDisableByGpio); + DynamicSiLibraryPpi->PchDisableGbe (); + + return EFI_SUCCESS; +} + +EFI_STATUS +TypeWilsonCityRPOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeWilsonCityRPPchEarlyUpdateTable =3D +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeWilsonCityRPPchLanConfig, + TypeWilsonCityRPOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeWilsonCityRPPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeWilsonCityRPPchEarlyUpdateTable, + sizeof(TypeWilsonCityRPPchEarlyUpdateTable) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeW= ilsonCityRP/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..56338b458e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/P= eiBoardInit.h @@ -0,0 +1,77 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// TypeWilsonCityRP +EFI_STATUS +TypeWilsonCityRPPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPPlatformUpdateAcpiTablePcds ( + VOID +); + +EFI_STATUS +TypeWilsonCityRPInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPPchEarlyUpdate ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeWilsonCityRPInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +// TypeWilsonCityRP +EFI_STATUS +TypeWilsonCityRPInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) ; + +EFI_STATUS +TypeWilsonCityRPInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Ty= peWilsonCityRP/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..44279bb1bd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/P= eiBoardInitLib.c @@ -0,0 +1,156 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include +#include +#include + +EFI_STATUS +EFIAPI +TypeWilsonCityRPPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + UINT8 ChannelIndex; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + if (PlatformInfo->BoardId =3D=3D TypeWilsonCityRP) { + + DEBUG ((EFI_D_INFO, "PEI UBA init BoardId 0x%X: WilsonCityRP\n", Platf= ormInfo->BoardId)); + + // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + for (ChannelIndex =3D 0; ChannelIndex < MAX_CH; ChannelIndex++) { + switch (SocketIndex) { + case 0: + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorSmt; + break; + case 1: + // Fall through since socket 1 is PTH type + default: + // Use the more restrictive type as the default case + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorPth; + break; + } + } + } + + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfo), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D TypeWilsonCityRPInstallGpioData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPInstallPcdData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPPchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPPlatformUpdateUsbOcMappings (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeWilsonCityRPInstallKtiEparamData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + + // + // Set default memory type connector. + // Socket 0: DimmConnectorSmt + // Socket 1: DimmConnectorPth + // + if (SocketIndex % 2 =3D=3D 0) { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orSmt); + } else { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orPth); + } + } + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown; + } + + // + // TypeWilsonCityRPIioPortBifurcationInit will use PlatformInfo->Inte= rposerType for PPO. + // + Status =3D TypeWilsonCityRPIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + } + return Status; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/= TypeWilsonCityRP/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..974831de89 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/P= eiBoardInitLib.inf @@ -0,0 +1,166 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TypeWilsonCityRPPeiBoardInitLib + FILE_GUID =3D 14074de7-ed3e-4f58-a19c-b461656af3e0 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D TypeWilsonCityRPPeiBoardInitLibConstr= uctor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + PeiBoardInit.h + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWils= onCityRP/Pei/SlotTable.c new file mode 100644 index 0000000000..49d83dbb4a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/S= lotTable.c @@ -0,0 +1,171 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeWilsonCityRPPchPciSlotImpementedTableData[] =3D { + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeWilsonCityRPIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeWilsonCityRPIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeWilsonCityRPBroadwayTable= [] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeWilsonCityRPSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeWilsonCityRPBroadwayTable, + GetTypeWilsonCityRPIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeWilsonCityRPSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeWilsonCityRPBroadwayTable, + GetTypeWilsonCityRPIOU0Setting, + 0, + GetTypeWilsonCityRPIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeWilsonCityRPPchPciSlotI= mplementedTable =3D { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeWilsonCityRPPchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeWilsonCityRPInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeWilsonCityRPSlotTable, + sizeof(TypeWilsonCityRPSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeWilsonCityRPSlotTable2, + sizeof(TypeWilsonCityRPSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeWilsonCityRPPchPciSlotImplementedTab= le, + sizeof(TypeWilsonCityRPPchPciSlotImplemen= tedTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Typ= eWilsonCityRP/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..055b2de311 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/S= oftStrapFixup.c @@ -0,0 +1,120 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeWilsonCityRPSoftStrapTable[] =3D +{ +// SoftStrapNumber, LowBit, BitLength, Value + {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary M= ux Select + {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control + {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2) + {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3) + {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select b= etween sSATA Port 2 and PCIe Port 8) + {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_G= P2) + {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_G= P3) + {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled + {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2 + {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3 + {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0 + {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1 + {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2 + {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3 + {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4 + {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2 + {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5 + {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6 + {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7 + {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act a= s Downlink or Uplink(PCIEUDS) + {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address + {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address + {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable + {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect + {88, 8, 2, 0x3 }, // Root Port Configuration 0 + {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between S= ATA Port 0 and PCIe Port 12 + {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between S= ATA Port 1 and PCIe Port 13 + {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between S= ATA Port 2 and PCIe Port 14 + {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between S= ATA Port 3 and PCIe Port 15 + {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between S= ATA Port 4 and PCIe Port 16 + {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between S= ATA Port 5 and PCIe Port 17 + {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between S= ATA Port 6 and PCIe Port 18 + {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between S= ATA Port 7 and PCIe Port 19 + {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0= and PCIe Port 12 + {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1= and PCIe Port 13 + {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2= and PCIe Port 14 + {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3= and PCIe Port 15 + {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4= and PCIe Port 16 + {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5= and PCIe Port 17 + {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6= and PCIe Port 18 + {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7= and PCIe Port 19 + {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection + {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled + {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled +// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled +// {133, 2, 1, 0x1 }, // Quad Output Read Enabled +// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled +// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode +// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable +// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency +// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode + +// +// END OF LIST +// + {0, 0, 0, 0} +}; + +UINT32 +TypeWilsonCityRPSystemBoardRevIdValue (VOID) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT(GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return 0xFF; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + return PlatformInfo->TypeRevisionId; +} + +VOID +TypeWilsonCityRPPlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeWilsonCityRPSoftStrapUpdate =3D +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeWilsonCityRPSoftStrapTable, + TypeWilsonCityRPPlatformSpecificUpdate +}; + +EFI_STATUS +TypeWilsonCityRPInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeWilsonCityRPSoftStrapUpdate, + sizeof(TypeWilsonCityRPSoftStrapUpdate) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityR= P/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCi= tyRP/Pei/UsbOC.c new file mode 100644 index 0000000000..e978abbb8e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/U= sbOC.c @@ -0,0 +1,126 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + + +#include +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeWilsonCityRPUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPin7, + UsbOverCurrentPin7, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin4, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeWilsonCityRPUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeWilsonCityRPUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeWilsonCityRPPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeWilsonCityRPUsb20OverCurrentMapping= s[0]; + *Usb30OverCurrentMappings =3D &TypeWilsonCityRPUsb30OverCurrentMapping= s[0]; + + *Usb20AfeParams =3D TypeWilsonCityRPUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeWilsonCityRPUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeWilsonCityRPPlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeWilsonCityRPPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + //# + //# USB, see PG 104 in GZP SCH + //# + +// USB2 USB3 Port OC +// +//Port00: PORT5 Back Panel ,OC0# +//Port01: PORT2 Back Panel ,OC0# +//Port02: PORT3 Back Panel ,OC1# +//Port03: PORT0 NOT USED ,NA +//Port04: BMC1.0 ,NA +//Port05: INTERNAL_2X5_A ,OC2# +//Port06: INTERNAL_2X5_A ,OC2# +//Port07: NOT USED ,NA +//Port08: EUSB (AKA SSD) ,NA +//Port09: INTERNAL_TYPEA ,OC6# +//Port10: PORT1 Front Panel ,OC5# +//Port11: NOT USED ,NA +//Port12: BMC2.0 ,NA +//Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeWilsonCityRPUsbOcUpdate, + sizeof(TypeWilsonCityRPUsbOcUpdate) + ); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf b/Platform/I= ntel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf new file mode 100644 index 0000000000..fb461c55d7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf @@ -0,0 +1,24 @@ +## @file +# Uba Pei fdf file +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +INF $(RP_PKG)/Uba/CfgDb/Pei/CfgDbPei.inf + +# +# Board Init Peim +# +INF $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf + +# +# For Dynamic Feature Support +# + +# +# Update all PCDs for UBA in PEI phase +# +INF $(RP_PKG)/Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platf= orm/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc new file mode 100644 index 0000000000..6f367b58e7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc @@ -0,0 +1,44 @@ +## @file UbaRpBoards.dsc +# UBA DSC include file for board specific build items +# +# @copyright +# Copyright 2012 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Components.IA32] +# +# Board Init Peim +# +$(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf { + + NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Pei/PeiBoardInitLib= .inf + NULL|$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Pei/PeiBoardInitLib= .inf + # + #### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!! + # + # Do not place any platform specific PeiBoardInitLib.inf entrie= s after PeiCommonBoardInitLib.inf + # The order of this libary class list is translated directly in= to the autogen.c created + # to execute the libary constructors for all the platforms in t= his list. + # PeiCommonBoardInitLib.inf depends on being the last construct= or to execute and + # assumes that a platform specific constructor has executed and= installed its UBA + # configuration information. + # + NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf +} + +[Components.X64] +# +# Platform TypeWilsonCityRP +# +$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.i= nf +$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe= .inf +$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdat= eDxe.inf + +# +# Platform TypeCooperCityRP +# +$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.i= nf +$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe= .inf +$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdat= eDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Updat= ePcdsPei.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Updat= ePcdsPei.c new file mode 100644 index 0000000000..0f33613dbb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPe= i.c @@ -0,0 +1,43 @@ +/** @file + UBA PCDs update PEIM. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UpdatePcdsPei.h" + +EFI_PEI_PPI_DESCRIPTOR mPpiListUpdatePcds =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gUpdatePcdGuid, + NULL +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +UpdatePcdPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices +) +{ + EFI_STATUS Status; + + Status =3D PlatformUpdatePcds(); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (&mPpiListUpdatePcds); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Updat= ePcdsPei.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Updat= ePcdsPei.h new file mode 100644 index 0000000000..b4eaae28e9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPe= i.h @@ -0,0 +1,20 @@ +/** @file + UBA PCDs update PEIM. + + @copyright + Copyright 2014 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UPDATE_SKU_TYPE_PEIM_H_ +#define _UPDATE_SKU_TYPE_PEIM_H_ + +#include +#include +#include +#include +#include +#include + +#endif // _UPDATE_SKU_TYPE_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Updat= ePcdsPei.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/Upd= atePcdsPei.inf new file mode 100644 index 0000000000..1e419c63de --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPe= i.inf @@ -0,0 +1,50 @@ +## @file +# Uba update pcds in PEI phase. +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UpdatePcdPei + FILE_GUID =3D AB8F1705-7EB6-4d08-A9B3-918BDE24F479 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D UpdatePcdPeimEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + UpdatePcdsPei.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + PeiServicesLib + PeimEntryPoint + DebugLib + PeiServicesTablePointerLib + UbaPlatLib + +[Guids] + +[Ppis] + gUpdatePcdGuid + +[Pcd] + +[Depex] + gBoardInitGuid + + --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 12 Jul 2021 17:42:32 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="190456265" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="190456265" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:06 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653423035" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:01 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 14/17] WhitleyOpenBoardPkg: Add build scripts and package metadata Date: Mon, 12 Jul 2021 17:41:28 -0700 Message-Id: <20210713004131.1782-15-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: IYBoiMy2L5bOczwvhkIjNghWx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136957; bh=N/Lf9gHBDG1K5p2Pmt40HzpDCjjav+T5hFUbkZFja5c=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=CdAOoh60jJdZiFTD+GsAh67M55kSH0nVWkpAHO2bsYQCkY+w/J9N1D3iqKzLp/VgNxJ 2Dfmj+4dUbbl+WqtdIoek4zCuxP/yXQ1kfUrcOGglTMmvpTWGpw3+qMwdskFB/mXOqYDt P4/tFEUeW52W9PZgvWFI7Y1959C1OmkRzh8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136959853100001 Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- .../CooperCityRvp/build_board.py | 111 + .../CooperCityRvp/build_config.cfg | 36 + .../WhitleyOpenBoardPkg/DynamicExPcd.dsc | 19 + .../WhitleyOpenBoardPkg/FspFlashOffsets.fdf | 21 + .../Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 781 ++ .../Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 931 ++ .../Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 827 ++ .../WhitleyOpenBoardPkg/PlatformPkgConfig.dsc | 45 + .../WhitleyOpenBoardPkg/StructurePcd.dsc | 8553 +++++++++++++++++ .../WhitleyOpenBoardPkg/StructurePcdCpx.dsc | 3796 ++++++++ .../WilsonCityRvp/build_board.py | 111 + .../WilsonCityRvp/build_config.cfg | 36 + 12 files changed, 15267 insertions(+) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_= board.py create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_= config.cfg create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_= board.py create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_= config.cfg diff --git a/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.p= y b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py new file mode 100644 index 0000000000..87b49b32c8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py @@ -0,0 +1,111 @@ +# @ build_board.py +# Extensions for building CooperCityRvp using build_bios.py +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE= "], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] =3D os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] =3D os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] =3D os.path.join(config["BUILD_DIR_PATH"], 'IA32') + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D0" + else: + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D1" + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd =3D os.path.join(fv_path, "BINARY.fd") + main_fd =3D os.path.join(fv_path, "MAIN.fd") + secpei_fd =3D os.path.join(fv_path, "SECPEI.fd") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.= cfg b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg new file mode 100644 index 0000000000..6399818e78 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg @@ -0,0 +1,36 @@ +# @ build_config.cfg +# This is the CooperCityRvp board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhitleyOpenBoardPkg +PROJECT =3D WhitleyOpenBoardPkg/CooperCityRvp +BOARD =3D CooperCityRvp +FLASH_MAP_FDF =3D WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC =3D WhitleyOpenBoardPkg/PlatformPkg.dsc +BOARD_PKG_PCD_DSC =3D WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS =3D WhitleyOpenBoardPkg/CooperCityRvp/build_board.py +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D -D CPUTARGET=3DCPX -D RP_PKG=3DWhitleyOpenBoardPkg -D = SILICON_PKG=3DWhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=3D6= 4 -D MAX_THREAD=3D2 -D PLATFORM_PKG=3DMinPlatformPkg +MAX_SOCKET =3D 8 +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D CedarIslandFspBinPkg +FSP_PKG_NAME =3D CedarIslandFspPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 diff --git a/Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc b/Platform= /Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc new file mode 100644 index 0000000000..ebeda4e8c7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc @@ -0,0 +1,19 @@ +## @file +# FSP DynamicEx PCDs +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[PcdsDynamicExDefault] + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdImr3Enable + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf b/Platf= orm/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf new file mode 100644 index 0000000000..a14afd693b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf @@ -0,0 +1,21 @@ +## @file +# FDF file for calculation of FSP rebase addresses for WhitleyOpenBoardPkg +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# @todo: This file is currently only used to enable RebaseFspBinBaseAddres= s.py to function. +# The FDF file for WhitleyOpenBoardPkg should be adapted to leverag= e FlashMapInclude.fdf +# format found in other OpenBoardPkgs. + +DEFINE FLASH_BASE =3D 0x= FF000000 # + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00020000 # Flash addr (0xFF020000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00040000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 00060000 # Flash addr (0xFF060000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 00221000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 00281000 # Flash addr (0xFF281000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00006000 # diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dec new file mode 100644 index 0000000000..8e0b674505 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -0,0 +1,781 @@ +## @file +# Platform Package +# Cross Platform Modules for Tiano +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D PlatformPkg + PACKAGE_GUID =3D 9A29FD32-8C72-4b25-A7C4-767F7A2838EB + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + Include/Protocol + +#TODO: Move these generated temp files into include. + Uba/BoardInit/Dxe + +[Guids] + gBiosInfoGuid =3D { 0x1b453c67, 0x= cb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } } + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } + gUbaCurrentConfigHobGuid =3D { 0xe4b2025b, 0x= c7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } } + + gCommonSystemConfigurationGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } } + gEfiSetupVariableGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } + gEfiSetupVariableDefaultGuid =3D { 0x8d247131, 0x= 385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } } + gEfiGlobalVariableControlGuid =3D { 0x99a96812, 0x= 4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } } + gMainPkgListGuid =3D { 0x6205c3a4, 0x= 1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } } + gAdvancedPkgListGuid =3D { 0xc09c81cb, 0x= 31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } } + gTpmPkgListGuid =3D { 0x7da45aa9, 0x= 6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } } + gSecurityPkgListGuid =3D { 0x3a885aae, 0x= 3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } } + gBootOptionsPkgListGuid =3D { 0x62197ef0, 0x= 7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } } + gEfiOcDataGuid =3D { 0x4af92599, 0x= 8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } } + gEfiDprRegsProgrammedGuid =3D { 0x4b844201, 0x= 6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } } + gPlatformModuleTokenSpaceGuid =3D { 0x69d13bf0, 0x= af91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } + gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gPchSetupVariableGuid =3D { 0x4570b7f1, 0x= ade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } } + +# +# UBA_START +# + #OEM SKU + gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } + gPlatformKtiEparamUpdateDataGuid =3D { 0x7bc065cf, 0x= afe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } + gPlatformGpioInitDataGuid =3D { 0x9282563e, 0x= ae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } +# +# UBA_END +# + gReserveMemFlagVariableGuid =3D { 0xb87aa73f, 0x= dcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } } + gEfiOpaSocketMapHobGuid =3D { 0x829d41d2, 0x= 6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } } + gEfiPlatformTxtPolicyDataGuid =3D { 0xa353290b, 0x= 867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } } + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } + gSystemBoardInfoConfigDataGuid =3D { 0x68B046F7, 0x= 15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } } + + # Fce multi mode support + gPlatformVariableHobGuid =3D { 0x71e6d4bc, 0x= 4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } } + gDefaultDataFileGuid =3D { 0x1ae42876, 0x= 008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } } + + gCpPlatIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + gEfiIpmiFormatFruGuid =3D { 0x3531fdc6, 0x= eae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } } + gServerCommonIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + + gServerMgmtPkgListGuid =3D { 0x35dcfcd1, 0x= c14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } } + + + ## Include/Guid/CpPlatPkgTokenSpace.h + gCpPlatTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gEfiSetupEnterGuid =3D { 0x71202EEE, 0x= 5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } } + gEfiSetupExitGuid =3D { 0xD6E335EC, 0x= 0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }} + + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + +[Ppis] +# +# UBA_START +# + gEfiPeiPlatformTypeWolfPassPpiGuid =3D { 0xd2a92001, 0x= 22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } } + gEfiPeiPlatformTypeNeonCityEPRPPpiGuid =3D { 0xa2e5609e, 0x= 8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } } + gEfiPeiPlatformTypeTennesseePassPpiGuid =3D { 0xf7b87a79, 0x= a640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } } + gEfiPeiPlatformTypeNeonCityEPECBPpiGuid =3D { 0x21877e2f, 0x= f86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } } + gEfiPeiPlatformTypeOpalCitySTHIPpiGuid =3D { 0xa07b3bdf, 0x= b78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } } + gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid =3D { 0x3c234470, 0x= 69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } } + gEfiPeiPlatformTypeCrescentCityPpiGuid =3D { 0x4ad920ef, 0x= 4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } } + gEfiPeiPlatformTypeHedtEVPpiGuid =3D { 0x41781f4f, 0x= a3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } } + gEfiPeiPlatformTypeHedtCRBPpiGuid =3D { 0x9bb6e29a, 0x= 2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } } + gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid =3D { 0xaf2417f4, 0x= 7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } } + gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid =3D { 0xf70a4116, 0x= fdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } } + gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid =3D { 0x0c04b0ff, 0x= 227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } } + gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid =3D { 0x94c0203b, 0x= 54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } } + gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid =3D { 0x4284a11c, 0x= 18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } } + gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid =3D { 0x4f51c243, 0x= 7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } } + gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid =3D { 0x5d9516d3, 0x= bc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } } + gEfiPeiPlatformTypeKyanitePpiGuid =3D { 0xb23ce2c1, 0x= 16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } } + gEfiPeiPlatformTypeNeonCityFPGAPpiGuid =3D { 0x48e796bd, 0x= 4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } } + gEfiPeiPlatformTypeOpalCityFPGAPpiGuid =3D { 0xe5434b26, 0x= aedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } } + gEfiPeiPlatformTypeWilsonCityRPPpiGuid =3D { 0x0629aff2, 0x= 4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } } + gEfiPeiPlatformTypeWilsonCityModularPpiGuid =3D { 0x3170ea7b, 0x= 6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } } + gEfiPlatformTypeIsoscelesPeakPpiGuid =3D { 0xfc7b089f, 0x= 5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } } + + gPeiIpmiTransportPpiGuid =3D { 0x7bf5fecc, 0x= c5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } } + +# +# UBA_END +# + + gBoardInitGuid =3D { 0xecc07551, 0x= d64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } } + gUbaConfigDatabasePpiGuid =3D { 0xc1176733, 0x= 159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } } + + gPeiSpiSoftStrapsPpiGuid =3D { 0x7F19E716, 0x= 419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } } + gUpdatePcdGuid =3D { 0xa08e4c6b, 0x= ff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } } + gPlatformVariableInitPpiGuid =3D { 0x9b1b911b, 0x= 4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } } + gUpdateBootModePpiGuid =3D { 0x927186a0, 0x= a13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } } + + gEfiPeiExStatusCodeHandlerPpiGuid =3D { 0x4e942617, 0x= bbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } } + + +[Protocols] + gEfiPlatformTypeProtocolGuid =3D { 0x171e9398, 0x= 269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } } + gUbaConfigDatabaseProtocolGuid =3D { 0xe03e0d46, 0x= 5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } } +# +# UBA_START +# + gEfiPlatformTypeNeonCityEPRPProtocolGuid =3D { 0xc0cd2d36, 0x= a81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } } + gEfiPlatformTypeHedtCRBProtocolGuid =3D { 0x2c824f87, 0x= 0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } } + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid =3D { 0x1b4ae0f8, 0x= ed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } } + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid =3D { 0x45b59855, 0x= 500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } } + gEfiPlatformTypeWilsonCityRPProtocolGuid =3D { 0x8430776f, 0x= bd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } } + gEfiPlatformTypeIsoscelesPeakProtocolGuid =3D { 0xcff3f211, 0x= 5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } } + gEfiPlatformTypeWilsonCityModularProtocolGuid =3D { 0x28e862f4, 0x= a4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } } + + gEfiPlatformTypeWilsonCitySMTProtocolGuid =3D { 0xEE55562D, 0x= 4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } + gEfiPlatformTypeCooperCityRPProtocolGuid =3D { 0x45c302e1, 0x= 4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } + +# +# UBA_END +# + + gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } + gEfiWindowsInt10Workaround =3D { 0x387f555, 0x2= 0a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } } + gEfiVMDDriverProtocolGuid =3D { 0x5a676ae9, 0x= db23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } } + gEfiHfiPcieGen3ProtocolGuid =3D { 0x7b59316e, 0x= e9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } } + gEfiLegacyBiosProtocolGuid =3D { 0xdb9a1e3d, 0x= 45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } } + + gEfiIpmiSolStatusProtocolGuid =3D { 0xe790848e, 0x= b6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } } + gEfiIpmiTransportProtocolGuid =3D { 0x6bb945e8, 0x= 3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } } + gSmmIpmiTransportProtocolGuid =3D { 0x8bb070f1, 0x= a8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } } + gEfiIpmiBootGuid =3D { 0x5c9b75ec, 0x= 8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } + gEfiGenericIpmiDriverInstalledGuid =3D { 0x7cdad61a, 0x= 3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } + + +[PcdsFixedAtBuild] + +#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used = here to it, or move these values to the SocketPkg where the GUID is defined +# Using a GUID defined in another .DEC file is a violation of the= UEFI packaging standards. + + gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E + gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x300000= 1A + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x300000= 1B + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x300= 0001C + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x300= 0001D + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000= 001E + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000= 001F + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000= 020 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000= 021 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x3000= 0027 + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000= 001 + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x300= 00004 + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x000000= 0|UINT32|0x30000006 + gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0= x30000008 + + gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030 + gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031 + + gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 + + # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied + # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max + gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 + gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 = #BIT4 =3D> SVID BUS 0, BIT3-BIT0 =3D> VR ADDRESS + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003 + + # PCD for failsafe variable ffs in other FV rather than bb1 + # by default, FCE will insert into SECPEI, and you don't need to set the= se two PCD if bb1(secpei)is used + gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034 + gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035 + + gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4,= 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30= 000036 + + # + # These need to move to MinPlatformPkg.dec + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF000= 00A9 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF000= 00AA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF0= 0000AB + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE + + #IIO configuration data for socket 3 will be used for sockets 4..7 + gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF + + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00= 000B0 + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00= 000B1 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x0= 5, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x400= 00004 + ## Specify memory size with page number for a pre-allocated reserved mem= ory to be used + # by PEI in S3 phase. The default size 32K. When changing the value mak= e sure the memory size + # is large enough to meet PEI requirement in the S3 phase. + # @Prompt Reserved S3 Boot ACPI Memory Size + gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|= 0x90010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 + gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018 + + + gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021 + gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022 + gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023 + gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90= 000024 + + gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025 + gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26 + gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027 + gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B + gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D + gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014 + gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006 + +[PcdsDynamicEx] + +# +# PAL +# + gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000= 008 + +#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use = local GUID... + gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x= 00000048 + + ## This value is used to save memory address of MRC data structure. + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 + +# +# IMR0 programming values +# + gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000 + gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001 + gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002 + gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003 + gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004 + +# +# IMR3 programming values +# + gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022 + +# +# Server common Hot Key binding +# + # EFI Scan codes + # SCAN_F2 0x000C + # SCAN_F6 0x0010 + # SCAN_F7 0x0011 + gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009 + gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A + + + gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x= 0000000B + +#Indicate whether to perform LT Config lock +# The PCD can be set to false when there is the debug request +# TRUE - Force the LT config lock +# FALSE - Allow the LT config unlock for debug + gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x30000= 00e + +#Indicate whether LTSX enabled +# TRUE - Intel (R) TXT feature enabled on the platform +# FALSE - Disable Intel(R) TXT feature on the platform + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x30= 00000f + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00= 000020 + + ## + ## High Speed UART + ## + gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x000= 0002C + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + ## MemoryCheck value for checking memory before boot OS. + # To save the boot performance, the default MemoryCheck is set to 0. + gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005 + + + ## following PCDs should remove if CORE accept the fix + gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4 + + ## Vendor ID and Device ID of device producing onboard video + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013 + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014 + gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x300= 00009 + ## This PCD is to control which device is the potential trusted console = input device.

+ # For example:
+ # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)
+ # //Header VendorId ProductId Class SubClass P= rotocol
+ # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0= x01,
+ # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x= 0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,= 0x00}|VOID*|0x300000A + + ## This PCD is to control which device is the potential trusted console = output device.

+ # For example:
+ # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)
+ # //Header HID UID
+ # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
+ # //Header Func Dev
+ # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, + # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C + + + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT= 16|0x00010038 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C + +# +# UBA_START +# +[PcdsDynamicEx] + +# +#Board Definitions +# +#Integer for BoardID, must match the SKU number and be unique. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000 +#Integer for BoardFamily, must be unique + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001 +# Zero terminated unicode string to ID family + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT = "|VOID*|0x0000002 +# Zero terminated unicode string to Board Name + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT = "|VOID*|0x00000003 +# Number of Sockets on Board. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004 + +# Number of DIMM slots per channel for each Socket + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005 + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006 + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007 + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 + +# +# USB +# +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x000000= 10 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x000000= 11 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x000000= 12 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x000000= 13 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x000000= 14 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x000000= 15 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x000000= 16 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x000000= 17 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x000000= 18 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x000000= 19 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x000000= 1A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x000000= 1B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x000000= 1C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x000000= 1D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x00000020 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x00000021 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x00000022 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x00000023 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x00000024 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x00000025 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x00000026 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x00000027 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x00000028 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x00000029 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000= 100 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000= 101 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000= 102 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000= 103 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000= 104 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000= 105 + +# +# ACPI items +# +# Acpi Name, MUST be 8 chars long + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x000000= 30 + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x000000= 31 +# +# Misc. +# + + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039 + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040 + +# +# GPIO +# + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x000= 00050 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00= 000051 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00= 000052 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x0000= 0053 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x000= 00054 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x000= 00055 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x00000056 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x000000= 57 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x000000= 58 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x00000059 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x00000= 05a + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000= 005c + +# +# SATA registers +# + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b + +# +# Clock generator settings +# + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b + gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x000000= 6c + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT = "|VOID*|0x00000201 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203 + +# +# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't s= et related GPIO. +# + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x000002= 04 + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205 + + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206 + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 +# +# UBA_END +# + + gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x10000023 + gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x100000= 21 + gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208 + + +## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpac= eGuid.PcdBootState + gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208 + +[PcdsDynamicEx] + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026 + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024 + +[PcdsFixedAtBuild] +# +# Flash map related PCD. +# +# Note: most values here are overridden in the .fdf file +# +# +# Note: FlashNv PCD naming conventions are as follows: +# +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. +# + + + +# PCD's that are for the whole SPI part + + +#Block size of SPI +gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010= 000 |UINT32|0x50000102 + + +#AJW rename this to be more in keeping with the function +gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00= 000 |UINT32|0x50000105 + + + +# for PeiSec FD + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100= 000 |UINT32|0x50000221 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000= 000 |UINT32|0x50000222 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000= 000 |UINT32|0x50000260 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040= 000 |UINT32|0x50000261 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000= 000 |UINT32|0x50000211 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100= 000 |UINT32|0x50000212 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x001000= 00 |UINT32|0x50000233 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x000000= 00 |UINT32|0x50000234 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x000000= 00 |UINT32|0x50000235 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100= 000 |UINT32|0x50000241 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000= 000 |UINT32|0x50000242 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100= 000 |UINT32|0x50000251 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000= 000 |UINT32|0x50000252 + + +# for Main FD + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff0= 0000 |UINT32|0x50000300 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x0040= 0000 |UINT32|0x50000301 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x0020= 0000 |UINT32|0x50000311 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF82= 0000 |UINT32|0x50000312 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x0020= 0000 |UINT32|0x50000341 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF82= 0000 |UINT32|0x50000342 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF82= 0000 |UINT32|0x50000343 + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x0020= 0000 |UINT32|0x50000351 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF82= 0000 |UINT32|0x50000352 + +## This PCD specifies the size of the physical device containing the BIOS,= SMBIOS will use it. + +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF80= 0000 |UINT32|0x50000001 +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x0000= 0000 |UINT32|0x50000002 + +[PcdsFeatureFlag.common] + +## +## Those PCDs are used to control build process. +## + + # + # SV Tools + # + gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000 + gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E + # + # + # + +[PcdsDynamicEx] + ### Sample implementation...No real data. Use this PCD to override a pla= tform with Interposer ### + gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x8000001= 5 { + + Guid/PlatformInfo.h + + WhitleyOpenBoardPkg/PlatformPkg.dec + } + # Interposer A MC 0 mapped to original MC1 + # Enum values for Interposer + # Interposer A =3D> 1 + # Interposer B =3D> 2 + # Interposer Unknown =3D> 0 + gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] = |1 + +### Sample implementation...No real data. Use this PCD to override a platf= orm with Interposer ### + +[Guids] + gStructPcdTokenSpaceGuid =3D {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x7= 4, 0x29, 0x1b, 0x36, 0x16, 0xf4}} + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURA= TION|0XFCD0000C{ + + Include/Guid/EmulationDfxVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION= |0XFCD00010{ + + Include/Guid/FpgaSocketVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFC= D00004{ + + Include/Guid/IeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFC= D0000B{ + + Include/Guid/MeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG= |0XFCD00002{ + + Include/Guid/MemBootHealthGuid.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{ + + Include/PchSetupVariableLbg.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFI= GURATION|0XFCD00001{ + + Include/Guid/SocketCommonRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0= XFCD00006{ + + Include/Guid/SocketIioVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURA= TION|0XFCD0000D{ + + Include/Guid/SocketMemoryVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGUR= ATION|0XFCD00008{ + + Include/Guid/SocketMpLinkVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMA= NAGEMENT_CONFIGURATION|0XFCD00005{ + + Include/Guid/SocketPowermanagementVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSOR= CORE_CONFIGURATION|0XFCD00003{ + + Include/Guid/SocketProcessorCoreVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD0000= 9{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFC= D0000A{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209 + gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A + +[LibraryClasses] + ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLi= b.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc new file mode 100644 index 0000000000..41dc55a14d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -0,0 +1,931 @@ +## @file +# X64 Platform with 64-bit DXE. +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D $(RP_PKG) + PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943DBC= FA61 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/$(RP_PKG) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + VPD_TOOL_GUID =3D 8C3D856A-9BE6-468E-850A-24F7A8D3= 8E08 + FLASH_DEFINITION =3D $(RP_PKG)/PlatformPkg.fdf + PLATFORM_SI_PACKAGE =3D ClientOneSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE =3D WhitleySiliconBinPkg + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE FSP_BIN_PKG =3D CedarIslandFspBinPkg + DEFINE IIO_INSTANCE =3D Skx +!elseif $(CPUTARGET) =3D=3D "ICX" + DEFINE FSP_BIN_PKG =3D WhitleyFspBinPkg + DEFINE IIO_INSTANCE =3D Icx +!else + DEFINE IIO_INSTANCE =3D UnknownCpu +!endif + + # + # Platform On/Off features are defined here + # + !include $(RP_PKG)/PlatformPkgConfig.dsc + + # + # MRC common configuration options defined here + # + !include $(SILICON_PKG)/MrcCommonConfig.dsc + + !include $(FSP_BIN_PKG)/DynamicExPcd.dsc + !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc + !include $(RP_PKG)/DynamicExPcd.dsc + + !include $(RP_PKG)/Uba/UbaCommon.dsc + !include $(RP_PKG)/Uba/UbaRpBoards.dsc + + !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure= .dsc + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + +[DefaultStores] + 0|STANDARD + 1|MANUFACTURING + + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFeatureFlag] + # + # MinPlatform control flags + # + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE + + # don't degrade 64bit MMIO space to 32-bit + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE + + # Server doesn't support capsule update on Reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE + + gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE + +!if ($(CPUTARGET) =3D=3D "ICX") + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE +!endif # $(CPUTARGET) =3D=3D "ICX" + + gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE + gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE + + ## Uncomment for better boot performance +# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE +# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE + + gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE + + ## This PCD specified whether ACPI SDT protocol is installed. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ## This PCD specifies whether FPGA routine will be active + gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE + gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE +!endif + + ## This PCD specifies whether or not to enable the High Speed UART + gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + +[PcdsFixedAtBuild] + gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2 + + ## MinPlatform Boot Stage Selector + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # = Enable asserts, prints, code, clear memory, and deadloops on asserts. + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # = Built in messages: Error, MTRR, info, load, warn, init + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # = This is set to INT3 (0x2) for Simics source level debugging + + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E= 49 # "INTEL ID" + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 + + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gCpuPkgTokenSpaceGuid.PcdPlatformType|2 + gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + + #PcdCpuMicrocodePatchRegionSize =3D PcdFlashNvStorageMicrocodeSize - (EF= I_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER)) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70 + + # + # This controls the NEM code region cached during SEC + # It usually isn't necessary to match exactly the FV layout in the FDF f= ile. + # It is a performance optimization to have it match the flash region exa= ctly + # as then no extra reads are done to load unused flash into cache. + # + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000 + +!if ($(FSP_MODE) =3D=3D 0) + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000 +!endif + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + + # + # These will be initialized during build + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000 + + ## Specifies delay value in microseconds after sending out an INIT IPI. + # @Prompt Configure delay value after send an INIT IPI + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 + + gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2 + + gPlatformTokenSpaceGuid.PcdUboDev|0x08 + gPlatformTokenSpaceGuid.PcdUboFunc|0x02 + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC + + gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE + gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE + + ## Defines the ACPI register set base address. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Timer IO Port Address + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500 + + ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. + # @Prompt ACPI Hardware PCI Bus Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 + + ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Device Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F + + ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Function Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 + + ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 + + ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. + # @Prompt ACPI Hardware PCI Bar Enable BitMask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 + + ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Bar Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 + + ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. + # @Prompt Offset to 32-bit Timer register in ACPI BAR + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + +!if $(CPUTARGET) =3D=3D "ICX" + # + # ACPI PCD custom override + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013 +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + + # Enable DDRT scheduler debug features for power on + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE + + # Disable Fast Warm Boot for Whitley Openboard Package + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE + gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE +!endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74 + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75 + + # + # PlatformInitPreMem + # + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0 + + !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc + +[PcdsFixedAtBuild.IA32] +!if ($(FSP_MODE) =3D=3D 0) + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000 + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0 +!endif + +[PcdsFixedAtBuild.X64] + # Change PcdBootManagerMenuFile to UiApp + ## + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + # + # AcpiPlatform + # + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE + + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, = 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00} + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, = 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF,= 0x04, 0x00} + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x= 1F, 0x0} + gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01 + +[PcdsPatchableInModule] + # + # These debug options are patcheable so that they can be manipulated dur= ing debug (if memory is updateable) + # + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # = Enable status codes for debug, progress, and errors + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # = Displayed messages: Error, Info, warn + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 + +!if $(PREMEM_PAGE_ALLOC_SUPPORT) =3D=3D FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000 +!endif + +[PcdsDynamicExDefault.IA32] +!if ($(FSP_MODE) =3D=3D 0) + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000 +!endif + + +[PcdsDynamicExHii] + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGene= ricVariableGuid|0x0|TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 # Variable: L"Timeout" + gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformT= okenSpaceGuid|0x0|0 + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatT= okenSpaceGuid|0x0|TRUE + gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVaria= bleGuid|0x0|TRUE + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScra= tchPad"|gEfiGenericVariableGuid|0x0|FALSE + +[PcdsDynamicExDefault] + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE + + gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 + + #Platform should change it to by code + gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22 + + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + + # + # CPU features related PCDs. + # + gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy + gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle + gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01 + + ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, = 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } } + ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, = 0x1b, 0x90, 0xcc } } + ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x= 75, 0x8b, 0x73, 0x17 } } + + #TPM2.0# + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} + + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE + + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522 + + gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C + gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011 + gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d } + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 + +[PcdsDynamicExDefault.X64] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + + # + # Set video to 1024x768 resolution + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + +[PcdsDynamicExDefault] + +!if $(CPUTARGET) =3D=3D "CPX" + !include $(RP_PKG)/StructurePcdCpx.dsc +!else + !include $(RP_PKG)/StructurePcd.dsc +!endif + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc + +[LibraryClasses] + + # + # Simics source level debugging requires the non-null version of PeCoffE= xtraActionLib + # +!if $(TARGET) =3D=3D "DEBUG" + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf +!endif + + # + # Basic + # + + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # + # Framework + # + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + + SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/= SiliconPolicyInitLibShim.inf +!if ($(FSP_MODE) =3D=3D 0) + SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLibFsp.inf +!else + SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLib.inf +!endif + + SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf + + # + # ToDo: Can we use BaseAcpiTimerLib from MinPlatform? + # + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + + MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSuppo= rtLib.inf + ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf + PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSync= LibNull/PlatformSetupVariableSyncLibNull.inf + PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/P= latformVariableHookLibNull.inf + + PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManage= rLib/DxePlatformBootManagerLib.inf + SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf + PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf + + CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf + PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCm= osAccessLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf + + # + # MinPlatform uses port 80, we don't want to assume HW + # + PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf + + TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull= .inf + Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN= ull.inf + AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLi= b.inf + PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/Pc= iSegmentInfoLibSimple.inf + PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/Plat= formOpromPolicyLibNull.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + +[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses= .Common.PEIM] +!if ($(FSP_MODE) =3D=3D 0) + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf + FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fs= pWrapperPlatformLib.inf + FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf +!endif + FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf + FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf + FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf + +[LibraryClasses.Common.SEC] + # + # SEC phase + # + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf + +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] + # + # ToDo: Can we remove + # + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuE= xceptionHandlerLib.inf + + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf + + + PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHookl= ib.inf + PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocks= Lib.inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestP= ointCheckLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + + ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf + +[LibraryClasses.Common.PEIM] + # + # Library instance consumed by MinPlatformPkg PlatformInit modules. + # + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/Repo= rtCpuHobLib.inf + SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, Lib= raryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClass= es.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryCla= sses.common.UEFI_APPLICATION] + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + + Tcg2PhysicalPresenceLib|$(RP_PKG)/Library/Tcg2PhysicalPresenceLibNull/Dx= eTcg2PhysicalPresenceLib.inf + TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe= TcgPhysicalPresenceLib.inf + + BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf + + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + + Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm= .inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Test= PointCheckLibNull.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.i= nf + BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/B= oardBootManagerLibNull.inf + + CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashComm= onLib.inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestP= ointCheckLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.= inf + +[LibraryClasses.Common.SMM_CORE] + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf + +[LibraryClasses.Common] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + +[Components.IA32] + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + # + # Beware of circular dependencies on PCD if you want to use another = DebugLib instance. + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf = # Include FSP DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLat= eSilicon.inf # Include FvLateSilicon DynamicEx PCD + } + $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf + $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf + $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf + + $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei= .inf + + $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf + $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf + BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf + } + $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf + + $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{ + + SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibN= ull/SiliconWorkaroundLibNull.inf + } + $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf + $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf + BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + } + +!if ($(FSP_MODE) =3D=3D 0) + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf +!endif + + $(RP_PKG)/BiosInfo/BiosInfo.inf + + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + + UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { + + !if $(PERFORMANCE_ENABLE) =3D=3D TRUE + TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerL= ibUefiCpu.inf + !endif + } + +[Components.X64] + !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc + + $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf + + MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf + + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf + + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + + $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf + $(PLATFORM_PKG)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + + $(PLATFORM_PKG)/Acpi/AcpiTables/AcpiPlatform.inf { + + BoardAcpiTableLib|$(RP_PKG)/Library/BoardAcpiLib/DxeBoardAcpiTableLi= b.inf + } + + $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf { + + BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnable= Lib.inf + } + + $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { + + BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf + } + $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf { +!if ($(FSP_MODE) =3D=3D 0) + + *_*_*_CC_FLAGS =3D -D FSP_API_MODE +!endif + } + + $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + + $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf + $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf + + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + + # + # SiliconPkg code for Platform Integration are defined here + # +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_CPX_SUPPORT =3D TRUE +!else + DEFINE CPU_CPX_SUPPORT =3D FALSE +!endif +[PcdsFixedAtBuild] +!if ($(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE) + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE +!endif +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, Libr= aryClasses.common.UEFI_APPLICATION] + ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.= inf +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSy= stemLib.inf + + +##########################################################################= ######################### +# +# BuildOptions Section - Define the module specific tool chain flags that = should be used as +# the default flags for a module. These flags are a= ppended to any +# standard flags that are defined by the build proc= ess. They can be +# applied for any modules or only those modules wit= h the specific +# module style (EDK or EDKII) specified in [Compone= nts] section. +# +##########################################################################= ######################### +[BuildOptions.Common.EDKII] +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D is= Replace) +!if $(CRB_FLAG_ENABLE) =3D=3D TRUE + DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG +!else + DEFINE CRB_EDKII_BUILD_OPTIONS =3D +!endif + +!if $(DEBUG_FLAGS_ENABLE) =3D=3D TRUE + DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D DEBUG_CODE_BLOCK=3D1 -D PLATFORM= _VARIABLE_ATTRIBUTES=3D0x3 +!else + DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D SILENT_MODE -D PLATFORM_VARIABLE= _ATTRIBUTES=3D0x3 +!endif + +!if $(SPARING_SCRATCHPAD_ENABLE) =3D=3D TRUE + DEFINE SPARING_SCRATCHPAD_OPTION =3D -D SPARING_SCRATCHPAD_SUPPORT +!else + DEFINE SPARING_SCRATCHPAD_OPTIONS =3D +!endif + +!if $(SCRATCHPAD_DEBUG) =3D=3D TRUE + DEFINE SCRATCHPAD_DEBUG_OPTION =3D -D SCRATCHPAD_DEBUG +!else + DEFINE SCRATCHPAD_DEBUG_OPTION =3D +!endif + +!if $(PCH_SERVER_BIOS_ENABLE) =3D=3D TRUE + DEFINE PCH_BUILD_OPTION =3D -DPCH_SERVER_BIOS_FLAG=3D1 +!else + DEFINE PCH_BUILD_OPTION =3D +!endif + +!if $(SERVER_BIOS_ENABLE) =3D=3D TRUE + DEFINE SERVER_BUILD_OPTION =3D -DSERVER_BIOS_FLAG=3D1 +!else + DEFINE SERVER_BUILD_OPTION =3D +!endif + +DEFINE SC_PATH =3D -D SC_PATH=3D"Pch/SouthClusterLbg" + +DEFINE ME_PATH =3D -D ME_PATH=3D"Me/MeSps.4" + +DEFINE IE_PATH =3D -D IE_PATH=3D"Ie/v1" + +DEFINE NVDIMM_OPTIONS =3D + +!if $(CPUTARGET) =3D=3D "ICX" + DEFINE CPU_TYPE_OPTIONS =3D -D ICX_HOST -D A0_HOST -D B0_HOST +!elseif $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_TYPE_OPTIONS =3D -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_H= OST -D B0_HOST +!endif + +DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS =3D -D MAX_SOCKET=3D$(MAX_SOCKET) -D= MAX_CORE=3D$(MAX_CORE) -D MAX_THREAD=3D$(MAX_THREAD) + +DEFINE MRC_OPTIONS =3D -D LRDIMM_SUPPORT -D DDRT_SUPPORT + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE + DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D4 -D MAX_MC_CH=3D2 +!else + DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D2 -D MAX_MC_CH=3D3 +!endif + +DEFINE MAX_SAD_RULE_OPTION =3D -D MAX_SAD_RULES=3D24 -D MAX_DRAM_CLUSTERS= =3D1 + +DEFINE LT_BUILD_OPTIONS =3D -D LT_FLAG + +DEFINE FSP_BUILD_OPTIONS =3D -D FSP_DISPATCH_MODE_ENABLE=3D1 + +# +# MAX_KTI_PORTS needs to be updated based on the silicon type +# +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D6 +!else + DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D3 +!endif + +DEFINE IIO_STACK_OPTIONS =3D -D MAX_IIO_STACK=3D6 -D MAX_LOGIC_IIO_STACK= =3D8 + +DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_= BUILD_OPTION) + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(CRB_EDKII_BUILD_OPTIONS) $(ED= KII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX= _SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $= (KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) = $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -= D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADD= RESS=3D0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP= _BUILD_OPTIONS) + +DEFINE IE_OPTIONS =3D $(IE_PATH) -DIE_SUPPORT=3D0 + +!if $(LINUX_GCC_BUILD) =3D=3D TRUE + DEFINE EDK2_LINUX_BUILD_OPTIONS =3D -D EDK2_CTE_BUILD +!else + DEFINE EDK2_LINUX_BUILD_OPTIONS =3D +!endif + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS) + +DEFINE ME_OPTIONS =3D -DSPS_VERSION=3D4 $(ME_PATH) + +DEFINE ASPEED_ENABLE_BUILD_OPTIONS =3D -D ASPEED_ENABLE -D ESPI_ENABLE + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS) + + MSFT:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819 + GCC:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + +# +# Enable source level debugging for RELEASE build +# +!if $(TARGET) =3D=3D "RELEASE" + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D + + MSFT:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi + MSFT:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7 + MSFT:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /= DEBUG + GCC:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) + GCC:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) +!endif + +# +# Override ASL Compiler parameters in tools_def.template. +# + MSFT:*_*_*_ASL_PATH =3D=3D $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/= iasl.exe + GCC:*_*_*_ASL_PATH =3D=3D $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/i= asl + *_*_*_ASL_FLAGS =3D=3D -vr -we -oi +# +# Override the VFR compile flags to speed the build time +# + +*_*_*_VFR_FLAGS =3D=3D -n + +# +# add to the build options for DXE/SMM drivers to remove the log message: +# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!! +# +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.D= XE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +[BuildOptions] + GCC:*_GCC5_*_CC_FLAGS =3D -Wno-overflow -Wno-discarded-qualifiers -Wno-u= nused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types= -mabi=3Dms + GCC:*_GCC5_IA32_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs + GCC:*_GCC5_X64_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs + MSFT:*_*_*_CC_FLAGS =3D /FAsc diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf new file mode 100644 index 0000000000..927db9e210 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf @@ -0,0 +1,827 @@ +## @file +# FDF file of platform with 64-bit DXE +# This package provides platform specific modules and flash layout informa= tion. +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +DEFINE PLATFORM_PKG =3D MinPlatformPkg + +# 0x00000060 =3D (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_F= FS_FILE_HEADER)) +DEFINE FDF_FIRMWARE_HEADER_SIZE =3D 0x00000060 + +DEFINE MICROCODE_HEADER_SIZE =3D 0x00000090 + +DEFINE VPD_HEADER_SIZE =3D 0x00000090 + +!if $(FSP_MODE) =3D=3D 0 + DEFINE FSP_BIN_DIR =3D Api +!else + DEFINE FSP_BIN_DIR =3D Dispatch +!endif + +# +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTo= kenSpaceGuid space, and for +# Others should be examined with an effort to work toward thi= s guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. + + +# +# 16MiB Total FLASH Image (visible in memory mapped IO) +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFF000000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x01000000 + +##########################################################################= ###### +# +# FD SECPEI +# +# Contains all the SEC and PEI modules +# +# Layout: (Low address to high address) +# +# FvBsp for board specific components +# FvPostMemory for compressed post memory MinPlatform spec required co= mponents +# FvFspS for compressed post memory silicon initialization components +# FvPostMemorySilicon for silicon components +# FvFspM for pre memory silicon initialization components +# FvPreMemorySilicon for silicon components +# FvFspT for temp RAM silicon initilization components +# FvBspPreMemory for board specific components required to intialize m= emory +# FvAdvancedPreMemory FV for advanced features components +# FvPreMemory for components required by MinPlatform spec and to initi= alize memory +# FvPreMemorySecurity FV for stage 6 required components +# Contains reset vector +# +##########################################################################= ###### + +[FD.SecPei] + BaseAddress =3D 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiBase #The base address of the FLASH Device + Size =3D 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiSize #The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x360 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # At this time, the FSP FV must be aligned at the same address they were= built to, 0xFFD00000 + # This will be corrected in the future. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x0004= 0000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x0022= 1000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x0000= 6000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D 0x0000= 1000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize -= gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSiz= e - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D 0x00= 000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvBspSize + FV =3D FvBsp + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvPostMemorySize + FV =3D FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspSSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_S.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspMSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_M.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspTSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_T.fd + + # + # Shared FV layout + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + FV =3D FvBspPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize + FV =3D FvPreMemory + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D gCpP= latFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Set duplicate PCD + # These should not need to be changed + # + + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemoryBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemorySize + + # + # For FSP Dispatch Mode, specify the FV containing the PEI core. + # + !if $(FSP_MODE) =3D=3D 1 + # + # Tell SEC to use PEI Core from outside FSP for additional debug messa= ge control. + # + SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase + !endif + + # + # For API mode, wrappers have some duplicate PCD as well + # + !if $(FSP_MODE) =3D=3D 0 + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspTBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspSBase + !endif + +##########################################################################= ###### +# +# FD Main +# +# All DXE modules and other regions +# +# Layout: (Low address to high address) +# +# FvAdvanced for advanced feature components +# Assorted advanced feature FV +# FvSecurity for MinPlatform spec required components needed to boot s= ecurely +# FvOsBoot for MinPlatform spec required components needed to boot OS +# FvLateSilicon for silicon specific components +# FvUefiBoot for MinPlatform spec required components needed to boot t= o UEFI shell +# +##########################################################################= ###### +[FD.Main] + BaseAddress =3D 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainBase # The base address of the FLASH Device + Size =3D 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainSize # The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x9C0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # These are out of flash layout order because FvAdvanced gets any remain= ing space + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x0001= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x0023= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x0004= C000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x0000= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvAdvancedSize + FV =3D FvAdvanced + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvSecuritySize + FV =3D FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvOsBootSize + FV =3D FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvUefiBootSize + FV =3D FvUefiBoot + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvOsBootSize + +##########################################################################= ###### +# +# FD BINARY +# +# Contains the OPROM and other binary modules +# +# Layout: (Low address to high address) +# +# FvOpRom containing pre-built components +# FvAcmRegion containing ACM related content +# FV Header + Blank Space (1K) +# Policy block (3K) +# Blank space to align ACM on 64K boundary (60K) +# ACM binary +# FvMicrocode containing microcode update patches +# Unformatted region for PCI Gen 3 Data +# FvVpd containing PCD VPD data +# FvWhea for WHEA data recording +# FvNvStorageVariable for UEFI Variable storage +# FvNvStorageEventLog for NV Store management +# FvNvStorageFtwWorking for Fault Tolerant Write solution +# FvNvStorageFtwSpare for Fault Tolerant Write solution +# +##########################################################################= ###### +[FD.Binary] + BaseAddress =3D 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= aryBase + Size =3D 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= arySize + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2E0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize =3D = 0x00100000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize =3D = 0x00050000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D = 0x000D0000 + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize =3D = 0x00010000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize =3D = 0x00030000 + # + # These four items are tightly coupled. + # The spare area size must be >=3D the first three areas. + # + # There isn't really a benefit to a larger spare area unless the FLASH d= evice + # block size is larger than the size specified. + # + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D = 0x0003C000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlash= TokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceG= uid.PcdFlashNvStorageFtwWorkingSize + + # + # Calculate Offsets Once (You should not need to modify this section) + # Each offset is the prior region's offset plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = =3D 0x00000000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlat= formModuleTokenSpaceGuid.PcdFlashFvVpdSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically + # + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + $(MICROCODE_HE= ADER_SIZE) + + # + # FV Layout (You should not need to modify this section) + # + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceG= uid.PcdFlashFvOpromSize + FV =3D FvOprom + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSp= aceGuid.PcdFlashFvAcmRegionSize + FV =3D FvAcm + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvMicrocodeSize + FV =3D FvMicrocode + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSp= aceGuid.PcdFlashFvVpdSize + FV =3D FvVPD + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGu= id.PcdFlashFvWheaSize + FV =3D FvWhea + + # + # Do not modify. + # See comments in size discussion above. These four areas are tightly c= oupled and should be modified with utmost care. + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatF= lashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + + # + # Calculate base addresses (You should not need to modify this section) + # Each base is the prior region's base plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromOffset + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress =3D = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE) + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatform= ModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE) + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvWheaSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # ACM details + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize =3D 0x3000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize =3D 0x000400= 00 + + # + # Other duplicate PCD + # + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFla= shFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize =3D gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + +##########################################################################= ###### +# +# FD FPGA +# +# Contains the FPGA modules +# +##########################################################################= ###### + +[FD.Fpga] + BaseAddress =3D 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aBase #The base address of the FPGA Device ( 4G - 48M ) + Size =3D 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aSize #The size in bytes of the FPGA Device ( 32M ) + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2000 + + 0x00000000|0x02000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpac= eGuid.PcdFlashFvFpgaBbsSize + FV =3D FvFpga + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvSecurityPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 40ab290f-8494-41cf-b302-31b178b4ce0b + +[FV.FvPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + + FILE SEC =3D 1BA0062E-C779-4582-8566-336AE8F78F09 { + SECTION UI =3D "SecCore" + SECTION VERSION =3D "1.0" + SECTION Align =3D 16 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/1BA0062E-C779-4582-8566-336AE8F78F09SecCore.efi + SECTION Align =3D 16 RAW =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)= /ResetVec.bin + } + INF MdeModulePkg/Core/Pei/PeiMain.inf + + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusC= odeRouterPei.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHa= ndlerPei.inf + + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.= inf + + INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf + + FILE PEIM =3D 0043A734-CB11-4274-B363-E165F958CB5F { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/0043A7= 34-CB11-4274-B363-E165F958CB5FMultiPch.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/0043A734-CB11-4274-B363-E165F958CB5FMultiPch.efi + SECTION UI =3D "MultiPch" + } + + FILE PEIM =3D ac4b7f1b-e057-47d3-b2b5-1137493c0f38 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f= 1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi + SECTION UI =3D "DynamicSiLibraryPei" + } + + INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/Platform= VariableInitPei.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPla= tformInit.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf + + # + # UBA common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf + + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + + FILE PEIM =3D ca8efb69-d7dc-4e94-aad6-9fb373649161 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb= 69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi + SECTION UI =3D "SiliconPolicyInitPreAndPostMem" + } + + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePreMemory.fdf + + INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerTo= SvidMap.inf + + INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + !if $(FSP_MODE) =3D=3D 0 + FILE PEIM =3D 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F= 3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi + SECTION UI =3D "CsrPseudoOffsetInitPeim" + } + FILE PEIM =3D 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6C= ACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi + SECTION UI =3D "RegAccessPeim" + } + FILE PEIM =3D C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9= BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi + SECTION UI =3D "SiliconDataInitPeim" + } + INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf + !endif + + FILE FV_IMAGE =3D 40ab290f-8494-41cf-b302-31b178b4ce0b { + SECTION FV_IMAGE =3D FvSecurityPreMemory + } + +[FV.FvAdvancedPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 + +[FV.FvBspPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e6c65995-8c2d-4119-a52d-7dbf1acb45a1 + + FILE FV_IMAGE =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 { + SECTION FV_IMAGE =3D FvAdvancedPreMemory + } + +# +# FvPostMemory includes common hardware, common core variable services, lo= ad and invoke DXE etc +# +[FV.FvPostMemoryUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA + +[FV.FvPostMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 3298afc4-c484-47f1-a65a-5917a54b5e8c + + FILE FV_IMAGE =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvPostMemoryUncompressed + } + } + +# +# FvBsp includes board specific components +# +[FV.FvBspUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e4c65347-fd90-4143-8a41-113e1015fe07 + +[FV.FvBsp] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 9e151cf3-ca90-444f-b33b-a9941cbc772f + + FILE FV_IMAGE =3D e4c65347-fd90-4143-8a41-113e1015fe07 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvBspUncompressed + } + } + +[FV.FvUefiBootUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 + + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.= inf + INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDx= e.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDx= e.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + #ATA for IDE/AHCI/RAID support + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestD= xe.inf + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + +[FV.FvUefiBoot] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D ab9fe87b-1e37-440c-91cc-9aea03ce7bec + + FILE FV_IMAGE =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompressed + } + } + +[FV.FvOsBootUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + # + # DXE Phase modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf + + FILE FV_IMAGE =3D B7C9F0CB-15D8-26FC-CA3F-C63947B12831 { + SECTION UI =3D "FvLateSilicon" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateS= ilicon.fv + } + + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePostMemory.fdf + + # + # UBA DXE common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf + !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf + INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + + !if ($(FSP_MODE) =3D=3D 1) + INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf + !else + INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + !endif + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + FILE FV_IMAGE =3D a0277d07-a725-4823-90f9-6cba00782111 { + SECTION UI =3D "FvLateOpenBoard" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateO= penBoard.fv + } + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterR= untimeDxe.inf + INF RuleOverride =3D UI MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV. + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF ShellPkg/Application/Shell/Shell.inf + + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeR= outerSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.i= nf + + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf + + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBu= fferDxe.inf + + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecuto= rDxe.inf + + # UEFI USB stack + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + + INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +[FV.FvOsBoot] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D c7488640-5f51-4969-b63b-89fc369e1725 + + FILE FV_IMAGE =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompressed + } + } + +[FV.FvSecuritySilicon] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D AD262F8D-BDED-4668-A8D4-8BC73516652F + +[FV.FvSecurityUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 + + FILE FV_IMAGE =3D 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecuritySilicon + } + } + +[FV.FvSecurity] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 68134833-2ff6-4d22-973b-575d0eae8ffd + + FILE FV_IMAGE =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityUncompressed + } + } + +[FV.FvAdvancedUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 70aeaf57-4997-49ce-a4f7-122980745670 + +[FV.FvAdvanced] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D f21ee7a1-53a9-453d-aee3-b6a5c25bada5 + + FILE FV_IMAGE =3D 70aeaf57-4997-49ce-a4f7-122980745670 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedUncompressed + } + } + +# +# FV for all Microcode Updates. +# +[FV.FvMicrocode] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D D2C29BA7-3809-480F-9C3D-DE389C61425A + +!if $(CPUTARGET) =3D=3D "CPX" + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/M= icrocodeUpdates.inf +!else + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/M= icrocodeUpdates.inf +!endif + + +[FV.FvVPD] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D FFC29BA7-3809-480F-9C3D-DE389C61425A + FILE RAW =3D FF7DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-= 850A-24F7A8D38E08.bin + } + +# +# Various Vendor UEFI Drivers (OROMs). +# +[FV.FvOpromUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 + +[FV.FvOprom] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD + + FILE FV_IMAGE =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOpromUncompressed + } + } + +[FV.FvWhea] + BlockSize =3D 0x1000 + NumBlocks =3D 0x30 + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D d6a1cd70-4b33-4994-a6ea-375f2ccc5437 + +# +# FV For ACM Binary. +# +[FV.FvAcm] + BlockSize =3D 0x1000 + NumBlocks =3D 0x50 + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 11668261-8A8D-47ca-9893-052D24435E59 + +[FV.FvFpga] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 974650E7-6DFE-4998-A124-CEDEC5C9B47D + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc b/Pla= tform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc new file mode 100644 index 0000000000..ecfdb895ba --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc @@ -0,0 +1,45 @@ +## @file +# platform configuration file for DEBUG build. +# +# @copyright +# Copyright 2011 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +DEFINE CRB_FLAG_ENABLE =3D TRUE +DEFINE DEBUG_FLAGS_ENABLE =3D FALSE + +DEFINE PERFORMANCE_ENABLE =3D TRUE + +DEFINE SERVER_BIOS_ENABLE =3D TRUE +DEFINE PCH_SERVER_BIOS_ENABLE =3D TRUE + +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_SKX_ONLY_SUPPORT =3D TRUE +!else + DEFINE CPU_SKX_ONLY_SUPPORT =3D FALSE +!endif + +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_CPX_SUPPORT =3D TRUE +!else + DEFINE CPU_CPX_SUPPORT =3D FALSE +!endif + +DEFINE RAS_CPU_ONLINE_OFFLINE_ENABLE =3D FALSE + +DEFINE SPARING_SCRATCHPAD_ENABLE =3D TRUE +DEFINE SCRATCHPAD_DEBUG =3D TRUE + +DEFINE TPM2_ENABLE =3D FALSE + +DEFINE ME_PATH_CONFIG =3D Me/MeSps.4 + +DEFINE SECURE_BOOT_ENABLE =3D FALSE + +DEFINE PLATFORMX64_ENABLE =3D TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform= /Intel/WhitleyOpenBoardPkg/StructurePcd.dsc new file mode 100644 index 0000000000..e356c917fe --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc @@ -0,0 +1,8553 @@ +## @file +# @copyright +# Copyright 2019 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + VPD_TOOL_GUID =3D 8C3D856A-9BE6-468E-850A-24F7A8D38E08 + +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + +[DefaultStores] + 0|STANDARD # UEFI Standard default 0|STANDARD is reserved. + 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is r= eserved. + +[PcdsDynamicExVpd.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|* + +[PcdsDynamicExHii.common.DEFAULT.STANDARD] +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|L"FpgaSocketConfig"|gFpgaSock= etVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdPchSetup|L"PchSetup"|gPchSetupVariableGuid|0x0= 0||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSetup|L"Setup"|gEfiSetupVariableGuid|0x00||NV,= BS, RT +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|L"SocketCommonRcConfig"|g= EfiSocketCommonRcVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketIioConfig|L"SocketIioConfig"|gEfiSocketI= ioVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|L"SocketMemoryConfig"|gEfiS= ocketMemoryVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|L"SocketMpLinkConfig"|gEfiS= ocketMpLinkVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|L"SocketPowerManag= ementConfig"|gEfiSocketPowermanagementVarGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|L"SocketProcessorCor= eConfig"|gEfiSocketProcessorCoreVarGuid|0x00||NV, BS, RT + +!if $(TARGET) =3D=3D "DEBUG" +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x4 +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x8 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0xF +!else +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x0 +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0x0 +!endif + +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxHybridSystemLevelEmulati= on|0x0 # Hybrid SLE Mode +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxPmMsrTrace|0x0 = # MSR Trace for PM +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxUbiosGeneration|0x0 = # uBIOS Generation +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSetupEnabled|0x3 = # Sockets Enable Bitmap(Hex) +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[0]|0x0 = # Socket 0 BitStream +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[1]|0x0 = # Socket 1 BitStream +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[0]|0x5a = # Socket 0 Threshold 1 +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[1]|0x5a = # Socket 1 Threshold 1 +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[0]|0x5d = # Socket 0 Threshold 2 +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[1]|0x5d = # Socket 1 Threshold 2 +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeDidEnabled|0x1 = # DRAM Init Done Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci1Enabled|0x0 = # HECI-1 Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci2Enabled|0x0 = # HECI-2 Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci3Enabled|0x0 = # HECI-3 Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeIderEnabled|0x0 = # IDER Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeKtEnabled|0x0 = # KT Enable +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemId|0x7270 = # Subsystem ID +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemVendorId|0x8086 = # Subsystem Vendor ID +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraRequest|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraTimeout|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxHotKeyPressed|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxSelectionScreen|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Amt|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Asf|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosPause|0x1 = # BIOS Pause Before Booting Capability State +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosReflash|0x1 = # BIOS Reflash Capability State +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosSetup|0x1 = # BIOS Boot to Setup Capability State +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BreakRtcEnabled|0x0 = # Break RTC Configuration +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CLINKDisableOverride|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CoreBiosDoneEnabled|0x1 = # Core Bios Done Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CpuTypeEmulation|0xa +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationModeOve= rride|0x0 # Delayed Authentication Mode (DAM) Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationMode|0x= 0 # Delayed Authentication Mode (DAM) +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DidInitStat|0x0 = # DRAM Initialization Status +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DisableD0I3SettingForHeci|0x= 0 # D0I3 Setting for HECI Disable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.EndOfPostMessage|0x2 = # END_OF_POST Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication2|0x2 = # HECI-2 Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication3|0x2 = # HECI-3 Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication|0x2 = # HECI-1 Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.FWProgress|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[0]|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[1]|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HideUnConfigureMeConfirm|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HostResetNotification|0x1 = # Host Reset Warning +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HsioMessagingEnabled|0x0 = # Enable HSIO Messaging +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccClkOverride|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccProfile|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.KtDeviceEnable|0x2 = # KT Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.LocalFwUpdEnabled|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MdesCapability|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeEnableHeciTraces|0x0 = # Enable HECI Dump +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFirmwareMode|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFwDowngrade|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrLockEnabled|0x1 = # Global Reset Lock +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrPromotionEnabled|0x0 = # CF9 global reset promotion +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci1HideInMe|0x0 = # HECI-1 Hide in ME +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci2HideInMe|0x0 = # HECI-2 Hide in ME +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci3HideInMe|0x0 = # HECI-3 Hide in ME +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoEnableEnabled|0x0 = # HMRFPO_ENABLE Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoLockEnabled|0x1 = # HMRFPO_LOCK Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeIderEnabled|0x2 = # IDEr Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeImageType|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttEnabled|0x0 = # PTT Support +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSupported|0x0 = # ME PTT Supported +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSuppressCommandSend|0x0= # Suppress PTT Commands +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeRegionSelectEnabled|0x0 = # REGION_SELECT Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeStateControl|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeTimeout|0x2 = # ME Initialization Complete Timeout +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeType|0xee = # ME Firmware Type +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeWatchdogControlEnabled|0x1= # WATCHDOG_CONTROL Message +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxDebugMsg|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxGraphicsMode|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxNonUiTextMode|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxUiTextMode|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MngState|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2DisableOverride|0x0 = # Cores Disable Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2Disable|0x0 = # Cores To Disable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeOverride|0x0 = # Hardware Change Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeStatus|0x0 = # Hardware Changed +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtOverride|0x0 = # Power Measurement Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtSupport|0x0 = # Power Measurement +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPtuLoadOverride|0x0 = # PTU Load Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBootOverride|0x0 = # Boot Mode Override +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBoot|0x0 = # Boot Mode +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.PreDidMeResetEnabled|0x0 = # Pre-DramInitDone ME Reset +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RegLock|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RemoteSessionActive|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SecureBootExposureToFw|0x1 = # BIOS Secure Boot Capability Exposure to FW State +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[0]|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[1]|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SendDidMsg|0x1 = # DRAM Init Done Enable +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsAltitude|0x8000 = # Altitude +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsMctpBusOwner|0x0 = # MCTP Bus Owner +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[0]|0x58 = # PSU #1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[1]|0x59 = # PSU #2 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[2]|0x0 = # PSU #3 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[3]|0x0 = # PSU #4 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.USBProvision|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.UnConfigureMe|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.VproAllowed|0x1 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogOs|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerBios|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerOs|0x0 +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDog|0x0 +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayLeftEdge= |0x2 # RxDqsDelay Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayRightEdg= e|0x2 # RxDqsDelay Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefLeftEdge|0x2= # RxVref Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefRightEdge|0x= 2 # RxVref Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayLeftEdge|= 0x2 # TxDqDelay Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayRightEdge= |0x2 # TxDqDelay Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefLeftEdge|0x2= # TxVref Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefRightEdge|0x= 2 # TxVref Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.MemBootHealthCheck|0x2 = # Memory Boot Health Check +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.ResetOnCriticalError|0x1 = # Reboot On Critical Failure +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayLeftEdge|= 0x5 # RxDqsDelay Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayRightEdge= |0x5 # RxDqsDelay Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefLeftEdge|0x5 = # RxVref Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefRightEdge|0x5= # RxVref Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayLeftEdge|0= x5 # TxDqDelay Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayRightEdge|= 0x5 # TxDqDelay Right Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefLeftEdge|0x5 = # TxVref Left Edge +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefRightEdge|0x5= # TxVref Right Edge +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrCpuThermalWdt|0x0 = # CPU Thermal WDT ADR Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrGpioSel|0x0 = # ADR GPIO +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrHostPartitionReset|0x0 = # Host Partition Reset ADR Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrMultiplierVal|0x63 = # ADR timer multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrOverClockingWdt|0x0 = # Over-Clocking WDT ADR Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrPmcParityError|0x0 = # PMC Parity Error ADR Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrSysPwrOk|0x0 = # SYS_PWROK Failure ADR Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerEn|0x0 = # Enable/Disable ADR Timer +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerVal|0x4 = # ADR timer expire time +gStructPcdTokenSpaceGuid.PcdPchSetup.AetEnableMode|0x0 = # AET Enable Mode +gStructPcdTokenSpaceGuid.PcdPchSetup.Btcg|0x1 = # Trunk Clock Gating (BTCG) +gStructPcdTokenSpaceGuid.PcdPchSetup.DciEn|0x0 = # DCI enable (HDCIEN) +gStructPcdTokenSpaceGuid.PcdPchSetup.DeepSxMode|0x0 = # DeepSx Power Policies +gStructPcdTokenSpaceGuid.PcdPchSetup.DfxHdaVcType|0x0 = # Virtual Channel for HD Audio +gStructPcdTokenSpaceGuid.PcdPchSetup.DmiLinkDownHangBypass|0x0 = # DMI Link Down Hang Bypass (DLDHB) +gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_IEWDT|0x0 = # IE FW Watchdog Timer +gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_MEWDT|0x0 = # ME FW Watchdog Timer +gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_PMCGBL|0x1 = # Host Reset Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_BmcRootPort|0x5 = # BMC RootPort +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Enable|0x0 = # Dirty Warm Reset +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x1 = # IE Reset Prep Done +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x1 = # ME Reset Prep Done +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Stall|0x0 = # Dirty Warm Reset Stall +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableClockSpreadSpec|0x1 = # External SSC Enable - CK420 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[0]|0x0 = # USB 3.0 pin #1 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[1]|0x0 = # USB 3.0 pin #2 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[2]|0x0 = # USB 3.0 pin #3 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[3]|0x0 = # USB 3.0 pin #4 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[4]|0x0 = # USB 3.0 pin #5 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[5]|0x0 = # USB 3.0 pin #6 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[6]|0x0 = # USB 3.0 pin #7 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[7]|0x0 = # USB 3.0 pin #8 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[8]|0x0 = # USB 3.0 pin #9 +gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[9]|0x0 = # USB 3.0 pin #10 +gStructPcdTokenSpaceGuid.PcdPchSetup.FirmwareConfiguration|0x0 = # Firmware Configuration +gStructPcdTokenSpaceGuid.PcdPchSetup.FlashLockDown|0x0 = # Flash Lock-Down +gStructPcdTokenSpaceGuid.PcdPchSetup.GbeRegionInvalid|0x0 = # Gbe Region Valid +gStructPcdTokenSpaceGuid.PcdPchSetup.Gp27WakeFromDeepSx|0x0 = # GP27 Wake From DeepSx +gStructPcdTokenSpaceGuid.PcdPchSetup.IchPort80Route|0x0 = # Port 80h Redirection +gStructPcdTokenSpaceGuid.PcdPchSetup.PchAdrEn|0x0 = # Enable/Disable ADR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchAllUnLock|0x0 = # Unlock All PCH registers +gStructPcdTokenSpaceGuid.PcdPchSetup.PchBiosLock|0x1 = # BIOS Lock +gStructPcdTokenSpaceGuid.PcdPchSetup.PchCrossThrottling|0x1 = # PCH Cross Throttling +gStructPcdTokenSpaceGuid.PcdPchSetup.PchDciAutoDetect|0x0 = # DCI Auto Detect Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaLockDown|0x1 = # EVA registers LOCK +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom0HookEnable|0x1 = # MROM 0 Hook +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom1HookEnable|0x1 = # MROM 1 Hook +gStructPcdTokenSpaceGuid.PcdPchSetup.PchGpioLockDown|0x1 = # GPIO Lockdown +gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudio|0x1 = # Azalia +gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioCodecSelect|0x0 = # HDA-Link Codec Select +gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioPme|0x0 = # Azalia PME Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchIoApic24119Entries|0x1 = # IO-APIC 24-119 RTE +gStructPcdTokenSpaceGuid.PcdPchSetup.PchLanK1Off|0x0 = # K1 off +gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbDevReveal|0x0 = # Reveal PCH P2SB device +gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbUnlock|0x0 = # Unlock PCH P2SB +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[0]|0x0 = # Force LTR Override PCIE1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[1]|0x0 = # Force LTR Override PCIE2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[2]|0x0 = # Force LTR Override PCIE3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[3]|0x0 = # Force LTR Override PCIE4 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[4]|0x0 = # Force LTR Override PCIE5 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[5]|0x0 = # Force LTR Override PCIE6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[6]|0x0 = # Force LTR Override PCIE7 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[7]|0x0 = # Force LTR Override PCIE8 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[8]|0x0 = # Force LTR Override PCIE9 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[9]|0x0 = # Force LTR Override PCIE10 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[10]|0x0 = # Force LTR Override PCIE11 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[11]|0x0 = # Force LTR Override PCIE12 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[12]|0x0 = # Force LTR Override PCIE13 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[13]|0x0 = # Force LTR Override PCIE14 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[14]|0x0 = # Force LTR Override PCIE15 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[15]|0x0 = # Force LTR Override PCIE16 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[16]|0x0 = # Force LTR Override PCIE17 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[17]|0x0 = # Force LTR Override PCIE18 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[18]|0x0 = # Force LTR Override PCIE19 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[19]|0x0 = # Force LTR Override PCIE20 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieGlobalAspm|0x2 = # PCI-E ASPM Support (Global) +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[0]|0x1 = # PCH PCIE1 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[1]|0x1 = # PCH PCIE2 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[2]|0x1 = # PCH PCIE3 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[3]|0x1 = # PCH PCIE4 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[4]|0x1 = # PCH PCIE5 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[5]|0x1 = # PCH PCIE6 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[6]|0x1 = # PCH PCIE7 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[7]|0x1 = # PCH PCIE8 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[8]|0x1 = # PCH PCIE9 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[9]|0x1 = # PCH PCIE10 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[10]|0x1 = # PCH PCIE11 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[11]|0x1 = # PCH PCIE12 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[12]|0x1 = # PCH PCIE13 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[13]|0x1 = # PCH PCIE14 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[14]|0x1 = # PCH PCIE15 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[15]|0x1 = # PCH PCIE16 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[16]|0x1 = # PCH PCIE17 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[17]|0x1 = # PCH PCIE18 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[18]|0x1 = # PCH PCIE19 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[19]|0x1 = # PCH PCIE20 LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[0]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[1]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[2]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[3]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[4]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[5]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[6]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[7]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[8]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[9]= |0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[10= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[11= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[12= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[13= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[14= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[15= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[16= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[17= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[18= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[19= ]|0x2 # Non Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[0]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[1]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[2]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[3]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[4]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[5]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[6]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[7]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[8]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[9]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[10]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[11]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[12]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[13]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[14]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[15]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[16]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[17]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[18]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[19]|0x2 # Non Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[0= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[2= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[3= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[4= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[5= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[6= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[7= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[8= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[9= ]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 0]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 1]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 2]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 3]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 4]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 5]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 6]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 7]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 8]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 9]|0x3c # Non Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[0]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[1]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[2]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[3]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[4]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[5]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[6]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[7]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[8]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[9]|0x= 2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[10]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[11]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[12]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[13]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[14]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[15]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[16]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[17]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[18]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[19]|0= x2 # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [0]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [1]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [2]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [3]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [4]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [5]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [6]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [7]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [8]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [9]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [10]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [11]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [12]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [13]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [14]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [15]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [16]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [17]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [18]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [19]|0x2 # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[0]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[1]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[2]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[3]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[4]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[5]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[6]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[7]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[8]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[9]|0= x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[10]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[11]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[12]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[13]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[14]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[15]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[16]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[17]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[18]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[19]|= 0x3c # Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16CompletionTimeout|0x0 = # CTO for Uplink x16 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16MaxPayloadSize|0x2 = # MPL for Uplink x16 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8CompletionTimeout|0x0 = # CTO for Uplink x8 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8MaxPayloadSize|0x2 = # MPL for Uplink x8 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchRtcLock|0x1 = # RTC Lock +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrConfigLock|0x1 = # sSATA LTR Lock +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrEnable|0x1 = # PCH sSATA LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrOverride|0x0 = # sSATA LTR Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideMultiplie= r|0x2 # sSATA Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideValue|0x2= 8 # sSATA Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSata|0x1 = # SATA Controller +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrConfigLock|0x1 = # SATA LTR Lock +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrEnable|0x1 = # PCH SATA LTR +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrOverride|0x0 = # SATA LTR Override +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideMultiplier= |0x2 # SATA Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideValue|0x28= # SATA Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSirqMode|0x0 = # Serial IRQ Mode +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSlpLanLowDc|0x1 = # SLP_LAN# Low on DC Power +gStructPcdTokenSpaceGuid.PcdPchSetup.PchThermalUnlock|0x0 = # Unlock Thermal Registers +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubHide|0x1 = # Hide Trace Hub +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg0Size|0x0 = # MemRegion 0 Buffer Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg1Size|0x0 = # MemRegion 1 Buffer Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMode|0x2 = # TraceHub Enable Mode +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbDegradeBar|0x0 = # Place XHCI BAR below 4GB +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[0]|0x1 = # USB HS Physical Connector #0 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[1]|0x1 = # USB HS Physical Connector #1 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[2]|0x1 = # USB HS Physical Connector #2 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[3]|0x1 = # USB HS Physical Connector #3 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[4]|0x1 = # USB HS Physical Connector #4 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[5]|0x1 = # USB HS Physical Connector #5 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[6]|0x1 = # USB HS Physical Connector #6 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[7]|0x1 = # USB HS Physical Connector #7 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[8]|0x1 = # USB HS Physical Connector #8 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[9]|0x1 = # USB HS Physical Connector #9 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[10]|0x1 = # USB HS Physical Connector #10 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[11]|0x1 = # USB HS Physical Connector #11 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[12]|0x1 = # USB HS Physical Connector #12 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[13]|0x1 = # USB HS Physical Connector #13 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbManualMode|0x0 = # XHCI Manual Mode +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbPerPortCtl|0x0 = # USB Per-Connector Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[0]|0x1 = # USB SS Physical Connector #0 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[1]|0x1 = # USB SS Physical Connector #1 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[2]|0x1 = # USB SS Physical Connector #2 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[3]|0x1 = # USB SS Physical Connector #3 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[4]|0x1 = # USB SS Physical Connector #4 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[5]|0x1 = # USB SS Physical Connector #5 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[6]|0x1 = # USB SS Physical Connector #6 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[7]|0x1 = # USB SS Physical Connector #7 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[8]|0x1 = # USB SS Physical Connector #8 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[9]|0x1 = # USB SS Physical Connector #9 Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PchWakeOnLan|0x0 = # Wake on LAN +gStructPcdTokenSpaceGuid.PcdPchSetup.PchsSata|0x1 = # sSATA Controller +gStructPcdTokenSpaceGuid.PcdPchSetup.PciDelayOptimizationEcr|0x0 = # PCI Delay Optimization +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieComplianceTestMode|0x0 = # Compliance Test Mode +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiExtSync|0x0 = # DMI Link Extended Synch Control +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiStopAndScreamEnable|0x0 = # Stop and Scream +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[0]|0x6 = # PCIE1 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[1]|0x6 = # PCIE2 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[2]|0x6 = # PCIE3 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[3]|0x6 = # PCIE4 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[4]|0x6 = # PCIE5 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[5]|0x6 = # PCIE6 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[6]|0x6 = # PCIE7 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[7]|0x6 = # PCIE8 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[8]|0x6 = # PCIE9 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[9]|0x6 = # PCIE10 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[10]|0x6 = # PCIE11 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[11]|0x6 = # PCIE12 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[12]|0x6 = # PCIE13 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[13]|0x6 = # PCIE14 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[14]|0x6 = # PCIE15 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[15]|0x6 = # PCIE16 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[16]|0x6 = # PCIE17 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[17]|0x6 = # PCIE18 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[18]|0x6 = # PCIE19 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[19]|0x6 = # PCIE20 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[0]|0x6 = # PCIE1 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[1]|0x6 = # PCIE2 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[2]|0x6 = # PCIE3 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[3]|0x6 = # PCIE4 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[4]|0x6 = # PCIE5 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[5]|0x6 = # PCIE6 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[6]|0x6 = # PCIE7 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[7]|0x6 = # PCIE8 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[8]|0x6 = # PCIE9 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[9]|0x6 = # PCIE10 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[10]|0x6 = # PCIE11 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[11]|0x6 = # PCIE12 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[12]|0x6 = # PCIE13 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[13]|0x6 = # PCIE14 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[14]|0x6 = # PCIE15 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[15]|0x6 = # PCIE16 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[16]|0x6 = # PCIE17 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[17]|0x6 = # PCIE18 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[18]|0x6 = # PCIE19 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[19]|0x6 = # PCIE20 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PciePllSsc|0xfe = # Pcie Pll SSC +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[0]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[1]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[2]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[3]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[4]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[5]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[6]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[7]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[8]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[9]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[10]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[11]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[12]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[13]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[14]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[15]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[16]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[17]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[18]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[19]|0x1 = # ACS +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[0]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[1]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[2]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[3]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[4]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[5]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[6]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[7]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[8]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[9]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[10]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[11]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[12]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[13]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[14]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[15]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[16]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[17]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[18]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[19]|0x1 = # Advanced Error Reporting +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[0]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[1]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[2]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[3]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[4]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[5]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[6]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[7]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[8]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[9]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[10]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[11]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[12]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[13]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[14]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[15]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[16]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[17]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[18]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[19]|0x0 = # PCIE ASPM +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[0]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[1]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[2]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[3]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[4]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[5]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[6]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[7]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[8]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[9]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[10]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[11]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[12]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[13]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[14]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[15]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[16]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[17]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[18]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[19]|0x0 = # CER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[0]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[1]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[2]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[3]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[4]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[5]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[6]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[7]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[8]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[9]|0x0 = # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[10]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[11]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[12]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[13]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[14]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[15]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[16]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[17]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[18]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[19]|0x0= # Compl. Timeout +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[0]|0x1 = # PCI Express Root Port 1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[1]|0x1 = # PCI Express Root Port 2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[2]|0x1 = # PCI Express Root Port 3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[3]|0x1 = # PCI Express Root Port 4 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[4]|0x1 = # PCI Express Root Port 5 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[5]|0x1 = # PCI Express Root Port 6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[6]|0x1 = # PCI Express Root Port 7 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[7]|0x1 = # PCI Express Root Port 8 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[8]|0x1 = # PCI Express Root Port 9 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[9]|0x1 = # PCI Express Root Port 10 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[10]|0x1 = # PCI Express Root Port 11 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[11]|0x1 = # PCI Express Root Port 12 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[12]|0x1 = # PCI Express Root Port 13 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[13]|0x1 = # PCI Express Root Port 14 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[14]|0x1 = # PCI Express Root Port 15 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[15]|0x1 = # PCI Express Root Port 16 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[16]|0x1 = # PCI Express Root Port 17 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[17]|0x1 = # PCI Express Root Port 18 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[18]|0x1 = # PCI Express Root Port 19 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[19]|0x1 = # PCI Express Root Port 20 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[0]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[1]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[2]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[3]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[4]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[5]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[6]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[7]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[8]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[9]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[10]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[11]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[12]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[13]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[14]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[15]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[16]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[17]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[18]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[19]|0x1 = # Gen3 Eq Phase3 Method +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[0]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[1]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[2]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[3]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[4]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[5]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[6]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[7]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[8]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[9]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[10]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[11]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[12]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[13]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[14]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[15]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[16]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[17]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[18]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[19]|0x0 = # FER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFunctionSwapping|0x1 = # PCIe Root Port Function Swapping +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[0]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[1]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[2]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[3]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[4]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[5]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[6]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[7]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[8]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[9]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[10]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[11]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[12]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[13]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[14]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[15]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[16]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[17]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[18]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[19]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[0]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[1]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[2]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[3]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[4]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[5]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[6]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[7]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[8]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[9]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[10]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[11]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[12]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[13]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[14]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[15]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[16]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[17]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[18]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[19]|0x3 = # L1 Substates +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[0]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[1]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[2]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[3]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[4]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[5]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[6]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[7]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[8]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[9]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[10]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[11]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[12]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[13]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[14]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[15]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[16]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[17]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[18]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[19]|0x1 = # Max Payload Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxReadRequestSize|0x5 = # Max Read Request Size +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[0]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[1]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[2]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[3]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[4]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[5]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[6]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[7]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[8]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[9]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[10]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[11]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[12]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[13]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[14]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[15]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[16]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[17]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[18]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[19]|0x0 = # NFER +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[0]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[1]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[2]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[3]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[4]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[5]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[6]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[7]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[8]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[9]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[10]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[11]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[12]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[13]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[14]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[15]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[16]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[17]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[18]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[19]|0x0 = # PME SCI +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSBDE|0x0 = # Subtractive Decode +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[0]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[1]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[2]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[3]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[4]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[5]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[6]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[7]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[8]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[9]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[10]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[11]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[12]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[13]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[14]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[15]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[16]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[17]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[18]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[19]|0x0 = # SECE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[0]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[1]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[2]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[3]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[4]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[5]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[6]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[7]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[8]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[9]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[10]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[11]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[12]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[13]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[14]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[15]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[16]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[17]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[18]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[19]|0x0 = # SEFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[0]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[1]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[2]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[3]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[4]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[5]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[6]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[7]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[8]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[9]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[10]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[11]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[12]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[13]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[14]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[15]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[16]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[17]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[18]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[19]|0x0 = # SENFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[0]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[1]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[2]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[3]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[4]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[5]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[6]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[7]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[8]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[9]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[10]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[11]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[12]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[13]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[14]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[15]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[16]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[17]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[18]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[19]|0x0 = # PCIe Speed +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[0]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[1]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[2]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[3]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[4]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[5]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[6]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[7]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[8]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[9]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[10]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[11]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[12]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[13]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[14]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[15]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[16]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[17]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[18]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[19]|0x0 = # URR +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSBDEPort|0x0 = # Subtractive Decode Port# +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[0]|0x6 = # Coeff0 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[1]|0x4 = # Coeff1 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[2]|0x8 = # Coeff2 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[3]|0x2 = # Coeff3 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[4]|0xa = # Coeff4 Cm +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[0]|0x2 = # Coeff0 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[1]|0x2 = # Coeff1 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[2]|0x2 = # Coeff2 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[3]|0x2 = # Coeff3 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[4]|0x2 = # Coeff4 Cp +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqOverride|0x0 = # Override SW/HW EQ settings +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[0]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[1]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[2]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[3]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[4]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[5]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[6]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[7]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[8]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[9]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[10]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[11]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[12]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[13]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[14]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[15]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[16]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[17]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[18]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[19]|0x0 = # PCIE Lane Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.PmcReadDisable|0x1 = # PMC Read Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.PxDevSlp[2]|0x0 = # SATA Port 2 DevSlp +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[0]|0x0 = # NVRAM CYCLE ROUTER 0 ENABLE +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[1]|0x0 = # NVRAM CYCLE ROUTER 1 ENABLE +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[2]|0x0 = # NVRAM CYCLE ROUTER 2 ENABLE +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[0]|0x0 = # NVRAM CR0 PCIE Root Port Number +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[1]|0x0 = # NVRAM CR1 PCIE Root Port Number +gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[2]|0x0 = # NVRAM CR2 PCIE Root Port Number +gStructPcdTokenSpaceGuid.PcdPchSetup.SataAlternateId|0x0 = # Alternate Device ID on RAID +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[0]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[1]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[2]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[3]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[4]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[5]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[6]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[7]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHddlk|0x1 = # SATA HDD Unlock +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[0]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[1]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[2]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[3]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[4]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[5]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[6]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[7]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.SataInterfaceMode|0x0 = # Configure SATA as +gStructPcdTokenSpaceGuid.PcdPchSetup.SataLedl|0x1 = # SATA Led locate +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[0]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[1]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[2]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[3]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[4]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[5]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[6]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[7]|0x0 = # Mechanical Presence Switch +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[0]|0x1 = # Port 0 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[1]|0x1 = # Port 1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[2]|0x1 = # Port 2 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[3]|0x1 = # Port 3 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[4]|0x1 = # Port 4 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[5]|0x1 = # Port 5 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[6]|0x1 = # Port 6 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[7]|0x1 = # Port 7 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIooe|0x1 = # IRRT Only on ESATA +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIrrt|0x1 = # Intel Rapid Recovery Technology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[0]|0x0 = # Load EFI Driver for RAID +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[1]|0x0 = # Load EFI Driver for RAID +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOromDelay|0x0 = # RAID OROM prompt delay +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOub|0x1 = # RAID Option ROM UI banner +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR0|0x1 = # RAID 0 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR1|0x1 = # RAID 1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR10|0x1 = # RAID 10 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR5|0x1 = # RAID 5 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidSrt|0x1 = # Smart Response Technology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSalp|0x1 = # Support Aggressive Link Power Management +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[0]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[1]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[2]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[3]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[4]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[5]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[6]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[7]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTestMode|0x0 = # SATA test mode +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[0]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[1]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[2]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[3]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[4]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[5]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[6]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[7]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[0]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[1]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[2]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[3]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[4]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[5]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[6]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[7]|0x0 = # SATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.ShutdownPolicySelect|0x1 = # Shutdown Policy +gStructPcdTokenSpaceGuid.PcdPchSetup.StateAfterG3|0x0 = # PCH state after G3 +gStructPcdTokenSpaceGuid.PcdPchSetup.TestDmiAspmCtrl|0x1 = # PCH DMI ASPM Testing +gStructPcdTokenSpaceGuid.PcdPchSetup.TestMctpBroadcastCycle|0x0 = # MCTP Broadcast Cycle +gStructPcdTokenSpaceGuid.PcdPchSetup.TestSmbusSpdWriteDisable|0x1 = # SPD Write Disable +gStructPcdTokenSpaceGuid.PcdPchSetup.ThermalDeviceEnable|0x3 = # PCH Thermal Device +gStructPcdTokenSpaceGuid.PcdPchSetup.Usb3PinsTermination|0x1 = # Enable USB 3.0 pins +gStructPcdTokenSpaceGuid.PcdPchSetup.UsbPrecondition|0x0 = # USB Precondition +gStructPcdTokenSpaceGuid.PcdPchSetup.XTpmLen|0x1 = # Expanded SPI TPM Transaction Length Enable +gStructPcdTokenSpaceGuid.PcdPchSetup.XhciDisMSICapability|0x0 = # USB XHCI MSI Disable WA +gStructPcdTokenSpaceGuid.PcdPchSetup.XhciIdleL1|0x1 = # XHCI Idle L1 +gStructPcdTokenSpaceGuid.PcdPchSetup.XhciOcMapEnabled|0x1 = # XHCI Over Current Pins +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataAlternateId|0x0 = # Alternate Device ID on RAID +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[0]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[1]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[2]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[3]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[4]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[5]|0x0 = # Configure as eSATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHddlk|0x1 = # SATA HDD Unlock +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[0]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[1]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[2]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[3]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[4]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[5]|0x0 = # Hot Plug +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataInterfaceMode|0x0 = # Configure sSATA as +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataLedl|0x1 = # SATA Led locate +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[0]|0x1 = # Port 0 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[1]|0x1 = # Port 1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[2]|0x1 = # Port 2 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[3]|0x1 = # Port 3 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[4]|0x1 = # Port 4 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[5]|0x1 = # Port 5 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIooe|0x1 = # IRRT Only on ESATA +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIrrt|0x1 = # Intel Rapid Recovery Technology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOromDelay|0x0 = # RAID OROM prompt delay +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOub|0x1 = # RAID Option ROM UI banner +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR0|0x1 = # RAID 0 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR1|0x1 = # RAID 1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR10|0x1 = # RAID 10 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR5|0x1 = # RAID 5 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidSrt|0x1 = # Smart Response Technology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSalp|0x1 = # Support Aggressive Link Power Management +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[0]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[1]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[2]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[3]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[4]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[5]|0x0 = # Spin Up Device +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTestMode|0x0 = # SATA test mode +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[0]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[1]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[2]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[3]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[4]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataTopology[5]|0x0 = # SATA Topology +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[0]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[1]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[2]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[3]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[4]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataType[5]|0x0 = # sSATA Device Type +gStructPcdTokenSpaceGuid.PcdSetup.AEPErrorInjEn|0x0 = # PMem Error Injection +gStructPcdTokenSpaceGuid.PcdSetup.ARIEnable|0x1 = # ARI Support +gStructPcdTokenSpaceGuid.PcdSetup.ARIForward|0x0 = # ARI Forward +gStructPcdTokenSpaceGuid.PcdSetup.AntiFlashWearoutSupported|0x0 = # Anti Flash Wearout Supported +gStructPcdTokenSpaceGuid.PcdSetup.ApplicationProfile|0xff = # Application Profile Configuration +gStructPcdTokenSpaceGuid.PcdSetup.BaudRate|0x5 +gStructPcdTokenSpaceGuid.PcdSetup.BiosGuardEnabled|0x0 = # BIOS Guard +gStructPcdTokenSpaceGuid.PcdSetup.BiosGuardPlatformSupported|0x0 = # Bios Guard Supported +gStructPcdTokenSpaceGuid.PcdSetup.BootAllOptions|0x0 = # Boot All Options +gStructPcdTokenSpaceGuid.PcdSetup.BootNetwork|0x0 = # Boot to Network +gStructPcdTokenSpaceGuid.PcdSetup.Ce2LmLoggingEn|0x1 = # 2LM Correctable Error Logging in m2mem +gStructPcdTokenSpaceGuid.PcdSetup.ClearViralStatus|0x0 = # Clear Viral Status +gStructPcdTokenSpaceGuid.PcdSetup.CloakDevHideRegistersOs|0x0 = # Cloak Devhide registers from being accessible fr= om OS +gStructPcdTokenSpaceGuid.PcdSetup.CloakingEn|0x0 = # System Cloaking +gStructPcdTokenSpaceGuid.PcdSetup.ClrExtraTurboVoltage|0x0 = # CLR Extra Turbo Voltage +gStructPcdTokenSpaceGuid.PcdSetup.ClrMaxOcRatio|0x0 = # CLR Max OC Ratio +gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageMode|0x0 = # CLR Voltage Mode +gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOffset|0x0 = # CLR Voltage Offset +gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOffsetPrefix|0x0 = # Offset Prefix +gStructPcdTokenSpaceGuid.PcdSetup.ClrVoltageOverride|0x0 = # CLR Voltage Override +gStructPcdTokenSpaceGuid.PcdSetup.ConsoleRedirection|0x1 = # Console Redirection +gStructPcdTokenSpaceGuid.PcdSetup.CoreExtraTurboVoltage|0x0 = # Core Extra Turbo Voltage +gStructPcdTokenSpaceGuid.PcdSetup.CoreMaxOcRatio|0x0 = # Core Max OC Ratio +gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageMode|0x0 = # Core Voltage Mode +gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOffset|0x0 = # Core Voltage Offset +gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOffsetPrefix|0x0 = # Offset Prefix +gStructPcdTokenSpaceGuid.PcdSetup.CoreVoltageOverride|0x0 = # Core Voltage Override +gStructPcdTokenSpaceGuid.PcdSetup.CorrMemErrEn|0x1 = # Memory Corrected Error +gStructPcdTokenSpaceGuid.PcdSetup.CpuVccInVoltage|0x167 = # CPU VCCin Voltage Level +gStructPcdTokenSpaceGuid.PcdSetup.CsmiDynamicDisable|0x1 = # CSMI Dynamic Disable +gStructPcdTokenSpaceGuid.PcdSetup.DataBits|0x8 = # Data Bits +gStructPcdTokenSpaceGuid.PcdSetup.DcpmmUncPoison|0x1 = # PMem UNC Poison +gStructPcdTokenSpaceGuid.PcdSetup.DdrtInternalAlertEn|0x1 = # PMem Host Alert Policy +gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.ReservedS1|0x0 +gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1 = # LER MA Error Logging +gStructPcdTokenSpaceGuid.PcdSetup.EdpcEn|0x0 = # IIO eDPC Support +gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1 = # IIO eDPC ERR_COR Message +gStructPcdTokenSpaceGuid.PcdSetup.EdpcInterrupt|0x1 = # IIO eDPC Interrupt +gStructPcdTokenSpaceGuid.PcdSetup.EfiNetworkSupport|0x0 = # EFI Network +gStructPcdTokenSpaceGuid.PcdSetup.ElogCorrErrEn|0x1 = # Corrected Error eLog +gStructPcdTokenSpaceGuid.PcdSetup.ElogMemErrEn|0x1 = # Memory Error eLog +gStructPcdTokenSpaceGuid.PcdSetup.ElogProcErrEn|0x1 = # Processor Error eLog +gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiEn|0x2 = # EMCA CMCI-SMI Morphing +gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiThreshold|0x0 = # EMCA CMCI-SMI Threshold +gStructPcdTokenSpaceGuid.PcdSetup.EmcaEn|0x1 = # EMCA Logging Support +gStructPcdTokenSpaceGuid.PcdSetup.EmcaIgnOptin|0x0 = # Ignore OS EMCA Opt-in +gStructPcdTokenSpaceGuid.PcdSetup.EmcaMsmiEn|0x2 = # EMCA MCE-SMI Enable +gStructPcdTokenSpaceGuid.PcdSetup.EnableAntiFlashWearout|0x0 = # Flash Wear Out Protection +gStructPcdTokenSpaceGuid.PcdSetup.ExpectedBer|0x7ffffffff = # Expected BER +gStructPcdTokenSpaceGuid.PcdSetup.FanPwmOffset|0x0 = # Fan PWM Offset +gStructPcdTokenSpaceGuid.PcdSetup.FatalErrSpinLoopEn|0x0 = # FatalErrDebugHalt +gStructPcdTokenSpaceGuid.PcdSetup.FilterPll|0x0 = # Filter Pll +gStructPcdTokenSpaceGuid.PcdSetup.FivrEfficiencyEnable|0x1 = # FIVR Efficiency Management +gStructPcdTokenSpaceGuid.PcdSetup.FivrFaultsEnable|0x1 = # FIVR Faults +gStructPcdTokenSpaceGuid.PcdSetup.FlowControl|0x0 = # Flow Control +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorEn|0x1 = # PMem CTLR Errors +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorHighPrioritySignal|0x1 = # PMem CTLR High Priority Error Signaling +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorLowPrioritySignal|0x1 = # PMem CTLR Low Priority Error Signaling +gStructPcdTokenSpaceGuid.PcdSetup.ForceSetup|0x0 = # Force Setup +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[0]|0x1 = # FPK Port 1 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[1]|0x1 = # FPK Port 2 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[2]|0x1 = # FPK Port 3 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[3]|0x1 = # FPK Port 4 +gStructPcdTokenSpaceGuid.PcdSetup.GbeEnabled|0x0 = # PCH Internal LAN +gStructPcdTokenSpaceGuid.PcdSetup.GbePciePortNum|0x0 = # PCIE Port assigned to LAN +gStructPcdTokenSpaceGuid.PcdSetup.Gen12ErrorThreshold|0x0 = # Error Threshold (Gen1/2) +gStructPcdTokenSpaceGuid.PcdSetup.Gen12TimeWindow|0xffff = # Time Window (Gen1/2) +gStructPcdTokenSpaceGuid.PcdSetup.Gen2LinkDegradation|0x1 = # Gen2 Link Degradation +gStructPcdTokenSpaceGuid.PcdSetup.Gen34ErrorThreshold|0x10 = # Error Threshold (Gen3/4) +gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1 = # Gen3/4 Re-Equalization +gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2 = # Time Window (Gen3/4) +gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1 = # Gen3 Link Degradation +gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1 = # Gen4 Link Degradation +gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1 = # IIO Dma Error +gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1 = # IIO Dmi Error +gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1 = # IIO Error Registers Clear +gStructPcdTokenSpaceGuid.PcdSetup.IioErrorEn|0x1 = # IIO/PCH Global Error Support +gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin0En|0x0 = # IIO Error Pin0 Enable +gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin1En|0x0 = # IIO Error Pin1 Enable +gStructPcdTokenSpaceGuid.PcdSetup.IioErrorPin2En|0x0 = # IIO Error Pin2 Enable +gStructPcdTokenSpaceGuid.PcdSetup.IioIrpErrorEn|0x1 = # IIO Coherent Interface Error +gStructPcdTokenSpaceGuid.PcdSetup.IioMiscErrorEn|0x1 = # IIO Misc. Error +gStructPcdTokenSpaceGuid.PcdSetup.IioOOBMode|0x1 = # IIO OOB Mode +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddCorrErrorEn|0x1 = # IIO PCIE Additional Corrected Error +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddRcvComWithUr|0x0 = # IIO PCIE Additional Received Completion With UR +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddUnCorrEn|0x1 = # IIO PCIE Additional Uncorrected Error +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAerSpecCompEn|0x0 = # IIO PCIE AER Spec Compliant +gStructPcdTokenSpaceGuid.PcdSetup.IioSev1Pcc|0x0 = # Clear PCC for IIO Non-Fatal Error +gStructPcdTokenSpaceGuid.PcdSetup.IioVtdErrorEn|0x1 = # IIO Vtd Error +gStructPcdTokenSpaceGuid.PcdSetup.IoMcaEn|0x1 = # IIO MCA Support +gStructPcdTokenSpaceGuid.PcdSetup.IoaVoltageOffset|0x0 = # IOA Voltage Offset +gStructPcdTokenSpaceGuid.PcdSetup.IoaVoltageOffsetPrefix|0x0 = # Offset Prefix +gStructPcdTokenSpaceGuid.PcdSetup.IodVoltageOffset|0x0 = # IOD Voltage Offset +gStructPcdTokenSpaceGuid.PcdSetup.IodVoltageOffsetPrefix|0x0 = # Offset Prefix +gStructPcdTokenSpaceGuid.PcdSetup.ItcOtcCaMaEnable|0x0 = # ITC/OTC CA/MA Errors +gStructPcdTokenSpaceGuid.PcdSetup.KTIFailoverSmiEn|0x0 +gStructPcdTokenSpaceGuid.PcdSetup.KcsAccessPolicy|0x3 = # KCS Access Control Policy +gStructPcdTokenSpaceGuid.PcdSetup.KtiFirstCeLatchEn|0x0 = # Latch First Corrected Error in KTI +gStructPcdTokenSpaceGuid.PcdSetup.LegacyOsRedirection|0x1 = # Legacy OS Redirection +gStructPcdTokenSpaceGuid.PcdSetup.LegacyPxeRom|0x0 = # Legacy Option ROMs support +gStructPcdTokenSpaceGuid.PcdSetup.LerEn|0x0 = # IIO LER Support +gStructPcdTokenSpaceGuid.PcdSetup.LmceEn|0x1 = # LMCE Support +gStructPcdTokenSpaceGuid.PcdSetup.LomDisableByGpio|0x1 = # LOM +gStructPcdTokenSpaceGuid.PcdSetup.MRIOVEnable|0x0 = # MR-IOV Support +gStructPcdTokenSpaceGuid.PcdSetup.McBankWarmBootClearError|0x1 = # Mca Bank Warm Boot Clear Errors +gStructPcdTokenSpaceGuid.PcdSetup.McaBankErrInjEn|0x0 = # Mca Bank Error Injection Support +gStructPcdTokenSpaceGuid.PcdSetup.McaSpinLoop|0x0 = # MCA Spin Loop +gStructPcdTokenSpaceGuid.PcdSetup.MeSegErrorInjEn|0x0 = # ME Seg Error Injection Support +gStructPcdTokenSpaceGuid.PcdSetup.MemErrEn|0x1 = # Memory Error +gStructPcdTokenSpaceGuid.PcdSetup.NgnAddressRangeScrub|0x0 = # Set PMem Address Range Scrub +gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertDpa|0x0 = # Set PMem Host Alert Policy for DPA Error +gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertPatrolScrubUNC|0x1 = # Set PMem Host Alert Policy for Patrol Scrub +gStructPcdTokenSpaceGuid.PcdSetup.Numlock|0x0 = # NumLock +gStructPcdTokenSpaceGuid.PcdSetup.OsNativeAerSupport|0x0 = # Os Native AER Support +gStructPcdTokenSpaceGuid.PcdSetup.OverclockingSupport|0x0 = # OverClocking Feature +gStructPcdTokenSpaceGuid.PcdSetup.Parity|0x1 = # Parity +gStructPcdTokenSpaceGuid.PcdSetup.PatrolScrubErrorReporting|0x1 = # Patrol Scrub Error Reporting +gStructPcdTokenSpaceGuid.PcdSetup.PchStepping|0x0 = # PCH Stepping +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerAdNfatErrEn|0x1 = # PCIE AER Advisory Nonfatal Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerCorrErrEn|0x1 = # PCIE AER Corrected Errors +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerEcrcEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerFatErrEn|0x1 = # PCIE AER Fatal Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerNfatErrEn|0x1 = # PCIE AER NonFatal Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerSurpriseLinkDownEn|0x0 = # PCIE Surprise Link Down Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerUreEn|0x0 = # PCIE Unsupported Request Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieClockGatingDisabled|0x0 = # PCIE Clock Gating +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrCntr|0x0 = # PCIE Corrected Error Threshold Counter +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrLimit|0x50 = # PCIe Corrected Error Limit +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrLimitEn|0x0 = # PCIe Corrected Error Limit Check +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrThres|0x1 = # PCIE Corrected Error Threshold +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorrErrEn|0x1 = # Corrected Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieDmiAspm|0x0 = # PCH DMI ASPM +gStructPcdTokenSpaceGuid.PcdSetup.PcieErrEn|0x1 = # PCIE Error +gStructPcdTokenSpaceGuid.PcdSetup.PcieErrInjActionTable|0x0 = # Whea PCIe Error Injection Action Table +gStructPcdTokenSpaceGuid.PcdSetup.PcieFatalErrEn|0x1 = # Fatal Error Enable +gStructPcdTokenSpaceGuid.PcdSetup.PcieUncorrErrEn|0x1 = # Uncorrected Error +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmActiveMajorVersion|0x0 = # BMC PFM Active Major Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmActiveMinorVersion|0x0 = # BMC PFM Active Minor Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmRecoveryMajorVersion|0x0 = # BMC PFM Recovery Major Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfmRecoveryMinorVersion|0x0 = # BMC PFM Recovery Minor Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfrActiveSvn|0x0 = # BMC PFR Active SVN +gStructPcdTokenSpaceGuid.PcdSetup.PfrBmcPfrRecoverySvn|0x0 = # BMC PFR Recovery SVN +gStructPcdTokenSpaceGuid.PcdSetup.PfrCpldRotReleaseVersion|0x0 = # CPLD RoT Release Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrCpldRotSvn|0x0 = # CPLD RoT SVN +gStructPcdTokenSpaceGuid.PcdSetup.PfrLock|0x0 = # PFR Lock +gStructPcdTokenSpaceGuid.PcdSetup.PfrLockStatus|0x0 = # PFR Status: Locked +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmActiveMajorVersion|0x0 = # PCH PFM Active Major Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmActiveMinorVersion|0x0 = # PCH PFM Active Minor Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmRecoveryMajorVersion|0x0 = # PCH PFM Recovery Major Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfmRecoveryMinorVersion|0x0 = # PCH PFM Recovery Minor Version +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfrActiveSvn|0x0 = # PCH PFR Active SVN +gStructPcdTokenSpaceGuid.PcdSetup.PfrPchPfrRecoverySvn|0x0 = # PCH PFR Recovery SVN +gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL1|0x0 = # PFR PIT Level-1 Protection +gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL1Status|0x0 = # PFR Status: PIT Level-1 Protection Enabled +gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL2|0x0 = # PFR PIT Level-2 Protection +gStructPcdTokenSpaceGuid.PcdSetup.PfrPitL2Status|0x0 = # PFR Status: PIT Level-2 Protection Enabled +gStructPcdTokenSpaceGuid.PcdSetup.PfrProvision|0x0 = # PFR Provision +gStructPcdTokenSpaceGuid.PcdSetup.PfrProvisionStatus|0x0 = # PFR Status: Provisioned +gStructPcdTokenSpaceGuid.PcdSetup.PfrSupported|0x0 = # PFR Supported +gStructPcdTokenSpaceGuid.PcdSetup.PfrUnProvision|0x0 = # PFR UnProvision +gStructPcdTokenSpaceGuid.PcdSetup.PlatformOCSupport|0x0 = # Platform Over Clocking Support +gStructPcdTokenSpaceGuid.PcdSetup.PmsbRouterParityErrEn|0x1 = # PMSB Router Parity Error +gStructPcdTokenSpaceGuid.PcdSetup.PoisonEn|0x1 = # System Memory Poison +gStructPcdTokenSpaceGuid.PcdSetup.PropagatePerr|0x1 = # Assert NMI on PERR +gStructPcdTokenSpaceGuid.PcdSetup.PropagateSerr|0x1 = # Assert NMI on SERR +gStructPcdTokenSpaceGuid.PcdSetup.Ps2PortSwap|0x0 = # PS2 Port Swap +gStructPcdTokenSpaceGuid.PcdSetup.PsfUrEnable|0x1 = # PSF UR Error +gStructPcdTokenSpaceGuid.PcdSetup.PublishSetupPgPtr|0x0 = # Publish Setup page Pointer +gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeHour|0x0 = # Wake up hour +gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeMinute|0x0 = # Wake up minute +gStructPcdTokenSpaceGuid.PcdSetup.RTCWakeupTimeSecond|0x0 = # Wake up second +gStructPcdTokenSpaceGuid.PcdSetup.RasLogLevel|0x1 = # RAS Log Level +gStructPcdTokenSpaceGuid.PcdSetup.ReportAlertSPA|0x1 = # Enable Reporting SPA to OS +gStructPcdTokenSpaceGuid.PcdSetup.ReserveMem|0x0 = # Reserve Memory Range +gStructPcdTokenSpaceGuid.PcdSetup.ReserveStartAddr|0x100000 = # Start Address +gStructPcdTokenSpaceGuid.PcdSetup.ResetOnMemMapChange|0x0 = # Reset Platform on Memory Map Change +gStructPcdTokenSpaceGuid.PcdSetup.RsaSupport|0x0 = # RSA Support +gStructPcdTokenSpaceGuid.PcdSetup.SRIOVEnable|0x1 = # SR-IOV Support +gStructPcdTokenSpaceGuid.PcdSetup.SerialBaudRate|0x1c200 = # BIOS Serial Port Baud Rate +gStructPcdTokenSpaceGuid.PcdSetup.SetShellFirst|0x0 = # Boot Shell First +gStructPcdTokenSpaceGuid.PcdSetup.SgxErrorInjEn|0x0 = # SGX Memory Error Injection Support +gStructPcdTokenSpaceGuid.PcdSetup.ShellEntryTime|0x5 = # System Shell Timeout +gStructPcdTokenSpaceGuid.PcdSetup.ShutdownSuppression|0x0 = # Shutdown Suppression +gStructPcdTokenSpaceGuid.PcdSetup.SkipXmlComprs|0x0 = # Skip XML Compression +gStructPcdTokenSpaceGuid.PcdSetup.SpareIntSelect|0x1 = # Spare Interrupt +gStructPcdTokenSpaceGuid.PcdSetup.StopBits|0x1 = # Stop Bits +gStructPcdTokenSpaceGuid.PcdSetup.StorageOpROMSuppression|0x0 = # Storage OPROM Suppression +gStructPcdTokenSpaceGuid.PcdSetup.SvidEnable|0x1 = # SVID Support +gStructPcdTokenSpaceGuid.PcdSetup.SvidVoltageOverride|0x0 = # SVID Voltage Override +gStructPcdTokenSpaceGuid.PcdSetup.SystemErrorEn|0x1 = # System Errors +gStructPcdTokenSpaceGuid.PcdSetup.SystemPageSize|0x0 = # SR-IOV SystemPageSize +gStructPcdTokenSpaceGuid.PcdSetup.TagecMem|0x0 = # Reserve TAGEC Memory +gStructPcdTokenSpaceGuid.PcdSetup.TerminalResolution|0x0 = # Terminal Resolution +gStructPcdTokenSpaceGuid.PcdSetup.TerminalType|0x2 = # Terminal Type +gStructPcdTokenSpaceGuid.PcdSetup.UboxErrorMask|0x0 = # Ubox Error Mask +gStructPcdTokenSpaceGuid.PcdSetup.UboxToPcuMcaEn|0x1 = # UboxToPcuMca Enabling +gStructPcdTokenSpaceGuid.PcdSetup.UncoreVoltageOffset|0x0 = # Uncore Voltage Offset +gStructPcdTokenSpaceGuid.PcdSetup.UncoreVoltageOffsetPrefix|0x0 = # Offset Prefix +gStructPcdTokenSpaceGuid.PcdSetup.UsbEmul6064|0x0 = # Port 60/64 Emulation +gStructPcdTokenSpaceGuid.PcdSetup.UsbLegacySupport|0x0 = # Legacy USB Support +gStructPcdTokenSpaceGuid.PcdSetup.UsbMassResetDelay|0x1 = # Device Reset timeout +gStructPcdTokenSpaceGuid.PcdSetup.UsbNonBoot|0x0 = # Make USB Devices Non-Bootable +gStructPcdTokenSpaceGuid.PcdSetup.Use1GPageTable|0x1 = # Max Page Table Size Select +gStructPcdTokenSpaceGuid.PcdSetup.ValidationBreakpointType|0x0 = # Breakpoint Type +gStructPcdTokenSpaceGuid.PcdSetup.VccIoVoltage|0x0 = # VccIo Voltage Control +gStructPcdTokenSpaceGuid.PcdSetup.VideoSelect|0x0 = # Active Video +gStructPcdTokenSpaceGuid.PcdSetup.ViralEn|0x0 = # Viral Status +gStructPcdTokenSpaceGuid.PcdSetup.WakeOnLanS5|0x0 = # Wake On Lan from S5 +gStructPcdTokenSpaceGuid.PcdSetup.WakeOnLanSupport|0x0 = # Wake On Lan Support +gStructPcdTokenSpaceGuid.PcdSetup.WakeOnRTCS4S5|0x0 = # RTC Wake system from S4/S5 +gStructPcdTokenSpaceGuid.PcdSetup.WheaErrInjEn|0x1 = # WHEA Error Injection 5.0 Extension +gStructPcdTokenSpaceGuid.PcdSetup.WheaErrorInjSupportEn|0x0 = # WHEA Error Injection Support +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogMemoryEn|0x1 = # Whea Log Memory Error +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogPciEn|0x1 = # Whea Log PCI Error +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogProcEn|0x1 = # Whea Log Processor Error +gStructPcdTokenSpaceGuid.PcdSetup.WheaPcieErrInjEn|0x0 = # Whea PCIE Error Injection Support +gStructPcdTokenSpaceGuid.PcdSetup.WheaSupportEn|0x1 = # WHEA Support +gStructPcdTokenSpaceGuid.PcdSetup.XhciWakeOnUsbEnabled|0x1 = # XHCI Wake On Usb Enable +gStructPcdTokenSpaceGuid.PcdSetup.XmlCliSupport|0x1 = # Xml Cli Support +gStructPcdTokenSpaceGuid.PcdSetup.bsdBreakpoint|0x0 = # BsdBreakPoint +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs0|0x1 = # IIO IRP0 wrcache correcccs0 error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs1|0x1 = # IIO IRP0 wrcache correcccs1 error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_csraccunaligned|0x1 = # IIO IRP0 csr acc 32b unaligned +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_parityError|0x1 = # IIO IRP0 protocol parity error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_qtOverflow|0x1 = # IIO IRP0 protocol qt overflow underflow error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_rcvdpoison|0x1 = # IIO IRP0 protocol rcvd poison error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs0|0x1 = # IIO IRP0 wrcache uncecccs0 error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs1|0x1 = # IIO IRP0 wrcache uncecccs1 error +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unexprsp|0x1 = # IIO IRP0 protocol rcvd unexprsp +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugTrace|0x0 = # Trace Messages +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS8|0x0 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[0]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[1]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[2]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[3]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[4]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[5]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[6]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[7]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[8]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[9]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[10]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[11]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[12]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[13]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[14]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[15]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[16]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[17]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[18]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[19]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[20]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[21]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[22]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[23]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[24]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[25]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[26]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[27]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[28]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[29]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[30]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[31]|0xff +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS6|0xf +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.IsocEn|0x2 = # Isoc Mode +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MirrorMode|0x0 = # Mirror Mode +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgBase|0x6 = # MMCFG Base +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgSize|0x6 = # MMCFG Size +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohBase|0x2 = # MMIO High Base +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohSize|0x3 = # MMIO High Granularity Size +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.NumaEn|0x1 = # Numa +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.SystemRasType|0x0 = # System RAS Type +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.UmaBasedClustering|0x2 = # UMA-Based Clustering +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.VirtualNumaEnable|0x0 = # Virtual Numa +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[1]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[2]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[3]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[4]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[5]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[6]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[7]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[8]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[9]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[10]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[11]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[12]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[13]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[14]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[15]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[16]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[17]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[18]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[19]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[20]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[21]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[22]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[23]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[24]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[25]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[26]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[27]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[28]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[29]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[30]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[31]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[32]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[33]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[34]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[35]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[36]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[37]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[38]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[39]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[40]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[41]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[42]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[43]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[44]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[45]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[46]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[47]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[48]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[49]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[50]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[51]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[52]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[53]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[54]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[55]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[56]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[57]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[58]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[59]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[60]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[61]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[62]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[63]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[64]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[65]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[66]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[67]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[68]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[69]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[70]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[71]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[72]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[73]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[74]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[75]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[76]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[77]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[78]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[79]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[80]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[81]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[82]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIHP[83]|0x0 = # HotPlug ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[1]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[2]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[3]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[4]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[5]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[6]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[7]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[8]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[9]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[10]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[11]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[12]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[13]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[14]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[15]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[16]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[17]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[18]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[19]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[20]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[21]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[22]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[23]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[24]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[25]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[26]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[27]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[28]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[29]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[30]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[31]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[32]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[33]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[34]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[35]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[36]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[37]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[38]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[39]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[40]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[41]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[42]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[43]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[44]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[45]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[46]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[47]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[48]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[49]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[50]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[51]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[52]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[53]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[54]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[55]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[56]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[57]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[58]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[59]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[60]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[61]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[62]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[63]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[64]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[65]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[66]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[67]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[68]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[69]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[70]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[71]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[72]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[73]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[74]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[75]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[76]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[77]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[78]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[79]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[80]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[81]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[82]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPM[83]|0x0 = # PM ACPI Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[0]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[1]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[2]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[3]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[4]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[5]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[6]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[7]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[8]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[9]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[10]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[11]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[12]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[13]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[14]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[15]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[16]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[17]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[18]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[19]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[20]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[21]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[22]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[23]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[24]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[25]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[26]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[27]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[28]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[29]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[30]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[31]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[32]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[33]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[34]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[35]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[36]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[37]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[38]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[39]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[40]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[41]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[42]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[43]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[44]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[45]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[46]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[47]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[48]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[49]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[50]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[51]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[52]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[53]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[54]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[55]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[56]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[57]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[58]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[59]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[60]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[61]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[62]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[63]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[64]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[65]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[66]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[67]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[68]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[69]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[70]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[71]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[72]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[73]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[74]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[75]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[76]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[77]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[78]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[79]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[80]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[81]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[82]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[83]|0x0 = # ACPI PME Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1 = # ATS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[3]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[4]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[5]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[6]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[7]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[8]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[9]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[10]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[11]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[12]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[13]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[14]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[15]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[16]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[17]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[18]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[19]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[20]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[21]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[22]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[23]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[24]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[25]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[26]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[27]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[28]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[29]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[30]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[31]|0x1 = # DMA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[0]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[1]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[2]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[3]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[4]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[5]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[6]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[7]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[8]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[9]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[10]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[11]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[12]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[13]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[14]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[15]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[16]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[17]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[18]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[19]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[20]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[21]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[22]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[23]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[24]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[25]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[26]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[27]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[28]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[29]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[30]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3NoSnoopEn[31]|0x0 = # No Snoop +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCastEnable|0x1 = # CbDma MultiCast Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbRelaxedOrdering|0x0 = # Relaxed Ordering +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1 = # Coherency Support (Non-Isoch) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherentReadFull|0x0 = # PCIE Coherent Read Full +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherentReadPart|0x0 = # PCIE Coherent Read Partial +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0= x9 # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[0]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[1]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[2]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[3]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[4]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[5]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[6]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[7]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[8]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[9]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[10]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[11]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[12]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[13]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[14]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[15]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[16]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[17]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[18]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[19]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[20]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[21]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[22]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[23]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[24]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[25]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[26]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[27]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[28]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[29]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[30]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[31]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[32]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[33]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[34]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[35]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[36]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[37]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[38]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[39]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[40]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[41]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[42]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[43]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[44]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[45]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[46]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[47]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[48]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[49]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[50]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[51]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[52]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[53]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[54]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[55]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[56]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[57]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[58]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[59]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[60]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[61]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[62]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[63]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[64]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[65]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[66]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[67]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[68]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[69]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[70]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[71]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[72]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[73]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[74]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[75]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[76]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[77]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[78]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[79]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[80]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[81]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[82]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[83]|0x0 = # Compliance Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xff = # IOU0 (IIO PCIe Port 1) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xff = # IOU0 (IIO PCIe Port 1) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xff = # IOU0 (IIO PCIe Port 1) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[3]|0xff = # IOU0 (IIO PCIe Port 1) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[0]|0xff = # IOU1 (IIO PCIe Port 2) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[1]|0xff = # IOU1 (IIO PCIe Port 2) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[2]|0xff = # IOU1 (IIO PCIe Port 2) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[3]|0xff = # IOU1 (IIO PCIe Port 2) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[0]|0xff = # IOU2 (IIO PCIe Port 3) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[1]|0xff = # IOU2 (IIO PCIe Port 3) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[2]|0xff = # IOU2 (IIO PCIe Port 3) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[3]|0xff = # IOU2 (IIO PCIe Port 3) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[0]|0xff = # IOU3 (IIO PCIe Port 4) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[1]|0xff = # IOU3 (IIO PCIe Port 4) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[2]|0xff = # IOU3 (IIO PCIe Port 4) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[3]|0xff = # IOU3 (IIO PCIe Port 4) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[0]|0xff = # IOU4 (IIO PCIe Port 5) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[1]|0xff = # IOU4 (IIO PCIe Port 5) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[2]|0xff = # IOU4 (IIO PCIe Port 5) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[3]|0xff = # IOU4 (IIO PCIe Port 5) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ControlIommu|0x0 = # Pre-boot DMA Protection +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS9|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[0]|0x0 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[1]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[2]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[3]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[4]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[5]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[6]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[7]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[8]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[9]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[10]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[11]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[12]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[13]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[14]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[15]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[16]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[17]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[18]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[19]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[20]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[21]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[22]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[23]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[24]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[25]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[26]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[27]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[28]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[29]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[30]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[31]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[32]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[33]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[34]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[35]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[36]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[37]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[38]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[39]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[40]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[41]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[42]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[43]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[44]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[45]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[46]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[47]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[48]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[49]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[50]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[51]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[52]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[53]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[54]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[55]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[56]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[57]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[58]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[59]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[60]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[61]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[62]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[63]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[64]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[65]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[66]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[67]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[68]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[69]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[70]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[71]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[72]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[73]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[74]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[75]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[76]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[77]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[78]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[79]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[80]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[81]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[82]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[83]|0x1 = # PCI-E Port DeEmphasis +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DelayBeforePCIeLinkTraining|0x= 0 # Delay before link training +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[0]|0x0 = # IIO IOAPIC Stack 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS19|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS10|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[0]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[1]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[2]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[3]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[4]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[5]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[6]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[7]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[8]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[9]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[10]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[11]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[12]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[13]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[14]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[15]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[16]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[17]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[18]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[19]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[20]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[21]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[22]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[23]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[24]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[25]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[26]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[27]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[28]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[29]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[30]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[31]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[32]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[33]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[34]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[35]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[36]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[37]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[38]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[39]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[40]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[41]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[42]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[43]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[44]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[45]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[46]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[47]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[48]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[49]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[50]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[51]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[52]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[53]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[54]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[55]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[56]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[57]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[58]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[59]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[60]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[61]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[62]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[63]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[64]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[65]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[66]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[67]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[68]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[69]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[70]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[71]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[72]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[73]|0xff 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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[168]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[169]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[170]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[171]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[172]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[173]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[174]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[175]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[176]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[177]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[178]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[179]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[180]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[181]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[182]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[183]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[184]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[185]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[186]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[187]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[188]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[189]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[190]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[191]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[192]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[193]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[194]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[195]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[196]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[197]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[198]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[199]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[200]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[201]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[202]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[203]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[204]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[205]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[206]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[207]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[208]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[209]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[210]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[211]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[212]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[213]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[214]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[215]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[216]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[217]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[218]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[219]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[220]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[221]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[222]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[223]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[224]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[225]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[226]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[227]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[228]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[229]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[230]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[231]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[232]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[233]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[234]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[235]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[236]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[237]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[238]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[239]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[240]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[241]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[242]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[243]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[244]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[245]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[246]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[247]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[248]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[249]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[250]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[251]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[252]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[253]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[254]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS21[255]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[0]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[1]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[2]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[3]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[4]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[5]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[6]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[7]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[8]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[9]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[10]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[11]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[12]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[13]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[14]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[15]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[16]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[17]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[18]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[19]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[20]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[21]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[22]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[23]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[24]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[25]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[26]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[27]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[28]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[29]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[30]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[31]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[32]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[33]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[34]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[35]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[36]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[37]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[38]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[39]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[40]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[41]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[42]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[43]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[44]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[45]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[46]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[47]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[48]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[49]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[50]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[51]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[52]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[53]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[54]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[55]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[56]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[57]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[58]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[59]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[60]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[61]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[62]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[63]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[64]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[65]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[66]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[67]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[68]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[69]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[70]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[71]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[72]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[73]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[74]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[75]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[76]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[77]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[78]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[79]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[80]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[81]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[82]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS41[83]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[0]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[1]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[2]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[3]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[4]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[5]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[6]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[7]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[8]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[9]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[10]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[11]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[12]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[13]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[14]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[15]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[16]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[17]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[18]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[19]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[20]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[21]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[22]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[23]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[24]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[25]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[26]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[27]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[28]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[29]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[30]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[31]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[32]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[33]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[34]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[35]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[36]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[37]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[38]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[39]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[40]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[41]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[42]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[43]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[44]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[45]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[46]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[47]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[48]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[49]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[50]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[51]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[52]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[53]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[54]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[55]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[56]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[57]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[58]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[59]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[60]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[61]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[62]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[63]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[64]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[65]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[66]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[67]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[68]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[69]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[70]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[71]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[72]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[73]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[74]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[75]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[76]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[77]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[78]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[79]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[80]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[81]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[82]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS43[83]|0xff +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[0]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[1]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[2]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[3]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[4]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[5]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[6]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[7]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[8]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[9]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[10]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[11]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[12]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[13]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[14]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[15]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[16]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[17]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[18]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[19]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[20]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[21]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[22]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[23]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[24]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[25]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[26]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[27]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[28]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[29]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[30]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[31]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[32]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[33]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[34]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[35]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[36]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[37]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[38]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[39]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[40]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[41]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[42]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[43]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[44]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[45]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[46]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[47]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[48]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[49]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[50]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[51]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[52]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[53]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[54]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[55]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[56]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[57]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[58]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[59]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[60]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[61]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[62]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[63]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[64]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[65]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[66]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[67]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[68]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[69]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[70]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[71]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[72]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[73]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[74]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[75]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[76]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[77]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[78]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[79]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[80]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[81]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[82]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisPMETOAck[83]|0x0 = # PME to ACK +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DisableTPH|0x0 = # Disable TPH +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DmaCtrlOptIn|0x0 = # DMA Control Opt-In Flag +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DmiAllocatingFlow|0x1 = # DMI Allocating Write Flows +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DualCvIoFlow|0x1 = # Dual CV IO Flow +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EN1K|0x0 = # EN1K +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[0]|0x1 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[1]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[2]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[3]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[4]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[5]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[6]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[7]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[8]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[9]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[10]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[11]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[12]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[13]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[14]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[15]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[16]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[17]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[18]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[19]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[20]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[21]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[22]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[23]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[24]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[25]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[26]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[27]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[28]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[29]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[30]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[31]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[32]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[33]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[34]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[35]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[36]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[37]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[38]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[39]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[40]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[41]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[42]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[43]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[44]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[45]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[46]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[47]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[48]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[49]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[50]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[51]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[52]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[53]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[54]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[55]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[56]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[57]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[58]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[59]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[60]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[61]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[62]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[63]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[64]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[65]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[66]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[67]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[68]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[69]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[70]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[71]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[72]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[73]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[74]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[75]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[76]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[77]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[78]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[79]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[80]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[81]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[82]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EOI[83]|0x0 = # EOI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[0]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[1]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[2]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[3]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[4]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[5]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[6]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[7]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[8]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[9]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[10]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[11]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[12]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[13]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[14]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[15]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[16]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[17]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[18]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[19]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[20]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[21]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[22]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[23]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[24]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[25]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[26]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[27]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[28]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[29]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[30]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[31]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[32]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[33]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[34]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[35]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[36]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[37]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[38]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[39]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[40]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[41]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[42]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[43]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[44]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[45]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[46]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[47]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[48]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[49]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[50]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[51]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[52]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[53]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[54]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[55]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[56]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[57]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[58]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[59]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[60]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[61]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[62]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[63]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[64]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[65]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[66]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[67]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[68]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[69]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[70]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[71]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[72]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[73]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[74]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[75]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[76]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[77]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[78]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[79]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[80]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[81]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[82]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcChkEn[83]|0x0 = # ECRC Check +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[0]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[1]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[2]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[3]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[4]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[5]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[6]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[7]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[8]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[9]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[10]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[11]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[12]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[13]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[14]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[15]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[16]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[17]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[18]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[19]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[20]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[21]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[22]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[23]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[24]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[25]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[26]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[27]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[28]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[29]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[30]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[31]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[32]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[33]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[34]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[35]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[36]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[37]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[38]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[39]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[40]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[41]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[42]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[43]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[44]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[45]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[46]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[47]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[48]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[49]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[50]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[51]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[52]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[53]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[54]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[55]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[56]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[57]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[58]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[59]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[60]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[61]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[62]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[63]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[64]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[65]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[66]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[67]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[68]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[69]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[70]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[71]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[72]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[73]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[74]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[75]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[76]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[77]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[78]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[79]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[80]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[81]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[82]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.EcrcGenEn[83]|0x0 = # ECRC Generation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[0]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[1]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[2]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[3]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[4]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[5]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[6]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[7]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[8]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[9]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[10]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[11]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[12]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[13]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[14]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[15]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[16]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[17]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[18]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[19]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[20]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[21]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[22]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[23]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[24]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[25]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[26]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[27]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[28]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[29]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[30]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[31]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[32]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[33]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[34]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[35]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[36]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[37]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[38]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[39]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[40]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[41]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[42]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[43]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[44]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[45]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[46]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[47]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[48]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[49]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[50]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[51]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[52]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[53]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[54]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[55]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[56]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[57]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[58]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[59]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[60]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[61]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[62]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[63]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[64]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[65]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[66]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[67]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[68]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[69]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[70]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[71]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[72]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[73]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[74]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[75]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[76]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[77]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[78]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[79]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[80]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[81]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[82]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ExtendedSync[83]|0x0 = # PCI-E Extended Sync +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.GlobalPme2AckTOCtrl|0x0 = # PME2ACK Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.HaltOnDmiDegraded|0x0 = # Skip Halt On DMI Degradation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[0]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[1]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[2]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[3]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[4]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[5]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[6]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[7]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[8]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[9]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[10]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[11]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[12]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[13]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[14]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[15]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[16]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[17]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[18]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[19]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[20]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[21]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[22]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[23]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[24]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[25]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[26]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[27]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[28]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[29]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[30]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[31]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[32]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[33]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[34]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[35]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[36]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[37]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[38]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[39]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[40]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[41]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[42]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[43]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[44]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[45]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[46]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[47]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[48]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[49]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[50]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[51]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[52]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[53]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[54]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[55]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[56]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[57]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[58]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[59]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[60]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[61]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[62]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[63]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[64]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[65]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[66]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[67]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[68]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[69]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[70]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[71]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[72]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[73]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[74]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[75]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[76]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[77]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[78]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[79]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[80]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[81]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[82]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.IODC[83]|0x6 = # IODC Configuration +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[0]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[1]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[2]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[3]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[4]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[5]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[6]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[7]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[8]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[9]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[10]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[11]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[12]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[13]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[14]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[15]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[16]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[17]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[18]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[19]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[20]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[21]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[22]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[23]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[24]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[25]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[26]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[27]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[28]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[29]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[30]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[31]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[32]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[33]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[34]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[35]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[36]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[37]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[38]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[39]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[40]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[41]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[42]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[43]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[44]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[45]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[46]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[47]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[48]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[49]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[50]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[51]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[52]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[53]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[54]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[55]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[56]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[57]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[58]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[59]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[60]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[61]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[62]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[63]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[64]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[65]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[66]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[67]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[68]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[69]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[70]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[71]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[72]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[73]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[74]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[75]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[76]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[77]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[78]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[79]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[80]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[81]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[82]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS45[83]|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.InterruptRemap|0x2 = # Interrupt Remapping +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[0]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[1]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[2]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[3]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[4]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[5]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[6]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[7]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[8]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[9]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[10]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[11]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[12]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[13]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[14]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[15]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[16]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[17]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[18]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[19]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[20]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[21]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[22]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[23]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[24]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[25]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[26]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[27]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[28]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[29]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[30]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[31]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[32]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[33]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[34]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[35]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[36]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[37]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[38]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[39]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[40]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[41]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[42]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[43]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[44]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[45]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[46]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[47]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[48]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[49]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[50]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[51]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[52]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[53]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[54]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[55]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[56]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[57]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[58]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[59]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[60]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[61]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[62]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[63]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[64]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[65]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[66]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[67]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[68]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[69]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[70]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[71]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[72]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[73]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[74]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[75]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[76]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[77]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[78]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[79]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[80]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[81]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[82]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSICOREN[83]|0x0 = # Corr Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[0]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[1]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[2]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[3]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[4]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[5]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[6]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[7]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[8]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[9]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[10]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[11]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[12]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[13]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[14]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[15]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[16]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[17]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[18]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[19]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[20]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[21]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[22]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[23]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[24]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[25]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[26]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[27]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[28]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[29]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[30]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[31]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[32]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[33]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[34]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[35]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[36]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[37]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[38]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[39]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[40]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[41]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[42]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[43]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[44]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[45]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[46]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[47]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[48]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[49]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[50]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[51]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[52]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[53]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[54]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[55]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[56]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[57]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[58]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[59]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[60]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[61]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[62]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[63]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[64]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[65]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[66]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[67]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[68]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[69]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[70]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[71]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[72]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[73]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[74]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[75]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[76]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[77]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[78]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[79]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[80]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[81]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[82]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSIFATEN[83]|0x0 = # Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[0]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[1]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[2]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[3]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[4]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[5]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[6]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[7]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[8]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[9]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[10]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[11]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[12]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[13]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[14]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[15]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[16]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[17]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[18]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[19]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[20]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[21]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[22]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[23]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[24]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[25]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[26]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[27]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[28]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[29]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[30]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[31]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[32]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[33]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[34]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[35]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[36]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[37]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[38]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[39]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[40]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[41]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[42]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[43]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[44]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[45]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[46]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[47]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[48]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[49]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[50]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[51]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[52]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[53]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[54]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[55]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[56]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[57]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[58]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[59]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[60]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[61]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[62]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[63]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[64]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[65]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[66]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[67]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[68]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[69]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[70]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[71]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[72]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[73]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[74]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[75]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[76]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[77]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[78]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[79]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[80]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[81]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[82]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MSINFATEN[83]|0x0 = # Non-Fatal Err Over +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MaxReadCompCombSize|0x0 = # Max Read Comp Comb Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastBaseAddrRegion|0x0 = # MC BaseAddress Range +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastIndexPosition|0xc = # MC Index Position +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.McastNumGroup|0x8 = # MC Num Group +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[0]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[1]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[2]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[3]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[4]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[5]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[6]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[7]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[8]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[9]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[10]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[11]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[12]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[13]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[14]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[15]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[16]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[17]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[18]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[19]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[20]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[21]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[22]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[23]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[24]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[25]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[26]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[27]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[28]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[29]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[30]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[31]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[32]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[33]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[34]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[35]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[36]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[37]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[38]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[39]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[40]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[41]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[42]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[43]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[44]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[45]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[46]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[47]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[48]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[49]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[50]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[51]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[52]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[53]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[54]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[55]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[56]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[57]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[58]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[59]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[60]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[61]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[62]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[63]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[64]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[65]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[66]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[67]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[68]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[69]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[70]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[71]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[72]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[73]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[74]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[75]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[76]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[77]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[78]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[79]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[80]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[81]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[82]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MctpEn[83]|0x1 = # MCTP +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[0]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[1]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[2]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[3]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[4]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[5]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[6]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[7]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[8]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[9]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[10]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[11]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[12]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[13]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[14]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[15]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[16]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[17]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[18]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[19]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[20]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[21]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[22]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[23]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[24]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[25]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[26]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[27]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[28]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[29]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[30]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[31]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[32]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[33]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[34]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[35]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[36]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[37]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[38]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[39]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[40]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[41]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[42]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[43]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[44]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[45]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[46]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[47]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[48]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[49]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[50]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[51]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[52]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[53]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[54]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[55]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[56]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[57]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[58]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[59]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[60]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[61]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[62]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[63]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[64]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[65]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[66]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[67]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[68]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[69]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[70]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[71]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[72]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[73]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[74]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[75]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[76]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[77]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[78]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[79]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[80]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[81]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[82]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MsiEn[83]|0x0 = # MSI +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.MultiCastEnable|0x0 = # MultiCast Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NoSnoopRdCfg|0x0 = # NoSnoop Read Config +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NoSnoopWrCfg|0x1 = # NoSnoop Write Config +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[0]|0x= 0 # North TH Mem Buffer Size 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[1]|0x= 0 # North TH Mem Buffer Size 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[2]|0x= 0 # North TH Mem Buffer Size 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg0Size[3]|0x= 0 # North TH Mem Buffer Size 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[0]|0x= 0 # North TH Mem Buffer Size 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[1]|0x= 0 # North TH Mem Buffer Size 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[2]|0x= 0 # North TH Mem Buffer Size 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMemReg1Size[3]|0x= 0 # North TH Mem Buffer Size 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[0]|0x0 = # North Trace Hub Enable Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[1]|0x0 = # North Trace Hub Enable Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[2]|0x0 = # North Trace Hub Enable Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NorthTraceHubMode[3]|0x0 = # North Trace Hub Enable Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[0]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[1]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[2]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[3]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[4]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[5]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[6]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[7]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[8]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[9]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[10]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[11]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[12]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[13]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[14]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[15]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[16]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[17]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[18]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ1[19]|0x16 = # Embar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[0]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[1]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[2]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[3]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[4]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[5]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[6]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[7]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[8]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[9]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[10]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[11]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[12]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[13]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[14]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[15]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[16]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[17]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[18]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2[19]|0x16 = # Embar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[0]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[1]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[2]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[3]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[4]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[5]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[6]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[7]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[8]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[9]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[10]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[11]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[12]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[13]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[14]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[15]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[16]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[17]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[18]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_0[19]|0xc = # Embar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[0]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[1]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[2]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[3]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[4]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[5]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[6]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[7]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[8]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[9]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[10]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[11]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[12]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[13]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[14]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[15]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[16]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[17]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[18]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeEmBarSZ2_1[19]|0xc = # Embar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[0]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[1]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[2]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[3]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[4]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[5]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[6]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[7]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[8]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[9]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[10]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[11]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[12]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[13]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[14]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[15]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[16]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[17]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[18]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar1[19]|0x16 = # Imbar1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[0]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[1]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[2]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[3]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[4]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[5]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[6]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[7]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[8]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[9]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[10]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[11]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[12]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[13]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[14]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[15]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[16]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[17]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[18]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2[19]|0x16 = # Imbar2 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[0]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[1]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[2]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[3]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[4]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[5]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[6]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[7]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[8]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[9]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[10]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[11]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[12]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[13]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[14]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[15]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[16]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[17]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[18]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_0[19]|0xc = # Imbar2_0 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[0]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[1]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[2]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[3]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[4]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[5]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[6]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[7]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[8]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[9]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[10]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[11]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[12]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[13]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[14]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[15]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[16]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[17]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[18]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeImBar2_1[19]|0xc = # Imbar2_1 Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[0]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[1]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[2]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[3]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[4]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[5]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[6]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[7]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[8]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[9]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[10]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[11]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[12]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[13]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[14]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[15]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[16]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[17]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[18]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbBarSizeOverride[19]|0x0 = # Enable NTB BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbLinkBiosTrainEn|0x2 = # NTB Link Train by BIOS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[0]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[1]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[2]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[3]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[4]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[5]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[6]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[7]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[8]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[9]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[10]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[11]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[12]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[13]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[14]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[15]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[16]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[17]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[18]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbPpd[19]|0x0 = # Non-Transparent Bridge PCIe Port Definition +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[0]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[1]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[2]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[3]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[4]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[5]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[6]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[7]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[8]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[9]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[10]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[11]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[12]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[13]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[14]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[15]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[16]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[17]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[18]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbSplitBar[19]|0x0 = # Enable SPLIT BARs +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[0]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[1]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[2]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[3]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[4]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[5]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[6]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[7]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[8]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[9]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[10]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[11]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[12]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[13]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[14]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[15]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[16]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[17]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[18]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.NtbXlinkCtlOverride[19]|0x3 = # Crosslink control Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[0]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[1]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[2]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[3]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[4]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[5]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[6]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[7]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[8]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[9]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[10]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[11]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[12]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[13]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[14]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[15]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[16]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[17]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[18]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[19]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[20]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[21]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[22]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[23]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[24]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[25]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[26]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[27]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[28]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[29]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[30]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[31]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[32]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[33]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[34]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[35]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[36]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[37]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[38]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[39]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[40]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[41]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[42]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[43]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[44]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[45]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[46]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[47]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[48]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[49]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[50]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[51]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[52]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[53]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[54]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[55]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[56]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[57]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[58]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[59]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[60]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[61]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[62]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[63]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[64]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[65]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[66]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[67]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[68]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[69]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[70]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[71]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[72]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[73]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[74]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[75]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[76]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[77]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[78]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[79]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[80]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[81]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[82]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[83]|0x0 = # P2P Memory Read +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x1 = # PCIe Atomic Operation Request Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 = # PCIe Latency Tolerance Reporting +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCUF6Hide|0x0 = # Hide PCU Func 6 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[1]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[2]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[3]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[4]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[5]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[6]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[7]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[8]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[9]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[10]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[11]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[12]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[13]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[14]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[15]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[16]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[17]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[18]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[19]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[20]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[21]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[22]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[23]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[24]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[25]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[26]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[27]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[28]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[29]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[30]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[31]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[32]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[33]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[34]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[35]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[36]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[37]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[38]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[39]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[40]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[41]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[42]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[43]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[44]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[45]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[46]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[47]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[48]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[49]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[50]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[51]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[52]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[53]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[54]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[55]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[56]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[57]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[58]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[59]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[60]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[61]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[62]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[63]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[64]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[65]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[66]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[67]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[68]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[69]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[70]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[71]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[72]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[73]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[74]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[75]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[76]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[77]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[78]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[79]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[80]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[81]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[82]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[83]|0x0 = # Hide Port? +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pci64BitResourceAllocation|0x1= # PCI 64-Bit Resource Allocation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x1 = # PCIe 10-bit Tag Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[0]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[1]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[2]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[3]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[4]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[5]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[6]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[7]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[8]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[9]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[10]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[11]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[12]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[13]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[14]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[15]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[16]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[17]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[18]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[19]|0x0 = # Intel=EF=BF=BD AIC Retimer/AIC SSD HW at Stack5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[0]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[1]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[2]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[3]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[4]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[5]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[6]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[7]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[8]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[9]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[10]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[11]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[12]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[13]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[14]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[15]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[16]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[17]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[18]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICHotPlugEnable[19]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[0]|0x0 = # Port 1A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[1]|0x0 = # Port 1B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[2]|0x0 = # Port 1C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[3]|0x0 = # Port 1D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[4]|0x0 = # Port 2A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[5]|0x0 = # Port 2B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[6]|0x0 = # Port 2C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[7]|0x0 = # Port 2D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[8]|0x0 = # Port 3A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[9]|0x0 = # Port 3B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[10]|0x0 = # Port 3C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[11]|0x0 = # Port 3D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[12]|0x0 = # Port 4A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[13]|0x0 = # Port 4B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[14]|0x0 = # Port 4C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[15]|0x0 = # Port 4D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[16]|0x0 = # Port 5A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[17]|0x0 = # Port 5B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[18]|0x0 = # Port 5C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[19]|0x0 = # Port 5D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[20]|0x0 = # Port 1A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[21]|0x0 = # Port 1B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[22]|0x0 = # Port 1C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[23]|0x0 = # Port 1D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[24]|0x0 = # Port 2A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[25]|0x0 = # Port 2B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[26]|0x0 = # Port 2C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[27]|0x0 = # Port 2D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[28]|0x0 = # Port 3A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[29]|0x0 = # Port 3B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[30]|0x0 = # Port 3C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[31]|0x0 = # Port 3D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[32]|0x0 = # Port 4A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[33]|0x0 = # Port 4B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[34]|0x0 = # Port 4C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[35]|0x0 = # Port 4D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[36]|0x0 = # Port 5A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[37]|0x0 = # Port 5B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[38]|0x0 = # Port 5C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[39]|0x0 = # Port 5D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[40]|0x0 = # Port 1A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[41]|0x0 = # Port 1B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[42]|0x0 = # Port 1C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[43]|0x0 = # Port 1D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[44]|0x0 = # Port 2A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[45]|0x0 = # Port 2B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[46]|0x0 = # Port 2C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[47]|0x0 = # Port 2D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[48]|0x0 = # Port 3A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[49]|0x0 = # Port 3B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[50]|0x0 = # Port 3C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[51]|0x0 = # Port 3D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[52]|0x0 = # Port 4A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[53]|0x0 = # Port 4B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[54]|0x0 = # Port 4C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[55]|0x0 = # Port 4D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[56]|0x0 = # Port 5A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[57]|0x0 = # Port 5B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[58]|0x0 = # Port 5C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[59]|0x0 = # Port 5D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[60]|0x0 = # Port 1A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[61]|0x0 = # Port 1B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[62]|0x0 = # Port 1C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[63]|0x0 = # Port 1D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[64]|0x0 = # Port 2A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[65]|0x0 = # Port 2B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[66]|0x0 = # Port 2C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[67]|0x0 = # Port 2D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[68]|0x0 = # Port 3A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[69]|0x0 = # Port 3B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[70]|0x0 = # Port 3C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[71]|0x0 = # Port 3D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[72]|0x0 = # Port 4A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[73]|0x0 = # Port 4B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[74]|0x0 = # Port 4C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[75]|0x0 = # Port 4D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[76]|0x0 = # Port 5A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[77]|0x0 = # Port 5B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[78]|0x0 = # Port 5C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[79]|0x0 = # Port 5D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAcpiHotPlugEnable|0x0 = # PCIe ACPI Hot Plug +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAllocatingFlow|0x1 = # PCIe Allocating Write Flows +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x2 = # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieBiosTrainEnable|0x1 = # PCIe Train by BIOS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[0]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[1]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[2]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[3]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[4]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[5]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[6]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[7]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[8]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[9]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[10]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[11]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[12]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[13]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[14]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[15]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[16]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[17]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[18]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[19]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[20]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[21]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[22]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[23]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[24]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[25]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[26]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[27]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[28]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[29]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[30]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[31]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[32]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[33]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[34]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[35]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[36]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[37]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[38]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[39]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[40]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[41]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[42]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[43]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[44]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[45]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[46]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[47]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[48]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[49]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[50]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[51]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[52]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[53]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[54]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[55]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[56]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[57]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[58]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[59]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[60]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[61]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[62]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[63]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[64]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[65]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[66]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[67]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[68]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[69]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[70]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[71]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[72]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[73]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[74]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[75]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[76]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[77]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[78]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[79]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[80]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1 = # PCI-E Port Clocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[0]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[1]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[2]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[3]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[4]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[5]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[6]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[7]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[8]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[9]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[10]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[11]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[12]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[13]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[14]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[15]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[16]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[17]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[18]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[19]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[20]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[21]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[22]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[23]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[24]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[25]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[26]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[27]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[28]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[29]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[30]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[31]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[32]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[33]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[34]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[35]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[36]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[37]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[38]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[39]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[40]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[41]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[42]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[43]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[44]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[45]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[46]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[47]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[48]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[49]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[50]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[51]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[52]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[53]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[54]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[55]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[56]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[57]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[58]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[59]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[60]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[61]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[62]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[63]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[64]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[65]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[66]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[67]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[68]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[69]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[70]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[71]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[72]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[73]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[74]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[75]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[76]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[77]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[78]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[79]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[80]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[81]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[82]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDState[83]|0x0 = # PCI-E Port D-state +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[0]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[1]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[2]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[3]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[4]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[5]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[6]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[7]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[8]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[9]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[10]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[11]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[12]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[13]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[14]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[15]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[16]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[17]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[18]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[19]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[20]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[21]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[22]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[23]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[24]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[25]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[26]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[27]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[28]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[29]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[30]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[31]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[32]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[33]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[34]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[35]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[36]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[37]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[38]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[39]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[40]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[41]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[42]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[43]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[44]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[45]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[46]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[47]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[48]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[49]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[50]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[51]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[52]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[53]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[54]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[55]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[56]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[57]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[58]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[59]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[60]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[61]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[62]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[63]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[64]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[65]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[66]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[67]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[68]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[69]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[70]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[71]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[72]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[73]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[74]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[75]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[76]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[77]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[78]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[79]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[80]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[81]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[82]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[83]|0x1 # Data Link Feature Exchange +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x1 = # PCIe Extended Tag Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieGlobalAspm|0x1 = # PCI-E ASPM Support (Global) +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugEnable|0x0 = # PCIe Hot Plug +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[1]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[2]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[3]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[4]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[5]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[6]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[7]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[8]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[9]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[10]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[11]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[12]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[13]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[14]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[15]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[16]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[17]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[18]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[19]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[20]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[21]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[22]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[23]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[24]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[25]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[26]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[27]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[28]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[29]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[30]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[31]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[32]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[33]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[34]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[35]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[36]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[37]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[38]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[39]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[40]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[41]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[42]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[43]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[44]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[45]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[46]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[47]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[48]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[49]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[50]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[51]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[52]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[53]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[54]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[55]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[56]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[57]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[58]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[59]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[60]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[61]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[62]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[63]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[64]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[65]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[66]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[67]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[68]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[69]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[70]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[71]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[72]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[73]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[74]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[75]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[76]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[77]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[78]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[79]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[80]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[81]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[82]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[83]|0x2 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[0]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[1]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[2]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[3]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[4]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[5]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[6]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[7]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[8]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[9]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[10]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[11]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[12]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[13]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[14]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[15]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[16]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[17]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[18]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[19]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[20]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[21]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[22]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[23]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[24]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[25]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[26]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[27]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[28]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[29]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[30]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[31]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[32]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[33]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[34]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[35]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[36]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[37]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[38]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[39]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[40]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[41]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[42]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[43]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[44]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[45]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[46]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[47]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[48]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[49]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[50]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[51]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[52]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[53]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[54]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[55]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[56]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[57]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[58]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[59]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[60]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[61]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[62]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[63]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[64]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[65]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[66]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[67]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[68]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[69]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[70]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[71]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[72]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[73]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[74]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[75]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[76]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[77]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[78]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[79]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[80]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[81]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[82]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[83]|0x4 = # PCI-E Port L1 Exit Latency +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[1]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[2]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[3]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[4]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[5]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[6]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[7]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[8]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[9]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[10]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[11]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[12]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[13]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[14]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[15]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[16]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[17]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[18]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[19]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[20]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[21]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[22]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[23]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[24]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[25]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[26]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[27]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[28]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[29]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[30]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[31]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[32]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[33]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[34]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[35]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[36]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[37]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[38]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[39]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[40]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[41]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[42]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[43]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[44]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[45]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[46]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[47]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[48]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[49]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[50]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[51]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[52]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[53]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[54]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[55]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[56]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[57]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[58]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[59]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[60]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[61]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[62]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[63]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[64]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[65]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[66]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[67]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[68]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[69]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[70]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[71]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[72]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[73]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[74]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[75]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[76]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[77]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[78]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[79]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[80]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[81]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[82]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLinkDis[83]|0x0 = # PCI-E Port Link Disable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieLowLatencyRetimersEnabled|= 0x0 # PCIe Low Latency Retimers +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[0]|0x7 = # DMI Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[1]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[2]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[3]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[4]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[5]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[6]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[7]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[8]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[9]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[10]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[11]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[12]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[13]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[14]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[15]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[16]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[17]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[18]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[19]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[20]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[21]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[22]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[23]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[24]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[25]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[26]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[27]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[28]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[29]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[30]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[31]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[32]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[33]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[34]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[35]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[36]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[37]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[38]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[39]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[40]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[41]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[42]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[43]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[44]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[45]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[46]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[47]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[48]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[49]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[50]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[51]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[52]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[53]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[54]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[55]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[56]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[57]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[58]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[59]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[60]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[61]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[62]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[63]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[64]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[65]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[66]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[67]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[68]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[69]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[70]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[71]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[72]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[73]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[74]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[75]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[76]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[77]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[78]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[79]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[80]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[81]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[82]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[83]|0x7 = # PCI-E Port MPSS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxReadRequestSize|0x5 = # PCIe Max Read Request Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePhyTestMode|0x0 = # PCIe PHY test mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[0]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[1]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[2]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[3]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[4]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[5]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[6]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[7]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[8]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[9]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[10]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[11]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[12]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[13]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[14]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[15]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[16]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[17]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[18]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[19]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[20]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[21]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[22]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[23]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[24]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[25]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[26]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[27]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[28]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[29]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[30]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[31]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[32]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[33]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[34]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[35]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[36]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[37]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[38]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[39]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[40]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[41]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[42]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[43]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[44]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[45]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[46]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[47]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[48]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[49]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[50]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[51]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[52]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[53]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[54]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[55]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[56]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[57]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[58]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[59]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[60]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[61]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[62]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[63]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[64]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[65]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[66]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[67]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[68]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[69]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[70]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[71]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[72]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[73]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[74]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[75]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[76]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[77]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[78]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[79]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[80]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[81]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[82]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[83]|0x1 = # PCI-E Port Clock Gating +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[1]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[2]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[3]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[4]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[5]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[6]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[7]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[8]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[9]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[10]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[11]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[12]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[13]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[14]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[15]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[16]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[17]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[18]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[19]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[20]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[21]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[22]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[23]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[24]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[25]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[26]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[27]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[28]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[29]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[30]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[31]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[32]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[33]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[34]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[35]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[36]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[37]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[38]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[39]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[40]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[41]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[42]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[43]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[44]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[45]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[46]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[47]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[48]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[49]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[50]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[51]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[52]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[53]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[54]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[55]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[56]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[57]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[58]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[59]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[60]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[61]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[62]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[63]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[64]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[65]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[66]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[67]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[68]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[69]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[70]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[71]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[72]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[73]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[74]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[75]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[76]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[77]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[78]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[79]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[80]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[81]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[82]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[83]|0x2 = # PCI-E Port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[0]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[1]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[2]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[3]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[4]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[5]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[6]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[7]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[8]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[9]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[10]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[11]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[12]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[13]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[14]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[15]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[16]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[17]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[18]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[19]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[20]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[21]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[22]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[23]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[24]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[25]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[26]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[27]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[28]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[29]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[30]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[31]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[32]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[33]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[34]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[35]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[36]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[37]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[38]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[39]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[40]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[41]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[42]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[43]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[44]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[45]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[46]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[47]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[48]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[49]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[50]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[51]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[52]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[53]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[54]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[55]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[56]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[57]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[58]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[59]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[60]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[61]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[62]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[63]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[64]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[65]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[66]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[67]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[68]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[69]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[70]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[71]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[72]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[73]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[74]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[75]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[76]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[77]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[78]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[79]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[80]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[81]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[82]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkMaxWidth[83]|0x0 = # Override Max Link Width +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[0]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[1]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[2]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[3]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[4]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[5]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[6]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[7]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[8]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[9]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[10]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[11]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[12]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[13]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[14]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[15]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[16]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[17]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[18]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[19]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[20]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[21]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[22]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[23]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[24]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[25]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[26]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[27]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[28]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[29]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[30]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[31]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[32]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[33]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[34]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[35]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[36]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[37]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[38]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[39]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[40]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[41]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[42]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[43]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[44]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[45]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[46]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[47]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[48]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[49]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[50]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[51]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[52]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[53]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[54]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[55]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[56]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[57]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[58]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[59]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[60]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[61]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[62]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[63]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[64]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[65]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[66]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[67]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[68]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[69]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[70]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[71]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[72]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[73]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[74]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[75]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[76]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[77]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[78]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[79]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[80]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x0 = # PCIe PTM Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 = # Pcie Relaxed Ordering +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 = # PCIe Slot Item Control +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1 = # PCIe Slot 1 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom2|0x1 = # PCIe Slot 2 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom3|0x1 = # PCIe Slot 3 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom4|0x1 = # PCIe Slot 4 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom5|0x1 = # PCIe Slot 5 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom6|0x1 = # PCIe Slot 6 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom7|0x1 = # PCIe Slot 7 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom8|0x1 = # PCIe Slot 8 OpROM +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[1]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[2]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[3]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[4]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[5]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[6]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[7]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[8]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[9]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[10]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[11]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[12]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[13]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[14]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[15]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[16]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[17]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[18]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[19]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[20]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[21]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[22]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[23]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[24]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[25]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[26]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[27]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[28]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[29]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[30]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[31]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[32]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[33]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[34]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[35]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[36]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[37]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[38]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[39]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[40]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[41]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[42]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[43]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[44]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[45]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[46]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[47]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[48]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[49]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[50]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[51]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[52]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[53]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[54]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[55]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[56]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[57]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[58]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[59]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[60]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[61]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[62]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[63]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[64]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[65]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[66]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[67]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[68]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[69]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[70]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[71]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[72]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[73]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[74]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[75]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[76]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[77]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[78]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[79]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[80]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[81]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[82]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieTxRxDetPoll[83]|0x2 = # PCI-E Detect Wait Time +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[0]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[1]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[2]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[3]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[4]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[5]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[6]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[7]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[8]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[9]|0x0= # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[10]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[11]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[12]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[13]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[14]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[15]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[16]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[17]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[18]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[19]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[20]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[21]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[22]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[23]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[24]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[25]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[26]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[27]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[28]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[29]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[30]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[31]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[32]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[33]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[34]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[35]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[36]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[37]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[38]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[39]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[40]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[41]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[42]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[43]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[44]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[45]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[46]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[47]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[48]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[49]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[50]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[51]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[52]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[53]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[54]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[55]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[56]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[57]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[58]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[59]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[60]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[61]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[62]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[63]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[64]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[65]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[66]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[67]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[68]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[69]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[70]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[71]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[72]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[73]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[74]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[75]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[76]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[77]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[78]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[79]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[80]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[81]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[82]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieUnsupportedRequests[83]|0x= 0 # Unsupported Request +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PerformanceTuningMode|0x1 = # Performance Tuning Mode +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[0]|0x0 = # Enable MMIO read cmpl poison for STACK_0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[1]|0x0 = # Enable MMIO read cmpl poison for STACK_1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[2]|0x0 = # Enable MMIO read cmpl poison for STACK_2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[3]|0x0 = # Enable MMIO read cmpl poison for STACK_3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[4]|0x0 = # Enable MMIO read cmpl poison for STACK_4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[5]|0x0 = # Enable MMIO read cmpl poison for STACK_5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[6]|0x0 = # Enable MMIO read cmpl poison for STACK_0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[7]|0x0 = # Enable MMIO read cmpl poison for STACK_1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[8]|0x0 = # Enable MMIO read cmpl poison for STACK_2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[9]|0x0 = # Enable MMIO read cmpl poison for STACK_3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[10]|0x0 = # Enable MMIO read cmpl poison for STACK_4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[11]|0x0 = # Enable MMIO read cmpl poison for STACK_5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[12]|0x0 = # Enable MMIO read cmpl poison for STACK_0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[13]|0x0 = # Enable MMIO read cmpl poison for STACK_1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[14]|0x0 = # Enable MMIO read cmpl poison for STACK_2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[15]|0x0 = # Enable MMIO read cmpl poison for STACK_3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[16]|0x0 = # Enable MMIO read cmpl poison for STACK_4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[17]|0x0 = # Enable MMIO read cmpl poison for STACK_5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[18]|0x0 = # Enable MMIO read cmpl poison for STACK_0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[19]|0x0 = # Enable MMIO read cmpl poison for STACK_1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[20]|0x0 = # Enable MMIO read cmpl poison for STACK_2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[21]|0x0 = # Enable MMIO read cmpl poison for STACK_3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[22]|0x0 = # Enable MMIO read cmpl poison for STACK_4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[23]|0x0 = # Enable MMIO read cmpl poison for STACK_5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1 = # Posted Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PrioritizeTPH|0x0 = # Prioritize TPH +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ProblematicPort|0x0 = # Problematic port +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[2]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[3]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[4]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[5]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[6]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[7]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[8]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[9]|0= x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[10]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[11]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[14]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[15]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[16]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[17]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[18]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[19]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[20]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[21]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[22]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[23]|= 0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [2]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [3]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [4]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [5]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [6]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [7]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [8]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [9]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [10]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [11]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [14]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [15]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [16]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [17]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [18]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [19]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [20]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [21]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [22]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort0Reg2Override= [23]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [2]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [3]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [4]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [5]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [6]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [7]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [8]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [9]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [10]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [11]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [14]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [15]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [16]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [17]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [18]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [19]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [20]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [21]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [22]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerPseudoPort1Reg2Override= [23]|0x0 # - Override +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[0]|0x0 = # Sck0 RP Correctable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[1]|0x0 = # Sck1 RP Correctable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[2]|0x0 = # Sck2 RP Correctable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpCorrectableErrorEsc[3]|0x0 = # Sck3 RP Correctable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[0= ]|0x0 # Sck0 RP Fatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[1= ]|0x0 # Sck1 RP Fatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[2= ]|0x0 # Sck2 RP Fatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableFatalErrorEsc[3= ]|0x0 # Sck3 RP Fatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEs= c[0]|0x0 # Sck0 RP NonFatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEs= c[1]|0x0 # Sck1 RP NonFatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEs= c[2]|0x0 # Sck2 RP NonFatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RpUncorrectableNonFatalErrorEs= c[3]|0x0 # Sck3 RP NonFatal Uncorrectable Err +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RxClockWA|0x0 = # Rx Clock WA +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[0]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[1]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[2]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[3]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[4]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[5]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[6]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[7]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[8]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[9]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[10]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[11]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[12]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[13]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[14]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[15]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[16]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[17]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[18]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[19]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[20]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[21]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[22]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[23]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[24]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[25]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[26]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[27]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[28]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[29]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[30]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[31]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[32]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[33]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[34]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[35]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[36]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[37]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[38]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[39]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[40]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[41]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[42]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[43]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[44]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[45]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[46]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[47]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[48]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[49]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[50]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[51]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[52]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[53]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[54]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[55]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[56]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[57]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[58]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[59]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[60]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[61]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[62]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[63]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[64]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[65]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[66]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[67]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[68]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[69]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[70]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[71]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[72]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[73]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[74]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[75]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[76]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[77]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[78]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[79]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[80]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[81]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[82]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SERRE[83]|0x0 = # SERRE +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[1]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[2]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[3]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[4]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[5]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[6]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[7]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[8]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[9]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[10]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[11]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[12]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[13]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[14]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[15]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[16]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[17]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[18]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[19]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[20]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[21]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[22]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[23]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[24]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[25]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[26]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[27]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[28]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[29]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[30]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[31]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[32]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[33]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[34]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[35]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[36]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[37]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[38]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[39]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[40]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[41]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[42]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[43]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[44]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[45]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[46]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[47]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[48]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[49]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[50]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[51]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[52]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[53]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[54]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[55]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[56]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[57]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[58]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[59]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[60]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[61]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[62]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[63]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[64]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[65]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[66]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[67]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[68]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[69]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[70]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[71]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[72]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[73]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[74]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[75]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[76]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[77]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[78]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[79]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[80]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[81]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[82]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SLOTHPSUP[83]|0x0 = # Surprise Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[0]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[1]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[2]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[3]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[4]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[5]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[6]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[7]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[8]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[9]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[10]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[11]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[12]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[13]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[14]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[15]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[16]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[17]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[18]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[19]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[20]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[21]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[22]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[23]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[24]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[25]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[26]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[27]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[28]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[29]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[30]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[31]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[32]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[33]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[34]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[35]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[36]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[37]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[38]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[39]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[40]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[41]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[42]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[43]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[44]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[45]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[46]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[47]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[48]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[49]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[50]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[51]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[52]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[53]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[54]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[55]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[56]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[57]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[58]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[59]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[60]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[61]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[62]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[63]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[64]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[65]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[66]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[67]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[68]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[69]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[70]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[71]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[72]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[73]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[74]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[75]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[76]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[77]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[78]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[79]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[80]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[81]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[82]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SRIS[83]|0x0 = # SRIS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[0]|0x0= # Sierra Peak Memory Region Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[1]|0x0= # Sierra Peak Memory Region Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[2]|0x0= # Sierra Peak Memory Region Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SierraPeakMemBufferSize[3]|0x0= # Sierra Peak Memory Region Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS46|0x0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SkipRetimersDetection|0x0 = # Skip PCIe retimers detection +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SnoopResponseHoldOff|0x9 = # Snoop Response Hold Off +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.StopAndScream|0x0 = # PCIE Stop & Scream Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[0]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[1]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[2]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[3]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[4]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[5]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[6]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[7]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[8]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[9]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[10]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[11]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[12]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[13]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[14]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[15]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[16]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[17]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[18]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[19]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[20]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[21]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[22]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[23]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[24]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[25]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[26]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[27]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[28]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[29]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[30]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[31]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[32]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[33]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[34]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[35]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[36]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[37]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[38]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[39]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[40]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[41]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[42]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[43]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[44]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[45]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[46]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[47]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[48]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[49]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[50]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[51]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[52]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[53]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[54]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[55]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[56]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[57]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[58]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[59]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[60]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[61]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[62]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[63]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[64]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[65]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[66]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[67]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[68]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[69]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[70]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[71]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[72]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[73]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[74]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[75]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[76]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[77]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[78]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[79]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[80]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[81]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[82]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.TXEQ[83]|0x0 = # Alternate TxEq +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[0]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[1]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[2]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[3]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[4]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[5]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[6]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[7]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[8]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[9]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[10]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[11]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[12]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[13]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[14]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[15]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[16]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[17]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[18]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[19]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[20]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[21]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[22]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[23]|0x2 = # CfgBar attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[0]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[1]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[2]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[3]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[4]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[5]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[6]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[7]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[8]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[9]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[10]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[11]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[12]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[13]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[14]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[15]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[16]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[17]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[18]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[19]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[20]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[21]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[22]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[23]|0x19 = # CfgBar size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[0]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[1]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[2]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[3]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[4]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[5]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[6]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[7]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[8]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[9]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[10]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[11]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[12]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[13]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[14]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[15]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[16]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[17]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[18]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[19]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[20]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[21]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[22]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDDirectAssign[23]|0x0 = # VMD for Direct Assign +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[0]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[1]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[2]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[3]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[4]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[5]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[6]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[7]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[8]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[9]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[10]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[11]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[12]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[13]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[14]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[15]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[16]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[17]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[18]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[19]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[20]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[21]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[22]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDEnabled[23]|0x0 = # Enable/Disable VMD +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[0]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[1]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[2]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[3]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[4]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[5]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[6]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[7]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[8]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[9]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[10]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[11]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[12]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[13]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[14]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[15]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[16]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[17]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[18]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[19]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[20]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[21]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[22]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDHotPlugEnable[23]|0x0 = # Hot Plug Capable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[0]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[1]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[2]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[3]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[4]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[5]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[6]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[7]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[8]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[9]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[10]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[11]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[12]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[13]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[14]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[15]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[16]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[17]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[18]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[19]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[20]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[21]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[22]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar1Attr[23]|0x0 = # MemBar1 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[0]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[1]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[2]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[3]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[4]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[5]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[6]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[7]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[8]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[9]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[10]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[11]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[12]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[13]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[14]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[15]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[16]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[17]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[18]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[19]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[20]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[21]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[22]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[23]|0x1 = # MemBar2 attribute +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[0]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[1]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[2]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[3]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[4]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[5]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[6]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[7]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[8]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[9]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[10]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[11]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[12]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[13]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[14]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[15]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[16]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[17]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[18]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[19]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[20]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[21]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[22]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[23]|0x19 = # MemBar1 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[0]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[1]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[2]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[3]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[4]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[5]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[6]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[7]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[8]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[9]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[10]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[11]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[12]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[13]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[14]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[15]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[16]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[17]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[18]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[19]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[20]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[21]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[22]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[23]|0x14 = # MemBar2 size +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[0]|0x0 = # PCH Root Port 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[1]|0x0 = # PCH Root Port 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[2]|0x0 = # PCH Root Port 2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[3]|0x0 = # PCH Root Port 3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[4]|0x0 = # PCH Root Port 4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[5]|0x0 = # PCH Root Port 5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[6]|0x0 = # PCH Root Port 6 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[7]|0x0 = # PCH Root Port 7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[8]|0x0 = # PCH Root Port 8 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[9]|0x0 = # PCH Root Port 9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[10]|0x0 = # PCH Root Port 10 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[11]|0x0 = # PCH Root Port 11 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[12]|0x0 = # PCH Root Port 12 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[13]|0x0 = # PCH Root Port 13 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[14]|0x0 = # PCH Root Port 14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[15]|0x0 = # PCH Root Port 15 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[16]|0x0 = # PCH Root Port 16 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[17]|0x0 = # PCH Root Port 17 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[18]|0x0 = # PCH Root Port 18 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[19]|0x0 = # PCH Root Port 19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[20]|0x0 = # PCH Root Port 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[21]|0x0 = # PCH Root Port 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[22]|0x0 = # PCH Root Port 2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[23]|0x0 = # PCH Root Port 3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[24]|0x0 = # PCH Root Port 4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[25]|0x0 = # PCH Root Port 5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[26]|0x0 = # PCH Root Port 6 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[27]|0x0 = # PCH Root Port 7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[28]|0x0 = # PCH Root Port 8 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[29]|0x0 = # PCH Root Port 9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[30]|0x0 = # PCH Root Port 10 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[31]|0x0 = # PCH Root Port 11 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[32]|0x0 = # PCH Root Port 12 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[33]|0x0 = # PCH Root Port 13 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[34]|0x0 = # PCH Root Port 14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[35]|0x0 = # PCH Root Port 15 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[36]|0x0 = # PCH Root Port 16 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[37]|0x0 = # PCH Root Port 17 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[38]|0x0 = # PCH Root Port 18 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[39]|0x0 = # PCH Root Port 19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[40]|0x0 = # PCH Root Port 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[41]|0x0 = # PCH Root Port 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[42]|0x0 = # PCH Root Port 2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[43]|0x0 = # PCH Root Port 3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[44]|0x0 = # PCH Root Port 4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[45]|0x0 = # PCH Root Port 5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[46]|0x0 = # PCH Root Port 6 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[47]|0x0 = # PCH Root Port 7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[48]|0x0 = # PCH Root Port 8 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[49]|0x0 = # PCH Root Port 9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[50]|0x0 = # PCH Root Port 10 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[51]|0x0 = # PCH Root Port 11 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[52]|0x0 = # PCH Root Port 12 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[53]|0x0 = # PCH Root Port 13 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[54]|0x0 = # PCH Root Port 14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[55]|0x0 = # PCH Root Port 15 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[56]|0x0 = # PCH Root Port 16 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[57]|0x0 = # PCH Root Port 17 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[58]|0x0 = # PCH Root Port 18 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[59]|0x0 = # PCH Root Port 19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[60]|0x0 = # PCH Root Port 0 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[61]|0x0 = # PCH Root Port 1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[62]|0x0 = # PCH Root Port 2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[63]|0x0 = # PCH Root Port 3 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[64]|0x0 = # PCH Root Port 4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[65]|0x0 = # PCH Root Port 5 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[66]|0x0 = # PCH Root Port 6 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[67]|0x0 = # PCH Root Port 7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[68]|0x0 = # PCH Root Port 8 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[69]|0x0 = # PCH Root Port 9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[70]|0x0 = # PCH Root Port 10 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[71]|0x0 = # PCH Root Port 11 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[72]|0x0 = # PCH Root Port 12 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[73]|0x0 = # PCH Root Port 13 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[74]|0x0 = # PCH Root Port 14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[75]|0x0 = # PCH Root Port 15 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[76]|0x0 = # PCH Root Port 16 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[77]|0x0 = # PCH Root Port 17 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[78]|0x0 = # PCH Root Port 18 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPchPortEnable[79]|0x0 = # PCH Root Port 19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[4]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[5]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[6]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[7]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[8]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[9]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[10]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[11]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[12]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[13]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[14]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[15]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[16]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[17]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[18]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[19]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[20]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[21]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[22]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[23]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[28]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[29]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[30]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[31]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[32]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[33]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[34]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[35]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[36]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[37]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[38]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[39]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[40]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[41]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[42]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[43]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[44]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[45]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[46]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[47]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[52]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[53]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[54]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[55]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[56]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[57]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[58]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[59]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[60]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[61]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[62]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[63]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[64]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[65]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[66]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[67]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[68]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[69]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[70]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[71]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[76]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[77]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[78]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[79]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[80]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[81]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[82]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[83]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[84]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[85]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[86]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[87]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[88]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[89]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[90]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[91]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[92]|0x0 = # VMD port A +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[93]|0x0 = # VMD port B +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[94]|0x0 = # VMD port C +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDPortEnable[95]|0x0 = # VMD port D +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VTdSupport|0x1 = # Intel=EF=BF=BD VT for Directed I/O +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[0]|0x0 = # Intel=EF=BF=BD VT-d Disable Mask +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[1]|0x0 = # Intel=EF=BF=BD VT-d Disable Mask +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[2]|0x0 = # Intel=EF=BF=BD VT-d Disable Mask +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdDisabledBitmask[3]|0x0 = # Intel=EF=BF=BD VT-d Disable Mask +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit0|0x0 = # Source Validation +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit1|0x0 = # Translation Blocking +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit2|0x1 = # P2P Request Redirect +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit3|0x1 = # P2P Completion Redirect +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlBit4|0x1 = # Upstream Forwarding Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdPciAcsCtlWaEn|0x0 = # PCIe ACSCTL +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.X2ApicOptOut|0x0 = # X2APIC Opt Out +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Xppdef|0x0 = # Retimer workaround +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADDDCEn|0x0 = # ADDDC Sparing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 = # ADR Data Save Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 = # Enable ADR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 = # Enable ADDDC Error Injection +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186a0= # Adv MemTest Pause +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3cf0 = # Adv MemTest tREFI +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xa = # Adv MemTest tWR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondVdd|0x4c4 = # Adv MemTest VDD Level +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1 = # Adv MemTest Conditions +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestOptions|0x0 = # Adv MemTest Options +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestPpr|0x1 = # Adv MemTest PPR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[0]|0xfff= fffff # Rank location entry 0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[1]|0xfff= fffff # Rank location entry 1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[2]|0xfff= fffff # Rank location entry 2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[3]|0xfff= fffff # Rank location entry 3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[4]|0xfff= fffff # Rank location entry 4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[5]|0xfff= fffff # Rank location entry 5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[6]|0xfff= fffff # Rank location entry 6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankList[7]|0xfff= fffff # Rank location entry 7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRankListNumEntrie= s|0x0 # Number of Ranks to Test +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestResetList|0x0 = # Adv MemTest Reset Failure Tracking List +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestRetryAfterRepair|= 0x1 # Adv MemTest Retry After Repair +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AepNotSupportedException|0x= 0 # 100 series PMem Not Supported Exception +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ApdEn|0x0 = # APD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AppDirectMemoryHole|0x0 = # App Direct Memory Hole +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBoot|0x1 = # Attempt Fast Boot +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBootCold|0x1 = # Attempt Fast Cold Boot +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS92|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS99|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS100|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS101|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS104|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS89|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS93|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS102|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS103|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS91|0x10 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS88|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS90|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS95|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS96|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS94|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS97|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS98|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Blockgnt2cmd1cyc|0x1 = # BLOCK GNT2CMD1CYC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.BwLimitTfOvrd|0x0 = # Override BW_LIMIT_TF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CacheMemType|0x0 = # 2LM Memory Type +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkMode|0x2 = # CK in SR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeIdleTimer|0x14 = # CKE Idle Timer +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeProgramming|0x0 = # CKE Throttling +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdNormalization|0x1 = # Command Normalization +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdTxEqCalibration|0x0 = # CMD Tx Eq Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdVrefEnable|0x1 = # Command Vref Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmiInitOption|0x0 = # CMI Init Option +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmsEnableDramPm|0x1 = # CMS ENABLE DRAM PM +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ColumnCorrectionDisable|0x0= # Column Correction Disable +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRate|0x14 = # Custom Refresh Rate +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRateEn|0x0 = # Custom Refresh Enable +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DataDllOff|0x1 = # Data DLL Off EN +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerLimit|0x3a= 98 # 200 Series PMem Average Power Limit (in mW) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerTimeConsta= nt|0x6 # 200 Series PMem Turbo Average Power Time Constan= t (in mSec) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmEccModeSwitch|0x1 = # ECC Mode Switch +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbAveragePowerTimeCon= stant|0x3a98 # 200 Series PMem Memory Bandwidth Boost(MBB) Aver= age Power Time Constant (in mSec) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbFeature|0x1 = # 200 Series PMem Turbo/Memory Bandwidth Boost(MBB= ) Feature +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbMaxPowerLimit|0x465= 0 # 200 Series PMem Turbo/Memory Bandwidth Boost Fea= ture(MBB) Power Limit (in mW) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdjcTraining|0x1 = # DDJC Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrCacheSize|0xff = # DDR Cache Size +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrFreqLimit|0x0 = # Memory Frequency +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMemoryType|0x2 = # Memory Type +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1 = # PMem CKE +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtSrefEn|0x0 = # PMem SELF REFRESH +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DfeGainBias|0x0 = # DfeGainBias +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS127|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS121|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS135|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS129|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS120|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS136|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS139|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS132|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS63|0x7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS62|0xf +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS67|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS65|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS66|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS73|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS109|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS78|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS124|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS112|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS110|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS111|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS140|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS141|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS146|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS147|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS148|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS131|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS57|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS56|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS61|0x1ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS51|0x1f +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS52|0x7f +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS50|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS60|0x3f +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS58|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS59|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS55|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS53|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS54|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS70|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS79|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS119|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS118|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS137|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS128|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS123|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x8 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS125|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7ff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS126|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS134|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS130|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS145|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS49|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS69|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS133|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DieSparing|0x1 = # Set PMem Die Sparing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DisableDirForAppDirect|0x0 = # Snoopy mode for AD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Disddrtopprd|0x1 = # Disable DDRT DIMM OPPRD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplEnable|0x1 = # DRAM RAPL +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplExtendedRange|0x1 = # DRAM RAPL Extended Range +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplPwrLimitLockCsr|0x1= # DRAM RAPL Power Limit Lock CSR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRonEn|0x0 = # DRAM RON Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DutyCycleTraining|0x1 = # Duty Cycle Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EadrCacheFlushMode|0x1 = # CPU Cache Flush Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EadrSupport|0x0 = # eADR Support +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccEnable|0x1 = # ECC Enable +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccSupport|0x1 = # ECC Check +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EliminateDirectoryInFarMemo= ry|0x1 # Snoopy mode for 2LM +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS84|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS85|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS87|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableNgnBcomMargining|0x0 = # DDRT DIMM BCOM Margining Support +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableTapSweep|0x0 = # Enable Tap Sweep +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnableTwoWayNmCache|0x0 = # Enable biased 2-way near memory cache +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePOR|0x0 = # Enforce POR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePopulationPor|0x1 = # Enforce Population POR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EsddcEn|0x0 = # Enhanced SDDC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ExtendedType17|0x1 = # Extended Type 17 Structure +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FactoryResetClear|0x0 = # PMem Factory Reset/Clear +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FadrSupport|0x0 = # fADR Support +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastGoConfig|0x6 = # PMem FastGo Configuration +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastZeroMemSupport|0x0 = # Boot-time Fast Zero Memory +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FourxRefreshValue|0x5f = # Set FOURx Temperature Refresh +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HalfxRefreshValue|0x19 = # Set Halfx Temperature Refresh +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HwMemTest|0x1 = # MemTest +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LatchSystemShutdownState|0x= 1 # PMem Latch System Shutdown State +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LegacyADRModeEn|0x0 = # Legacy ADR Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LegacyRmt|0x0 = # Rank Margin Tool +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LockNgnCsr|0x0 = # Lock PMem CSRs +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmBacksideVrefEn|0x1 = # LRDIMM Backside Vref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRdVrefEn|0x1 = # LRDIMM Read Vref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRxDqCentering|0x1 = # LRDIMM RX DQ Centering +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmTxDqCentering|0x1 = # LRDIMM TX DQ Centering +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmWrVrefEn|0x1 = # LRDIMM Write Vref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrdimmDbDfeTraining|0x1 = # LRDIMM DB DFE Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LsxImplementation|0x1 = # LSx implementation +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.McRonEn|0x0 = # MC RON Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MdllOffEn|0x1 = # MDLL OFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemCeFloodPolicy|0x2 = # Memory Correctable Error Flood Policy +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotIn|0x1 = # MemHot Input Pin +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|= 0x1 # MEMHOT Output Throttling Mode Options +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOut|0x1 = # MemHot Output Pin +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestLoops|0x1 = # MemTest Loops +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestOnColdFastBoot|0x0 = # MemTest On Cold Fast Boot +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTripReporting|0x0 = # MEMTRIP REPORTING +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MinNormalMemSize|0x2 = # Minimum System Memory Size +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MultiThreaded|0x1 = # Multi-Threaded MRC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NfitPublishMailboxStructs|0= x0 # NVDIMM Mailbox in NFIT +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnArsPublish|0x1 = # Publish ARS capability +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnCmdTime|0x2 = # PMem CMD Time +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnDebugLock|0x0 = # Debug lock for PMem +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccCorr|0x2 = # PMem ECC Correctable error +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccExitCorr|0x2 = # PMem ECC Write Retry Flow Exit +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccRdChk|0x1 = # PMem ECC Read Check +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccWrChk|0x2 = # PMem ECC Write Check +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NonPreferredWayMask|0x1 = # Non-preferred way mask +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NsddcEn|0x1 = # New SDDC Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvDimmEnergyPolicy|0x0 = # NVDIMM Energy Policy +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusMaxAccessTime|0x= 15e # SMBus Max Access Time +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusReleaseDelay|0x9= 6 # SMBus Release Delay +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmMediaStatusException|0x1= # PMem MediaStatus Exception +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmQos|0x0 = # PMem QoS +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPerfConfig|0x0 = # PMem Performance Setting +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPowerCyclePolicy|0x1= # Power Cycle on PMem Surprise Clock Stop +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffPkgMemToMemTrip|0x0 = # OFF PKG MEM TO MEMTRIP +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffPkgMemToThermTrip|0x0 = # OFF PKG MEM TO THERMTRIP +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdAll|0x64 = # Offset CmdAll +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdVref|0x64 = # Offset CmdVref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCtlAll|0x64 = # Offset CtlAll +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRecEn|0x64 = # Offset RecEnDelay +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxDq|0x64 = # Offset RxDq +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxVref|0x64 = # Offset RxVref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxDq|0x64 = # Offset TxDq +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxVref|0x64 = # Offset TxVref +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OppSrefEn|0x0 = # Opportunistic SR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PagePolicy|0x2 = # Page Policy +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PanicWm|0x0 = # Refresh Watermarks +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PartialMirrorUefi|0x0 = # UEFI ARM Mirror +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PartialMirrorUefiPercent|0x= 0 # ARM Mirror percentage +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrub|0x2 = # Patrol Scrub +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubAddrMode|0x1 = # Patrol Scrub Address Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubDuration|0x18 = # Patrol Scrub Interval +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PclsEn|0x1 = # Partial Cache Line Sparing PCLS +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcomp|0x2 = # Periodic Rcomp +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcompInterval|0xf = # Periodic Rcomp Interval +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PkgcSrefEn|0x1 = # PKGC SREF EN +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PlusOneEn|0x0 = # Plus One | SDDC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PmemCaching|0x0 = # AppDirect cache +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PpdEn|0x1 = # PPD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PreferredReadFirst|0x1 = # Preferred read first +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PxcTraining|0x1 = # PXC Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RankSparing|0x0 = # Memory Rank Sparing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReadPreamble|0xff = # Read Preamble TCLK +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RecEnDelayAverage|0x2 = # Rank Switch Configuration +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RmtMinimumMarginCheck|0x1 = # RMT Minimum Margin Check +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS86|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RmtOnColdFastBoot|0x0 = # RMT On Cold Fast Boot +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RoundTripLatency|0x1 = # RoundTrip Latency Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxCtleTrnEn|0x1 = # Rx CTLE Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxDfe|0x0 = # Rx Dfe Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxOdtEn|0x1 = # Rx ODT Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SaiPolicyGroupWaBiosW|0x0 = # Enable Pcode WA for SAI PG +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEn|0x1 = # Data Scrambling for DDR4/5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEnDDRT|0x1 = # Data Scrambling for PMem +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedHigh|0xd395 = # Scrambling Seed High +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedLow|0xa02b = # Scrambling Seed Low +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SetMemTested|0x1 = # Allow Untested Memory for DXE Drivers +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ShortStroke2GB|0x0 = # 2GB Short Stroke Configuration +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmartTestKey|0x0 = # SmartTestKey +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmbSpdAccess|0x0 = # SPD-SMBUS Access +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 = # Sparing SW Error Match Threshold +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintEn|0x0 = # SPD Print +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintLength|0x0 = # SPD Print Length +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1 = # Publish SRAT +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SratCpuHotPlug|0x0 = # SRAT CPU Hot Plug +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SratMemoryHotPlug|0x0 = # SRAT Memory Hot Plug +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SrefProgramming|0x0 = # SREF Feature +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1End|0xa = # Tap1End +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Size|0x1 = # Tap1Step +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Start|0x8c = # Tap1Start +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2End|0xf = # Tap2End +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Size|0x1 = # Tap2Step +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Start|0x73 = # Tap2Start +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3End|0xc = # Tap3End +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Size|0x1 = # Tap3Step +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Start|0x70 = # Tap3Start +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4End|0x9 = # Tap4End +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Size|0x1 = # Tap4Step +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Start|0x6d = # Tap4Start +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TcoCompTraining|0x0 = # Tco Comp Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TempRefreshOption|0x0 = # Select Temperature Refresh Value +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrainingCompOptions|0x0 = # Training Compensation Options Values +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrainingResultOffsetFunctio= nEnable|0x0 # Training Result Offset +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiDelay|0x0 = # Additional TREFI Delay +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiNumofRank|0x1 = # The Number of Ranks for Stagger TREFI +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiPerChannel|0x0 = # Stagger TREFI Per Available Channel +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TriggerSWErrThEn|0x0 = # Trigger SW Error Threshold +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TwoxRefreshValue|0x53 = # Set TWOx Temperature Refresh +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TxRiseFallSlewRate|0x2 = # TX Rise Fall Slew Rate Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Vdd|0x4b0 = # Memory Voltage +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.WrCRC|0x0 = # WR CRC feature Control +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.WritePreamble|0xff = # Write Preamble TCLK +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.XMPMode|0x0 = # XMP Profile +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.XMPProfilesSup|0x0 = # XMP Profiles Supported +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableError|0x0 = # Allow Memory Training Correctable Error +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableMemTestErro= r|0x1 # Allow Memory Test Correctable Error +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.bdatEn|0x1 = # BDAT +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.check_platform_detect|0x0 = # Check PlatformDetectADR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.check_pm_sts|0x0 = # Check PCH_PM_STS +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.cmdSetupPercentOffset|0x32 = # Cmd Setup % Offset +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.commandTiming|0x0 = # Command Timing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS83|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS77|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS72|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS68|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS106|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS108|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS105|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS71|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[0]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[1]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[2]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[3]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[4]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[5]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[6]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[7]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[8]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[9]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[10]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[11]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[12]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[13]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[14]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS74[15]|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[3]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[4]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[6]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[7]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[9]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[10]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[12]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[13]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[15]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[16]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[18]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[19]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[21]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[22]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[24]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[25]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[27]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[28]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[30]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[31]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[33]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[34]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[36]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[37]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[39]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[40]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[42]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[43]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[45]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[46]|0xff +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS82|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS107|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.dimmIsolation|0x0 = # DIMM Isolation Enable +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.dllResetTestLoops|0x0 = # DLL Reset Test +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eraseArmNVDIMMS|0x1 = # Erase-Arm NVDIMMs +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eyeDiagram|0x0 = # Eye Diagrams +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.haltOnMemErr|0x1 = # Halt on mem Training Error +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.iModeTraining|0x1 = # iMode Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.imcBclk|0x0 = # IMC BCLK +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.interNVDIMMS|0x1 = # Interleave NVDIMMs +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHi|0x29 = # Leaky bucket high bit +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHour|0x18 = # Leaky bucket time window based interface Hour +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktLo|0x28 = # Leaky bucket low bit +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktMinute|0x0 = # Leaky bucket time window based interface Minute +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktTimeWindow|0x0 = # Leaky bucket time window based interface +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.logParsing|0x0 = # Enhanced Log Parsing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.lrdimmModuleDelay|0x0 = # LRDIMM Module Delay +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mdllSden|0x2 = # MDLL Off +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlows|0xffffffff = # Mem Flows +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt|0xffffffff = # Mem FlowsExt +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt2|0xffffffff = # Mem FlowsExt2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt3|0xffffffff = # Mem FlowsExt3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memInterleaveGran1LM|0x3 = # 1LM Memory Interleave Granularity +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memhotSupport|0x1 = # MEMHOT Throttling Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mrcRepeatTest|0x0 = # DDR Cycling +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiSparingRanks|0x2 = # Multi Rank Sparing +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400 = # Normal Operation Duration +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1 = # One Rank Timing Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1 = # Opp read during WMM +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsad0|0x0 = # Mirror TAD0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[0]|0x0 = # Partial Mirror 1 Size (GB) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[1]|0x0 = # Partial Mirror 2 Size (GB) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[2]|0x0 = # Partial Mirror 3 Size (GB) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[3]|0x0 = # Partial Mirror 4 Size (GB) +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1 = # PDA +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprErrInjTest|0x0 = # PPR Error Injection test +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2 = # PPR Type +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1 = # MRC Promote Warnings +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1 = # Promote Warnings +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1 = # Read Vref Centering +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2 = # 2x Refresh Enable +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.restoreNVDIMMS|0x1 = # Restore NVDIMMs +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseAllDIMMs|0x0 = # Erase All DIMMs +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[0]|0x0 = # S0 CH0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[1]|0x0 = # S0 CH1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[2]|0x0 = # S0 CH2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[3]|0x0 = # S0 CH3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[4]|0x0 = # S0 CH4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[5]|0x0 = # S0 CH5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[6]|0x0 = # S0 CH6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[7]|0x0 = # S0 CH7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[8]|0x0 = # S1 CH0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[9]|0x0 = # S1 CH1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[10]|0x0= # S1 CH2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[11]|0x0= # S1 CH3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[12]|0x0= # S1 CH4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[13]|0x0= # S1 CH5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[14]|0x0= # S1 CH6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[15]|0x0= # S1 CH7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[16]|0x0= # S2 CH0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[17]|0x0= # S2 CH1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[18]|0x0= # S2 CH2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[19]|0x0= # S2 CH3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[20]|0x0= # S2 CH4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[21]|0x0= # S2 CH5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[22]|0x0= # S2 CH6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[23]|0x0= # S2 CH7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[24]|0x0= # S3 CH0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[25]|0x0= # S3 CH1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[26]|0x0= # S3 CH2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[27]|0x0= # S3 CH3 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[28]|0x0= # S3 CH4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[29]|0x0= # S3 CH5 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[30]|0x0= # S3 CH6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.setSecureEraseSktCh[31]|0x0= # S3 CH7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.smbSpeed|0x2 = # SMB Clock Frequency +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spareErrTh|0x7fff = # Correctable Error Threshold +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spdCrcCheck|0x2 = # SPD CRC Check +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tCAS|0x0 = # CAS Latency +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tCWL|0x0 = # tCWL +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tFAW|0x0 = # tFAW +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRAS|0x0 = # tRAS +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRC|0x0 = # tRC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRCD|0x0 = # tRCD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tREFI|0x0 = # Refresh Rate +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRFC|0x0 = # tRFC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRP|0x0 = # tRP +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRRD|0x0 = # tRRD +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRRD_L|0x0 = # tRRD_L +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRTP|0x0 = # tRTP +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWR|0x0 = # tWR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWTR|0x0 = # tWTR +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x= 2 # Throttling Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x0 = # Correctable Error Time Window +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1 = # Turnaround Time Optimization +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1 = # Turnaround Time Optimization PMem +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1 = # Tx Eq Training +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1 = # Volatile Memory Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1 = # Write Vref Centering +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1 = # Bus Resources Allocation Ratio +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1 = # Bus Resources Allocation Ratio +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[2]|0x1 = # Bus Resources Allocation Ratio +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[3]|0x1 = # Bus Resources Allocation Ratio +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkSpeed|0x3 = # Current UPI Link Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkVnaOverride|0x= 7f # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiPortDisable|0x0 = # Link Disable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.D2KCreditConfig|0x2 = # D2K Credit configuration +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Degrade4SPreference|0x0 = # Degraded 4S Topology Preference +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DegradePrecedence|0x0 = # Degrade Precedence +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS154|0x5 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS159|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS176|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS181|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS182|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS180|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS178|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS179|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS183|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS167|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS168|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS158|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS164|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS157|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS163|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS151|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS156|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS162|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS187|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS186|0xffffffff +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS152|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS153|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS169|0x4 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS185|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS173|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS177|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS160|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS161|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS170|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS171|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS172|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS184|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS174|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS155|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS165|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS166|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS175|0x5 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DirectoryModeEn|0x2 = # Directory Mode Enable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IoDcMode|0x1 = # IO Directory Cache (IODC) +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IrqThreshold|0x1 = # Local/Remote Threshold +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationEn|0x2 = # UPI Adaptation Enable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationSpeed|0x3 = # UPI Adaptation Speed +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCpuSktHotPlugTopology|0x= 0 # CPU Hot Plug Topology +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCrcMode|0x2 = # CRC Mode +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiFailoverEn|0x2 = # UPI Dynamic Link Width Reduction Support +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLbEn|0x0 = # UPI Load Board for Failed Links +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL0pEn|0x2 = # Link L0p Enable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL1En|0x2 = # Link L1 Enable +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkVnaOverride|0x7f = # UPI VNA Credit Override +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiPrefetchEn|0x2 = # KTI Prefetch +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiSkuMismatchCheck|0x1 = # CPU SKU Type Mismatch check +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LLCDeadLineAlloc|0x1 = # LLC dead line alloc +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LegacyVgaSoc|0x0 = # Legacy VGA Socket +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LegacyVgaStack|0x0 = # Legacy VGA Stack +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.MbeBwCal|0x3 = # MBA BW Calibration +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.P2pRelaxedOrdering|0x0 = # PCIe Remote P2P Relaxed Ordering +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiCpuSktHotPlugEn|0x0 = # CPU Hot Plug +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeed|0x3 = # Link Frequency Select +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeedMode|0x1 = # Link Speed Mode +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.RdCurForXptPrefetchEn|0x2 = # RdCur for XPT Prefetch +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SncEn|0x0 = # SNC (Sub NUMA) +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SnoopAllCores|0x2 = # Snoop All Cores Configuration +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SnoopThrottleConfig|0x4 = # Snoop Throttle Configuration +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.SplitLock|0x0 = # SplitLock +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.StaleAtoSOptEn|0x2 = # Stale AtoS +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremEmpty|0x1 = # Loctorem Thresholds Empty +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremNorm|0x1 = # Loctorem Thresholds Normal +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TscSyncEn|0x2 = # TSC Sync support +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptPrefetchEn|0x2 = # XPT Prefetch +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptRemotePrefetchEn|0x2 = # XPT Remote Prefetch +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS3Enable|0x0 = # ACPI S3 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS4Enable|0x0 = # ACPI S4 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[0= ]|0x0 # Allow LP state +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[1= ]|0x0 # Allow LP state +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[2= ]|0x0 # Allow LP state +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AllowLpStateMdfs[3= ]|0x0 # Allow LP state +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AltEngPerfBIAS|0x7= # ENERGY_PERF_BIAS_CFG mode +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxIccpLevel|0x1 = # AVX ICCP pre-grant level +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxLicensePreGrant= |0x0 # AVX Licence Pre-Grant Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxSupport|0x1 = # AVX Support +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.BootPState|0x0 = # Boot performance mode +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoDemotion|0x1= # CPU C1 auto demotion +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoUnDemotion|0= x1 # CPU C1 auto undemotion +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C2C3TT|0x0 = # C2C3TT +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C6Enable|0xff = # CPU C6 report +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlM= ultiplier[0]|0x0 # MULTIPLIER: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlM= ultiplier[1]|0x0 # MULTIPLIER: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlM= ultiplier[2]|0x0 # MULTIPLIER: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alid[0]|0x0 # VALID: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alid[1]|0x0 # VALID: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alid[2]|0x0 # VALID: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alue[0]|0x0 # VALUE: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alue[1]|0x0 # VALUE: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CStateLatencyCtrlV= alue[2]|0x0 # VALUE: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLevel|0x0= # AVX P1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLock|0x1 = # Config TDP Lock +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentConfig|0x0 = # Current Limit Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentLimit|0x438= # Current Limitation +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.DynamicIss|0x0 = # Dynamic SST-PP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.DynamicL1|0x0 = # Dynamic L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EETurboDisable|0x0= # Energy Efficient Turbo +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EetOverrideEn|0x0 = # EET Mode +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[= 0]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[= 1]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[= 2]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Iio[= 3]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[= 0]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[= 1]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[= 2]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Kti[= 3]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlin= k[0]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlin= k[1]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlin= k[2]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLinkInL1Rlin= k[3]|0x0 # Link in L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableLowerLatency= Mode|0x0 # Register Access Low Latency Mode +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Dino[0]|0x0 # PKGC_CRITERIA DINO +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Dino[1]|0x0 # PKGC_CRITERIA DINO +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Dino[2]|0x0 # PKGC_CRITERIA DINO +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Dino[3]|0x0 # PKGC_CRITERIA DINO +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Fxr[0]|0x0 # PKGC_CRITERIA FXR +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Fxr[1]|0x0 # PKGC_CRITERIA FXR +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Fxr[2]|0x0 # PKGC_CRITERIA FXR +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Fxr[3]|0x0 # PKGC_CRITERIA FXR +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hbm[0]|0x1 # PKGC_CRITERIA HBMx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hbm[1]|0x1 # PKGC_CRITERIA HBMx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hbm[2]|0x1 # PKGC_CRITERIA HBMx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hbm[3]|0x1 # PKGC_CRITERIA HBMx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hcx[0]|0x0 # PKGC_CRITERIA HCX +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hcx[1]|0x0 # PKGC_CRITERIA HCX +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hcx[2]|0x0 # PKGC_CRITERIA HCX +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hcx[3]|0x0 # PKGC_CRITERIA HCX +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hqm[0]|0x0 # PKGC_CRITERIA HQM +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hqm[1]|0x0 # PKGC_CRITERIA HQM +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hqm[2]|0x0 # PKGC_CRITERIA HQM +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Hqm[3]|0x0 # PKGC_CRITERIA HQM +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Iio[0]|0x0 # PKGC_CRITERIA IIOx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Iio[1]|0x0 # PKGC_CRITERIA IIOx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Iio[2]|0x0 # PKGC_CRITERIA IIOx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Iio[3]|0x0 # PKGC_CRITERIA IIOx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Kti[0]|0x0 # PKGC_CRITERIA KTI +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Kti[1]|0x0 # PKGC_CRITERIA KTI +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Kti[2]|0x0 # PKGC_CRITERIA KTI +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Kti[3]|0x0 # PKGC_CRITERIA KTI +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[0]|0xff # PKGC_CRITERIA MCDDRx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[1]|0xff # PKGC_CRITERIA MCDDRx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[2]|0xff # PKGC_CRITERIA MCDDRx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[3]|0xff # PKGC_CRITERIA MCDDRx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mdfs[0]|0x0 # PKGC_CRITERIA MDFS +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mdfs[1]|0x0 # PKGC_CRITERIA MDFS +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mdfs[2]|0x0 # PKGC_CRITERIA MDFS +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mdfs[3]|0x0 # PKGC_CRITERIA MDFS +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Nac[0]|0x0 # PKGC_CRITERIA NAC +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Nac[1]|0x0 # PKGC_CRITERIA NAC +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Nac[2]|0x0 # PKGC_CRITERIA NAC +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Nac[3]|0x0 # PKGC_CRITERIA NAC +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Rlink[0]|0x0 # PKGC_CRITERIA Rlink +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Rlink[1]|0x0 # PKGC_CRITERIA Rlink +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Rlink[2]|0x0 # PKGC_CRITERIA Rlink +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Rlink[3]|0x0 # PKGC_CRITERIA Rlink +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Tip[0]|0x0 # PKGC_CRITERIA TIP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Tip[1]|0x0 # PKGC_CRITERIA TIP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Tip[2]|0x0 # PKGC_CRITERIA TIP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Tip[3]|0x0 # PKGC_CRITERIA TIP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgcCriteria= |0xff # Enable PKGC_SA_PS_CRITERIA +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableProcHot|0x3 = # PROCHOT Modes +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableThermalMonit= or|0x1 # Thermal Monitor +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableXe|0x1 = # Extreme Edition +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EngAvgTimeWdw1|0x1= a # Averaging Time Window +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnhancedPmaxDetect= or|0x1 # PMAX Detector Enhancement +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.FastRaplDutyCycle|= 0x40 # FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.GpssTimer|0x32 = # GPSS timer +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis= [0]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis= [1]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis= [2]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio0PkgcClkGateDis= [3]|0x0 # IIO0_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis= [0]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis= [1]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis= [2]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio1PkgcClkGateDis= [3]|0x0 # IIO1_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis= [0]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis= [1]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis= [2]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Iio2PkgcClkGateDis= [3]|0x0 # IIO2_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.InputUncoreFreq|0x= 7f # Uncore Freq: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IoBwPlmtOvrdEn|0x0= # IO_BW_PLIMIT_OVRD_EN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IomApmOvrdEn|0x0 = # IOM_APM_OVERRIDE_ENABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.IssTdpLevel|0x0 = # Intel SST-PP +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDi= s[0]|0x0 # UPI01_PKGC_CLK_GATE_DISABL +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDi= s[1]|0x0 # UPI01_PKGC_CLK_GATE_DISABL +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDi= s[2]|0x0 # UPI01_PKGC_CLK_GATE_DISABL +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01PkgcClkGateDi= s[3]|0x0 # UPI01_PKGC_CLK_GATE_DISABL +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[0]|= 0x1 # UPI01 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[1]|= 0x1 # UPI01 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[2]|= 0x1 # UPI01 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[3]|= 0x1 # UPI01 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[0]|0x1 = # UPI_0_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[1]|0x1 = # UPI_0_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[2]|0x1 = # UPI_0_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[3]|0x1 = # UPI_0_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[0]|0x1 = # UPI_1_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[1]|0x1 = # UPI_1_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[2]|0x1 = # UPI_1_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[3]|0x1 = # UPI_1_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDi= s[0]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDi= s[1]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDi= s[2]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23PkgcClkGateDi= s[3]|0x0 # UPI23_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[0]|= 0x1 # UPI23 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[1]|= 0x1 # UPI23 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[2]|= 0x1 # UPI23 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[3]|= 0x1 # UPI23 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[0]|0x1 = # UPI_2_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[1]|0x1 = # UPI_2_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[2]|0x1 = # UPI_2_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[3]|0x1 = # UPI_2_IN_L1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDi= s[0]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDi= s[1]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDi= s[2]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45PkgcClkGateDi= s[3]|0x0 # UPI45_PKGC_CLK_GATE_DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[0]|= 0x1 # UPI45 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[1]|= 0x1 # UPI45 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[2]|= 0x1 # UPI45 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[3]|= 0x1 # UPI45 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.KtiApmOvrdEn|0x0 = # UPI_APM_OVERRIDE_ENABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.LTRSwInput|0x1 = # LTR IIO Input +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[= 0]|0x0 # MC0 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[= 1]|0x0 # MC0 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[= 2]|0x0 # MC0 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0PkgcClkGateDis[= 3]|0x0 # MC0 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[0]|0x= 1 # MC0 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[1]|0x= 1 # MC0 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[2]|0x= 1 # MC0 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[3]|0x= 1 # MC0 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[= 0]|0x0 # MC1 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[= 1]|0x0 # MC1 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[= 2]|0x0 # MC1 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1PkgcClkGateDis[= 3]|0x0 # MC1 PKGC CLK GATE DISABLE +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[0]|0x= 1 # MC1 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[1]|0x= 1 # MC1 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[2]|0x= 1 # MC1 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[3]|0x= 1 # MC1 PLLs Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.MonitorMWait|0x1 = # Enable Monitor MWAIT +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NativeAspmEnable|0= x2 # Native ASPM +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatMult|0x0 = # Non-Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatOvrd|0x0 = # Non-Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatVal|0x0 = # Non-Snoop Latency Value +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NonSnpLatVld|0x0 = # Non-Snoop Latency Override Valid +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OSCx|0x0 = # OS ACPI Cx +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OnDieThermalThrott= ling|0x0 # T-State Throttle Level +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OverclockingLock|0= x1 # Overclocking Lock +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeHigh1|0x3= f # P0 TotalTimeThreshold High +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeLow1|0x28= # P0 TotalTimeThreshold Low +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[0]|0x1= # PCIe IIO0 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[1]|0x1= # PCIe IIO0 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[2]|0x1= # PCIe IIO0 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[3]|0x1= # PCIe IIO0 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[0]|0x1= # PCIe IIO1 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[1]|0x1= # PCIe IIO1 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[2]|0x1= # PCIe IIO1 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[3]|0x1= # PCIe IIO1 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[0]|0x1= # PCIe IIO2 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[1]|0x1= # PCIe IIO2 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[2]|0x1= # PCIe IIO2 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[3]|0x1= # PCIe IIO2 PLL Shutdown En +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PackageCState|0xff= # Package C State +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[0]|0x1 = # PCIE Port0 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[1]|0x1 = # PCIE Port0 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[2]|0x1 = # PCIE Port0 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[3]|0x1 = # PCIE Port0 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[0]|0x1 = # PCIE Port1 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[1]|0x1 = # PCIE Port1 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[2]|0x1 = # PCIE Port1 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[3]|0x1 = # PCIE Port1 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[0]|0x1 = # PCIE Port2 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[1]|0x1 = # PCIE Port2 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[2]|0x1 = # PCIE Port2 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[3]|0x1 = # PCIE Port2 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[0]|0x1 = # PCIE Port3 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[1]|0x1 = # PCIE Port3 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[2]|0x1 = # PCIE Port3 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[3]|0x1 = # PCIE Port3 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[0]|0x1 = # PCIE Port4 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[1]|0x1 = # PCIE Port4 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[2]|0x1 = # PCIE Port4 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[3]|0x1 = # PCIE Port4 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[0]|0x1 = # PCIE Port5 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[1]|0x1 = # PCIE Port5 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[2]|0x1 = # PCIE Port5 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[3]|0x1 = # PCIE Port5 PCIE_IN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcodeWdogTimerEn|0= x2 # Pcode Dispatcher Watchdog Timer +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitClipC|0x= 1f # Perf P-Limit Clip +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitEn|0x1 = # Perf P Limit +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLmtThshld|0xf= # Perf P-Limit Threshold +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPlimitDifferen= tial|0x1 # Perf P-Limit Differential +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskDino[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskDino[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskDino[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskDino[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskFxr[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskFxr[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskFxr[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskFxr[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHcx[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHcx[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHcx[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHcx[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHqm[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHqm[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHqm[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskHqm[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskNac[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskNac[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskNac[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskNac[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskTip[0]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskTip[1]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskTip[2]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaAllowe= dPsMaskTip[3]|0x0 # PKGC_ALLOWED_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoDino[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoDino[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoDino[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoDino[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoFxr[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoFxr[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoFxr[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoFxr[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHbm[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHbm[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHbm[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHbm[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHcx[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHcx[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHcx[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHcx[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHqm[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHqm[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHqm[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoHqm[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoIio[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoIio[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoIio[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoIio[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoKti[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoKti[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoKti[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoKti[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMcddr[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMcddr[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMcddr[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMcddr[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMdfs[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMdfs[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMdfs[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoMdfs[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoNac[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoNac[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoNac[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoNac[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoRlink[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoRlink[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoRlink[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoRlink[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoTip[0]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoTip[1]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoTip[2]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaInstan= ceNoTip[3]|0x0 # Instance_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpType[0]|0x0 # CPU0 Logical_ip_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpType[1]|0x0 # CPU1 Logical_ip_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpType[2]|0x0 # CPU2 Logical_ip_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpType[3]|0x0 # CPU3 Logical_ip_type +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeHbm[0]|0x18 # HBM: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeHbm[1]|0x18 # HBM: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeHbm[2]|0x18 # HBM: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeHbm[3]|0x18 # HBM: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[0]|0x20 # IIO: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[1]|0x20 # IIO: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[2]|0x20 # IIO: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[3]|0x20 # IIO: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[0]|0x10 # MCDDR: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[1]|0x10 # MCDDR: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[2]|0x10 # MCDDR: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[3]|0x10 # MCDDR: +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCLatNeg|0x1 = # PKG C-state Lat. Neg. +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCstEntryValCtl|= 0x0 # PKGC_ENTRY_CRITERIA OVRD +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskD= ino[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskD= ino[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskD= ino[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskD= ino[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskF= xr[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskF= xr[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskF= xr[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskF= xr[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= cx[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= cx[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= cx[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= cx[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= qm[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= qm[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= qm[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskH= qm[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskN= ac[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskN= ac[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskN= ac[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskN= ac[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskT= ip[0]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskT= ip[1]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskT= ip[2]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteraPsMaskT= ip[3]|0x0 # PKGC_CRITERIA_PS_MASK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onHbm[0]|0x0 # HBM Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onHbm[1]|0x0 # HBM Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onHbm[2]|0x0 # HBM Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onHbm[3]|0x0 # HBM Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onMcddr[0]|0x0 # MCDDR Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onMcddr[1]|0x0 # MCDDR Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onMcddr[2]|0x0 # MCDDR Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgcCriteriaPsOpti= onMcddr[3]|0x0 # MCDDR Option +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxAutoAdjustment= |0x0 # BIOS Auto Adjustment +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxDetector|0x1 = # Detector +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxLoadLine|0x0 = # DC LL Select +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxOffset|0x0 = # PMAX Config Positive Offset +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxOffsetNegative= |0x0 # PMAX Config Negative Offset +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxSign|0x0 = # PMAX Config Sign +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxTriggerSetup|0= x0 # Trigger Setup +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1En|0x1 = # PL1 Limit +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Power|0= x0 # PL1 Power Limit +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Time|0x= 1 # PL1 Time Window +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2En|0x1 = # PL2 Limit +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Power|0= x0 # PL2 Power Limit +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Time|0x= 1 # PL2 Time Window +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PpcccLock|0x1 = # Lock Indication +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorAPSrocket= ing|0x0 # APS rocketing +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorActivePbf= |0x0 # Activate SST-BF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorC1eEnable= |0x1 # Enhanced Halt State (C1E) +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorConfigure= Pbf|0x1 # Configure SST-BF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEPPEnable= |0x1 # EPP Enable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistEnabl= e|0x1 # SpeedStep (Pstates) +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistPsdFu= nc|0x0 # EIST PSD Function +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEppProfil= e|0x80 # EPP profile +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMEnabl= e|0x1 # Hardware P-States +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMInter= rupt|0x0 # HardwarePM Interrupt +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorOutofBand= AlternateEPB|0x0 # PECI PCS EPB +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorRaplPrior= itization|0x0 # RAPL Prioritization +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorScalabili= ty|0x0 # Scalability +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotLock|0x1 = # PROCHOT LOCK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotResponseRat= io|0x0 # PROCHOT RATIO +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfSwitch|0x1 = # Dynamic Loadline Switch +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfTuning|0x0 = # Power Performance Tuning +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.RunCpuPpmInPei|0x0= # Run CPU PPM code in PEI +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SAPMControl|0x0 = # SAPM Control +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[0]|0x1= # SAPMCTL_CFG LOCK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[1]|0x1= # SAPMCTL_CFG LOCK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[2]|0x1= # SAPMCTL_CFG LOCK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[3]|0x1= # SAPMCTL_CFG LOCK +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable= [0]|0x0 # SetVID Decay Disable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable= [1]|0x0 # SetVID Decay Disable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable= [2]|0x0 # SetVID Decay Disable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SetvidDecayDisable= [3]|0x0 # SetVID Decay Disable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatMult|0x0 = # Snoop Latency Multiplier +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatOvrd|0x0 = # Force Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVal|0x0 = # Force Non-Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVld|0x0 = # Snoop Latency Override +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SwLtrOvrdCtl|0x0 = # PCIe LTR Override Control +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TCCActivationOffse= t|0x0 # TCC Activation Offset +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TStateEnable|0x0 = # Software Controlled T-States +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStat= usFilter|0x0 # Therm-Monitor-Status Filter +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStat= usFilterTimeWindow|0x9 # Therm-Monitor-Status Filter Time Window +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboMode|0x1 = # Turbo Mode +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitCsr= Lock|0x1 # Package RAPL Limit CSR Lock +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitLoc= k|0x0 # Package RAPL Limit MSR Lock +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[0]|0xff # TurboRatioCores0 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[1]|0xff # TurboRatioCores1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[2]|0xff # TurboRatioCores2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[3]|0xff # TurboRatioCores3 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[4]|0xff # TurboRatioCores4 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[5]|0xff # TurboRatioCores5 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[6]|0xff # TurboRatioCores6 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[7]|0xff # TurboRatioCores7 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[0]|0x0 # TurboRatioLimit0 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[1]|0x0 # TurboRatioLimit1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[2]|0x0 # TurboRatioLimit2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[3]|0x0 # TurboRatioLimit3 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[4]|0x0 # TurboRatioLimit4 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[5]|0x0 # TurboRatioLimit5 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[6]|0x0 # TurboRatioLimit6 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitRat= io[7]|0x0 # TurboRatioLimit7 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncoreFreqRaplLimi= t|0x1 # Uncore Freq RAPL +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncoreFreqScaling|= 0x1 # Uncore Freq Scaling +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncrPerfPlmtOvrdEn= |0x1 # UNCORE_PERF_PLIMIT_OVRD_EN +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.VccSAandVccIOdisab= le|0x0 # VccSA/VccIO Disable +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.WFRWAEnable|0x0 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.WorkLdConfig|0x0 = # Workload Configuration +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AcExceptionOnSplitLo= ckEnable|0x0 # #AC Exception On Split Lock +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AcmType|0x0 = # ACM Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AesEnable|0x1 = # AES-NI +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AllowMixedPowerOnCpu= Ratio|0x0 # Skip Flex Ratio Override +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AmpPrefetchEnable|0x= 0 # AMP Prefetch +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BiosAcmErrorReset|0x= 0 # BIOS ACM Error Reset +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BspSelection|0xff = # Bsp Selection +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRPucodeEnable|0x0 = # Processor Pcode/Ucode CFR +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRPucodeManualCommi= t|0x0 # Manual Commit Pcode/Ucode CFR +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRS3mEnable|0x0 = # Processor S3M CFR +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CFRS3mManualCommit|0= x0 # Manual Commit S3M FW CFR +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CheckCpuBist|0x1 = # Check CPU BIST Result +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[0]|0= x0 # Disable Bitmap +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[1]|0= x0 # Disable Bitmap +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[2]|0= x0 # Disable Bitmap +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[3]|0= x0 # Disable Bitmap +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1 = # Core Failover +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashLogGprs|0x0 = # Cpu CrashLog Gprs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuDbpEnable|0x0 = # DBP-F +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuL1NextPagePrefetc= herDisable|0x0 # L1 Next Page Prefetcher +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuMtoIWa|0x1 = # MtoI Workaround +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuPaLimit|0x1 = # Limit CPU PA to 46 bits +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuidMaxValue|0x0 = # Max CPUID Value Limit +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CrDimmsPresent|0x0 = # SW Guard Extensions (SGX) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUIPPrefetcherEnabl= e|0x1 # DCU IP Prefetcher +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUModeSelection|0x0= # DCU Mode +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUStreamerPrefetche= rEnable|0x1 # DCU Streamer Prefetcher +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DebugInterface|0x0 = # DEBUG INTERFACE +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS245|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS192|0x0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS234|0x0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS241|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS238|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS242|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS244|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS240|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS243|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS236|0x0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS237|0x0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS235|0x0 = # TME key restore +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableMktme|0x0 = # Total Memory Encryption Multi-Tenant(TME-MT) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableSaf|0x0 = # Enable FuSa (SAF) - variable to handle dynamic B= IOS menu +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableSgx|0x0 = # SW Guard Extensions (SGX) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EnableTme|0x0 = # Total Memory Encryption (TME) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EpochUpdate|0x2 = # Select Owner EPOCH input type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.FastStringEnable|0x1= # Fast String +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ForcePhysicalModeEna= ble|0x0 # APIC Physical Mode +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.GlobalPsmiEnable|0x1= # Global PSMI Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IedTraceSize|0x0 = # IED Trace memory +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IioLlcWaysMask|0x0 = # IIO LLC Ways [19:0](Hex) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[0]|0x0 = # IOT Cfg +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[1]|0x0 = # IOT Cfg +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[2]|0x0 = # IOT Cfg +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.IotEn[3]|0x0 = # IOT Cfg +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.L2RfoPrefetchDisable= |0x0 # L2 RFO Prefetch Disable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LlcPrefetchEnable|0x= 1 # LLC Prefetch +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LockChipset|0x1 = # Lock Chipset +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MachineCheckEnable|0= x1 # Machine Check +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcSpatialPrefetcher= Enable|0x1 # Adjacent Cache Prefetch +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcStreamerPrefetche= rEnable|0x1 # Hardware Prefetcher +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[0]|0= x1 # OCLA Tor IDs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[1]|0= x1 # OCLA Tor IDs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[2]|0= x1 # OCLA Tor IDs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[3]|0= x1 # OCLA Tor IDs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[0]|0x1 = # Num of OCLA ways +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[1]|0x1 = # Num of OCLA Ways +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[2]|0x1 = # Num of OCLA Ways +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[3]|0x1 = # Num of OCLA Ways +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PCIeDownStreamPECIWr= ite|0x0 # Down Stream PECI +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtEspiTrustBit|= 0x0 # eSPI Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtGenericTrustB= it|0x0 # Generic Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtIeTrustBit|0x= 1 # IE Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtLegacyTrustBi= t|0x1 # Legacy Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciAgtSmbusTrustBit= |0x0 # SMBus Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciInTrustControlBi= t|0x1 # PECI +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PpinControl|0x1 = # PPIN Control +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PrmrrSize|0x80000000= # PRMRR Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRat= io|0x17 # CPU Core Flex Ratio +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRat= ioOverrideEnable|0x0 # CPU Flex Ratio Override +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorHyperThread= ingDisable|0x0 # Hyper-Threading [ALL] +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorLtsxEnable|= 0x0 # Enable Intel(R) TXT +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrLockCont= rol|0x1 # MSR Lock Control +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrPkgCstCo= nfigControlLock|0x1 # PKG CST CONFIG CONTROL MSR Lock +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorSmxEnable|0= x0 # Enable SMX +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0= x1 # VMX +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorX2apic|0x1 = # Extended APIC +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[0]|0= x1 # PSMI Handler Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[1]|0= x1 # PSMI Handler Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[2]|0= x1 # PSMI Handler Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[3]|0= x1 # PSMI Handler Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[0]|0x0 = # PSMI Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[1]|0x0 = # PSMI Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[2]|0x0 = # PSMI Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTrace[3]|0x0 = # PSMI Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[0]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[1]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[2]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[3]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[0]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[1]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[2]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[3]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[0]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[1]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[2]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[3]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[0]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[1]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[2]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[3]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[0]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[1]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[2]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[3]|0x1 # Buffer Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on0[0]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on0[1]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on0[2]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on0[3]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on1[0]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on1[1]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on1[2]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on1[3]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on2[0]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on2[1]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on2[2]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on2[3]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on3[0]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on3[1]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on3[2]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on3[3]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on4[0]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on4[1]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on4[2]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceMemTypeRegi= on4[3]|0x0 # Cache Type +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[0]|= 0x0 # PSMI Trace Region 0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[1]|= 0x0 # PSMI Trace Region 0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[2]|= 0x0 # PSMI Trace Region 0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion0[3]|= 0x0 # PSMI Trace Region 0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[0]|= 0x0 # PSMI Trace Region 1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[1]|= 0x0 # PSMI Trace Region 1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[2]|= 0x0 # PSMI Trace Region 1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion1[3]|= 0x0 # PSMI Trace Region 1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[0]|= 0x0 # PSMI Trace Region 2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[1]|= 0x0 # PSMI Trace Region 2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[2]|= 0x0 # PSMI Trace Region 2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion2[3]|= 0x0 # PSMI Trace Region 2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[0]|= 0x0 # PSMI Trace Region 3 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[1]|= 0x0 # PSMI Trace Region 3 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[2]|= 0x0 # PSMI Trace Region 3 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion3[3]|= 0x0 # PSMI Trace Region 3 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[0]|= 0x0 # PSMI Trace Region 4 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[1]|= 0x0 # PSMI Trace Region 4 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[2]|= 0x0 # PSMI Trace Region 4 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceRegion4[3]|= 0x0 # PSMI Trace Region 4 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.RdtCatOpportunisticT= uning|0x0 # RDT CAT Opportunistic Tuning +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.RemoteWaysMask|0x0 = # Remote Ways [22:12](Hex) +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxAutoRegistrationA= gent|0x0 # Enable/Disable SGX Auto MP Registration Agent +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxDebugMode|0x0 = # Enable/Disable SGX Debug Mode +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxEpoch0|0x0 = # Software Guard Extensions Epoch 0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxEpoch1|0x0 = # Software Guard Extensions Epoch 1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxFactoryReset|0x0 = # SGX Factory Reset +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash0|0x0= # SGXLEPUBKEYHASH0 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash1|0x0= # SGXLEPUBKEYHASH1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash2|0x0= # SGXLEPUBKEYHASH2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLePubKeyHash3|0x0= # SGXLEPUBKEYHASH3 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLeWr|0x1 = # SGXLEPUBKEYHASHx Write Enable +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxPackageInfoInBand= Access|0x0 # SGX Package Info In-Band Access +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxQoS|0x1 = # SGX QoS +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmbusErrorRecovery|0= x1 # Smbus Error Recovery +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmmBlockedDelayed|0x= 0 # SMM Blocked and Delayed +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ThreeStrikeTimer|0x1= # 3StrikeTimer +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TscResetEnable|0x0 = # TSC Reset +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TsegSize|0x5 = # TSEG Smram Size +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.eSmmSaveState|0x0 = # eSMM Save State +gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseAboveFourGiga|0x100000000 = # Mega-Block base above 4GB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseAboveOneMega|0x100000 = # Mega-Block base above 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.BaseBelowOneMega|0x50000 = # Mega-Block base below 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.CoreMegaBlock|0x0 = # Core Mega Block Support +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedAboveFourGiga|0x0 = # Mega-Block non-used policy above 4GB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedAboveOneMega|0x0 = # Mega-Block non-used policy above 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUnUsedBelowOneMega|0x0 = # Mega-Block non-used policy below 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedAboveFourGiga|0x4 = # Mega-Block policy above 4GB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedAboveOneMega|0x4 = # Mega-Block policy above 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.PolicyUsedBelowOneMega|0x4 = # Mega-Block policy below 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeAboveFourGiga|0x0 = # Mega-Block size above 4GB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeAboveOneMega|0x0 = # Mega-Block size above 1MB +gStructPcdTokenSpaceGuid.PcdSvConfiguration.SizeBelowOneMega|0x0 = # Mega-Block size below 1MB +gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION.TpmDevice|0x1 = # Attempt TPM Device +gStructPcdTokenSpaceGuid.PcdTCG2_VERSION.PpiVersion|0x332e31 = # Attempt PPI Version +gStructPcdTokenSpaceGuid.PcdTCG2_VERSION.Tpm2AcpiTableRev|0x4 = # Attempt Rev of TPM2 ACPI Table + +[PcdsDynamicHii.common.DEFAULT.MANUFACTURING] +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x0 = # IE Reset Prep Done +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x0 = # ME Reset Prep Done +gStructPcdTokenSpaceGuid.PcdSetup.StorageOpROMSuppression|0x1 = # Storage OPROM Suppression +gStructPcdTokenSpaceGuid.PcdSetup.TagecMem|0x1 = # Reserve TAGEC Memory +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|= 0x0 # MEMHOT Output Throttling Mode Options +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PCIeDownStreamPECIWr= ite|0x1 # Down Stream PECI +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorMsrLockCont= rol|0x0 # MSR Lock Control +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0= x0 # VMX + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc b/Platf= orm/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc new file mode 100644 index 0000000000..0c166ade00 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc @@ -0,0 +1,3796 @@ +## @file +# @copyright +# Copyright 2019 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + VPD_TOOL_GUID =3D 8C3D856A-9BE6-468E-850A-24F7A8D38E08 + +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + +[DefaultStores] + 0|STANDARD # UEFI Standard default 0|STANDARD is reserved. + 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is r= eserved. + +[PcdsDynamicExVpd.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|* + +[PcdsDynamicExHii.common.DEFAULT.STANDARD] +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|L"FpgaSocketConfig"|gFpgaSock= etVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|L"SocketMemoryConfig"|gEfiS= ocketMemoryVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdPchSetup|L"PchSetup"|gPchSetupVariableGuid|0x0= 0||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|L"SocketProcessorCor= eConfig"|gEfiSocketProcessorCoreVarGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSetup|L"Setup"|gCommonSystemConfigurationGuid|= 0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|L"SocketCommonRcConfig"|g= EfiSocketCommonRcVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|L"SocketPowerManag= ementConfig"|gEfiSocketPowermanagementVarGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|L"SocketMpLinkConfig"|gEfiS= ocketMpLinkVariableGuid|0x00||NV, BS, RT +gStructPcdTokenSpaceGuid.PcdSocketIioConfig|L"SocketIioConfig"|gEfiSocketI= ioVariableGuid|0x00||NV, BS, RT + +!if $(TARGET) =3D=3D "DEBUG" +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x4 +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x8 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0xF +!else +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x0 +gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0x0 +!endif + +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[12]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[18]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[24]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[30]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCastEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0= x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU1[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU2[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU3[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU4[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[12]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[18]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[24]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[30]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[36]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[42]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[48]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[49]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[50]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[51]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[52]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[53]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[54]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[55]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[56]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[57]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[58]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[59]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[60]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[61]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[62]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[63]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[64]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[65]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[66]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[67]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[68]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[69]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[70]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[71]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[72]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[73]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[74]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[75]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[76]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[77]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[78]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[79]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[80]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[81]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[82]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DeEmphasis[83]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[12]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[18]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.DevPresIoApicIio[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS19|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[4]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[5]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[6]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[7]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[8]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[9]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[10]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[11]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[12]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[13]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[14]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[15]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[16]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[17]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[18]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[19]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[20]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[21]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[22]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[23]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[24]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[25]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[26]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[27]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[28]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[29]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[30]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[31]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[32]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[33]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[34]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[35]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[36]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[37]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[38]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[39]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[40]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[41]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[42]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[43]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[44]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[45]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[46]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[47]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[48]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[49]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[50]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[51]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[52]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[53]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[54]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[55]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[56]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[57]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[58]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[59]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[60]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[61]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[62]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[63]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[64]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[65]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[66]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[67]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[68]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[69]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[70]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[71]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[72]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[73]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[74]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[75]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[76]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[77]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[78]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[79]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[80]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[81]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[82]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS39[83]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[0]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[1]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[2]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[3]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[4]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[5]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[6]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[7]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[8]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[9]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[10]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[11]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[12]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[13]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[14]|0x29 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ReservedS26[15]|0x29 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+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[24]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[30]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[36]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[42]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[48]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[49]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[50]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[51]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[52]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[53]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[54]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[55]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[56]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[57]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[58]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[59]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[60]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[61]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[62]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[63]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[64]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[65]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[66]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[67]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[68]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[69]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[70]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[71]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[72]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[73]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[74]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[75]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[76]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[77]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[78]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[79]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[80]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[12]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[18]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[24]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[30]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[36]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[42]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[48]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[49]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[50]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[51]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[52]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[53]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[54]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[55]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[56]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[57]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[58]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[59]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[60]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[61]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[62]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[63]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[64]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[65]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[66]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[67]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[68]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[69]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[70]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[71]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[72]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[73]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[74]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[75]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[76]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[77]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[78]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[79]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[80]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[81]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[82]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[83]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieGlobalAspm|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[0]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[1]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[2]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[3]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[4]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[5]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[6]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[7]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[8]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[9]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[10]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[11]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[12]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[13]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[14]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[15]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[16]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[17]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[18]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[19]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[20]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[21]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[22]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[23]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[24]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[25]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[26]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[27]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[28]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[29]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[30]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[31]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[32]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[33]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[34]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[35]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[36]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[37]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[38]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[39]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[40]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[41]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[42]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[43]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[44]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[45]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[46]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[47]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[48]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[49]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[50]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[51]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[52]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[53]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[54]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[55]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[56]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[57]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[58]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[59]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[60]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[61]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[62]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[63]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[64]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[65]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[66]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[67]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[68]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[69]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[70]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[71]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[72]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[73]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[74]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[75]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[76]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[77]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[78]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[79]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[80]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[81]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[82]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieL1Latency[83]|0x4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[0]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[1]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[2]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[3]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[4]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[5]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[6]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[7]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[8]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[9]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[10]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[11]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[12]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[13]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[14]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[15]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[16]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[17]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[18]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[19]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[20]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[21]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[22]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[23]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[24]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[25]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[26]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[27]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[28]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[29]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[30]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[31]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[32]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[33]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[34]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[35]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[36]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[37]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[38]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[39]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[40]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[41]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[42]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[43]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[44]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[45]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[46]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[47]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[48]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[49]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[50]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[51]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[52]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[53]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[54]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[55]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[56]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[57]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[58]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[59]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[60]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[61]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[62]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[63]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[64]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[65]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[66]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[67]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[68]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[69]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[70]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[71]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[72]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[73]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[74]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[75]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[76]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[77]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[78]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[79]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[80]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[81]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[82]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxPayload[83]|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieMaxReadRequestSize|0x7 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[12]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[18]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[24]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[30]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[36]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[42]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[48]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[49]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[50]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[51]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[52]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[53]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[54]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[55]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[56]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[57]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[58]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[59]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[60]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[61]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[62]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[63]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[64]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[65]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[66]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[67]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[68]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[69]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[70]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[71]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[72]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[73]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[74]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[75]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[76]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[77]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[78]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[79]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[80]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[81]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[82]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortClkGateEnable[83]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[1]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[2]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[3]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[4]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[5]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[6]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[7]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[8]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[9]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[10]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[11]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[12]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[13]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[14]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[15]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[16]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[17]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[18]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[19]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[20]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[21]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[22]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[23]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[24]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[25]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[26]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[27]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[28]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[29]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[30]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[31]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[32]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[33]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[34]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[35]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[36]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[37]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[38]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[39]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[40]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[41]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[42]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[43]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[44]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[45]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[46]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[47]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[48]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[49]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[50]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[51]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[52]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[53]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[54]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[55]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[56]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[57]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[58]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[59]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[60]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[61]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[62]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[63]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[64]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[65]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[66]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[67]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[68]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[69]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[70]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[71]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[72]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[73]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[74]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[75]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[76]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[77]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[78]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[79]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[80]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[81]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[82]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortEnable[83]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom2|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom3|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom4|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom5|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom6|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom7|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom8|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PerformanceTuningMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.SnoopResponseHoldOff|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[1]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[2]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[3]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[4]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[5]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[7]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[8]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[9]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[10]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[11]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[13]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[14]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[15]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[16]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[17]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[19]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[20]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[21]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[22]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[23]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[1]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[2]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[3]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[4]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[5]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[7]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[8]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[9]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[10]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[11]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[13]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[14]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[15]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[16]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[17]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[19]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[20]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[21]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[22]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[23]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[8]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[9]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[10]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[11]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[13]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[14]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[15]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[16]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[17]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[19]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[20]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[21]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[22]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[23]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[1]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[2]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[3]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[4]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[5]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[7]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[8]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[9]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[10]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[11]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[13]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[14]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[15]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[16]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[17]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[19]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[20]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[21]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[22]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[23]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[1]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[2]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[3]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[4]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[5]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[7]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[8]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[9]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[10]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[11]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[13]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[14]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[15]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[16]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[17]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[19]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[20]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[21]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[22]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[23]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VtdAcsWa|0x1 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohBase|0x2 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmiohSize|0x3 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgBase|0x6 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.MmcfgSize|0x6 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.IsocEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.NumaEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS6|0xF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[4]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[5]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[6]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[7]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[8]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[9]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[10]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[11]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[12]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[13]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[14]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[15]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[16]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[17]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[18]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[19]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[20]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[21]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[22]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[23]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[24]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[25]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[26]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[27]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[28]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[29]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[30]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig.ReservedS7[31]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.D2KCreditConfig|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS154|0x5 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS159|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS176|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS177|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS181|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS182|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS180|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS178|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS179|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS167|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS168|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS158|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS164|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS157|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS163|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS151|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS156|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS162|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS152|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS153|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS169|0x8 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS173|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS160|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS161|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS170|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS171|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS172|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS184|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS174|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS155|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS165|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS166|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.ReservedS175|0x5 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DirectoryModeEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IoDcMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.IrqThreshold|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiAdaptationSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiCrcMode|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiFailoverEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL0pEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkL1En|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiLinkVnaOverride|0x7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiPrefetchEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.KtiSkuMismatchCheck|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.LLCDeadLineAlloc|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.QpiLinkSpeedMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.RdCurForXptPrefetchEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.StaleAtoSOptEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremEmpty|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TorThresLoctoremNorm|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.MbeBwCal|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.TscSyncEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptPrefetchEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.XptRemotePrefetchEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu0P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu1P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu2P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186A0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3CF0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xA +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondVdd|0x4EC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.allowCorrectableMemTestErro= r|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AttemptFastBootCold|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS99|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS100|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS101|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS104|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS89|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS102|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS103|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS91|0x10 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS88|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS90|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS95|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS96|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS97|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS98|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Blockgnt2cmd1cyc|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkeIdleTimer|0x14 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CkMode|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdNormalization|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.cmdSetupPercentOffset|0x32 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmdTxEqCalibration|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CmsEnableDramPm|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.CustomRefreshRate|0x14 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DataDllOff|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerLimit|0x2E= E0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmAveragePowerTimeConsta= nt|0x6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmEccModeSwitch|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbAveragePowerTimeCon= stant|0x3A98 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbFeature|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DcpmmMbbMaxPowerLimit|0x3A98 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdjcTraining|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMemoryType|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS83|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS121|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS120|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS136|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS63|0x7 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS62|0xF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS67|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS65|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS66|0x40 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS73|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS109|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS78|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS68|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS110|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS57|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS56|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS61|0x1FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS51|0x1F +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS52|0x7F +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS50|0x40 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS60|0x3F +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS58|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS59|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS55|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS53|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS54|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS108|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS70|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS79|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS117|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS118|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS140|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS141|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x4 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[4]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[5]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[12]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[13]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[14]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[15]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[16]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[17]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[24]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[25]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[26]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[27]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[28]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[29]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[36]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[37]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[38]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[39]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[40]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[41]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7FF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS134|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS69|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS133|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DieSparing|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Disddrtopprd|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplExtendedRange|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRaplPwrLimitLockCsr|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DramRonEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DutyCycleTraining|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EccSupport|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EliminateDirectoryInFarMemo= ry|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS84|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS85|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePopulationPor|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EnforcePOR|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.eraseArmNVDIMMS|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.EsddcEn|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FastGoConfig|0x6 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.FourxRefreshValue|0x5F +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HalfxRefreshValue|0x19 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.haltOnMemErr|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.HwMemTest|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.iModeTraining|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LatchSystemShutdownState|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHi|0x29 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktHour|0x18 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.leakyBktLo|0x28 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmBacksideVrefEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRdVrefEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmRxDqCentering|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmTxDqCentering|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LrDimmWrVrefEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.LsxImplementation|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.McRonEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MdllOffEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.mdllSden|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemCeFloodPolicy|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlows|0xFFFFFFFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt|0xFFFFFFFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt2|0xFFFFFFFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memFlowsExt3|0xFFFFFFFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemHotOuputAssertThreshold|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.memInterleaveGran1LM|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MemTestLoops|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiSparingRanks|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.MultiThreaded|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnArsPublish|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnCmdTime|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccCorr|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccExitCorr|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccRdChk|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NgnEccWrChk|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NonPreferredWayMask|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusMaxAccessTime|0x= 15E +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvdimmSmbusReleaseDelay|0x96 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmdimmPowerCyclePolicy|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.NvmMediaStatusException|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdAll|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCmdVref|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetCtlAll|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxDq|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetRxVref|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxDq|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.OffsetTxVref|0x64 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PagePolicy|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrub|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubAddrMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PatrolScrubDuration|0x18 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcomp|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PeriodicRcompInterval|0xF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PkgcSrefEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PpdEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PreferredReadFirst|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.PxcTraining|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.restoreNVDIMMS|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RoundTripLatency|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.RxCtleTrnEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleEnDDRT|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedHigh|0xD395 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ScrambleSeedLow|0xA02B +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.smbSpeed|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spareErrTh|0x7FFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.spdCrcCheck|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1End|0xA +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Size|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap1Start|0x8C +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2End|0xF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Size|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap2Start|0x73 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3End|0xC +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Size|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap3Start|0x70 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4End|0x9 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Size|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Tap4Start|0x6D +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TempRefreshOption|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TrefiNumofRank|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.TwoxRefreshValue|0x53 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Vdd|0x4B0 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.CurrentLimit|0x438 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EngAvgTimeWdw1|0x17 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1Time|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2Time|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS3Enable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AcpiS4Enable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AltEngPerfBIAS|0x7 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxIccpLevel|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.AvxSupport|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoDemotion|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.C1AutoUnDemotion|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ConfigTdpLock|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgcCriteria= |0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[0]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[1]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[2]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[3]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableProcHot|0x3 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableThermalMonit= or|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnableXe|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnhancedPmaxDetect= or|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.FastRaplDutyCycle|= 0x40 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.GpssTimer|0x32 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[0]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[1]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[2]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[3]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[0]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[1]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[2]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[3]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[0]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[1]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[2]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[3]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.LTRSwInput|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.MonitorMWait|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.NativeAspmEnable|0= x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.OverclockingLock|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeHigh1|0x3A +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0TtlTimeLow1|0x23 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PackageCState|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcodeWdogTimerEn|0= x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitClipC|0x= 1F +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPlimitDifferen= tial|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLimitEn|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PerfPLmtThshld|0xF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[0]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[1]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[2]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[3]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[0]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[1]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[2]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[3]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PmaxDetector|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit1En|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PowerLimit2En|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PpcccLock|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorC1eEnable= |0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorConfigure= Pbf|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEistEnabl= e|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEPPEnable= |0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorEppProfil= e|0x55 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProcessorHWPMEnabl= e|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ProchotLock|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PwrPerfSwitch|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboMode|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboPowerLimitCsr= Lock|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[0]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[1]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[2]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[3]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[4]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[5]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[6]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TurboRatioLimitCor= es[7]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.UncrPerfPlmtOvrdEn= |0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PrmrrSize|0x80000000 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.AesEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.BspSelection|0xFF +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CheckCpuBist|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUIPPrefetcherEnabl= e|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.DCUStreamerPrefetche= rEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS245|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS241|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS242|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ReservedS240|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.EpochUpdate|0x2 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.FastStringEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.GlobalPsmiEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.KeySplit|0x7 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.LockChipset|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MachineCheckEnable|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcSpatialPrefetcher= Enable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.MlcStreamerPrefetche= rEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[0]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[1]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[2]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[3]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PeciInTrustControlBi= t|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PpinControl|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorFlexibleRat= io|0x17 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ProcessorVmxEnable|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[0]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[1]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[2]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[3]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxAutoRegistrationA= gent|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxLeWr|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxPackageInfoInBand= Access|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SgxQoS|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.SmbusErrorRecovery|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.ThreeStrikeTimer|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.TsegSize|0x5 +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorErrThres|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.CpuVccInVoltage|0x167 +gStructPcdTokenSpaceGuid.PcdSetup.SerialBaudRate|0x1C200 +gStructPcdTokenSpaceGuid.PcdSetup.Gen12TimeWindow|0xFFFF +gStructPcdTokenSpaceGuid.PcdSetup.ReserveStartAddr|0x100000 +gStructPcdTokenSpaceGuid.PcdSetup.BaudRate|0x5 +gStructPcdTokenSpaceGuid.PcdSetup.ExpectedBer|0x7FFFFFFFF +gStructPcdTokenSpaceGuid.PcdSetup.XmlCliSupport|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ApplicationProfile|0xFF +gStructPcdTokenSpaceGuid.PcdSetup.LomDisableByGpio|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[0]|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[1]|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[2]|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FpkPortConfig[3]|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.XhciWakeOnUsbEnabled|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.SystemErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.RasLogLevel|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PoisonEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.UboxToPcuMcaEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.EmcaEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.EmcaCsmiEn|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.CsmiDynamicDisable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.EmcaMsmiEn|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.ElogCorrErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ElogMemErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ElogProcErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.LmceEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.WheaSupportEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogMemoryEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogProcEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.WheaLogPciEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.WheaErrInjEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.MemErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.CorrMemErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.SpareIntSelect|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorLowPrioritySignal|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FnvErrorHighPrioritySignal|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.NgnHostAlertPatrolScrubUNC|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ReportAlertSPA|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IoMcaEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioSev1Pcc|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.EdpcInterrupt|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioIrpErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioMiscErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioVtdErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddCorrErrorEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.IioPcieAddUnCorrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PsfUrEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PmsbRouterParityErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieCorrErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieUncorrErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieFatalErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerCorrErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerNfatErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerFatErrEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PcieAerEcrcEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.McBankWarmBootClearError|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_parityError|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_qtOverflow|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unexprsp|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_csraccunaligned|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs1|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_unceccCs0|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_rcvdpoison|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs1|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.irpp0_crreccCs0|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PropagateSerr|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PropagatePerr|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.Use1GPageTable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.UsbMassResetDelay|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ConsoleRedirection|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.LegacyOsRedirection|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.DataBits|0x8 +gStructPcdTokenSpaceGuid.PcdSetup.Parity|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.StopBits|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ARIEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.SRIOVEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.SvidEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FivrFaultsEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.FivrEfficiencyEnable|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.Gen34ErrorThreshold|0x10 +gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.Gen2LinkDegradation|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.Ce2LmLoggingEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.KtiFirstCeLatchEn|0x1 +gStructPcdTokenSpaceGuid.PcdSetup.PatrolScrubErrorReporting|0x0 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[0= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[2= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[3= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[4= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[5= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[6= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[7= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[8= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[9= ]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 0]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 1]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 2]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 3]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 4]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 5]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 6]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 7]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 8]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1= 9]|0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[0]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[1]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[2]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[3]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[4]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[5]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[6]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[7]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[8]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[9]|0= x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[10]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[11]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[12]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[13]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[14]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[15]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[16]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[17]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[18]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[19]|= 0x3C +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideValue|0x28 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideValue|0x28 +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrMultiplierVal|0x63 +gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerVal|0x4 +gStructPcdTokenSpaceGuid.PcdPchSetup.Btcg|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_BmcRootPort|0x5 +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_PMCGBL|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchBiosLock|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchCrossThrottling|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaLockDown|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom0HookEnable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom1HookEnable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchGpioLockDown|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudio|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieGlobalAspm|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[14]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[15]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[16]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[17]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[18]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[19]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[0]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[1]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[2]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[3]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[4]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[5]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[6]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[7]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[8]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[9]= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[10= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[11= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[12= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[13= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[14= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[15= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[16= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[17= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[18= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[19= ]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[0]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[1]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[2]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[3]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[4]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[5]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[6]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[7]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[8]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[9]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[10]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[11]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[12]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[13]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[14]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[15]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[16]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[17]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[18]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultipl= ier[19]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[0]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[1]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[2]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[3]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[4]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[5]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[6]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[7]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[8]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[9]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[10]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[11]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[12]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[13]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[14]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[15]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[16]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[17]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[18]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[19]|0= x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [0]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [1]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [2]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [3]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [4]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [5]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [6]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [7]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [8]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [9]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [10]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [11]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [12]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [13]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [14]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [15]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [16]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [17]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [18]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier= [19]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16MaxPayloadSize|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8MaxPayloadSize|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchRtcLock|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSata|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrConfigLock|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrEnable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideMultiplier= |0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSlpLanLowDc|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchsSata|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrConfigLock|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrEnable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideMultiplie= r|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubHide|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMode|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[0]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[1]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[2]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[3]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[4]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[5]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[6]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[7]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[8]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[9]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[10]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[11]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[12]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[13]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[14]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[15]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[16]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[17]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[18]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[19]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[0]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[1]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[2]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[3]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[4]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[5]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[6]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[7]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[8]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[9]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[10]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[11]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[12]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[13]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[14]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[15]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[16]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[17]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[18]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[19]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PciePllSsc|0xFE +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[14]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[15]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[16]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[17]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[18]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[19]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[14]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[15]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[16]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[17]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[18]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[19]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[14]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[15]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[16]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[17]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[18]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[19]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[8]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[9]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[10]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[11]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[12]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[13]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[14]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[15]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[16]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[17]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[18]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[19]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFunctionSwapping|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[0]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[1]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[2]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[3]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[4]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[5]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[6]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[7]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[8]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[9]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[10]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[11]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[12]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[13]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[14]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[15]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[16]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[17]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[18]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[19]|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxReadRequestSize|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[0]|0x6 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[1]|0x4 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[2]|0x8 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[3]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[4]|0xA +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[0]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[1]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[2]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[3]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[4]|0x2 +gStructPcdTokenSpaceGuid.PcdPchSetup.PmcReadDisable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataHddlk|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataLedl|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[6]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[7]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIooe|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIrrt|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOub|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR0|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR1|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR10|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR5|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidSrt|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.SataSalp|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHddlk|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataLedl|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[0]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[1]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[2]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[3]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[4]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[5]|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIooe|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIrrt|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOub|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR0|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR1|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR10|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR5|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidSrt|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSalp|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.TestSmbusSpdWriteDisable|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.ThermalDeviceEnable|0x3 +gStructPcdTokenSpaceGuid.PcdPchSetup.Usb3PinsTermination|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.XhciIdleL1|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.XhciOcMapEnabled|0x1 +gStructPcdTokenSpaceGuid.PcdPchSetup.XTpmLen|0x1 +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSetupEnabled|0x3 +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[0]|0x5A +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[1]|0x5A +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[0]|0x5D +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[1]|0x5D + +!if $(MAX_SOCKET) > 4 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[36]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[42]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[48]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[49]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[50]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[51]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[52]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[53]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[54]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[55]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[56]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[57]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[58]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[59]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[60]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[61]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[62]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[63]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[25]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[26]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[27]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[28]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[29]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[31]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[32]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[33]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[34]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[35]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[37]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[38]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[39]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[40]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[41]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[43]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[44]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[45]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[46]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarAttr[47]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[25]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[26]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[27]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[28]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[29]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[31]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[32]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[33]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[34]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[35]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[37]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[38]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[39]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[40]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[41]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[43]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[44]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[45]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[46]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDCfgBarSz[47]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[25]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[26]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[27]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[28]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[29]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[31]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[32]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[33]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[34]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[35]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[37]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[38]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[39]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[40]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[41]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[43]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[44]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[45]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[46]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBar2Attr[47]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[25]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[26]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[27]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[28]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[29]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[31]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[32]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[33]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[34]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[35]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[37]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[38]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[39]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[40]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[41]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[43]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[44]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[45]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[46]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz1[47]|0x19 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[25]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[26]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[27]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[28]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[29]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[31]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[32]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[33]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[34]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[35]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[37]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[38]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[39]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[40]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[41]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[43]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[44]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[45]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[46]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.VMDMemBarSz2[47]|0x14 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5KtiLinkSpeed|0x3 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5KtiLinkVnaOverride|0x= 7F +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu4P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu5P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu6P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P0ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P1ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P2ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P3ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P4ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS189|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS190|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS191|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu7P5ReservedS246|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[48]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[49]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[50]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[51]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[52]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[53]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[60]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[61]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[62]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[63]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[64]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[65]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[72]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[73]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[74]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[75]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[76]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[77]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[84]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[85]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[86]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[87]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[88]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[89]|0xFF +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[4]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[5]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[6]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.EnablePkgCCriteria= Mcddr[7]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[4]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[5]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[6]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti01pllOffEna[7]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti0In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti1In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[4]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[5]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[6]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti23pllOffEna[7]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti2In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[4]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[5]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[6]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Kti45pllOffEna[7]|= 0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc0pllOffEna[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.Mc1pllOffEna[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P0pllOffEna[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P1pllOffEna[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.P2pllOffEna[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio0In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio1In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio2In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio3In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio4In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PcieIio5In[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[4]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[5]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[6]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeIio[7]|0x20 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[4]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[5]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[6]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PkgCCriteriaLogica= lIpTypeMcddr[7]|0x10 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SapmCtlLock[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[4]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[5]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[6]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMaxTorEntry[7]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.OclaMinWay[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[4]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[5]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[6]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiHandlerSize[7]|0= x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion0[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion1[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion2[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion3[7]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[4]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[5]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[6]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.PsmiTraceBufferSizeR= egion4[7]|0x1 +!endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.p= y b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py new file mode 100644 index 0000000000..7d0716172e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py @@ -0,0 +1,111 @@ +# @ build_board.py +# Extensions for building WilsonCityRvp using build_bios.py +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE= "], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] =3D os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] =3D os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] =3D os.path.join(config["BUILD_DIR_PATH"], 'IA32') + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D0" + else: + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D1" + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd =3D os.path.join(fv_path, "BINARY.fd") + main_fd =3D os.path.join(fv_path, "MAIN.fd") + secpei_fd =3D os.path.join(fv_path, "SECPEI.fd") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.= cfg b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg new file mode 100644 index 0000000000..42bbb852d5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg @@ -0,0 +1,36 @@ +# @ build_config.cfg +# This is the WilsonCityRvp board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhitleyOpenBoardPkg +PROJECT =3D WhitleyOpenBoardPkg/WilsonCityRvp +BOARD =3D WilsonCityRvp +FLASH_MAP_FDF =3D WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC =3D WhitleyOpenBoardPkg/PlatformPkg.dsc +BOARD_PKG_PCD_DSC =3D WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D -D CPUTARGET=3DICX -D RP_PKG=3DWhitleyOpenBoardPkg -D = SILICON_PKG=3DWhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=3D6= 4 -D MAX_THREAD=3D2 -D PLATFORM_PKG=3DMinPlatformPkg +MAX_SOCKET =3D 4 +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D WhitleyFspBinPkg +FSP_PKG_NAME =3D WhitleyFspPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 15/17] Platform/Intel: Add WhitleyOpenBoardPkg to build_bios.py Date: Mon, 12 Jul 2021 17:41:29 -0700 Message-Id: <20210713004131.1782-16-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: fIxgn5pm4wv7leW8KXEereZ0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136932; bh=BojQzt1Jwilt4L2mnEhr6WSzjM3Ufhrc7shcXV6eT6E=; h=Cc:Date:From:Reply-To:Subject:To; b=AY6b6nqCYcri8GHoz/UqVbwcZ2P5onHgIelN4urrC9ktDDxCM7tcIZ/zvp4cGcH9/fk kKcrD/gnANmmAjcTye/rids9iX7d0e5jtnjbvvw1nJXXTX6glooqOTRr/mltt8h6gK8/9 zW9usZnRRWKuWeMqxQpzaGKejrtpbmCXW64= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136933923100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- Platform/Intel/build.cfg | 2 ++ Platform/Intel/build_bios.py | 28 ++++++++++++++++------------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index ede542f9f5..896ea340df 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -62,3 +62,5 @@ UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_confi= g.cfg WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg +CooperCityRvp =3D WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg +WilsonCityRvp =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index 8f855f63eb..4450b2c37f 100644 --- a/Platform/Intel/build_bios.py +++ b/Platform/Intel/build_bios.py @@ -1,4 +1,5 @@ - +#!/usr/bin/env python3 +# # @ build_bios.py # Builds BIOS using configuration files and dynamically # imported functions from board directory @@ -35,7 +36,7 @@ except ImportError: def pre_build(build_config, build_type=3D"DEBUG", silent=3DFalse, toolchai= n=3DNone): """Sets the environment variables that shall be used for the build =20 - :param build_config: The build configuration as defined in the JOSN + :param build_config: The build configuration as defined in the JSON configuration files :type build_config: Dictionary :param build_type: The build target, DEBUG, RELEASE, RELEASE_PDB, @@ -58,7 +59,7 @@ def pre_build(build_config, build_type=3D"DEBUG", silent= =3DFalse, toolchain=3DNone): # update the current config with the build config config.update(build_config) =20 - # make the config and build python 2.7 compartible + # make the config and build python 2.7 compatible config =3D py_27_fix(config) =20 # Set WORKSPACE environment. @@ -130,9 +131,9 @@ def pre_build(build_config, build_type=3D"DEBUG", silen= t=3DFalse, toolchain=3DNone): config["PACKAGES_PATH"] +=3D os.pathsep + filepath config["PACKAGES_PATH"] +=3D os.pathsep + config["WORKSPACE_DRIVERS"] config["PACKAGES_PATH"] +=3D os.pathsep + \ - os.path.join(config["WORKSPACE"], "FSP") + os.path.join(config["WORKSPACE"], config["WORKSPACE_FSP_BIN"]) config["PACKAGES_PATH"] +=3D os.pathsep + \ - os.path.join(config["WORKSPACE"], "edk2") + os.path.join(config["WORKSPACE"], config["WORKSPACE_CORE"]) config["PACKAGES_PATH"] +=3D os.pathsep + os.path.join(config["WORKSPA= CE"]) config["PACKAGES_PATH"] +=3D os.pathsep + config["WORKSPACE_PLATFORM_B= IN"] config["EDK_TOOLS_PATH"] =3D os.path.join(config["WORKSPACE"], @@ -389,7 +390,10 @@ def build(config): command.append(config["REBUILD_MODE"]) =20 if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] !=3D "": - command.append(config["EXT_BUILD_FLAGS"]) + ext_build_flags =3D config["EXT_BUILD_FLAGS"].split(" ") + ext_build_flags =3D [x.strip() for x in ext_build_flags] + ext_build_flags =3D [x for x in ext_build_flags if x !=3D ""] + command.extend(ext_build_flags) =20 if config.get('BINARY_CACHE_CMD_LINE'): command.append(config['HASH']) @@ -453,7 +457,7 @@ def post_build(config): shell =3D True command =3D ["FitGen", "-D", final_fd, temp_fd, "-NA", - "-I", config["BIOS_INFO_GUID"]] + "-I", config["BIOS_INFO_GUID"]] #@todo: Need mech= anism to add additional options to the FitGen command line =20 if os.name =3D=3D "posix": # linux shell =3D False @@ -600,7 +604,7 @@ def post_build_ex(config): =20 =20 def clean_ex(config): - """ An extension of the platform cleanning + """ An extension of the platform cleaning =20 :param config: The environment variables used in the clean process :type config: Dictionary @@ -658,7 +662,7 @@ def execute_script(command, env_variables, collect_env= =3DFalse, :type command: List:String :param env_variables: Environment variables passed to the process :type env_variables: String - :param collect_env: Enables the collection of evironment variables + :param collect_env: Enables the collection of environment variables when process execution is done :type collect_env: Boolean :param enable_std_pipe: Enables process out to be piped to @@ -705,7 +709,7 @@ def execute_script(command, env_variables, collect_env= =3DFalse, # wait for process to be done execute.wait() =20 - # if collect enviroment variables + # if collect environment variables if collect_env: # get the new environment variables std_out, env =3D get_environment_variables(std_out, env_marker) @@ -713,7 +717,7 @@ def execute_script(command, env_variables, collect_env= =3DFalse, =20 =20 def patch_config(config): - """ An extension of the platform cleanning + """ An extension of the platform cleaning =20 :param config: The environment variables used in the build process :type config: Dictionary @@ -888,7 +892,7 @@ def get_config(): =20 =20 def get_platform_config(platform_name, config_data): - """ Reads the platform specifig config file + """ Reads the platform specific config file =20 param platform_name: The name of the platform to be built :type platform_name: String --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77717): https://edk2.groups.io/g/devel/message/77717 Mute This Topic: https://groups.io/mt/84168632/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 16:20:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77720+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77720+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626136940; cv=none; d=zohomail.com; s=zohoarc; b=KMQYkh+DLsh08vKMMgIEGoDHWfCEwizvhP4CCj96ESYCbW1/NCYMfVdsSCmhsPwzSLyRbWe6rWsXVnpqUkxZFUG5NHvlMvs24QVNGfneVGg1Y2a8B1H8ELaYDnMvlD20Z+Gp8mNz0iFZgrZlUYj9aLXn1qUPDtfbx1EgTMWLdEc= ARC-Message-Signature: i=1; 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Mon, 12 Jul 2021 17:42:14 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723198" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723198" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:07 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653423050" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:06 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 16/17] Readme.md: Add WhitleyOpenBoardPkg Date: Mon, 12 Jul 2021 17:41:30 -0700 Message-Id: <20210713004131.1782-17-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: L5q4kKqVp32MZuQnxjr1vNprx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136939; bh=qH+jOdHQFir/mIctK0XKqXDKRFXs3X7y1oIy5ljvbdQ=; h=Cc:Date:From:Reply-To:Subject:To; b=LiBcYom/H57ckvMu0gv73pAjpF6uAFr83eZ+yu42bPrpBzjifTJKAdbuHXwLSzeUh+Z 3zWcxy7Tx7GKcq/j4HWd6XsnwsPGQ6DeuyGze4EgOP9OPWiEdeSZc3iAYDtd61sqaa+GX PW37GDVe5eX6iu3loCmCM0XmBf9kz+Zo7j4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136940254100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- Platform/Intel/Readme.md | 14 ++++++++++++++ Readme.md | 2 ++ 2 files changed, 16 insertions(+) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 06c5f32b1e..0052538be1 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -59,6 +59,7 @@ A UEFI firmware implementation using MinPlatformPkg is co= nstructed using the fol * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. * The `CometlakeOpenBoardPkg` contains board implementations for CometLake= systems. * The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake= systems. +* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP= and Cooper Lake systems. =20 ### **Supported Hardware** =20 @@ -78,6 +79,8 @@ A UEFI firmware implementation using MinPlatformPkg is co= nstructed using the fol | WHL-U DDR4 RVP | WhiskeyLake = | WhiskeylakeOpenBoardPkg | WhiskeylakeURvp | | CML-U LPDDR3 RVP | CometLake V1 = | CometlakeOpenBoardPkg | CometlakeURvp | | TGL-U DDR4 RVP | TigerLake = | TigerlakeOpenBoardPkg | TigerlakeURvp | +| Wilson City RVP | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | WilsonCityRvp | +| Cooper City RVP | Copper Lake = | WhitleyOpenBoardPkg | CooperCityRvp | =20 *Note: RVP =3D Reference and Validation Platform* =20 @@ -257,6 +260,14 @@ return back to the minimum platform caller. | | | build set= tings, environment variables. | | | | | |------WhiskeylakeOpenBoardPkg + | | | |------CooperCityRvp + | | | | |---build_config.cfg: CooperCit= yRvp specific build + | | | | settings = environment variables. + | | | |------WilsonCityRvp + | | | |---build_config.cfg: WilsonCit= yRvp specific build + | | | settings = environment variables. + | | | + | | |------WhitleyOpenBoardPkg | | | |------UpXtreme | | | |---build_config.cfg: UpXtreme = specific build | | | settings = environment variables. @@ -328,6 +339,9 @@ For PurleyOpenBoardPkg 1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and Integrated Graphic Device. 2. This firmware project has been also tested booting to Puppy Linux Bioni= cPup64 8.0 with AHCI mode and Integrated Graphic Device. =20 +**WhitleyOpenBoardPkg** +1. This firmware project has been tested booting to UEFI shell with headle= ss serial console + ### **Package Builds** =20 In some cases, such as BoardModulePkg, a package may provide a set of func= tionality that is included in other diff --git a/Readme.md b/Readme.md index d8cd211334..62876b4b7d 100644 --- a/Readme.md +++ b/Readme.md @@ -246,6 +246,8 @@ they will be documented with the platform. * [Simics](Platform/Intel/SimicsOpenBoardPkg) * [Whiskey Lake](Platform/Intel/WhiskeylakeOpenBoardPkg) * [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg) +* [Tiger Lake](Platform/Intel/TigerlakeOpenBoardPkg) +* [Whitley/Cedar Island](Platform/Intel/WhitleyOpenBoardPkg) =20 For more information, see the [EDK II Minimum Platform Specification](https://edk2-docs.gitbooks.io/edk-= ii-minimum-platform-specification). --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 12 Jul 2021 17:42:14 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="295723201" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="295723201" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:07 -0700 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="653423058" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.212.211.135]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 17:42:06 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Isaac Oram , Mohamed Abbas , Chasel Chiu , Michael D Kinney , Liming Gao , Eric Dong , Michael Kubacki Subject: [edk2-devel] [edk2-platforms] [PATCH V1 17/17] Maintainers.txt: Add WhitleyOpenBoardPkg and WhitleySiliconPkg Date: Mon, 12 Jul 2021 17:41:31 -0700 Message-Id: <20210713004131.1782-18-nathaniel.l.desimone@intel.com> In-Reply-To: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> References: <20210713004131.1782-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: vsqLz4lrixyICYnspV16R9Arx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626136949; bh=3dnh2jSKR6DfgYFz3CR6fHlfR4dKvWR6XS6mPpz81qw=; h=Cc:Date:From:Reply-To:Subject:To; b=AhDGx+VeRMys5ESc+vA7URX4K8xa4w58fbLoxSNb2e8fefNafDibRKe1EEqdVVATqhM dNzxGPYtvamR+MyIk/sNRq/FdFZzEvz0uZNsm8TPume1YCCGhRWzAvRPZoQFRt9ErUpXV g1Fjd6KAmGSgLttIw9/arZWBBlYr3V+oINs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626136950855100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nate DeSimone Co-authored-by: Isaac Oram Co-authored-by: Mohamed Abbas Cc: Chasel Chiu Cc: Michael D Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Liming Gao Cc: Eric Dong Cc: Michael Kubacki Acked-by: Michael D Kinney --- Maintainers.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 10a9521ec3..9b8d6aead9 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -219,6 +219,12 @@ M: Sai Chaganty M: Nate DeSimone R: Heng Luo =20 +Platform/Intel/WhitleyOpenBoardPkg +F: Platform/Intel/WhitleyOpenBoardPkg/ +M: Isaac Oram +M: Nate DeSimone +M: Chasel Chiu + Platform/Intel/SimicsOpenBoardPkg F: Platform/Intel/SimicsOpenBoardPkg/ M: Agyeman Prince @@ -279,6 +285,12 @@ M: Sai Chaganty M: Nate DeSimone R: Heng Luo =20 +Silicon/Intel/WhitleySiliconPkg +F: Silicon/Intel/WhitleySiliconPkg/ +M: Isaac Oram +M: Nate DeSimone +M: Chasel Chiu + Silicon/Intel/SimicsX58SktPkg F: Silicon/Intel/SimicsX58SktPkg/ M: Agyeman Prince --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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