From nobody Sat May 4 03:31:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77663+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77663+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1625898736; cv=none; d=zohomail.com; s=zohoarc; b=SZJ1yb3ofK2tOZS3UCFX4aBuD04hVS1WtjqVVZ54tfiGNxRzJshWq5LAzWii5dEjaQFU1hiI8H5HGgZPo7S+pdxCObU/t1CklYjid4EGYchLzbX7PQ3A9vUGz2m4H0nEKb+YHPcUywreQ7x1391dtlPbYZs+SaG6Qfwq6YDkxVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625898736; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=x7Ap8e+SpJH+w+wbSjwHKWUmFVonSt2hAk0gucpA5lI=; b=WmW+f83eIDhOI7uH7cUjJ4UauZP61AkCYzJc5Cot3S/JSU7e7Z6CJfslJXN1rZQvGQs1FioFc9w3i/qBtTOkgyqr/M5UgQgaxt+ZPg2OCYLHrfzIuVrLyVSq0sQxIN3N/IZAktOc3ycOkvHFTbqE42pW/rCsCPEEniMalRfYBKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77663+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1625898736320109.71948394688366; Fri, 9 Jul 2021 23:32:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id lMOiYY1788612x6njNhTZz0S; Fri, 09 Jul 2021 23:32:15 -0700 X-Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mx.groups.io with SMTP id smtpd.web08.21721.1625898695823857158 for ; Fri, 09 Jul 2021 23:31:35 -0700 X-Received: by mail-pl1-f172.google.com with SMTP id d1so967483plg.0 for ; Fri, 09 Jul 2021 23:31:35 -0700 (PDT) X-Gm-Message-State: ZuvNuArootiWYlb3TWlGlYsGx1787277AA= X-Google-Smtp-Source: ABdhPJzUR39T0BPB77+J6r81KkTflsUS7M9UUIrT2KCUf4r4lBflma2B7nmjwM5CEsYraVXd0qeoYA== X-Received: by 2002:a17:90a:d102:: with SMTP id l2mr41924303pju.225.1625898695183; Fri, 09 Jul 2021 23:31:35 -0700 (PDT) X-Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id 11sm8104748pfl.41.2021.07.09.23.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 23:31:34 -0700 (PDT) From: Sunil V L To: devel@edk2.groups.io Cc: sunil.vl@gmail.com, Sunil V L , Liming Gao , Bob Feng , Yuwei Chen , Pete Batard , Abner Chang , Daniel Schaefer Subject: [edk2-devel] [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation Date: Sat, 10 Jul 2021 12:01:14 +0530 Message-Id: <20210710063114.4278-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1625898735; bh=YePFnsJHl+YDtwCb3zJpoun5UGd/TEFn/+vORgnvinA=; h=Cc:Date:From:Reply-To:Subject:To; b=BJblZ93Ex7qlGoIUbs0fY8jQ+YVaLHki/m5g/V6KA8aFhUvADUkj0v9W1ZedVAiSLsR 1CVpDxJGGKIaUiefbibl/X/wyuTc24qcoDzPdVc9InjhnEAwqI7Ph0zSn+hEq+RzbqG6c gyblPEAGdDwSXLdPtK3PaSGd1kImeaYeLtc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1625898738415100001 Content-Type: text/plain; charset="utf-8" Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3459 This patch adds support for R_RISCV_PCREL_LO12_S relocation type. The logic is same as existing R_RISCV_PCREL_LO12_I relocation except the difference between load vs store instruction formats. Signed-off-by: Sunil V L Cc: Liming Gao Cc: Bob Feng Cc: Yuwei Chen Cc: Pete Batard Cc: Abner Chang Cc: Daniel Schaefer Acked-by: Abner Chang Acked-by: Liming Gao Reviewed-by: Daniel Schaefer Tested-by: Pete Batard --- BaseTools/Source/C/GenFw/Elf64Convert.c | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index 3d7e20aaff..0bb3ead228 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -557,6 +557,60 @@ WriteSectionRiscV64 ( Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); break; =20 + case R_RISCV_PCREL_LO12_S: + if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) { + int i; + Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); + + Value =3D ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5); + Value =3D (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5))); + + if(Value & (RISCV_IMM_REACH/2)) { + Value |=3D ~(RISCV_IMM_REACH-1); + } + Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex]; + + if(-2048 > (INT32)Value) { + i =3D (((INT32)Value * -1) / 4096); + Value2 -=3D i; + Value +=3D 4096 * i; + if(-2048 > (INT32)Value) { + Value2 -=3D 1; + Value +=3D 4096; + } + } + else if( 2047 < (INT32)Value) { + i =3D (Value / 4096); + Value2 +=3D i; + Value -=3D 4096 * i; + if(2047 < (INT32)Value) { + Value2 +=3D 1; + Value -=3D 4096; + } + } + + // Update the IMM of SD instruction + // + // |31 25|24 20|19 15|14 12 |11 7|6 0| + // |-------------------------------------------|-------| + // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode| + // --------------------------------------------------- + + // First Zero out current IMM + *(UINT32 *)Targ &=3D ~0xfe000f80; + + // Update with new IMM + *(UINT32 *)Targ |=3D (RV_X(Value, 5, 7) << 25); + *(UINT32 *)Targ |=3D (RV_X(Value, 0, 5) << 7); + + // Update previous instruction + *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12)); + } + mRiscVPass1Sym =3D NULL; + mRiscVPass1Targ =3D NULL; + mRiscVPass1SymSecIndex =3D 0; + break; + case R_RISCV_PCREL_LO12_I: if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) { int i; @@ -1587,6 +1641,7 @@ WriteRelocations64 ( case R_RISCV_PCREL_HI20: case R_RISCV_GOT_HI20: case R_RISCV_PCREL_LO12_I: + case R_RISCV_PCREL_LO12_S: break; =20 default: --=20 2.32.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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