From nobody Thu Dec 18 19:59:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77106+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77106+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1624656136; cv=none; d=zohomail.com; s=zohoarc; b=KAnWwT1LEWtcVZ0t5qJpnBVea26K9UHlaJmVtByQKc37n5mVMv7SxVdH7QLinXf82kXR7vSQvTxWD0Cimn8PYoxvFvk5DTIOt6OqPS0df+DaPc4Gjp67ooC/J5NaTPWslZp6GSQCry/0HNbHWE4M339w0U0I6HbsLL+aYCeTzvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1624656136; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wYGHRdPdyixzgLIiV9ZR9/esmr4rJlZ2cxkZ8zSpIvk=; b=ZLJ9xvNZbW6++tGlUiul8AT/tfWR4LP6SZUzfQyUavvh1x6/eEfmg+2ZUI70eRik/vy46dlgT6x9Ow90rjs9Ma1g1Z2mkJly8XrBL8MeEYN/IHjFaK7S+SxnAcd+zDey9578RRJJVGY47P/96Diyg7UwgIc1bfAXxfYQCRhKf10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77106+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1624656136211815.4407026984; Fri, 25 Jun 2021 14:22:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id f843YY1788612xX3QuuUrOWq; Fri, 25 Jun 2021 14:22:15 -0700 X-Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web08.386.1624656135267695522 for ; Fri, 25 Jun 2021 14:22:15 -0700 X-Received: from localhost.localdomain (unknown [167.220.2.74]) by linux.microsoft.com (Postfix) with ESMTPSA id 0B7EB20B83F8; Fri, 25 Jun 2021 14:22:15 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 0B7EB20B83F8 From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH v4 09/41] IntelSiliconPkg: Add SmmSpiFlashCommonLib Date: Fri, 25 Jun 2021 17:20:48 -0400 Message-Id: <20210625212120.235-10-mikuback@linux.microsoft.com> In-Reply-To: <20210625212120.235-1-mikuback@linux.microsoft.com> References: <20210625212120.235-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mikuback@linux.microsoft.com X-Gm-Message-State: agJA5Rj35j8qKwAYJY2XYis5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1624656135; bh=NOM9ML3NCm+ijH16rI70jGatVqi/66nTr2ivTk/tJzo=; h=Cc:Date:From:Reply-To:Subject:To; b=Qv8jN4efZb2aHKesBnqpLbUS+gorrJPWNb9yFOHvNRloSgB2/Uhs9i9085W0fZf3H4F +x2R7eGv3LfemM51ry9Any3Fum18N5OktZpmD0N4qyuA+aAdznVCjXfNKGPhQlqEyM9xR 3OcR6M/mLCBY3rtRXPVk+mGbbt3MB0rsYlM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Adds the SMM instance of SpiFlashCommonLib. The code is based on refactoring existing library instances into a consolidated version with no functional impact. Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Michael Kubacki Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty =20 --- Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashComm= onLib.c | 58 ++++++ Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.= c | 209 ++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = | 5 + Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashComm= onLib.inf | 48 +++++ 4 files changed, 320 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/Smm= SpiFlashCommonLib.c b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashComm= onLib/SmmSpiFlashCommonLib.c new file mode 100644 index 000000000000..7941b8f8720c --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlas= hCommonLib.c @@ -0,0 +1,58 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mBiosAreaBaseAddress; +extern UINTN mBiosSize; +extern UINTN mBiosOffset; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 BaseAddr; + UINT32 RegionSize; + + mBiosAreaBaseAddress =3D (UINTN)PcdGet32 (PcdBiosAreaBaseAddress); + mBiosSize =3D (UINTN)PcdGet32 (PcdBiosSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr= , &RegionSize); + mBiosOffset =3D BaseAddr; + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/Spi= FlashCommon.c b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/= SpiFlashCommon.c new file mode 100644 index 000000000000..daebaf8e5e33 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SpiFlashCo= mmon.c @@ -0,0 +1,209 @@ +/** @file + Wrap PCH_SPI_PROTOCOL to provide some library level interfaces + for module use. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// Variables for boottime and runtime usage. +// +UINTN mBiosAreaBaseAddress =3D 0; +UINTN mBiosSize =3D 0; +UINTN mBiosOffset =3D 0; + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mBiosAreaBaseAddress); + if (Address < mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset =3D Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); + if ((*NumBytes + Offset) > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mBiosAreaBaseAddress); + if (Address < mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset =3D Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); + if ((*NumBytes % SECTOR_SIZE_4KB) !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); + if ((*NumBytes + Offset) > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dsc index aeed452ed521..d4e15100bfde 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -59,6 +59,10 @@ [LibraryClasses.common.DXE_DRIVER] HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf =20 +[LibraryClasses.common.DXE_SMM_DRIVER] + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf + ##########################################################################= ######################### # # Components Section - list of the modules and components that will be pro= cessed by compilation @@ -95,6 +99,7 @@ [Components] IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf IntelSiliconPkg/Library/SpiFlashCommonLibNull/SpiFlashCommonLibNull.inf + IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf =20 [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/Smm= SpiFlashCommonLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCo= mmonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 000000000000..f6a06351ace5 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlas= hCommonLib.inf @@ -0,0 +1,48 @@ +## @file +# SMM Library instance of Spi Flash Common Library Class +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 99721728-C39D-4600-BD38-71E8238FEEF2 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + SmmServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES + +[Sources] + SmmSpiFlashCommonLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid --=20 2.28.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77106): https://edk2.groups.io/g/devel/message/77106 Mute This Topic: https://groups.io/mt/83794789/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-