From nobody Thu May 2 06:33:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77063+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77063+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1624541140; cv=none; d=zohomail.com; s=zohoarc; b=JaQXWoI5oAzZ3npICrsXGsciNtm0a6JTBzhEPBDCJsjC6nLXr8rwzFDjd427KU8fphFWQOFS6VqOr71IxYyxBRR9tvG1y6d57d2LJeJZ4PGrPquPLZ7/P3AhF1eG00k3CDPPPk6I8USkNDcPzo7IdXZGpKSKAxqlgZFbfLX0Si4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1624541140; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=FrzOw83k7ZHChClLkaUHU7IwYp8PUZD8kFRiZWWmx1U=; b=PxorYIHc6aQyZyb9kshXE/K4Zc1658ymw3t4jYm4VFFiNR5gkZ2mZ763GnhExc+Uxc50O0ifosRWEaJ+jP8NX6hn5soCLCphXFItQiDh3owTetdlbEXcdB96d9e3NZIxfJv5ZQrJG93O+Zp7uPfDPbFe0ds0X/LHvmWD/E2LA6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77063+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1624541140135731.0099254022025; Thu, 24 Jun 2021 06:25:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id z79tYY1788612xjxOW1CuOHl; Thu, 24 Jun 2021 06:25:39 -0700 X-Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web09.7488.1624541139168415638 for ; Thu, 24 Jun 2021 06:25:39 -0700 X-Received: by mail-pj1-f53.google.com with SMTP id s17-20020a17090a8811b029016e89654f93so5916473pjn.1 for ; Thu, 24 Jun 2021 06:25:39 -0700 (PDT) X-Gm-Message-State: EuntWUNDHvpHYmBImKAkhiOKx1787277AA= X-Google-Smtp-Source: ABdhPJwqfWtAzyxS0SD3eZHavzMsQxnSjmkLRVv9ZBH5gKvpYDhakSK0Db7TrykctVmc/hVp8FJAhQ== X-Received: by 2002:a17:902:8ec7:b029:119:a15f:3a1c with SMTP id x7-20020a1709028ec7b0290119a15f3a1cmr4565707plo.48.1624541138427; Thu, 24 Jun 2021 06:25:38 -0700 (PDT) X-Received: from sunil-ThinkPad-T490.dc1.ventanamicro.com ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id q125sm2989900pfb.193.2021.06.24.06.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 06:25:38 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Abner Chang , Daniel Schaefer , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt Subject: [edk2-devel] [PATCH v4] BaseTools GenFw: Add support for RISCV GOT/PLT relocations Date: Thu, 24 Jun 2021 18:55:31 +0530 Message-Id: <20210624132531.54062-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1624541139; bh=kJkK5ETgBplC3yzoSpRXeIWcykbCQh0DFJTOVSsGcqY=; h=Cc:Date:From:Reply-To:Subject:To; b=lWqGcaOBwd3BNtqboa9jeU97nFH4B394Tb1ZhJj1TkqD1uddJfsNGzFiO2WNb2APg1S zkM7+Z3LgRBGOMOxzT02a6Bokor5FG5dQ4VJW29O9XBnIBvylnclyfktMmTLaHrrIDwvc 41wEqNRNGQh+YhGTJsfEIVtaQZ9CWt42Mao= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 relocations generated by PIE enabled compiler. This also needed changes to R_RISCV_32 and R_RISCV_64 relocations as explained in https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682= 710 Changes in v4: - Fixed the typecast issue found by VS2019. Changes in v3: - Added the comments to address Liming's feedback. Changes in v2: - Addressed Daniel's comment on formatting Testing: 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. 2) Debian 10.2.0 and booted QEMU virt model. 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Daniel Schaefer Tested-by: Daniel Schaefer Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Cc: Heinrich Schuchardt Tested-by: Pete Batard --- BaseTools/Source/C/GenFw/Elf64Convert.c | 59 ++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 6 deletions(-) diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index d097db8632..f86be95fbb 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; STATIC UINT8 *mRiscVPass1Targ =3D NULL; STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL; STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0; +STATIC INT32 mRiscVPass1Offset; +STATIC INT32 mRiscVPass1GotFixup; =20 // // Initialization Function @@ -473,17 +475,18 @@ WriteSectionRiscV64 ( { UINT32 Value; UINT32 Value2; + Elf64_Addr GOTEntryRva; =20 switch (ELF_R_TYPE(Rel->r_info)) { case R_RISCV_NONE: break; =20 case R_RISCV_32: - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a= ddr + mCoffSectionsOffset[Sym->st_shndx]); + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; break; =20 case R_RISCV_64: - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections= Offset[Sym->st_shndx]; + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; break; =20 case R_RISCV_HI20: @@ -533,6 +536,18 @@ WriteSectionRiscV64 ( mRiscVPass1SymSecIndex =3D 0; break; =20 + case R_RISCV_GOT_HI20: + GOTEntryRva =3D (Sym->st_value - Rel->r_offset); + mRiscVPass1Offset =3D RV_X(GOTEntryRva, 0, 12); + Value =3D (UINT32)RV_X(GOTEntryRva, 12, 20); + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); + + mRiscVPass1Targ =3D Targ; + mRiscVPass1Sym =3D SymShdr; + mRiscVPass1SymSecIndex =3D Sym->st_shndx; + mRiscVPass1GotFixup =3D 1; + break; + case R_RISCV_PCREL_HI20: mRiscVPass1Targ =3D Targ; mRiscVPass1Sym =3D SymShdr; @@ -545,11 +560,17 @@ WriteSectionRiscV64 ( if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) { int i; Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); - if(Value & (RISCV_IMM_REACH/2)) { - Value |=3D ~(RISCV_IMM_REACH-1); + + if(mRiscVPass1GotFixup) { + Value =3D (UINT32)(mRiscVPass1Offset); + } else { + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); + if(Value & (RISCV_IMM_REACH/2)) { + Value |=3D ~(RISCV_IMM_REACH-1); + } } Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex]; + if(-2048 > (INT32)Value) { i =3D (((INT32)Value * -1) / 4096); Value2 -=3D i; @@ -569,12 +590,35 @@ WriteSectionRiscV64 ( } } =20 - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar= g, 0, 20)); + if(mRiscVPass1GotFixup) { + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20) + | (RV_X(*(UINT32*)Targ, 0, 20)); + // Convert LD instruction to ADDI + // + // |31 20|19 15|14 12|11 7|6 0| + // |-----------------------------------------| + // |imm[11:0] | rs1 | 011 | rd | 0000011 | LD + // ----------------------------------------- + + // |-----------------------------------------| + // |imm[11:0] | rs1 | 000 | rd | 0010011 | ADDI + // ----------------------------------------- + + // To convert, let's first reset bits 12-14 and 0-6 using ~0x707f + // Then modify the opcode to ADDI (0010011) + // All other fields will remain same. + + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13); + } else { + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T= arg, 0, 20)); + } *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12)); } mRiscVPass1Sym =3D NULL; mRiscVPass1Targ =3D NULL; mRiscVPass1SymSecIndex =3D 0; + mRiscVPass1Offset =3D 0; + mRiscVPass1GotFixup =3D 0; break; =20 case R_RISCV_ADD64: @@ -586,6 +630,7 @@ WriteSectionRiscV64 ( case R_RISCV_GPREL_I: case R_RISCV_GPREL_S: case R_RISCV_CALL: + case R_RISCV_CALL_PLT: case R_RISCV_RVC_BRANCH: case R_RISCV_RVC_JUMP: case R_RISCV_RELAX: @@ -1528,6 +1573,7 @@ WriteRelocations64 ( case R_RISCV_GPREL_I: case R_RISCV_GPREL_S: case R_RISCV_CALL: + case R_RISCV_CALL_PLT: case R_RISCV_RVC_BRANCH: case R_RISCV_RVC_JUMP: case R_RISCV_RELAX: @@ -1537,6 +1583,7 @@ WriteRelocations64 ( case R_RISCV_SET16: case R_RISCV_SET32: case R_RISCV_PCREL_HI20: + case R_RISCV_GOT_HI20: case R_RISCV_PCREL_LO12_I: break; =20 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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