From nobody Fri Dec 19 20:14:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+77037+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77037+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1624505601; cv=none; d=zohomail.com; s=zohoarc; b=d8Id2vaMjtQm+4t+n7D8oZ3AQ+pQcy/lVJt5zrXsHuERSY9H0czcaM8ezEA9nNNbqtMdIyfCi7/4K+wngsFc3x9D9K+UwuPWZjaBO7m0sHeOeXZLzmGdYQPbua4mwF+Bx6mCSZMIWxmvy1IJjnf4eVLfF3cxMiI1aSFHJggZ+Ck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1624505601; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=w3hE9BC2f/xvNFsrcj1DoMOvu48l2hnElcYucepbti0=; b=LBZJ+7i4RWMHdAMtuYGD6oi6vs18Is3PG+tCLR6Js5z43QRGViPCvf9KNpN7twQit2NEztepeK23rHDhji0g3JOjsi1F4FG4jer+bAEZI9Vebme8PLmhyT24tSZYToI/Kqtlb0d84EjAFkCwxK6/1L+OSzkm/WPck9GBxA5YE+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+77037+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1624505601505425.5372111847878; Wed, 23 Jun 2021 20:33:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id bsblYY1788612xyiNIQbCSNW; Wed, 23 Jun 2021 20:33:21 -0700 X-Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) by mx.groups.io with SMTP id smtpd.web12.2534.1624505600682215495 for ; Wed, 23 Jun 2021 20:33:20 -0700 X-Received: by mail-pf1-f173.google.com with SMTP id i6so4028062pfq.1 for ; Wed, 23 Jun 2021 20:33:20 -0700 (PDT) X-Gm-Message-State: e0UKKVI708GyI5V0pRgwOJH9x1787277AA= X-Google-Smtp-Source: ABdhPJxYYX+bAMOKxkqmMAKMZj4rhJAfYPnHM39dUWACISqEQfuhwy0xwQo9KLdQT2w+FpTrN2T80Q== X-Received: by 2002:a05:6a00:a1e:b029:2e2:89d8:5c87 with SMTP id p30-20020a056a000a1eb02902e289d85c87mr2946347pfh.73.1624505600116; Wed, 23 Jun 2021 20:33:20 -0700 (PDT) X-Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id u1sm555901pgh.80.2021.06.23.20.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Jun 2021 20:33:19 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Michael Kubacki Subject: [edk2-devel] [PATCH v2 2/2] MdePkg: MmConfiguration: Added definition of MM Configuration PPI Date: Wed, 23 Jun 2021 20:33:08 -0700 Message-Id: <20210624033308.1111-3-kuqin12@gmail.com> In-Reply-To: <20210624033308.1111-1-kuqin12@gmail.com> References: <20210624033308.1111-1-kuqin12@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kuqin12@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1624505601; bh=UFc5v2Ghaknu/bhtd5jDPVZdll/z5oTvLswrQU2ERt0=; h=Cc:Date:From:Reply-To:Subject:To; b=r0yxBdNd2p1Nc/t6fE3GQ7qO9pwKgcFnsK65q+uu4E73hXY+uOtfQ1nkue9uGCrmOXR 6+az9iBlp00vcmQYIhhrH5GB4HVtdpo/GsW8kxICoGN1UwbgsFsx/4nqmkwRkAw9ok999 Efn6U4SrVG9b5AXJD4J/s9Dvdta5V9Atelw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3440 MM Configuration PPI was defined in PI Specification since v1.5. This change added definition of such PPI and related GUIDs into MdePkg. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Michael Kubacki Signed-off-by: Kun Qin --- Notes: v2: - Include PiMultiPhase.h instead of PiMmCis.h [Liming] MdePkg/Include/Ppi/MmConfiguration.h | 62 ++++++++++++++++++++ MdePkg/MdePkg.dec | 3 + 2 files changed, 65 insertions(+) diff --git a/MdePkg/Include/Ppi/MmConfiguration.h b/MdePkg/Include/Ppi/MmCo= nfiguration.h new file mode 100644 index 000000000000..862a80e372f8 --- /dev/null +++ b/MdePkg/Include/Ppi/MmConfiguration.h @@ -0,0 +1,62 @@ +/** @file + EFI MM Configuration PPI as defined in PI 1.5 specification. + + This PPI is used to: + 1) report the portions of MMRAM regions which cannot be used for the MMR= AM heap. + 2) register the MM Foundation entry point with the processor code. The e= ntry + point will be invoked by the MM processor entry code. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_CONFIGURATION_PPI_H_ +#define MM_CONFIGURATION_PPI_H_ + +#include + +#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \ + { \ + 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3,= 0xa4 } \ + } + +typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI; + +/** + This function registers the MM Foundation entry point with the processor= code. This entry point will be + invoked by the MM Processor entry code as defined in PI specification. + + @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance. + @param[in] MmEntryPoint MM Foundation entry point. + + @retval EFI_SUCCESS The entry-point was successfully registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) ( + IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This, + IN EFI_MM_ENTRY_POINT MmEntryPoint + ); + +/// +/// This PPI is a PPI published by a CPU PEIM to indicate which areas with= in MMRAM are reserved for use by +/// the CPU for any purpose, such as stack, save state or MM entry point. = If a platform chooses to let a CPU +/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM. +/// +/// The MmramReservedRegions points to an array of one or more EFI_MM_RESE= RVED_MMRAM_REGION structures, with +/// the last structure having the MmramReservedSize set to 0. An empty arr= ay would contain only the last +/// structure. +/// +/// The RegisterMmEntry() function allows the MM IPL PEIM to register the = MM Foundation entry point with the +/// MM entry vector code. +/// +struct _EFI_PEI_MM_CONFIGURATION_PPI { + EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions; + EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry; +}; + +extern EFI_GUID gEfiPeiMmConfigurationPpi; + +#endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index b49f88d8e18f..c5319fdd71ca 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -983,6 +983,9 @@ [Ppis] ## Include/Ppi/MmControl.h gEfiPeiMmControlPpiGuid =3D { 0x61c68702, 0x4d7e, 0x4f43, { 0x8= d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} =20 + ## Include/Ppi/MmConfiguration.h + gEfiPeiMmConfigurationPpi =3D { 0xc109319, 0xc149, 0x450e, { 0xa3= , 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } } + # # PPIs defined in PI 1.7. # --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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