From nobody Mon Feb 9 16:34:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+76294+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+76294+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1623288829; cv=none; d=zohomail.com; s=zohoarc; b=X+fT5ZSDCeKqiWaPYBRaRgK/nFZO+2SQIUCjVeujVnXaInw9xZD/nnGz2n6nxq7SrEmIxYybMlzdRT6exAHDNmJlF5zENc7kL3sRJqL9T5agexUGChkD2eI6MfuIg09SSj+SNJAj5pNSH46K5AV3NtLLYho9KMElFI6dSdr5y5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623288829; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6WCYcqufjVQdqtK/Uzwl4Evmo3qEQ+kSJxh67THEYMk=; b=ahbBedpRwuqzrjl9fZ6qNDKKSvt/8vOoaoR3O3T4wJ/jzqHdf9ths+5fupX5AvjUJCoqqyGAwoW8tX4+5UEWgyh+gv8umEuSs5qF8u7B4zq6o09Y3yvkNBUau0M3mG49tsfUfn67EwLMXwdyNTqOqy5/JzU99hSIWwbPUM/GfH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+76294+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1623288829778285.6975693653402; Wed, 9 Jun 2021 18:33:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jjhxYY1788612xQxomqLXJ7a; Wed, 09 Jun 2021 18:33:49 -0700 X-Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web11.4374.1623288826156455282 for ; Wed, 09 Jun 2021 18:33:48 -0700 IronPort-SDR: Jmn3/7x0YwG4kSHxrSe4ut7RRJHThvGqfWzKkVQuq44hVCG+68VPVKA9iqz6fDBkdubPgzPF03 MnzmwCZSZXPQ== X-IronPort-AV: E=McAfee;i="6200,9189,10010"; a="266359691" X-IronPort-AV: E=Sophos;i="5.83,262,1616482800"; d="scan'208";a="266359691" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2021 18:33:48 -0700 IronPort-SDR: X6uivXCUAyd8573fe13yqUGh0Qsuv4pdvZg25J1CAa9f49qoomrqE+kFzduJjeMVlPbT5SyzmM aQ2fLroB0sjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,262,1616482800"; d="scan'208";a="402630970" X-Received: from fieedk002.ccr.corp.intel.com ([10.239.158.144]) by orsmga003.jf.intel.com with ESMTP; 09 Jun 2021 18:33:47 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Jian J Wang , Hao A Wu Subject: [edk2-devel] [Patch V4 2/9] MdeModulePkg: Add new structure for the PCI Root Bridge Info Hob Date: Thu, 10 Jun 2021 09:33:11 +0800 Message-Id: <20210610013318.1885-3-zhiguang.liu@intel.com> In-Reply-To: <20210610013318.1885-1-zhiguang.liu@intel.com> References: <20210610013318.1885-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: 2AFcC9HLOBCoHyDrnNaTkH0Hx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1623288829; bh=7tfiYUqQG5vh5gqI25qgn2itjYjvnZE2B3UCyl3tleo=; h=Cc:Date:From:Reply-To:Subject:To; b=H79nPLlM6EJfK4FCQV4hE/7KbgM9kyz9WI2TKHZSFCI+M+fkA+mLL/A1CIzAD1eiKon 5gHF7K2a12qfScsBsnufDKY5quX/Kw5/RDRbhFQmYto0vMi1P8Hd7j+GVm1RprRcp+N8h XPseqHmTroKEkyT23FrfU9UIl2v7INOX318= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Michael D Kinney Cc: Liming Gao Cc: Jian J Wang Cc: Hao A Wu Reviewed-by: Hao A Wu Signed-off-by: Zhiguang Liu --- MdeModulePkg/Include/UniversalPayload/PciRootBridges.h | 91 ++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ MdeModulePkg/MdeModulePkg.dec | 6 ++++++ 2 files changed, 97 insertions(+) diff --git a/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h b/MdeMo= dulePkg/Include/UniversalPayload/PciRootBridges.h new file mode 100644 index 0000000000..ea5b87480e --- /dev/null +++ b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h @@ -0,0 +1,91 @@ +/** @file + This file defines the structure for the PCI Root Bridges. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Universal Payload Specification 0.75 (https://universalpayload.githu= b.io/documentation/) +**/ + +#ifndef __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__ +#define __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__ + +#include + +#pragma pack(1) + +// +// (Base > Limit) indicates an aperture is not available. +// +typedef struct { + // + // Base and Limit are the device address instead of host address when + // Translation is not zero + // + UINT64 Base; + UINT64 Limit; + // + // According to UEFI 2.7, Device Address =3D Host Address + Translation, + // so Translation =3D Device Address - Host Address. + // On platforms where Translation is not zero, the subtraction is probab= ly to + // be performed with UINT64 wrap-around semantics, for we may translate = an + // above-4G host address into a below-4G device address for legacy PCIe = device + // compatibility. + // + // NOTE: The alignment of Translation is required to be larger than any = BAR + // alignment in the same root bridge, so that the same alignment can be + // applied to both device address and host address, which simplifies the + // situation and makes the current resource allocation code in generic P= CI + // host bridge driver still work. + // + UINT64 Translation; +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE; + +/// +/// Payload PCI Root Bridge Information HOB +/// +typedef struct { + UINT32 Segment; ///< S= egment number. + UINT64 Supports; ///< S= upported attributes. + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes() + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + UINT64 Attributes; ///< I= nitial attributes. + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes() + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + BOOLEAN DmaAbove4G; ///< D= MA above 4GB memory. + ///< S= et to TRUE when root bridge supports DMA above 4GB memory. + BOOLEAN NoExtendedConfigSpace; ///< W= hen FALSE, the root bridge supports + ///< E= xtended (4096-byte) Configuration Space. + ///< W= hen TRUE, the root bridge supports + ///< 2= 56-byte Configuration Space only. + UINT64 AllocationAttributes; ///< A= llocation attributes. + ///< R= efer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and + ///< E= FI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes() + ///< i= n EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< B= us aperture which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< I= O aperture which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< M= MIO aperture below 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< M= MIO aperture above 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< P= refetchable MMIO aperture below 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< P= refetchable MMIO aperture above 4GB which can be used by the root bridge. + UINT32 HID; ///< P= nP hardware ID of the root bridge. This value must match the corresponding + ///< _= HID in the ACPI name space. + UINT32 UID; ///< U= nique ID that is required by ACPI if two devices have the same _HID. + ///< T= his value must also match the corresponding _UID/_HID pair in the ACPI name= space. +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE; + +typedef struct { + UNIVERSAL_PAYLOAD_GENERIC_HEADER Header; + BOOLEAN ResourceAssigned; + UINT8 Count; + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0]; +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES; + +#pragma pack() + +#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1 + +extern GUID gUniversalPayloadPciRootBridgeInfoGuid; + +#endif // __UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H__ diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 8d38383915..5cee4e159a 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -404,6 +404,12 @@ ## Include/Guid/MigratedFvInfo.h gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4,= 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } } =20 + # + # GUID defined in UniversalPayload + # + ## Include/UniversalPayload/PciRootBridges.h + gUniversalPayloadPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e,= { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }} + [Ppis] ## Include/Ppi/AtaController.h gPeiAtaControllerPpiGuid =3D { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0,= 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }} --=20 2.30.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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